--------------------GAME----------------------

Library ieee;
Use ieee.std_logic_1164.all;

------------------------------------------------------------------

Entity lab1 is
Port

(
clk: in std_logic;
D: in std_logic_vector(0 to 7);
Q: out std_logic_vector(0 to 7)
);

End Entity;

-----------------------------------------------------------------

Architecture behave of lab1 is

Signal A: std_logic_vector(2 downto 0);
Signal b: std_logic_vector(6 downto0);
component D_Flipfop
Port

(
clk,D: in std_logic;
Q: out std_logic

);

End component;
component My_xor is
Port(
I1,I2:in std_logic;
O: out std_logic);
End component;
Begin
copy1: D_Flipfop port map(clk=>clk,D=>A(0),Q=>B(0));
copy2: D_Flipfop port map(clk=>clk, D=>B(0),Q=>B(1));
copy3: D_Flipfop port map(clk=>clk, D=>B(1),Q=>B(2));
copy4: D_Flipfop port map(clk=>clk, D=>B(2),Q=>B(3));
copy5: D_Flipfop port map(clk=>clk, D=>B(3),Q=>B(4));
copy6: D_Flipfop port map(clk=>clk, D=>B(4),Q=>B(5));
copy7: D_Flipfop port map(clk=>clk, D=>B(5),Q=>B(6));
copy8: D_Flipfop port map(clk=>clk, D=>B(6), Q=>A(3));
copy1: My_xor port map(I1=>A(1), I2=>B(1),O=>A(0));
copy2: My_xor port map(I1=>A(2), I2=>B(2),O=>A(1));
copy3: My_xor port map(I1=>A(3), I2=>B(3),O=>A(2));
End Behave;

---------------------------End------------------------------------

--------------------Master-slave D flip-flop----------------------

Library ieee;
Use ieee.std_logic_1164.all;

------------------------------------------------------------------

Entity D_Flipfop is
Port( clk,D: in std_logic;
Q: out std_logic);
End Entity;

-----------------------------------------------------------------

Architecture Struct of D_Flipfop is

Signal A,Qm,Qs: std_logic;
ATTRIBUTE keep : boolean;
ATTRIBUTE keep of A,Qm,Qs : SIGNAL IS true;
component gated_D_latch

Port( clk,D: in std_logic;

Q: out std_logic);
End component;
component my_not is
Port( clk:in std_logic;
F: out std_logic);
End component;
Begin
copy1: gated_D_latch port map(A,D,Qm);
copy2: gated_D_latch port map(clk,Qm,Qs);
copy3: My_not port map(clk,A);
Q<=Qs;
End Struct;

---------------------------End------------------------------------

-------------------My_NOT--------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--------------------------------------------------------------

ENTITY My_not IS
PORT ( clk : IN STD_LOGIC;

F : OUT STD_LOGIC);
END entity;

Architecture behave of My_not is

Begin
F <='0' when clk='1' else '1';
End behave;

-------------------Gated D Latch------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--------------------------------------------------------------

ENTITY gated_D_latch IS
PORT ( Clk, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END entity;

-------------------------------------------------------------

ARCHITECTURE Structural OF gated_D_latch IS

SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC ;
ATTRIBUTE keep : boolean;

ATTRIBUTE keep of R_g, S_g, Qa, Qb : SIGNAL IS true;

BEGIN
R_g <= not(D) AND Clk;
S_g <= D AND Clk;
Qa <= NOT (R_g OR Qb);
Qb <= NOT (S_g OR Qa);
Q <= Qa;
END Structural;

----------------------------End------------------------------------------------My_xor--------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

--------------------------------------------------------------

ENTITY My_xor IS
PORT (
I1,I2 : IN STD_LOGIC;
O : OUT STD_LOGIC
);
END entity;

Architecture behave of My_xor is

Begin
F <='0' when ( (I1='1')&(I2='1') ) else '1';
End behave;