CHNG 1: CU TO VI X L 89V51RB2

CHNG 1: CU TO VI X L 89V51RB2
1.1. Tm tt phn cng MCS-51 l h IC vi iu khin do hng INTEL sn xut. Cc IC tiu biu cho h l 8031, 8051, 8951 Nhng c im chnh v nguyn tc hot ng ca cc b vi iu khin ny khc nhau khng nhiu. Khi s dng thnh tho mt vi iu khin th ta c th nhanh chng vn dng kinh nghim lm quen v lm ch cc ng dng ca b vi iu khin khc. V vy c nhng hiu bit c th v cc b vi iu khin cng nh phc v cho ti ny ta bt u tm hiu mt b vi iu khin thng dng nht, l h MCS-51 1.2. S khi, s chn, chc nng cc chn: 1.2.1 S khi:

1.2.2. S chn:

CHNG 1: CU TO VI X L 89V51RB2

1.2.3.Chc nng cc chn: 89V51RB2 c 40 chn trong 32 chn c cng dng xut/ nhp. Trong 32 chn c 24 chn c tc dng kp (ngha l 1 chn c 2 chc nng), mi mt ng c th hot ng xut/ nhp, hot ng nh mt ng iu khin hoc hot ng nh mt ng a ch/ d liu ca bus a ch/ d liu a hp. 1.2.4. Cc port:

Port 0:
- Port 0 (P0.0 P0.7) c s chn t 32 39. - Port 0 c chc nng xut nhp d liu (P0.0 P0.7) trong cc thit k c nh khng s dng b nh ngoi. - Port 0 c chc nng l bus a ch byte thp v bus d liu a hp (AD0 AD7) trong cc thit k c ln c s dng b nh ngoi.

Port 1:
- Port 1 (P1.0 P1.7) c s chn t 1 8. - Port 1 l port xut nhp d liu (P1.0 P1.7) khi s dng hoc khng s dng b nh ngoi.

Port 2:
- Port 2 (P2.0 P2.7) c s chn t 21 28. - Port 2 c chc nng l port xut nhp d liu (P2.0 P2.7) khi khng s dng b nh ngoi. - Port 2 c chc nng l bus a ch byte cao (A8 - A15) khi s dng b nh ngoi.

Port 3:
- Port 3 (P3.0 P3.7) c s chn t 10 17. - Port 3 c chc nng xut nhp d liu (P3.0 P3.7) khi khng s dng b nh ngoi hoc cc chc nng c bit. - Port 3 c chc nng l cc tn hiu iu khin khi s dng b nh ngoi hoc cc chc nng c bit. - Chc nng ca cc chn port 3: Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 Tn RxD TxD \INT0 \INT1 T0 T1 \WR a ch bit B0H B1H B2H B3H B4H B5H B6H Chc nng .Chn nhn d liu ca port ni tip .Chn pht d liu ca port ni tip .Ng vo ngt ngoi 0 .Ng vo ngt ngoi 1 .Ng vo ca b nh thi/ m 0 .Ng vo ca b nh thi/ m 1 .iu khin ghi vo RAM ngoi

CHNG 1: CU TO VI X L 89V51RB2

P3.7

\RD

B7H

.iu khin c t RAM ngoi

Bng tm tt chc nng cc chn ca Port 3 1.2.5. Cc chn tn hiu iu khin.

Chn PSEN:
- PSEN (Program Store Enable): cho php b nh chng trnh, chn s 29. - Chn PSEN\ c chc nng l tn hiu cho php truy xut (c) b nh chng trnh (ROM) ngoi hoc l tn hiu truy xut, tch cc mc thp. - PSEN mc thp trong thi gian CPU tm - np lnh t ROM ngoi. Khi CPU s dng ROM trong, PSEN s mc cao. - Khi s dng b nh chng trnh bn ngoi, chn PSEN\ thng c ni vi chn OE\ ca ROM ngoi cho php CPU c m lnh t ROM ngoi.

Chn ALE:
- ALE (Address Latch Enable): cho php cht a ch, chn s 30. - Chn ALE c chc nng l tn hiu cho php cht a ch thc hin vic gii a hp cho bus a ch byte thp v bus d liu a hp (AD0 AD7). Ngoi ra chn ALE cn l tn hiu xut, tch cc mc cao. - Cc xung tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chp v c th c dng lm tn hiu clock cho cc phn khc ca h thng. Chn ALE c dng lm ng vo xung lp trnh (PGM\).

Chn EA\:
- EA ( External Access): truy xut ngoi, chn s 31. - Tn hiu vo EA\ thng c mc ln mc 1 hoc mc 0. Nu mc 1, 89V51RB2 thi hnh chng trnh t ROM ni. Nu mc 0, 89V51RB2 thi hnh chng trnh t ROM ngoi. - Khi lp trnh cho ROM trong chip th chn EA ng vai tr l ng vo ca in p lp trnh (Vpp = 12V 12,5V cho 89V51RB2).

Chn RST:
- RST (Reset): thit lp li, chn s 9. - Khi ng vo RST a ln cao t nht 2 chu k my, 89V51RB2 thit lp li trng thi ban u. Khi ng vo RST mc thp IC hot ng bnh thung.

Chn XTAL1, XTAL2:

- XTAL (Crystal): tinh th thch anh, chn s 18 19.
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CHNG 1: CU TO VI X L 89V51RB2

- XTAL1: ng vo mch to xung clock trong chip. - XTAL2: ng ra mch to xung clock trong chip. - B dao ng c tch hp bn trong 89V51RB2, khi s dng 89V51RB2 ngi thit k ch cn ni thm thch anh (tn s thch anh thng s dng l 12MHZ) v t.

Chn Vcc, GND:

- Vcc: chn s 40, cung cp ngun in cho chip hot ng. Vcc = 4,5 5,5V. - GND: chn s 20. GND = 0V.
1.3 T chc b nh.

PSEN\ FFFFH FFFH B nh chng trnh (m) 000H B nh trong chip 0000H B nh chng trnh (m)

WR\ RD\

SFR 80H 7FH 00H

B nh d liu

B nh ngoi chip

Hnh: Tm tt cc vng nh ca 89V51RB2

CHNG 1: CU TO VI X L 89V51RB2

Bng tm tt b nh d liu trn chip 89V51

( Special Function Register: Thanh ghi chc nng c bit )

1.3.1. B nh trong: B nh trong 89V51RB2 bao gm ROM v RAM. RAM trong 89V51RB2 bao gm nhiu thnh phn: RAM a chc nng, RAM nh a ch bit v cc dy thanh ghi. 1.3.1.1. B nh ROM ( B nh chng trnh): B nh chng trnh dng lu tr chng trnh iu khin cho chip hot ng. 1.3.1.2. B nh RAM (B nh d liu):

CHNG 1: CU TO VI X L 89V51RB2

B nh d liu dng lu tr cc d liu v tham s. 1.3.1.3. RAM a chc nng: - Trn hnh v cho thy 80 byte RAM a chc nng chim a ch t 30H n 7FH. - Mi a ch trong vng RAM a chc nng u c th truy xut t do dng kiu nh a ch trc tip hoc gin tip. 1.3.1.4. RAM nh a ch bit: - RAM nh a ch bit gm 128 bit c nh a ch cha cc byte c a ch t 20H n 2FH. - RAM nh a ch bit c 3 kiu truy xut d liu: trc tip, gin tip hoc theo tng bit. 1.3.1.5. Cc dy thanh ghi: - 32 v tr thp ca b nh ni cha cc dy thanh ghi. Cc lnh ca 89V51RB2 h tr 8 thanh ghi t R0 R7 thuc dy 0 v theo mc nh sau khi Reset h thng cc thanh ghi ny cc a ch t 00H n 07H. - Cc lnh dng cc thanh ghi R0 n R7 s ngn hn v nhanh hn so vi cc lnh c chc nng tng ng dng kiu a ch trc tip. Cc d liu c dng thng xuyn nn dng mt trong cc thanh ghi ny. - Do c 4 dy thanh ghi nn ti mt thi im ch c mt dy thanh ghi tch cc. Dy thanh ghi tch cc c th c thay i bng cch thay i bit chn dy trong t trng thi chng trnh PSW. 1.3.1.6. Cc thanh ghi chc nng c bit: - Cc thanh ghi ni ca hu ht cc b vi x l u c truy xut r rng bi mt tp lnh. - Cc thanh ghi ni ca 89V51RB2 c cu hnh thnh mt phn ca RAM trn chip, v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh cc thanh ghi t R0 n R7, ta c 21 thanh ghi chc nng c bit (SFR: Special Function Register) chim phn trn ca RAM ni t a ch 80H n FFH.

CHNG 1: CU TO VI X L 89V51RB2

- Ngoi tr thanh ghi A c th c truy xut r rng cn li hu ht cc thanh ghi chc nng c bit c truy xut bng kiu nh a ch trc tip. Thanh ghi t PSW ( Program Status Word ): Bit PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 K hiu CY AC F0 RS1 RS0 a ch D7H D6H D5H D4H D3H M t bit C nh C nh ph C 0 (Chn dy thanh ghi (bit 1 :(Chn dy thanh ghi (bit 0 dy 0: a ch t 00H n 07H = 00 dy 1: a ch t 08H n 0FH = 01 dy 2: a ch t 10H n 17H = 10 dy 2: a ch t 18H n 1FH = 11 PSW.2 PSW.1 PSW.0 OV P D2H D1H D0H Thanh ghi PSW Thanh ghi A: - Thanh ghi A l thanh ghi tch ly c cng dng cha d liu ca cc php ton m vi iu khin x l. V d lnh MUL AB s nhn nhng gi tr khng du 8 bit c trong hai thanh ghi A v B, ri tr v kt qu 16 bit trong A (byte thp) v B (byte cao). Lnh DIV AB s ly A chia B, kt qu s nguyn t vo A, s d t vo B. - Thanh ghi A c a ch byte l E0H v a ch bit t E0H E7H. Thanh ghi B: - Thanh ghi B a ch F0H c dng cng vi thanh ghi A cho cc php ton nhn chia. - Thanh ghi B c th c dng nh mt thanh ghi m trung gian a mc ch. N l nhng bit nh v thng qua nhng a ch t F0H F7H.
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C trn D tr C kim tra chn l

CHNG 1: CU TO VI X L 89V51RB2

Thanh ghi SP: - Con tr ngn xp (SP: Stack Pointer) l mt thanh ghi 8 bit a ch byte l 81H, dng lu tr tm thi cc d liu. y l thanh ghi khng nh a ch bit. Thanh ghi ny cha a ch ca byte d liu hin hnh trn nh ngn xp. Cc lnh trn ngn xp bao gm lnh ct d liu vo ngn xp (PUSH) v lnh ly d liu ra khi ngn xp (POP). Lnh ct d liu vo ngn xp s lm tng SP trc khi ghi d liu v lnh ly ra khi ngn xp s lm gim SP. i vi chip 8051 th vng nh c dng lm ngn xp c lu gi trong RAM ni. - s dng ngn xp th ta phi khi ng thanh ghi SP (ngha l np gi tr cho thanh ghi SP) => vng nh ca ngn xp c a ch bt u l (SP) +1 v a ch kt thc l 7FH. - Sau khi reset IC, SP s mang gi tr mc nh l 07H v d liu u tin s c ct vo nh ngn xp c a ch 08H. Nu phn mm ng dng khng khi ng SP mt gi tr mi th dy thanh ghi 1, c th c 2 v 3 s khng dng c v vng RAM ny c dng lm ngn xp. Ngn xp c truy xut trc tip bng cc lnh PUSH v POP lu tr tm thi v ly li d liu, hoc truy xut ngm bng lnh gi chng trnh con (ACALL, LCALL) v cc lnh tr v (RET, RETI) lu tr gi tr ca b m chng trnh khi bt u thc hin chng trnh con v ly li khi kt thc chng trnh con. Thanh ghi DPTR: - Con tr d liu (DPTR: Data Pointer Register) l thanh ghi 16 bit cha a ch ca nh cn truy xut thuc ROM trong hoc ngoi v RAM ngoi - Thanh ghi DPTR c a ch byte l 82H (DPL: byte thp) v 83H (DPH: byte cao). Thanh ghi ny khng nh a ch bit. Thanh ghi port xut nhp: - Cc Port ca 89V51RB2 bao gm Port 0 a ch 80H, Port 1 a ch 90H, Port 2 a ch A0H, Port 3 a ch B0H. Tt c cc Port ny u c th truy xut tng bit nn rt thun tin trong kh nng giao tip. Thanh ghi port ni tip: - 89V51RB2 cha mt port ni tip cho vic trao i thng tin vi cc thit b ni tip nh my tnh hoc giao tip ni tip vi cc IC khc. Mt thanh
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CHNG 1: CU TO VI X L 89V51RB2

ghi m d liu ni tip (SBUF: Serial Buffer) a ch 99H s gi c d liu truyn v d liu nhn. Khi truyn d liu th ghi ln SBUF, khi nhn d liu th c SBUF. Ngoi ra cn c thanh ghi iu khin port ni tip (SCON: Serial Control) c a ch byte 98H dng bo trng thi v iu khin qu trnh hot ng ca port ni tip. Thanh ghi nh thi: - 89V51RB2 c cha hai b nh thi/ b m 16 bit c dng cho vic nh thi hoc m s kin. Timer 0 a ch 8AH (TL0: byte thp) v 8CH (TH0: byte cao). Timer 1 a ch 8BH (TL1: byte thp) v 8DH (TH1: byte cao). Vic khi ng Timer c SET bi Timer Mode (TMOD) a ch 89H v thanh ghi iu khin Timer (TCON) a ch 88H. Ch c TCON c a ch ho tng bit. Thanh ghi ngt: - Thanh ghi IE (Interrupt Enable: cho php ngt) c a ch byte A8H v a ch bit A8H AFH c cng dng cho php hoc khng cho php cc ngt hot ng (c th tng ngt ring r hoc tt c cc ngt) - Thanh ghi IP (Interrup Priority: u tin ngt) c a ch byte B8H v a ch bit B8H BCH c cng dng thit lp mc u tin cho cc ngt (u tin thp hoc u tin cao) Thanh ghi iu khin ngun: - Thanh ghi PCON (Power Control: iu khin ngun) khng c bit nh v. N a ch 87H cha nhiu bit iu khin. Thanh ghi PCON c tm tt nh sau: Bit 7 (SMOD) => cho php tng gp i tc truyn d liu ni tip (tc baud) khi SMOD = 1. Bit 6, 5, 4 => khng c a ch. Bit 3, 2 (GF1, GF0) => cho php ngi lp trnh dng vi mc ch ring. Bit 1 (PD) => dng quy nh ch ngun gim. Bit 0 (IDL) => dng quy nh ch ngh.

CHNG 1: CU TO VI X L 89V51RB2

Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC h MCS 51 nhng ch c thi hnh trong s bin dch ca CMOD. 1.3.2. B nh ngoi: - 89V51RB2 c kh nng m rng khng gian b nh chng trnh ln n 64KB v khng gian b nh d liu ln n 64KB. - Khi dng b nh ngoi, Port 0 khng cn chc nng I/O na m l bus a ch byte thp v bus d liu a hp (AD0 AD7). Port 2 l bus a ch byte cao (A8 - A15). Port 3 l cc tn hiu iu khin (WR\, RD\ Kt ni v truy xut b nh d liu ngoi:

8951 AD0 AD7 EA\ AL E A8 A15 WR\ RD\

RAM 64KB D0 D7 74373

D Q G

A0 A7 CS\
A8 A15

WR\ OE\
S kt ni v truy xut b nh d liu ngoi

B nh d liu ngoi l b nh c/ ghi c cho php bi cc tn hiu RD\ v WR\ cc chn P3.7 v P3.6. Lnh dng truy xut b nh d liu ngoi l MOVX, s dng con tr d liu 16 bit DPTR hoc R0, R1 lm thanh ghi cha a ch. Gii m a ch: Nu trng hp ROM v RAM c kt hp t nhiu b nh c dung lng nh hoc c hai giao tip vi chip 89V51 th cn phi gii m a ch. Vic gii m ny cn cho hu ht cc b vi x l. V d nu cc ROM v RAM c dung lng 8KB c s dng th tm a ch m chip 89V51 qun l (0000H FFFFH) cn phi c gii m thnh
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CHNG 1: CU TO VI X L 89V51RB2

tng on 8KB chip c th chn tng IC nh trn cc gii hn 8KB tng ng: IC1: 0000H 1FFFH, IC2: 2000H 3FFFH, IC chuyn dng cho vic to tn hiu gii m l 74HC138, cc ng ra ca IC ny ln lt ni vi cc ng vo chn chip CS\ tng ng ca cc IC nh cho cc IC nh hot ng (ti mt thi im ch c mt IC nh c php hot ng). Cn lu l do cc ng cho php IC nh hot ng ring l cho tng loi (PSEN\ cho b nh chng trnh, RD\ v WR\ cho b nh d liu) nn 89V51 c th qun l khng gian nh ln n 64KB cho ROM v 64KB cho RAM. Cc khng gian nh chng trnh v d liu gi nhau: V b nh chng trnh l b nh ch c, mt tnh hung kh x c pht sinh trong qu trnh pht trin phn mm cho 8951. Lm th no phn mm c vit cho mt h thng ch g ri nu phn mm ch c th c thc thi t khng gian b nh chng trnh ch c. Gii php tng qut l cho cc b nh chng trnh v d liu ngoi gi ln nhau. V PSEN\ c dng c chng trnh v RD\ c dng c b nh d liu, mt RAM c th chim khng gian nh chng trnh v d liu bng cch ni chn OE\ ti ng ra cng AND c cc ng vo l PSEN\ v RD\. 1.3.3. Hot ng Reset: 89V51RB2 c ng vo Reset tc ng mc cao trong khong thi gian 2 chu k xung my, sau xung mc thp 89V51RB2 bt u lm vic. RST c th kch bng tay bi mt nt nhn thng h hoc RST khi cp ngun, s mch Reset tng hp nh sau:

Trng thi ca cc thanh ghi sau khi Reset h thng: B m chng trnh (PC) Thanh ghi A
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0000H 00H

CHNG 1: CU TO VI X L 89V51RB2

Thanh ghi B Thanh ghi PSW Thanh ghi SP Thanh ghi DPTR Port 0 Port3 Thanh ghi IP Thanh ghi IE Cc thanh ghi nh thi Thanh ghi SCON Thanh ghi SBUF Thanh ghi PCON (HMOS) Thanh ghi PCON (CMOS) 1.3.4. Cc lnh s hc ADD A, <src,byte> SUBB A, <src, byte> INC <byte> DEC <byte> MUL AB DIV AB 1.3.5. Cc lnh logic

00H 00H 07H 0000H FFH xxx00000B 0xx00000B 00H 00H 00H 0xxxxxxxB 0xxx0000B

: (A) LOW [(A) x (B)]; c nh hng c OV : (B) HIGH [(A) x (B)]; c Carry c xo : (A) Integer result of [(A) / (B)]; c OV : (B) Remainder of [(A) / (B)]; c Carry xo

Tt c cc lnh logic s dng thanh ghi A nh l mt trong nhng ton hng thc thi mt chu k my, ngoi A mt 2 chu k my. Nhng hot ng logic c th c thc hin trn bt k byte no trong v tr nh d liu ni m khng thng qua thanh ghi A. Cc hot ng logic c tm tt nh sau: ANL <dest-byte>,<src-byte> ORL <dest-byte><src-byte> XRL <dest-byte>,<src-byte> RL A : Quay thanh ghi A qua tri 1 bit

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CHNG 1: CU TO VI X L 89V51RB2

RLC A RR JC JNC JB JNB JBC ACALL LCAL RET RETI AJMP LJMP SJMP CJNE DJNE DJNZ A Rel Rel bit,rel bit,rel bit, rel 1.3.6. Cc lnh r nhnh

: Quay vng thanh ghi A qua tri 1 bit c c Carry : Quay thanh A ghi sang phi 1 bit : Nhy n Rel nu c carry C =1. : Nhy n Rel nu c Carry C =0 : Nhy n Rel nu (bit) =1 : Nhy n rel nu (bit) =0 : Nhy n rel nu (bit) =1 v xo bit. : Lnh gi tuyt i trong Page 2K :Lnh gi di chng trnh con trong 64 K

addr 11 Addr 16

: Kt thc chng trnh con tr v chng trnh chnh. : Kt thc th tc phc v ngt quay v chng trnh chnh addr11: Nhy tuyt i khng iu kin trong 2 K addr16 rel Rn,rel direct, rel : Nhy di khng iu kin trong 64 K : Nhy ngn khng iu kin trong (-128 127) byte : Gim Rn v nhy nu Rn 0 : Gim v nhy nu direct 0

A, direct, rel : so snh v nhy n A nu A direct

1.3.7. Cc lnh dch chuyn d liu Cc lnh dch chuyn d liu trong nhng vng nh ni thc thi 1 hoc 2 chu k my. Mu lnh MOV <destination>, <source> cho php di chuyn d liu bt k 2 vng nh no ca RAM ni hoc cc vng nh ca cc thanh ghi chc nng c bit m khng thng qua thanh ghi A. Vng Stack ca 8051 ch cha 128 byte RAM ni, nu con tr Stack SP c tng qu a ch 7FH th cc byte c PUSH vo s mt i vo cc byte POP ra th khng bit r. Cc lnh dch chuyn b nh ni v b nh ngoi dng s nh v gin tip. a ch gin tip c th dng a ch 1 byte (@ Ri) hoc a ch 2 byte (@ DPTR). Tt c cc lnh dch chuyn hot ng trn ton b nh ngoi thc thi trong 2 chu k my v dng thanh ghi A lm ton hng DESTINATION. Vic c v ghi RAM ngoi (RD v WR) ch tch cc trong sut qu trnh thc thi ca lnh MOVX, cn bnh thng RD v WR khng tch cc (mc 1).

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CHNG 1: CU TO VI X L 89V51RB2

1.3.8.Cc lnh lun l CLR C CLR BIT SET C SET BIT CPL C CPL BIT : Xo c Carry xung 0. C nh hng c Carry. : Xo bit xung 0. Khng nh hng c Carry. : Set c Carry ln 1. C nh hng c Carry. : Set bit ln 1. Khng nh hng c Carry. : o bit c Carry. C nh hng c Carry. : o bit. Khng nh hng c Carry.

ANL C, BIT : C nh hng c Carry. ANL C, BIT : Khng nh hng c Carry. ORL C, BIT : Tc ng c Carry. ORL C, : Tc ng c Carry. MOV C, BIT : C Carry b tc ng. MOV BIT, C : Khng nh hng c Carry. 1.4. Hot ng ca cc Port ni tip. Phn cng truy xut ti Port ni tip qua cc chn TxD (P3.1) v RxD (P3.0). Port ni tip tham d hot ng y (s pht v thu cng lc), v thu vo b m m n cho php 1 k t nhn vo v c ct b m trong khi k t th hai c nhn vo. Nu CPU c k t th nht trc khi k t th hai c nhn vo hon ton th d liu khng b mt. Hai thanh ghi chc nng c bit cung cp cho phn mm truy xut n Port ni tip l SBUF v SCON. S m Port ni tip (SBUF) a ch 99H l 2 s m tht s: Ghi ln SBUF (np d liu pht) v c SBUF (truy xut d liu nhn). y l hai thanh ghi ring bit v r rt, v thanh ghi pht ch ghi cn thanh ghi thu ch c 1.4.1. Thanh ghi iu khin Port ni tip SCON Mode hot ng ca Port ni tip c set bi vic ghi ln thanh ghi mode ca Port ni tip SCON a ch 99H. Bng tm tt thanh ghi iu khin Port ni tip SCON nh sau:

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Bit K hiu a ch SCON.7 SM0 9FH SCON.6 SM1 9EH SCON.5 SM2 9DH

M t hot ng Bit 0 ca mode Port ni tip Bit 1 ca mode Port ni tip Bit 2 ca mode Port ni tip. cho php s truyn ca b x l a knh mode 2 v 3; RI .s khng tch cc nu bit th 9 thu vo l 0 REN = 1 s cho php thu k t Pht bit 8. Bit 9 pht trong mode 2 v 3, c set v xa bi phn mm Thu bit 8. Bit th 9 nhn c C ngt pht. C ny c set ngay khi kt thc vic pht mt k t; c xa bi phn mm C ngt thu. C ny c set ngay khi kt thc vic thu mt k t; c xa bi phn mm

SCON.4 SCON.3 SCON.2 SCON.1

REN TB8 RB8 TI

9CH 9BH 9AH 99H

SCON.0

RI

98H

SM0 SM1 MODE BngM T ca thanh ghi SCON BAUD TC Chc nng 0 0 0 Thanh ghi dch (C nh (tn s dao ng/12 (Thay i (thit lp bi b nh thi 0 1 1 UART 8 bit (C nh (tn s dao ng /12 hoc /64 1 0 2 UART 9 bit (Thay i (thit lp bi b nh thi 1 1 3 UART 9 bit
Cc ch hot ng ca port ni tip

Trc khi dng Port ni tip, SCON phi c nh ng ch . VD: khi to Port ni tip ch 1 (SM0/SM1 = 0/1), cho php thu (REN = 1), v set c ngt ca vic pht sn sng hot ng (TI = 1), ta dng lnh sau : MOV SCON, #01010010H. Port ni tip ca 8051 c 4 mode hot ng ty thuc theo trng thi ca SM0/SM1. Ba trong 4 mode cho php truyn ng b vi mi k t thu hoc pht s c b tr bi bit Start hoc bit Stop. 1.4.2. Khi ng v truy xut cc thanh ghi Port ni tip 1.4.2.1. Cho php thu
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Bit cho php thu REN trong thanh ghi SCON phi c set bi phn mm cho php s thu cc k t. iu ny thng c dng lm u chng trnh khi cc Port ni tip v cc timer c khi ng. Ta c th tc ng bng lnh: SETB REN hoc: MOV SCON, # xxx1xxxxB 1.4.2.2. Dng timer to tc Baud cho port ni tip Mun to ra tc Baud, ta khi to TMOD ch t np li 8 bit (mode 2 ca timer) v t trc gi tr np li ng vo byte cao ca thanh ghi timer 1 (TH1) to ra tc trn chnh xc. C nhng tc Baud rt chm ta dng ch 16 bit l ch 1 ca timer, nhng ta phi khi to li sau mi ln trn cho TL1/TH1. Hot ng khc c m gi bi vic dng timer 1 ngoi l T1 (P3.5). Cng thc chung xc nh tc Baud trong mode 1 v mode 3 l:
BAUD RATE = TIMER 1 OVERFLOW RATE 32

V d mt hot ng 1200 Baud i hi mt tc trn l 1200/32 = 38,4 KHz. Nu thch anh 12MHz li dao ng trn Chip, th timer 1 c m gi tc ca tn s 1 MHz. Bi v timer phi trn tc tn s 38,4 KHz v Timer m gi tc ca tn s 1 MHz, nn mt s trn c yu cu vi 1000/38,4 = 26,04 clock (lm trn 26). Bi v cc timer m ln v trn khi c s chuyn i t FFH 00H ca b m, nn 26 l gi tr cn np cho TH1 (gi tr ng l -26). Ta dng lnh: MOV TH1, #26 V d sau khi khi ng Port ni tip hot ng ging nh mt UART 8 bit tc 2400 Baud, dng timer 1 cung cp tc Baud: MOV SCON, #01010010B MOV TMOD, #20 MOV TH1, #-13 SETB TR1 ; Port ni tip mode 1 ; Timer 1 mode 2 ; Np vo b m tc 2400Baud ;Start timer 1

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Trong SCON c SM0/SM1 vo mode UART 8 bit, REN = 1 cho php Port ni tip thu cc k t v TI = 1 cho php pht k t u tin bi vic cho bit thanh ghi m rng. TMOD c M1/M0 = 1/0 t timer 1 vo mode t ng np li 8 bit. Vic set bit TR1 m my chy timer. Tc Baud 2400 s cho ta tc trn timer 1 l 2400/32 = 76,8 KHz (ng vi thch anh 12 MHz) s cho s xung clock sau mi s trn l 1000/76,8 = 13,02 (ly trn l 13). Vy -13 l gi tr cn np vo TH1 c tc Baud l 2400 Baud. 1.5. Hot ng ngt ca 89V51RB2 Trong nhiu ng dng i hi ta phi dng ngt (Interrupt) m khng dng timer bi v nu dng timer ta phi mt thi gian ch c trn timer TFx set mi x l tip chng trnh. Do ta khng c thi gian lm cc vic khc m ng dng i hi. y l chng trnh rt quan trng ca 8051 ni ring v h MSC 51 ni chung. Ngt l mt s c c iu kin m n gy ra s ngng li tm thi ca chng trnh phc v mt chng trnh khc. Cc ngt ng vai tr quan trng trong vic thit k v hin thc cc ng dng ca b vi iu khin. cc ngt cho php h thng p ng mt s kin theo cch khng ng b v x l s kin trong khi mt chng trnh khc ang thc thi. Mt h thng c iu khin bi ngt cho ta o tng ang lm nhiu cng vic ng thi. Tt nhin CPU khng th thc thi nhiu lnh ti mt thi im, nhng n c th tm thi treo vic thc thi ca chng trnh chnh thc thi chng trnh khc v sau quay li chng trnh chnh. Khi chng trnh chnh ang thc thi m c mt s ngt xy n th chng trnh chnh ngng thc thi v r nhnh n th tc phc v ngt ISP (Interrupt Service Routine). ISR thc thi thc hin hot ng v kt thc vi lnh RETI: chng trnh tip tc ni m n dng li. Timer Ta c th tm tt s thc thi ca 1 chng trnh trong trng hp c ngt v khng c ngt nh sau:
Main Program Thc thi chng trnh khng c ngt ISR * Main Timer Thc thi chng trnh c ngt ** Main ISR * ** 17Main ISR * ** Main

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S ngt ca 8051 Trong k hiu * cho bit ngt chng trnh chnh thc thi chng trnh con trong th tc phc v ngt ISR. Cn k hiu ** cho bit vic quay li chng trnh chnh thc thi tip sau khi kt thc chng trnh con trong ISR. 1.5.1. T chc ngt ca 8051 8051 cung cp 5 ngun ngt, 2 ngt ngoi, 3 ngt timer v mt ngt Port ni tip. tt c cc ngt b mt tc dng bi s mc nh sau khi reset h thng v c cho php c bit bi phn mm. Trong trng hp c hai hoc nhiu hn s ngt xy ra ng thi hoc mt s ngt ang c phc v m xut hin mt s ngt khc, th s c hai cch thc hin s ngt l s kim tra lin tip v s u tin cp 2. 1.5.2. S cho php ngt v s cm ngt Mi ngun ngt c cho php ring bit hoc s cm ring bit qua thanh ghi chc nng c bit c bit nh v IE (Interrupt Enable) ti a ch 0A8H. Cng nh s c bit cho php cc bit ca mi ngun ngt c 1 bit cho php (hoc cm) chung m n c c xa cm tt c cc ngt hoc c set cho php chung cc ngt. Hot ng ca tng bit trong thanh ghi cho php ngt IE c tm tt trong bng sau:

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Bit Symbol Bit Address IE.7 EA AFH IE.6 AEH IE.5 ET2 ADH IE.4 ES ACH IE.3 ET1 ABH IE.2 EX1 AAH IE.1 ET0 A9H IE.0 EX0 A8H

(S m t (Enable=1; Disable Cho php ngt ton cc Khng nh ngha (Cho php ngt timer 2 (8052 Cho php ngt Port ni tip Cho php ngt timer 1 Cho php ngt ngoi External 1 Cho php ngt timer 0 Cho php ngt ngoi External 0

Hot ng ca tng bit trong thanh ghi cho php ngt IE Hai bit phi set cho php 1 s ngt no : l bit cho php ring v bit cho php chung. V d cho php ngt timer 1 ta c th thc hin trn bit: SETB ET1 v SETB EA hoc s thc hin trn byte: MOV IE, #10001000B C hai phng php ny c kt qu chnh xc sau khi reset h thng, nhng kt qu khc nhau nu thanh ghi IE c ghi trn tuyn gia chng trnh. Gii php th nht khng c tc dng trn cc bit cn li trong thanh ghi IE, cn gii php th hai xa cc bit cn li trong thanh ghi IE. u chng trnh ta nn khi to IE vi lnh MOV BYTE, nhng s cho php ngt v cm ngt trn tuyn trong mt chng trnh s dng cc lnh SETB bit v CLR bit trnh kt qu ph vi cc bit khc trong thanh ghi IE. 1.5.3. X l cc ngt
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Khi mt ngt xut hin v c chp nhn bi CPU th chng trnh chnh b ngt. Cc hot ng sau y xut hin: Lnh hin hnh v kt thc thc thi. B m chng trnh PC c ct gi vo Stack. Trng thi ngt hin hnh c ct gi vo bn trong. Nhng s ngt b ngn li ti mc ngt. B m chng trnh PC c LOAD vi a ch vect ca th tc phc v ngt ISR. Th tc phc v ngt ISR c thc thi. Th tc phc v ngt ISR thc thi v a hot ng vo p ng ngt, th tc phc v ngt ISR kt thc vi lnh RETI (quay tr v chng trnh chnh t Stack). iu ny khi phc li gi tr ca b m chng trnh t Stack v hon ton dng li trng thi c. S thc thi ca chng trnh chnh tip tc ni m n ngng li.

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