Thit lp Fuse Bits

AVR c sn mt s mch in v cc thit b h tr bn trong, vic iu khin cc mch in ny c thc hin thng qua cc Fuse bits. V d bn trong cc chip AVR c b to dao ng cho chip, nu mun s dng hoc v hiu ha b to dao ng ny chng ta s set cc Fuse bits iu khin ngun xung clock(c th phn sau). Nh th, Fuse bits cng ging nh cc cu ch hay cc cng tc cng ni AVR vi cc mch in h tr. V l cc cng tc cng nn chng phi c set ring bit, khng set c bng lnh "mm". Mi loi AVR c s lng mch in h tr khc nhau v v th s lng Fuse bits s khc nhau. V tr cc Fuse bits cng khc nhau trn mi dng chip tuy nhin tn gi th nh nhau. Ti s dng chip ATmega32 lm minh ha. Chip ATmega32 c 16 Fuse bits c b tr trong 2 byte gi l Fuse High Byte v Fuse Low Byte. V tr cc Fuse bits khng quan trng (v chng ta dng phn mm h tr set tng Fuse bit) nhng tn gi v chc nng th cn kho st. Bng 1 tm tt cc bits trong Fuse High Byte v bng 2 tm tt cc bits trong Fuse Low Byte. Bng 1. Fuse High Byte

Bng 2. Fuse Low Byte

a s cc chng trnh np chip u h tr np Fuse bits. Cc Fuse c np c lp i vi file chng trnh. Cc phn mm np nh PonyProg, phn mm np trong CodevisionAVR, Bascom, ICCAVRh tr set tng Fuse bit mt trong khi mt s chng trnh nh avrdude ch h tr np cc byte Fuse, nu mun s dng cc chng trnh np ny np Fuse bn cn tnh ton gi tr 2 byte Fuse trc. Mt ch rt quan trng l i vi cc Fuse bits, gn gi tr 0 cho 1 Fuse bit ng ngha vi Fuse bit c lp trnh (programmed), trong khi 1 ngha l khng c lp trnh (unprogrammed). Ti s s dng phn mm PonyProg lm minh ha np Fuse bits cho chip ATmega32. Trc khi np Fuse bits bn cn chn device v loi mch np trong PonyProg (xem li bi Mch np). np Fuse bits bn hy chn menu Command/Security and Configuration Bits hoc nhn Ctrl+S (mch np phi c ni sn vi my tnh v mch AVR). Nhn nt Read c cc cu hnh Fuse bits trn chip ca bn, nu y l ln u tin chip ATmega32 ca bn c np Fuse bits th bn s thu c kt qu cu hnh cc Fuse bits nh trong hnh 1.

Hnh 1. Cu hnh Fuse bits mc nh trn chip ATmega32. Chng ta s ln lt kho st cc Fuse bit theo nhm chc nng ca chng. 1. JTAGEN (JTAG Enable): trn AVR c tch hp sn b JTAG, l mt module giao tip vi phn cng ca chip. Nhn chung, JTAG thng c dng kim tra hot ng ca chip. Trn AVR, JTAG c th c dng np chng trnh nhng ph bin hn l dng debug li chng trnh (g ri chng trnh). Module JTAG lm vic thng qua 4 chn TCK, TMS, TDO v TDI, trn chip ATmega32 4 chn ln ln lt l PC2, PC3, PC4 v PC5. Theo mc nh JTAG c kch hot, bit JTAGEN=0 (programmed) nh trong hnh 1. V th vi cc chip ATmega32 mi mua v, cc chn PC2:5 trn PORTC c th khng s dng xut nhp thng thng c. Nu bn khng mun s dng chc nng Debug trc tip trn chip th hy uncheck bit JTAGEN(uncheck tng ng unprogrammed, tng ng JTAGEN=1) dng cc chn JTAG nh cc chn xut nhp thng thng. 2. OCDEN (On Chip Debug Enable): nh trnh by trn, AVR cho php chng ta g ri chng trnh trc tip trn chip thng qua module JTAG. Trong khi bit JTAGEN cho php kch hot JTAG th bit OCDEN cho php thc hin Debug trn chip (Ngha l cho d kch hot JTAG bn cha th dng chc nng debug nu cha kch hot OCDEN). Nu bn c mt mch Debug cho AVR nh mch JTAG ICE ca Atmel (xem bi Debug vi JTAG ICE) v bn mun debug chng trnh th hy set bit OCDEN bng 0 (check vo OCDEN). Bn cn nh rng, khi lp trnh cho bit OCDEN th AVR s hot ng trong mode Debug, trong mode ny chip s trong trng thi ng (Sleep mode), bn ch c th thc hin Debug m khng th chy chng trnh tht. Theo mc nh, OCDEN khng c lp trnh v ch Debug c v hiu ha. Li khuyn l bn nn bit ny unprogrammed trc khi

a chip vo s dng. (ng ng vo bit ny nu bn khng c nh Debug trn chip). 3. BODEN (Brown-Out Detection Enable) v BODLEVEL(BOD Level): AVR c sn mt mch in Brown-Out Detection, hiu nm na l mch pht hin st in p ngun. Nu fuse BODEN c lp trnh th mch BOD c kch hot, khi fuse bit BODLEVEL chn mc in p ca BOD (mc in p dng so snh st ngun). Nu BODLEVEL=1 (unprogrammed) th mc in p BOD mc nh l 2.7V, ngc li nu BODLEVEL c lp trnh th mc in p BOD l 4.0V. Khi mch BOD c s dng, nu in p VCC gim xung thp hn mc in p BOD th 1 Reset BOD xy ra. Nu khng tht s cn thit hy cc bit ny khng c lp trnh nh mc nh. Hnh 2 m t mt s kin BOD trn AVR.

Hnh 2. S kin BOD trn AVR. 4. EESAVE (EEPROM Erase SAVE): nu bit EESAVE c lp trnh (bng 0), th b nh EEPROM s khng b xa khi xa chip, ngc li EESAVE =1 (unprogrammed) th EEPROM s b xa theo chip. 5. BOOT LOADER: y l mt tnh nng rt hay trn cc chip AVR mi (ch khng phi dng AVR no cng c Boot Loader), Boot Loader l phn b nh chng trnh c kch hot u tin khi khi ng chip. Boot Loader trn cc chip AVR c b tr pha di ca b nh chng trnh (xem li bi 2, cu trc AVR). Boot Loader thng c s dng ghi hoc c ni dung b nh chng trnh, v th ng dng ph bin nht ca n l update chng trnh cho chip mt mt cch nhanh chng m khng cn mch np. C ch nh sau: -Trc ht chng ta cn c 1 chng trnh Boot Loader c np sn trong phn b nh Boot Loader (pha di b nh chng trnh). Chng trnh ny c

kh nng giao tip vi my tnh (thng qua UART chng hn) v c, ghi b nh chng trnh ca chip. -Khi cn update chng trnh mi cho AVR, trn my tnh c 1 chng trnh giao tip vi Boot Loader, kt ni AVR vi my tnh, chng trnh trn my tnh s gi ni dung cn update cho AVR, chng trnh Boot Loader s c ni dung ny v ghi vo b nh chng trnh ca AVR. Bng cch ny chng ta np chng trnh cho AVR m khng cn dng mch np. Np chng trnh bng Boot Loader cho php khch hng ca bn t cp nht cc chc nng mi m khng cn trao chip cho bn. S dng hay khng s dng Boot Loader s c xc lp thng qua cc Fuse bits BOOTRST, BOOTSZ1 v BOOTSZ0. -BOOTRST (Select Reset Vector) : Nu Fuse bit BOOTRST khng c lp trnh (bng 1) th khi va khi ng chip, con tr chng trnh s nhy n v tr u tin trong chng trnh (0x0000) ln lt thc thi phn chng trnh nh thng thng. Nu BOOTRST c lp trnh (bng 0) th v tr Reset l a ch u ca phn Boot Loader, khng phi a ch 0x0000 nh thng l. Khi phn chng trnh trong Boot Loader s c thc thi thay cho chng trnh chnh pha trn (xem hnh 3).

Hnh 3. nh hng ca Fuse bit BOOTRST. -BOOTSZ1 v BOOTSZ0 (Select Boot Size): kch thc phn b nh dnh cho Boot Loader khng c nh, nu Boot Loader khng c kch hot (fuse BOOTRST=1) th ton b b nh chng trnh dnh cho chng trnh chnh. Khi Boot Loader c kch hot, 2 Fuse bits BOOTSZ1 v BOOTSZ0 s quyt nh kch thc Boot Loader. Bng 3 tm tt cc kch thc ca phn Boot Loader ph thuc vo 2 bit BOOTSZ1:0. Ch l kch thc tnh theo

INSTRUCTION WORD, vi AVR 1 INSTRUCTION WORD = 2 bytes. Phi nhc li i vi Fuse bits, gi tr 1 ngha l khng c lp trnh (khng check trong PonyProg). Nu bit BOOTRST khng c lp trnh th 2 bit BOOTSZ khng c tc dng. Bng 3. Kch thc Boot Loader.

Trong cc ng dng lp trnh thng thng, Boot Loader khng c quan tm, v th ti khuyn bn nn cc Fuse bit BOOTRST, BOOTSZ1:0 nh mc nh, khi no cn s dng ti s ni r (xem bi Debug vi mch JTAG ICE). 6. Chn Ngun Xung gi nhp v thi gian khi ng (start-up times): y l phn rt c quan tm khi set Fuse bits. C n 7 Fuse bits tham gia vo vic ny l 4 bits CKSEL3:0, 2 bis SUT1:0 v bit CKOPT. Trong 2 bit SUT1:0 ch yu dng chn thi gian khi ng, phn ny khng nh hng nhiu trong hu ht cc trng hp (t nht l cc v d trong Cng hc AVR) v th ti s b qua, chng ta 2 fuse bits nh mc nh. Nu start-up time tht s nh hng n chng trnh ca bn, bn hy tham kho thm phn System Clock and Clock Option trong datasheet ca chip. Phn ny ti ch yu trnh by cch chn ngun xung gi nhp cho chip. C tt c 5 loi ngun xung gi nhp chnh cho chip nhng n gin chng ta ch xt 2 trng hp l dng ngun thch anh ngoi v dng xung gi nhp c to bi mch RC trong chip. Xung gi nhp trong chip (xung ni): Hu ht cc chip AVR c trang b 1 mch to xung gi nhp RC bn trong, nu s dng ngun xung gi nhp ny chng ta c th b qua mch to xung bn ngoi. Ngun xung gi nhp c to ra bn trong chip c c nh 1 trong 4 mc : 1MHz, 2 MHz, 4 Mhz v 8 MHz. Cc Fuse bits CKSEL3:0 quyt nh vic chn ngun xung ny. Bng 4 tm tt cch phi hp cc Fuse bits CKSEL chn ngun xung ni.

Bng 4. Chn xung gi nhp ni bng cc Fuse bits CKSEL.

(Nomial frequency: tn s danh ngha, gi tr thc c th khc do sai s) i vi chip ATmega32, ngun xung ni 1MHz c set mc nh trn cc chip mi. Xem li hnh 1 bn thy CKSEL3=0 (c checked), CKSEL2=0 (c checked), CKSEL1=0 (c checked), CKSEL0=1 (khng check). Cc hnh 4, 5, 6 v 7 bn di gi bn cch chn ngun xung ni bng phn mm np PonyProg, ch sau khi chn cc bits bn phi nhn bt Write ghi vo chip.

Hnh 4. Chn ngun xung ni 1MHz (ng thi tt JTAG, Boot Loader, BOD).

Hnh 5. Chn ngun xung ni 2MHz (ng thi tt JTAG, Boot Loader, BOD).

Hnh 6. Chn ngun xung ni 4MHz (ng thi tt JTAG, Boot Loader, BOD).

Hnh 7. Chn ngun xung ni 8MHz (ng thi tt JTAG, Boot Loader, BOD).

Xung gi nhp t mch thch anh bn ngoi (Crystal): dng xung ni c nhc im l tn s xung c gi c nh trong 4 mc v tn s cao nht c th t l 8MHz trong khi AVR cho php lm vic 16Mhz, mc khc sai s cng tng i ln khi xng xung ni. Dng thch anh to xung gi nhp l mt gii php tt, c th to mt mch thch anh n gin v ni vi 2 chn XTAL1 v XTAL2 ca AVR nh trong hnh 8.

Hnh 8. Mch to xung ngoi bng thch anh. bo cho AVR bit l chng ta mun s dng thch anh ngoi lm mch to xung, hy set cc Fuse bits CKSEL3:0 thnh 1 trong 2 gi tr: 1111 hoc 1010 (nh phn). Trong trng hp ny, Fuse bit CKOPT c tc dng chn gia 2 ch khuych i, ch CKOPT = 0 (programmed) thch hp vi thch anh c tn s ln nht l 16MHz v CKOPT=1 (unprorgammed) khi tn s thch anh nh hn hoc bng 8MHz. Cc hnh 9 v 10 gi cch set Fuse bits chn ngun xung nhp l mch thch anh ngoi vi cc tn s ln nht 8MHz v ln nht 16MHz.

Hnh 9. Chn xung gi nhp t thch anh ngoi vi tn s ln nht l 8MHz.

Hnh 10. Chn xung gi nhp t thch anh ngoi vi tn s ln nht l 16MHz. Sau khi chn cc Fuse bits, vic cui cng v rt quan trng l ghi cc Fuse bits ny vo chuip bng cch nhn nt Write (PonyProg). i vi cc chng trnh np chip khc, Fuse bits cng c set tng t.