Vi Dieu Khien Avr Atmega128 C Le Trung Thang 2008 7976

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VI IU KHIN AVR ATmega 128
L Trung Thng Con ngi nh c m m v i
. Ti liu ny trc y l seminar ca ti v vi iu khin AVR vo khong

cui nm 2007, lc u cng ch ghi chp nh mt cun s tay ghi nh, n lc xong ci seminar th thy con AVR ny cng rt th v, nn ti chnh sa li bn ghi chp son thnh ti liu ny. C l l do quen vi h 8051 do Atmel sn xut, nn khi chuyn sang AVR s cm thy quen thuc hn. Mc ch chnh m ti vit ti liu ny l chia s vi cc bn c cng s thch v AVR, qua chng ta c th to ra mt cng ng AVR-Friends tht ng o v si ni. Mt cng ng AVR ng o l rt c ch cho chnh ti v cho cc bn, v nh th chng ta s c nhiu c hi trao i v hc hi nhau hn. Ti liu ny ti cng mun gi tng em trai L Trung Thng, hy vng em c th b sung cho anh nhng phn cn thiu ca ti liu ny. Ton b ti liu ny ch yu c dch ra t datasheet ca con Atmega128, nhng do khng c nhiu thi gian nn ti liu cn thiu rt nhiu phn, nn ti hi vng cc bn no c kinh nghim v AVR s tip tc b sung, chnh sa chng ta c mt ti liu hon chnh hn, nu cn, ti c th gi file word cho cc bn tin li cho vic b sung, chnh sa (mail to: thangvl2a@yahoo.com).
Si Gn, 08-2008. L Trung Thng. TVT - K2002.
H Khoa Hc T Nhin TP. H Ch Minh - 2007
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Mc Lc:
Chng I ------------------------------------TNG QUAN. Chng II -----------------------------------CU TRC B NH V CNG VO - RA. Chng III ----------------------------------B NH THI CA ATmega128. Chng IV ----------------------------------CU TRC NGT CA ATmega128. Chng V -----------------------------------CC B PHN NGOI VI KHC. Chng VI -----------H THNG XUNG CLOCK V LP TRNH B NH ON-CHIP. Chng VI --------------------------------- LP TRNH AVR BNG NGN NG C.
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Chng I
TNG QUAN
Nhng Tnh Nng Chnh Ca ATmega128:
ROM : 128 Kbytes SRAM: 4Kbytes EEPROM : 4Kbytes 64 thanh ghi I/O 160 thanh ghi vo ra m rng 32 thanh ghi a mc ch. 2 b nh thi 8 bit (0,2). 2 b nh thi 16 bit (1,3). B nh thi watchdog B dao ng ni RC tn s 1 MHz, 2 MHz, 4 MHz, 8 MHz ADC 8 knh vi phn gii 10 bit ( dng Xmega ln ti 12 bit ) 2 knh PWM 8 bit 6 knh PWM c th lp trnh thay i phn gii t 2 ti 16 bit B so snh tng t c th la chn ng vo Hai khi USART lp trnh c Khi truyn nhn ni tip SPI Khi giao tip ni tip 2 dy TWI H tr boot loader 6 ch tit kim nng lng La chn tn s hot ng bng phn mm ng gi 64 chn kiu TQFP. Tn s ti a 16MHz in th : 4.5v - 5.5v v.v Vi iu khin AVR do hng Atmel ( Hoa K ) sn xut c gi thiu ln u nm 1996. AVR c rt nhiu dng khc nhau bao gm dng Tiny AVR ( nh AT tiny 13, AT tiny 22) c kch thc b nh nh, t b phn ngoi vi, ri n dng AVR ( chn hn AT90S8535, AT90S8515,) c kch thc b nh vo loi trung bnh v mnh hn l dng Mega ( nh ATmega32, ATmega128,) vi b nh c kch thc vi Kbyte n vi trm Kb cng vi cc b ngoi vi a dng c tch hp trn chip, cng c dng tch hp c b LCD trn chip ( dng LCD AVR ). Tc ca dng Mega cng cao hn so vi cc dng khc. S khc nhau c bn gia cc dng chnh l cu trc ngoi vi, cn nhn th vn nh nhau, Hnh 1.1. t bit, nm 2008, Atmel li tip tc cho ra i dng AVR mi l XmegaAVR, vi nhng tnh nng mnh m cha tng c cc dng AVR trc . C th ni XmegaAVR l dng MCU 8 bit mnh m nht hin nay.
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Hnh1.1 Cc dng AVR khc nhau: Tiny, AVR v Mega Cu trc c bn ca vi iu khin AVR c th hin hnh 1.2.
Hnh 1.2. Cu trc ca Vi iu khin AVR
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Chng II CU TRC B NH V CNG VO - RA I. CU TRC B NH Gii Thiu:

B nh vi iu khin AVR c cu trc Harvard l cu trc c ng Bus ring cho b nh chng trnh v b nh d liu. B nh AVR c chia lm 2 phn chnh: B nh chng trnh ( program memory ) v b nh d liu ( Data memory ). B Nh Chng Trnh : B nh chng trnh ca AVR l b nh Flash c dung lng 128 K bytes. B nh chng trnh c rng bus l 16 bit. Nhng a ch u tin ca b nh chng trnh c dng cho bng vc t ngt ( xem chi tit v bng vc t ngt chng 4 ). Cn l vi iu khin ATmega128 b nh chng trnh cn c th c chia lm 2 phn : phn boot loader ( Boot loader program section ) v phn ng dng ( Application program section ). Phn boot loader cha chng trnh boot loader. Chng trnh Boot loader l mt phn mm nh np trong vi iu khin v c chy lc khi ng. Phn mm ny c th ti vo trong vi iu khin chng trnh ca ngi s dng v sau thc thi chng trnh ny. Mi khi reset vi iu khin CPU s nhy ti thc thi chng trnh boot loader trc, chng trnh boot loader s d xem c chng trnh no cn np vo vi iu khin hay khng, nu c chng trnh cn np, boot loader s np chng trnh vo vng nh ng dng (Application program section ), ri thc thi chng trnh ny. Ngc li, boot loader s chuyn ti chng trnh ng dng c sn trong vng nh ng dng thc thi chng trnh ny. Phn ng dng (Application program section ) l vng nh cha chng trnh ng dng ca ngi dng. Kch thc ca phn boot loader v phn ng dng c th ty chn. Hnh 2.1 th hin cu trc b nh chng trnh c s dng v khng s dng boot loader, khi s dng phn boot loader ta thy 4 word u tin thay v ch th cho CPU chuyn ti chng trnh ng dng ca ngi dng (l chng trnh c nhn start ) th ch th CPU nhy ti phn chng trnh boot loader thc hin trc, ri mi quay tr li thc hin chng trnh ng dng.
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Hnh 2.1 B nh chng trnh c v khng c s dng boot loader
B Nh D Liu : B nh d liu ca AVR chia lm 2 phn chnh l b nh

SRAM v b nh EEPROM. Tuy cng l b nh d liu nhng hai b nh ny li tch bit nhau v c nh a ch ring. B nh SRAM c dng lng 4 K bytes, B nh SRAM c hai ch hot ng l ch thng thng v ch tng thch vi ATmega103, mun thit lp b nh SRAM hot ng theo ch no ta s dng bit cu ch M103C ( M103C fuse bit (9) ). B nh SRAM ch bnh thng : ch bnh thng b nh SRAM c chia thnh 5 phn: Phn u l 32 thanh ghi chc nng chung (General Purpose Register ) R0 n R31 c a ch t $0000 ti $001F. Phn th 2 l khng gian nh vo ra vi 64 thanh ghi vo ra ( I/O Register ) c a ch t $0020 ti $005F. Phn th 3 dng cho vng nh dnh cho cc thanh ghi vo ra m rng ( Extended I/O Registers ) c a ch t $0060 ti $00FF. Phn th 4 l vng SRAM ni vi 4096 byte c a ch t $0100 ti $10FF. Phn th 5 l vng nh SRAM ngoi ( External SRAM ) bt u t a ch $1100, vng SRAM m rng ny c th m rng ln n 64 K byte. Khi ni b nh SRAM c dung
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lng 4 K byte l ni ti phn th 4 ( SRAM ni ). Nu tnh c cc thanh ghi th b nh SRAM trong ch bnh thng s l 4.25 K byte = 4352 byte. B nh SRAM ch tng thch ATmega103 : ch ny b nh SRAM c bn cng ging ch bnh thng, ngoi tr phn th 3 l vng nh dnh cho cc thanh ghi vo ra m rng khng tn ti, ngoi ra kch thc ca phn SRAM ni ( internal SRAM ) ch c 4000 byte so vi 4096 byte ch bnh thng. Hnh 2.2 th hin s b nh d liu c hai ch : Bnh thng v tng thch ATmega103. T hnh 2.2 ta thy nu cu hnh b nh SRAM hot ng ch tng thch ATmega103 th ta s b mt i 160 thanh ghi vo ra m rng ( extended I/O Register ), l nhng thanh ghi ng vai tr quan trng trong cc ch hot ng ca vi iu khin.
Hnh 2.2 Bn b nh d liu A : Ch bnh thng B: Ch tng thch ATmega103

Trong vng nh vo ra m rng ( $0060 - $00FF ) ch c 6 lnh sau l c th c s dng, l : ST / STS / STD v LD / LDS / LDD.
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Lnh CBI v SBI ch c th lm vic vi 32 thanh ghi thp hn trong vng nh vo ra , tc cc thanh ghi I/O c a ch t $20 ti $3F ( a ch SRAM ). 64 thanh ghi vo ra trong vng nh vo ra ( phn s 2 ) c 2 kiu chn a ch : Nu xem chng l vng nh vo ra th a ch s l $00 - $3F, khi s dng cc lnh in, out ta phi s dng a ch ny. Nu xem chng nh l mt phn ca b nh SRAM th s c a ch l $0020 - $005F, khi ta dng cc lnh nh LD, ST ta phi s dng kiu a ch ny. (hnh 2.3 ). Trong ti liu ny cc a ch c s dng s c hiu nh l a ch SRAM nu khng c gii thch g thm. l 160 thanh ghi vo ra m rng ( $0060 - $00FF ) khng c 2 kiu chn a ch nh trn, a ch ca chng chnh l cc a ch SRAM .
$00 Thanh ghi PIN F $0020
$01 Thanh ghi PIN E
$0021
a Ch Vao Ra
64 thanh ghi vao ra
a Ch SRAM
Thanh ghi SPH
$3F Thanh ghi SREG $005F

Hnh 2.3 Vng nh 64 thanh ghi vo ra c 2 cch chn a ch Chi tit v 64 thanh ghi vo ra v 160 thanh ghi vo ra m rng c th tm thy datasheet ca vi iu khin ATmega128. Tip ghanh ghi ( register file ) : Tip 32 thanh ghi a chc nng ( $0000 - $001F ) c ni trn, ngoi chc nng l cc thanh ghi a chc nng, th cc thanh ghi t R26 ti R31 tng i mt to thnh cc thanh ghi 16 bit X, Y, Z c dng lm con tr tr ti b nh chng trnh v b nh d liu ( Hnh 2.4 ). Thanh ghi con tr X, Y c th dng lm con tr tr ti b nh d liu, cn thanh ghi Z c th dng lm con tr tr ti b nh chng trnh. Cc trnh bin dch C thng dng cc thanh ghi con tr ny qun l Data stack ca chng trnh C.
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Hnh 2.4. Chc nng con tr ca cc thanh ghi R26 R31 B nh EEPROM : y l b nh d liu c th ghi xa ngay trong lc vi iu khin ang hot ng v khng b mt d liu khi ngun in cung cp b ct. C th v b nh d liu EEPROM ging nh l cng ( Hard disk ) ca my vi tnh. Vi vi iu khin ATmega128, b nh EEPROM c kch thc l 4 Kbyte. EEPROM c xem nh l mt b nh vo ra c nh a ch c lp vi SRAM, iu ny c ngha l ta cn s dng cc lnh in, out khi mun truy xut ti EEPROM. iu khin vo ra d liu vi EEPROM ta s dng 3 thanh ghi sau : 1. Thanh Ghi EEAR ( EEARH v EEARL )
EEAR l thanh ghi 16 bit lu gi a ch ca cc nh ca EEPROM, thanh ghi EEAR c kt hp t 2 thanh ghi 8 bit l EEARH v thanh ghi EEARL. V b nh
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EEPROM ca ATmega128 c dung lng 4 Kbyte = 4096 byte = 212 byte nn ta ch cn 12 bit ca thanh ghi EEAR , 4 bit t 15 -12 c d tr, ta nn ghi 0 vo cc bit d tr ny. 2. Thanh Ghi EEDR
y l thanh ghi d liu ca EEPROM, l ni cha d liu ta nh ghi vo hay ly ra t EEPROM. 3. Thanh Ghi EECR
y l thanh ghi iu khin EEPROM, ta ch s dng 4 bit u ca thanh ghi ny, 4 bit cui l d tr, ta nn ghi 0 vo cc bit d tr. Sau y ta xt chc nng ca tng bit. Bit 3 EERIE: EEPROM Ready Interrupt Enable : y l bit cho php EEPROM ngt CPU, khi bit ny c set thnh 1 v ngt ton cc c cho php ( bng cch set bit I trong thanh ghi SREG ln 1 ) th EEPROM s to ra mt ngt vi CPU khi bit EEWE c xa, iu ny c ngha l khi cc ngt c cho php ( bit I trong thanh ghi SREG v bit EERIE trong thanh ghi EECR c set thnh 1 ) v qu trnh ghi vo ROM va xong th s to ra mt ngt vi CPU, chng trnh s nhy ti vc t ngt c a ch l $002C thc thi chng trnh phc v ngt ( ISR ). Khi bit EERIE l 0 th ngt khng c cho php. Bit 2 EEMWE: EEPROM Master Write Enable : Khi bit EEMWE v bit EEWE l 1 s ra lnh cho CPU ghi d liu t thanh ghi EEDR vo EEPROM, a ch ca nh cn ghi trong EEPROM c lu trong thanh ghi EEAR . Khi bit ny l 0 th khng cho php ghi vo EEPROM. Bit EEMWE s c xa bi phn cng sau 4 chu k my. Bit 1 EEWE: EEPROM Write Enable : Bit ny va ng vai tr nh mt bit c, va l bit iu khin vic ghi d liu vo EEPROM. vai tr ca mt bit iu khin nu bit EEMWE c set ln 1 th khi ta set bit EEWE ln 1 s bt u qu trnh ghi d
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liu vo EEPROM. Trong sut qu trnh ghi d liu vo EEPROM bit EEWE lun gi l 1. vai tr ca mt bit c khi qu trnh ghi d liu vo EEPROM hon tt, phn cng s t ng xa bit ny v 0. Trc khi ghi d liu vo EEPROM ta cn phi bit chc l khng c qu trnh ghi EEPROM no khc ang xy ra, bit c iu ny ta cn kim tra bit EEWE. Nu bit EEWE l 1 tc l EEPROM ang c ghi, ta phi ch cho cho qu trnh ghi vo EEPROM hon tt th mi ghi tip. Nu bit EEWE l 0 tc l khng c qu trnh ghi EEPROM no ang din ra, lc ny ta c th bt u ghi d liu vo EEPROM. Khi bit EEWE c set ln 1 ( bt u ghi vo EEPROM ) CPU s tm ngh trong 2 chu k my trc khi thc hin lnh k tip. Bit 0 EERE: EEPROM Read Enable : Khi bit ny l 1, s cho php c d liu t EEPROM, d liu t EEPROM c a ch lu trong thanh ghi EEAR lp tc c chuyn vo thanh ghi EEDR. Khi bit EERE l 0 th khng cho php c EEPROM. Trc khi c d liu t EEPROM ta cn bit chc l khng din ra qu trnh ghi EEPROM bng cch kim tra bit EEWE. l sau khi qu trnh c EEPROM hon tt, bit EERE s c t ng xo bi phn cng. Nu EEPROM ang c ghi th ta khng th c c d liu t EEPROM. Khi bt u qu trnh c d liu t EEPROM, CPU s tm ngh 4 chu k my trc khi thc hin lnh k tip.
Tm li ghi vo EEPROM ta cn thc hin cc bc sau:

1. Ch cho bit EEWE v 0. 2. Cm tt c cc ngt. 3. Ghi a ch vo thanh ghi EEAR. 4. Ghi d liu m ta cn ghi vo EEPROM vo thanh ghi EEDR. 5. Set bit EEMWE thnh 1. 6. Set bit EEWE thnh 1 . 7. Cho php cc ngt tr li. Nu mt ngt xy ra gia bc 5 v 6 s lm hng qu trnh ghi vo EEPROM bi v bit EEMWE sau khi set ln 1 ch c gi trong 4 chu k my, chng trnh ngt s lm ht thi gian ( time out ) duy tr bit ny mc 1. Mt ngt xut hin cui bc 4 cng c th lm cho a ch v d liu cn ghi vo EEPROM tr nn khng chnh xc nu trong chng trnh phc v ngt c chnh sa li cc thanh ghi EEAR v EEDR. l l do ta cn cm cc ngt trc khi thc hin tip cc bc 3, 4, 5, 6. Qu trnh ghi d liu vo EEPROM cng c th khng an ton nu in th ngun nui ( Vcc ) qu thp. on chng trnh sau thc hin qu trnh ghi d liu vo EEPROM.
EEPROM_write: ; ch cho bit EEWE v 0

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sbic EECR,EEWE rjmp EEPROM_write ;cm cc ngt cli ; ghi a ch vo thanh ghi EEAR out EEARH, r18 out EEARL, r17 ; Ghi d liu vo thanh ghi EEDR out EEDR,r16 ; set bit EEMWE thnh 1 sbi EECR,EEMWE ; Set bit EEWE ln 1 bt u ghi vo EEPROM sbi EECR,EEWE ; cho php cc ngt hot ng tr li sei ret
c d liu t EEPROM:
Vic c d liu t EEPROM n gin hn ghi d liu vo EEPROM, c d liu t EEPROM ta thc hin cc bc sau: 1. Ch cho bit EEWE v 0. 2. Ghi a ch vo thanh ghi EEAR. 3. Set bit EERE ln 1. on chng trnh sau thc hin qu trnh c d liu t EEPROM. EEPROM_read: ; ch cho bit EEWE v 0 sbic EECR,EEWE rjmp EEPROM_read ; a a ch vo thanh ghi EEAR out EEARH, r18 out EEARL, r17 ; Set bit EERE bt u c EEPROM sbi EECR,EERE ; a d liu vo thanh ghi R16 in r16,EEDR ret
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Tm tc: Bn b nh bn trong ca ATmega128 c th tm tc li nh sau:

Bo nh chng trnh
$0000 $0000
Bo nh d lieu
32 Thanh Ghi 64 Thanh ghi I/O 160 Thanh ghi I/O m rong
Bo nh EEPROM
$000 4 Kbyte
16 Bit
128 Kbyte 4 Kbyte SRAM noi 8 Bit

$10FF $FFF
8 Bit
$FFFF
Ban o bo nh ATmega128
Hnh 2.5. Tm tc bn b nh ATmega128
II. CNG VO RA II.1. GII THIU

Cng vo ra l mt trong s cc phng tin vi iu khin giao tip vi cc thit b ngoi vi. ATmega128 c c thy 7 cng ( port ) vo ra 8 bit l : PortA, PortB, PortC, PortD, PortE, PortF, PortG, tng ng vi 56 ng vo ra. Cc cng vo ra ca AVR l cng vo ra hai chiu c th nh hng, tc c th chn hng ca cng l hng vo (input ) hay hng ra (output ). Tt cc cc cng vo ra ca AVR iu c tnh nng c Chnh sa Ghi ( Read Modify write ) khi s dng chng nh l cc cng vo ra s thng thng. iu ny c ngha l khi ta thay i hng ca mt chn no th n khng lm nh hng ti hng ca cc chn khc. Tt c cc chn ca cc cng ( port )
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iu c in tr ko ln ( pull-up ) ring, ta c th cho php hay khng cho php in tr ko ln ny hot ng. in tr ko ln l mt in tr c dng khi thit k cc mch in t logic. N c mt u c ni vi ngun in p dng (thng l Vcc hoc Vdd) v u cn li c ni vi tn hiu li vo/ra ca mt mch logic chc nng. in tr ko ln c th c lp t ti cc li vo ca cc khi mch logic thit lp mc logic li vo ca khi mch khi khng c thit b ngoi ni vi li vo. in tr ko ln cng c th c lp t ti cc giao din gia hai khi mch logic khng cng loi logic, c bit l khi hai khi mch ny c cp ngun khc nhau. Ngoi ra, in tr ko ln cn c lp t ti li ra ca khi mch khi li ra khng th ni ngun to dng, v d cc linh kin logic TTL c cc gp h. i vi h logic lng cc vi ngun nui 5 Vdc th gi tr ca in tr ko ln thng nm trong khong 1000 n 5000 Ohm, ty theo yu cu cp dng trn ton gii hot ng ca mch. Vi lgc CMOS v lgc MOS chng ta c th s dng cc in tr c gi tr ln hn nhiu, thng t vi ngn n mt triu Ohm do dng r r cn thit li vo l rt nh. Trong vic thit k cc vi mch ng dng, nu mt IC c ng ra loi cc thu h giao tip vi nhiu IC khc th gi tr ca in tr ko ln s tng i nh (khong vi trm Ohm). Bi v lc ny h s fanout ln dn n dng ng ra ca IC phi ln cung cp cho cc ng vo ca cc IC khc, nu khng vi mch s hot ng chp chn hoc c th khng hot ng.
II.2. CCH HOT NG :

Khi kho st cc cng nh l cc cng vo ra s thng thng th tnh cht ca cc cng ( PortA, PortB,PortG ) l tng t nhau, nn ta ch cn kho st mt cng no trong s 7 cng ca vi iu khin l . Mi mt cng vo ra ca vi iu khin c lin kt vi 3 thanh ghi : PORTx, DDRx, PINx. ( y x l thay th cho A, B,G ). Ba thanh ghi ny s c phi hp vi nhau iu khin hot ng ca cng, chn hn thit lp cng thnh li vo c s dng in tr pull-up, ..v.v.. . Sau y l din t c th vai tr ca 3 thanh ghi trn.
a. Thanh Ghi DDRx.

y l thanh ghi 8 bit ( c th c ghi ) c chc nng iu khin hng ca cng (l li ra hay li vo ). Khi mt bit ca thanh ghi ny c set ln 1 th chn tng ng vi n c cu hnh thnh ng ra. Ngc li, nu bit ca thanh ghi DDRx l 0 th chn tng ng vi n c thit lp thnh ng vo. Ly v d: Khi ta set tt c 8 bit ca thanh ghi DDRA u l 1, th 8 chn tng ng ca portA l PA1, PA2, PA7 ( tng ng vi cc chn s 50, 49, 44 ca vi iu khin ) c thit lp thnh ng ra.
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Thanh ghi DDRA
b. Thanh Ghi PORTx.

PORTx l thanh ghi 8 bit c th c ghi. y l thanh ghi d liu ca PORTx, Nu thanh ghi DDRx thit lp cng l li ra, khi gi tr ca thanh ghi PORTx cng l gi tr ca cc chn tng ng ca PORTx, ni cch khc, khi ta ghi mt gi tr logic ln 1 bit ca thanh ghi ny th chn tng ng vi bit cng c cng mc logic. Khi thanh ghi DDRx thit lp cng thnh li vo th thanh ghi PORTx ng vai tr nh mt thanh ghi iu khin cng. C th , nu mt bit ca thanh ghi ny c ghi thnh 1 th in tr treo ( pull-up resistor ) chn tng ng vi n s c kch hot, ngc li nu bit c ghi thnh 0 th in tr treo chn tng ng s khng c kch hot, cng trng thi cao tr ( Hi-Z ).
Thanh ghi PORTA
c. Thanh Ghi PINx.

PINx khng phi l mt thanh ghi thc s, y l a ch trong b nh I/O kt ni trc tip ti cc chn ca cng. Khi ta c PORTx tc ta c d liu c cht trong PORTx, cn khi c PINx th gi tr logic hin thi chn ca cng tng ng c c. V th i vi thanh ghi PINx ta ch c th c m khng th ghi. Bng 25 th hin cc cc thit lp cch hot c th c ca cng.
Thanh ghi PINA
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DDRxn 0 0 0 1 1
PORTxn
Ch thch PUD ( Trong I/O Pull-up thanh ghi SFIOR Cao tr 0 x Ng vo khng Nh mt ngun dng 1 0 Ng vo c Cao tr 1 1 Ng vo khng Ng ra thp 0 x Ng ra khng Ng ra cao 1 x Ng ra khng Bng 25. Cu hnh cho cc chn cng DDRxn l bit th n ca thanh ghi DDRx PORTxn l bit th n ca thanh ghi PORTx Du x ct th 3 ch gi tr logic l ty
Hnh 30. S mt cng vo ra
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Hnh 30 th hin s ca mt chn ca cng vo ra. s trn ta thy ngoi 2 bit ca cc thanh ghi DDRx v PORTx tham gia iu khin in tr treo (pull-up resistor ), cn c mt tn hiu na iu khin in tr treo, l tn hiu PUD, y l bit nm trong thanh ghi SFIOR, khi set bit ny thnh 1 th in tr ko ln s khng c cho php bt k cc thit lp ca cc thanh ghi DDRx v PORTx. Khi bit ny l 0 th in tr ko ln c cho php nu { DDRxn, PORTxn } = { 0, 1 } .
Thanh ghi SFIOR Di y l a ch ca tt c cc port : Tn PORT PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND PORTE DDRE PINE PORTF DDRF PINF PORTG DDRG PING a ch I/O $1B $1A $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $03 $02 $01 Khng c Khng c $00 Khng c Khng c Khng c a ch SRAM $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 $23 $22 $21 $62 $61 $20 $65 $64 $63
: 3 bit cui ( bit 5, 6, 7 ) ca cc thanh ghi PORTG, DDRG v PING khng s dng c. Khi c ta lun nhn c gi tr 0.
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Chng III
B NH THI CA ATmega128
ATmega128 c 4 b nh thi , b nh thi 1 v 3 l b nh thi 16 bit, b nh thi 0 v 2 l b nh thi 8 bit. Di y l m t chi tit ca 4 b nh thi.
I. B NH THI 1.
S khi b nh thi 1 (3):
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B nh thi 1 v 3 l b nh thi 16 bit, b nh thi 1 s dng 13 thanh ghi lin quan, cn b nh thi 3 s dng 11 thanh ghi lin quan vi nhiu ch thc thi khc nhau.V b nh thi 1 v 3 hot ng ging nhau nn y ch trnh by b nh thi 1. Mt m cn l trong cc thanh ghi lin quan ti b nh thi 1 v 3 th c nhiu thanh ghi c chia s cho c hai b nh thi, chn hn thanh ghi ETIPR c bt cui l OCF1C c dng cho b nh thi 1, cc bit cn li l dng cho b nh thi 3. Thm ch c nhng thanh ghi chia s cho b nh thi 0 hoc 2, chn hn thanh ghi TIMSK c hai bit cui dng cho b nh thi 2, hai bit u dng cho b nh thi 0, cc bit cn li dng cho b nh thi 1. Cc thanh ghi lin quan ti b nh thi 3 cng c lit k ra m khng cn gii thch chi tit, tuy vy cng c vi khc bit nh gia b nh thi 1 v 3 c ch thch cho tng trng hp c th trong mc B nh Thi 3. tm hiu v b nh thi 1 (3) ta cn nm vng cc thanh ghi lin quan ti b nh thi 1(3) v cc ch hot ng ca b nh thi. CC NH NGHA: Cc nh ngha sau s c s dng cho b nh thi 1 v 3 : BOTTOM B m t ti gi tr BOTTOM khi n c gi tr 0000h MAX B m t ti gi tr MAX khi n bng FFFFh TOP B m t gi tr TOP khi n bng vi gi tr cao nht trong chui m, gi tr cao nht trong chui m khng nht thit l FFFFh m c th l bt kh gi tr no c qui nh trong thanh ghi OCRnX (X=A,B,C) hay ICRn, ty theo ch thc thi. CC THANH GHI B NH THI 1. 1. Thanh ghi TCCR1A (Timer/Counter1 Control Register)
Bit 7:6 COMnA1:0: Compare Output Mode for Channel A Bit 5:4 COMnB1:0: Compare Output Mode for Channel B Bit 3:2 COMnC1:0: Compare Output Mode for Channel C Bit 1:0 WGMn1:0: Waveform Generation Mode Bit 7:2 COMnX1:0 (X=A, B, C): Compare Output Mode for Channel X : iu khin cch hot ng ca ng ra so snh (compare output) ca ln lt cc chn OCnA, OCnB v OCnC. Nu mt hay c hai bit COMnA1:0 c set ln 1 th ng ra
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OCnA s u tin hn chc nng port I/O thng thng m n kt ni ti . Nu mt hay c hai bit COMnB1:0 c set ln 1 th ng ra OCnB s u tin hn chc nng port I/O thng thng m n kt ni ti . Nu mt hay c hai bit COMnC1:0 c set ln 1 th ng ra OCnC s u tin hn chc nng port I/O thng thng m n kt ni ti, iu ny c ngha l mi mt chn ca vi iu khin c th thc hin nhiu chc nng khc nhau, bnh thng cc chn OCnA, OCnB, OCnC hot ng nh cc chn vo ra thng thng, nhng khi b nh thi ang hot ng cc ch c s dng ti chc nng so snh khp (compare match) nh cc ch CTC, PWM,ca b nh thi th hnh vi ca chn ng ra OCnA, OCnB, OCnC s do b nh thi iu khin. Tuy nhin ch l bit ca thanh ghi DDR tng ng vi cc chn OCnA, OCnB, OCnC phi c set cho php ng ra. Khi OCnA, OCnB, OCnC c kt ni ti chn th tc dng ca cc bit COMnX1:0 cn ph thuc vo la chn ca cc bit WGM3:0, ngha l khi ta set mt hay c hai Bit COMn1:0 ln 1 th chc nng ng ra so snh c u tin, tuy nhin cch hot ng ng ra OCnX nh th no th cn ph thuc vo vic la chn ca cc bit WGMn3:0, c th hin trong cc bng di (Bng 58, 59, 60). Trong cc ch PWM, khi gi tr cc thanh ghi dng so snh (OCRnX, ICRn) c gi tr bng vi TOP, th s kin so snh khp (compare match) b b qua. Tuy vy cc chn OCnX vn b set hay xa (ty vo cc bit COMnX 1:0) BOTTOM.
Bng 58. Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) ph thuc vo cc thit lp ca cc bit COMnA1:0, COMnB1:0, COMnC1:0 trong ch non-PWM
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Bng 59. Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) ph thuc vo cc thit lp ca cc bit COMnA1:0, COMnB1:0, COMnC1:0 tromg ch Fast-PWM
Bng 60. Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) ph thuc vo cc thit lp ca cc bit COMnA1:0, COMnB1:0, COMnC1:0 tromg ch PWM hiu chnh pha v tn s
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Bit 1:0 WGMn1:0: Waveform Generation Mode : Kt hp vi cc bit WGMn3:2 tm trong thanh ghi TCCRnB , nhng bit ny cho php ta la chn ch thc thi ca b nh thi, nh c th iu khin vic m tun t ca b m. Gi tr b m ln nht l TOP v dng sng to ra chn OCnX (X=A, B, C; n=1, 3) c s dng cho nhiu mc ch khc nhau (bng 61). Cc ch thc thi c h tr bi khi Timer/counter l : Normal mode ( counter ), Clear Timer on Compare match (CTC) mode , PWM mode. l vi b nh thi 1 th c 4 bit WGM l: WGM13, WGM12,WGM11 v WGM10.
Bng 61. La chn cc ch thc thi ca b nh thi 1(3) 2. Thanh ghi TCCR1B
Bit 7 ICNCn: Input Capture Noise Canceler Bit 6 ICESn: Input Capture Edge Select Bit 5 Reserved Bit
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Bit 4:3 WGMn3:2: Waveform Generation Mode Bit 2:0 CSn2:0: Clock Select Bit 7 ICNCn: Input Capture Noise Canceler (vit tt: ICNC): Vic set bit ny ti 1 s kch hot chc nng chng nhiu ca b chng nhiu li vo ( ICNC ). Khi chc nng ICNC c kch hot th ng vo t chn ICPn s c lc. Chc nng lc i hi 4 mu c gi tr bng nhau lin tip chn ICPn cho s thay i ng ra ca n ( xem chi tit v khi Input Capture ). Bit 6 ICESn: Input Capture Edge Select: Bit ny la chn cnh chn Input Capture Pin (ICPn) dng bt s kin trigger ( Trigger event (10) ). Khi bit ICESn c thit lp thnh 0 th mt cnh dng xung ( falling (3) ) c dng nh mt trigger ( tn hiu ny). Ngc li, khi bit ny c set thnh 1 th mt cnh m ln (rising (4) ) c dng nh mt trigger. Khi xy ra s kin Input capture (2) (theo thit lp ca bit ICESn l 1 hay 0) th gi tr ca b m c ghi vo thanh ghi Input Capture Register ICRn (n=1, 3), v khi c ICFn (Input Capture Flag) c set. iu ny s to ra mt ngt Input capture nu ngt ny c cho php. Khi thanh ghi ICRn c s dng nh mt gi tr TOP th chn ICPn khng c kt ni v v th chc nng Input capture khng c cho php. Bit 5 : D tr. Bit 4:3 WGMn3:2: Waveform Generation Mode: ni phn thanh ghi TCCR1A. Bit 2:0 CSn2:0: Clock Select : Dng la chn tc xung clock (xem bng 62). cm b nh thi hot ng ta ch cn cho {CSn2, CSn1, CSn0} = {0, 0, 0}.
Bng 62. La chn tc xung clock
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3. Thanh ghi TCCR1C
Bit 7 FOCnA: Force Output Compare for Channel A Bit 6 FOCnB: Force Output Compare for Channel B Bit 5 FOCnC: Force Output Compare for Channel C Bit 4:0 Reserved Bits Cc bit FOCnA/FOCnB/FOCnC ch hot ng khi cc bit WGMn3:0 ch nh ch Non-PWM. Khi cc bit FOCnA/FFOCnB/FOCnC c set thnh 1 th ngay lp tc mt s kin So snh khp cng ch (Forced Compare Match (1) ) xy ra trong b to sng. Ng ra OCnA/OCnB/OCnC c thay i theo thit lp ca cc bit COMnX 1:0 (n=1, 3; X=A, B, C), ngha l bnh thng s kin so snh khp ch xy ra khi khi gi tr b nh thi (thanh ghi TCNTn (n=1, 3) ) bng vi gi tr thanh ghi OCRnX( n=1,3; X=A,B,C), nhng khi cc bit FOCnX( n=1, 3; X=A, B, C) c set thnh 1 th s kin so snh khp s xy ra mc d gi tr ca b nh thi khng bng vi gi tr ca thanh ghi OCRnX( n=1,3; X=A,B,C). Ch l cc bit FOCnA/FOCnB/FOCnC cng hot ng nh l nhng que d (strobe), v th n l gi tr hin thi ca cc bit COMnX1:0 xc nh tc ng ca so snh cng ch (forced compare). Cc que d FOCnA/FOCnB/FOCnC khng to ra bt k ngt no v cng khng xa b nh thi trong ch CTC s dng thanh ghi OCRnA nh l gi tr TOP. Cc bit FOCnA/FOCnB/FOCnC ch c th ghi, khi c cc bit ny ta lun nhn c gi tr 0. Bit 4:0 d tr ,phi ghi thnh 0 khi ghi vo thanh ghi TCCRnC. 4. Thanh Ghi Timer/Counter1 TCNT1H and TCNT1L
Thanh ghi b nh thi TCNT1 l thanh ghi 16 bit c kt hp t hai thanh ghi TCNT1H v thanh ghi TCNT1L. Thanh ghi TCNT1 c th c hay ghi. c 2 byte ca TCNT 1 c c hay ghi ng thi ngi ta dng mt thanh ghi tm 8 bit byte cao 8-bit Temporary High Byte Register (TEMP). Thanh ghi TEMP c chia s cho tt c cc thanh ghi 16 bit khc. Khng nn chnh sa thanh ghi TCNTn (n=1,3) khi n ang m trnh b hng Compare Match gia TCNTn v mt trong nhng thanh ghi OCRnX(n=1,3. X=A,B,C).
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5. Thanh Ghi Output Compare Register 1 A OCR1AH and OCR1AL
6. Thanh Ghi Output Compare Register 1 B OCR1BH and OCR1BL
7. Thanh Ghi Output Compare Register 1 C OCR1CH and OCR1CL
Thanh ghi output compare register (OCR1A/OCR1B/OCR1C) l thanh ghi 16 bit, gi tr ca n c lin tc so snh vi b m (TCNT1). Khi c s bng nhau ca hai thanh ghi ny s to ra mt ngt so snh hay mt dng sng chn ng ra so snh OCnX (X=A,B,C). Ging nh thanh ghi TCNT1 , thanh ghi OCRnX (X=A,B,C) cng l thanh ghi 16 bit nn c hai byte cao v thp ca thanh ghi c ghi hay c ng thi khi CPU cn truy xut thanh ghi ny, ngi ta dng thanh ghi tm byte cao (TEMP), thanh ghi TEMP lun lu gi byte cao ca cc thanh ghi 16 bit khi cc thanh ghi ny cn dng ti n (xem hnh 3.1). Ch l khi ghi mt gi tr vo thanh ghi OCRnX trong lc b m ang chy, th gi tr ca thanh ghi OCRnX c th cp nht tc thi, nhng cng c th ch c cp nht khi b m t ti mt gi tr no (bng 61), chn hn, gi tr TOP, BOTTOM
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Hnh 3.1. Thanh ghi TEMP 8. Thanh Ghi Input Capture Register 1 ICR1H and ICR1L
Thanh ghi Input capture (ICR1n) s cp nht gi tr ca b m TCNTn mi khi xy ra s kin chn ICPn. Ngoi ra thanh ghi ny cn c s dng nh ngha gi tr TOP ca b m. Ngi ta cng s dng thanh ghi TEMP khi cn truy xut thanh ghi ICRn (n=1, 3). 9. Thanh Ghi Timer/Counter Interrupt Mask Register TIMSK (Interrupt for Timer/counter 1)
Bit 5 TICIE1: Timer/Counter1, Input Capture Interrupt Enable Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable
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Bit 5 TICIE1: Timer/Counter1, Input Capture Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt bt mu ng vo b Timer/couter1 (Timer/Counter1 Input Capture interrupt) c cho php. Vector ngt tng ng s c thc thi khi c ICF1 trong thanh ghi TIFR c set. Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 1A (Timer/Counter1 Output Compare A Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF1A trong thanh ghi TIFR c set. Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 1B (Timer/Counter1 Output Compare B Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF1B trong thanh ghi TIFR c set. Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt c trn b nh thi 1 (Timer/Counter1 overflow interrupt) c cho php. Vector ngt tng ng s c thc thi khi c TOV1 trong thanh ghi TIFR c set. 10. Thanh Ghi Extended Timer/Counter Interrupt Mask Register ETIMSK (Interrupt for Timer/counter 3)
Bit 7:6 Reserved Bits Bit 5 TICIE3: Timer/Counter3, Input Capture Interrupt Enable Bit 4 OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable Bit 3 OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable Bit 2 TOIE3: Timer/Counter3, Overflow Interrupt Enable Bit 1 OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable Bit 0 OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable Thanh ghi ETIMSK lin quan n c hai b nh thi 1 v 3. Bit 7:6 Reserved Bits: D tr , phi ghi cc bit ny thnh 0 khi ghi vo thanh ghi ETIMSK Bit 5 TICIE3: Timer/Counter3, Input Capture Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt bt mu ng
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vo b Timer/couter 3 (Timer/Counter3 Input Capture interrupt) c cho php. Vector ngt tng ng s c thc thi khi c ICF3 trong thanh ghi ETIFR c set. Bit 4 OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 3A (Timer/Counter1 Output Compare A Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF3A trong thanh ghi ETIFR c set. Bit 3 OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 3B (Timer/Counter3 Output Compare B Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF3B trong thanh ghi ETIFR c set. Bit 2 TOIE3: Timer/Counter3, Overflow Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt c trn b nh thi 3 (Timer/Counter3 overflow interrupt) c cho php. Vector ngt tng ng s c thc thi khi c TOV4 trong thanh ghi ETIFR c set. Bit 1 OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 3C (Timer/Counter3 Output Compare C Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF3C trong thanh ghi ETIFR c set. Bit 0 OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable: Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 1C (Timer/Counter1 Output Compare C Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF1C trong thanh ghi ETIFR c set. 11. Thanh Ghi Timer/Counter Interrupt Flag Register TIFR
Bit 5 ICF1: Timer/Counter1, Input Capture Flag Bit 4 OCF1A: Timer/Counter1, Output Compare A Match Flag Bit 3 OCF1B: Timer/Counter1, Output Compare B Match Flag Bit 2 TOV1: Timer/Counter1, Overflow Flag Thanh ghi TIFR lin quan ti b nh thi 1 v 2.
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Bit 5 ICF1: Timer/Counter1, Input Capture Flag: C ny c set khi xy ra s kin bt mu ng vo (Input Capture) ca chn ICP1. Khi thanh ghi ICR1 (Input Capture Register) c thit lp bi cc bit WGMn3:0 s dng nh mt gi tr TOP th c ICF1 s c set khi b m t ti gi tr TOP. C ICF1 s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 4 OCF1A: Timer/Counter1, Output Compare A Match Flag: C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1A (Output Compare Register A). Ch l mt so snh cng bc (FOC1A) s khng set c ny. C OCF1A s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 3 OCF1B: Timer/Counter1, Output Compare B Match Flag: C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1B (Output Compare Register B). Ch l mt so snh cng bc (FOC1B) s khng set c ny. C OCF1B s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 2 TOV1: Timer/Counter1, Overflow Flag: Vic thit lp c ny ph thuc vo thit lp ca cc bit WGMn3:0, trong ch bnh thng v CTC c TOV1 c set khi b nh thi trn. Xem li bng 61 v mc Cc ch thc thi bit cc trng hp khc. 12. Thanh Ghi Extended Timer/Counter Interrupt Flag Register ETIFR
Bit 7:6 Reserved Bits Bit 5 ICF3: Timer/Counter3, Input Capture Flag Bit 4 OCF3A: Timer/Counter3, Output Compare A Match Flag Bit 3 OCF3B: Timer/Counter3, Output Compare B Match Flag Bit 2 TOV3: Timer/Counter3, Overflow Flag Bit 1 OCF3C: Timer/Counter3, Output Compare C Match Flag Bit 0 OCF1C: Timer/Counter1, Output Compare C Match Flag Bit 7:6 Reserved Bits: D tr, phi ghi 0 khi ghi vo thanh ghi ETIFR. Bit 5 ICF3: Timer/Counter3, Input Capture Flag: C ny c set khi xy ra s kin bt ng vo (Input Capture) ca chn ICP3. Khi thanh ghi ICR3 (Input Capture Register) c thit lp bi cc bit WGMn3:0 s dng nh mt gi tr TOP th c ICF3
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s c set khi b m t ti gi tr TOP. C ICF3 s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 4 OCF3A: Timer/Counter3, Output Compare A Match Flag: : C ny c set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3A (Output Compare Register A). Ch l mt so snh cng bc (FOC3A) s khng set c ny. C OCF3A s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 3 OCF3B: Timer/Counter3, Output Compare B Match Flag: C ny c set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3B (Output Compare Register B).Ch l mt so snh cng bc (FOC3B) s khng set c ny. C OCF3B s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 2 TOV3: Timer/Counter3, Overflow Flag: Vic thit lp c ny ph thuc vo thit lp ca cc bit WGMn3:0, trong ch bnh thng v CTC c TOV3 c set khi b nh thi trn. Xem li bng 52 v mc Cc ch thc thi bit cc trng hp khc. Bit 1 OCF3C: Timer/Counter3, Output Compare C Match Flag: C ny c set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3C (Output Compare Register C). Ch l mt so snh cng bc (FOC3C) s khng set c ny. C OCF3C s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 0 OCF1C: Timer/Counter1, Output Compare C Match Flag: C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1C (Output Compare Register C). Ch l mt so snh cng bc (FOC1C) s khng set c ny. C OCF1C s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. 13. Thanh Ghi Special Function IO Register SFIOR
Bit 7 TSM: Timer/Counter Synchronization Mode Bit 0 PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
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Bit 7 TSM: Timer/Counter Synchronization Mode: Ghi bit ny thnh 1 s kch hot ch ng b b nh thi. Trong ch ny gi tr ghi vo hai bit PSR0 v PSR321 c gi, v th n gi cho tn hiu reset ca b chia trc ( prescaler (8) ) tng ng c xc nhn ( do b chia trc prescaler vn trng thi Reset ). iu ny chc chn l cc b Timer/couter tng ng c tm dng c th c cu hnh vi gi tr nh nhau m khng lm hng cc cu hnh sn c khc. Khi TMS l 0 th cc bit PSR0 v PSR321 c xa bi phn cng v cc b nh thi (1,2,3) bt u m ng thi. ( Xem thm mc : Ch ng B B nh Thi ). Bit 0 PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1: Khi bit ny l 1 th b chia trc (prescaler) ca ba b nh thi 1,2,3 c reset. Bit PSR321 c xa bi phn cng ngoi tr trng hp bit TSM c set. Ch l ba b nh thi 1, 2, 3 cng chia s mt b chia trc (prescaler) nn vic reset b chia trc (prescaler) s tc ng ln c ba b nh thi ny.
II. B NH THI 3
B nh thi 3 ging b nh thi 1 nn y ch trnh by cc thanh ghi lin quan ti b nh thi 3, chc nng ca tng thanh ghi c th xem cc thanh ghi tng ng vi n b nh thi 1. 1. Thanh ghi TCCR3A (Timer/Counter3 Control Register A)
Bit 7:6 COM3A1:0: Compare Output Mode for Channel A Bit 5:4 COM3B1:0: Compare Output Mode for Channel B Bit 3:2 COM3C1:0: Compare Output Mode for Channel C Bit 1:0 WGMn1:0: Waveform Generation Mode 2. Thanh ghi TCCR3B (Timer/Counter3 Control Register B) l khi Input Capture Unit ca b nh thi 3 c khc cht t so vi ca b nh thi 1. Xem chi tit v khi Input Capture Unit phn m t Khi Input Capture Unit.
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Bit 7 ICNC3: Input Capture Noise Canceler Bit 6 ICES3: Input Capture Edge Select Bit 5 Reserved Bit Bit 4:3 WGM3 3:2: Waveform Generation Mode Bit 2:0 CS3 2:0: Clock Select 3. Thanh ghi TCCR3C (Timer/Counter3 Control Register C)
Bit 7 FOC3A: Force Output Compare for Channel A Bit 6 FOC3B: Force Output Compare for Channel B Bit 5 FOC3C: Force Output Compare for Channel C Bit 4:0 Reserved Bits 4. Thanh Ghi Timer/Counter1 TCNT3H and TCNT3L
5. Thanh Ghi Output Compare Register 3 A OCR3AH and OCR3AL
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6. Thanh Ghi Output Compare Register 3 B OCR3BH and OCR3BL
7. Thanh Ghi Output Compare Register 3C OCR3CH and OCR3CL
8. Thanh Ghi Input Capture Register 3 ICR3H and ICR3L
9. Thanh Ghi Extended Timer/Counter Interrupt Mask Register ETIMSK (Interrupt for Timer/counter 3) l b nh thi 1 c s dng thanh ghi TIMSK v ETIMSK , cn b nh thi 3 ch s dng thanh ghi ETIMSK.
10. Thanh Ghi Extended Timer/Counter Interrupt Flag Register ETIFR l b nh thi 1 s dng c 2 thanh ghi TIFR v ETIFR , cn b nh thi 3 ch s dng thanh ghi TIFR.
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11. Thanh Ghi Special Function IO Register SFIOR
12. Ng Ra Khi Compare Match Output Unit
Hnh 3.2. Ng ra khi Compare Match Output Unit
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Nhn hnh 3.2 trn ta thy Pin OCnX (chn hn pin 15 ca IC tng ng vi OC1A), l ng ra ca khi Compare Match Output Unit, c th c ni vi 3 thanh ghi l OCnX, PortX v DDRX . Thanh ghi no c ni vi OCn l ph thuc vo cc bit COMn1:0 (tc ty theo ch hot ng ca b nh thi), gi s ta thit lp cc bit COMn1:0 cho thanh ghi OCn c ni vi PIN OCn, th hot ng ca PIN OCn (tc dng sng ng ra OCn ) li ph thuc vo thit lp ca cc bit WGMn3:0, cc bit WGMn3:0 s qui nh dng sng ng ra ti OCn nh th no (xem bng 61 ). Ngc li, nu ta thit lp b nh thi hot ng ch bnh thng (tc khng s dng chc nng so snh khp th chn OCn tr thnh chn vo ra s thng thng . Ng ra khi Compare Match Output Unit ca b nh thi 1 cng ging nh b nh thi 3.
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III. B NH THI 0
S khi b nh thi 0
B nh thi 0 l b nh thi 8 bit, b nh thi 0 lin quan ti 7 thanh ghi vi nhiu ch thc thi khc nhau. CC NH NGHA: Cc nh ngha sau s c s dng cho b nh thi 0 v 2: BOTTOM B m t ti gi tr BOTTOM khi n c gi tr 00h. MAX B m t ti gi tr MAX khi n bng FFh. TOP B m t gi tr TOP khi n bng vi gi tr cao nht trong chui m, gi tr cao nht trong chui m khng nht thit l FFh m c th l bt kh gi tr no c qui nh trong thanh ghi OCRn (n=0,2), ty theo ch thc thi. B nh thi 0 c vi c im chnh nh: B m n knh, xa b nh thi khi c s kin so snh khp (compare match) v t np li, c th m t b dao ng 32 KHz bn ngoi, ch PWM hiu chnh pha,Di y l m t chc nng ca cc thanh ghi lin quan ti b nh thi 0.
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1. Thanh Ghi Timer/Counter Control Register TCCR0
Bit 7 FOC0: Force Output Compare ( 6 ) Bit 6, 3 WGM01:0: Waveform Generation Mode Bit 5:4 COM01:0: Compare Match Output Mode Bit 2:0 CS02:0: Clock Select Bit 7 FOC0: Force Output Compare: Bit ny ch hot ng khi cc bit WGM ch nh ch non-PWM ( chn hn ch CTC,). Khi ch PWM nn ghi bit ny thnh 0. ch non-PWM, khi bit FOC0 c ghi thnh 1 lp tc mt s kin so snh khp cng bc ( Force compare match ) xy ra b to sng, tc l s kin so snh khp b bt buc xy ra mt d gi tr b nh thi khng bng vi gi tr ghi sn trong thanh ghi OCR0. Lc ny ng ra OC0 s thay i ty theo thit lp ca nhng bit COM01:0 tng ng vi n. Bit FOC0 s t ng xa bi phn cng sau 1 chu k clock. Bit ny khng th c. Bit 6, 3 WGM01:0: Waveform Generation Mode : Nhng bit ny iu khin cc ch thc thi ca b m, theo dng sng tng ng c to ra t b to sng. Cc ch thc thi c h tr l : Normal, CTC, PWM. C th xem bng 52.
Bng 52. La chn cc ch thc thi ca b nh thi 0. (1): Tn cc bit CTC0 v PWM0 khng c s dng na v c thay th bng cc tn khc l WGM01 v WGM00. Khi lp trnh nn ch iu ny. Bit 5:4 COM01:0: Compare Match Output Mode : Hai bit ny iu khin hnh vi ca chn OC0. Nu mt trong hai bit ny c set thnh 1 th ng ra OC0 c u tin hn chc nng I/O thng thng. Ch l cc bit tng ng ca OC0 trong thanh ghi DDR phi c set cho php ng ra. Khi bit OC0 c kt ni vi chn ng ra OC0 th
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tc ng ca cc bit COM01:0 i vi hnh vi ca chn OC0 cn ph thuc vo cc thit lp ca cc bit WGM01:0. Chi tit xem bng 53, 54, 55. Chn hn, khi ta set bit { WGM00, WGM01, COM00, COM01} = { 0, 0, 1, 0 } th b nh thi 0 s hot ng ch Normal v ch ny hnh vi ca chn OC0 l: OC0 s thay i mc logic mi khi c s kin So snh khp ( Compare match ). l ch Normal, vi thit lp cc bit WGM00, WGM01, COM00, COM01nh trn, gi tr thanh ghi OCR0 c cp nht ngay tc thi, khc vi ch PWM gi tr thanh ghi OCR0 ch c cp nht khi b nh thi m ti gi tr TOP (gi nh trong on chng trnh ng dng c s thay i gi tr thanh ghi OCR0). on chng trnh sau s thit lp b nh thi hot ng ch CTC v set chn OC0 ln 1 mi khi c s kin so snh. ldi r17,0xFF out DDRB,r17 ldi r16,0xF0 out OCR0,r16 ldi r16,0x39 out TCCR0,r16 ; configured as output
; match value ; CTC mode
Bng 53. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch non-PWM
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Bng 55. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch PWM hiu chnh pha
Bng 54. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch PWM nhanh Ch (1): C trng hp t bit l khi thanh ghi OCR0 c gi tr l TOP v bit COM01 c set , trong trng hp ny vic so snh khp (Compare match) b b qua, nhng vic set hay xa OC0 TOP vn c thc hin. Bit 2:0 CS02:0: Clock Select: y l 3 bit dng la chn xung clock cho b nh thi. Xem Bng 56. dng b nh thi ta chn { CS00, CS01, CS02 } = {0, 0, 0 }.
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Bng 56. La chn tc xung clock cho b nh thi 0 2. Thanh Ghi Timer/Counter Register TCNT0
y l thanh ghi m 8 bit ca b nh thi 0 .Gi tr thanh ghi ny tng hoc gim 1 n v sau mi chu k clock. Khng nn ghi vo thanh ghi ny khi n ang m. 3. Thanh Ghi Output Compare Register OCR0
OCR0 l thanh ghi 8 bit, gi tr ca n c lin tc so snh vi gi tr ca thanh ghi TCNT0. Khi hai gi tr ca hai thanh ghi ny bng nhau th xy ra mt s kin so snh khp (compare match). S kin so snh khp s to ra mt ngt, nu ngt c cho php. Hay to ra mt dng sng chn ng ra OC0, ty theo ch thc thi ca b nh thi.
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4. Thanh Ghi Timer/Counter Interrupt Mask Register TIMSK
Bit 1 OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable Bit 1 OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable: Khi bit OCIE0 ghi l 1 v bit I ca thanh ghi trng thi SREG c set thnh 1 th ngt s kin so snh khp (compare match interrupt ) c cho php. Khi mt ngt s c thc thi khi xy ra mt s kin so snh khp. Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable: Khi bit ny c ghi l 1 v ngt ton cc c cho php th ngt trn b nh thi (Timer/Counter0 Overflow interrupt) c cho php. Khi mt ngt tng ng s c thc thi khi b nh thi trn. 5. Thanh Ghi Timer/Counter Interrupt Flag Register TIFR
Bit 1 OCF0: Output Compare Flag 0 Bit 0 TOV0: Timer/Counter0 Overflow Flag Bit 1 OCF0: Output Compare Flag 0: Bit ny s c set ln 1 khi xy ra so snh khp (compare match) gia b nh thi (tc thanh ghi TCCN0) vi thanh ghi OCR0. C OCF0 s t ng xa khi ngt tng ng c thc thi. Ngoi ra ta cng c th xa c OCF0 bng cch ghi mt gi tr logic vo n. Khi bit I trong thanh ghi SREG, bit OCIE0 (Timer/Counter0 Compare Match Interrupt Enable) v bit OCF0 c set ln 1 th ngt so snh khp (Compare Match Interrupt) s c thc thi. Bit 0 TOV0: Timer/Counter0 Overflow Flag: Bit TOV0 c set thnh 1 khi b nh thi trn v n c xa khi ngt tng ng c thc thi. Ngoi ra cng c th xa bng cch ghi mt gi tr logic vo v tr ca n . Khi bit I trong thanh ghi SREG, bit TOIE0 (Timer/Counter0 Overflow interrupt) v bit TOV0 c set ln 1 th ngt trn b nh thi 0 (Timer/Counter0 Overflow Interrupt ) s c thc thi. Trong ch PWM c TOV0 c Set khi b nh thi 0 i hng m ti gi tr 00h.
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6. Thanh Ghi Special Function IO Register SFIOR
Bit 7 TSM: Timer/Counter Synchronization Mode Bit 1 PSR0: Prescaler Reset Timer/Counter0 Bit 7 TSM: Timer/Counter Synchronization Mode: Ghi bit ny thnh 1 s kch hot ch ng b b nh thi (Timer/Counter Synchronization). Trong ch ny, mt gi tr c ghi vo cc bit PSR0 v PSR321 s c gi li, v th n gi cho tn hiu reset ca b chia trc (prescaler) tng ng c xc nhn ( do b chia trc (prescaler) vn trng thi Reset ). iu ny l chc chn l cc b nh thi tng ng s c tm ngh v c th c cu hnh vi cc gi tr nh nhau m khng lm nh hng n mt trong nhng cu hnh nng cao khc ca chng. Khi bit ny c ghi thnh 0 th cc b nh thi s bt u m ng thi. Bit 1 PSR0: Prescaler Reset Timer/Counter0: Khi bit ny l 1 th b chia trc ca b nh thi 0 (Timer/couter 0 prescaler) s c t li. Bit ny thng c xa tc thi bi phn cng. Nu bit ny c ghi khi b nh thi 0 ang thc thi ch khng ng b th n vn gi nguyn gi tr ca n cho n khi b chia trc c t li. Bit ny s khng c xa bi phn cng nu nh bit TSM c set thnh 1. 7. Thanh Ghi Asynchronous Status Register ASSR
Bit 3 AS0: Asynchronous Timer/Counter0 Bit 2 TCN0UB: Timer/Counter0 Update Busy Bit 1 OCR0UB: Output Compare Register0 Update Busy Bit 0 TCR0UB: Timer/Counter Control Register0 Update Busy Bit 3 AS0: Asynchronous Timer/Counter0: Khi bit AS0 l 0 th b nh thi c m t ngun xung clock I/O, tc ClkI/O. Khi AS0 c ghi thnh 1 b nh thi
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c m t xung thch anh chn TOSC1. Khi gi tr ca AS0 b thay i th ni dng ca cc thanh ghi TCNT0, OCR0 v TCCR0 c th b hng. Bit 2 TCN0UB: Timer/Counter0 Update Busy: Khi b nh thi 0 thc thi qu trnh khng ng b v thanh ghi TCNT0 ang c ghi th bit TCN0UB s set ln 1. Khi thanh ghi TCNT0 va c cp nht t thanh ghi lu tr tm th bit ny b xa bi phn cng. Mc logic 0 trong trng hp ny l ch ra rng thanh ghi TCNT0 sn sng cp nht mt gi tr mi. Bit 1 OCR0UB: Output Compare Register0 Update Busy: Khi b nh thi 0 thc thi qu trnh khng ng b v thanh ghi OCR0 ang c ghi th bit OCR0UB s set ln 1. Khi thanh ghi OCR0 va c cp nht t thanh ghi lu tr tm th bit ny b xa bi phn cng .Mc logic 0 trong trng hp ny l ch ra rng thanh ghi OCR0 sn sng cp nht mt gi tr mi. Bit 0 TCR0UB: Timer/Counter Control Register0 Update Busy: Khi b nh thi 0 thc thi qu trnh khng ng b v thanh ghi TCCR0 ang c ghi th bit TCR0UB s set ln 1. Khi thanh ghi TCCR0 va c cp nht t thanh ghi lu tr tm th bit ny b xa bi phn cng. Mc logic 0 trong trng hp ny l ch ra rng thanh ghi TCCR0 sn sng cp nht mt gi tr mi. Nu ghi vo mt trong ba thanh ghi ca b nh thi 0 (TCNT0, OCR0, TCCR0) trong lc c bo bn cp nht (update busy flag) ca chng c set, th gi tr cp nht c th b hng v s to ra mt ngt khng bit trc.
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IV. B NH THI 2
S khi b nh thi 2
B nh thi 2 l b nh thi 8 bit, b nh thi 2 lin quan ti 5 thanh ghi vi nhiu ch thc thi khc nhau. Cc thuc tnh chnh ca b nh gm: B m n knh, xa b nh thi khi c s kin so snh khp v t ng np li, PWM hiu chnh pha, m s kin bn ngoi Cc Thanh Ghi B nh Thi 2. 1. Thanh ghi Timer/Counter Control Register TCCR2
Bit 7 FOC2: Force Output Compare Bit 6, 3 WGM21:0: Waveform Generation Mode
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Bit 5:4 COM21:0: Compare Match Output Mode Bit 2:0 CS22:0: Clock Select Bit 7 FOC2: Force Output Compare : Bit FOC2 ch hot ng khi bit WGM20 ch nh ch Non-PWM, trong ch PWM nn ghi bit ny thnh 0. ch non-PWM, khi bit FOC0 c ghi thnh 1 lp tc mt so snh khp (compare match ) xy ra b to sng, ng ra OC2 thay i ty theo thit lp ca nhng bit COM21:0 tng ng vi n. Bit ny khng th c, khi c ta lun nhn gi tr 0. Bit ny hot ng ging nh bit FOC0 ca b nh thi 0. Bit 6, 3 WGM21:0: Waveform Generation Mode : Nhng bit ny iu khin cc ch thc thi ca b m, theo dng sng tng ng c to ra t b to sng. Cc ch thc thi c h tr l : Normal, CTC, PWM. Xem bng 64.
Bng 64. La chn cc ch thc thi ca b nh thi 2 Ch : Tn cc bit CTC2 v PWM2 khng c s dng na v c thay th bng cc tn khc l WGM21 v WGM20. Bit 5:4 COM21:0: Compare Match Output Mode: Hai bit ny iu khin hot ng ca chn OC2. Nu mt trong hai bit ny c set thnh 1 th ng ra OC2 c u tin hn chc nng I/O thng thng . Ch l cc bit tng ng ca OC2 trong thanh ghi DDR phi c set cho php ng ra. Khi OC2 c kt ni vi chn ng ra OC2 th vai tr ca cc bit COM21:0 cn ph thuc vo cc thit lp ca cc bit WGM21:0. Chi tit xem bng 65, 66, 67. Cc bit ny hot ng ging vi cc bit COM01:0 ca b nh thi 0. Xem li b nh thi 0.
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Bng 65. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch non-PWM
Bng 66. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch PWM nhanh
Bng 67. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch PWM hiu chnh pha
Ch : C trng hp t bit l khi thanh ghi OCR2 c gi tr l TOP v bit COM21 c set , trong trng hp ny s kin so snh khp (Compare match) b b qua, nhng vic set hay xa OC2 TOP vn c thc hin. Bit 2:0 CS22:0: Clock Select: Dng la chn ngun xung clock cho b nh thi 2. Xem chi tit bng 68.
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Bng 68. La chn tc xung clock cho b nh thi 0 : B nh thi 2 c th c m t ngun clock bn ngoi thng qua chn T2. Khi chuyn sang ngun clock ngoi, b m vn m bnh thng ngay c khi chn T2 c cu hnh l ng ra. 2. Thanh ghi Timer/Counter Register TCNT2
y l thanh ghi m 8 bit ca b nh thi 2. Gi tr thanh ghi ny tng hoc gim 1 n v sau mi chu kh clock. Thanh ghi TCNT2 c truy xut trc tip khi c hay ghi ( iu ny khc vi b nh thi 1 v 3 l khi truy xut cc thanh ghi TCNT1 hay TCNT3 cn phi thng qua thanh ghi tm trung gian 8 bit ). Khng nn chnh sa thanh ghi TCNT2 khi b nh thi ang chy. 3. Thanh ghi Output Compare Register OCR2
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Thanh ghi OCR2 l thanh ghi 8 bit, gi tr ca thanh ghi OCR2 s c lin tc so snh vi gi tr ca b m, tc thanh ghi TCNT2. Khi gi tr ca hai thanh ghi ny bng nhau s to ra s kin so snh khp ( Compare match). Mt ngt so snh khp ( compare match interrupt ) c th c to ra nu ngt c cho php, hay mt dng sng s c to ra chn OC2.Thanh ghi ny hot ng tng t nh thanh ghi OCR0 b nh thi 0. 4. Thanh ghi Timer/Counter Interrupt Mask Register TIMSK
Bit 7 OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable Bit 6 TOIE2: Timer/Counter2 Overflow Interrupt Enable Bit 7 OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable: Khi bit OCIE2 c set thnh 1 v bit I trong thanh ghi trng thi c set thnh 1 th ngt so snh khp (compare match interrupt ) ca b nh thi 2 c cho php. Khi mt ngt tng ng s c thc thi khi xy ra mt s kin so snh khp b nh thi 2. Chn hn, xy ra mt so snh khp (compare match ) b nh thi 2 ta c th set bit OCF2 trong thanh ghi TIFR, hoc l ch cho n khi no gi tr ca hai thanh ghi TCNT2 v OCR2 bng nhau th mt so snh khp (compare match ) s xy ra. Bit 6 TOIE2: Timer/Counter2 Overflow Interrupt Enable: Khi bit ny c ghi l 1 v ngt ton cc c cho php (bit I trong thanh ghi trng thi SREG c set thnh 1) th ngt trn b nh thi 2 (Timer/Counter2 Overflow interrupt) c cho php. Khi mt ngt tng ng s c thc thi khi b nh thi 2 trn. Chn hn, ta set bit TOV2 trong thanh ghi TIFR thnh 1 hoc l ch cho b nh thi 2 b trn khi vt qu gi tr TOP ( hay MAX ). 5. Thanh ghi Timer/Counter Interrupt Flag Register TIFR
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Bit 7 OCF2: Output Compare Flag 2 Bit 6 TOV2: Timer/Counter2 Overflow Flag Bit 7 OCF2: Output Compare Flag 2 : Bit ny s c set ln 1 khi xy ra s kin so snh khp (compare match) gia b nh thi 2 (tc thanh ghi TCCN2) vi thanh ghi OCR2. C OCF2 s t ng xa khi ngt tng ng c thc thi. Ngoi ra ta cng c th xa c OCF2 bng cch ghi mt gi tr logic vo n. Khi bit I trong thanh ghi SREG, bit OCIE2 (Timer/Counter2 Compare Match Interrupt Enable) v bit OCF2 c set ln 1 th ngt s kin so snh khp (Compare Match Interrupt) ca b nh thi 2 s c thc thi. Bit 6 TOV2: Timer/Counter2 Overflow Flag: Bit TOV2 c set thnh 1 khi b nh thi trn v n c xa khi ngt tng ng c thc thi. Ngoi ra cng c th xa bng cch ghi mt gi tr logic vo v tr ca n. Khi bit I trong thanh ghi SREG, bit TOIE2 (Timer/Counter2 Overflow interrupt) v bit TOV2 c set ln 1 th ngt trn b nh thi 2 (Timer/Counter2 Overflow Interrupt ) s c thc thi. Trong ch PWM c TOV2 c set khi b nh thi 2 i hng m ti gi tr 00h.
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Chng IV
CU TRC NGT CA ATmega128

I. KHI NIM V NGT
Ngt l mt s kin bn trong hay bn ngoi lm ngt b vi iu khin bo cho n bit rng thit b cn dch v ca n. Mt b vi iu khin c th phc v mt vi thit b, c hai cch thc hin iu ny l s dng cc ngt (interrupt) v thm d (polling). Trong phng php s dng cc ngt th mi khi c mt thit b bt k cn n dch v ca n th n bo cho b vi iu khin bng cch gi mt tn hiu ngt. Khi nhn c tn hiu ngt th b vi iu khin ngt tt c nhng g n ang thc hin chuyn sang phc v thit b. Chng trnh i cng vi ngt c gi l trnh dch v ngt ISR (Interrupt Service Routine) hay cn gi l trnh qun l ngt (Interrupt handler). Cn trong phng php thm d th b vi iu khin hin th lin tc tnh trng ca mt thit b cho v iu kin tho mn th n phc v thit b. Sau n chuyn sang hin th tnh trng ca thit b k tip cho n khi tt c u c phc v. Mc d phng php thm d c th th hin th tnh trng ca mt vi thit b v phc v mi thit b khi cc iu kin nht nh c tho mn nhng n khng tn dng ht cng dng ca b vi iu khin. im mnh ca phng php ngt l b vi iu khin c th phc v c rt nhiu thit b (tt nhin l khng ti cng mt thi im). Mi thit b c th nhn c s ch ca b vi iu khin da trn mc u tin c gn cho n. i vi phng php thm d th khng th gn mc u tin cho cc thit b v n kim tra tt c mi thit b theo kiu quay vng . Quan trng hn l trong phng php ngt th b vi iu khin cng cn c th che hoc lm l mt yu cu dch v ca thit b. iu ny li mt ln na khng th thc hin c trong phng php thm d. L do quan trng nht m phng php ngt c u chung nht l v phng php thm d lm hao ph thi gian ca b vi iu khin bng cch hi d tng thit b k c khi chng khng cn n dch v.
II. TRNH PHC V NGT V BNG VECTOR NGT

i vi mi ngt th phi c mt trnh phc v ngt ISR (Interrupt Service Routine) hay trnh qun l ngt (Interrupt handler). Khi mt ngt c gi th b vi iu khin phc v ngt. Khi mt ngt c gi th b vi iu khin chy trnh phc v ngt. i vi mi ngt th c mt v tr c nh trong b nh gi a ch ISR ca n. Nhm cc v tr nh c dnh ring gi cc a ch ca cc ISR c gi l bng vc t ngt.
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Khi kch hot mt ngt b vi iu khin i qua cc bc sau: Vi iu khin kt thc lnh ang thc hin v lu a ch ca lnh k tip (PC) vo ngn xp. N nhy n mt v tr c nh trong b nh c gi l bng vc t ngt ni lu gi a ch ca mt trnh phc v ngt. B vi iu khin nhn a ch ISR t bng vc t ngt v nhy ti . N bt u thc hin trnh phc v ngt cho n lnh cui cng ca ISR l RETI (tr v t ngt). Khi thc hin lnh RETI b vi iu khin quay tr v ni n b ngt. Trc ht n nhn a ch ca b m chng trnh PC t ngn xp bng cch ko hai byte trn nh ca ngn xp vo PC. Sau bt u thc hin cc lnh t a ch .
III. BNG VECTOR NGT CA ATmega128.

Di y l bng vc t ngt ca ATmega128 , cng vi a ch ca n trong b nh chng trnh ( bng 23 ).
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Bng 23. Bng Vector Ngt Ca ATmega128
IV. TH T U TIN NGT.

Khng nh vi iu khin h 8051, th t u tin ca cc ngt c th thay i c ( bng cch lp trnh ). Vi vi iu khin AVR th t u tin cc ngt l khng th thay i v theo qui tc: Mt vec t ngt c a ch thp hn trong b nh chng trnh c mc u tin cao hn . Chn hn ngt ngoi 0 ( INT0 ) c mc u tin cao hn ngt ngoi 1 ( INT1 ). cho php mt ngt ngi dng cn cho php ngt ton cc ( set bit I trong thanh ghi SREG ) v cc bit iu khin ngt tng ng. Khi mt ngt xy ra v ang c phc v th bit I trong thanh ghi SREG b xa, nh th khi c mt ngt khc xy ra n s khng c phc v, do cho php cc ngt
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trong khi mt ISR ( interrupt service routine ) khc ang thc thi, th trong chng trnh ISR phi c lnh SEI set li bit I trong SREG.
V. NGT TRONG NGT.

Khi AVR ang thc hin mt trnh phc v ngt thuc mt ngt no th li c mt ngt khc c kch hot. Trong nhng trng hp nh vy th mt ngt c mc u tin cao hn c th ngt mt ngt c mc u tin thp hn. Lc ny ISR ca ngt c mc (*) u tin cao hn s c thc thi . Khi thc hin xong ISR ca ngt c mc u tin cao hn th n mi quay li phc v tip ISR ca ngt c mc u tin thp hn trc khi tr v chng trnh chnh. y gi l ngt trong ngt. ( hnh 4.1 ).
Ngat 2 Ngat 1
Ngat 1
Chng Trnh Chnh Thi gian

Hnh 4.1. Cc ngt lng nhau
Chng Trnh Chnh
Ch : - Gi nh l khi mt ISR no ang thc thi th xy ra mt yu cu ngt t mt ISR khc c mc u tin thp hn th ISR c mc u tin thp hn khng c phc v, nhng n s khng b b qua lun m trng thi ch. Ngha l ngay sau khi ISR c mc u tin cao hn thc thi xong th n lt ISR c mc u tin thp hn s c phc v. - (*) : iu ny ch xy ra khi trong code ca ISR ca ngt c mc u tin thp hn c lnh set bit I trong thanh ghi SREG ( l lnh SEI ).
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VI. CC NGT NGOI.

ATmega128 c 8 ngt ngoi t INT0 n INT7 ( y cha k ti ngt reset ). Tm ngt ny tng ng vi 8 chn ca MCU l INT0 ,INT1, , INT7. l ngay c khi cc chn INT0, INT1, , INT7 ca MCU c cu hnh nh l chn li ra, th cc ngt ngoi vn c tc dng nu c cho php. Cc ngt ngoi c th bt mu theo kiu cnh ln ( Rising ), cnh xung ( Falling ) hay mc thp ( Low level ). iu ny c qui nh trong hai thanh ghi EICRA v EICRB. Di y l m t chi tit 2 thanh ghi EICRA v EICRB v cc thanh ghi lin quan ti cc ngt ngoi. 1. Thanh ghi External Interrupt Control Register A EICRA
Bits 7..0 ISC31, ISC30 ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
Tm bit ca thanh ghi EICRA s iu khin kiu bt mu cho 4 ngt INT3, INT2, INT1, INT0. Qui nh c th c th hin trong Bng 48 . ISCn1 ISCn0 0 0 1 1 Kiu bt mu
0 Mc thp s to yu cu ngt 1 D tr 0 Cnh xung ( Falling ) s to yu cu ngt 1 Cnh ln ( Rising ) s to yu cu ngt n = 3, 2, 1, 0 Bng 48 . iu khin kiu bt mu ngt
2. Thanh Ghi External Interrupt Control Register B EICRB
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Bits 7..0 ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits. Tm bit ca thanh ghi EICRA s iu khin kiu bt mu cho 4 ngt INT7, INT6, INT5, INT4. . Qui nh c th c th hin trong Bng 50 .
ISCn1 ISCn0 0 0 1 1 0 1 0 1
Kiu bt mu Mc thp s to yu cu ngt Bt c s thay i mc logic no chn INTn s tao ra mt yu cu ngt Cnh xung ( Falling ) gia hai mu s to yu cu ngt Cnh ln ( Rising ) gia hai mu s to yu cu ngt
n = 7,6, 5, 4 Bng 50 . iu khin kiu bt mu ngt 3. Thanh Ghi External Interrupt Mask Register EIMSK
Bits 7..0 INT7 INT0: External Interrupt Request 7 - 0 Enable : Khi cho php ngt ton cc ( set bit I trong thanh ghi SREG thnh 1 ) th cc ngt vn cha th thc thi, ngt c th thc thi ta cn phi cho php n, 8 bit trong thanh ghi EIMSK s quyt nh 8 ngt ngoi tng ng ( t INT7 ...INT0 ) c c cho php hay khng. Khi mt trong s 8 bit ( t INT7 ...INT0 ) c set thnh 1 v ngt ton cc c cho php th ngt ngoi tng ng c cho php. Cn tn hiu ngt l mc hay cnh s do cc thanh ghi
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EICRA v EICRB ( nu trn ) qui nh. Kch hot bt c chn ( Pin ) no trong 8 chn ca ngt ngoi cng to ra yu cu ngt ngay c khi chn c thit lp thnh ng ra. 4. Thanh Ghi External Interrupt Flag Register EIFR
Bits 7..0 INTF7 - INTF0: External Interrupt Flags 7 0 : y l tm c ngt tng ng vi tm ngt ngoi INT7..INT0. Khi c tn hiu yu cu ngt ngoi th c ngt tng ng s c set thnh 1, nu ngt tng ng c cho php th MCU s nhy ti bng vc t ngt, c ngt s c xa khi chng trnh phc v ngt ( ISR ) c thc thi. Ngoi ra ta cng c set hay xa c ngt bng cch ghi trc tip mt gi tr logic vo n. 5. Thanh Ghi MCU Control Register MCUCR
Trong phn ny ta ch quan tm ti hai bit l: IVCE (Interrupt Vector Select ) v bit IVSEL (Interrupt Vector Change Enable ) ca thanh ghi MCUCR. Bit ny lin quan n vic thit lp v tr bng vc t ngt. Bit 1 IVSEL: Interrupt Vector Select: Khi bit ny l 0 v tr ca bng vc t ngt c t phn u b nh chng trnh. Khi bit ny l 1 bng vc t ngt c di chuyn ti phn u ca vng nh Boot Loader. Bit 0 IVCE: Interrupt Vector Change Enable : Bit ny phi c ghi thnh 1 cho php thay i bit IVSEL. Bit IVCE c xa sau 4 chu k my sau khi n c set hay bit IVSEL c ghi. Trong lc bit ICVE ang set cc ngt s b cm cho ti khi bit IVSEL c ghi, nu bit IVSEL khng c ghi th cc ngt vn b cm trong 4 cho k my lin tip ( sau 4 chu k my th bit IVCE s t ng b xa nn cc ngt c cho php tr li ).
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Chng V
CC B PHN NGOI VI KHC

Ngoi cc b phn ngoi vi c gii thiu cc chng trc nh : B nh thi, cc cng vo ra, EEPROM Vi iu khin ATmega128 c c nhiu b phn ngoi vi khc, cc b ngoi vi ny rt tin li trong cc ng dng iu khin ( b PWM ), x l s liu ( b ADC, b so snh Analog ), giao tip ( b USART, SPI, I2C ) Vic tch hp cc b ngoi vi ny vo trong chip gip cho cc thit k tr nn thun tin hn, kch thc bo mch cng gn gng hn ...
I. B SO SNH TNG T
S n gin ca b so snh tng t ( Analog Comparator ) nh hnh 5.1. B so snh c hai ng vo tng t l AIN0 v AIN1 v mt ng ra s ACO. Nguyn tc hot ng ca b so snh tng t l : Khi ng vo AIN0 c in th cao hn ng vo AIN1 th ng ra ACO s mc cao ( tng ng vi logic 1 ), ngc li khi ng vo AIN0 c in th thp hn ng vo AIN1 th ng ra ACO s mc thp ( tng ng vi logic 0). Thng th trong hai ng vo, c mt ng vo c in th c gi c nh dng lm in th tham chiu ( VRef ), in th ng cn li c th thay i tham chiu vi ng vo VRef . Trng thi ca ng ra ACO ca b so snh c th c dng to ra mt ngt, kt ni ti b nh thi 1 s dng chc nng input capture ca b nh thi ny ( xem m t sau ).
AIN0 PBx
+
ACO Control Logic
Interrupt Flag
AIN1 PBy
To timer 1
Hnh 5.1. S gin lt ca b so snh tng t Cn ch l c s khc bit v chi tit b so snh tng t i vi cc dng AVR khc nhau, chn hn b so snh tng t ca AT90S8535 hi khc vi b so snh tng t ATmega128, tuy nhin cu trc c bn th vn nh nhau. Sau y l m t c th v b so snh tng t ca ATmega128.
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hnh 5.1 ta thy hai ng vo AIN0 v AIN1 tng ng vi hai chn PBx v PBy ( x = 2, y = 3 i vi AT90S8535 ), ATmega128 ta c nhiu la chn ng vo hn, cc thanh ghi lin quan s gip ta tht lp cc la chn ny.
1. Thanh ghi Special Function IO Register SFIOR
Bit 3 ACME: Analog Comparator Multiplexer Enable
thanh ghi ny ta ch s dng bit Bit 3 ACME , khi bit ny l 1 v chc nng ADC khng cho php hot ng ( bit ADEN trong thanh ghi ADCSRA l 0 ) th ng vo m ca b so snh tng t c th l 1 trong s 8 ng vo ADC ty theo thit lp ca cc bit MUX 2, MUX 1, MUX 0 ( xem bng 94 ), chn hn nu { ACME, ADEN, MUX 2, MUX 1, MUX 0 } = { 1, 0, 0, 0, 0 } th ng ADC0 ( tng ng vi chn s 61 ca vi iu khin ) c chn lm ng vo m. Nu bit ACME l 0 th ng vo m ca b so snh tng t l AIN1 ( tng ng vi chn s 5 ca vi iu khin ).
Bng 94. La chn li vo m

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2. Thanh ghi Analog Comparator Control and Status Register ACSR
Bit 7 ACD: Analog Comparator Disable Bit 6 ACBG: Analog Comparator Bandgap Select Bit 5 ACO: Analog Comparator Output Bit 4 ACI: Analog Comparator Interrupt Flag Bit 3 ACIE: Analog Comparator Interrupt Enable Bit 2 ACIC: Analog Comparator Input Capture Enable Bits 1, 0 ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
Bit 7 ACD: Analog Comparator Disable : Khi bit ny l 1 s khng cho php b so snh tng t hot ng. Khi bit ny l 0 b so snh tng t c php hot ng. Ta c th thay i bit ny bt c lc no cho php hay khng cho php b so snh tng t hot ng. Nhng cn ch l bt c s thay i no ca bit ACD cng c th to ra mt ngt (ngt ca b so snh tng t ), do nu khng cn thit ta nn cm ngt ca b so snh tng t bng cch xa bit ACIE ca thanh ghi ACSR. Bit 6 ACBG: Analog Comparator Bandgap Select : Khi bit ny l 1 ng vo dng s c gi mc in th c nh khong 1,23 V ( 250C v Vcc = 5 V ) v c dng lm in th tham chiu, gi l in th tham chiu ni ( Internal voltage reference ). Nh vy, trong trng hp ny ng vo m s thay i gi tr v tham chiu ti gi tr 1,23 V. Ch l khi ta s dng in th tham chiu ni 1,23 V nh nu trn th ta cn thit lp bit ACBG thnh 1 trc khi cho php b so snh tng t hot ng, bi v khi in th tham chiu ni c cho php n cn mt khong thi gian khi ng l 40 s c th n nh in th 1,23 V. Khi bit ny l 0 chn AIN0 ( tng ng vi chn s 4 ca vi iu khin ) tr thnh ng vo dng. Bit 5 ACO: Analog Comparator Output : Bit ny chnh l trng thi ng ra ca b so snh, c bit ny ta s bit c trng thi hin thi ca ng vo. Khi tng quan so snh hai ng vo thay i, cn t 1 ti 2 chu k my phn nh kt qu ny ng ra ACO. Bit 4 ACI: Analog Comparator Interrupt Flag : y l bit c ngt ca b so snh tng t, khi xy ra ngt b so snh tng t bit ny s c set ln 1 bi phn cng, trnh phc v ngt c thc thi nu ngt c cho php ( bng cch set bit ACIE trong ghi ACSR v bit I trong thanh ghi SREG ). Vc t ngt ca b so snh tng t c a ch l $002E. Bit ACI s c t ng xa bi phn cng khi trnh phc v ngt c thc thi. Ch : Bit ACI s t ng xa khi c bt c s thay i no ca thanh ghi ACSR. Chn hn khi ta ghi vo bit ny gi tr logic 1 th sau khi thc hin xong lnh
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ghi ta vn nhn c gi tr logic 0 bit ny . Do ta khng th no set c bit ny bng phn mm. Bit 3 ACIE: Analog Comparator Interrupt Enable : y l bit cho php ngt ca b so snh tng t. Khi bit ny l 1 th ngt b so snh tng t c cho php. Ngc li, khi bit ny l 0 th ngt b so snh tng t b cm. Bit 2 ACIC: Analog Comparator Input Capture Enable : bit ny lin quan ti tnh nng input capture ca b nh thi 1 ( xem li b nh thi 1 ). Khi bit ny l 1 ng ra ca b so snh c ni trc tip ti li vo ca khi input capture ca b nh thi 1, nh cch ny ta c th tn dng tnh nng kh nhiu ng vo input capture ca b nh thi 1, trong cch thit lp ny ngt input capture vn c th hot ng nu c cho php ( bng cch cho php ngt ton cc v set bit TICIE1 trong thanh ghi TIMSK ln 1 ). Khi bit ny l 0 ng ra ca b so snh tng t khng c kt ni vi ng vo ca khi input capture ca b nh thi 1. Bits 1, 0 ACIS1, ACIS0: Analog Comparator Interrupt Mode Select : Hai bit ny qui nh cch thc to ra ngt khi c s thay i trng thi ng ra ACO. Chn hn, khi ta thit lp { ACIS1, ACIS0 } = { 0, 0 } th khi c s thay i mc ( bao gm mc cao xung mc thp hoc mc thp ln mc cao ) ng ra ACO s to ra ngt. Cc thit lp khc c m t bng 93. ACIS1 0 0 1 1 ACIS0 0 1 0 1 M t Thay i mc to ra ngt Khng s dng ( d tr ) Cnh xung ng ra to ra ngt Cnh ln ng ra to ra ngt
Bng 93. Cc cch thc to ra ngt b so snh tng t Ch : Khi ta thay i mt trong hai ( hoc c hai ) bit ACIS1, ACIS0 c th to ra ngt ca b so snh tng t nu ngt c cho php. Do , nu khng cn thit ta nn cm ngt ca b so snh tng t trc khi thay i hai bit ny. Hnh 107 m t cu trc ca b so snh tng t ca ATmega128, ta c th phn tch hot ng ca b so snh tng t thng qua s ny. u tin l tn hiu ACBG ( nt s 1 ), khi ACBG l 1 chn AIN0 b cm, in th tham chiu ni ( nt s 9 ) i qua cng truyn hai chiu ti ng vo dng. Ngc li khi ACBG l 0 in th tham chiu ni b cm. Xt tn hiu ACME v ADEN ( nt s 2 ) hai tn hiu ny iu khin 2 cng truyn ni vi n cho php ng vo m l AIN1 hay cc chn ADC ( nt s 10 ). Tn hiu ACD
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( nt s 3 ) l 1 s cp ngun cho b so snh tng t hot ng, ngc li ngun nui ca b so snh tng t b ngt. Bn c c th t phn tch cc tn hiu cn li.
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Tm li lp trnh cho b so snh tng t ta thc hin cc bc sau: 1. Chn ng vo dng ( l in th tham chiu ni hay chn AIN0 ) bng cch thit lp bit ACBG. 2. Chn ng vo m ( l cc chn ADC hay chn AIN1 ) bng cch thit lp cc bit ACME v ADEN. 3. Chn kiu hot ng ca b so snh tng t nh: s dng ngt, kt ni ti b nh thi 1 4. Ghi bit ACD thnh 0 cho php b so snh tng t hot ng.
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II. B BIN I ADC 1. Gi Thiu B ADC Ca ATmega128.

B bin i ADC c chc nng bin i tn hiu tng t (analog signal) c gi tr thay i trong mt di bit trc thnh tn hiu s (digital signal). B ADC ca ATmega128 c phn gii 10 bit, sai s tuyt i 2 LSB, di tn hiu ng vo t 0v VCC, tn hiu ng vo c nhiu la chn nh : c 8 ng vo a hp n hng (Multiplexed Single Ended), 7 ng vo vi sai (Differential Input), B ADC ca ATmega128 l loi ADC xp x lin tip (succesive approximation ADC) vi hai ch hot ng c th lu chn l chuyn i lin tc (Free Running) v chuyn i tng bc (Single Conversion). S khi n gin ca mt b ADC c th hin nh hnh 5.2.
Hnh 5.2. S n gin ca mt khi ADC Nguyn tc hot ng ca khi ADC : Tn hiu tng t a vo cc ng ADC0:7 c ly mu v bin i thnh tn hiu s tng ng. Tn hiu s c lu trong hai thanh ghi ACDH v ADCL. Mt ngt c th c to ra khi hon thnh mt chu trnh bin i ADC.
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Thc t, b ADC ca ATmega128 phc tp hn nhiu, tuy nhin c s vn da vo nguyn tc trn. kho st b ADC ca ATmega128 ta cn tm hiu cc khi chc nng sau: in Th Tham Chiu: l gi tr in th dng so snh vi in th ca tn hiu tng t cn bin i ng vo ADC. ATmega128 c 3 la chn in th tham chiu l AVCC bng vi VCC, in th tham chiu ni 2.56v, v Vref l ty chn. Bn c cn l AVR c 2 ngun in th tham chiu ni l internal reference = 2.56v v bandgap reference = 1.24v. in th bandgap reference l mt hng s vt l, n lun l 1.24v, cn in th internal reference th c th thay i ty theo cc dng chip khc nhau. Trong AVR, internal reference c to ra t bandgap reference. Trong ti liu ny, tc gi iu dch hai dng in th trn iu l in th tham chiu ni, tuy vy, bn c nn hiu s khc nhau gia hai khi nim trn. Tn S Clock ADC: l tn s clock cung cp cho b bin i ADC, gi tr c th thay i t vi KHz n vi MHz. Tuy nhin, tn s thch hp khong t 50KHz n 200KHz cho phn gii 10 bit v c th cao hn 200KHz nu phn gii thp hn. Ng Vo Tng T: ATmega128 c hai la chn ng vo tng t: - 10 ng vo n hng (single ended): 10 ng vo ny l ADC0:7, AGND v bandgap reference. Thc t ta thng dng 8 ng vo ADC0:7. V c 8 ng vo ADC0:7 nn ta c th a vo 8 tn hiu tng t khc nhau. Khi la chn ng vo kiu ny (tc kiu single ended) th kt qu chuyn i c tnh nh sau:
ADC =
Vin *1024 Vref
- Ng vo vi sai: Ta c th a hai tn hiu tng t vo ng vo ADC, hai tn hiu tng t ny s qua mt b vi sai (mch tr), kt qu ng ra c th c khuch i ri sau mi a vo khi ADC bin i. B vi sai c 2 ng vo l Vpos (ng vo dng) v Vneg (ng vo m). Cc chn ADC3:7 dng lm ng vo dng, cc chn ADC0:2 l ng vo m, hnh 5.3. i vi la chn ny, kt qu ADC s l :
ADC =
(VPOS VNEG ) * Gain *512 VREF

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y Gain l li c th ty chn. Cng thc trn cho thy kt qu ADC c th l s m khi Vpos < Vneg. Do , di gi tr ca ADC trong trng hp ny l -512 ti 511. V vy, kt qu trong thanh ghi ADC c biu din di dng s b 2. bit c kt qu l s m hay dng ta kim tra bit ADC9 (trong thanh ghi ADCH), nu bit ny l 1 th kt qu l s m, nu bit ny l 0 th kt qu l s dng. Ch : in th qua b vi sai c th m, nhng in th cp cc ng vo ADC0:7 (cho c hai trng hp ng vo vi sai v ng vo n hng) phi lun nm trong khong 0v AVCC.
Hnh 5.3. Ng vo vi sai Ch Hot ng: C hai ch hot ng ca b ADC l chuyn i lin tc (Free Running) v chuyn i tng bc (Single Conversion). - Chuyn i lin tc: l ch m sau khi khi ng th b ADC thc hin chuyn i lin tc khng ngng. - Chuyn i tng bc: l m b ADC sau khi hon thnh mt chuyn i th s ngng, mt chuyn i tip theo ch c bt u khi phn mm c yu cu chuyn i tip.
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2. Cc Thanh Ghi Ca B ADC.

a. Thanh ghi ADC Multiplexer Selection - ADMUX
Bit 7:6 REFS1:0: Reference Selection Bits Bit 5 ADLAR: ADC Left Adjust Result Bits 4:0 MUX4:0: Analog Channel and Gain Selection Bits
Bit 7:6 REFS1:0: Reference Selection Bits: hai bit ny dng la chn in th tham chiu l mt trong 3 ngun: AVCC, in th tham chiu ni 2.56v v VREF nh bng 97. Nu chn in th VREF th cc ty chn cn li khng c s dng trnh b ngn mch, iu ny c ngha l nu ta chn in th tham chiu l VREF ri, th trong sut qu trnh hot ng ca b ADC ta khng c la chn in th tham chiu khc, v nu khng, ngun in th VREF bn ngoi do cha c tho i s lm hng chip do ngn mch.
Bng 97. La chn in th tham chiu Bit 5 ADLAR: ADC Left Adjust Result: Bit ny la chn cch b tr d liu trong hai thanh ghi d liu ADCH v ADCL. Xem phn m t hai thanh ghi d liu ADCH v ADCL bit chi tit. Bits 4:0 MUX4:0: Analog Channel and Gain Selection Bits: Cc bit ny la chn kiu ng vo (n hay vi sai) v li, xem bng 98.
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Bng 98. La chn kiu ng vo v li

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b. Thanh ghi ADC Control and Status Register A ADCSRA
Bit 7 ADEN: ADC Enable Bit 6 ADSC: ADC Start Conversion Bit 5 ADFR: ADC Free Running Select Bit 4 ADIF: ADC Interrupt Flag Bit 3 ADIE: ADC Interrupt Enable Bits 2:0 ADPS2:0: ADC Prescaler Select Bits Bit 7 ADEN: ADC Enable: Bit ny l 1 s cho php b ADC hot ng, ngc li, s ngng b ADC ngay c khi n ang trong qu trnh bin i. Bit 6 ADSC: ADC Start Conversion: Ghi bit ny thnh 1 bt u qu trnh chuyn i. Trong ch chuyn i tng bc, sau mi ln chuyn i hon thnh bit ny b xa v 0, ta phi set li bit ny bt u mt bin i tip theo. Trong ch chuyn i lin tc, ta ch cn set bit ny mt ln. Bit 5 ADFR: ADC Free Running Select: Set bit ny ln 1 la chn ch hot ng bin i lin tc. Bit ny l 0 s cho php ch bin i tng bc. Bit 4 ADIF: ADC Interrupt Flag: Bit ny s c set thnh 1 khi mt chu trnh bin i ADC hon thnh, bit ny c xa bi phn cng khi trnh phc v ngt tng ng c thc thi. Ch l khi ta chnh sa thanh ghi ADCSRA (nh dng cc lnh CBI, SBI) th bit ny s b xa. V vy, xa bit ny bi phn mm, ta ch cn ghi gi tr 1 vo n. Bit 3 ADIE: ADC Interrupt Enable: Bit ny cho php ngt ADC, khi bit ADIE (cho php ngt ADC) v bit I (cho php ngt ton cc) trong thanh ghi SREG c set ln 1 s cho php ngt ADC hot ng. Bits 2:0 ADPS2:0: ADC Prescaler Select Bits: V tn s clock ADC c ly t xung clock h thng (hnh 109), nn cc bit ADPS2:0 s cho php chia xung clock h thng vi cc h s xc nh (bng 99) trc khi a vo ngun clock ADC. Vi phn gii 10 bit, tn s clock ADC khong t 50 200 KHz, nn ty theo tn s clock h thng m ta la chn h s chia thch hp. : Trnh bin dch AVRStudio 4 ca Atmel xem ADCSRA v ADCSR l mt, c hai iu ch ti thanh ghi ADCSRA. Chn hn, lnh sbi ADCSRA, ADSC v sbi ADCSR, ADSC l tng ng.
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Hnh 109. Ngun clock ADC
Bng 99. La chn cc h s chia cho ngun clock ADC
c. Thanh ghi ADC Data Register ADCL and ADCH

y l hai thanh ghi cha kt qu ADC, ty theo thit lp ca bit ADLAR (trong thanh ghi ADMUX) m 10 bit d liu ADC c th c b tr v pha phi hay tri ca hai thanh ghi ADCH v ADCL, c th nh sau:
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ADLAR = 0
ASDLAR = 1
Tm tt: s dng b ADC ta thc hin cc bc sau: 1. Cu hnh cho b ADC: chn in th tham chiu, kiu ng vo bng cch cu hnh cho thanh ghi ADMUX. 2. Cho php ADC hot ng: Chn ch hot ng, cc ngt, tn s Clock ADC bng cch cu hnh cho thanh ghi ADCSRA. V d. on chng trnh nh sau cho php b ADC hot ng ch bin i tng bc, ng vo l chn ADC3, khng dng ngt. (vit bng C c th xem chng VII) ADC_Init: ldi r16,3 ; out ADMUX, r16 ldi r16, 0b10000101 out ADCSRA, r16 sbi ADCSRA, ADSC // chn ng vo ADC3, in th tham chiu VREF
// khng dng ngt, h s chia clock l 32, chy tng bc // khi ng b ADC
Wait: sbis ADCSRA, ADIF //i ADC hon thnh rjmp Wait in r16, ADCL in r17,ADCH // lu kt qu ADC
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III. B TRUYN NHN D LIU NI TIP USART 1. Tm Lc V USART.

USART (Universal Synchronous and Asynchronous serial Receiver and Transmitter): B Truyn Nhn Ni Tip ng B V Bt ng B Ph Dng, y l khi chc nng dng cho vic truyn thng gia vi iu khin vi cc thit b khc. Trong vn truyn d liu s, c th phn chia cch thc (method) truyn d liu ra hai ch (mode) c bn l : Ch truyn nhn ng b (Synchronous) v Ch truyn nhn Bt ng b (Asynchronous). Ngoi ra, nu gc phn cng th c th phn chia theo cch khc l: Truyn nhn d liu theo kiu Ni tip (serial) v Song song (paralell). Truyn ng B: l kiu truyn d liu trong b truyn (Transmitter) v b nhn (Receiver) s dng chung mt xung ng h (clock). Do , hot ng truyn v nhn d liu din ra ng thi. Xung clock ng vai tr l tn hiu ng b cho h thng (gm khi truyn v khi nhn). u im ca kiu truyn ng b l tc nhanh, thch hp khi truyn d liu khi (block). Truyn Bt ng B: L kiu truyn d liu trong mi b truyn (Transmitter) v b nhn (Receiver) c b to xung clock ring, tc xung clock hai khi ny c th khc nhau, nhng thng khng qu 10 o/o . Do khng dng chung xung clock, nn ng b qu trnh truyn v nhn d liu, ngi ta phi truyn cc bit ng b (Start, Stop,) i km vi cc bit d liu. Cc b truyn v b nhn s da vo cc bit ng b ny quyt nh khi no th s thc hin hay kt thc qu trnh truyn hoc nhn d liu. Do , h thng truyn khng b cn c gi l h thng truyn t ng b. T hai kiu truyn d liu c bn trn, ngi ta a ra nhiu giao thc (Protocol) truyn khc nhau nh: SPI (ng b), USRT (ng b), UART (bt ng b),Tuy vy, cng c giao thc truyn m khng th xp c vo kiu no: ng b hay bt ng b, chn hn kiu truyn I2C (Trong AVR gi l TWI), tuy vy mt cch hi gng p th c th thy giao thc truyn I2C gn vi kiu ng b hn v cc thit b giao tip vi nhau theo chun I2C iu dng chung mt xung clock.
2. Gi Thiu B USART Ca ATmega128.

ATmega128 c hai b USART l USART0 v USART1. Hai b USART ny l c lp nhau, iu ny c ngha l hai khi USART0 v USART1 c th hot ng cng mt lc. S khi n gin ca khi USART th hin trong hnh 79.
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Hnh 79. S khi b USART S khi ca b USART phn chia thnh ba phn r rng: Khi to xung clock (clock Generator), Khi Truyn (Transmitter) v Khi nhn (Receiver). Cn cc thanh ghi iu khin USART c dng chung. (Phn ny cha y , cn c bn c b sung)
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Chng VI
H THNG XUNG CLOCK V LP TRNH B NH ON-CHIP

I. H THNG XUNG CLOCK
H thng xung clock ca ATmega128 c chia thnh nhiu khi khc nhau, mi khi (module ) s cung cp xung clock cho cc khi ngoi vi ng dng tng ng. Hnh 18 th hin s ca h thng xung clock trn ATmega128.
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cu hnh cho chip hot ng theo ch xung clock no, ngi ta dng cc bit cu ch ( fuse bit ) CKSEL 3, CKSEL2, CKSEL 1. Ngoi ra khi vi iu khin c nh thc t cc ch ngh sang ch hot ng bnh thng, b to dao ng cn c mt khong thi gian n nh, khong thi gian ny gi l thi gian khi ng ( start-up time ). CPU ch thc hin lnh khi ht khong thi gian khi ng ny. Khi ta reset CPU cng cn mt khong thi gian tr hon (delay time ) ngun nui t mc n nh trc khi thc bt u thc thi lnh. Ngi ta dng cc bit cu ch CKSEL 0, SUT1, SUT0 thit lp thi gian khi ng v thi gian tr hon. Khong thi gian khi ng v thi gian tr hon c o c o bng mt ng h ring, l b dao ng Watchdog. Tn s ca b dao ng Watchdog ph thuc vo in th ngun nui v nhit mi trng. Vcc = 5V v nhit 25oC th tn s ca b dao ng Watchdog l 1 MHz. Lin quan n vic thit lp ca h thng xung clock ngi ta cn dng ti bit cu ch CKOPT m vai tr ca n kh linh hot ty theo vic thit lp xung clock cho h thng nh th no. Hnh 18 cho thy ATmega128 c ti 7 b to xung clock c th c la chn. Di y l m t c th cho tng trng hp cu hnh xung clock ca h thng.
1. B DAO NG THCH ANH

B dao ng thch anh c mc theo hnh 19. Trong chn XTAL1 v XTAL2 ( tng ng chn s 24 , 23 ca vi iu khin ) ln lt l ng vo v ng ra ca b khuch i o c tch hp sn trong chip.
Hnh 19. Ghp ni b dao ng thch anh Gi tr ca t C1 v C2 phi bng nhau v thng c gi tr vo khong 12pF 22pF. Vi ATmega128 th tn s xung clock h thng ti a l 16MHz v t c tn s ti a ny bit cu ch CKOPT phi c lp trnh ( ghi thnh 0 ). Nu bit CKOPT khng c lp trnh ( ghi gi tr 1 ) th tn s ti a ch l 8 MHz. Cc bit CKSEL3..1 c dng la
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chn di tn s ti u nh trong bng 8. Cc bit CKSEL0 v SUT1..0 c dng thit lp thi gian khi ng ( start-up ) v thi gian tr hon ( delay time ) nh trong bng 9. Ta cng c th thay th tinh th thch anh ( Quartz crystal ) bng gm cng hng ( Ceramic Resonator ).
Bng 8. Ti u di tn s La chn (1) ch nn dng cho gm cng hng, khng nn dng cho thch anh
Bng 9. Thit lp thi gian khi ng v tr hon
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V d s dng thch anh 16 MHz lm xung clock h thng, thi gian khi ng l 16 K ( 16384 chu k xung clock ca b dao ng watchdog ) v thi gian tr hon l 65 ms th ta cn thit lp cho cc bit cu ch l : { CKOPT, CKSEL3..0, SUT1..0 } = { 0, 1, 0, 1, 1, 1, 1 }
2. B DAO NG THCH ANH C TN S THP

Thch anh trong trng hp ny c tn s thp 32,768 KHz c mc vo mch nh hnh 19. Tn s thp c s dng gim cng sut tiu th ca h thng v thch hp cho cc ng dng cn o thi gian thc. cu hnh cho h thng xung clock theo ch ny, cn thit lp cc bit cu ch { CKSEL3..0 } = { 1, 0, 0, 1 }. Cc t C1, C2 cng c th c b i bng cch lp trnh cho bit CKOPT cho php t bn trong chip hot ng. T bn trong chip c gi tr nh danh l 36 pF. Thi gian khi ng v thi gian tr hon c la chn nh vo cc bit cu ch SUT1..0 theo nh bng 10.
3. B DAO NG R-C BN NGOI

B dao ng R-C bn ngoi thch hp cho nhng ng dng khng i hi cao v s chnh xc thi gian . Mch R-C c mc nh hnh 20. Tn s dao ng vo khong: 1 f = 3* R * C Trong gi tr ca C phi ti thiu l 22 pF. Tuy nhin ta cng c th b i t C bng cch lp trnh cho bit cu ch CKOPT cho php t bn trong chip ( mc gia XTAL1 v GND ) hot ng. Gi tr nh danh ca t bn trong chip l 36 pF. Cc bit cu ch CKSEL3..0 s cu hnh di tn s ti u nh bng 11 v cc bit cu ch SUT1..0 s thit lp thi gian khi ng v thi gian tr hon nh bng 12.
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Hnh 20. Mch dao ng R-C
Bng 11. Ti u di tn s
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4. B DAO NG NI R-C TINH CHNH C

B dao ng ni RC cung cp cc tn s xung clock c nh 1 MHz, 2 MHz, 4 MHz, 8 MHz ( Vcc = 5V v nhit 25oC ). Ta c th dng xung clock ny nh l xung clock ca h thng bng cch cu hnh cho cc bit cu ch CKSEL 3..0 c ch ra bng 13. Khi s dng xung clock ca b dao ng ni lm xung clock ca h thng ta khng cn phi dng b dao ng bn ngoi. Khi cu hnh xung clock h thng theo trng hp ny bit cu ch CKOPT khng c lp trnh ( ghi l 1 ). V b dao ng watchdog c lp vi b dao ng ni RC ( xem hnh 18 ) nn khi h thng hot ng theo xung clock ca b dao ng ni RC th b dao ng watchdog vn c s dng cho b nh thi watchdog. Ngoi ra, ngi dng c th tinh chnh tn s ca b dao ng ni bng cch thay i gi tr ca thanh ghi OSCCAL. L do ca vic tinh chnh ny l bi v trong qu trnh m ( tc pht xung clock ) ca b dao ng ni, sau 1 thi gian th s c sai s, v d b dao ng ni c tn s 1 MHz sau 1000000 ln m th khong thi gian tng ng 1s s tri qua. Nu thi gian m ko di s c th c sai s. Do ngi ta cn tinh chnh li tc ca b dao ng ni bng cch lm cho n m nhanh hn hay chm i so vi gi tr nh danh. lm c iu ny ngi ta tng hay gim gi tr ca thanh ghi OSCCAL.
Bng 13. La chn tn s dao ng ni Khong thi gian khi ng v thi gian tr hon c thit lp bi cc bit cu ch SUT1..0 theo bng 14.
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5. B TO XUNG CLOCK BN NGOI

Ngi dng cng c th s dng mt my pht xung clock bn ngoi lm xung clock cho h thng. S ghp ni vi my to xung clock bn ngoi c th hin hnh 21.
Hnh 21. Ghp ni vi my pht xung clock bn ngoi
Bng 16. Thit lp thi gian khi ng v tr hon Trong trng hp ny cc bit cu ch CKSEL3..0 phi ghi thnh 0000. Ngi dng cng c th cho php t bn trong chip ( gia XTAL1 v GND ) hot ng bng cch lp trnh cho bit CKOPT ( ghi CKOPT thnh 0 ). Gi tr nh danh ca t bn trong chip l 36 pF. Thi gian khi ng v thi gian tr hon c thit lp bi cc bit SUT1..0 c cho bng 16.
6. B DAO NG NH THI
Ngi dng cng c th mc trc tip b dao ng thch anh vo gia 2 chn TOSC1 v TOSC2 ca vi iu khin ( khng cn t ) to xung clock cho h thng nh hnh 21b. B dao ng c ti u cho tn s thch anh 32,768 KHz.
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7. Thanh Ghi XDIV Chia Tn S Ngun Xung Clock

Ngi ta dng thanh ghi XDIV chia tn s ca ngun xung clock cho mt s t 2 n 129 ty theo gi tr c ghi vo thanh ghi ny.
Bit 7 XDIVEN: XTAL Divide Enable: Khi bit ny l 1 s cho php chia tn s xung clock ca CPU v xung clock ca tt c cc ngoi vi ( clkI/O, clkADC, clkCPU, clkFLASH ) cho mt s t 2 n 129 . Gi tr ca s chia c th c thay i trong lc chng trnh ang chy vi iu kin l bit XDIVEN ang logic 0. Ghi bit ny l 0 th khng cho php chia ( tng ng vi chia cho 1 ). Bits 6..0 XDIV6..XDIV0: XTAL Divide Select Bits 6 0: 7 bit ny s xc nh gi tr ca s chia. Nu ghi vo 7 bit ny gi tr l d th tn s xung clock ca CPU v cc ngoi vi s l :
fclk =
fnguon 129 d
thay i h s d th bit XDIVEN phi xa v 0 trc khi ghi gi tr mi vo cc bit XDIV6..XDIV0. Ch : Khi tn s ca h thng xung clock c chia, b nh thi 0 ch hot ng c vi xung clock bt ng b, tn s ca xung clock bt ng b phi nh hn ln tn s xung clock chia. Ngun xung clock bt ng b l ngun xung clock c to t b dao ng thch anh ( ti u l 32,768 KHz ) kt ni trc tip ti 2 chn TOSC1 v TOSC2 nh Hnh 21b. V nguyn tc c th dng my pht xung clock kt ni trc tip vi chn TOSC1 dng lm ngun xung clock bt ng b cho b nh thi 0. Chi tit v ch hot ng bt ng b ca b nh thi 0 c trnh by chng 3 B nh Thi ca ATmega128 , mc 3. Theo mc nh ca nh sn xut th gi tr ban u ca cc bit cu ch l: { CKSEL3..0, SUT1..0 } = {0, 0, 0, 1, 1, 0 }, tc Chip s s dng b dao ng ni c tn s 1 MHz vi thi gian khi ng l 65 ms .
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II.
LP TRNH B NH TRN CHIP

(Nu bn np c chng trnh vo Chip th coi nh xong phn ny ) (Phn ny cha y , cn c bn c b sung)
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Chng VII LP TRNH AVR BNG NGN NG C

Phn ny ch tm tc cc vn lin quan ti lp trnh AVR bng ngn ng C, xem nh bn c c kin thc v ngn ng C. Trnh bin dch c s dng y l CodeVisionAVR ( http://www.hpinfotech.com/ ).
VII.1 Cc Ch Thch V Tin X L (PreProcessor) - Cc Ch Thch. Thng thng bt u mt chng trnh l cc ch thch v project, cc ch thch phi bt u bng du // hay /* cc ch thch */ v c trnh bin dch b qua khi bin dch, chn hn:
//*************************************** // comments placed in there // File: demo.c // Author: Le Trung Thang // Date: 2007 //***************************************
- Cc Tin X L. #include : Dng chn cc file cn thit vo project, cc file ny nn trong th mc inc ca trnh bin dch CodeVisionAVR. V d:
#include <mega128.h> cho php s dng cc thanh ghi ca Atmega128.
Tc bo cho trnh bin dch bit chng ta ang s dng vi iu khin Atmega128. y s l dng code u tin trong chng trnh C. #define : Dng nh ngha mt gi tr no bng cc k t. V d:
#define max 0xff
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nh ngha max c gi tr l 0xff. Ch khng c du chm phy (;) cui cu v define ch l mt macro ch khng phi l mt lnh. Macro cng c th c tham s. v d:
#define SUM(a,b) a+b main( ) { //cc lnh khc int I = SUM(2,3); //cc lnh khc };
Th i s c gn thnh i = 2 + 3 = 5. VII.2 Cc Kiu D Liu ( DataTypes) Ngoi cc kiu d liu ca C, CodeVisionAVR cn c kiu d liu bit l kiu d liu 1 bit, nn di gi tr ch c 0 v 1. Kiu bit ch h tr i vi khai bo bin ton cc l chnh. Vi bin bit cc b, trnh bin dch ch cho khai bo ti a 8 bin bit. V d :
bit a; //a l bin kiu bit
cc kiu khc c cho trong bng di.
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a. Hng - Cc hng s c t trong b nh FLASH, ch khng t trong RAM. - Khng c khai bo hng trong chng trnh con. - Gi tr 100 c hiu l s thp phn (decimal), 0b101 ch gi tr nh phn (binary) v 0xff ch gi tr thp lc (hexadecimal) V d:
const char a = 128 ; // hng s a c kiu char v c gi tr l 128.
b. Bin - Bin gm c bin ton cc (global) l bin m hm no cng c th truy xut, v bin cc b (local) l bin m ch c th truy xut trong hm m n c khai bo. - Bin ton cc, nu khng c gi tr khi to s c mt nh l 0. Bin cc b, nu khng c gi tr khi to s c gi tr khng bit trc. - Bin ton cc c lu tr trong cc thanh ghi Rn, nu dng ht cc thanh ghi th s chuyn sang lu tr trong vng SRAM. ngn cn cc bin ton cc c lu vo cc thanh ghi Rn, d cc thanh ghi ny vn cn t do, ta dng t kha volatile (xem sau). - Bin ton cc, nu khng lu trong cc thanh ghi a chc nng th c lu tr trong b nh SRAM, cn bin cc b, nu khng lu trong cc thanh ghi a chc nng, th c lu tr trong vng data STACK. Khi chng trnh tr v gi tr cui cng cho hm th cc bin cc b c lu tr trong stack s b xa. bin cc b khng b xa khi thot khi hm ta dng t kha static. - Bin bit ton cc c cp pht cc thanh ghi R2 ti R14 ca vi iu khin, cc bit c cp pht t R2 ti R14 theo th t khai bo, nhc li l ATmega128 c 32 thanh ghi a chc nng R0 n R31. - Trong chng trnh C, ni bt u thc thi chng trnh l im bt u ca hm main. Thc t, khi bin dch sang hp ng (assembly), im bt u ca chng trnh vn l v tr vector reset (a ch 0000h). Trc khi chy ti v tr chng trnh main, chng trnh hp ng s thc hin khi to cc bin ton cc, stack,... Do , khi chy vo hm main, cc bin ton cc, m thc cht l cc
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nh (byte hay word), c gi tr khi to sn. Vi cc bin cc b, trnh hp ng khng khi to trc gi tr. - v d: khai bo bin cc b nh sau:
main ( ) { unsigned char test = 9 ; test+=1; }
S dch sang hp ng l :
LDI SUBI Rn,0x09 ;// n ty theo dng chip v chng Rn,0xFF ;// trnh ta vit, R17 chn hn
Nh vy, vi bin cc b, khi no s dng th mi khi to. V d 1:

/* khai bo bin ton cc */ char a; int b; /* c th khi to gi tr */ long c = 0b1111; /* chng trnh con */ int increment(void) { /* khai bo bin static */ static int n ; return n++ ; } /* chng trnh chnh*/ void main(void) { /* khai bo bin cc b */ char d; int e; /* c th khi to gi tr */ long f = 16; d = increment() ; /* d = 1 */ e = increment() ; /* e = 2 , v khi thot khi hm increment th gi tr ca bin static n vn khng b xa*/ } H Khoa Hc T Nhin TP. H Ch Minh - 2007
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V d 2:
bit bit_mot ; // bit 0 ca thanh ghi R2 c cp cho bin bit_mot bit bit_hai ; // bit 1 ca thanh ghi R2 c cp cho bin bit_hai
l cc bin kiu bit trn l bin ton cc, i vi bin bit cc b, trnh bin dch s ct trong thanh ghi R15. Cc thanh ghi R2 ti R14 cng c th c cp pht cho bin thanh ghi (register variable), ty vo cc ty chn khi cu hnh cho trnh bin dch. (c th khng ng vi cc version mi ca trnh bin dch). Bin volatile: - tng thch vi cc thit b ngoi vi khi ghp ni vi vi iu khin, chn hn b ADC, ghp ni vi RTC ngi ta dng cc bin volatile. Bin Volatile l bin m gi tr ca n khng c thay i bi chng trnh, nhng c th c thay i bi phn cng. V d 3. Ta mun ghp ni MCU vi mt Real time clock (RTC), gi tr ca thanh ghi RTC c c sau mi mt khong thi gian.
unsigned int *milliseconds = 0x8000 ; // tr ti thanh //ghi cha gi tr giy ca chip RTC unsigned int x,y,time ; time = *milliseconds ; // (1) c gi tr thanh ghi RTC ln 1 x = time ; time = *milliseconds ; // (2) c gi tr thanh ghi RTC ln 2 y = time ;
on chng trnh trn s ch c gi tr thanh ghi RTC c mt ln nn kt qu l thi gian th hin s khng ng, nguyn nhn l t dng (1) ti (2), bin *milliseconds khng b thay i gi tr (trong chng trnh ta khng lm g thay i *milliseconds c), do trnh bin dch s ti u on code trn bng cch b bt dng s (2), gn y = x. Nhng thc t l phn cng (s m ca ng h) lm thay i *milliseconds. Do , gi tr time (1) s khc time (2) .
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ngn trnh bin dch ti u on code trn ta dng t kha volatile cho bin milliseconds. on code cn c sa thnh:
unsigned int volatile *milliseconds = 0x8000 ; // tr ti //thanh ghi cha gi tr giy ca chip RTC unsigned int x,y,time ; time = *milliseconds ; // (1) c gi tr thanh ghi RTC ln 1 x = time ; time = *milliseconds ; // (2) c gi tr thanh ghi RTC ln 2 y = time ;
Ta cng c th ch nh vic lu tr mt bin ton cc mt a ch c th trong SRAM bng cch dng ton t @. V d 4:
int a @0x80 ; // bin nguyn a c ct a ch 80h trong //b nh SRAM
c. Chuyn i Kiu D Liu Trong mt biu thc ton hc, cc ton hng c th c kiu d liu khc nhau, khi trnh bin dch s t ng chuyn tt c cc ton hng v cng mt kiu duy nht. Th t u tin chuyn i l :
Char -> unsigned char -> int -> unsigned int -> long -> unsigned long -> float
V d 1.
int a ; long c, b; c = a*b ; //a s c t ng chuyn thnh long
V d 2. Php nhn sau y cho kt qu sai:

int a, b = 30000; long c ; c = a*b ;
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php ton trn s nhn a vi b trc, vi tch thu c l int b trn, ri mi chuyn tch thu c sang long, ri gn tch b trn ny cho c. khng b trn, ta sa li biu thc trn nh sau:
int a, b = 30000; long c ; c = (long) a*b ;
lc ny a, b c chuyn thnh long trc khi nhn, nn tch s l long khng b trn, ri gn kt qu cho c. VII.3 Mng (Array) Mng l mt dy cc bin xp lin tc nhau. K hiu [ ] dng khai bo mng. Mng khai bo ngoi hm gi l mng ton cc (global array), mng khai bo trong hm gi l mng cc b ( local array). V d:
int global_array[4]={1,2,3,4}; //mng c 4 phn t (dng nguyn) c khi to gi tr ban u. global_array[0] = 9 ; //ghi gi tr 9 vo phn t u tin ca mng int multidim_array[2][3]={{1,2,3},{4,5,6}}; //mng a chiu c khi to gi tr ban u.
VII.4 Hm (Function) - Hm l on chng trnh thc hin trn vn mt cng vic nht nh. - Hm chia ct vic ln bng nhiu vic nh. N gip cho chng trnh sng sa, d sa, nht l i vi cc chng trnh ln. - Chng trnh phc v ngt (ISR) cng c th xem l mt hm, nhng khng c tham s truyn vo v cng khng c tham s tr v (xem sau). - Hm vit cho MCU cng ging nh vit trn PC, bn c c th xem li cc ti liu v ngn ng C khi cn thit. - Gi tr tr v ca hm c lu trong cc thanh ghi R30, R31, R22, R23. VII.5 Con Tr (Pointer)
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Nhng bin lu tr a ch ca mt bin khc c gi l con tr (pointer). C hai ton t lin quan ti con tr l : & v * . & : l ton t ly a ch, c ngha l a ch ca . * : l ton t tham chiu, c ngha l Gi tr c tr bi. s dng con tr ta phi khai bo n. Kiu khai bo nh sau:
type * pointer_name;
V d:
int *con_tro ;
l du sao (*) m chng ta t khi khai bo mt con tr ch c ngha rng: l mt con tr v hon ton khng lin quan n ton t tham chiu * m chng ta ni trn. n gin ch l hai tc v khc nhau c biu din bi cng mt du. Khi mt bin con tr c khai bo, n cha cha gi tr no c, ging nh cc kiu bin khc. gn a ch cho con tr chng ta cn phi gn gi tr cho con tr (tc khi to con tr). V d.
int number; int *con_tro;// khai bo bin con_tro l mt con tr nguyn con_tro = &number ;// bin con_tro tr ti bin number
Sau khi khi to, ta c th s dng con tr bnh thng trong cc biu thc. V d.
int value1 = 5 ; int value2 = 15; int * mypointer; mypointer = &value1; // con tr mypointer tr ti bin value1 *mypointer = 10; //gi tr ca bin value1 = 10 mypointer = &value2; // con tr mypointer tr ti bin value2
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VI IU KHIN AVR ATmega 128 *mypointer = 20; // gi tr ca bin value2 = 20
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VII.5 Truy Xut Cc Thanh Ghi Vo/Ra (Accessing The I/O Registers) Vic truy xut cc thanh ghi I/O ca AVR kh n gin, tt c cc thanh ghi I/O ca AVR c khai bo trong file io.h, ta ch vic include file header io.h (hoc file header cho tng chip c th, mega128.h) vo chng trnh l c th s dng cc thanh ghi ny. Ch l vic truy xut bit trong cc thanh ghi c a ch 5Fh tr ln trong vng nh SRAM l khng th thc hin c. V d.
include<io.h> Char temp ; temp = PIND; // c gi tr cng D vo bin temp TCCR0 = 0x4F;// ghi gi tr 4Fh vo thanh ghi TCCR0 DDRD |= 0x0C; // set bit 2 v 3 ca thanh ghi DDRD
VII.6 Truy Xut EEPROM Dng t kha eeprom khi khai bo bin (ton cc) th bin s c lu vo EEPROM. , l bin trong eeprom khng c gi tr khi to ngay khi chng trnh thc thi, ngay c khi, trong khai bo bin eeprom ta c khi to gi tr cho bin ny. Gi tr khi to ch c dng np trc tip vo eeprom bi phn mm. (iu ny c th khng chnh xc vi cc phin bn mi hn ca trnh bin dch). V d. ( xem thm v d mc VII.8.h )
eeprom int alfa=1; eeprom char beta ; y, khi chng trnh bt u thc thi, bin alfa vn khng chc l c gi tr 1, n l mt gi tr khng bit trc. Do , chc chn ghi gi tr 1 vo bin alfa, ta nn vit li : eeprom int alfa=1; eeprom char beta ; alfa = 1 ;
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Ta cng c th t mt bin vo mt v tr ty trong eeprom bng cch dng ton t @. V d:

eeprom int alfa @0x10;//bin alfa t v tr 0x10 trong eeprom
VII.6 S Dng Ngt (interrupt) thc thi chng trnh ngt, ta dng t kha interrupt. Khun dng ca chng trnh phc v ngt l :
interrupt [interrupt_number] void routine_name (void) { //t chng trnh phc v ngt y }
interrupt_number : l s th t ca vector ngt, c th tm thy datasheet ca
MCU hay t file header ca MCU trong th mc inc. Ta c th thay th s th t ca vector ngt bng tn gi nh c nh ngha trong file header ca MCU. routine_name: tn chng trnh ngt, l ty chn. Chng trnh phc v ngt khng c tham s truyn vo v cng khng c tham s tr v.
V d.
// Gi nh MCU ang dng l ATmega128, ngt trn Timer 0 interrupt [17] void timer0_overflow(void) { // t chng trnh phc v ngt y } Hoc l: interrupt [TIM0_OVF] void timer0_overflow(void) { // t chng trnh phc v ngt y }
Trnh bin dch s t ng lu gi gi tr cc thanh ghi b tc ng trong lc ang gi trnh phc v ngt v s phc hi li gi tr cc thanh ghi ny khi thot khi trnh phc v ngt. Tuy nhin ta c th ngn cn s lu gi gi tr cc thanh ghi b tc ng bng cch dng ch th #pragma savereg - . ( khuyn khch l khng nn dng )
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VII.7 S Dng B ADC

Trong C, s dng ADC ta ch cn khai bo cc thng s cho b ADC trong hm main, sau c th s dng mu hm c ADC do CodeVision AVR to ra. l nu s dng chc nng debug Jtag th c mt s chn ADC (ADC4,..,ADC7) ca AVR khng s dng c. Bn c nn xem phn chng nhiu cho ADC trong datasheet. y ch tp trung vo kha cnh lp trnh. V d sau dng ADC 10bit, tc 500.000 kHz, chy tng bc. (xem thm phn m t b ADC trang 61)
#include <mega128.h> //Khai bo l ang dng ATmega128 // hm c kt qu ADC, tn hm l ty ,theo chun C unsigned int read_adc(unsigned char adc_input) { ADMUX=adc_input | (ADC_VREF_TYPE & 0xff); // Delay needed for the stabilization of the ADC input voltage delay_us(10); // Start the AD conversion ADCSRA|=0x40; // Wait for the AD conversion to complete while ((ADCSRA & 0x10)==0); ADCSRA|=0x10; return ADCW; } // hm main Void Main( ) { Unsigned int adc_temp ; // khai bo bin lu kt qu ADC // Khi to cho b ADC y // Tn s bin i: 500.000 kHz //Chn lm in th so snh cho b ADC l AVCC //in th ca AVCC l c nh (bng VCC cp cho AVR) ADMUX=ADC_VREF_TYPE & 0xff; ADCSRA=0x84; // xong phn khi to // ... adc_temp = read_adc (0) ; //c kt qu ADC chn ADC0 adc_temp = read_adc (1) ; //c kt qu ADC chn ADC1 // ... adc_temp = read_adc (7) ; //c kt qu ADC chn ADC7 //phi disable chc nng jtag };
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VII.8 Tm Tt Cc Cu Trc iu Khin

Phn ny ch gip cc bn tra cu nhanh, nu qun.
a. Cu trc iu kin: if v else.

if (condition 1) { Khi lnh 1 } else if (codition 2) { Khi lnh 2 } else { Khi lnh khc }
V d.
if(input == KEY_1)PORTD = 0x01; else if (input == KEY_2) PORTD = 0x02; else if (input == KEY_3)PORTD = 0x03; else PORTD = 0x00;
b. Vng lp while v do While

while (expression) statement ; // (1) do statement while (condition); // (2)
Chc nng ca (1) n gin ch l lp li statement khi iu kin expression cn tho mn. Chc nng ca (2) hon ton ging vng lp while ch tr c mt iu l iu kin iu khin vng lp c tnh ton sau khi statement c thc hin, v vy statement s c thc hin t nht mt ln ngay c khi condition khng bao gi c tho mn. V d.
int i ; while (i < 128) { PORTD = i; i = i*2 ; H Khoa Hc T Nhin TP. H Ch Minh - 2007
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VI IU KHIN AVR ATmega 128 }
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c th lp v hn, ta dng cu trc:

While (1) { Statement }
c. Vng lp for
for (initialization; condition; increase) statement;
Chc nng chnh ca n l lp li statement chng no condition cn mang gi tr ng, nh trong vng lp while. Nhng thm vo , for cung cp ch dnh cho lnh khi to v lnh tng. V vy vng lp ny c thit k c bit lp li mt hnh ng vi mt s ln xc nh. 1. initialization c thc hin. Ni chung n t mt gi kh ban u cho bin iu khin. Lnh ny c thc hin ch mt ln. 2. condition c kim tra, nu n l ng vng lp tip tc cn nu khng vng lp kt thc v statement c b qua. 3. statement c thc hin. N c th l mt lnh n hoc l mt khi lnh c bao trong mt cp ngoc nhn. 4. Cui cng, increase c thc hin tng bin iu khin v vng lp quay tr li bc 2. V d.
for(int i = 1; i <= 128; i = i*2) { PORTD = i ; }
Cu trc sau s lp v hn, ging nh cu trc while (1) :

for(;;) { // Statement } H Khoa Hc T Nhin TP. H Ch Minh - 2007
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d. Lnh r nhnh break v continue

S dng break chng ta c th thot khi vng lp ngay c khi iu kin n kt thc cha c tho mn. Lnh ny c th c dng kt thc mt vng lp khng xc nh hay buc n phi kt thc gia chng thay v kt thc mt cch bnh thng. Lnh continue lm cho chng trnh b qua phn cn li ca vng lp v nhy sang ln lp tip theo.
V d 1.
int n; for (n=10; n>0; n--) { PORTD = n ; if (n== 7) { break; } } Chng trnh trn s cho PORTD = 10, 9, 8, 7.
Ch , nu sa li th t on code trn nh sau:

int n; for (n=10; n>0; n--) { if (n== 7) { break; } PORTD = n ; }
Th PORTD = 10, 9, 8. V d 2.
for (int n=10; n>0; n--) { if (n==5) continue; PORTD = n ; H Khoa Hc T Nhin TP. H Ch Minh - 2007
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VI IU KHIN AVR ATmega 128 } Kt qu l PORTD = 10, 9, 8, 7, 6, 4, 3, 2, 1.
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Ch , nu sa li th t on code trn nh sau:

for (int n=10; n>0; n--) { PORTD = n ; if (n==5) continue; }
Th PORTD = 10, 9, 8, 7, 6, 5, 4, 3, 2, 1.
e. Lnh nhy goto

Lnh goto cho php nhy v iu kin ti bt k im no trong chng trnh. V d.
int n=10; loop : PORTD = n ; n-- ; if (n>0) goto loop; PORTD = 10, 9, 8, 7, 6, 5, 4, 3, 2, 1. loop l nhn ca chng trnh, ging cch vit trong hp ng.
, lnh n-- ,lnh ny s gim n i 1. Ta c th vit gn hai cu lnh:

PORTD = n ; n-- ; thnh: PORTD = n--; lnh ny c hiu l thc hin php gn trc ri mi gim n i 1. Nu sa li thnh PORTD = --n ; th s gim n i 1 ri mi thc hin php gn.
Tc tng ng vi:
n-- ; PORTD = n ; Lc ny PORTD = 9, 8, 7, 6, 5, 4, 3, 2, 1. Trng hp ++n v n++ cng hiu tng t, vi du + ch s tng ln.
f. Cu trc la chn switch

95
VI IU KHIN AVR ATmega 128 switch (expression) { case constant1: block of instructions 1 break; case constant2: block of instructions 2 break; . . . . . . . . . default: default block of instructions }
L Trung Thng
Switch hot ng theo cch sau: switch tnh biu thc v kim tra xem n c bng constant1 hay khng, nu ng th n thc hin block of instructions 1 cho n khi tm thy t kho break, sau nhy n phn cui ca cu trc la chn switch. Cn nu khng, switch s kim tra xem biu thc c bng constant2 hay khng. Nu ng n s thc hin block of instructions 2 cho n khi tm thy t kho break. Cui cng, nu gi tr biu thc khng bng bt k hng no c ch nh trn (bn c th ch nh bao nhiu cu lnh case tu thch), chng trnh s thc hin cc lnh trong phn default nu n tn ti v phn ny khng bt buc phi c. C s tng t gia lnh Switch v cu trc if else.
switch (x) { case 1: PORTD = 0x01; break; case 2: PORTD = 0x02; break; default: PORTD = 0x00; }
Tng ng vi :
if (x == 1) { PORTD = 0x01; }
96
VI IU KHIN AVR ATmega 128 else if (x == 2) { PORTD = 0x02; } else { PORTD = 0x00; }
L Trung Thng
g. Chng Hp Ng Vo Trong Chng Trnh C

c th vit hp ng trong chng trnh C, ta dng ch th #asm v #endasm. Cc thanh ghi R0, R1, R22, R23, R24, R25, R26, R27, R30, R31 c th s dng trong on chng trnh hp ng. V d.
#asm Sei // cho php ngt ton cc #endasm Nu ch vit trn mt dng th c th vit gn l: #asm(sei)
h. T Chc B Nh SRAM
Trnh bin dch phn chia v qun l b nh SRAM ca AVR nh sau (xem nh di). truy xut trc tip ti mt a ch no trong cc vng nh ca AVR ta dng cch sau, cch ny thch hp khi ta mun qun l mt khi nh cho mt chc nng no : Truy xut b nh RAM
unsigned char *Pointer; Pointer=(unsigned char *) 0x90h ; // truy xut vo a ch 0x90h ca SRAM
Truy xut b nh Flash:

flash unsigned char *Pointer; Pointer=(flash unsigned char *)0x90h ; // truy xut vo a ch
// 0x90h ca flash Truy xut b nh Eeprom:

eeprom unsigned char *Pointer; Pointer=(eeprom unsigned char *)0x90h; // truy xut vo a ch
// 0x90h ca eeprom
97
L Trung Thng
Ty theo s lng bin (cc b v ton cc) m trnh bin dch s phn chia kch thc cc vng nh mt cch thch hp. Vng nh heap c th khng c nu trong chng trnh khng s dng n. Vng Stack cng dng lu a ch quay v ca hm, tc cc gi tr ca con tr SP (stack pointer). Nh vy, khc vi hp ng ch c mt vng stack, l ni lu cc gi tr quay v ca chng trnh khi chng trnh cn nhy ti v thc thi mt on chng trnh con no . Trong C, vng data stack ch lu cc bin cc b, cc tham s truyn vo ca hm,.. Cn vng stack cng mi lu a ch quay v ca hm. Vng nh heap dng cp pht bin ng (dynamic variable). Kch thc ca cc vng nh trn c th d dng la chn trong Codevision AVR. (chn Project -> Configure -> C complier ). Ring phn stack cng th trnh bin dch s khi to trong start-up code. ( Nhng ngi mi hc c th cha cn quan tm ti phn ny).
98
L Trung Thng
PH LC:
Gii Thch Cc T Ng Trong Ti Liu

( 1 ) Compare Match (1) : y l mt chc nng ca b nh thi, theo , gi tr ca b nh thi (tc gi tr thanh ghi TCNTn (n=0,..,3)) lin tc c so snh snh vi gi tr ca thanh ghi OCRn (n=0,..,3). Khi hai gi tr ny bng nhau s to ra s thay i mc logic chn OCn (n=0,..,3). Nh , ta c th to ra xung PWM ng ra OCn (n=0,..,3) ca vi iu khin. ( 2 ) Input capture (2) : l tn ca mt chn li vo (ICn, n=1, 3) ca AVR, chn ny ni vi khi input capture unit, chc nng ca khi ny l: Khi c s kin (rising, falling, level) chn input capture th gi tr ca thanh ghi b nh thi (TCNTn, n=1, 3) s c cp nht (copy) vo thanh ghi input capture register (ICRn, n=1, 3). Chc nng ny dng o khong thi gian gia cc s kin. l khi xy ra s kin input capture th s to ra mt ngt, nu ngt input capture c cho php. Ngoi s kin input capture to ra chn ICn, th ng ra ca khi analog Comparator ( ACO ), do c ni vi khi input capture unit nn cng c th to ra s kin input capture. ( 3 ) Falling (3) : Cnh xung ca tn hiu. ( 4 ) Rising (4) : Cnh ln ca tn hiu ( 5 ) Toggle (5) : S thay i mc logic t 0 ln 1 hoc t 1 xung 0. ( 6 ) Force Output Compare ( 6 ) : S kin Compare Match khng phi do s bng nhau ca hai thanh ghi TCNTn (n=0,..,3) v OCRn (n=0,..,3) m xy ra do b p buc bng cch set cc bt FOCnX (n=0,1,X=A,B,C) trong thanh ghi TCCRn. ( 7 ) Global interrupt (7) : Ngt ton cc. Mun cho php bt k mt ngt ring r no hot ng th cng phi cho php ngt ton cc trc. ( 8 ) Prescaler (8) : Khi chc nng gip chia nh gi tr ca xung clock. ( 9 ) Fuse bit (9) : Bit cu ch, cu hnh phn cng cho vi iu khin trc khi n c th hot ng. ( 10 ) Trigger event (10) : Bt c mt s thay i logic no xy ra trn chn (thng l ng vo) ca ca vi iu khin th gi l mt s kin trigger.
Ti Liu Tham Kho

1. Datasheet 8-bit AVR ATmega128 - Copyright 2007 Atmel Corporation. 2. CodeVisionAVR Help - Copyright 1998-2008 by Pavel Haiduc and HP InfoTech.
99

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VI IU KHIN AVR ATmega 128

L Trung Thng Con ngi nh c m m v i

. Ti liu ny trc y l seminar ca ti v vi iu khin AVR vo khong

Si Gn, 08-2008. L Trung Thng. TVT - K2002.

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

Hnh 1.2. Cu trc ca Vi iu khin AVR

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

Chng II CU TRC B NH V CNG VO - RA I. CU TRC B NH Gii Thiu:

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

Hnh 2.1 B nh chng trnh c v khng c s dng boot loader

B Nh D Liu : B nh d liu ca AVR chia lm 2 phn chnh l b nh

VI IU KHIN AVR ATmega 128

Hnh 2.2 Bn b nh d liu A : Ch bnh thng B: Ch tng thch ATmega103

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

$01 Thanh ghi PIN E

64 thanh ghi vao ra

Thanh ghi SPH

$3F Thanh ghi SREG $005F

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

Tm li ghi vo EEPROM ta cn thc hin cc bc sau:

EEPROM_write: ; ch cho bit EEWE v 0

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

Tm tc: Bn b nh bn trong ca ATmega128 c th tm tc li nh sau:

128 Kbyte 4 Kbyte SRAM noi 8 Bit

II. CNG VO RA II.1. GII THIU

VI IU KHIN AVR ATmega 128

II.2. CCH HOT NG :

a. Thanh Ghi DDRx.

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

Thanh ghi DDRA

b. Thanh Ghi PORTx.

Thanh ghi PORTA

c. Thanh Ghi PINx.

Thanh ghi PINA

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

Hnh 30. S mt cng vo ra

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

H Khoa Hc T Nhin TP. H Ch Minh - 2007

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

VI IU KHIN AVR ATmega 128

Bng 62. La chn tc xung clock