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Hng dn lp trnh Assembly Cho AVR

s dng AVRstudio 4.2 Hng dn lp trnh AVR vi ni dung hng dn cc bn mi lm quen vi vi iu khin AVR v phn mm AVRstudio4.2 . Ni dung chnh ca ti liu ny l . Hng dn cc bn cch vit mt chng trnh assembly v iu khin vo ra d liu. Ti liu ny c chia lm 3 phn: Phn 1: Cc ch th hp dch trong ASSEMBLY. Phn 2:Vit m lnh cho mt chng trnh ASSEMBLY. Phn3: iu khin vo ra d liu v cc thit b tch hp trong AVR.

Phn 1: Cc ch th hp dch. Chng trnh dch Assembly lm vic trn file chng trnh ngun v mt file ngun bao gm : cc lnh , cc nhn v cc ch dn.Chng c xp tun t trong file ngun. Mt dng lnh c chiu di cc i l :120 k t. Mi dng lnh u c th t trc bi mt nhn,n l mt chui k t v kt thc bng du 2 chm.Nhn c s dng nh l ch cho cc lnh nhy, V cc ch th r nhnh.V cn c s dng nh l tn bin trong b nh chng trnh v b nh d liu. Mt dng lnh c th l mt trong bn dng sau: 1. [nhan: ] ch_th [ton_hng] [;li ch thch] 2. [nhan: ] lnh [ton_hng] [;li ch thch] 3. ;ch thch 4. dng trng (khng cha k t no) Mt li ch thch lun i sau du chm phy(;)v n khng c dch sang m my ch c tc dng cho ngi c chng trnh d hiu. Chng trnh Assembly h tr mt s cc ch th.Cc ch th ny khng c dch ra m nh phn (m my).V n c s dng iwuf khin qu trnh dch v c th l : iu khiu ghi lnh vo b nh chng trnh, nh ngha cc bin 1

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Di y l bng cc ch th : Ch th M t BYTE nh ngha mt bin kiu byte CSEG on m chng trnh DB nh ngha mt hng s kiu byte DEF nh ngha mt tn gi nh cho mt thanh ghi DEVICE nh ngha loi VK cho chng trnh DSEG on d liu DW nh ngha mt hng s kiu 2 byte (word) ENDMACRO Kt thc ca mt macro EQU Thay mt biu thc bng mt k t. ESEG on EEPROM EXIT Thot ra t mt file INCLUDE S dng m ngun t mt file khc LIST Cho php to ra trong file list LISTMAC Cho php thm macro vo list khi c gi MACRO Bt u macro NOLIST Khng cho php to ra trong file list ORG Thit lp mc ca chng trnh SET Gn mt nhn cho mt gi tr Tt c cc ch th u t sau du chm (.). 1.1.BYTE : Ch th ny ginh trc ti nguyn b nh trong SRAM.Ch th ny phi i sau mt nhn v c mt tham s,n ch ra s byte c ginh trc.Ch th ny ch dng trong on d liu. C php : LABEL: .BYTE expression V d: .DSEG var1: .BYTE 1 ; var2 : .BYTE 10; .CSEG ldi r30,low(var1); Nu nh bn no hc qua mt ngn ng cp cao no th thc ra vng nh ny cng nh l mt bin.D liu s khng t ng c ghi vo v ch khi bn dng cc lnh tc ng n n m thi.Nhn chnh l a ch u ca on b nh c ginh trc . 2

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1.2.Ch th CSEG: Ch th ny nh ngha im bt u ca on m chng trnh.Mt file ngun assembly c th cha nhiu on m chng trnh ,v chng li c lin kt thnh mt on m lnh khi dch.Ch th BYTE khng c s dng trong on ny.Mt on chng trnh nu khng c nh ngha l m lnh hay d liu th u c mc nh l on m lnh.Mi on m linh th c mt a ch ring 16 bit (hay l mt t).Ch th ORG c th c s dng t v tr ca cc on m lnh v hng s trong b nh chng trnh .Ch th ny khng km theo bt k mt tham s no. C php: .CSEG V d: .DSEG var1: .BYTE 1 .CSEG CONST: .DW 2 MOV R1,R0

1.3.DB: nh ngha cc hng s kiu byte c lu trong b nh chng trnh hac b nh EEPROM.V ch th ny lun theo sau mt nhn .Ch th ny thng c s dng trong vic lu gi cc bng v cc biu thc (nhng c th tnh ra gi tr cui cng) .Cc nhn chnh l a ch khi u cho gi tr ban u ca bng.Ch dn ny ch c th t c trong on m hoc on b nh EEPROM. Cc phn t trong bng c phn bit bng du phy. C php: Label: .DB danh_sach_biu_thc V d: .CSEG Sin: .DB 0,1,2,3,4,6,7 .ESEG const: .DB 1,2,3 Ch : Mt s hay mt biu thc (phi c kt qu) nm trong khong 128 n 255.Nu s l s m th s c lu di dng 8bit m b 2. 4.DEF: 3

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Ch th ny c tc dng cho php lp trnh vin t tn cho mt thanh ghi.Thay bng nh thanh ghi lp trnh vin c th t tn cho n vi ci tn gi nh hn . C php: .DEF tn_gi_nh=thanh_ghi V d: .DEF xh=R28 .DEF xl=R29 Ch : Mt thanh ghi c th c rt nhiu tn gi nh gn cho n nhng iu s rt nguy him c th v tnh bn lm mt d liu trong thanh ghi m bn khng mong mun. 1.5.DEVICE: Ch th ny ch cho chng trnh dch bit loi vi iu khin m ta ang vit chng trnh. C php: .DEVICE Loi_vi_iu_khin V d: .DEVICE AT90S8535 Ch th ny s bo cho chng ta nhng li sinh ra khi m chng trnh dch tm thy nhng lnh cng nh nhng thitb ngoi vi khng c h tr trong loi vi iu khin ny. 1.6.DSEG: Ch th ny nh ngha im bt u ca on d liu.Mt file ngun c th c nhiu on d liu nhng khi dch chng th chng c gp lin kt vo mt on.Mt on d liu bnh thng ch cha duy nht ch th BYTE.Mi on d liu u c mt con tr v tr ring v l con tr 8 bit (v chng trong b nh RAM).Ch th ORG c th c s dng t cc bin ti cc v tr xc nh trong RAM (ch th ny s c ni sau). C php: .DSEG var1: .BYTE 1 table: .BYTE table_size 1.7.DW: y l ch th cho php ngi s dng nh ngha cc hng s dng 2 byte trong b nh chng trnh hoc bn nh EEPROM n hon ton tng t nh ch th DB. C php: Label: .DW danh_sch_biu_thc V d: Var: .DW 12,354,3434,31345 4

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1.8.ENDMACRO: Kt thc ca mt macro.Ch th ny khng i km mt tham s no c. C php: .Endmacro V d: .Macro subi16 subi r16,low(@0) subi r17,high(@0) .Endmacro 1.9.EQU: Ch th EQU gn gi tr ca mt biu thc cho mt nhn.Nhn sau khi gn gi tr tr thnh mt hng s v khng c nh li gi tr. C php: .EQU const=expression V d: .EQU io=0x23 .EQU ios=io-10 1.10. ESEG: Hon ton ging vi CSEG 1.11. EXIT: Ch th EXIT bo cho chng trnh dch bit dng vic c file li.Bnh thng th chng trnh dch s chy cho ti khi ht file th kt thc.Nhng nu nh trong file c cha ch th ny th khi no chng trnh dch gp ch th ny th s kt thc qa trnh c. C php: . EXIT 1.12.INCLUDE Ch th ny bo cho chng trnh dch bit bt u c t mt file xc nh cho ti khi ht file hoc mt ch th ngng c (EXIT). C php: .Include tn_file ; i khi c tn file v ng dn. V d: ;Ni dung ca file iodef.asm .EQU sreg = 0x3f .EQU sphigh=0x3e .EQU splow=0x3d ;Trong chng trnh .INCLUDE iodef.asm in r0,sreg ; c thanh ghi trang thi. 1.13.LIST: 5

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Cho php chng trnh dch to ra file list. C php: .LIST Ch :Mc nh ca chng trnh dch l cho php to ra file list v ch th ny lun i km vi ch th NOLIST. 1.14.LISTMAC: Hon ton ging vi LIST nhng vi macro. 1.15.MACRO: Ch dn khai bo macro.Vy macro l g? Macro thc ra l mt on chng trnh .Khi m macro c gi th on chng trnh s c dn vo v tr gi macro. Tham s i theo ngay sau ch th ny l tn ca macro.Mt macro c th c ti 10 tham s. C php: .Macro macro_name V d: .Macro sub16 ..;lnh g .;lnh no .Endmacro .CSEG sub16 ;goi macro 1.16.NOLIST: 1.17. ORG: Ch th ORG thit lp mt con tr tuyt i .Gi tr c thit lp chnh l tham s cho ch th ny.Nu nh ch th ny nm trong on d liu th v tr c thit lp chnh l mt v tr trong SRAM v c th l v tr bt u ca bin c khai bo sau ch th BYTE. Cn khi ch th ny c khai bo trong on chng trnh th v tr tuyt i nm trong b nh chng trnh v on m lnh theo sau n s c ghi vo bin nh chng trnh t con tr .V i vi on ESEG cng tng t.Nu nh ch th ny i sau mt nhn th nhn c gi tr chnh bng tham s ca ch th ny. C php: . org tham_s hoc Label: . org tham_s V d: .DSEG . org 0x60 var1: .BYTE 2 6

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. ESEG . org 0x20 evar: .DB 0xff .CSEG . org 0x10 mov r0,r1 1.18.SET: Gn mt gi tr cho mt nhn.Nhn ny c th s dng thay cho gi tr v n hon ton c th b thay i ph thuc vo chng trnh.( y l im khc bit ca n so vi ch th EQU). Mt s ch th khc : .IFDEF <symbol> .IFNDEF <symbol> .IF <expression> .IFDEF <symbol> |.IFNDEF <symbol> ... .ELSE | .ELIF<expression> ... .ENDIF V d: .MACRO SET_BAT .IF @0>0x3F .MESSAGE "Address larger than 0x3f" lds @2, @0 sbr @2, (1<<@1) sts @0, @2 .ELSE .MESSAGE "Address less or equal 0x3f" .ENDIF .ENDMACRO

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Phn 2: Vit lnh cho VK Trc khi chng ta vit lnh cho VK th cn nm c cc vn sau: 1.Cu trc b nh chng trnh v b nh d liu. 2. Cc cch nh a ch. 3.Cc thanh ghi chc nng c bit. 4.Cc lnh c th 5.Mt chng trnh mu. 6.Lp trnh cu trc. 7.Chng trnh con v Macro. Ta ln lt tm hiu tng ni dung.

2.1.Cu trc b nh:

Cng nh mi vi iu khin khc AVR c cu trc Harvard tc l c b nh v ng bus ring cho b nh chng trnh v b nh d liu. S b nh:

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Ta thy khng gian b nh ca b nh chng trnh gm 4Kx8 v c a ch nh t 0000H ti FFFH. B nh d liu gm hai phn :b nh RAM v b nh EEPROM trong khng gian b nh RAM li chia lm 3 phn :Cc thanh ghi chc nng chung,cc thanh ghi vo ra v cui cng l 512 byte b nh SRAM . B nh EEPROM mc d cng l mt phn ca b nh d liu nhng li hon ton ng c lp nh mt b nh c lp v cng c nh a ch ring. 2.1.1.B nh d liu: Cc thanh ghi chc nng chung:AVR c 32 thanh ghi chc nng chung v chng c lin kt trc tip vi ALU y l im khc bit ca AVR v to cho n mt tc x l cc cao.Cc thanh ghi c t tn t R0 ti R31.V c bit cp 6 thanh ghi cui (t R6 ti R31) tng i mt tao thnh cc thanh ghi 16 bit s dng lm con tr tr ti b nh chng trnh v d liu. Chng ln lt c tn l X,Y,Z (v s tm hiu k hn phn sau). Khng gian cc thanh ghi cng vo ra bao gm c thanh ghi d liu v thanh ghi iu khin cho cng vo ra.(Phn ny s c ni ti trong phn lp trnh cho cc thit b ngoi vi). Cui cng l b nh SRAM. 2.1.2.B nh chng trnh: Vi b nh chng trnh c a ch t 0000H ti 0010H c ginh cho bng vc t ngt. c th: a ch b nh Ngun bo ngt Ngt $0000 RESET Khi ng li h thng $001 INT0 Ngt ngoi 0 $002 INT1 Ngt ngoi 1 $003 TIMER2 COMP b so snh timer2 $004 TIMER2 over Trn b m/nh thi 2 $005 TIMER1 CAPT $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F 9

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$010 $011

Ht vc t ngt.

2.2.Cc ch chuy nhp a ch ca AVR:

2.2.1. a ch thanh ghi n trc tip:

ch d ny da ch ca thanh ghi c ly trc tip t vng cc thanh ghi (t 0 ti 31) V d: COM Rd NEG Rd 2.2.2. a ch hai thanh ghi trc tip: y l ch m trong mt lnh ALU truy nhp trc tip vo hai thanh ghi.

Ch ny hon ton tng tng nh ch trn. V d: ADD Rd,Rr 2.2.3. a ch trc tip cng vo ra:

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Trong a ch ca ton hng c cha trong 6 bit ca mt t lnh .n l a ch ca thanh ghi ngun hoc ch. V d: Out DDRB,R16 In R12, DDRB 2.2.4.Trc tip d liu: a ch ca d liu trong RAM c a trc tip vo lnh V d: LDS R12,0x0fff STS 0x0fff,R11 2.2.5. a ch d liu dn tip cng vi dch chuyn: V d: LDD R11,Y+10 a ch ca ton hng ngun hac ch c tr bi thanh ghi Y hoc Z cng thm mt ch s no 2.2.6. a ch gin tip d liu: y l cch m CPU truy nhp ti d liu trong RAM thng qua thanh ghi X,Y,Z a ch ca d liu c lu trong thanh ghi ny. V d: ST X,R11 LD R13,Y 2.2.7. a ch d liu dn tip cng vi tng hoc gim con tr: V d: LD R17,X+ LD -Y,R14 . 11

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2.2.8. a ch ca hng s trong b nh chng trnh. Cch ny ch s dng cho lnh LPM a ch ca hng s c lu trong thanh ghi Z V d: LDI R30,0x07;dia chi truc tiep du lieu 0x07 LDI R31,0xFF LPM ; a ni dung ca nh c a ch trong Z (0x07FF )v thanh ghi R0. 2.2.9. a ch b nh chng trnh gian tip: a ch on m c tr bi thanh ghi Z s dng trong cc lnh IJMP v ICALL. V d: Label: LDI R29,High(Label) LDI R28,Low(Lebel) ICALL 2.2.10. a ch tng di ca b nh chng trnh. Cc nh a ch ny dng cho cc lnh RJMPv RCALL khi CPU s c gi tr PC+k+1 V d: Label: LDI R29,High(Label) LDI R28,Low(Lebel) RCALL Label

2.3.Cc thanh ghi chc nng c bit:

Bao gm cc thanh ghi d liu v cc thanh ghi iu khin cc cng vo ra.Chng c th truy nhp c bng 2 cch: Bng a ch trc tip V d nh: STR $3F,R11 hoc: STR SREG.R11 Ta c th truy nhp gin tip chng thng qua thanh ghi X,Y,Z V d : LDI R28,0x00 LDI R27,0x5F STD X,R11 hai v d ny hon ton tng ng. u ghi d liu vo thanh ghi SREG. C th tng thanh ghi v chc nng ca chng s c ni ti trong phn lp trnh cho cc thit b ngoi vi v vo ra d liu.

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y ch gii thiu v thanh ghi rt c bit m thi (Cc thanh ghi khc s tm hiu cc phn lp trnh vo ra d liu v iu khin cc thit b ngoi vi).

Status Register (SREG)

y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php tnh s hc v logic. C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp) Z: Zero Flag ;C zero (Nu kt qu php ton bng 0) N: Negative Flag (Nu kt qu ca php ton l m) V: Twos complement overflow indicator (C ny c thit lp khi trn s b 2) S: N V, For signed tests (S=N XOR V) H: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau) T: Transfer bit used by BLD and BST instructions(c s dng lm ni chung gian trong cc lnh BLD,BST). I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt.Nu bit ny trang thi logic 0 th khng c mt ngt no c phc v.)

Registers and Operands(k hiu cc thanh ghi v cc ton hng)

Rd: Thanh ghi ch (mt trong 32 cc thanh ghi chc nng chung) Rr: Thanh ghi ngun (Mt trong 32 thanh ghi chc nng chung) R: Kt qu sau khi lnh chy. K: Hng s d liu k: Hng s a ch (C th l mt nhn hoc mt a ch c th) b: Bit trong thanh ghi chc nng chung hoc trong thanh ghi chc nng c bit (0-7). s: Bit trong thanh ghi trng thi (0-7). X,Y,Z: Thanh ghi a ch ( tr ti a ch trong RAM ,hoc Z c th tr ti a ch trong ROM). (X=R27:R26, Y=R29:R28 and Z=R31:R30) A: I/O location address q:Ch s cho cc a ch trc tip (0-63).

Stack :Ngn xp.

STACK: L ni lu gi con tr PC cho cc chng trnh con v cc trnh phc v ngt .(C tht l mt vng nh c tnh nng vo sau ra trc) SP: L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc nng c bit 8 bit.C a ch trong cc thanh ghi chc nng c bit l 13

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$3E(Trong b nh RAM l $5E).C nhim v tr ti vng nh trong RAM cha ngn xp. Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngng xp gim hai v tr.V con tr ngn xp s gim 1 khi thc hin lnh push.Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2.Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v.V gi tr ngn xp t nht cng phi ln hn hc bng 60H (0x60) v 5FH tr li l vng cc thanh ghi.

2.4.Cc lnh c th:

C l phn lnh ny cc bn tham kho cun AVR assembly user guide Rt y v chi tit.Ti ch c th hng dn cc bn cch c mt lnh trong m thi. V d: LDI Load Immediate 1.Description: 2. Loads an 8 bit constant directly to register 16 to 31. 3.Operation: 4.(i) Rd K 5.Syntax: Operands: Program Counter: 6.(i) LDI Rd,K 16 d 31, 0 K 255 PC PC + 1 7.16-bit Opcode: 8.Status Register (SREG) and Boolean Formula: 9.Example: clr r31 ; Clear Z high byte ldi r30,$F0 ; Set Z low byte to $F0 lpm ; Load constant from Program ; memory pointed to by Z Words: 1 (2 bytes) Cycles: 1 1110 KKKK dddd KKKK ITHSVNZC on trn m t v lnh ly d liu trc tip . Muc description m t ton b v lnh ny.V tnh nng v cc thanh ghi c s dng trong lnh.

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Cc bn ch ti dng th 5:Dng ny chia lm 3 ct ct 1 :syntax l c php ca cu lnh.Ct 2: Operands l cc ton hng c s dng trong lnh.Cc bn thy ct vit: 16 d 31, 0 K 255. y d tc l Rd hay c th hn l ton hng ny ch c th l cc thanh ghi t R16 ti R31.Cn K l mt s nguyn c gi tr t 0 ti 255. ct th ba cc bn thy program counter : ch s thay i con tr PC khi thc hin lnh ny. Dng s 8: l cc thanh ghi b tc ng sau lnh ny.V dng th 9 l mt v d minh ha. Kinh nghim hc phn ny : Cc bn mun hc tt phn ny th cn phi chiu kh vit cc lnh cng nhiu cng tt. c bit khi vit mt lnh cc bn nn vit c phn gii thch bng tin anh ca n na .V d: ADIW Rd,K add immediate to word V cc bn nh xc nh lnh ny dng kiu nh a ch g.V nh lnh trn th Rd l thanh ghi ch v y l kiu nh a ch trc tip thanh ghi.Cn K l mt hng s t 0 n 255 (8bit).V y l cch nh a ch d liu trc tip. hc c nhiu lnh th cc bn nn hc theo tng nhm lnh v d nh lnh v chuyn d liu: Cc bn c lnh Load nh vy cc bn hy xem lnh ny c nhng kiu nh a ch th no v bn ln lt vit tng lnh v chc chn rng sau mt ln vit th bn nh gn nh ton b cc lnh . Sau khi nm gn nh ton b cc lnh d th cc bn ch n cc c v s tc ng ca chng n tng c mt. c bit ch : Mt s cc lnh ch thc hin vi na s thanh ghi t 16 tr i nh l LDI

2.5.Mt chng trnh mu ;chuong trinh dau tien ;khia bao thiet bi .DEVICE AT90S8535;khai bao thit b .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .def tam=R16 ;dinh nghia mot ten moi cho thanh ghi R16

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.Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start .org 0x0001 rjmp int_0 .org 0x0011 start: ldi xh,0x0 ldi xl,0xa ldi yh,0x0 ldi yl,0x5 sub16 rcall add16 here: rjmp here int_0: ;chuong trinh phuc vu ngat int0 nop reti;tro lai chuong trinh chinh tu ngat add16: ;chuong trinh con cong hai so 16 bit ;bien vao:xh,xl ; yh,yl ;bien ra: :xh,xl va co C add xl,yl adc xh,yh ret y l mt chng trnh u tin v l mt chng trnh rt c bn i vi cc bn.

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3.2.6. Lp trnh cu trc trong Assembly: Mi ngi thng ni y l im mnh cu ngn ng bc cao ! Vng ng vy.Nhng iu khng c ngha l ngn ng cp thp nh assembly li khng lm c. vit c cc dng cu trc nh trong cc ngn ng bc cao i hi cc bn phi vit nhiu v rt nhiu.Sau y ti s vit mt vi v d cc bn tham kho. 1. if (iu kin) { khi lnh } else { khi lnh } v c th nh sau: Nu R10 = 0xff th copy thanh ghi R10 vo thanh ghi R11 v nu khng bng th a gi tr 0 vo thanh ghi R11 ;doan chuong trinh viet theo cach 1: ldi R0,0xff cp R10,R0 brne else mov R11,R10 rjmp endif else: ldi R11,0x00 endif: ;doan chuong trinh viet bang cah 2: ldi R0,0xff cp R10,R0 breq then ldi R11,0x00 rjmp endif then: mov R11,R10 endif: 2. 17

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For (khi to bin,iu kin,ton hng) { khi lnh. } Vit on chng trnh c 10 byte t b nh SRAM bt u t a ch 0x60 ra 10 thanh ghi u tin.chng trnh s dng thanh ghi R16 lm bin con chy v thanh ghi X tr ti a ch ca 10 thanh ghi v thanh ghi Y tr ti b nh SRAM Chng trnh vit di dng cu trc nh sau: For (X=0x00;Y=0x60;R10=10,R10<=0,++X;++Y;--R10) { c ni dung t [Y] a [X] } Chng trnh assembly nh sau: ldi xl,0x00 ;khi to cc bin con chy ldi xh,0x00 ldi yl,0x60 ldi yh,0x00 ldi R16,0xa ldi R17,0x00 loop: cp R16,R17 ;kim tra R16 =0? breq exit ;Nu R16=0 th thot khi cng lp. ld R11,Y+ ;ly d liu t [Y] v tng Y ln 1 ST X+,R11 ;Lu vo [X] v tng X ln 1 dec R16 rjmp loop exit: ;nh vy khi thoat khi vng lp th 10 byte c ly. 3. Do { Khi lnh. } While (iu khin) V d 1: ta c th vit li chng trnh phn 2 nh sau: 18

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Chng trnh assembly nh sau: ldi xl,0x00 ;khi to cc bin con chy ldi xh,0x00 ldi yl,0x60 ldi yh,0x00 ldi R16,0xa loop: ld R11,Y+ ;ly d liu t [Y] v tng Y ln 1 ST X+,R11 ;Lu vo [X] v tng X ln 1 dec R16 brne loop ;kim tra R16 nu nh >0 tip tc vng lp V d 2: Ly d liu t cng PA vo v khi no ly c mt s m th dng li v ghi s vo vng nh 0x064 trong SRAM y l mt vng lp m bn cha h bit trc s ln lp: ;chng trnh c vit nh sau: ldi R16,0x00 sts DDA ,R16 ;nh ngha cng PA l cng vo. ldi R16.0xff sts PORA,R16 ; li vo c a ln pull-up do: in R15,$19 ;ly d liu t cng PORA mov R16,R15 ;copy mt bn ca d liu lsl R16 ;dch tri c c nh ly bit MSB brcc do ;kim tra bit nu bng 0 th lp li qu trnh ly mu ; tm c s m ldi xl,0x64 ;t a ch cho con tr SRAM ldi xh,0x00 st x,R15 ;Lu d liu vo SRAM ;on chng trnh tm c s m t cng PA Cc cu trc cn li cc bn c th t khm ph.V kinh nghim ca ti khi vit v phn ny l vit v vit tht nhiuth bn c th s dng c thnh tho mi cu trc. Nh vy v phn ngn ng lp trnh cho ti gi cc bn thy Assembly cng khng phi l mt ngn ng qu phc tp v khng xy dng c cc ng dng ln.N hon ton c th modul ha cc d n ln v c th thc hin mi cu trc ca bt k ngn ng cp cao no.

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32.7.Chng trnh con v Macro C l khi ni ti chng trnh con th ai cng bit. i vi assembly th chng trnh con ht sc n gin. V d: Sub16: ;chng trnh con cng hai s 16bit ;inputs: ah=R20,al=R19 ; bh=R22,bl=R21 ;outputs ah,al,co c .def ah=R20 .def al=R19 .def bh=R22 .def bl=R21 add al,bl adc ah,bh ret Nh cc bn thy y mt chng trnh con r t n gin.Tn chng trnh con l mt nhn v khi kt thc chng trnh con bng lnh RET.Hot ng ca chong trnh con: V d: .CSEG .include 8535def.inc org 0x0000 rjmp start org 0x0011 start: ldi R20,10 ldi R21,0 ldi R19,0 ldi R22,0x1f rcall sub16 ;goi chuong trinh con here: rjmp here Sub16: ;khai bao chuong trinh con ;chng trnh con cng hai s 16bit ;inputs: ah=R20,al=R19 ; bh=R22,bl=R21 ;outputs ah,al,co c .def ah=R20 .def al=R19 20

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.def .def

bh=R22 bl=R21 add al,bl adc ah,bh

ret ;ket thuc chuong trinh con. Khi chng trnh chnh chy ti lnh gi chong trnh con (rcall sub16 th con tr PC s tr ti ni luugwx chng trnh con v c th l nhn sub16.Thc hin ht cc dng lnh cho ti khi gp lnh RET th con tr PC li tr ti lnh ngay sau lnh rcall.Qu trnh ct PC v khi phc PC th CPU s dng ngn xp.(S c ni sau) Macro: nh ngha Macro trc ht ta hy xt mt v d v Macro: .Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro ;ket thuc macro T v d cc bn c th thy mt macro c khai bo bng ch th macro ( ni trc) (Ti sao li l ch th?).Ti xin c nhc li mt cht l :Ch th l nhng ch dn gip cho chong trnh dich dch cc lnh trong file ngun m thi n khng phi l mt lnh ca vi diu khin (chng ta s li tr li vn ny sau) Nh vy vit mt macro cc bn dng ch dn MACRO khai bo.Tham s i ngay theo sau ch dn ny chnh l tn ca macro (N c ngha g ?)v theo sau tn c th l cc tham s hoc khng (chng c cch nhau bi du phy) Sau khi khai bo macro l khi lnh m cc bn mun thc hin. kt thc macro th cc bn dng ch dn .endmacro Macro s lm vic nh th no ?Ta s tm hiu qua v d sau: ;chuong trinh su dung macro ;khia bao thiet bi .DEVICE AT90S8535 .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .Macro sub16 ;khai bao macro 21

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;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 ;bat dau chuong trinh chinh rjmp start .org 0x0011 start: ldi xh,0x0 ;khoi tao cac thanh ghi ldi xl,0xa ldi yh,0x0 ldi yl,0x5 sub16 ;gi macro Cc bn nhn thy y :Macro c s dng tr hai s 16 bit vi bin u vo l thanh ghi x v thanh ghi y.Kt qu c lu vo thanh ghi x. Khi dch chng trnh ny ra m my th khi gp lnh gi macro (lnh sub16)th chng trnh dch s copy v dn ton b ni dung bn trong ca hai ch dn .macro v .endmacro vo v tr c lnh gi. C th chng trnh trn tng ng vi chng trnh sau: ;chuong trinh dau tien ;khia bao thiet bi .DEVICE AT90S8535 .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start .org 0x0011 start: ldi xh,0x0 ldi xl,0xa ldi yh,0x0 22

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ldi yl,0x5 sub xl,yl sbc xh,yh .Nh vy n by gii c l cc bn bit c th no l mt macro !.Vy macro l mt on chng trnh m khi c lnh gi n chng trnh dch s dn ni dung rong macro vo v tr gi n.V y l l do v ngi ta gi l ch th macro !!!Ch khi s dng macro:Do macro c thit k vi mc ch modul ha cc on chng trnh v c th dng lai nhiu ln (V d bn vit mt file lu gi tng macro v khi cn th bn ch cn include chng vo file d n ca bn l c (Phn ny th c l cc bn mi hc th hi kh nm bt ti s ni n trong phn modul ha chng trnh ln)).V v mt mc ch n gin na l cc bn khng phi vit i vit li nhiu ln mt on chng trnh.V vy phn gii thiu v macro l phn rt quan trng.Mc d chng khng c dch ra m my (chng ch l nhng ch dn gip cho ngi c chng trnh d hiu)nh n s lm cho nhng ngi s dng n d hiu v c th s dng c chng. S khc nhau gia chng trnh con v Macro l g ? Cu hi ny c l rt nhiu bn thc mc ?nhng sau khi tm hiu v chng trnh con v macro c l cc bn cng t tr li c.Nhng ti cng xin tm li cht t nh sau: Th nht:Chng trnh con l mt c ch m CPU cho php thay i v tr truy nhp b nh chng trnh(khi c lnh gi chng trnh con th CPU truy nhp ti ni lu chung trnh con v khi gp lnh RET th CPU tr li chng trnh chnh) cn Macro ch l ch th chng trnh dch bit cch copy nhng on chng trnh ging nhau vo nhng v tr xc nh (v tr gi macro). Th hai: V mt s dng ty tng ng dng m ta s dng chng trnh con hay Macro.Nu nh bn mun tit kim b nh tc l nhiu on ging nhau th ta ch cn vit mt on v t mt ni trong b nh khi cn dng n n th cho con tr PC tr ti n sau khi dng xong th tr li chung trnh chnh (chng trnh con).Nhng mi ln tr ti n nh th th bn s rt mt thi gian (v cc lnh gi chng trnh v tr v chng trnh chnh s ngn i ca bn chng 3 chu k my)nh vy th nu bn t lun on chng trnh cn chy ngay th tit kim c 3 chu k my (Macro).Nh vy c hai phng php ny u c im manh v im yu v chng tri ngc nhau.Ty mc ch s dng m cc bn nn chn loi no. Phng php modul ha chng trnh: Nh bao ngi vn quan nim.Ngn ng assembly ch dng hc v vi iu khin ch khng th s dng vi cc ng dng ln c.V mi ngi 23

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thng ni C hay Pascal hoc Basic mi thch hp vi iu .y thc s l mt quan nim rt sai lm !!!Ti s gii thiu cho cc bn mt phng php modul ha (chia nh)mt d n ln thnh cc chng trnh nh.i vi AVR studio vic ny l hon ton n gin. Ta c th lm mt v d: Gi s bn tao mt d n mi c tn l thu v tt nhin file asembly do chng trnh t tao ra cng c tn l thu.asm v c ni dung nh sau: ;chuong trinh dau tien ;khia bao thiet bi .DEVICE AT90S8535;khai bao thit b .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .def tam=R16 ;dinh nghia mot ten moi cho thanh ghi R16

.Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start .org 0x0001 rjmp int_0 .org 0x0011 start: ldi xh,0x0 ldi xl,0xa ldi yh,0x0 ldi yl,0x5 sub16 rcall add16 here: rjmp here 24

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int_0: ;chuong trinh phuc vu ngat int0 nop reti;tro lai chuong trinh chinh tu ngat add16: ;chuong trinh con cong hai so 16 bit ;bien vao:xh,xl ; yh,yl ;bien ra: :xh,xl va co C add xl,yl adc xh,yh ret Nh vy trong chng trnh ca ti c 1 macro.Ti s nhm tt c cc macro v a vo mt file khc. lm iu ny ti vo project chn create new file sau nh tn file l macro.asm(hoc macro.inc hoc tn bt k nh c ui l .asm hoc .inc)v ghi vo th mc c cha d n. vi ni dung file nh sau: .Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro V chng trnh ca ti c vit li nh sau: ;chuong trinh duoc viet lai ;khia bao thiet bi .DEVICE AT90S8535 .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .def tam=R16 ;dinh nghia mot ten moi cho thanh ghi R16

.include "macro.asm" ;mo file chua cac modul va doc .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start 25

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.org 0x0001 rjmp int_0 .org 0x0011 start: ldi xh,0x0 ldi xl,0xa ldi yh,0x0 ldi yl,0x5 sub16 rcall add16 here: rjmp here int_0: ;chuong trinh phuc vu ngat int0 nop reti;tro lai chuong trinh chinh tu ngat add16: ;chuong trinh con cong hai so 16 bit ;bien vao:xh,xl ; yh,yl ;bien ra: :xh,xl va co C add xl,yl adc xh,yh ret Nh vy thay vo v tr t macro ti thay vo bng ch th include :m file macro.asm v c (khi bin dch ). V tr t ca ch th ny khng nht thit nm v tr khia bo macro m ch cn n t v tr trc khi gi macro l c. Mt file c th lu rt nhiu macro m d n ca bn cn. trn cc bn c ti phn tch cch lm thng qua mt v d c th.n lt cc bn,nu nh cc bn mun lm mt d n ln c nhiu lp trnh vin th cn phi c ngi qun tr d n y l ngi c vai tr tch mt chng trnh ln thnh cc chng trnh nh v giao nhim v cho tng lp trnh vin .Cui cng ngi cn c nhim v ghp cc modul nh li thnh mt chng trnh hon chnh. Ch :khng ch c macro m bn c th tch tng khi no ca chng trnh vo mt file khc v lin kt n bng ch th include nhng ch th ny cn t ng v tr m khi lnh c t chng trnh chnh

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Phn 3:Vo ra d liu v lp trnh cho cc thit b ngoi vi.

Mt vi iu khin th nh cc bn bit n bao gm CPU l b no trung tm ca n.Nhng n khng th ng c lp c.v x l c d liu th tt nhin n phi ly d liu t mt ngun d li no .Cc thit b ngoi vi trn n v cc port chnh l cc thit b trung gian a d liu vo cho CPU v chuyn d liu x l ra cc c cu chp hnh v ln mng thng tnQu trnh vo ra d liu l qu trnh iu khin cc port cc thit b ngoi vi sao cho CPU c th nhp hc xut d liu mt cch ng b C 3 phng php vo ra d liu l:vo ra d liu bng chng trnh,vo ra d liu bng ngt v vo ra d liu bng DMA. y vi iu khin AVR ch c hai phng php trn cn DMA cc bn mun tm hiu thm c th xem to liu v 8086 hc Pentum. 1.Vo ra d liu bng chng trnh : y l phng php m CPU hi thit b ngoi vi v kh nng s sng chao i d liu.Phng php ny c hai ch l ch u tin v ch bnh n.Ch u tin l ch :

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ch ny th thit b c quyn u tin s chao i d liu xong mi ti thit b c mc u tin thp hn. Ch bnh ng:

V tng thit b mt s c hi nu nh khng c nhu cu chao i d liu th CPU s hi thit b khc. u im ca phng php ny l: CPU ch ng v phn c quyn u tin.Nhng nhc im ca phng ohp ny l :Khng p ng c cc s kin tc thi xy ra (V nh c mt thit b c yu cu chao i d liu khn cp m vn ch ti lt c hi),v trong thi gian hi trng thi ca cc thit b th cpu khng th lm vic khc, iu ny lm lng ph ti nguyn x l ca CPU. 2.Phng php vo ra bng ngt. Ngt l nguyn tc cho php thit b ngoi vi bo cho CPU bit v kh nng sn sng chao i d liu ca mnh. Cc bn c th t tm thy u v nhc im ca phng php ny. Trn VK c 32 ng vo ra gm nhiu chc nng c th s dng lm cng vo ra s ,cho cc thit b ngoi vi tng t.Sau y ta s tm hiu tng thit b ngoi vi v cc cng vo ra.(mc ch ca phn ny l hiu c cu to v c th iu khin vo ra d liu c chng).

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3.1.Cng vo ra: Vi iu khin AT90S8535 c 32 ng vo ra chia lm bn nhm 8bit mt.Cc ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y chng ta s xet chng l cc cng vo ra s.Nu xt trn mt ny th cc cng vo ra ny l cng vo ra hai chiu c th nh hng theo tng bit.V cha c in tr pull-up (c th lp trnh c).Mc d mi port c cc c im ring nhng khi xet chng l cc cng vo ra s th dng nh iu khin vo ra d liu th hon ton nh nhau.Chng ta c thanh ghi v mt a ch cng i vi mi cng , l : thanh ghi d liu cng (PORTA,PORTB,PORTC),thanh ghi d liu iu khin cng (DDRA, DDRB, DDRC)v cui cng l a ch chn vo ca cng(PINA,PINB,PINC) 1.Thanh ghi DDRA: y l thanh ghi 8 bit (cc bn c th c v ghi cc bit thanh ghi ny) v c tc dng iu khin hng cng PA(tc l cng ra hay cng vo).Nu nh mt bit trong thanh ghi ny c set th bit tng ng trn PA c nh ngha nh mt cng ra.Ngc li nu nh bit khng c set th bit tng ng trn PA c nh ngha l cng vo. 2.Thanh ghi PORTA: y cng l thanh ghi 8 bit (cc bit c th c v ghi c) n l thanh ghi d liu ca cng PA v trong trng hp nu cng c nh ngha l cng ra th khi ta ghi mt bit ln thanh ghi ny th chn tng ng trn port cng c cng mc logic. Trong trng hp m cng c nh ngha l cng vo th thanh ghi ny li mang d liu iu khin cng.C th nu bit no ca thanh ghi ny c set (a ln mc 1) th in tr cheo (pull-up)ca chn tng ng ca port s c kh hot.Ngc li n s trng thi cao tr. Thanh ghi ny sau khi kh ng VK s c gi tr l 0x00. 3. a ch chn vo PINA: y l a ch cho php truy nhp trc tip ra cc chn vt l ca vi iu khin.Tt nhin v th m vi a ch ny bn ch c th c m thi(Khng th ghi c!!!) Ta c bng tm tt sau: DDAn PORTAn I/O Pull-up Ch thch 0 0 cng vo Khng Cao tr 0 1 cng vo C 1 0 cng ra Khng u ra y ko 1 1 cng ra Khng u ra y ko Trong : DDAn l bit th n trong thanh ghi DDA Bng cc thanh ghi v a ch ca chng cho tng PORT 30

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PORT A A A B B B C C C D D D

Tn PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND

a ch thanh ghi/a ch trong SRAM 0x1B/0x3B 0x1A/0x3A 0x19/0x39 0x18/0x38 0x17/0x37 0x16/0x36 0x15/0x35 0x14/0x34 0x13/0x33 0x12/0x32 0x11/0x31 0x10/0x30

Tm li: 1. c d liu t ngoi th ta phi thc hin cc bc sau: Da d liu ra thanh ghi iu khin DDRxn t cho PORT (hoc bit trong port) l u vo (xa thanh ghi ddr hoc bit) Sau kch hot in tr pull-up bng cch set thanh ghi PORT( bit) Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit) Sau y l mt v d: V d 1: c cng PA vo thanh ghi R16 ;chng trnh bt u ldi R17,0x00 sts $3a,R17 ; nh ngha port A l cng vo ser R17 ;set thanh ghi R17 sts $3b,R17 ;Kch hot in tr pull-up in R16,PINA V d 2 : t cng PA thanh hai na byte.Mt na thp l cng ra cn na cao l cng vo. Ldi R17,0x0f Out DDRA,R17 ; nh ngha SER R17 OUT PORTA,R17 IN R16,PINA

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Nh cc bn thy y ! hai on chng trnh trn ti ch thay d liu mi ca thanh ghi DDRA.Hai on lnh ny ti s dng cc kiu nh da ch khc nhau do cc bn cm tng nh hon ton khc nha. Thc ra th lnh: OUT DDRA,R17 Hon ton tng ng vi: STS 0x3a,R17 . V d 3: c d liu t bit 4 ca cng PA Cc bc tin hnh: t bit 4 ca cng PA l u vo .Sau kch hot in tr pull-up v cui cng l ly d liu. ;chuong trinh duoc viet nhu sau: .def tam=R17 ;dinh nghia ten moi cho R17 de se su dung lid tam,0b11110111 OUT DDRA,tam SER tam ;dua thanh ghi nay len 0xff OUT PORTA,tam INT tam,PINA BST tam,0x4 ;bit nay duoc luu vao co T ;het 2. a d liu t VK ra cc port cng c cc bc hon ton tng t.Ban u cc bn cng phi nh ngha l cng ra bng cch set bit tng ng ca cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx. 3.2.Ngt v lp trnh ngt. Cc kin thc v ngt c l cc bn nm c trong mn vi x l 1 ti ch nhc li mt s ki nim c bn:Ngt l mt c ch cho php thit b ngoi vi bo cho CPU bit v tnh trng sn xng cho i d liu ca mnh.V d:Khi b truyn nhn UART nhn c mt byte n s bo cho CPU bit thng qua c RXC,hc khi n truyn c mt byte th c TX c thit lp Phc v ngt: Nu nh ngt c cho php thc hin th: Khi c tn hiu bo ngt.CPU s tm dng cng vic ng thc hin li v lu v tr ang thc hin chng trnh (con tr PC) vo ngn xp sau tr ti vector phuc v ngt v thc hin chng trnh phc v ngt ch ti khi gp lnh RETI (return from interrup) th CPU li ly PC t ngn xp ra v tip tc thc hin chng trnh m trc khi c ngt n ang thc hin. Trong trng hp m c nhiu ngt yu cu cng mt lc th CPU s lu 32

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cc c bo ngt li v thc hin ln lt cc ngt theo mc u tin.Trong khi ang thc hin ngt m xut hin ngt mi th s xy ra hai trng hp .Trng hp ngt ny c mc u tin cao hn th n s c phc v.Cn n m c mc u tin thp hn th n s b b qua. khi phc li v tr thc hin chng trnh chnh th CPU s dng n ngn xp: Vy ngn xp l g ?v n lm u ?.Vng xin tr li l l ngn xp l mt vng nh m c cch truy nhp hi c bit l vo sau ra trcv bn hy tng tng nh trng a CD ca bn cng vy:

Bn thy y bn a vo t ci mt mi ti ci th 3 v mun ly ci th 1 ra th bn khng th tho ra ly m phi ly ci th 3 ri n th 2 ri mi ly c ci th nht (Tm hiu nh th).Nhng trong ti liu ca hng sn xut khng thy ni ti b nh ngn xp?vng n l vng bt k trong SRAM t a ch 0x60 tr ln. truy nhp vo SRAM thng thng th bn dng con tr X,Y,Z v truy nhp vo SRAM theo kiu ngn xp th bn dng con tr SP.Con tr ny l mt thanh ghi 16 bit v c truy nhp nh hai thanh ghi 8 bit chung c a ch :SPL :0x3D/0x5D(IO/SRAM) V SPH:0x3E/0x5E. Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngng xp gim hai v tr.V con tr ngn xp s gim 1 khi thc hin lnh push.Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2.Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi 33

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hoc cc ngt c cho php phc v.V gi tr ngn xp t nht cng phi ln hn 60H (0x60) v 5FH tr li l vng cc thanh ghi. thau gi tr ca SP bn c hai cch: ;Su dung dia chi truc tiep trong cac thanh I/O Ldi R17,0x00 OUT SPH,R17 ;nap gia tri 0x00 vao thanh ghi SPH Ldi R17,0xff OUT SPL ;nap gia tri 0xff vao thanh ghi SPL ;end ;su dung dia chi cua chung gian tiep qua SRAM Ldi R17,0x00 STS 0x5E,R17 Ldi R17,0xFF STS 0x5D,R17 ;end

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3.3.SPI Serial peripheral interface Giao din ni tip thit b ngoi vi: SPI l mt giao din thc hin vic chao i d liu gia cc thit b tng thch vi khung gi liu 8bit v c truyn ng b (cng xung nhp ng h) SPI cho php truyn d liu ni tip ng b gia thit b ngoi vi v vi iu khin AVR hoc gia cc vi iu khin AVR . SPI ca AT90S8535 c cc c im c bit sau: -Ch song cng,truyn d liu ng b 3 dy. -C th gi vai tr Master hoc Slave. -Bit MSB hoc LSB c th c truyn trc ty vo ngi lp trnh. -Bn tc truyn c th lp trnh thng qua hai bit -C ngt bo kt thc truyn -Vn hnh t trng thi ng (c nh thc t trng thi ng). S cu trc:

iu khin khi giao tip SPI th chng ta c 3 thanh ghi. l 1 thanh ghi iu khin:SPCR(SPI control Register).Mt thanh ghi trang thi SPSR (SPI status Register) V cui cng l thanh ghi d liu SPDR(SPI Dt Register). 35

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1.Thanh ghi SPCR: y l thanh ghi 8 bit c a ch trong cc thanh I/O l 0x0D v trong SRAM l 0x2D.cc bit trong thanh ghi ny u c th c hoc ghi. Bit 7-SPIE: SPI interrupt enable Bit ny cho php ngt ca b truyn tin SPI (nu ngt ton cc v ngt ny c cho php th nu c SPIF c bt th ngt s c phc v.) Bit 6-SPE: SPI Enable Nu bit ny c set th khi SPI s c hot ng v n phi c set trong sut qu trnh SPI hot ng. Bit 5-DORD: Data order Khi m DORD c set th LSB ca byte d liu s c truyn trc v ngc li. Bit 4-MSTR: Master/Slave select y l bit dng la chn ch master hay slave.Nu bit ny c set th b SPI ny c vai tr l Master v ngc li.Nu nh SS c cu hnh l li vo v c t xung mc thp th MSTR b xa v 0v SPIF v SPSR b t ln 1 khi bn s phi t li MSTR v 1. Bit 3-CPOL: Clock polarity Khi bit ny c set th SCK mc cao trong trang thi ng v ngc lai . Bit 2-CPHA:Clock Phase Quy nh pha kch hot ca xung nhip. Bit 1,0-SPR1,SPR0 :Clock rate select: y l hai bit iu khin tc xung nhp truyn ca kt ni v c thit lp trn Master.N khng c tc dng g nu nh ta thit lp trn slave. V gi tr ca chng ng theo t hp cc bit nh sau: SPR1 SPR0 Tn s SCK 0 0 Fcl/4 0 1 Fcl/16 1 0 Fcl/64 1 1 Fcl/128 Nh vy y l thanh ghi iu khin ton b khi SPI t vai tr (Master/slave n tc truyn,cho php ngt,cho php hot ng,mc logic trong trang thi ng v pha kch hot xung nhp. V d 1:

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Thit lp giao din SPI vi vai tr Master tc truyn l Fcl/128 pha kch hot xung nhp thp khng cho php ngt v cha cho php hot ng. l c iu trc ht cc bn cn phi thit lp cc chn cho SPI .C th SCK l chn PB7 l output ng ngha vi DDB7 c set.MISO(PB6) l chn vo v vy DDB6 xa v kch hot in tr ko th PORTB6 phi c set ln 1 .MOSI(PB5) l chn ra do DDB5 cn phi set ln 1.SS(PB4) y l chn la chon thit b Slave v vy c nh ngha l chn ra v mc tch cc thp (xa DDB4 v PORTB4). ;on chng trnh nh sau: sbi 0x17,7 ;set bit DDBR7 - t SCK l chn ra. cbi 0x17,6 ;xa bit DDBR6-t PB6 l cng vo. sbi 0x18,6 ;set bit PORTB6-Kch hot in tr ko. sbi 0x17,5 ;t PB5 l chn ra. sbi 0x17,4 cbi 0x18,4 ;t xong cu hnh cc chn ;Tc dng ln tng bit khng nh hng n cc chn khc. ;By gi tip tc t cu hnh cho SPI OUT 0x0d,0b00010111 ;ht. thit lp cho n l Slave th hon ton tng t. 2.Thanh ghi SPSR: y l thanh ghi 8 bit (c a ch 0x0e/0x2e)lu gi trng thi ca b truyn nhn SPI.Nhng n ch c hai bt c nh ngha c kh nng c v ghi.Cc bit cn li khng c nh ngha v khi c chng th c gi tr zero. Bit 7-SPIF: SPI interrupt Flag Khi truyn xong mt byte d liu th bit ny c set v mt ngt c to ra.Nu bit cho php ngt SPIE trong thanh ghi SPCR c set v ngt ton cc c cho php th ngt c thi hnh.Nu khng n s b b qua.Khi m chn ss ca Master c nh ngha l cng vo li c thit lp mc thp th c ny cng c set.N c xa bi phn cng hi ngt c phc v. Bit 6-WCOL: wite collision flag C bo xung t khi ghi:C ny c set ln 1 nu nh d liu c ghi ln thanh ghi d liu SPI khi ang din ra mt cuc truyn.V n c xa cng vi c SPIF khi c thanh ghi trng thi v truy nhp vo thanh ghi d liu. 37

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bt u mt cuc truyn th cc bn cn cho php b truyn nhn hot ng.Khi truyn bn ch cn ghi byte d liu cn truyn ln thanh ghi d liu v i cho ti khi c c SPIF bt ln ri tip tc truyn byte mi. bt u nhn d liu cng vy.SPI c khi ng,ch khi no c SPIF bt ln th ta c d liu (c t xa khi ta c thanh ghi trng thi). 3.Thanh ghi SPDR: y cng l thanh ghi 8 bit (0x0f/0x2f) c th c v ghi c.N c s dng truyn d liu gia hai b truyn nhn SPI.Ghi d liu vo thanh ghi ny c ngha l ta bt u cuc truyn.V c d liu t thanh ghi ny l c d liu c nhn. 4.Nguyn l hot ng: xt hnh sau:

y l s ghp ni gia hai b SPI song cng (nh ca 2 vi iu khin AVR). i vi VK AVR th cc chn SCK (Serial clock) l chn PB7,y l chn xung nhp ra trong trng hp n l Master v l chn xung nhp vo nu n l Slave.khi ghi d liu ln thanh ghi d liu SPDR ca khi Master s khi ng b to xung v d liu c dch v a ra chn MOSI (PB5) v vo chn MOSI ca slave (PB5 i vi AVR).Sau khi dch ht mt byte b to xung ngng hot ng,v c SPIF c pht bo kt thc truyn.Nu nh ngt ny c php th chng trnh phc vu ngt s c phc v v khi c s b xa.u vo la chn slave (SS v l chn PB4) c set mc tch cc thp la chn thit b SPI slave v c dng cho vic ghp ni nhiu VK.Hai thanh ghi dch ca hai b truyn v nhn (Master v slave) c xem nh l mt thanh ghi dch vng 16 bit.V trong mt ln chao i d liu th d liu thanh ghi ca Master v slave chao i cho nhau.Mt bSIP lm ng thi c hai nhim v truyn v nhn nhng chng li ch c mt b m khi truyn c hai b m khi nhn.Nh vy c ngha l d liu truyn i s khng c ghi ln thanh ghi d liu truyn nu nh byte 38

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trc cha c truyn xong (hay c SPIF cha c bt).V khi nhn d liu cng vy d liu cn phi c c trc khi d liu mi c nhn xong. Bng cu hnh chn: Chn Trc tip,Master Trc tip,Slave MOSI Ngi dng nh ngha Chn vo MISO Chn vo Ngi dng nh ngha SCK Ngi dng nh ngha Chn vo SS Ngi dng nh ngha Chn vo Vy nh v d 1 cc bn bit lm th no cu hnh cho giao din SPI Sau y l mt v d c th:

Hai VK AVR c ghp vi nhau theo giao din SPI .Vit chng trnh con lp mt VK l master v ci cn li l Slave.Ly 10 byte trong b nh SRAM k t v tr 0xff g sang vi iu khin th hai. vi iu khin th hai nhn 10 byte ny v ghi vo SRAM kt t v tr oxff.Bit chng hot ng cung xung nhp. Chng trnh vi master: ; on khi to cng sbi 0x17,7 ;set bit DDBR7 - t SCK l chn ra. cbi 0x17,6 ;xa bit DDBR6-t PB6 l cng vo. sbi 0x18,6 ;set bit PORTB6-Kch hot in tr ko. sbi 0x17,5 ;t PB5 l chn ra. sbi 0x17,4 cbi 0x18,4 ;t xong cu hnh cc chn ;Tc dng ln tng bit khng nh hng n cc chn khc. ;By gi tip tc t cu hnh cho SPI 39

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LDI R17, 0b01010111 OUT 0x0d,R17 ;bt u hot ng vi xung nhp Fcl/128 SENDFUNTION: ldi R17,0x0a ;khi to s m ldi xh,0x00 ;khi to con tr ldi xl,0xff ;khi to con tr SEND: Ld Out Dec Breq In Bst Brts Exit: RET Chng trnh vi Slave Cc bn t vit. 3.4. UART: R16,X+ SPDR,R16 R17 exit R16,SPSR R16,7 SEND ;ly d liu trong RAM ;thot nu R17=0 ;Ly thanh ghi trang thi ;ly bit SPIF ;tip tc gi khi byte trc c gi.

3.5.Watchdog timer:

3.6. B nh ROM c th c xa bng in: EEPROM B nh EEPROM l mt b nh khng b mt d liu khi ngun in cung cp b ngt.D liu trong n c th c ghi v xa bng in v v vy vic ghi v c b nh ny VK c th lm trc tip. B nh ny c xem nh mt b nh d liu nhng chng khng c truy nhp nh mt b nh SRAM m c truy nhp nh mt thit b ngoi vi.Thi gian truy cp vit mt khong 2.5 n 4 ms,v ph thuc vo ngun in cung cp cho vi iu khin (Vcc). iu khin vo ra d liu vi EEPROM chng ta c th s dng 3 thanh ghi l:EEPROM address ,EEDR v EECR. 40

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1.EEPROM address : y l thanh ghi 16 bit lu a ch ca cc nh ca EEPROM (t 0 n 511). N c truy nhp nh hai thanh ghi 8 bit c lp EEARH v EEARL :

2.EECR :EEPROM control register y l thanh ghi iu khin EEPROM

L thanh ghi 8 bit trong c 4 bit c nh ngha iu khin hot ng ghi c d liu b nh EEPROM. -Bit 3-EERIE :EEPROM ready interrupt enable Bit ny cho php ngt hat ng (thng bo cho CPU bit kh nng chao i d liu vi CPU.).Nu bit ny c set 1 th n c php hot ng.V ngc li. -Bit 2-EEMWE: EEPROM master write enable. Bit ny khi c set 1 s ghi d liu t thanh ghi EEDR vo nh c a ch lu trong thanh ghi EEAR ca EEPROM. Bit ny c set bng phn mm v c xa bng phn cng sau bn chu khi my. -Bit 1-EEWE: EEPROM write enable y l bit cho php ghi d liu vo EEPROM trnh trng hp ta ghi d liu khi m mt d liu trc cha c ghi xong.N c xo bng phn cng khi m s liu c ghi xong vo EEPROM. -Bit 0-EERE : EEPROM read enable Bit ny ra lnh cho CPU c d liu t b nh ny ra thanh ghi d liu vi a ch lu bn trong thanh ghi a ch.V n c xa bng phn cng khi m d liu c c ra thanh ghi d liu. Vy ghi d liu vo EEPROM ta lm cc bc sau: Bc1:ch i bit EEWE b xa cha ? Bc 2:Ghi d liu mi vo thanh ghi d liu (EEDR) Bc3:Set bit EEWE ri n bit EEMWE bt u ghi d liu. 41

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Ch :Nu nh dang ghi d liu EEPROM m xut hin ngt th d liu s khng c ghi mt cch an ton vo EEPOM. Sau y l mt v d: Ghi 1 byte vo b nh EEPROM a ch lu trong thanh ghi Y ,d liu trong R17. Write: Sbic EECR,1 ;nhy qua nu EEWE b xa. Rjmp Write Write_start: Out EEAL,YL Out EEAH,YH Out EEDR,R17 ;Nap d liu vo thanh ghi d liu. Cli ;cam tat ca ca ngat. Sbi EECR,1 Sbi EECR,2 Sei ;cho php ngt. c d liu vo EEPROM th dn gin hn. Bc1:kim tra bit EEWE nu nh c qu trnh ghi EEPROM th ch i. Bc2: a a ch cn c vo thanh ghi a ch EEAR Bc3:Set bit EERE ln 1 bt u qu trnh c. Bc4:Ch i oc xong bng cch kim tra bit EERE nu c xa th c d liu thanh ghi d liu.Sau c d liu. V d: c mt byte d liu t trong EEPROM bt t a ch lu trong thanh ghi Z v d liu c ra thanh ghi R17 READ: Sbic EECR,1 ;kim tra xem c ghi khng? Rjmp READ READ_START: ;Bt u c. Out EEAL,ZL Out EEAH,ZH Sbi EECR,0 Here: Sbic EECR,0 ;kim tra EERE b xa hay cha? Rjmp here In R17, EEDR ;Ht.

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3.EEDR:EEPROM data register y l thanh ghi 8 bit lu d liu ly ra t EEPROM hoc d liu nh ghi vo EEPROM.

3.7. B so snh tng t: Analog comparator B so sanh tng t ca AVR c u vo li hai chn PB2 v PB3 (nh hnh v).Vi chn PB2 c ni vo cc dng ca b so snh v PB3 c ni vo cc m ca b so snh.N to ra hai mc logic nu V+>V- th tn hiu ra l 1 v ngc li l 0.

iu khin v qua st trng thi ca b so snh tng t ta c mt thanh ghi l thanh ghi ACSR.Trc khi tm hiu v nguyn tc hot ng ca n ti s gii thiu cho cc bn v thanh ghi ny. Thanh ghi ACSR l mt thanh ghi 8 bit c a ch trong cc thanh ghi I/O l 0x08 v c a ch trong khng gian b nh SRAM l 0x28.Trong 8 bit th c 7 bit c nh ngha v bit 6 khng c nh ngha.N ch c th c v lun c gi tr logic l 0. 1.Bit 7-ACD:Analog comparator disable y l bit iu khin. Bit ny ttrc tip iu khin hot ng ca AC(b so snh tng t).Nu nh bit ny c set ln 1 th ngun cung cp cho AC hot 43

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ng b tt (turn off) v ng ngha vi vic n khng hot ng.V nu n c xa th AC c cp ngun v hot ng bnh thng.Ch :Ta c th thay i gi tr logic ca bit ny lc no cng c ngng hot ng ca chng hoc cho chng hot ng tr li nhng khi thay i gha tr logic ca n th ngt (ngt ca AC)cn b cm nu khng n s sinh ra mt ngt (C th l bit ACIE cn b xa). 2.Bit 5-ACO:Analog comparator output y l bit trng thi. Bit ny c ni trc tip vi u ra ca b so snh tng t. 3.Bit 4-ACI:Analog comparator interrupt flag y l bit trng thi. C bo ngt ca b so sanh tng t.Nu nh ci ny c set v cc ngt c php th mt chng trnh phc v ngt c gi v chng c xa bng phn cng khi chng trinhg bo ngt c phc v. Cc trng hp lm thay i trng thi c ngy ngoi vic thay i bit ACD s c ni ti trong cc bt o v 1. 4.Bit 3-ACIE:AC interrupt enable y l bit iu khin. Nu bit ny c set th ngt ny c php v ngc li. 5.Bit 2ACIC:Analog comparator input Capture Enable y l bit iu khin. Khi bit ny c set ln 1 th u ra ca AC c ni trc tip vo u vo ca chc nng bt s kin ca Timer/counter 1.( c thm timer/counter1). 6.Bit ACIS1 v ACIS0 :Ac interrupt mode select y l hai bit iu khin. ACIS1 ACIS0 Ch ngt 0 0 Theo mc 0 1 Dnh ring(cha dng n) 1 0 Sn sun 1 1 Sn ln Ch :Cc bit ny cng c th c thay i bt c khi no.Nhng khi thay i th ngat ca no phi b cm. Ta c th s dng lnh SBI hoc CBIU thay i trng thi cc bit trn thanh ghi ny tr bit ACI.Bi ny sau khi c c cng s b xa (nu n c set). Thit port u vo cho b so snh tng t: Hai chn PB2 v PB3 ny cn c thit lp l u vo vo b in tr treo. lp trnh cho AC ta bt u cc bc sau: 44

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Bc 1:Thit lp cc chn u vo cha AC. Bc 2:Chn cc ch cho AC v nh dng ngt Bc 3:Khi ng AC bng cch xa bit ACD . Sau y l mt v d: Bn c mt bi ton n gin nh sau: iu khin nhit ca phng sao cho n nh hn 40.Dng LM335 khi u vo bn mc trc tip vo PB2 AVR khng thng qua ADC v u PB3 mc vo gi tr in p tng ng vi 40 ca LM335(v nh 3.5v chng hn).Khi nu nhit ln hn 40 th t mc logic ca PC0 ln 1 cho ti khi n gim xung th thi. Cch 1:khng dng ngt(s dng vo ra bng chng trnh) ;Chng trnh c vit nh sau: ;Thit lp cng vo cho AC cbi DDBR,2 ;thit lp chn PB2 l chn vo cbi PORTB,2 ;Loi b in tr treo. Cbi DDBR,3 ;Thit lp chn PB3 l chn vo. Cbi PORTB,3 ;Loi b in tr treo . ;Thit lp cho AC sbi ACSR,0 ;Tm ngng hot ng ca AC cbi ACSR,3 ;Cm ngt cbi ACSR,0 ;Bt u hot ng ;Theo di AC loop1: sbis ACSR,ACO ;kim tra xem nhit c cao ;hn ngng t trc khng. Rjmp loop ;nt khng ln hn tip tc theo di. ;Nhit cao hn. ; nh ngha chn PC0 l chn ra: sbi DDRC,0 ; nh ngha l chn ra sbi PORTC,0 ; t ln mc 1 loop2: sbic ACSR,ACO Rjmp Loop2 Sbc portc,0 ;xa nu nhit nh hn Rjmp loop2 ;the end. Cch 2: s dng ngt: 3.8. ADC :analog to digital converter 45

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Vi iu khin AVR 8535 c mt b bin i ADC tch hp trong chip. C cc c im: phn gii bit. Sai s tuyn tnh:0.5LSB. D chnh xc +/-2LSB. Thi gian chuyn i:65-260s. 8 Knh u vo c th c la chn. C hai ch chuyn i. C ngun bo ngt khi hon thnh chuyn i. Loi b nhiu trong ch ng. S khi:

T s khi cc bn c th thy: Tm u vo ca ADC l tm chn ca PORTA v chng c chn thng qua mt MUX. iu khin hot ng vo ra d liu ca ADC v CPU chng ta c 3 thanh ghi:ADMUX y l thanh ghi iu khin la chn knh u vo cho ADC . ADCSR y l thanh ghi iu khin v thanh ghi trng thi ca ADC. ADCD :y l thanh ghi d liu. Sau y l tng thanh ghi: 1.ADMUX: Multiplexer select register y l thanh ghi iu khin 8 bit:

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Vi 3 bit c nh ngha l MUX2,MUX1,v MUX0.ng vi cc t hp logic cc bn c th chn knh u vo.C th:

Ch :Nu nh ta thay i knh trong thi im m ADC anh chuyn i th khi qu trnh chuyn i hoang thinh th khn vo mi c thay i. 2.ADCSR :ADC control and status register y l thanh ghi iu khin v lu trng thi ca ADC:

Bit 7-ADEN:ADC enable y l bit iu khin hot ng ca ADC .Khi bit ny c set 1 th ADC c th hot ng v ngc li.Nu nh ta ngng hot ng ca ADC trong khi n ang chuyn i th n s kt thc qu trnh chuyn i.Mc d cha chuyn i xong. Bit 6-ADSC: ADC start conversion

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Ti liu ny ti ang vit d nhng cc bn c th c. (Do thi gian c hn nn nh my sai hi nhiu mong cc bn c dch) My hm na hon thanh ht ti s up tip ln cho cc bn. Chc cc bn thnh cng ! vutricongbka@yahoo.com

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