1

VCC R8 20K A SCL SDA VIN WEN R6 1k U2 AVDD VCC V1 V2 DVDD A1 F1 C2 B2 C1 B3 F3 B1 E2 E3 F2 100nF OV7670 AVDD DOVDD VREF1 VREF2 DVDD AGND DOGND PWDN STROBE XCLK #RESET SIO_C SIO_D VSYNC HREF PCLK A3 A2 D1 D2 E1 VSYNC HREF PCLK R7 1k U1 1 2 3 A VCC B GND Y SN74LVC1G00 U3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DI0 DI1 DI2 DI3 WE GND TST WRST WCK VDD DI4 DI5 DI6 DI7 5 4 VIN C9 10UF C10 10uF

co m

A VCC C13 100nF AVDD R5 0R

U5

2.8V Power

cu .

C11 100nF

1 2 3

VIN OUT GND EN BYT

C12 100nF

C1 100nF C2 100nF C3 100nF C4 100nF B C5 100nF

PAM3101DAB28

C14 100uF

P1 VIN 3.3V VCC SCCB Clock SCL SCCB Data SDA VSYNC Frame Synchro HREF Line Synchro FIFO Write Enable WEN XCK CMOS CLK FIFO Read Address Reset RRST OE FIFO Chip Select CS FIFO Read Clock RCLK
FIFO Output Data FIFO Output Data FIFO Output Data FIFO Output Data FIFO Output Data FIFO Output Data FIFO Output Data FIFO Output Data

VCC R4 10K

C6

ow

D0 D1 D2 D3 D4 D5 D6 D7

er

B4 A4 B5 A5 F5 E5 F4 E4

C_D0 C_D1 C_D2 C_D3 C_D4 C_D5 C_D6 C_D7

VSYNC

VIN

DO0 DO1 DO2 DO3 RE GND OE RRST RCK DEC DO4 DO5 DO6 DO7

28 27 26 25 24 23 22 21 20 19 18 17 16 15

D0 D1 D2 D3

XCLK R1 OE RRST RCLK D4 D5 D6 D7 R2 1K R3 0R

no solder
VCC

AL422B C7 100nF C8 100nF

D0 D1 D2 D3 D4 D5 D6 D7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Header 2x10

U4 1 C 2 NC GND X_24MHZ VCC VOUT 4 3 VCC XCLK

.p

w w

. Title OV7670 + AL422B ( FIFO) Camera Module( V2.0 ) Size A4 Date: File: 2012-5-21 D:\OV7670+FIFO\7670.SCHDOC Sheet of Drawn By: 4 _ Number 1 Revision REV2.0