Huong Dan Mo Phong VHDL Voi ModelSim

H Bch Khoa TP.
HCM-Khoa in-in T
L Ch Thng - chithong@gmail.com
HNG DN C BN M PHNG VHDL/VERILOG VI MODELSIM
Download v ci t chng trnh

Download min ph chng trnh ModelSim Student Edition (version 6.6d ti 12/2010) ti www.model.com
Lm ng theo 3 bc c hng dn trn www.model.com
Hng dn c bn
Khi ng ModelSim
To Project Bm File -> New -> Project
Page 1 of 12
H Bch Khoa TP.HCM-Khoa in-in T
Mch t hp cn thit k bao gm mt AND_GATE v mt OR_GATE.
Nhp tn project l comb_ckt, thng chn tn project ging vi tn file cha m VHDL (.vhd) v thng thng cng ging vi tn ca entity ca m VHDL. Bm Browse chn th mc cha project. Nn to mt th mc ring cha cc file ca mt project. Bm OK
Thm file vo project
Bm Create New File to mt file mi. (Nu li g on m v d sau y th chn Add Existing File, ri chn fie comb_ckt.vhd km theo hng dn ny )
Nhp tn file l comb_ckt, chn loi file l VHDL, gi nguyn Folder l Top Level, ri bm OK. Page 2 of 12
Bm Close. Bm i vo tn file comb_ckt.vhd m ca s son tho chng trnh
Nhp vo on m VHDL sau

------------------------------------------------------------- Combinational Logic Design -- (ESD book figure 2.4) -- by Weijun Zhang, 04/2001 --- A simple example of VHDL Structure Modeling -- we might define two components in two separate files, -- in main file, we use port map statement to instantiate -- the mapping relationship between each components -- and the entire circuit. -----------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity OR_GATE is port( X: in std_logic; Y: in std_logic; F2: out std_logic); end OR_GATE; architecture behv of OR_GATE is begin process(X,Y) begin F2 <= X or Y; end process; end behv; -- component #1
M t linh kin th 1: OR_GATE
-- behavior des.
------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; -- component #2
M t linh kin th 2: AND_GATE
Page 3 of 12

entity AND_GATE is port( A: in std_logic; B: in std_logic; F1: out std_logic ); end AND_GATE; architecture behv of AND_GATE is begin process(A,B) begin F1 <= A and B; end process; end behv;
-- behavior des.
-------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use work.all; entity comb_ckt is port( input1: in std_logic; input2: in std_logic; input3: in std_logic; output: out std_logic ); end comb_ckt; architecture struct of comb_ckt is component AND_GATE is port( A: in std_logic; B: in std_logic; F1: out std_logic ); end component; component OR_GATE is port( X: in std_logic; Y: in std_logic; F2: out std_logic ); end component; signal wire: std_logic; begin -- use sign "=>" to clarify the pin mapping Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire); Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output); end struct; ----------------------------------------------------------------- as entity of AND_GATE -- top level circuit
M t mch t hp: comb_ckt
-- as entity of OR_GATE
-- signal just like wire
Bm File -> Save hoc bm biu tng
lu chng trnh.
Page 4 of 12
Bin dch (compile)

Bm Compile -> Compile All (hoc Compile Seleted nu ch mun bin dch 1 file)
Nu c thng bo li th bm i vo dng thng bo li m ra ca s bo li.
Page 5 of 12
Xem bo li g v ti dng lnh no. (Trong v d trn, li thiu du ; ti dng lnh 43) Bm Close ng ca s bo li. Sa li, lu v bin dch li cho n khi khng cn li.
To Testbench
Bm Project -> Add to Project -> New File to mt file testbench. (Nu li g on m v d sau y th chn Existing File, ri chn fie tb_ckt.vhd km theo hng dn ny )
Nhp vo tn file testbench l tb_ckt, , chn loi file l VHDL, gi nguyn Folder l Top Level, ri bm OK.
Page 6 of 12
Tng t nh phn to file comb_ckt.vhd, nhp on m VHDL sau cho file tb_ckt.vhd.
--------------------------------------------------------------------- Test Bench for comb_ckt.vhd -- (ESD figure 2.4) -- by Weijun Zhang, 04/2001 --- Testbench is used to ensure the design is working properly -- according to the specification. -- assert statements are used to test the wrong value against -- our desired one. we should test as many cases as possible, -- particularly, we should include upper and lower limits -- of the operations. -------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity CKT_TB is end CKT_TB; -- empty entity
------------------------------------------------------------------architecture TB of CKT_TB is -- declare the whole circuit(entity of comb_ckt.vhd) as a component component comb_ckt is port( input1: in std_logic; input2: in std_logic; input3: in std_logic; output: out std_logic ); end component; -- declare all I/O ports from unit under test as signals. -- signals are usually declared within architecture signal T_input1, T_input2, T_input3, T_output: std_logic; begin U_UT: comb_ckt port map (T_input1,T_input2,T_input3,T_output); process variable err_cnt: integer := 0; begin -- Test case 1 T_input1 <= '0'; T_input2 <= '0'; T_input3 <= '0'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 2
Page 7 of 12

T_input1 <= '1'; T_input2 <= '1'; T_input3 <= '1'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 3 T_input1 <= '1'; T_input2 <= '0'; T_input3 <= '1'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- Test case 4 T_input1 <= '0'; T_input2 <= '1'; T_input3 <= '0'; wait for 10 ns; assert (T_output=((T_input1 or T_input2) and T_input3)) report "Failed Case1!" severity error; if (T_output/=((T_input1 or T_input2) and T_input3)) then err_cnt := err_cnt +1; end if; -- summary of all the tests to see if any errors if (err_cnt=0) then assert false report "Testbench completed successfully!" severity note; else assert true report "Something wrong, try again pls!" severity error; end if; wait; end process; end TB; ------------------------------------------------------------------configuration CFG_TB of CKT_TB is for TB end for; end CFG_TB; --------------------------------------------------------------------- stop running
Lu v bin dch file tb_ckt.vhd ny cho n khi khng cn li.
Page 8 of 12
Chy m phng
Bm chn tab Library
Bm vo du cng trc th mc work trong ca s Library, ri bm i vo dng ckt_tb bt u chy m phng
Page 9 of 12
H Bch Khoa TP.HCM-Khoa in-in T Bm chn tab Wave thy ca s Wave
Page 10 of 12
Bm chn ca s Objects, ri bm Add -> To Wave -> Signals in Region thm cc tn hiu cn quan st vo ca s Wave Cc tn hiu va thm vo
Bt u chy m phng
Cch 1: Bm Simulate -> Run -> Run 100 chy m phng trong 100 ns
Cch 2: Nhp thi gian cn chy m phng, ri bm nt
(Run)
Page 11 of 12
Cch 3: Nhp lnh run 100 vo du nhc lnh trong ca s Transcript ri Enter.
Quan st dng sng thu c trn ca s Wave. d quan st, bm nt phi chut trn ca s Wave, ri bm Zoom Full.
Kt qu t dng sng: Thi gian t_input1 t_input2 t_input3 t_output 0 10 ns 0 0 0 0 10 20 ns 1 1 1 1 20 30 ns 1 0 1 1 30 40 ns 0 1 0 0 Kt qu ny chng t mch t hp thit k ng !
Trong v d trn, ta vit m VHDL ca AND_GATE v OR_GATE chung vi comb_ckt trong cng mt file comb_ckt.vhd. Ta cng c th vit m VHDL ca AND_GATE v OR_GATE trong hai file ring r l AND_GATE.vhd v OR_GATE.vhd. Khi , ta phi thm vo project tng cng l 4 file (comb_ckt.vhd, AND_GATE.vhd, OR_GATE.vhd v tb_ckt.vhd). Xem thm v th chy m phng cc mch trong th mc VHDL codes km theo bi hng dn ny. Cc m VHDL dng trong bi hng dn ny v trong th mc VHDL codes l ca tc gi Weijun Zhang, University of California Riverside. Page 12 of 12

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Huong Dan Mo Phong VHDL Voi ModelSim

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H Bch Khoa TP.

HNG DN C BN M PHNG VHDL/VERILOG VI MODELSIM

Download v ci t chng trnh

Lm ng theo 3 bc c hng dn trn www.model.com

To Project Bm File -> New -> Project

H Bch Khoa TP.HCM-Khoa in-in T

Mch t hp cn thit k bao gm mt AND_GATE v mt OR_GATE.

Thm file vo project

H Bch Khoa TP.HCM-Khoa in-in T

Bm Close. Bm i vo tn file comb_ckt.vhd m ca s son tho chng trnh

Nhp vo on m VHDL sau

M t linh kin th 1: OR_GATE

------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; -- component #2

M t linh kin th 2: AND_GATE

H Bch Khoa TP.HCM-Khoa in-in T

M t mch t hp: comb_ckt

-- signal just like wire

Bm File -> Save hoc bm biu tng

H Bch Khoa TP.HCM-Khoa in-in T

Bin dch (compile)

Nu c thng bo li th bm i vo dng thng bo li m ra ca s bo li.

H Bch Khoa TP.HCM-Khoa in-in T

H Bch Khoa TP.HCM-Khoa in-in T

H Bch Khoa TP.HCM-Khoa in-in T

Lu v bin dch file tb_ckt.vhd ny cho n khi khng cn li.

H Bch Khoa TP.HCM-Khoa in-in T

Bm vo du cng trc th mc work trong ca s Library, ri bm i vo dng ckt_tb bt u chy m phng

H Bch Khoa TP.HCM-Khoa in-in T Bm chn tab Wave thy ca s Wave

H Bch Khoa TP.HCM-Khoa in-in T

Cch 2: Nhp thi gian cn chy m phng, ri bm nt

H Bch Khoa TP.HCM-Khoa in-in T

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