Kit Thuc Tap PIC

NHN XT CA GIO VIN HNG DN
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Ngy ..thng.nm 2008
Gio vin hng dn
Thc s : L NH KHA
NHN XT CA GIO VIN PHN BIN

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Ngy ..thng.nm 2008
Gio vin phn bin
Thy : PHAN DUY ANH
Li cm n
Sau nhng nm hc ti trng,chng em c
hc v tip thu nhiu kin thc mi t s ch bo tn tnh
ca Qu Thy C, s gip ca bn b. y l khong
thi gian y ngha. n tt nghip ra trng l nn
tng quan trng v nh du mt bc ngoc mi trong
cuc i ca chng em.
Chng em xin gi li cm n chn thnh n Thy
L nh Kha. Thy hng dn ti thc hin n tt
nghip v cung cp cho ti nhiu kinh nghim qu bu.
Chng em xin chn thnh cm n Qu Thy c
khoa in T - Tin Hc v cc Cn b Cng nhn vin
Trng Cao ng K Thut Cao Thng, to iu kin
thun li ti c th hon thnh tt n tt nghip
ny..
Sinh vin thc hin

Trn Thnh Tm
Nguyn Tin Ngha
LI NI U
Ngy nay Khoa hc K thut pht trin mnh m,

cng vi s pht trin khng ngng ca cc ngnh k thut
ni chung v k thut in t ni ring. Chng i su
vo mi mc i sng hng ngy ca ngi dn. c bit
s dng vi iu khin iu khin cc thit b dn dng v
cc thit b cng nghip. Nm c tm quan trng , nhm
chng em lm ti: KIT THC TP PIC cho cc bn sinh
vin c cng c hc tp v thc hnh mn vi iu khin Pic.
Nhng kin thc v nng lc t c trong qu trnh
hc tp ti trng s c nh gi qua t bo v n tt
nghip. V chng em c gng tn dng tt c nhng kin thc
hc trng cng vi s tm ti nghin cu, c th hon
thnh tt n tt nghip ny. Nhng kt qu nhng sn
phm t c trong ngy hm nay tuy khng ln lao nhng
n l thnh qu ca ba nm hc tp ti trng. L thnh cng
u tin ca chng em trc khi ra trng.
Do khong thi gian v kin thc cn hn hp, mc d
chng em c gng hon thnh n tt nghip ny ng thi
hn. Nn khng trnh khi nhng thiu xt mong Qu thy c
thng cm. Chng em mong nhn c nhng kin ng gp
tn tnh ca qu thy c v cc bn. Cui cng em xin chn
thnh cm n qu thy c v cc bn .
n Tt Nghip Kha 2005 2008
GVHD:Thc s L nh Kha
MC LC
CHNG 0
DN NHP11
PHN I KHO ST VI IU KHIN PIC 16F877A .............. 12

CHNG I CU TRC PHN CNG CA 16F877A.................................... 13
1.1. S lt v vi iu khin PIC 16F877A .................................................................... 13
1.2. S lt v cc chn ca PIC 16F877A ..................................................................... 13
1.3.Mt s im c bit ca CPU ............................................................................ 18
1.3.1. Dao ng ..................................................................................................... 18
1.3.2. Reset ............................................................................................................ 19
1.3.3.MCLR(Master clear) .................................................................................... 19
1.3.4. Interrupts ..................................................................................................... 20
1.3.5. Ch ngun thp Sleep(Power down Mode) ........................................... 20
1.3.6. B nh thi gim st (Watch Dog Timer WDT) .................................... 21
1.4.T chc b nh ............................................................................................................. 22
1.4.1. B nh chng trnh ................................................................................... 22
1.4.2. B nh d liu ............................................................................................. 23
1.4.2.2. Vng thanh ghi chc nng t bit....................................................... 24
1.4.3. Cc thanh ghi chc nng c bit................................................................ 27
1.4.3.1.Thanh ghi trng thi(Status register): .................................................... 27
1.4.3.2. Thanh ghi ty chn (Option Reg_Register) ......................................... 28
1.4.3.3. Thanh ghi iu khin ngt INTCON .................................................... 29
1.4.3.4. Thanh ghi cho php ngt ngoi vi 1 ..................................................... 30
1.4.3.5. Thanh ghi c ca cc ngt ngoi vi 1 ................................................... 31
1.4.3.6. Thanh ghi cho php ngt ngoi vi 2 ..................................................... 32
1.4.3.7. Thanh ghi c ca cc ngt ngoi vi 2 ................................................... 33
1.4.4. PCL v PCLATH ........................................................................................ 33
1.4.5. Ngn xp Stack............................................................................................ 34
1.4.6. nh a ch trc tip v a ch gin tip, thanh ghi INF v FSR.............. 34
1.5. I/O port ............................................................................................................................ 35
1.5.1. Port B v thanh ghi TRIS B ........................................................................ 35
1.5.2. Port B v thanh ghi TRIS B ........................................................................ 37
1.5.3. Port C v thanh ghi TRIS C ........................................................................ 38
1.5.4. Port D v thanh ghi TRIS D ........................................................................ 40
1.5.5. Port E v thanh ghi TRIS E......................................................................... 40
SVTH :Trn Thnh Tm & Nguyn Tin Ngha
Trang 4
GVHD:Thc s L nh Kha
CHNG II B NH THI................................................................................ 43
2.1. B nh thi timer 0 .................................................................................................... 43
2.1.1. Gii thiu..................................................................................................... 43
2.1.2. Hot ng ca b nh thi ......................................................................... 43
2.1.3. Ngt Timer 0 ............................................................................................... 43
2.1.4. S dng Timer 0 vi ngun xung clock ngoi............................................ 44
2.1.5. B tin nh t l 8 bit ca Timer 0 ............................................................. 44
2.2. B nh thi Timer 1................................................................................................... 44
2.2.1. Gii thiu..................................................................................................... 44
2.2.2. Thanh ghi iu khin Timer 1 ..................................................................... 45
2.2.3. Ch nh thi trong hot ng ca Timer 1 ........................................... 45
2.2.4. Ch m ................................................................................................. 45
2.2.5. Giao ng ring ca Timer 1....................................................................... 46
2.2.6. Ngt Timer 1 ............................................................................................... 46
2.3. B nh thi Timer 2................................................................................................... 46
2.3.1. Gii thiu .................................................................................................... 46
2.3.2. Thanh ghi iu khin T2CON..................................................................... 47
2.3.3. Xa cc b t l............................................................................................ 47
2.3.4. Ngun xung clock cho Timer 2................................................................... 47
2.3.5. Thanh ghi TMR2 v PR2 ............................................................................ 47
2.3.6. Tn hiu bo trng thi cn bng ................................................................. 47
2.3.7. Ch ng .................................................................................................. 48
CHNG III MODULE CCP ................................................................................. 49
3.1. Gii thiu ...................................................................................................................... 49
3.2. Thanh ghi iu khin module CCP ........................................................................... 49
3.3. Ch Capture ............................................................................................................ 50
3.3.1. B nh t l ca CCP.................................................................................. 50
3.4. Ch Compare .......................................................................................................... 51
3.5. Ch iu bin xung PWM..................................................................................... 51
3.5.1. Chu k PWM............................................................................................... 51
3.5.2.Chu k nhim v ca PWM ......................................................................... 52
3.5.3. Ci t hot ng cho PWM ....................................................................... 52
3.5.4. Module MSSP ............................................................................................. 54
Trang 5
GVHD:Thc s L nh Kha
CHNG IV B BIN I ADC 10 BIT............................................................. 55

4.1. Gii thiu module ADC 10 bit .................................................................................. 55
4.2. Cc thanh ghi iu khin ............................................................................................ 55
4.3. Hot ng ca Module ADC ..................................................................................... 57
4.4.Thi gian ly mu......................................................................................................... 58
4.5. La chn xung clock cho bin i ADC .................................................................. 58
4.6. Cu hnh cc chn Analog.......................................................................................... 59
4.7. Chuyn i ADC ......................................................................................................... 59
4.8. Hot ng ca module ADC trong ch ng ....................................................... 60
4.9. nh hng ca Reset .................................................................................................. 60
CHNG V IN TH THAM CHIU V CC B SO SNH IN ......... 61
5.1. Module Comparator .................................................................................................... 61
5.1.1. Gii thiu v module comparator................................................................ 61
5.1.2. Ci t ch cho b so snh ..................................................................... 61
5.1.3. Ngun tham chiu ca b so snh............................................................... 63
5.1.3.1. Tn hiu in p tham chiu ngoi ....................................................... 63
5.1.3.2. Tn hiu in p tham chiu ni ........................................................... 63
5.1.4. Thi gian p ng ...................................................................................... 63
5.1.5. Tn hiu ng ra ca b so snh.................................................................... 63
5.1.6. Ngt ca cc b so snh .............................................................................. 64
5.1.7. Hot ng ca cc b so snh trong ch ng ......................................... 64
5.1.8. nh hng ca Reset................................................................................... 64
5.2. Module in p tham chiu ........................................................................................ 64
5.2.1. Gii thiu module in p tham chiu ........................................................ 64
5.2.2. Thanh ghi iu khin CVRCON ................................................................. 65
5.2.3. chnh xc ca in p tham chiu ......................................................... 66
5.2.4. Hot ng ca module VREF trong ch ng ......................................... 66
5.2.5. Trng thi ca module khi Reset................................................................. 66
5.2.6. S dng module vi cc mch ngoi .......................................................... 66
PHN II CC THNH PHN CA KIT THC TP

PIC 16F877A ................................................................................... 67
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CHNG I
GVHD:Thc s L nh Kha
HIN TH LED N....................................................................... 68
1.1. Gii thiu chung ......................................................................................................... 68

1.2. Mch nguyn l ........................................................................................................... 69
CHNG II HIN TH LED 7 ON................................................................. 70
2.1. Cc khi nim c bn ................................................................................................. 70
2.2. Kt ni vi vi iu khin ............................................................................................ 71
2.3. Giao tip vi iu khin vi nhiu led 7 on ........................................................... 72
2.4. Lu gii thut ......................................................................................................... 74
2.5.Mch nguyn l ............................................................................................................ 75
CHNG III N GIAO THNG ........................................................................ 76
3.1. Gii thiu ..................................................................................................................... 76
3.2. S nguyn l ........................................................................................................... 77
3.3. Lu gii thut ......................................................................................................... 78
CHNG IV LED MA TRN ................................................................................ 79
4.1. Hin th led ma trn ..................................................................................................... 79
4.1.1. Gii thiu..................................................................................................... 79
5.1.2. Led ma trn 8x8........................................................................................... 79
4.2. Phng php hin th bng IC cht........................................................................... 80
4.2.1. Cht hng .................................................................................................... 81
4.2.2. Cht ct ....................................................................................................... 81
4.3. Phng php dng thanh ghi dch............................................................................. 82
4.3.1. Qut hng .................................................................................................... 82
4.3.1.1. Gii thiu chung v phng php qut hng..................................... 82
4.3.1.2. Qu trnh thc hin qut hng ........................................................... 83
4.3.1.3. V d .................................................................................................. 83
4.3.2. Qut ct ....................................................................................................... 84
4.3.2.1. Gii thiu chung v phng php qut ct........................................ 84
4.3.2.2. Qu trnh thc hin qut ct .............................................................. 83
4.3.2.3. V d ........................................................................................................... 84
4.4. Mch nguyn l ........................................................................................................... 86
CHNG V LCD .................................................................................................... 87
Trang 7
GVHD:Thc s L nh Kha
5.1. Gii thiu chung v LCD .......................................................................................... 87

5.1.1. Cc thanh ghi............................................................................................... 89
5.1.2. C bo bn BF............................................................................................. 90
5.1.3. B m a ch AC ...................................................................................... 90
5.1.4. Vng RAM hin th DDRAM..................................................................... 90
5.1.5. Vng ROM cha k t CGROM ................................................................ 91
5.1.6. Vng RAM cha k t ha CGRAM .................................................... 92
5.2. Tp lnh ca LCD ....................................................................................................... 94
5.3. Khi to LCD .............................................................................................................. 97
5.3.1. Mch khi to bn trong chip HD44780..................................................... 97
5.3.2. Khi to bng lnh ...................................................................................... 97
5.4. Lu gii thut ......................................................................................................... 99
5.5. Mch nguyn l ......................................................................................................... 100
CHNG VI ADC.................................................................................................. 101
6.1. Gii thiu v module ADC ...................................................................................... 101
6.1.1. C bn v ADC ........................................................................................ 101
6.1.2. ADC trong PIC 16F877A.......................................................................... 102
6.2. S nguyn l ......................................................................................................... 103
CHNG VII BN PHM GIAO TIP LCD.................................................... 104
7.1. Keypad v nguyn l hot ng ............................................................................. 104
7.2. Keypad giao tip vi LCD ....................................................................................... 104
7.3. S gii thut ......................................................................................................... 106
CHNG VIII
GIAO TIP I2C........................................................................ 107
8.1. Gii thiu chung v I2C .......................................................................................... 107

8.1.1. c im giao tip I2C.............................................................................. 107
8.1.2. START and STOP conditions................................................................... 109
8.1.3. nh dng d liu truyn........................................................................... 109
8.1.4. nh dng a ch thit b .......................................................................... 111
8.1.5. Truyn d liu trn bus I2C ...................................................................... 112
8.1.6. Ch Multi-Master ................................................................................. 113
8.2. Module I2C Trong Vi iu Khin PIC ....................................................................... 113
8.2.1. c im phn cng ca PIC16F877A.................................................... 113
8.2.2. Cch thc s dng Module I2C trong CCS .............................................. 114
Trang 8
GVHD:Thc s L nh Kha
8.2.3. EEPROM 24C04 ....................................................................................... 115

8.2.3.1. Hnh dng......................................................................................... 115
8.2.3.2. S cu to.................................................................................... 115
8.2.3.3. S chn .............................................................................................. 115
8.3. Mch nguyn l ........................................................................................................ 117
CHNG IX O NHIT DNG LM35 ...................................................... 118
9.1. Gii thiu .................................................................................................................... 118
9.2. Mt s c tnh c bn ca LM35........................................................................... 118
9.3. Mch nguyn l ....................................................................................................... 119
PHN III CC BI TP THC HNH .................................. 120

BI 1 HIN TH TRNG THI PORT TRN LED N .............................. 121
BI 2 HIN TH TRNG THI CC PORT V THAY I THI GIAN
DELAY..123
BI 3 HIN TH NGY THNG NM SINH TRN LED 7 ........................... 125
BI 4 HIN TH NG H TRN LED 7 ........................................................ 127
BI 5 CHNG TRNH N GIAO THNG.................................................. 129
BI 6 CHY CH LED MA TRN.................................................................... 131
BI 7 HIN TH K T TRN LCD ................................................................. 133
BI 8 GIAO TIP BN PHM S HEX HIN TH LCD.135
BI 9 IU CHNH ADC HIN TH LED N .............................................. 137
BI 10 O NHIT .......................................................................................... 139
PHN VI GII CC BI TP THC HNH ........................ 141

BI 1 HIN TH TRNG THI PORT TRN LED N .............................. 142
BI 2 HIN TH TRNG THI CC PORT V THAY I THI GIAN
DELAY..144
BI 3 HIN TH NGY THNG NM SINH TRN LED 7 ........................... 146
BI 4 HIN TH NG H TRN LED 7 ..148
BI 5 CHNG TRNH N GIAO THNG.................................................. 150
BI 6 CHY CH LED MA TRN.................................................................... 152
BI 7 HIN TH K T TRN LCD ................................................................ 155
BI 8 GIAO TIP BN PHM S HEX HIN TH LCD.158
BI 9 IU CHNH ADC HIN TH LED N .............................................. 162
Trang 9
GVHD:Thc s L nh Kha
BI 10 O NHIT .......................................................................................... 163
PHN VI
PH LC ............................................................ 167
Ph lc 1 : 16F877A.................................................................................. 168
Ph lc 2 : DEFS_16F877A. .................................................................... 175
Trang 10
GVHD:Thc s L nh Kha
Chng 0 : DN NHP
I. t vn :
Ngy nay vi s pht trin ca cng nghip vi in t, k thut s cc h thng iu
khin dn c t ng ha.Vi cc k thut tin tin nh vi x l, vi mch sc
ng dng vo lnh vc iu khin, th cc h thng iu khin c kh th s, vi tc
x l chm chm t chnh xc c thay th bng cc h thng iu khin t ng vi
cc lnh chng trnh c thit lp trc.
c th hc tt mn vi iu khin chng ta phi c thit b hc tp mt trong
nhng thit b l kit thc tp, v c s ng ca khoa in T - Tin Hc Trng
Cao ng K Thut Cao Thng. Nhm chng em quyt nh lm ti tt nghip: Kit
Thc Tp Vi iu Khin Pic.
II. Gii hn ti:
Vi thi gian gn nm tun thc hin ti cng nh trnh chuyn mn c hn,
chng em c gng ht sc hon thnh n ny nhng ch gii quyt c nhng
vn sau:
Led n.
Hin th Led 7 on.
n giao thng .
Chy ch led ma trn.
Hin th LCD.
ADC
Giao tip bn phm.
o nhit dng LM35.
III. Mc ch nghin cu :
Mc ch trc ht khi thc hin ti ny l hon tt chng trnh mn hc
iu kin ra trng. C th khi nghin cu ti l chng em mun pht huy nhng
thnh qu ng dng ca vi iu khin to ra nhng sn phm cho cc bn sinh vin
kha sau. Khng nhng th n cn l tp ti liu cho cc bn sinh vin tham kho.
Ngoi ra qu trnh thc hin ti l mt c hi chng em t kim tra li nhng
kin thc hc trng. ng thi pht huy tnh sng to, kh nng gii quyt mt vn
theo nhu cu t ra. V y cng l dp chng em khng nh mnh trc khi ra
trng tham gia vo cc hot ng sn xut ca x hi.
Trang 11
GVHD:Thc s L nh Kha
PHN I
KHO ST VI IU KHIN PIC

16F877A
CHNG I
: CU TRC PHN CNG CA PIC16F877A
CHNG II : B NH THI
CHNG III : MODULE CCP (Capture Compare PWM)
CHNG IV : B BIN I ADC 10 BIT
CHNG V : IN TH THAM CHIU V CC B SO SNH
IN
Trang 12
GVHD:Thc s L nh Kha
CHNG I : CU TRC PHN CNG CA

PIC16F877A
1.1 S lc v vi iu khin PIC16F877A:
PIC 16F877A l dng PIC ph bin nht hin nay ( mnh v tnh nng, 40 chn,
b nh cho hu ht cc ng dng thng thng). Cu trc tng qut ca PIC
16F877A nh sau:
- 8 K Flash ROM.
- 368 Bytes RAM.
- 256 Bytes EEPROM.
- 5 ports (A, B, C, D, E) vo ra vi tn hiu iu khin c lp.
- 2 b nh thi 8 bits (Timer 0 v Timer 2).
- Mt b nh thi 16 bits (Timer 1) c th hot ng trong ch tit kim nng
lng (SLEEP MODE) vi ngun xung Clock ngoi.
- 2 b CCP( Capture / Compare/ PWM).
- 1 b bin i AD 10 bits, 8 ng vo.
- 2 b so snh tng t (Compartor).
- 1 b nh thi gim st (WatchDog Timer).
- Mt cng song song 8 bits vi cc tn hiu iu khin.
- Mt cng ni tip.
- 15 ngun ngt.
- C ch tit kim nng lng.
- Np chng trnh bng cng ni tip ICSP(In-Circuit Serial Programming)
- c ch to bng cng ngh CMOS
- 35 tp lnh c di 14 bits.
- Tn s hot ng ti a 20MHz.
1.2 S lc v cc chn ca PIC16F877A:
Trang 13
GVHD:Thc s L nh Kha
Trang 14
GVHD:Thc s L nh Kha
Trang 15
GVHD:Thc s L nh Kha
PIC16F877A l h vi iu khin c 40 chn, mi chn c mt chc nng khc

nhau.Trong c mt s chn a cng dng: mi chn c th hot ng nh mt ng
xut nhp hoc l mt chn chc nng c bit dng giao tip vi cc thit b ngoi vi.
Trang 16
GVHD:Thc s L nh Kha
S khi PIC16F877A.
Trang 17
GVHD:Thc s L nh Kha
1.3 Mt s im c bit ca CPU:

1.3.1 Dao ng:
PIC16F877A c th hot ng trong bn ch dao ng khc nhau:
Trong cc ch LP, XT v HS chng ta

s dng thch anh dao ng ni vo cc chn
OSC1 v OSC2 to dao ng.
Vic la chn t trong dao ng thch anh da vo bng sau:
Lu : T c gi tr ln s tng tnh n
nh ca dao ng nhng cng lm tng
thi gian khi ng.
Ch dao ng RC c s dng
nh mt gii php tit kim trong cc
ng dng khng cn s chnh xc v thi
gian.
* Cch tnh chu k my:

V d ta s dng thch anh 10Mhz. Khi :
Tn s dao ng ca thch anh l Fosc = 10Mhz
Chu k dao ng ca thch anh l Tosc = 1/Tosc= 1/10*106 (s)
Trang 18
GVHD:Thc s L nh Kha
Chu k my:
T_instruction = 4*Tosc = 4/10*106(s) = 0.4 s = 400 ns
1.3.2 Reset:
PIC16F877A c th b reset bi nhiu nguyn nhn khc nhau nh:
1.3.3 MCLR :
PIC16F877A c mt b lc nhiu
phn MCLR . B lc nhiu ny s pht hin
v b qua cc tn hiu nhiu.
Ng vo MCLR trn chn 4 ca
PIC16F877A. Khi a chn ny xung
thp th cc thanh ghi bn trong VK s
c ti nhng gi tr thch hp khi
ng li h thng.
(Lu : Reset do WDT khng lm chn
MCLR xung mc thp).
Trang 19
GVHD:Thc s L nh Kha
1.3.4 Interrupts:
PIC16F877A c nhiu ngun ngt khc nhau. y l mt s ngt tiu biu :
- Ngt ngoi xy ra trn chn INT.
- Ngt do Timer0.
- Ngt do Timer1.
- Ngt do Timer2.
- Ngt do thay i trng thi trn cc chn PortB.
- Ngt so snh in th.
- Ngt do Port song song.
- Ngt USART.
- Ngt nhn d liu.
- Ngt truyn d liu .
- Ngt chuyn i ADC.
- Ngt mn hnh LCD.
- Ngt hon tt ghi EEPROM.
- Ngt module CCP.
- Ngt Module SSP.
* Cc thanh ghi chc nng ngt: INTCON, PIE1, PIR1, PIE2, PIR2 (cc thanh ghi
ny s c nghin cu cc phn sau).
1.3.5 Ch ngun thp Sleep (Power down Mode) :

y l ch hot ng ca VK khi lnh sleep c thc thi. Khi nu c
cho php hot ng, b m ca WDT s b xa nhng WDT vn tip tc hot ng bit
PD (STATUS <3>) c reset v khng, bit TO c set, oscillator ngng hot ng v
cc PORT gi nguyn trng thi nh trc khi lnh sleep c thc thi.
Trang 20
GVHD:Thc s L nh Kha
Do khi ch sleep dng cung cp cho VK l rt nh nn ta cn thc hin cc

bc sau trc khi VK thc thi lnh sleep.
a tt c cc chn v trng thi VDD hoc VSS.
Cn m bo rng khng c mch ngoi vi no c iu khin bi dng
in ca VK v dng in nh khng kh nng cung cp cho cc mch
ngoi vi hot ng.
Tm ngng hot ng ca khi A/D v khng cho php cc xung clock bn
ngoi tc dng vo VK.
chc nng in tr ko ln ca PORTB.
Pin MCLR phi mc logic cao.
1.3.6 B nh thi gim st (Watch Dog Timer -WDT):
Gi s bn vit mt chng trnh, bn mong i chng trnh ny s chy nu
khng c g trc trc xy ra th n s khng bao gi dng li, nh vy bn phi lm mt
vng lp khi chng trnh chy n im cui th n li quay tr v im bt u.
Nhng m hy xem mt trng hp: Gi s chng trnh kim tra mt chn input, nu
n ln mc cao th con Pic s tip tc kim tra mt chn input th hai c ln mc cao hay
khng, nu chn input th hai khng ln mc cao, con Pic s ngi ch v n s ch
thot ra khi ch ngi ca n nu chn input th hai ln mc cao.
By gi hy xem mt trng hp khc, gi s nh bn vit mt chng trnh, bn
compiled n thnh cng, v ngay c bn cho chy m phng tng bc, tng bc
mt trn my tnh, bng MPLAB chng hn, c v nh mi chuyn u tt, bn em np
vo con Pic. Sau mt thi gian chy th, con Pic thnh lnh b kt vo ni no trong
chng trnh m khng th thot ra c trng thi hin ti. iu g l cn thit gii
quyt hai trng hp trn, reset li hay vn cho n b kt khng thot ra c, l
mc ch ca mch Watchdog.
Mch Watchdog th khng phi l mi m g, c rt nhiu microprocessors v
microcontrollers c mch Watchdog, nhng m n lm vic ra sao ?
Bn trong con Pic c mt mch RC, mch ny cung cp 1 xung Clock c lp vi
bt k xung Clock no cung cp cho Pic. Khi Watchdog Timer (vit tt l WDT) c
cho php (enabled), n s m bt u t 00 v tng ln 1 cho n FFh, khi n tng t
FFh n 00 ( FFh+1) th con Pic s b Reset bt k ang lm g, ch c 1 cch l ngn
khng cho WDT m ti 00.
Khi con Pic b kt khng th thot ra khi tnh trng hin ti th WDT vn tip tc
m m khng b bt k iu g ngn cm n m ti FF v n FF+1, v vy n s reset
con Pic lm cho chng trnh phi khi ng li t u.
s dng WDT chng ta cn lm 3 vic.
Th nht, cn thi gian bao lu reset WDT ?
Th hai, lm sao xo WDT ?
Cui cng, chng ta phi ni cho con Pic bit chng trnh cho php WDT hot
ng.
Trang 21
GVHD:Thc s L nh Kha
1.4 T chc b nh:

PIC16F877A c tt c 3 khi b nh ring bit bao gm: B nh chng trnh, b
nh d liu v b nh EEPROM.
1.4.1 B nh chng trnh:
PIC16F877A c b m chng trnh di 13 bits c th nh a ch cho khong
khng gian nh 8K x 14bits. Khng gian b nh ny c chia lm 8 trang, c a ch t
0005h n 1FFFh.
Mi s truy cp ngoi vng khng gian nh ny s khng c tc dng.
Ngoi ra, b nh chng trnh cn bao gm mt ngn xp (Stack) 8 mc. Vector
Reset c t ti a ch 0000h v vector ngt c t ti a ch 0004h.
Trang 22
GVHD:Thc s L nh Kha
1.4.2 B nh d liu:
Bng cu trc b nh d liu P16F877A
Trang 23
GVHD:Thc s L nh Kha
B nh d liu bao gm 4 Bank: Bank 0, Bank1, Bank2 v Bank3. Mi bank c

dung lng 128 Bytes, bao gm vng Ram a mc ch (GPR) v vng thanh ghi chc
nng c bit (SFR).
Cc Bank ny c la chn bng 2 bit thanh ghi STATUS l RP0(Status<5>) v
RP1(Status<6>).
1.4.2.1 Vng Ram a mc ch:

Vng RAM a mc ch c chiu rng 8 bit v c th c truy nhp trc tip hoc
gin tip thng qua thanh ghi FSR. Vng RAM a mc ch c phn phi cc Bank
nh sau:
- Bank 0: 96 Bytes t a ch 20h n a ch 7Fh.
- Bank 1: 80 Bytes t a ch A0h n a ch EFh.
- Bank 2: 96 Bytes t a ch 110h n a ch 16Fh.
- Bank 3: 96 Bytes t a ch 190h n a ch 1EFh.
1.4.2.2 Vng thanh ghi chc nng c bit:
Cc thanh ghi chc nng c bit c s dng bi b x l trung tm CPU hoc
cc module ngoi vi iu khin hot ng ca VK. Cc thanh ghi chc nng c bit
ny c chia lm 2 loi: loi th nht dng cho cc chc nng ca CPU, loi th 2 dng
cho cc chc nng ngoi vi.
Trang 24
GVHD:Thc s L nh Kha
Bng tm tt cc thanh ghi chc nng c bit:
Trang 25
GVHD:Thc s L nh Kha
Trang 26
GVHD:Thc s L nh Kha
1.4.3 Cc thanh ghi chc nng c bit:

1.4.3.1 Thanh ghi trng thi ( Status Register):
Thanh ghi trng thi cha cc trng thi s hc ca b ALU, trng thi Reset v cc
bit chn Bank ca b nh d liu.
Trang 27
Bit 7
GVHD:Thc s L nh Kha
IRP: Bit la chn bank thanh ghi (S dng cho nh a ch gin tip).
1 = Bank 2, 3 (100h 1FFh )
0 = Bank 0, 1 (00h FFh)
Bit 6 5 RP1 RP0: Bit la chn bank thanh ghi (Dng trong nh i ch trc tip).
11 = Bank 3 ( 180h 1FFh)
10 = Bank 2 (100h 17Fh)
01 = Bank 1 (80h FFh)
00 = Bank 0 (00h 7Fh)
Each bank is 128 bytes
Bit 4 TO: Bit bo hiu hot ng ca WDT.
1: Lnh xa WDT hoc Sleep xy ra.
0: WDT hot ng.
Bit 3 PD: Bit bo cng sut thp ( Power down bit).
1: Sau khi ngun tng hoc c lnh xa WDT.
0: Thc thi lnh Sleep.
Bit 2 Z: bit Zero
1: Khi kt qu ca mt php ton bng 0.
0: Khi kt qu ca mt php ton khc 0.
Bit 1 DC: Digit Carry
1: C mt s nh c sinh ra bi php cng hoc php tr 4 bit thp.
0: Khng c s nh sinh ra.
Bit 0 C: c nh (Carry Flag)
1: C mt s nh sinh ra bi php cng hoc php tr.
0: Khng c s nh sinh ra.
1.4.3.2 Thanh ghi ty chn (Option _Reg Register):
Thanh ghi ty chn cha cc bit iu khin cu hnh cho cc cha nng nh:
ngt ngoi, Timer 0 chc nng ko ln Vdd ca cc chn Port B, v thi gian ch ca
WDT
Bit 7
RBPU : Bit cho php PORTB c ko ln ngun.
1: Khng cho php PORTB ko ln ngun.

0: Cho php PORTB ko ln ngun.
Trang 28
GVHD:Thc s L nh Kha
Bit 6 INTEDG: Bit la chn cnh tc ng ngt (INTERRUPT EDGE)

1: Ngt s c tc ng bi cnh ln ca chn RB0/INT
0: Ngt s c tc ng bi cnh xung ca chn RB0/INT
Bit 5 T0CS: Bit la chn ngun xung Clock cho Timer 0
1: Xung Clock cung cp bi ngun ngoi qua chn RA4/T0CKI
0: Xung Clock cung cp bi ngun dao ng ni.
Bit 4 T0SE: Bit la chn cnh no ca xung clock tc ng ln timer 0
1: Cnh xung
0: Cnh ln
Bit 3
PSA: Bit quyt nh tc m PS2:PS0 s tc ng ln Timer 0 hay WDT

1: Tc m PS2:PS0 s tc ng ln WDT
0: Tc m PS2:PS0 s tc ng ln Timer 0
Bit 2-0 PS2:PS0: Dng la chn tc m ca timer hay WDT

Thi gian trn WDT
18 ms
36ms
72ms
144ms
288ms
576ms
1.1s
2.2s
1.4.3.3 Thanh ghi iu khin ngt INTCON (Interrupt Control Register):
Bit 7 GIE: Bit cho php ngt ton cc

1: Cho php ngt ton cc
0: Khng cho php ngt
Bit 6 PEIE: Bit cho php ngt khi ghi vo EEPROM hon tt.
1: Cho php ngt ghi vo EEPROM hot ng
0: Khng cho php ngt ghi vo EEPROM hot ng
Trang 29
GVHD:Thc s L nh Kha
Bit 5 TMR0IE: Bit cho php ngt khi timer 0 trn

1: Cho php ngt khi timer 0 trn
0: Khng cho php ngt khi timer 0 trn
Bit 4 INTE: Bit cho php ngt ngoi vi trn chn RB0/INT
1: Cho php ngt ngoi vi
0: Khng cho php ngt ngoi vi
Bit 3 RBIE: Cho php ngt khi trng thi PORTB thay i
1: Cho php
0: Khng cho php
Bit 2 TMR0IF: C bo ngt Timer 0
1: Timer 0 trn
0: Timer 0 cha trn
Bit 1 INTF: C bo ngt ngoi RB0/INT
1: C ngt
0: Khng xy ra ngt.
Bit 0 RBIF: C bo ngt khi c thay i trng thi PORTB
1: C thay i
0: Khng c thay i xy ra trn PORTB
1.4.3.4 Thanh ghi cho php ngt ngoi vi 1(PIE1 Register):
Ch : Bit PEIE (INTCON<6>) phi c set cho php bt k ngt ngai vi no

xy ra.
Bit 7 PSPIE: Bit cho php ngt c/ ghi Port song song
1: Cho php
0: Khng cho php
Bit 6 ADIE: Bit cho php ngt chuyn i A/D
1: Cho php
0: Khng cho php
Bit 5 RCIE: Bit cho php ngt nhn USART
1: Cho php
0: Khng cho php
Bit 4 TXIE: Bit cho php ngt truyn USART
1: Cho php
Trang 30
GVHD:Thc s L nh Kha
0: Khng cho php

Bit 3 SSPIE: Bit cho php ngt Port ni tip ng b
1: Cho php
0: Khng cho php
Bit 2 CCP1IE: Bit cho php ngt module CCP1
1: Cho php ngt
0: Khng cho php
Bit 1 TMR2IE: Bit cho php ngt xy ra khi TMR2 bng thanh ghi PR2
1: Cho php
0: Khng cho php
Bit 0 TMR1IE: Bit cho php ngt trn TMR1
1: Cho php
0: Khng cho php
1.4.3.5 Thanh ghi c ca cc ngt ngoi vi 1:
Bit 7 PSPIF: C ngt c/ ghi ca Port song song

1: Mt hot ng c/ghi din ra (phi xa bng phn mm)
0: Khng c hot ng c/ghi.
Bit 6 ADIF: C bo ngt chuyn i A/D
1: Mt qu trnh chuyn i A/D hon thnh
0: Chuyn i A/D cha hon tt
Bit 5 RCIF: C bo ngt nhn USART
1: Buffer nhn USART y
0: Buffer nhn USART trng.
Bit 4 TXIF: C bo ngt pht USART
1: Buffer truyn USART trng
0: Buffer truyn USART y
Bit 3 SSPIF: C bo ngt port ni tip ng b (ngt SSP)
1: Ngt SSP xy ra v phi c xa bng phn mm trc khi tr li
chng trnh chnh t chng trnh phc v ngt.
0: Khng c ngt xy ra
Bit 2 CCP1IF: C bo ngt CCP1
Trang 31
GVHD:Thc s L nh Kha
Ch Capture (Bt gi):

1: Mt Capture thanh ghi TMR1 xy ra( phi c xa bng phn mm)
0: Khng xy ra Capture thanh ghi TMR1
Ch Compare ( So snh):
1: Khi cc gi tr so snh trong thanh ghi TMR1 c tha ( phi c xa
bng phn mm)
0: Khi cc gi tr so snh trong thanh ghi TMR1 khng c tha
Ch PWM: Khng s dng trong ch ny
Bit 1 TMR2IF: C bo ngt xy ra khi gi tr trong thanh ghi TMR2 bng trong thanh
ghi PR2
1: Gi tr trong thanh ghi TMR2 bng thanh ghi PR2 (phi c xa bng
phn mm)
0: Gi tr trong thanh ghi TMR2 cha bng thanh ghi PR2
Bit 0 TMR1IF: C bo trn thanh ghi TMR1
1: Thanh ghi TMR1 trn (phi c xa bng phn mm)
0: Thanh ghi TMR1 cha trn
1.4.3.6 Thanh ghi cho php ngt ngoi vi 2:
Ch : Bit PEIE (INTCON<6>) phi c set cho php bt k ngt ngai vi no

xy ra.
Bit 7,5,2,1
Unimplemented : read as 0
Bit 6 CMIE: Bit cho php ngt do b so snh in th

1: Cho php
0: Khng cho php
Bit 4 EEIE: Bit cho php ngt do ghi EEPROM
1: Cho php
0: Khng cho php
Bit 3 BCLIE: Bit cho php ngt do xung t bus
1: Cho php
0: Khng cho php
Bit 0 CCP2IE: Cho php ngt module CCP2
1: Cho php
0: Khng cho php
Trang 32
GVHD:Thc s L nh Kha
1.4.3.7 Thanh ghi c ca cc ngt ngoi vi 2:
Bit 7,5,2,1
Unimplemented : read as 0
Bit 6 CMIF: C bo ngt do b so snh

1: Ng vo b so snh thay i (phi c xa bng phn mm)
0: Ng vo b so snh khng thay i.
Bit 4 EEIF: C bo ngt ghi EEPROM
1: Ghi EEPROM hon tt (phi c xa bng phn mm)
0: Ghi EEPROM cha hon tt.
Bit 3 BCLIF: C bo ngt do xung t bus
1: Xung t bus xut hin trong ch SSP
0: Khng c xung t bus xy ra
Bit 0 CCP2IF: C bo ngt CPP2
Ch Capture (bt gi):
1: Mt s bt gi thanh ghi TMR1 xy ra (phi c xa bng phn
mm)
0: Khng xy ra Capture thanh ghi TMR1
Ch Compare (So snh):
1: Mt thut ton so snh trong thanh ghi TMR1 xy ra (phi c xa
bng phn mm)
0: Khng xy ra thut ton so snh
1.4.4 PCL v PCLATH:
B m chng trnh PC
(program counter) c di 13 bit,
c dng cha a ch ca lnh
c thc thi k tip. Byte thp cha
trong thanh ghi PCL c th c/ghi
mt cch trc tip. Cc bit cao (bit
12:8) cha trong thanh ghi PCLATH,
khng th c nhng c th ghi gin
tip bng cch s dng thanh ghi
PCLATH. Khi c bt k s Reset no
xy ra, cc bit cao ca b m chng
trnh PC s b xa. Xem thm hai v d
sau y hiu thm v hot ng ca
b m chng trnh PC.
Trang 33
GVHD:Thc s L nh Kha
1.4.5 Ngn xp Stack:

Stack cho php 8 lnh gi chng trnh con v ngt hot ng. Stack cha a ch
m chng trnh chnh s quay v thc hin t sau chng trnh con hay ngt. i vi
PIC16F877A Stack c su 8 lp. Stack khng nm trong c b nh chng trnh ln
b nh d liu.
1.4.6 a ch trc tip v a ch gin tip, thanh ghi INF v thanh ghi FSR:
Thanh ghi INF khng phi l mt thanh ghi vt l. N cha gi tr ca thanh ghi c
a ch nm thanh ghi FSR.
V d:
Thanh ghi ti a ch 10h c gi tr 5Ah
Nu ta a 10h vo thanh ghi FSR th khi c thanh ghi INF ta s c gi tr 5Ah.
Data EEPROM v Flash Program Memory:

EEPROM l b nh c kh nng c v ghi trong iu kin lm vic bnh thng
(khi ngun Vdd khng i). B nh ny khng c nh a ch trc tip trong bn
b nh m c nh a ch gin tip thng qua cc thanh ghi chc nng c bit:
- EECON1
- EECON2
- EEDATA
- EEDATH
- EEADR
- EEADRH
Trong thanh ghi EEDATA lu gi gi tr 8 bit s c ghi hoc c. Thanh ghi
EEADR lu gi a ch m chng ta mun ghi hoc c, thanh ghi ny c kh nng nh
a ch cho 256 byte EEPROM. Thanh ghi EECON1 cha cc bit iu khin cn thanh
ghi EECON2 c s dng khi to qu trnh ghi/c.
Trang 34
GVHD:Thc s L nh Kha
1.5 I/O ports:

1.5.1 Port A v thanh ghi TRISA:
Port A gm 6 chn t RA0 n RA5. Vic
ghi gi tr vo thanh ghi TRISA s qui nh cc
chn ca Port A l input hay output (nu l 1 th
l input, l output nu l 0). Vic c thanh ghi
Port A s c trng thi ca cc chn Port A.
Vic ghi gi tr vo thanh ghi Port A s thay i
trng thi ca cc chn Port A.
Ring chn RA4 c tch hp chc nng
l chn cung cp xung clock ngoi cho Timer 0
(RA4/T0CKI). Nhng chn khc ca Port A
c a hp vi cc chn ng vo Analog ca
ADC v chn ng vo in th so snh ca b
so snh Comparator. Hot ng ca nhng chn
ny c quy nh bng nhng bit tng ng
trong cc thanh ghi ADCCON1 v CMCON1.
Khi cc chn ca Port A c s dng lm ng
vo Analog th cc bit trong thanh ghi TRISA
phi c set bng 1.
Trang 35
GVHD:Thc s L nh Kha
Chc nng ca cc chn Port A
Trang 36
GVHD:Thc s L nh Kha
Bng tm tt cc thanh ghi lin quan n Port A
1.5.2 Port B v thanh ghi TRISB:

Port B gm 8 chn t chn RB0-RB7. Vic ghi gi tr vo thanh ghi TRISB s quy
nh cc chn ca Port B l input hay output (1: input, 0: output). Vic c thanh ghi Port
B s c trng thi ca cc chn Port B. Vic ghi gi tr vo thanh ghi Port B s thay
i trng thi ca cc chn Port B.
Ba chn ca Port B c a hp vi chc nng In-Circuit Debugger v Low
Voltage Programming function: RB3/PGM, RB6/PGC, RB7/PGD.
Mi chn Port B c mt transistor ko ln Vdd. Chc nng ny hot ng khi bit
RBPU (Option <7>) c xa. Chc nng ny s t ng c xa khi Port B c quy
nh l input.
Bn chn ca Port B t RB7 n RB4 c chc nng ngt khi trng thi chn Port B
thay i (Khi Port B c quy nh l output th chc nng ny khng hot ng. Gi tr
chn ca Port c so snh vi gi tr c lu trc , khi c s sai lch gia 2 gi
tr ny ngt s xy ra vi c ngt RBIF (INTCON<0) s bt ln. Ngt c th lm cho
VK thot khi trng thi SLEEP.
Bt c s truy xut no trn PortB s xa trng thi sai lch, kt thc ngt v cho
php xa c ngt RBIF.
Trang 37
GVHD:Thc s L nh Kha
Bng chc nng PortB :
Bng tm tt cc thanh ghi lin quan n Port B :
1.5.3 Port C v thanh ghi TRISC:

Port C gm 8 chn t chn RC0-RC7. Vic ghi gi tr vo thanh ghi TRISC s quy
nh cc chn ca Port C l input hay output (1: input, 0: output). Vic c thanh ghi
Port C s c trng thi ca cc chn Port C. Vic ghi gi tr vo thanh ghi Port C s
thay i trng thi ca cc chn Port C.
Cc chn ca Port C c a hp vi cc chc nng ngoi vi.
Khi cc chc nng ngoi vi c cho php ta cn quan tm cht ch ti gi tr cc
bit ca thanh ghi TRISC. Mt s chc nng ngoi vi s ghi gi tr 0 ln cc bit ca
thanh ghi TRISC v mc nh cc chn ny l output, ngoi ra mt s chc nng ngoi vi
khc s t ng mc nh mt s chn l ng vo. Do cn xem xt k cc tnh nng
ca cc hm ngoi vi thit lp gi tr cc bit trong thanh ghi TRISC cho thch hp.
Trang 38
GVHD:Thc s L nh Kha
Bng chc nng Port C :
Bng tm tt cc thanh ghi lin quan n Port C :
Trang 39
GVHD:Thc s L nh Kha
1.5.4 Port D v thanh ghi TRISD

Port D gm 8 chn t chn RD0-RD7. Bn cnh chc nng l port xut nhp,
Port D cn c th hot ng nh mt cng song song bng cch set bit PSPMODE
(TRISE<4>), trong ch ny buffer ng vo l TTL.
Bng chc nng Port D :
Bng tm tt cc thanh ghi lin quan n Port D :
1.5.5 Port E v thanh ghi TRISE:

Port E c 3 chn RE0 /RD/AN5, RE1/WR /AN6, RE2 /CS/AN7, c th c cu
hnh nh cc chn xut nhp thng thng.
Cc chn ca Port E c th tr thnh
cc chn iu khin cho cng song song ca
VK khi bit PSPMODE (TRISE<4>) c
set bng 1. Trong ch ny, ngi s dng
phi m bo cc chn ca PortE l ng vo.
Ngoi ra cc chn Port E cn c th
c cu hnh nh cc ng vo Analog, ti
ch ny, khi c gi tr ca cc chn ny
s cho ta gi tr l 0.
Thanh ghi TRISE quy nh chc nng
xut nhp ca Port E ngay c khi n c s
dng nh cc ng vo Analog. Phi m bo
cc chn ny c quy nh l ng vo trong
ch ny.
Trang 40
GVHD:Thc s L nh Kha
Bng chc nng cc chn Port E :
Bng tm tt cc thanh ghi lin quan n Port E :
Thanh ghi TRISE :
Cc bit iu khin trng thi ca Port song song

Bit 7 IBF : Bit trng thi bo buffer ng vo y
1 : Mt t (word -16bit) c nhn vo v ang c c bi CPU
0 : Khng c t no c nhn vo
Bit 6 OBF: Bit trng thi bo buffer ng ra y
1 : Buffer ng ra vn cn gi mt t c c trc
0 : Buffer ng ra c c.
Bit 5 IBOV: Bit bo trng thi buffer ng vo trn ( trong ch Vi x l)
1 : Chu k ghi mi bt u nhng gi tr c vn cn trang buffer ( phi
c xa bng phn mm)
0 : Khng c trn xy ra
Trang 41
GVHD:Thc s L nh Kha
Bit 4 PSPMODE: Bit chn ch cng song song cho Port D

1 : Port D c cu hnh nh cng song song
0 : Port D cu hnh nh ng xut nhp thng thng
Bit 3 Khng s dng, c l 0
Cc bit xc nh xut nhp ca Port E:
Bit 2 Bit 2: Xc nh chiu xut nhp cho chn RE2/CS/AN7
1 : Ng vo
0 : Ng ra
Bit 1 Bit 1: Xc nh chiu xut nhp cho chn RE1/WR/AN6
1 : Ng vo
0 : Ng ra
Bit 0 Bit 0: xc nh chiu xut nhp cho chn RE0/RD/AN5
1 : Ng vo
0 : Ng ra
Trang 42
GVHD:Thc s L nh Kha
CHNG II : B NH THI
2.1 B nh thi Timer 0 :
2.1.1 Gii thiu :
Module Timer 0 l mt b nh thi/ m 8 bit, c kh nng c v ghi c , c
mt b tin nh t l (Prescaler) 8 bit lp trnh c, c bit la chn ngun xung clock
trong hoc ngoi, c ngt khi Timer trn, c bit la chn cnh tc ng ca xung clock
ngoi.
2.1.2 Hot ng ca b nh thi .

Ch nh thi c chn bng cch xa bit T0CS (OPTION_REG <5>). Trong
ch ny thanh ghi TMR0 s tng ln sau mi chu k (prescaler khng c tc dng hoc
t l 1 :1). Nu thanh ghi TMR0 c ghi mt gi tr mi, gi tr trong thanh ghi ny s
khng tng trong 2 chu k lnh k tip.V vy khc phc hin tng ny chng ta c
th hiu chnh gi tr nhp vo thanh ghi TMR0.
Ch m c la chn bng cch set bit T0CS (OPTION_REG <5>). Trong
ch m, thanh ghi TMR0 s tng ln khi c cnh ln hoc cnh xung xut hin trn
chn T0CKL ( cnh ln hoc cnh xung c la chn bi bit T0SE (OPTION_REG
<4>, xa bit T0SE s la chn cnh ln).
2.1.3 Ngt Timer 0 .
Ngt Timer 0 c to ra khi thanh ghi TMR0 trn t 0FFh n 00h. Khi xy ra
trn, c T0IF(INTCON<2>) c bt ln. Ngt c th c ngn chn bng cch xa bit
T0IE (INTCON<5>). C ngt T0IF phi c xa bng phn mm truc khi thot khi
chng trnh ngt tr v chng trnh chnh.
Trang 43
GVHD:Thc s L nh Kha
Lu : Ngt Timer 0 khng lm VK thot khi trng thi ng.

2.1.4 S dng Timer 0 vi ngun xung clock ngoi.
Khi b tin nh t l khng c s dng, ng vo xung clock ngoi cng ging
nh ng ra b tin nh t l. Ngun xung clock ngoi s c ng b vi xung clock
ni bng cch: n s c ly mu ti chu k Q2 v Q4 ca xung clock ni. Do ,
T0CKI phi mc cao t nht 2 Tosc v mc thp t nht cng l 2 Tosc.
2.1.5 B tin nh t l 8 bit ca Timer 0.
B m 8 bit c s dng nh b tin nh t l cho Timer 0 hoc b hu nh t l
cho WDT. Bit PSA (OPTION_REG<3>) s la chn b m ny s s dng cho Timer
0 hay WDT, cc bit PS2, PS1, PS0 s xc nh t l ca b m.
(Xem li phn thanh ghi OPTION_REG)

Cc thanh ghi c lin quan n Timer 0:
2.2 B nh thi Timer 1.

2.2.1 Gii Thiu.
Timer 1 l mt b nh thi/ m 16 bit bao gm hai thanh ghi 8 bit (TMR1H v
TMR1L), c kh nng c c v ghi c. Cp thanh ghi TMR1H v TMR1L s tng
t 0000h ln FFFFh ri sau trn v 0000h. Nu c cho php (bit TMR1IE c set),
ngt s xy ra khi gi tr TMR1 trn t FFFFh v 0000h, lc c ngt TMR1IF s bt
ln.
Trang 44
GVHD:Thc s L nh Kha
2.2.2 Thanh ghi iu khin Timer 1:
Bit 7,6
Khng s dng, c l 0.
Bit 5,4 T1CKPS1 : T1CKPS0 : Cc bit chn t l xung ng vo cho Timer1.

11
1 : 8 gi tr t l
10
1 : 4 gi tr t l
01
1 : 2 gi tr t l
00
1 : 1 gi tr t l
Bit 3
T10SCEN : Bit cho php b dao ng Timer 1 Oscillator

1 : Cho php dao ng
0 : Khng cho php dao ng
Bit 2
T1SYNC : Bit la chn ng b ha xung clock ngoi ca Timer 1

(Ch : Bit ny ch c tc dng khi bit TMR1CS = 1)
1: Khng ng b ha xung clock ngoi
0: ng b ha xung clock ngoi.
Bit 1
TMR1CS : Bit chn ngun xung clock cho Timer 1

1: Chn xung clock ngoi qua chn T1OSC/T1CKI ( tc ng cnh
ln)
0: Chn xung clock ni (Fosc/4)
Bit 0
TMR1ON: Bit cho php ngoc ngng Timer 1

1: Cho php
0: Khng cho php
2.2.3 Ch nh thi trong hot ng ca Timer 1 :

Ch nh thi c la chn bng cch xa bit TMR1CS (T1CON<1>). Trong
ch ny, xung clock cung cp cho Timer 1 l Fosc/4, bit ng b T1SYNC
(T1CON<2>) khng c tc dng v xung clock ni lun lun c ng b.
2.2.4 Ch m :
Timer 1 c th hot ng c ch ng b hoc bt ng b ty thuc vo vic
ci t bit TMR1CS (T1CON<1>).
m ng b :
Ch ny c la chn bng cch set bit TMR1CS v xa bit T1SYNC. Trong
ch ny gi tr ca Timer 1 s tng khi c xung cnh ln trn chn T1OSI/RC1 ( nu
bit T1OSCEN c set) hoc chn trn T1OSO (nu bit T1OSCEN c xa).
Xung clock ngoi s c ng b vi xung clock ni, hot ng ng b c
thc hin ngay sau b tin nh t l xung (prescaler). Trong ch ng hot ng ng
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b s b tt cho d c xung clock ngoi th Timer 1 cng khng tng. iu ny c ngha

l ch m ng b s khng hot ng c trong ch ng (SLEEP).
Khi ch s dng xung clock ngoi c la chn cho Timer 1 ch m
ng b, chng ta phi m bo xung clock ngoi c ng b vi xung clock ni.
m bt ng b :
Nu bit T1SYNC c set, xung clock ngoi s khng c ng b ha. B nh
thi s tip tc m trong sut qu trnh Sleep ca VK v c kh nng to ra mt ngt
khi b nh thi trn v lm VK thot khi trng thi ng.
* Mt s c im lu khi c ghi vo Timer :
- Vic c thanh ghi TMR1H hoc TMR1L trong khi b nh thi ang chy t
mt ngun xung clock ngoi khng ng b s cho gi tr tc thi (khng phi ngng
Timer li). Tuy nhin, phi ch rng vic c Timer 1 s phi bao gm 2 ln c gi tr
8 bit, do c th pht sinh vn l Timer c th b trn gia 2 ln c.
- ghi vo Timer tt nht chng ta nn dng Timer li v ghi gi tr chng ta
mong mun. Chng ta c th ghi gi tr vo khi Timer ang chy nhng vic c th
to ra mt gi tr khng nh ta mong mun.
2.2.5 Dao ng ring ca Timer 1 :
Chng ta c th to mt b dao ng c lp cho Timer 1 bng cch s dng thch
anh c tn s ti a 200Khz.Vi b dao ng ny Timer c th m ngay c khi VK
ri vo trng thi ng.
2.2.6 Ngt Timer 1 :
Khi ngt c cho php, n s xy ra khi Timer trn t gi tr FFFFh xung 0000h.
Khi xy ra trn, c bo ngt TMR1IF s bt ln. Ngt c th ngn chn bng cch xa bit
TMR1IE, c TMR1IF phi c xa bng phn mm trc khi thot khi chng trnh
phc v ngt tr v chng trnh chnh.
Lu : Ngt ca Timer 1 ch nh thi v ch m ng b khng lm
cho VK thot khi trng thi ng, ch c ngt ch m bt ng b mi lm cho
VK thot khi trng thi ng.
Cc thanh ghi lin quan n Timer 1 :
2.3 B nh thi Timer 2 :

2.3.1 Gii thiu :
Timer 2 l mt b nh thi 8 bit bao
gm mt b tin nh t l v mt b hu
nh t l, Timer 2 cung cp thi gian hot
ng cho ch PWM nu module CCP
c chn. Thanh ghi TMR2 l mt thanh
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ghi c th c v ghi c, n b xa bi bt c tc ng reset no.

Xung clock ng vo (Fosc/4) c cc ty chn t l l 1:1, 1:4, 1:16, c la chn
bng cc bit iu khin T2CKPS1 : T2CKPS0 (T2CON<1 :0>).
Timer 2 c mt thanh ghi khong thi gian 8 bit PR2, y l mt thanh ghi c kh
nng c c v ghi c. Timer 2 s tng t 00h n khi bng gi tr thanh ghi PR2
n s reset v 00h chu k tng tip theo.
2.3.2 Thanh ghi iu khin T2CON
Bit 7
Bit 6:3
Khng s dng
TOUTPS3:TOUTPS0: Bit chn t l ng ra ca Timer 2
0000: 1:1 T l ng ra
0001: 1:2 T l ng ra
.
.
.
1111: 1:16 T l ng ra
Bit 2 TMR2ON: Bit cho php hot ng ca Timer 2

1: Cho php
0: Khng cho php.
Bit 1:0T2CKPS1:T2CKPS0: Bit chn t l ng vo ca Timer 2
00 : Prescaler 1
01 : Prescaler 4
1x : Prescaler 16
2.2.3 Xa cc b t l.
Hai b m prescaler v postcaler s b xa bi mt trong cc nguyn nhn sau
y :
- Ghi mt gi tr vo thanh ghi TMR2
- Ghi mt gi tr vo thanh ghi TCON2
- Bt c mt reset thit b no.
Thanh ghi TMR2 khng b xa khi thanh ghi TCON2 c ghi.
2.3.4 Ngun xung clock cho Timer 2.
Timer 2 c mt ngun xung clock l xung clock ca VK. Mt b tin nh t
l c la chn bi cc bit T2CKPS1:T2CKPS0
2.3.5 Thanh ghi TMR2 v PR2.
Thanh ghi TMR2 v PR2 l 2 thanh ghi c c v ghi c. Timer 2 s tng t
gi tr 00h ln ti gi tr nm trong thanh ghi PR2, sau n s reset v 00h cho n chu
k m k tip.
2.3.6 Tn hiu bo trng thi cn bng.
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Khi gi tr trong thanh ghi TMR2 bng vi gi tr trong PR2, b so snh s to ra

mt xung bo hiu, xung ny c th c dng cho b hu nh t l hoc c dng lm
xung clock cho module truyn ni tip. Ngoi ra n cn c dng lm tn hiu Reset
cho Timer 2.
2.3.7 Ch ng.
Trong ch ng Timer 2 khng hot ng, gi tr ca b nh t l s c lu li
v phc hi sau khi VK thot khi trng thi ng.
Cc thanh ghi lien quan n Timer 2:
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CHNG III : MODULE CCP

3.1 Gii thiu :
Module CCP c xy dng h tr cho
vic o lng v iu khin thi gian hot ng
ca cc tn hiu, o chu k hot ng ca tn hiu,
to ra cc tn hiu c tn s khc nhau, iu khin
tc ng c DC
Mi module CCP c mt thanh ghi 16 bit c
th hot ng nh:
- Mt thanh ghi Capture 16 bit
- Mt thanh ghi Compare 16 bit
- Mt thanh ghi iu khin chu k nhim v ca b PWM.
PIC16F877A c 2 module CCP l CCP1 v CCP2:
Module CCP1:
Thanh ghi CCPR1 bao gm 2 thanh ghi 8 bit: CCPR1L v CCPR1H. Thanh ghi
CCP1CON iu khin hot ng ca module CCP1. Cc xung c bit xy ra bng cc
thut ton so snh v s reset Timer 1.
Module CCP2:
Thanh ghi CCPR2 bao gm 2 thanh ghi 8 bit: CCPR2L v CCPR2H. Thanh ghi
CCP2CON iu khin hot ng ca module CCP2. Cc xung c bit xy ra bng cc
thut ton so snh s reset Timer 1 v bt u chuyn i ADC (nu chuyn i ADC
c cho php).
3.2 Thanh ghi iu khin module CCP:
Bit 7,6
Khng s dng
Bit 5,4 DCxB1:DCxB0: Bit 0 v bit 1 ca ch PWM

Ch Capture v ch Compare : Khng s dng
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Ch PWM: Trong ch PWM c 10 bit dng nh chu k nhim v cho

PWM, y l 2 bit trong s 10 bit , 8 bit cn li nm trong thanh ghi CCPRxL.
Bit 3:0 CCPxM3:CCPxM0: Cc bit chn ch cho module CCPx
0000: Tt tt c cc chc nng CCP
0100: Ch Capture, hot ng mi xung cnh xung
0101: Ch Capture, hot ng mi xung cnh ln.
0110: Ch Capture, hot ng mi 4 xung cnh ln.
0111: Ch Capture, hot ng mi 16 xung cnh ln.
1000: Ch Compare, ban u ng ra CCP mc thp, khi iu kin cn
bng xut hin n ln mc cao (c CCPIF c set).
1001: Ch Compare, ban u ng ra CCP mc cao, khi iu kin cn
bng xut hin n xung mc thp (c CCPIF c set).
1010: Ch Compare, to ra mt ngt phn mm khi iu kin cn bng
xut hin (c CCPIF c set, chn CCP khng i)
1011: Ch Compare , s kin c bit xy ra (c CCPIF c set, chn
CCP khng i), CCP1 reset TMR1, CCP2 reset TMR1, bt u chuyn i A/D
( nu module ADC c cho php).
11xx: Ch PWM .
3.3 Ch Capture.
module CCP hot ng trong ch
Capture th Timer 1 phi thit lp ch
nh thi hoc ch m ng b, nu
khng ch Capture s khng lm vic. Khi
ch Capture c s dng, chn CCP phi
c mc nh l ng vo.
Trong ch Capture, hai thanh ghi
CCPRxH v CCPRxL s ghi li gi tr 16 bit
ca Timer 1 khi c mt s kin xut hin trn chn CCPx (gi tr trong Timer 1 khng b
reset). Mt s kin c nh ngha bi:
- Bt c mt xung cnh xung
- Bt c mt xung cnh ln
- Bt c 4 xung cnh ln
- Bt c 16 xung cnh ln
S kin c la chn bi cc bit iu khin CCPxM3:CCPxM0
(CCPxCON<3:0>). Khi mt s kin xut hin gi tr trong Timer 1 c ghi li v c
CCPxIF c bt ln, c ny phi c xa bng phn mm trc khi mt s kin khc
xy ra nu khng gi tr lu trc s b xa.
Khi thay i hot ng ch Capture s to ra mt ngt nn khi mun thay i
hot ng ch Capture trc ht phi v hiu ha cc ngt v xa cc c ngt.
3.3.1 B nh t l ca CCP:
B nh t l prescaler c 4 gi tr t l c la chn bi cc bit CCPxM3:CCPxM0.
Bt c khi no module CCP ngng hot ng hoc khng hot ng trong ch
Capture th gi tr t l s b xa. Bt c reset no cng xa gi tr t l.
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Khi thay i gi tr prescaler c th gy ra mt ngt. Gi tr m prescaler s khng

b xa nn s Capture u tin c th khng xut pht t gi tr 0 ca b prescaler.
3.4 Ch Compare:
module CCP hot ng trong ch
Compare th Timer 1 phi thit lp ch
nh thi hoc ch m ng b, nu
khng ch Compare s khng lm vic.
Khi ch Compare c s dng, chn CCP
phi c mc nh l ng vo.
Trong ch Compare gi tr trong
thanh ghi TMR1 s c so snh vi mt gi
tr c lu sn trong thanh ghi 16 bit
CCPRx, khi hai gi tr ny bng nhau, mt
ngt s xy ra nu c cho php.Chn CCPx
s:
- Ln mc cao
- Xung mc thp
- Hay gi nguyn trng thi
Trng thi ca chn CCP s ph thc vo cc bit CCPxM3:CCPxM0.
Vic xa thanh ghi CCPxCON s y trng thi ca chn CCP xung mc
thp.
c bit trong ch ny, khi gi tr trong 2 thanh ghi TMR1 v CCPRx bng nhau
th mt xung tn hiu s c to ra. Xung ny s reset cp thanh ghi TMR1H v
TMR1L. iu ny cho php thanh ghi CCPRx hot ng ging nh mt thanh ghi
khong thi gian cho Timer 1.
3.5 Ch iu bin xung PWM:
Trong ch iu ch rng xung PWM,
chn CCP to ra mt tn hiu c phn gii 10
bit. Chn CCP phi c mc nh l ng ra.
Vic xa thanh ghi CCPxCON s y chn
ng ra CCPx xung mc mc nh thp.
3.5.1 Chu k PWM:

Chu k PWM c ch nh trong thanh ghi PR2. Chu k c th c tnh bng
cng thc:
Chu k PWM = [(PR2 + 1)*4*Tosc*gi tr t l TMR2)
Tn s PWM = 1/ chu k PWM.
Khi gi tr trong hai thanh ghi TMR2 v PR2 bng nhau, ba tc v sau y s din ra:
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Thanh ghi TMR2 b xa

Chn CCPx c set ln mc 1
Gi tr Duty cycle ( Chu k nhim v) t thanh ghi CCPRxL s chuyn sang thanh
ghi CCPRxH.
Lu : B postcaler ca Timer 2 khng c tc dng trong vic quyt nh tn s
PWM. B prescaler c kt hp vi thanh ghi TMR2 to ra b m 10 bit
tng ng.
3.5.2 Chu k nhim v ca PWM:
Gi tr chu k nhim v ca PWM c quy nh bng 10 bit : 8 bit trong thanh ghi
CCPRxL v 2 bit trong thanh ghi CCPxCON (DCxB1, DCxB0). Chu k nhim v PWM
c th c tnh theo cng thc sau:
Ton PWM = ( Gi tr ca DCxB9:DcxB0) * Tosc * gi tr t l tin nh TMR2
Gi tr DCxB9:DcxB0 c th thay i ty nhng gi tr ny s khng c ti
vo trong thanh ghi CCPRxH cho n khi trng thi cn bng xy ra gia 2 thanh ghi
PR2 v TMR2. Trong ch PWM thanh ghi CCPRxH l thanh ghi ch c.
phn gii PWM c th tnh theo cng thc sau:
3.5.3 Ci t hot ng cho PWM:

ci t hot ng cho ch PWM ta tin hnh cc bc sau:
- nh chn CCPx l ng ra.
- Thit lp chu k PWM bng vic ghi vo thanh ghi PR2
- Thit lp chu k nhim v PWM bng vic ghi gi tr vo cc bit DCxB9:DCxB0.
- Ci t gi tr t l cho Timer 2 v cho php Timer 2 hot ng bng cch ghi vo
thanh ghi T2CON.
- Cu hnh cho module CCP hot ng trong ch PWM.
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3.5.4 Module MSSP (Master Synchronous Serial Port):

Gii thiu:
Module MSSP l mt giao din ni tip,
hu dng cho vic giao tip vi cc thit b
ngoi vi hoc cc VK khc. Nhng thit b
ngoi vi ny c th l EEPROMs ni tip,
thanh ghi dch, iu khin hin th hay b bin
i ADC
Module MSSP c th hot ng mt
trong hai ch :
- SPI ( Serial Peripheral Interface)
- I2C (Inter- Intergrated Circuit)
+ Full master Mode
+ Slave Mode ( with general address
call)
Giao tip I2C cung cp cc ch sau
y trong phn cng:
- Master mode
- Multi Master Mode
- Slave Mode
Thanh ghi iu khin:
Module MSSP c 3 thanh ghi lin quan:
thanh ghi trng thi (SSPSTAT) v hai thanh
ghi iu khin (SSPCON v SSPCON2). Vic
s dng v ci t gi tr cho cc thanh ghi
ny ph thuc vo vic Module MSSP hot
ng ch no.
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CHNG IV : B BIN I ADC 10 BIT

4.1 Gii thiu module ADC 10 bit:
Trn VK c mt b bin i ADC 10bit, 8 ng vo Analog, 8 ng vo ny c
ni vi ng vo ca b chuyn i. Sau b chuyn i s to ra mt kt qu 10 bit
tng ng vi gi tr Ananlog u vo. in th tham chiu u vo s c la chn
bng phn mm (t Vdd, Vss hoc 2 chn AN2, AN3. Module ADC l module duy nht
c kh nng hot ng trong ch ng. hot ng trong ch ng Sleep, xung
clock cung cp cho ADC phi c nhn t dao ng ni RC ca ADC.
Module ADC bao gm 4 thanh ghi:
- Thanh ghi cha byte cao ca kt qu ADRESH
- Thanh ghi cha byte thp ca kt qu ADRESL
- Thanh ghi cha cc bit iu khin ADCON0
- Thanh ghi cha cc bit iu khin ADCON1
4.2 Cc thanh ghi iu khin:
Thanh ghi iu khin ADCON0:
Bit 7:6 ADCS1:ADCS0: Cc bit la chn tn s chuyn i A/D

00 =FOSC/2
01 =FOSC/4
10 =FOSC/32
11 =FRC (xung clock c ly t dao ng ni RC)
Bit 5:3 CHS2:CHS0: Cc bit la chn knh Analog
000: Knh 0, (AN0)
001: Knh 1, (AN1)
010: Knh 2, (AN2)
011: Knh 3, (AN3)
100: Knh 4, (AN4)
101: Knh 5, (AN5)
110: Knh 6, (AN6)
111: Knh 7, (AN7)
Bit 2 GO/ DONE: Bit bo trng thi chuyn i A/D
Khi bit ADON = 1
1: Qu trnh A/D ang thc hin (Khi chng ta set bit ny ln th qu trnh
chuyn i s xy ra, khi qu trnh kt thc n s t ng c xa bng
phn mm).
0: Qu trnh A/D khng xy ra hoc hon tt.
Bit 1 Khng s dng, gi tr l 0
Bit 0 ADON : Bit cho php module A/D hot ng.
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1: Ngun c cung cp cho A/D

0: Ngng cung cp ngun cho A/D
Thanh ghi iu khin ADCON1:
Bit 7 ADFM: Bit la chn nh dng kt qu A/D

1: Canh phi, 6 bit cao nht ca thanh ghi ADRESH c gi tr 0
0: Canh tri, 6 bit thp nht ca thanh ghi ADRESL c gi tr 0
Bit 6 ADCS2: Bit la chn clock chuyn i A/D
Bit 5,4
Khng s dng
Bit 3:0 PCFG3:PCFG0: Cc bit iu khin cu hnh cc chn ADC
4.3 Hot ng ca module ADC

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Hai thanh ghi ADRESH v ADRESL cha gi tr 10 bit ca kt qu ADC. Khi qu

trnh chuyn i hon tt, kt qu ADC s c lu li trong cp thanh ghi ny. Bit
GO/DONE b xa v c ngt ADIF c bt ln.
Sau khi module ADC c cu hnh nh mong mun, chng ta phi la chn
knh chuyn i A/D trc khi chuyn i ADC xy ra. Cc chn Analog phi c
chn l ng vo bng cch set cc bit trong thanh ghi TRIS tng ng.
tin hnh chuyn i ADC, tin hnh theo cc bc sau:
Bc 1: Cu hnh cho module ADC:
- Cu hnh cho cc chn ng vo/ in th chun v I/O s (ADCON1)
- La chn knh ng vo A/D (ADCON0)
- La chn tn s chuyn i (ADCON0)
- Cp ngun cho module ADC (ADCON0)
Bc 2: Cu hnh cc ngt ADC (nu cn):
- Xa c ngt ADIF
- Set bit GIE (Cho php ngt ton cc)
- Set bit ADIE (Cho php ngt chuyn i ADC)
Bc 3: i thi gian Acquisition (ly mu) cn thit
Bc 4: Bt u qu trnh chuyn i ADC:
Set bit GO/ DONE (ADCON0)
Bc 5: i qu trnh ADC hon tt:
Chy vng lp i bit GO/DONE b xa hoc c ngt ADIF bt ln
Bc 6 : c kt qu trong 2 thanh ghi ADRESH v ADRESL, xa bit ADIF ( nu cn
thit)
Bc 7: Nu mun tip tc thc hin chuyn i ADC trong chu k k tip th quay li
bc 1 hoc bc 2.
S khi ca b bin i ADC 10 bit:
4.4 Thi gian ly mu:
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Thi gian ly mu bao gm hai giai on:

Thi gian acquition: L thi gian cn t in ca b sample and hold (tm dch
l b ly mu v gi) np in c gi tr in th bng vi gi tr ca ngun analog
cn ly mu.
Thi gian chuyn i t tng t sang s: Vo khong 12 chu k ca b ADC.
Tng 2 thi gian ta c thi gian ly mu
Cch tnh thi gian acquition:
TACQ = Thi gian n nh ca phn cng khuch i + Thi gian np ca t + h
s nhit
TACQ = TAMP + TC + TCOFF
= 2s + TC +[(Nhit - 250C)(0.05/0C)]
= 19.72 s
4.5 La chn xung clock cho bin i A/D:

Thi gian chuyn i 1 bit c nh ngha l chu k TAD. bin i 10 bit
chng ta cn thi gian xp x 12TAD . Ngun xung clock cung cp cho ADC c la
chn bng phn mm. C 4 gi tr la chn:
- 2 Tosc
- 8 Tosc
- 32 Tosc
- Dao ng ni RC ca module ADC (2-6s)
m bo qu trnh ADC chnh xc th xung clock ADC (TAD) phi c la
chn m bo rng gi tr ti thiu ca TAD l 1.6s.
Bng sau y ch ra mi lin h gia TAD v tn s ca thit b:
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4.6 Cu hnh cc chn Analog:

Cc thanh ghi ADCON1 v TRIS iu khin hot ng ca cc chn ADC. i vi
cc chn cn c quy nh l ng vo Analog th cc bit tng ng trong thanh ghi
TRIS phi c set, nu cc bit trong thanh ghi TRIS b xa (output) th cc ng ra s
(VOH hoc VOL) s c chuyn i. Hot ng ca b ADC s ph thuc vo trng
thi ca cc bit CHS2:CHS0 v cc bit trong thanh ghi TRIS.
4.7 Chuyn i ADC:
Vic xa bit GO/DONE trong qu trnh chuyn i s b qua chuyn i hin ti.
Cp thanh ghi kt qu chuyn i ADC s khng c cp nht nhng mu chuyn i
ADC hon tt. Do , cp thanh ghi ADRESH v ADRESL s cha gi tr ca ln
chuyn i hon tt cui cng ( hoc gi tr c ghi cui cng vo 2 thanh ghi ny).
Sau khi mt chuyn i ADC b b qua, vic ly mu tip theo da trn knh ADC
chn s t ng din ra. Sau bit GO/DONE c th c set bt u chuyn i
ADC.
Ch : Bit GO/DONE khng nn c set trong cng mt lnh vi lnh m
module ADC.
Cp thanh ghi ADRESH v ADRESL dng lu kt qu ADC 10 bit. Module

ADC cho php ta la chn vic canh tri hay canh phi kt qu 10 bit trong thanh ghi kt
qu bng cch xa hoc set bit ADFM. Cc bit cn li mang gi tr l 0.
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4.8 Hot ng ca module ADC trong ch ng:

Module ADC c th hot ng trong ch ng (Sleep). iu ny yu cu ngun
xung clock cung cp cho ADC phi t dao ng RC (ADCS1:ADCS0 = 11). Khi xung
clock RC c chn, module ADC s i mt chu k my trc khi bt u tin hnh
chuyn i ADC. iu ny cho php lnh SLEEP c th c thc thi m khng gy
nhiu n qu trnh ADC. Khi chuyn i ADC hon tt, bit GO/DONE s b xa v kt
qu c lu vo cp thanh ghi ADRESH, ADRESL. Nu ngt ADC c cho php, n
s lm VK thot khi ch ng. Nu ngt khng c cho php, module ADC sau
s b tt mc d bit ADCON vn cn mc cao.
Khi ngun xung clock khc c chn ch khng phi RC, lnh SLEEP s lm cho
chuyn i ADC hin ti b b qua v module ADC s b tt d bit ADCON vn cn
ang mc 1.
4.9 nh hng ca Reset:
Mt reset thit b s buc tt c cc thanh ghi ri vo trng thi Reset ca chng.
iu ny buc module ADC b tt v bt k chuyn i ADC no cng b b qua. Tt c
cc chn ng vo A/D s c cu hnh l cc ng vo Analog.
Gi tr trong cp thanh ghi ADRESH:ADRESL khng b thay i trong mt Reset
Power-on. Cp thanh ghi ny s cha mt gi tr khng bit trc sau reset Power-on.
Cc thanh ghi v cc bit lin quan n module ADC:
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CHNG V : IN TH THAM CHIU V CC B SO

SNH IN
5.1 Module Comparator:
5.1.1 Gii thiu module comparator :
Module so snh (Compararor) cha 2 b so snh tng t. Ng vo ca b so snh
c a hp vi cc chn xut nhp t RA0 n RA3 trong khi ng ra li a hp vi cc
chn RA4 v RA5. in th trn chip cng c th a vo ng vo ca b so snh.
Thanh ghi CMCON iu khin ng vo v ng ra ca b so snh.
Bit 7 C2OUT: Bit cho bit kt qu ng ra ca b so snh 2

Khi C2INV = 0:
1: Nu C2Vin+ > C2Vin0: Nu C2Vin+ < C2VinKhi C2INV = 1:
1: Nu C2Vin+ < C2Vin0: Nu C2Vin+ > C2VinBit 6 C1OUT : Bit ng ra b so snh 1
Khi C1INV = 0:
1: Nu C1Vin+ > C1Vin0: Nu C1Vin+ < C1VinKhi C1INV = 1:
1: Nu C1Vin+ < C1Vin0: Nu C1Vin+ > C1VinBit 5 C2INV : Bit o ng ra b so snh 2
1: Ng ra C2 o
0: Ng ra C2 khng o
Bit 4 C1INV: Bit o ng ra b so snh 1
1: Ng ra C1 o
0: Ng ra C1 khng o
Bit 3 CIS: Bit chuyn i ng vo b so snh
Khi CM2:CM0 = 110:
1: C1 Vin- ni vi chn RA3/AN3
C2 Vin- ni vi chn RA2/AN2
0: C1 Vin- ni vi chn RA0/AN0
C1 Vin- ni vi chn RA1/AN1
Bit 2-0 CM2:CM0: Bit chn ch hot ng ca b so snh.
5.1.2 Ci t ch cho b so snh:
C 8 ch hot ng ca b so snh, thanh ghi CMCON c s dng la
chn nhng ch ny. Thanh ghi TRIS iu khin cc chn I/O ca b so snh trong
mi ch . Nu ch so snh b thay i, ng ra ca b so snh s khng cn chnh
xc na.
Trang 61
GVHD:Thc s L nh Kha
Lu : Cc ngt do b so snh sinh ra nn c cm trong sut qu trnh thay i

ch hot ng, nu khng cc ngt ngoi mun c th sinh ra.
Mt b so snh n c trnh by
trong hnh bn cnh y, n cho chng ta
bit s thay i trng thi logic ng ra
tng ng vi trng thi tn hiu Analog
ng vo.
Khi VIN+ > VIN- th ng ra ln mc
cao v ngc li.
Ti nhng cnh ny ng ra khng
bit chc chn.
Trang 62
GVHD:Thc s L nh Kha
5.1.3 Ngun tham chiu ca b so snh:

Mt ngun tham chiu ni hoc ngoi c th c s dng. Vic la chn ngun
ni hay ngoi ty thuc vo ch hot ng ca b so snh.
5.1.3.1 Tn hiu in th tham chiu ngoi:
Khi s dng ngun tham chiu ngoi, module so snh c th c cu hnh hot
ng t mt hoc 2 ngun so snh khc nhau. in th so snh phi nm trong khong t
Vss n Vdd v in p ny c th c a vo bt c mt chn no ca b so snh.
5.1.3.2 Tn hiu in th tham chiu ni:
Module so snh cng cho php la chn mt in th so snh ni dng cho cc b
so snh. Tn hiu tham chiu ni c s dng trong ch so snh CM2:CM0 = 010.
Trong ch ny tn hiu so snh ni c a vo chn VIN+ ca 2 b so snh.
5.1.4 Thi gian p ng:
Thi gian p ng l thi gian tnh t khi la chn mt in th tham chiu hoc
mt tn hiu ng vo cho n khi c mt gi tr in p hp l ng ra.
5.1.5 Tn hiu ng ra ca cc b so snh:
Tn hiu ng ra ca cc b so snh c c thng qua thanh ghi CMCON khi cc
bit ny sn sng. Ng ra ca cc b so snh c th c ni trc tip vi cc chn
xut nhp RA4 v RA5, cc chn ny phi c cu hnh l ng ra trong ch ny.
Ch :
- Khi cc chn port c cu hnh l cc chn ng vo Analog, vic c cc thanh
ghi port s cho gi tr l 0
S khi chn ng ra ca cc b so snh
Trang 63
GVHD:Thc s L nh Kha
5.1.6 Ngt ca cc b so snh:

C ngt CMIF ca cc b so snh c bt ln khi gi tr ng ra ca cc b so snh
thay i so vi gi tr ca bit CMxOUT. C ngt ny phi c xa bng phn mm
mt ngt k tip c th xy ra.
Ngoi ra mt ngt c th xy ra chng ta cn phi set cc bit CMIE, PEIE, GIE
ln 1
5.1.7 Hot ng ca cc b so snh trong ch ng:
Cc b so snh vn hot ng trong ch ng v cc ngt vn c th xy ra nu
c cho php. Do cc ngt ny s nh thc VK.
5.1.8 nh hng ca Reset:
Khi mt Reset thit b xy ra, n s buc thanh ghi CMCON v trng thi reset ca
n, lm cho module ri vo ch tt, CM2:CM0 = 111.
Cc thanh ghi lin quan n module so snh:
5.2 Module in p tham chiu :

5.2.1 Gii thiu module in th tham chiu
Module in p tham chiu so snh c s dng ch yu vi module so snh khi
cn s dng ngun so snh l ngun ni.
Module in p tham chiu bao gm mt h thng 16 in tr, h thng in tr
ny s cung cp cho chng ta mt in p tham chiu c th lp trnh c .
Dy in tr ny c chia nh ra cung cp cho chng ta cc in th tham chiu
khc nhau.
S khi ca module in th so snh
Trang 64
GVHD:Thc s L nh Kha
5.2.2 Thanh ghi iu khin CVRCON:
Bit 7 CVREN: Bit cho php CVR hot ng.

1: Cung cp ngun cho CVR
0: Ngng cp ngun cho CVR.
Bit 6 CVROE: Cho php ng ra CVR
1: in p CVREF l ng ra trn chn RA2
0: in p CVREF khng kt ni vi chn RA2
Bit 5 CVRR: Bit la chn di gi tr hot ng ca CVREF
1: 0 n 0.75 CVRSRC, vi kch thc mi buc l CVRSRC/24
0: 0.25 CVRSRC n 0.75 CVRSRC, vi kch thuc bc l CVRSRC/32
Bit 4 Khng s dng, gi tr l 0
Bit 3-0 CVR3:CVR0: Cc bit la chn gi tr VREF ( 0 <= VR3:VR0 <= 15)
Khi VRR =1:
VREF = ( VR<3:0>/24) * Vdd
Khi VRR = 0:
VREF = * VDD + ( VR<3:0>/32) * Vdd
Bng in th tham chiu tiu biu vi VDD=5.0V
CVR3:CVR0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VREF
CVRR =1
0.00V
0.21V
0.42V
0.63V
0.83V
1.04V
1.25V
1.46V
1.67V
1.88V
2.08V
2.29V
2.50V
2.71V
2.92V
3.13V
CVRR =0
1.25V
1.14V
1.56V
1.72V
1.88V
2.03V
2.19V
2.34V
2.50V
2.66V
2.81V
2.97V
3.13V
3.28V
3.44V
3.59V
Trang 65
GVHD:Thc s L nh Kha
5.2.3 chnh xc ca in th tham chiu:

Gi tr in th VREF khng th bng Vdd hay Vss c v c hai con transistor
hai u.
5.2.4 Hot ng ca module VREF trong trng thi ng
Khi VK thot khi trng thi ng hay watchdog timer, ni dung ca thanh ghi
CVRCON s khng cn tc dng. hn ch cng sut tiu th, trong ch ng
module in th tham chiu nn cm.
5.2.5 Trng thi ca module khi reset:
Khi VK c reset n s xa bit CVREN, bit CVROE, bit CVRR v cc bit
CVRCON<3:0>
5.2.6 S dng module vi cc mch ngoi :
Nn nh rng module VREF hot ng c lp vi module comparator. Ng ra ca
module ny c th c kt ni vi chn ng ra nu bit tng ng trong thanh ghi TRIS
c xa. Vic cho php module VREF cung cp in th cho cc mch ngoi s lm
tng cng sut ca VK. Ngoi ra module ny c th dng nh b bin i D/A n
gin. Do s gii hn v dng in ng ra nn mt Bufer in th c s dng m
bo chnh xc ca tn hiu in th.
Cc thanh ghi lin quan n in p tham chiu
Trang 66
GVHD:Thc s L nh Kha
PHN II
CC THNH PHN CA KIT

THC TP PIC 16F877A
CHNG I: HIN TH LED N.
CHNG II: HIN TH LED 7 ON.
CHNG III: N GIAO THNG.
CHNG IV: CHY CH LED MATRN.
CHNG V: HIN TH LCD.
CHNG VI: ADC
CHNG VII: BN PHM GIAO TIP LCD.
CHNG VIII: GIAO TIP I2C
CHNG IX: O NHIT DNG LM35
Trang 67
GVHD:Thc s L nh Kha
CHNG I : HIN TH LED N

1.1 Gii Thiu Chung:
LED (vit tt ca Light Emitting Diode, c ngha l it pht quang) l cc it c
kh nng pht ra nh sng hay tia hng ngoi, t ngoi. Cng ging nh it, LED c
cu to t mt khi bn dn loi p ghp vi mt khi bn dn loi n.
Hot ng ca LED ging vi nhiu loi it bn dn. Khi bn dn loi p cha
nhiu l trng t do mang in tch dng nn khi ghp vi khi bn dn n (cha cc
in t t do) th cc l trng ny c xu hng chuyn ng khuch tn sang khi n.
Cng lc khi p li nhn thm cc in t (in tch m) t khi n chuyn sang. Kt qu
l khi p tch in m (thiu ht l trng v d tha in t) trong khi khi n tch in
dng (thiu ht in t v d tha l trng).
bin gii hai bn mt tip gip, mt s in t b l trng thu ht v khi chng
tin li gn nhau, chng c xu hng kt hp vi nhau to thnh cc nguyn t trung ha.
Qu trnh ny c th gii phng nng lng di dng nh sng (hay cc bc x
in t c bc sng gn ).
Ty theo mc nng lng gii phng cao hay thp m bc sng nh sng pht ra
khc nhau (tc mu sc ca LED s khc nhau). Mc nng lng (v mu sc ca LED)
hon ton ph thuc vo cu trc nng lng ca cc nguyn t cht bn dn.
LED thng c in th phn cc thun cao hn it thng thng, trong khong 1,5
n 3 V. Nhng in th phn cc nghch LED th khng cao. Do , LED rt d b h
hng do in th ngc gy ra.
Loi LED
Vng
Xanh l cy
in th phn cc thun
1,4 - 1,8V
2 - 2,5V
2 - 2,8V
Trang 68
GVHD:Thc s L nh Kha
1.2 Mch Nguyn L
VCC
4R2
1
L6
L7
1
L5
L4
L3
L2
L1
8
7
6
5
4
3
2
1
L0
9
8
7
6
5
4
3
2
330
LEDDON
Vi VCC = 5VDC , in p trung bnh trn mi LED l 2V, dng qua LED l
10mA th in tr hn dng cho LED l:
Rled =
5VDC 2VDC
= 300
10mA
Chn Rled = 330
Trang 69
GVHD:Thc s L nh Kha
CHNG II : HIN TH LED 7 ON

2.1 Cc khi nim c bn
Trong cc thit b, bo trng thi hot ng ca thit b cho ngi s dng vi
thng s ch l cc dy s n thun, thng ngi ta s dng "led 7 on". Led 7 on
c s dng khi cc dy s khng i hi qu phc tp, ch cn hin th s l , chng
hn led 7 on c dng hin th nhit phng, trong cc ng h treo tng bng
in t, hin th s lng sn phm c kim tra sau mt cng on no ...
Led 7 on c cu to bao gm 7 led n c dng thanh xp theo hnh v c thm
mt led n hnh trn nh th hin du chm trn gc di, bn phi ca led 7 on.
Tm led n trn led 7 on c Anode(cc +) hoc Cathode(cc -) c ni chung
vi nhau vo mt im, c a chn ra ngoi kt ni vi mch in. 8 cc cn li
trn mi led n c a thnh 8 chn ring, cng c a ra ngoi kt ni vi
mch in. Nu led 7 on c Anode(cc +) chung, u chung ny c ni vi +Vcc,
cc chn cn li dng iu khin trng thi sng tt ca cc led n, led ch sng khi
tn hiu t vo cc chn ny mc 0. Nu led 7 on c Cathode(cc -) chung, u
chung ny c ni xung Ground (hay Mass), cc chn cn li dng iu khin trng
thi sng tt ca cc led n, led ch sng khi tn hiu t vo cc chn ny mc 1.
V led 7 on cha bn trong n cc led

n, do khi kt ni cn m bo dng qua mi
led n trong khong 10mA-20mA bo v led.
Nu kt ni vi ngun 5V c th hn dng bng
in tr 330 trc cc chn nhn tn hiu iu
khin
S v tr cc led c trnh by nh hnh
bn: Cc in tr 330 l cc in tr bn ngoi
c kt ni gii hn dng in qua led nu
led 7 on c ni vi ngun 5V. Chn nhn tn
hiu a iu khin led a sng tt, ng vo b iu
khin led b. Tng t vi cc chn v cc led cn li.
Trang 70
GVHD:Thc s L nh Kha
2.2 Kt ni vi Vi iu Khin
Ng nhn tn hiu iu khin ca led 7 on c 8 ng, v vy c th dng 1 Port
no ca Vi iu khin iu khin led 7 on. Nh vy led 7 on nhn mt d liu
8 bit t Vi iu khin iu khin hot ng sng tt ca tng led led n trong n, d
liu c xut ra iu khin led 7 on thng c gi l "m hin th led 7 on". C
hai kiu m hin th led 7 on: m dnh cho led 7 on c Anode (cc +) chung v m
dnh cho led 7 on c Cathode (cc -) chung. Chng hn, hin th s 1 cn lm cho
cc led v tr b v c sng, nu s dng led 7 on c Anode chung th phi t vo hai
chn b v c in p l 0V (mc 0) cc chn cn li c t in p l 5V(mc 1), nu
s dng led 7 on c Cathode chung th in p (hay mc logic) hon ton ngc li,
tc l phi t vo chn b v c in p l 5V (mc 1).
Bng m hin th led 7 on:
Phn cng c kt ni vi 1 Port bt k ca Vi iu khin, thun tin cho vic
x l v sau phn cng nn c kt ni nh sau: Px.0 ni vi chn a, Px.1 ni vi chn
b, ln lt theo th t cho n Px.7 ni vi chn h.
D liu xut c dng nh phn nh sau : hgfedcba
Bng m hin th led 7 on dnh cho led 7 on c Anode chung (cc led n
sng mc 0):
S hin th trn led M hin th led 7 on dng
7 on
nh phn
hgfedcba
0
11000000
1
11111001
2
10100100
3
10110000
4
10011001
5
10010010
6
11000010
7
11111000
8
10000000
9
10010000
A
10001000
B
10000011
M hin th led 7 on dng

thp lc phn
C0
F9
A4
B0
99
92
82
F8
80
90
88
83
Trang 71
C
D
E
F
-
11000110
10100001
10000110
10001110
10111111
GVHD:Thc s L nh Kha
C6
A1
86
8E
BF
Bng m hin th led 7 on dnh cho led 7 on c Cathode chung (cc led n sng
mc 1):
S hin th trn led M hin th led 7 on dng M hin th led 7 on dng

7 on
nh phn
thp lc phn
0
00111111
3F
1
00000110
06
2
01011011
5B
3
01001111
4F
4
01100110
66
5
01101101
6D
6
01111101
7D
7
00000111
07
8
01111111
7F
9
01101111
6F
A
01110111
77
B
01111100
7C
C
00111001
39
D
01011110
5E
E
01111001
79
F
01110001
71
01000000
40
2.3 Giao Tip Vi iu Khin Vi Nhiu Led 7 on :
Nu kt ni mi mt Port ca Vi iu khin vi 1 led 7 on th ti a kt ni c
4 led 7 on. Mt khc nu kt ni nh trn s hn ch kh nng thc hin cc cng vic
khc ca Vi iu khin. Cho nn cn phi kt ni, iu khin nhiu led 7 on vi s
Trang 72
GVHD:Thc s L nh Kha
lng chn iu khin t Vi iu khin cng t cng tt. C hai gii php: mt l s dng
cc IC chuyn dng cho vic hin th led 7 on, hai l kt ni nhiu led 7 on vo cng
mt ng xut tn hiu hin th. Ni phn ny s cp n cch kt ni nhiu led 7
on theo gii php th 2.
Mt ngi c c im sinh l l ch thu nhn 24 hnh/giy tng hp cc hnh
nh v th gii xung quanh. Nu mt tn hiu nh sng c chu k sng tt hn 24 ln
trong 1 giy, mt ngi lun cm nhn l mt ngun sng lin tc. minh ha cho
iu ny, bn hy ly cc chng trnh thc hin vi led n v lm ngn thi gian
delay li, n mt gi tr no bn s thy cc led u sng lin tc.
kt ni nhiu led 7 on vo vi iu khin thc hin nh sau: ni tt c cc chn
nhn tn hiu ca tt c cc led 7 on (chn abcdefgh) cn s dng vo cng 1 Port, 6
led 7 on c cc chn nhn tn hiu cng c c ni vi PC. Dng cc ng ra cn
li ca Vi iu khin iu khin on/off cho led 7 on, mi ng ra iu khin ON/OFF
cho 1 led 7 on, (ON: led 7 on c cp ngun hin th, OFF: led 7 on b ngt
ngun nn khng hin th c).
61
52
43
34
25
16
60PA
6RN3
7
8
9
10
11
12
4.7K
VCC
h
g
f
e
d
c
b
a
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A
B
C
D
E
F
G
H
330
16
15
14
13
12
11
10
9
A
B
C
D
E
F
G
H
6RN2
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
6LED6
6LED5
A
B
C
D
E
F
G
H
8
7
6
5
4
3
2
1
6LED4
6LED3
A
B
C
D
E
F
G
H
60PC
6LED2
Q6
A1015
Q5
A1015
A
B
C
D
E
F
G
H
VCC
6LED1
Q4
A1015
Q3
A1015
VCC
Q2
A1015
Q1
A1015
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
Trong s trn, led 7 on c s dng l loi c Anode chung, vi tt c cc

chn nhn tn hiu c kt ni vi Port C qua in tr hn dng. iu khin
Trang 73
GVHD:Thc s L nh Kha
ON/OFF cho cc led 7 on, s dng transitor loi PNP, transitor ny nhn dng iu
khin t mt ng ra ca Vi iu khin, led 7 on s c ON khi tn hiu t vi iu
khin n transitor mc 0. C th s transitor loi A1015hoc 2N3905 hoc mt
transitor PNP khc c thng s ph hp. Cc in tr 4.7K v in tr treo 4.7K m bo
transitor lun hot ng ch bao ha .Port A dng chn led 7 on (m bo khi
led 7 on ang trng thi OFF s b tt hon ton, khng b sng m m).
Ti mi thi im, ch nn cho Vi iu khin iu khin cho 1 led 7 on hot
ng, do ti mi thi im ch nn c 1 ng ra duy nht ni vi transitor mc 0. Ti
mi thi im ch c mt led 7 on c ON nn s khng xy ra tnh trng qu ti cho
ti v qu ti cho vi iu khin khi iu khin nhiu led 7 on.
Trong s kt ni trn, chng hn cn hin th s 451, qui c th t cc led 7
c m t phi sang tri, nh vy cn lm cho led 7 on th nht hin th s 1, led 7
on th hai hin th s 5, led 7 on th 3 hin th s 4, cc led cn li khng hin th.
u tin OFF tt c cc led 7 on. K tip xut m hin th led 7 on hin th s 1,
ON led 7 on th nht, lc ny dng in ch i qua led 7 on th nht, lm cho led 7
on th nht hin th s 1, thi gian ON trong khong vi chc s(1s=1/10-6s). K tip
xut m hin th led 7 on hin th s 5, OFF led 7 on th nht v ng thi ON led 7
on th 2, lc ny ch c led 7 on th hai hin th v hin th s 5. Tip theo xut m
hin th led 7 on hin th s 4, OFF led 7 on th hai v ON led 7 th ba, lc ny ch
duy nht led 7 on th ba hin th s 4. C th lp li qu trnh trn lin tc. Thi gian
ON/OFF ch trong khong vi chc s, v ti mi thi im ch c mi mt led 7 on
hin th s ca chnh n, v vy mt ngi thy 3 led 7 on khng sng t qung, m
sng lin tc, mi led hin th 1 s ring ca n. Thc hin tng t m rng s lng
led 7 on cn s dng.
2.4 Lu d gii thut:
Bt u
Qut led 1,2
Xut d liu
Trang 74
GVHD:Thc s L nh Kha
2.5 Mch nguyn l:
61
52
43
34
25
16
60PA
6RN3
7
8
9
10
11
12
4.7K
VCC
VCC
A
B
C
D
E
F
G
H
VCC
VCC
VCC
A
B
C
D
E
F
G
H
VCC
VCC
VCC
VCC
VCC
6LED6
A
B
C
D
E
F
G
H
330
h
g
f
e
d
c
b
a
6LED5
6LED4
A
B
C
D
E
F
G
H
16
15
14
13
12
11
10
9
Q6
A1015
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
VCC
VCC
6RN2
8
7
6
5
4
3
2
1
Q5
A1015
Q4
A1015
A
B
C
D
E
F
G
H
60PC
6LED3
6LED2
6LED1
Q3
A1015
Q2
A1015
VCC
Q1
A1015
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
Mt led 7 on do 8 led n ghp li do in tr hn dng cho led l 330

5V
Led sng bnh thng th: Ic = Iled =10mA.

Ic8led =80mA
Ta c: IC8 led = ICS = 80mA
Chn =80
IBS =
RB =
I CS
= 1 mA ( IB=IBS )
VCC VEB
5 0 .8
=
= 4.2 K
IB
1mA
RB
Q1
A1015
330
RC
LED
Chn RB = 4.7 K
Trang 75
GVHD:Thc s L nh Kha
CHNG III : N GIAO THNG

3.1 Gii thiu:
Giao thng l mt vn c bn ca cuc sng, tuy nhin vi tnh hnh giao thng
nh hin nay Vit Nam th vn ny tr nn rt bc xc i vi ngi tham gia
giao thng. Khi tham gia giao thng, chng ta s phi chp hnh theo tn hiu n giao
thng. Vy bn c bit h thng n ny hot ng nh th no ko? Vi mc ch tm
hiu s hot ng ca mt h thng n giao thng nhm chng em c gng vit mt
chng trnh n gin.
Vi kin thc v vi x l cn hn ch, chc chn chng trnh ti vit s cn nhiu
sai st, mong nhn c s gp ca ngi c. Chn thnh cm n!
Hot ng ca cc n nh hnh:
X1 2
T1
T4
V1 2
1 V2
T3
T2
1 X2
Gin xung:
X1
V1
1
X2
V2
2
T
Trang 76
GVHD:Thc s L nh Kha
3.2 S nguyn l:
Trang 77
GVHD:Thc s L nh Kha
3.3 Lu gii thut:

BEGIN
Xanh 1 = 0, 2 = 0
DL 7s
Vng 1 = 0, 2 = 0
DL 3s
Xanh 2 = 0, 1 = 0
S
DL 7s
Vng 2 = 0, 1 = 0
S
DL 3s
Trang 78
GVHD:Thc s L nh Kha
CHNG IV : LED MA TRN

4.1 Hin th led Ma Trn
4.1.1 Gii Thiu:
Led ma trn l mt thut ng quen thuc ngy nay, nhng ta nn lt qua s pht
trin v ng dng ca cc dng c ny:
Silicon carbide l vt liu u tin c ghi nhn l pht ra nh sng lnh t
lnh y dng phn bit qu trnh pht x t s bc x en m vt liu nng ln
khi c dng in i qua. Cho n gn 1940, ngi ta nhn thy min pht sng l tip
xc p-n. Nhng cng trnh trc nm 1950 bo co l s pht sng c t nhiu vt
liu dng cc diode bn dn kim loi tip xc im: GaP, GaAs, GaSb, InP v Ge, Si.
Ri i n bc k tip dng bn dn hn hp (compound semiconductor) c c
nh sng ra nhiu hn.
Cc ng dng ca led ma trn nh dng ch th, hin th, lm ngun sng trong
cc my in laser, v quan trng hn l cc led ma trn c s dng rng ri trong cc h
thng thng tin da vo quang si.
S la chn vt liu quyt nh mu ca nh sng pht ra. Vi cc hin th v b ch
th th cn c cc led ma trn nh sng thy c, tri li vi thng tin quang si cn c
mt mt thp, tn x thp trong si v kh dng cc b pht hin thch hp.
Led ma trn c coi l mt trong cc ngun quang in t, ph bin nht. N
khng t, tiu th t cng sut, v d dng thch hp cho cc mch in t.
4.1.2 Led Ma Trn 8x8:
Led matrix l led ma trn hin th bao gm nhiu led ma trn nh kt hp li to
thnh mt ma trn gm m ct v n hng (led ma trn mn). Led ma trn 88 l led ma
trn gm c 8 ct v 8 hng. Led ma trn ny c hai loi: loi th nht l common
cathode (cathode chung ct cathode, hng anode), loi th hai l common anode
(anode chung ct anode, hng cathode).
S chn ra v hnh dng thc t:
Hnh 4.1 : Hnh dng

thc t v s chn
led ma trn 8 x 8.
U1
12
9
6
3
13
16
19
22
h1
h2
h3
h4
h5
h6
h7
h8
matrix 8x8
c1 c2 c3 c4 c5 c6 c7 c8
10
7 4 1
15 18 21 24
Trang 79
GVHD:Thc s L nh Kha
(a)
(b)
Hnh 4.2: S cu trc bn trong ca led ma trn: (a) cathode chung, (b) anode
chung.
4.2 Phng Php Hin Th Dng IC Cht:
Hin th led ma trn bng phng php cht gip cho ngi lp trnh thay i cch
thc qut v hin th mt cch linh hot v nhanh chng.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
12
9
6
3
13
16
19
22
11
1
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
c1
c2
c3
c4
c5
c6
c7
c8
2
3
4
5
6
7
8
9
matrix_3mau
23
20
17
14
2
5
8
11
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
U7
LE
OE
11
1
D0
D1
D2
D3
D4
D5
D6
D7
DM74LS573
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
OE
LE
DM74LS573
1
11
hx8
hx7
hx6
hx5
hx4
hx3
hx2
hx1
24
21
18
15
1
4
7
10
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
12
13
14
15
16
17
18
19
hd8
hd7
hd6
hd5
hd4
hd3
hd2
hd1
DM74LS573
Hnh 4.3: Giao tip led ma trn dng phng php cht.
Trang 80
GVHD:Thc s L nh Kha
4.2.1 Cht Hng:

Cht hng l phng php trong mt khong
thi gian xc nh ch c mt ct c tch cc, d
liu c a ra 8 hng ri cht li, d liu c
hin th trn mn hnh led ma trn. Sau d liu
k tip c a ra 8 hng v c cht li bi mt
IC cht khc, trong khi d liu trc vn hin
din ti ng ra ca IC cht. Nh vy d liu ca
hng no c a ra ng a ch ca hng
trong khi cc d liu ca cc hng khc vn hin
din trn hng m khng b mt i. Vic thc hin
cht hng c th hin lu nh sau:
Hnh 4.4: Qui trnh hin th cht hng.

4.2.2 Cht Ct:
Cht ct l phng php trong mt
khong thi gian xc nh ch c mt hng
c tch cc, d liu c a ra 8 ct ri
cht li, d liu c hin th trn mn hnh
Led ma trn. Sau d liu c a ra 8 ct
k tip v c cht li bi mt IC cht khc,
trong khi d liu trc vn hin din ti
ng ra ca IC cht (d liu vn hin din ti
cc ct). Nh vy d liu ca ct no c
a ra ng a ch ca ct trong khi cc
d liu ca cc ct khc vn hin din trn ct
m khng b mt i. Vic thc hin cht ct
c th hin lu nh sau:
Hnh 4.5: Qui trnh hin th cht ct..
Trang 81
GVHD:Thc s L nh Kha
Phng Php Hin Th Led Ma Trn S Dng IC Cht:

u im:
M rng s hng, s ct ca bng quang bo.
D liu c truyn i nhanh.
Chuyn i cch qut hng, ct mt cch linh hot.
Nhc im:
To bng m kh khn.
Kh khn trong vic lp trnh xut d liu ra.
4.3 Phng Php Dng Thanh Ghi Dch:
4.3.1 Qut Hng:
4.3.1.1 Gii thiu chung v phng php qut hng.
Phng php qut hng l phng php m trong mt khong thi gian xc nh ch
cho mt hng c tch cc hin th trong khi cc hng khc u tt, cc hng c qut
(tch cc) tun t cc khong thi gian k tip nhau c lp li nhiu ln vi tc >
25hnh/1s s cho ta mt hnh nh lin tc cn hin th ln trn mn hnh Led ma trn.
Vdd
Vdd
R2
R3
Q5
HB.1
R15 R
Q2
Q6
H1
H2
Vdd
R26
R25
Q12
HB.5
Q16
R39 R
Q13
12
9
6
3
13
16
19
22
Q17
matrix_3mau
R4
HB.2
Q3
HB.3
Q7
R17 R
18
Q4
SDO
R16 R
R13 R
Q8
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
R5
R
R12 R
23
20
17
14
2
5
8
11
Vdd
17
16
15
14
7
6
5
4
Vdd
24
21
18
15
1
4
7
10
H5
4
5
6
7
14
15
16
17
hd8
hd7
hd6
hd5
hd4
hd3
hd2
hd1
H6
U10
TPIC6B595
18
R38 R
R34 R
c1
c2
c3
c4
c5
c6
c7
c8
R33 R
HB.4
H8
H7
H6
H5
H4
H3
H2
H1
Vdd
SDO
R14 R
Q1
hx8
hx7
hx6
hx5
hx4
hx3
hx2
hx1
HB.0
R11 R
DRAIN7
DRAIN6
DRAIN5
DRAIN4
DRAIN3
DRAIN2
DRAIN1
DRAIN0
R10 R
U9
HB.6
SRCLK
RCLK
SDI
3
SRCLR
G
8
9
13
12
R36 R
G
SRCLR
R24
R23
R31 R
9
8
SDI
3
Vdd
12
13
H4
H3
Vdd
RCLK
SRCLK
TPIC6B595
R32 R
Q10
R37 R
HB.7
Q14
Q11
Q15
H8
H7
Hnh 4.6: S mch thanh ghi.

Trang 82
GVHD:Thc s L nh Kha
4.3.1.2. Qu trnh thc hin qut hng:

Qut hng s dng thanh ghi dch l tng i phc tp cho ngi lp trnh trong
vic a d liu ra ct. D liu ln lt c a vo chn Datain ca thanh ghi dch sau
tc ng xung clock d liu c dch i.
VD: a d liu ra 8 ct c din ra nh sau.
Hnh 4.7: Qui trnh a d liu ra 8 ct cho led ma trn.

D liu ca hng th nht c a ra ct sau tch cc hng th nht nh vy d
liu ca hng th nht c hin th trn mn hnh Led ma trn, tip tc d liu ca hng
th hai c a ra ct sau tch cc hng th hai lc ny d liu ca hng th hai
c hin th trn man hnh Led ma trn, c nh vy cho n d liu ca hng cui cng
c a ra ct sau tch cc hng cui cng. C nh th qu trnh trn c lp i
lp li > 25ln/1s, n y chng ta quan st c mt hnh nh lin tc hin th trn
mn hnh Led ma trn.
4.3.1.3.V d:
Hin th ch B ln mn hnh Led ma trn(hng c tch cc mc 1, ct c tch
cc mc 0).
Trang 83
GVHD:Thc s L nh Kha
Hng 1
Hng 8
Ct 8
Hnh 4.8: Hin th ch B trn led ma trn dng phng php qut hng.
D liu th nht c ga tr: 11111111 c a ra ct tch cc hng th nht (iu
khin hng th nht cho ra gi tr l 1); d liu th hai c gi tr: 00001111 a ra ct,
tch cc hng th hai; d liu th 3 c gi tr: 01110111 a ra ct, tch cc hng th 3;
d liu th 4 c gi tr: 01110111 a ra ct, tch cc hng th 4; tip tc d liu hng
th 5 c gi tr: 00001111 a ra ct, tch cc hng th 5; k tip l d liu ca hng th
6 c gi tr: 01110111 c a ra ct, tch cc hng th 6 ; d liu ca hng th 7 c
gi tr: 01110111 a ra ct, tch cc hng th 7; d liu th 8 c gi tr: 00001111 a
ra ct, tch cc hng th 8. Nh vy ton b d liu ca ch B c a ra hin th
trn mn hnh Led ma trn. Qu trnh trn c din ra rt nhanh > 24ln/ 1s nn chng
ta c cm gic n din ra mt cch ng thi nh m chng ta quan st c trn mn
hnh Led ma trn l mt ch B lin tc.
4.3.2 Qut Ct:
4.3.2.1 Gii thiu chung v phng php qut ct.
Phng php qut ct l phng php m trong mt khong thi gian xc nh ch
cho mt ct c tch cc hin th trong khi cc ct khc u tt, cc ct c qut (tch
cc) tun t cc khong thi gian k tip nhau c lp li nhiu ln vi tc >
25hnh/1s s cho ta mt hnh nh lin tc cn hin th ln trn mn hnh Led ma trn.
4.3.2.2 Qu trnh thc hin qut ct.
D liu ca ct th nht c a ra hng sau tch cc ct th nht nh vy d
liu ca ct th nht c hin th trn mn hnh Led ma trn, tip tc d liu ca ct th
hai c a ra hng sau tch cc ct th hai lc ny d liu ca hng th hai c
hin th trn mn hnh Led ma trn, c nh vy cho n d liu ca ct cui cng c
a ra hng sau tch cc ct cui cng. C nh th qu trnh trn c lp i lp li >
24ln/1s, n y chng ta quan st c mt hnh nh lin tc hin th trn mn hnh
Led ma trn.
4.3.2.3.V d:
Hin th ch B ln mn hnh Led ma trn (hng c tch cc mc1, ct c tch
cc mc 0).
Trang 84
GVHD:Thc s L nh Kha
Hng 1
Hng 8
Ct 8
Ct 1
Hnh 4.9: Hin th ch B trn led ma trn dng phng php qut ct.
D liu th nht c ga tr: 11111110 c a ra hng, tch cc ct th nht (iu
khin ct th nht cho ra gi tr l 0); d liu th hai c gi tr: 10010010 a ra hng,
tch cc ct th hai; d liu th 3 c gi tr: 10010010 a ra hng, tch cc ct th 3; d
liu th 4 c gi tr: 10010010 a ra hng, tch cc ct th 4; tip tc liu hng th 5
c gi tr: 01101100 a ra hng, tch cc ct th 5; k tip l d liu ca ct th 6 c
gi tr: 00000000 c a ra hng, tch cc ct th 6 ; d liu ca ct th 7 c gi tr:
00000000 a ra hng, tch cc ct th 7; d liu th 8 c gi tr: 00000000 a ra hng,
tch cc ct th 8. Nh vy ton b d liu ca ch B c a ra hin th trn mn
hnh Led ma trn. Qu trnh trn c din ra rt nhanh > 24ln/ 1s nn chng ta c cm
gic n din ra mt cch ng thi, nh chng ta quan st c trn mn hnh Led ma
trnl mt ch B lin tc.
Phng php hin th Led ma trn s dng thanh ghi dch:
u im:
Tit kim ng truyn, hiu qu kinh t.
Tit kim chn PORT.
Truyn d liu i xa hn.
M rng bng Ma trn ln mt cch d dng.
Lp trnh d dng trong phng php qut ct.
Nhc im:
Tn thi gian thc hin vic truyn d liu n cc ct.
Chuyn i khng linh hot bng s dng phng php cht.
Lp trnh kh khn hn khi s dng phng php qut hng.
Trang 85
90PC
90PD
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
4k7
9RN2
4k7
9RN
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
b8
b7
b6
b5
b4
b3
b2
b1
b16
b15
b14
b13
b12
b11
b10
b9
90PB
8
7
6
5
4
3
2
1
b9
b1
1
2
3
4
5
6
7
8
330
9RN3
c9
16
15
14
13
12
11
10
9
b10
Q9
A1015
c1
b2
Q1
A1015
h8
h7
h6
h5
h4
h3
h2
h1
c10
h8
h7
h6
h5
h4
h3
h2
h1
13
3
4
10
6
11
15
16
Q10 b11
A1015
c2
b3
Q2
A1015
MTRAN1
b5
Q4
A1015
c12
Q12 b13
A1015
c4
c1c2c3c4 c5c6c7c8
c11
Q11 b12
A1015
c3
b4
Q3
A1015
c13
Q13 b14
A1015
c5
b6
Q5
A1015
c14
Q14 b15
A1015
c6
Q6 b7
A1015
h8
h7
h6
h5
h4
h3
h2
h1
13
3
4
10
6
11
15
16
Q15 b16
A1015
c15
c7
b8
Q7
A1015
VCC
MTRAN2
c13c14c15c16
c9c10c11c12
c16
Q16
A1015
c8
Q8
A1015
5
2
7
1
12
8
14
9

5
2
7
1
12
8
14
9
VCC

GVHD:Thc s L nh Kha
4.4 Mch nguyn l:
Trang 86
GVHD:Thc s L nh Kha
CHNG V : LCD
(Liquid Crystal Display)
5.1 Gii Thiu Chung V LCD
C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn hnh 1 l
hai loi LCD thng dng.
Hnh 1 : Hnh dng ca hai loi LCD thng dng

Khi sn xut LCD, nh sn xut tch hp chp iu khin (nh HD44780) bn
trong lp v v ch a cc chn giao tip cn thit. Cc chn ny c nh s th t v
t tn nh hnh 2 :
Hnh 2 : S chn ca LCD

2> Chc nng cc chn :
Tn Chn V Chc Nng
Chn S
Tn
VSS
2
3
VDD
Vee
RS
Chc Nng
Chn ni t cho LCD.
Chn cp ngun cho LCD.
Chn ny dng iu chnh tng phn ca
LCD
Chn chn thanh ghi (Register select). Ni chn
RS vi logic 0 (GND) hoc logic 1 (VCC)
chn thanh ghi.
+ Logic 0: Bus DB0-DB7 s ni vi thanh
ghi lnh IR ca LCD ( ch ghi-write)
hoc ni vi b m a ch ca LCD ( ch
c - read).
+ Logic 1: Bus DB0-DB7 s ni vi thanh
Trang 87
GVHD:Thc s L nh Kha
ghi d liu DR bn trong LCD.

5
7-14
R/W
Chn chn ch c/ghi (Read/Write). Ni

chn R/W vi logic 0 LCD hot ng
ch ghi, hoc ni vi logic 1 LCD
ch c.
Chn cho php (Enable). Sau khi cc tn hiu

c t ln bus DB0-DB7, cc lnh ch c
chp nhn khi c 1 xung cho php ca chn E.
+ ch ghi: D liu bus s c LCD
chuyn vo (chp nhn) thanh ghi bn trong n
khi pht hin mt xung (high-to-low transition)
ca tn hiu chn E.
+ ch c: D liu s c LCD xut ra
DB0-DB7 khi pht hin cnh ln (lowto-high
transition) chn E v c LCD gi bus n
khi no chn E xung mc thp.
DB0DB7
Tm ng ca bus d liu dng trao i

thng tin vi MPU. C 2 ch s dng 8
ng bus ny :
+ Ch 8 bit : D liu c truyn trn c 8
ng, vi bit MSB l bit DB7.
+ Ch 4 bit : D liu c truyn trn 4
ng t DB4 ti DB7, bit MSB l DB7
.
Bng 1 : Chc nng cc chn ca LCD
* Ghi ch : ch c, ngha l MPU s c thng tin t LCD thng qua cc chn
DBx.Cn khi ch ghi, ngha l MPU xut thng tin iu khin cho LCD thng
qua cc chn DBx.
Trang 88
GVHD:Thc s L nh Kha
3> S
khi ca HD44780:
Hnh 3 : S khi ca HD44780
5.1.1 Cc thanh ghi :

Chp HD44780 c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor
Register) v thanh ghi d liu DR (Data Register)
- Thanh ghi IR : iu khin LCD, ngi dng phi ra lnh thng qua tm
ng bus DB0-DB7. Mi lnh c nh sn xut LCD nh a ch r rng. Ngi
dng ch vic cung cp a ch lnh bng cch np vo thanh ghi IR. Ngha l, khi ta np
vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m lnh ti a ch m IR
cung cp v thc hin lnh .
VD : Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0)
Lnh hin th mn hnh v con tr c m lnh l 00001110
- Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM
DDRAM hoc CGRAM ( ch ghi) hoc dng cha d liu t 2 vng RAM ny
gi ra cho MPU ( ch c). Ngha l, khi MPU ghi thng tin vo DR, mch ni bn
trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi thng tin
Trang 89
GVHD:Thc s L nh Kha
v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni s c chuyn ra

DR truyn cho MPU.
- Bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2 thanh
ghi ny khi giao tip vi MPU. Bng sau y tm tt li cc thit lp i vi hai chn RS
v R/W theo mc ch giao tip.
Bng 2 : Chc nng chn RS v R/W theo mc ch s dng

5.1.2 C bo bn BF: (Busy Flag)
Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong
thi gian hon tt. Khi ang thc thi cc hot ng bn trong chip nh th, LCD b
qua mi giao tip vi bn ngoi v bt c BF (thng qua chn DB7 khi c thit lp RS=0,
R/W=1) ln bo cho MPU bit n ang bn. D nhin, khi xong vic, n s t c
BF li mc 0.
5.1.3 B m a ch AC : (Address Counter)
Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM
(DDRAM v CGRAM) m thng qua b m a ch AC. B m ny li ni vi 2 vng
RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh ghi IR, thng tin
c ni trc tip cho 2 vng RAM nhng vic chn la vng RAM tng tc c
bao hm trong m lnh.
Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v
ni dung ca AC c xut ra cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v
R/W=1 (xem bng tm tt RS - R/W).
Lu : Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp
nht sau khi c BF ln mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay
mt khong tADD khong 4uS- 5uS (ngay sau khi BF=1) trc khi np d liu mi. Xem
thm hnh bn di.
Hnh 4 : Gin xung cp nht AC

5.1.4 Vng RAM hin th DDRAM : (Display Data RAM)
y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt
k t trn mn hnh v khi bn ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti
v tr tng ng trn mn hnh mt k t c m 8 bit m bn cung cp. Hnh sau y s
trnh by r hn mi lin h ny.
Trang 90
GVHD:Thc s L nh Kha
Hnh 4 : Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD

Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng
RAM cn li khng dng cho hin th c th dng nh vng RAM a mc ch.
Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX
5.1.5 Vng ROM cha k t CGROM: Character Generator ROM
Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v
nh a ch bng 8 bit. Tuy nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu
5x10 (tng cng l 240 thay v 28 = 256 mu k t). Ngi dng khng th thay i vng
ROM ny.
Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t.

Nh vy, c th ghi vo v tr th x trn mn hnh mt k t y no , ngi
dng phi ghi vo vng DDRAM ti a ch x (xem bng mi lin h gia DDRAM v v
tr hin th) mt chui m k t 8 bit trn CGROM. Ch l trong bng m k t trong
CGROM hnh bn di c m ROM A00.
Trang 91
GVHD:Thc s L nh Kha
V d : Ghi vo DDRAM ti a ch 01 mt chui 8 bit 01100010 th trn LCD ti

th 2 t tri sang (dng trn) s hin th k t b.
Bng 3 : Bng m k t (ROM code A00)

5.1.6 Vng RAM cha k t ha CGRAM : (Character Generator RAM)
Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000
ngi dng c th to cc mu k t ha ring. Tuy nhin dung lng vng ny rt
hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t loi 5x10 im nh.
ghi vo CGRAM, hy xem hnh 6 bn di.
Trang 92
GVHD:Thc s L nh Kha
Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t.

4> Tp lnh ca LCD :
Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip vi
LCD :
* Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp trnh iu
khin LCD ta ch c th tc ng trc tip c vo 2 thanh ghi DR v IR thng qua cc
chn DBx, v ta phi thit lp chn RS, R/W ph hp chuyn qua li gi 2 thanh ghi
ny. (xem bng 2)
* Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh
lu i vi tc ca MPU, nn ta cn kim tra c BF hoc i (delay) cho LCD thc
thi xong lnh hin hnh mi c th ra lnh tip theo.
* a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh ghi vo
RAM. (iu ny gip chng trnh gn hn)
* Cc lnh ca LCD c th chia thnh 4 nhm nh sau :
Cc lnh v kiu hin th. VD : Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit /
4 bit),
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GVHD:Thc s L nh Kha
Ch nh a ch RAM ni.
Nhm lnh truyn d liu trong RAM ni.
Cc lnh cn li . (!!!)
5.2 Tp lnh ca LCD
Tn lnh
Clear
Display
Return
home
Entry
mode set
Display
on/off
control
Hot ng
M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 0 0 0 0 1
Lnh Clear Display (xa hin th) s ghi mt khong trngblank (m hin k t 20H) vo tt c nh trong DDRAM,
sau tr b m AC=0, tr li kiu hin th gc nu n b
thay i. Ngha l : Tt hin th, con tr di v gc tri (hng
u tin), ch tng AC
DBx = 0 0 0 0 0 0 1 *
Lnh Return home tr b m a ch AC v 0, tr li kiu
hin th gc nu n b thay i. Ni dung ca DDRAM
khng thay i
DBx = 0 0 0 0 0 1 [I/D] [S]
I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin
th AC 1 n v mi khi c hnh ng ghi hoc c vng
DDRAM. V tr con tr cng di chuyn theo s tng gim
ny.
S : Khi S=1 ton b ni dung hin th b dch sang phi
(I/D=0) hoc sang tri (I/D=1) mi khi c hnh ng ghi
vng DDRAM. Khi S=0: khng dch ni dung hin th.
Ni dung hin th khng dch khi c DDRAM hoc c/ghi
vng CGRAM.
DBx = 0 0 0 0 1 [D] [C] [B]
D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th,
ni dung DDRAM khng thay i.
C: Hin th con tr khi C=1 v ngc li. V tr v hnh dng
con tr, xem hnh 8
B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li.
Xem thm hnh 8 v kiu nhp nhy. Chu k nhp nhy
khong 409,6ms khi mch dao ng ni LCD l 250kHz.
Trang 94
GVHD:Thc s L nh Kha
Hnh 8: Kiu con tr, kiu k t v nhp nhy k t

Cursor
or
display
shift
Function
set
DBx = 0 0 0 1 [S/C] [R/L] * *
Lnh Cursor or display shift dch chuyn con tr hay d liu
hin th sang tri m khng cn hnh ng ghi/c d liu.
Khi hin th kiu 2 dng, con tr s nhy xung dng di
khi dch qua v tr th 40 ca hng u tin. D liu hng u
v hng 2 dch cng mt lc. Chi tit s dng xem bng bn
di:
S/C R/L Hot ng :
Bng 5: Hot ng lnh Cursor or display shift

DBx = 0 0 1 [DL] [N] [F] * *
DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit
(t bit DB7 n DB0).
Ngc li, giao thc giao tip l 4 bit (t bit DB7 n bit
DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2
ln lin tip. vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn
sau.
N : Thit lp s hng hin th. Khi N=0 : hin th 1 hng,
N=1: hin th 2 hng.
F : Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh,
F=1: kiu k t 5x10 im nh.
.
* Ch :
Ch thc hin thay i Function set u chng trnh.
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GVHD:Thc s L nh Kha
V sau khi c thc thi 1 ln, lnh thay i Function set

khng c LCD chp nhn na ngoi tr thit lp
chuyn i giao thc giao tip.
Khng th hin th kiu k t 5x10 im nh kiu hin
th 2 hng
Set
CGRAM
address
DBx = 0 1 [ACG][ACG][ACG][ACG][ACG][ACG]
Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG]
ch 1 bit ca chui d liu 6 bit. Ngay sau lnh ny l lnh
c/ghi d liu t CGRAM ti a ch c ch nh.
.
Set
DDRAM
address
DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD]
Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn
thit lp ta hin th mong mun. Ngay sau lnh ny l
lnh c/ghi d liu t DDRAM ti a ch c ch nh.
Khi ch hin th 1 hng, a ch c th t 00H n 4FH.
Khi ch hin th 2 hng, a ch t 00h n 27H cho
hng th nht, v t 40h n 67h cho hng th 2.
Read BF
and
address
DBx = [BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC] (RS=0,
R/W=1)
Nh cp trc y, khi c BF bt, LCD ang lm vic
v lnh tip theo (nu c) s b b qua nu c BF cha v
mc thp. Cho nn, khi lp trnh iu khin, bn phi kim
tra c BF trc khi ghi d liu vo LCD.
Khi c c BF, gi tr ca AC cng c xut ra cc bit
[AC]. N l a ch ca CG hay DDRAM l ty thuc vo
lnh trc
Write
data to
CG or
DDRAM
DBx = [Write data] (RS=1, R/W=0)
Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo
cc chn DBx t mch ngoi s c LCD chuyn vo trong
LCD ti a ch c xc nh t lnh ghi a ch trc
(lnh ghi a ch cng xc nh lun vng RAM cn ghi).
Sau khi ghi, b m a ch AC t ng tng/gim 1 ty theo
thit lp Entry mode.Lu l thi gian cp nht AC khng
tnh vo thi gian thc thi lnh.
DBx = [Read data] (RS=1, R/W=1)
Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c
chuyn ra MPU thng qua cc chn DBx (a ch v vng
RAM c xc nh bng lnh ghi a ch trc ).
Read
data
from CG
or
DDRAM
Trang 96
GVHD:Thc s L nh Kha
Sau khi c, AC t ng tng/gim 1 ty theo thit lp Entry

mode, tuy nhin ni dung hin th khng b dch bt chp ch
Entry mode.
5> Giao tip gia LCD v MPU :
c tnh in ca cc chn giao tip :
LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong c
tnh in sau y:
Bng 6 : Maximun Rating

c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V n
5.5V, T = -30 n +75C)
5.3 Khi to LCD6> Khi to LCD:
Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to
gip ta thit lp cc giao thc lm vic gia LCD v MPU. Vic khi to ch c thc
hin 1 ln duy nht u chng trnh iu khin LCD v bao gm cc thit lp sau :
Display clear : Xa/khng xa ton b ni dung hin th trc .
Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t
5x8/5x10.
Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng
nhp nhy.
Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim
(Increment).
5.3.1 Mch khi to bn trong chp HD44780:
Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n.
V trong thi gian khi to ny c BF bt ln 1, n khi vic khi to hon tt c BF cn
gi trong khong 10ms sau khi Vcc t n 4.5V (v 2.7V th LCD hot ng). Mch
khi to ni s thit lp cc thng s lm vic ca LCD nh sau:
Display clear : Xa ton b ni dung hin th trc .
Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8
Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off.
Entry mode set: I/D =1 : Tng; S=0 : Khng dch.
Nh vy sau khi m ngun, bn s thy mn hnh LCD ging nh cha m ngun do
ton b hin th tt. Do , ta phi khi to LCD bng lnh.
5.3.2 Khi to bng lnh: (chui lnh)
Vic khi to bng lnh phi tun theo lu sau ca nh sn xut
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GVHD:Thc s L nh Kha
Trang 98
GVHD:Thc s L nh Kha
Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc

mi bt in ln). V khi kt ni mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng
c kt ni n LCD, nn lnh khi to ban u (lnh chn giao thc giao tip
function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua
4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble.
Lu l sau khi thit lp function set, bn khng th thay i function set ngoi tr
thay i giao thc giao tip (4bit/8bit).
5.4 Lu gii thut:
Bt u
Init LCD
Gi Data
Hin th
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GVHD:Thc s L nh Kha
5.5 Mch nguyn l:
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
D0
D1
D2
D3
D4
D5
D6
D7
VDD
CON8
V0
RS
R/W
E
4
5
6
A
K
15
16
3VR
10K
LCD
J3
VCC
LCD
VSS
5
4
3
2
1
J4
CON5
Trang 100
GVHD:Thc s L nh Kha
CHNG VI : ADC
6.1 Gii thiu v module ADC.
6.1.1 C bn v ADC.
Trong cuc sng ca chng ta, nhng tn hiu m chng ta thng tip cn l tn
hiu tng t , v d nh ting ni, sng in thoi, vv... Nu chng ta x l trc tip tn
hiu tng t ny th rt kh, v vy cn thit phi chuyn i chng sang dng s.
Bin i tng t s (analog digital) l thnh phn cn thit trong vic x l
thng tin v cc cch iu khin s dng phng php s. Tn hiu thc Analog. Mt
h thng tip nhn d liu phi c cc b phn giao tip Analog Digital (A/D).
Cc b chuyn i tng t s, vit tt l ADC thc hin hai chc nng c bn l
lng t ha v m ha. Lng t ha l gn cho nhng m nh phn cho tng gi tr ri
rc sinh ra trong qu trnh lng t ha
Bin i AD c tnh cht t l. Tn hiu vo Analog c bin i thnh mt phn
s X bng cch so snh vi tn hiu tham chiu Vref. u ra ca b ADC l m ca phn
s ny. Bt k mt sai s tn hiu Vref no cng s dn n sai s mc ra, v vy ngi
ta c gn gi cho Vref cng n nh cng tt.
Vref
ADOUTPUT_a(0
B111110);C
Vin
Digital output
Hnh 2.1 Quan h vo ra cc khi ADC

Nu b ADC xut m ra gm n bit th s mc ra ri rc l 2n. i vi quan h tuyn
tnh, tn vo c lng t ha theo ng mc ny. Mi mc nh vy l mt tn hiu
Analog c phn bit vi hai m k tip nhau, n chnh l kch thc ca LSB (Least
Significant Bit).
Q=LSB=
FS
2n
Trong :
Q
: Lng t
LSB : Bit c trng s thp nht
FS : Gi tr ton thang
Tt c cc gi tr Analog ca lng t Q c biu din bi m s, m m ny
tng ng vi gi tr trung bnh ca lng t (c th hiu l gia khong LSB) gi l
mc ngng. Cc gi tr Analog nm trong khong t mc ngng sai bit i LSB
vn c th hin bng cng mt m, l sai s lng t ha. Sai s ny c th s gim
i bng cch tng s bit trong m ra b ADC.
Sau y ti s trnh by nguyn tc chuyn i:
- Bc 1 : Ly mu t hiu n tng t ( tc l ri rc ha tn hiu tng t ) c th l
iu ch bin pha (PWM)
Trang 101
GVHD:Thc s L nh Kha
Tn s ly mu cng cao th chnh xc ca ri rc ha l cng cao v ngc li,

nu tn s ly mu cng ln th cn lng d liu ln do cn b nh ln v khi x
l s rt phc tp.
Tn s ly mu >= 2 ln tn s cao nht ca tn hiu ( trnh hin tng gp ph )
- Bc 2 : Lng t ha cc xung c ly mu .( m ha ) tc l iu ch xung
PCM. Lng t ha y c ngha l dng mt thc o vi k bc nh phn ( tc l 2^k
khong bng nhau ) o cc xung c ly mu v d
T ta c cc s tng ng vi xung v n c th hin qua cc s nh phn v

d vi k = 8 ( tc l biu din s ny da vo 8bit ) ta mun biu din s 9 s nh phn
tng ng l: 0 0 0 0 1 0 0 1 trong bt u tin l MSB lm du
My tnh s thu nhn gi tr ny ri thc hin vic lu tr , x l.
6.1.2 ADC trong PIC 16F877A
Trn VK c mt b bin i ADC 10bit, 8 ng vo Analog, 8 ng vo ny c
ni vi ng vo ca b chuyn i. Sau b chuyn i s to ra mt kt qu 10 bit
tng ng vi gi tr Ananlog u vo. in th tham chiu u vo s c la chn
Trang 102
GVHD:Thc s L nh Kha
bng phn mm (t Vdd, Vss hoc 2 chn AN2, AN3. Module ADC l module duy nht
c kh nng hot ng trong ch ng. hot ng trong ch ng Sleep, xung
clock cung cp cho ADC phi c nhn t dao ng ni RC ca ADC.
Mt b ADC c bn gm c:
Ng vo VIN.
in p chun VREF.
Cc bit ng ra.
Quan h cc i lng ny c th m t nh sau:
N=(VIN / VREF).NMax
Vi:
N : Chuyn i thp phn ca cc bit ng ra
NMax :Gi tr thp phn ln nht ti ng ra .
Nmax ph thuc vo s lng bit ti ng ra ca ADC
V d :s dng ADC 8 bit th gi tr Nmax =28 1 =255
Khi : N=(VIN / VREF).255
6.2 S nguyn l:
L0
VCC
2
L1
1R46
10K
1R47
1DX
1C7
1RS 104
VR 10K
1C8
1C9
33p
33p
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MCLR/VPP
RB7/PGD
RA0/AN0
RB6/PGC
RA1/AN1
RB5
RA2/AN2/VRef -/CVRef RB4
RA3/AN3/VRef + RB3/PGM
RA4/T0CKI/C1OUT
RB2
RA5/AN4/SS/C2OUT
RB1
RB0/INT
RE0/RD/AN5
VDD
RE1/WR/AN6
GND
RE2/CSAN7
VDD
RD7/PSP7
GND
RD6/PSP6
OSC1/CLKI
RD5/PSP5
RD4/PSP4
OSC2/CLKO
RC0/T1OSO/T1CKI RC7/RX/DT
RC1/T1OSI/CCP2 RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL RC4/SDI/SDA
RD0/PSP0
RD3/PSP3
RD1/PSP1
RD2/PSP2
VCC
L2
1U1
VCC 100
1Y1
40
39
38
37
36
35
34
33
32
31 VCC
30
29
28
27
26
25
24
23
22
21
4R2
2
L3
L4
1
L5
1
2
L6
9
8
7
6
5
4
3
2
330
1
L7
2
PIC16F877A
Vi Vcc = 5V.Bin tr VR=10k
Trang 103
GVHD:Thc s L nh Kha
CHNG VII : BN PHM GIAO TIP LCD

7.1 Keypad V Nguyn L Hot ng
Mt bn phm s Hex c thnh lp t 16 nt nhn n. Cc nt nhn ny c
ni vo vi iu khin. Khi thc hin kim tra phm nhn, vn cn thit l phi thc
hin chng rung phm v chng nhiu. Qu trnh chng rung phm v chng nhiu c th
thc hin bng phn mm: Do thi gian rung phm vo khong 20ms nn qu trnh
chng rung bng phn mm n gin l to mt thi gian ch ln chng trnh b
qua nh hng khi rung phm v chng nhiu.
5V
R4
10k
J1
8
7
6
5
4
3
2
1
R3
10k
R2
10k
R1
10k
PORT B
pht hin phm nhn ta s dng phng php qut hng. Khi khng nhn phm
th hng ca bn phm Hex ni vi Vcc thng qua in tr R nn c mc logic 1.
phn bit c trng thi ca phm nhn th mc logic khi nhn phm phi l mc logic 0.
M khi nhn mt phm no th tng ng hng v ct ca bn phm Hex s kt ni
vi nhau. Do , thc hin kim tra mt phm th ta phi cho trc ct cha phm
tng ng mc logic 0, sau kim tra hng ca phm, nu hng = 0 th c nhn phm
cn hng = 1 th khng nhn phm.
V d nh mun kim tra phm 4 th ta cho ct cha phm 4 mc logic 0(chn 4
ca J1, cc ct khc = 1), sau thc hin kim tra chn 7 ca J1 (hng ca phm 4), nu
chn ny = 0 th phm 4 c nhn.
7.2 Keypad v giao tip vi LCD.
Trong mch di LCD c ni vi Port B cn bn phm ni vi Port D.
Chng trnh ch n gin l ch xem c phm no nhn th hin th phm ln mn
hnh LCD.
Trang 104
1C7
1C9
33p
1C8
33p
VCC
100
1R47
1R46
10K
1Y 1
1RS 104
1DX
VCC
10
9
8
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
23
24

PIC16F877A
R6
R
R5
R
R4
R
RE2/CSAN7
RB7/PGD
RE1/WR/AN6
RB6/PGC
RE0/RD/AN5
RB5
RB4
MCLR/VPP
RB3/PGM
RA0/AN0
RB2
RA1/AN1
RB1
RA2/AN2/VRef -/CVRef
RB0/INT
RA3/AN3/VRef +
VDD
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
GND
RD7/PSP7
VDD
RD6/PSP6
GND
RD5/PSP5
OSC1/CLKI
RD4/PSP4
OSC2/CLKO
RC0/T1OSO/T1CKI RD3/PSP3
RC1/T1OSI/CCP2 RD2/PSP2
RD1/PSP1
RC2/CCP1
RD0/PSP0
RC3/SCK/SCL
RC4/SDI/SDA
RC7/RX/DT
RC5/SDO
RC6/TX/CK
1U1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
22
21
20
19
26
25
R6
R
VCC
SW6
SW10
SW14
SW9
SW13
SW8
SW12
SW2
SW5
SW1
lcd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U1
SW4
SW1
VCC
10k
R7
VCC
SW15
SW11
SW7
SW3

GVHD:Thc s L nh Kha
Trang 105
GVHD:Thc s L nh Kha
7.3 S Gii Thut
Bt u
Init LCD
Qut phm
C
phm
nhn
Hin th
Trang 106
GVHD:Thc s L nh Kha
CHNG VIII : GIAO TIP I2C

(GIAO TIP EEPROM 24C04)
8.1 Gii Thiu Chung V I2C:
Ngy nay trong cc h thng in t hin i, rt nhiu ICs hay thit b ngoi vi cn
phi giao tip vi cc ICs hay thit b khc giao tip vi th gii bn ngoi. Vi mc
tiu t c hiu qu cho phn cng tt nht vi mch in n gin, Phillips pht
trin mt chun giao tip ni tip 2 dy c gi l I2C. I2C l tn vit tt ca cm t
Inter Intergrated Circuit Bus giao tip gia cc IC vi nhau.
I2C mc d c pht trin bi Philips, nhng n c rt nhiu nh sn xut IC
trn th gii s dng. I2C tr thnh mt chun cng nghip cho cc giao tip iu khin,
c th k ra y mt vi tn tui ngoi Philips nh: Texas Intrument (TI), Maxim-Dallas,
analog Device, National Semiconductor Bus I2C c s dng lm bus giao tip
ngoi vi cho rt nhiu loi IC khc nhau nh cc loi Vi iu khin 8051, PIC, AVR,
ARM, chip nh nh RAM tnh (Static Ram), EEPROM, b chuyn i tng t sang s
(ADC), s sang tng t(DAC), IC iu khin LCD, LED
8.1.1 c im giao tip I2C

Mt giao tip I2C gm c 2 dy: Serial Data (SDA) v Serial Clock (SCL). SDA
l ng truyn d liu 2 hng, cn SCL l ng truyn xung ng h v ch theo mt
hng.
Nh hnh v trn, khi mt thit b ngoi vi kt ni vo ng I2C th chn SDA ca
n s ni vi dy SDA ca bus, chn SCL s ni vi dy SCL.
Hnh 1.2. Kt ni thit b vo bus I2C ch chun (Standard mode)

v ch nhanh (Fast mode)
Trang 107
GVHD:Thc s L nh Kha
Mi dy SDA hay SCL u c ni vi in p dng ca ngun cp thng qua

mt in tr ko ln (pull-up resistor). S cn thit ca cc in tr ko ny l v chn
giao tip I2C ca cc thit b ngoi vi thng l dng cc mng h (open-drain or opencollector).
Gi tr ca cc in tr ny khc nhau ty vo tng thit b v chun giao tip,
thng dao ng trong khong 1K n 4.7K.
Tr li vi hnh mc 8.1, ta thy c rt nhiu thit b (ICs) cng c kt ni vo
mt bus I2C, tuy nhin s khng xy ra chuyn nhm ln gia cc thit b, bi mi thit
b s c nhn ra bi mt a ch duy nht vi mt quan h ch/t tn ti trong sut thi
gian kt ni. Mi thit b c th hot ng nh l thit b nhn d liu hay c th va
truyn va nhn. Hot ng truyn hay nhn cn ty thuc vo vic thit b l ch
(master) hay t (slave).
Mt thit b hay mt IC khi kt ni vi bus I2C, ngoi mt a ch (duy nht)
phn bit, n cn c cu hnh l thit b ch (master) hay t (slave). Ti sao li c s
phn bit ny ? l v trn mt bus I2C th quyn iu khin thuc v thit b ch
(master). Thit b ch nm vai tr to xung ng h cho ton h thng, khi gia hai thit
b ch/t giao tip th thit b ch c nhim v to xung ng h v qun l a ch ca
thit b t trong sut qu trnh giao tip. Thit b ch gi vai tr ch ng, cn thit b t
gi vai tr b ng trong vic giao tip.
Master truyn d liu
Master nhn d liu

Nhn hnh trn ta thy xung ng h ch c mt hng t ch n t, cn lung d
liu c th i theo hai hng, t ch n t hay ngc li t n ch.
V d liu truyn trn bus I2C, mt bus I2C chun truyn 8bit d liu c hng
trn ng truyn vi tc l 100Kbits/s Ch chun (Standard mode). Tc
truyn c th ln ti 400Kbits/s Ch nhanh (Fast mode) v cao nht l 3,4Mbits/s
Ch cao tc (Highspeed mode).
Mt bus I2C c th hot ng nhiu ch khc nhau:
9 Mt ch mt t (one master one slave).
9 Mt ch nhiu t (one master multi slave).
9 Nhiu ch nhiu t (Multi master multi slave).
D ch no, mt giao tip I2C iu da vo quan h ch/t. Gi thit mt thit b A.
mun gi d liu n thit b B, qu trnh c thc hin nh sau:
9 Thit b A (Ch) xc nh ng a ch ca thit b B (t), cng vi vic xc nh
a ch, thit b A s quyt nh vic c hay ghi vo thit b t.
9 Thit b A gi d liu ti thit b B.
9 Thit b A kt thc qu trnh truyn d liu.
Khi A mun nhn d liu t B, qu trnh din ra nh trn, ch khc l A s nhn d
liu t B. Trong giao tip ny, A l ch cn B vn l t. Chi tit vic thit lp mt giao
tip gia hai thit b s c m t chi tit trong cc mc di y.
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GVHD:Thc s L nh Kha
8.1.2 START and STOP conditions

START v STOP l nhng iu kin bt buc phi c khi mt thit b ch mun
thit lp giao tip vi mt thit b no trong mng I2C. START l iu kin khi u,
bo hiu bt u ca giao tip, cn STOP bo hiu kt thc mt giao tip. Hnh di y
m t iu kin START v STOP.
Ban u khi cha thc hin qu trnh giao tip, c hai ng SDA v SCL u
mc cao (SDA = SCL = HIGH). Lc ny bus I2C c coi l ri (bus free), sn sng
cho mt giao tip. Hai iu kin START v STOP l khng th thiu trong vic giao tip
gia cc thit b I2C vi nhau.
Hnh 1.4. iu kin START v STOP ca bus I2C

iu kin START: mt s chuyn i trng thi t cao xung thp trn ng SDA
trong khi ng SCL ang mc cao (cao = 1; thp = 0) bo hiu mt iu kin START.
iu kin STOP: Mt s chuyn i trng thi t mc thp ln cao trn ng SDA
trong khi ng SCL ang mc cao.
C hai iu kin START v STOP u c to ra bi thit b ch. Sau tn hiu START,
bus I2C coi nh ang trong trang thi lm vic (busy). Bus I2C s ri, sn sng cho mt
giao tip mi sau tn hiu STOP t pha thit b ch.
Sau khi c mt iu kin START, trong qua trnh giao tip, khi c mt tn hiu
START c lp li thay v mt tn hiu STOP th bus I2C vn tip tc trong trng thi
bn. Tn hiu START v lp li START u c chc nng ging nhau l khi to mt
giao tip.
8.1.3 nh dng d liu truyn
D liu c truyn trn bus I2C theo tng bit, bit d liu c truyn i ti mi
sn dng ca xung ng h trn dy SCL, qu trnh thay i bit d liu xy ra khi
SCL ang mc thp.
Hnh 1.5. Qu trnh truyn 1 bit d liu

Mi byte d liu c truyn c di l 8 bits. S lng byte c th truyn trong
mt ln l khng hn ch. Mi byte c truyn i theo sau l mt bit ACK bo hiu
nhn d liu. Bit c trng s cao nht (MSB) s c truyn i u tin, cc bt s
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GVHD:Thc s L nh Kha
c truyn i ln lt. Sau 8 xung clock trn dy SCL, 8 bit d liu c truyn i.
Lc ny thit b nhn, sau khi nhn 8 bt d liu s ko SDA xung mc thp to
mt xung ACK ng vi xung clock th 9 trn dy SDA bo hiu nhn 8 bit.
Thit b truyn khi nhn c bit ACK s tip tc thc hin qu trnh truyn hoc kt
thc.
Hnh 1.6. D liu truyn trn bus I2C
Hnh 1.7. Bit ACK trn bus I2C
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GVHD:Thc s L nh Kha
Mt byte truyn i c km theo bit ACK l iu kin bt buc, nhm m bo cho

qu trnh truyn nhn c din ra chnh xc. Khi khng nhn c ng a ch hay khi
mun kt thc qu trnh giao tip, thit b nhn s gi mt xung Not-ACK (SDA mc
cao) bo cho thit b ch bit, thit b ch s to xung STOP kt thc hay lp li
mt xung START bt u qu trnh mi.
8.1.4 nh dng a ch thit b
Mi thit b ngoi vi tham gia vo bus I2C u c mt a ch duy nht, nhm phn
bit gia cc thit b vi nhau. di a ch l 7 bit, iu c ngha l trn mt bus
I2C ta c th phn bit ti a 128 thit b. Khi thit b ch mun giao tip vi ngoi vi
no trn bus I2C, n s gi 7 bit a ch ca thit b ra bus ngay sau xung START.
Byte u tin c gi s bao gm 7 bit a ch v mt bt th 8 iu khin hng truyn.
Hnh 1.8. Cu trc byte d liu u tin

Mi mt thit b ngoi vi s c mt a ch ring do nh sn xut ra n quy nh.
a ch c th l c nh hay thay i. Ring bit iu khin hng s quy nh chiu
truyn d liu. Nu bit ny bng 0 c ngha l byte d liu tip theo sau s c truyn
t ch n t, cn ngc li nu bng 1 th cc byte theo sau byte u tin s l d liu
t con t gi n con ch. Vic thit lp gi tr cho bit ny do con ch thi hnh, con t s
ty theo gi tr m c s phn hi tng ng n con ch.
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GVHD:Thc s L nh Kha
8.1.5 Truyn d liu trn bus I2C, ch Master - Slave

Vic truyn d liu din ra gia con ch v con t. D liu truyn c th theo 2
hng, t ch n t hay ngc li. Hng truyn c quy nh bi bit th 8 (R\W)
trong byte u tin c truyn i.
Truyn d liu t ch n t (ghi d liu): Thit b ch khi mun ghi d liu n

con t, qu trnh thc hin l:
9 Thit b ch to xung START
9 Thit b ch gi a ch ca thit b t m n cn giao tip cng vi bit RW = 0 ra
bus v i xung ACK phn hi t con t.
9 Khi nhn c xung ACK bo nhn din ng thit b t, con ch bt u gi
d liu n con t theo tng byte mt. Theo sau mi byte ny u l mt xung
ACK. S lng byte truyn l khng hn ch.
9 Kt thc qu trnh truyn, con ch sau khi truyn byte cui s to xung STOP bo
hiu kt thc
Truyn d liu t t n ch (c d liu): Thit b ch mun c d liu t thit

b t, qu trnh thc hin nh sau:
9 Khi bus ri, thit b ch to xung START, bo hiu bt u giao tip.
9 Thit b ch gi a ch ca thit b t cn giao tip cng vi bit RW = 1 v i
xung ACK t pha thit b t
9 Sau xung ACK du tin, thit b t s gi tng byte ra bus, thit b ch s nhn d
liu v tr v xung ACK. S lng byte khng hn ch.
9 Khi mun kt thc qu trnh giao tip, thit b ch gi xung Not-ACK v to xung
STOP kt thc.
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GVHD:Thc s L nh Kha
Qu trnh kt hp ghi v c d liu: gia hai xung START v STOP, thit b ch

c th thc hin vic c hay ghi nhiu ln, vi mt hay nhiu thit b. thc hin vic
, sau mt qu trnh ghi hay c, thit b ch lp li mt xung START v li gi li a
ch ca thit b t v bt u mt qu trnh mi.
Ch giao tip Master-Slave l ch c bn trong mt bus I2C, ton b bus

c qun l bi mt master duy nht. Trong ch ny s khng xy ra tnh trng xung
t bus hay mt ng b xung clock v ch c mt master duy nht c th to xung clock.
8.1.6 Ch Multi-Master
Trn bus I2C c th c nhiu hn mt master iu khin bus. Khi bus I2C s
hot ng ch Multi-Master.
8.2 Module I2C Trong Vi iu Khin PIC
Vi nhng tin ch em li, khi giao tip I2C c tch hp cng trong kh
nhiu loi Vi iu khin khc nhau. Trong cc loi Vi iu khin PIC dng Mid-range
ph bin ti Vit Nam, ch t 16F88 mi c h tr phn cng I2C, cn cc loi 16F84,
16F628 th khng c. Vi nhng loi Vi iu khin khng c h tr phn cng giao tip
I2C, s dng ta c th dng phn mm lp trnh, khi ta s vit mt chng trinh
iu khin 2 chn bt k ca Vi iu khin n thc hin giao tip I2C (cc hm
START, STOP, WRITE, READ). Trong bi vit ny ta cp n vic s dng giao tip
I2C ca cc loi PIC c tch hp khi I2C sn trong n, m c th l Vi iu khin
PIC16F877A.
8.2.1 c im phn cng ca PIC16F877A
Hnh di y ch ra cu trc phn cng ca khi iu khin giao tip ni tip ng
b (MSSP) hot ng ch I2C. Khi I2C c y chc nng, hot ng c 2 ch
l MASTER (ch) v SLAVE (t), c ngt xy ra khi c iu kin START hay STOP
xy ra, nhm nh r ng I2C c ri hay khng ( chc nng Multi-master ). Ch a
ch c th l 7 bit hay 10 bit.
Khi I2C c 6 thanh ghi iu khin hot ng, l:
9 SSPCON: Thanh ghi iu khin.
9 SSPCON2: Thanh ghi iu khin th 2.
9 SSPSTAT: Thanh ghi trng thi.
9 SSPBUF: Thanh ghi b m truyn nhn.
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GVHD:Thc s L nh Kha
9 SSPSR: Thanh ghi dch.

9 SSPADD: Thanh ghi a ch.
Cc thanh ghi SSPCON, SSPBUF, SSPADD v SSPSON2 c th truy cp c/ghi
c.Thanh ghi SSPSR khng th truy cp trc tip, l thanh ghi dich d liu ra hay vo.
Cc thanh ghi SSPCON, SSPCON2 v SSPSTAT c nh a ch bit, mi bit c chc
nng ring. ngha ca tng thanh ghi v ca mi bit trong tng thanh ghi c
cp k trong ti liu Datasheet ca PIC
Hnh2.1. Cu trc khi I2C trong PIC

8.2.2 Cch thc s dng Module I2C trong CCS
Trong vic lp trnh cho PIC s dng giao tip I2C ca n trong cc ng dng,
ngi lp trnh c th thc hin mt cch d dng vi trnh dch CCS. Ni d dng y
l ch v mt c php lnh, ta khng cn s dng nhiu cu lnh kh nh nh trong lp
trnh ASM.
Vic khi to, chn ch hot ng v thc hin giao tip ca I2C c cc hm
dng sn ca CCS thc hin. Cc hm lit k di y l ca phin bn CCS 3.242,
l:
9 I2C_isr_state(): Thng bo trng thi giao tip I2C
9 I2C_start(): To iu kin START
9 I2C_stop(): To iu kin STOP
9 I2C_read(): c gi tr t thit b I2C, tr v gi tr 8 bit
9 I2C_write(): Ghi gi tr 8 bit n thit b I2C
s dng khi I2C ta s dng khai bo sau:
#use i2c(ch_, tc , sda = PIN_C4, scl=PIN_C3)
9 Ch : Master hay Slave
Trang 114
GVHD:Thc s L nh Kha
9 Tc : Slow (100KHz) hay Fast (400KHz)

9 SDA v SCL l cc chn I2C tng ng ca PIC
Sau khai bo trn, ta c th s dng cc hm nu trn thc hin, x l cc giao tip
I2C vi cc thit b ngoi vi khc.
8.2.3 EEPROM 24C04
24C04 l loi EEROM 4k, gm 2 block 256 x 8 bit. B nh tng thch vi chun
I2C vi 2 dy SDA v SDL. B nh xut ra 4 bit v mt thit b duy nht c nhn ra
v p ng li trn bus I2C.
8.2.3.1 Hnh Dng
8.2.3.2 S cu to:
8.2.3.3 S Chn
Trang 115
GVHD:Thc s L nh Kha
SCL (Serial clock) : ng vo ng b d liu ra vo ca b nh.

SDA(Serial Data Address Input/Output): chn ny dng bin i d liu v
truyn ra hay nhn vo b nh.
E1 E2 ( chip Enable): l ng vo chn chip v phi s dng t nht 2 bt quan
trng b2,b3 ca 7 bt chn thit b.ng vo ny c iu khin t ng v c ni vi
Vcc hay Vss thnh lp m chn thit b( Device select Code)
PRE(Protect Enable): dng b xung tnh trng ca bit Block Address Pointer
MODE: ng vo ny trn chn 7 ca 24c04 v c th c iu khin t ng. N
phi c chn l VIH hay VIL cho ch ghi cc Byte.
VIH ( Multibyte Write mode ): c th bt u trn bt c a ch no trn b nh.
Master s gi t 1 n 4 byte d liu km theo ACK bo nhn. v qu trnh truyn ch
kt thc khi c iu kin kt thc pht ra t Master.
VIL ( Page Write mode ): cho php ghi 8 bit trong 1 chu k. Do 5 bit a ch quan
trng ca b nh ( A3 n A7) l ging nhau trong 1 block. V vy Master s gi t 1
n 8 byte d liu vi bit ACK bo nhn sau mi byte c truyn. V a ch Byte bn
trong Couter s tng trong mi byte c truyn.
Khi khng kt ni mc nh l VIH .
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GVHD:Thc s L nh Kha
WC (Write Control): tn hiu ny dng cho php ( WC = VIH) hay khng

cho php ( WC = VIL) bo v b nh ngoi.
Khi khng kt ni WC =VIL v b nh khng c bo v.
8.3 Mch Nguyn L
VCC
U1402
1
2
3
4
7
A0
A1
A2
GND
WP
VCC
2k2
2K2
SCL
SDA
2
1
24C04A
DOMINO1401
Trang 117
GVHD:Thc s L nh Kha
CHNG IX :O NHIT DNG LM35

9.1 Gii thiu:
o nhit l mt phng thc o lng khng in, o nhit c chia thnh
nhiu di:
- o nhit thp
- o nhit trung bnh
- o nhit cao
Vic o nhit c tin hnh nh cc dng c h tr chuyn bit nh:
- Cp nhit in
- Nhit in k kim loi
- Nhit in tr kim loi
- Nhit in tr bn dn
- Cm bin thch anh
Vic s dng cc IC cm bin nhit l mt phng php thng dng c nhm
s dng trong n tt nghip ny, nn y ch gii thiu v IC cm bin nhit.
o nhit c chnh xc, tt nhin cn c mt u d nhit thch hp. u
d l mt cm bin nhit c nhim v chuyn i t nhit qua tn hiu in, da
vo l thuyt v thc t ca mch cn thit k ta dng phng php o bng IC cm bin
nhit . Cc IC cm bin nhit c chnh xc cao, d tm v gi thnh r. Mt
trong s l IC LM35DZ, l loi thng dng trn th trng hin nay, ng thi n c
nhng c tnh lm vic ph hp vi thit k chi tit ca mch.
9.2 Mt s tnh cht c bn ca LM35:
- LM35 c bin thin theo nhit : 10mV / 1oC.
- chnh xc cao, tnh nng cm bin nhit rt nhy, nhit 25oC n c sai
s khng qu 1% . Vi tm o c t -55oC - 150oC, tn hiu ng ra tuyn tnh lin tc
vi nhng thay i ca tn hiu ng vo.
- Thng s k thut:
Tiu tn cng sut thp.
Dng lm vic t 400uA 5mA
Dng ngc 15mA
Dng thun 10mA
chnh xc: khi lm vic nhit 25oC vi dng lm vic 1mA th in p ng
ra t 2.94V-3.04V.
- c tnh in:
Theo thng s ca nh sn xut LM35, quan h gia nhit v in p ng ra
nh sau:
Vout = 0,01ToK = 2,73 + 0,01ToC
Vy ng vi tm hot ng t 0oC 100oC ta c s bin thin in p ng ra l:
0oC th in p ng ra Vout = 2,73 (V).
5oC th in p ng ra Vout = 2, 78 (V).
..
100oC th in p ng ra Vout = 3,73 (V).
Trang 118
GVHD:Thc s L nh Kha
9.3 Mch Nguyn L
Trang 119
GVHD:Thc s L nh Kha
PHN III
CC BI TP THC HNH
BI 1 : HIN TH TRNG THI PORT TRN LED N.
BI 2 : HIN TH TRNG THI PORT TRN LED
V THAY I THI GIAN DELAY
BI 3 : HIN TH NGY THNG NM SINH TRN LED 7
BI 4 : HIN TH NG H TRN LED 7
BI 5 : CHNG TRNH N GIAO THNG
BI 6 : CHY CH TRN LED MA TRN
BI 7 : HIN TH K T TRN LCD
BI 8 : GIAO TIP BN PHM S HEX HIN TH LCD
BI 9 : IU CHNH ADC HIN TH LED N
BI 10: O NHIT DNG LM35
Trang 120
GVHD:Thc s L nh Kha
BI 1 : HIN TH TRNG THI PORT TRN LED N

Ngy Thng.Nm 2008
Thi Gian Thc Hin : 3 Gi
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
Thc hnh lp trnh ng dng trn my tnh, bin dch chng trnh, np vo
VK v s dng m hnh th nghim kim chng.
iu khin thit b ngoi vi bng cc Port ca VK.
iu khin vic hin th bng cch s dng LED n.
Vit cc chng trnh con to thi gian tr s dng trong cc ng dng VK.
YU CU:
Nm vng cc tp lnh ca VK PIC16F877A.
Bit cch vit cc chng trnh iu khin LED n cc ch khc nhau.
Nm c s v nguyn l hot ng ca khi LED n trn m hnh th
nghim.
Nm c nguyn l iu khin LED n cc ch khc nhau.
Bit cch vit cc chng trnh to thi gian tr vi cc khon thi gian bt k.
TRNH T TIN HNH TH NGHIM:
Tt ngun cp cho m hnh th nghim.
Dng dy bus 8 ni PortB vi LED n.
NG DNG:
Vit chng trnh cho LED chp tt theo nhiu dng khc nhau.
Trang 121
GVHD:Thc s L nh Kha
S MCH :
VCC
4R2
1
L5
L6
L7
L4
L3
1
L2
1
L1
8
7
6
5
4
3
2
1
L0
9
8
7
6
5
4
3
2
330
LEDDON
Trang 122
GVHD:Thc s L nh Kha

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin vic hin th bng cch s dng LED n.
Vit cc chng trnh con to thi gian tr s dng trong cc ng dng VK.
YU CU:
Bit cch vit cc chng trnh iu khin LED n cc ch khc nhau.
Nm c s v nguyn l hot ng ca khi LED n trn m hnh th
nghim.
Nm c nguyn l iu khin LED n cc ch khc nhau.
Bit cch vit cc chng trnh to thi gian tr vi cc khon thi gian bt k.
NG DNG:
Vit chng trnh cho LED chp tt theo nhiu dng khc nhau v thay i thi
gian delay sau mi ln xut.
Trang 123
GVHD:Thc s L nh Kha
S MCH:
VCC
4R2
L6
L7
L5
L4
L3
L2
L1
8
7
6
5
4
3
2
1
L0
9
8
7
6
5
4
3
2
330
LEDDON
Trang 124
GVHD:Thc s L nh Kha
BI 3: HIN TH NGY THNG NM SINH TRN LED 7

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin vic hin th bng cch s dng LED 7 on theo nhiu phng php
khc nhau.
iu khin vic hin th cc thng tin v s liu bng cch s dng cc b hin th
dng LED 7 on.
YU CU:
Bit cch vit cc chng trnh iu khin LED 7 on.
Nm c s v nguyn l hot ng ca khi LED 7 on trn m hnh th
nghim.
Nm c nguyn l iu khin LED 7 on cc ch khc nhau.
Dng dy bus 6 ni Port A vi chn B transistor
Dng dy bus 8 ni Port B vi LED 7.
NG DNG:
S dng phng php qut th hin ngy, thng , nm ( 2 s cui) tng s chy t
LED 1 n LED 6 v hin th y trn 6 LED.
Trang 125
GVHD:Thc s L nh Kha
S MCH :
61
52
43
34
25
16
60PA
6RN3
7
8
9
10
11
12
4.7K
VCC
VC C
VC C
A
B
C
D
E
F
G
H
VC C
A
B
C
D
E
F
G
H
VC C
VC C
VC C
VC C
VC C
A
B
C
D
E
F
G
H
330
16 h
15 g
14 f
13 e
12 d
11 c
10 b
9 a
A
B
C
D
E
F
G
H
6RN2
6LED6
6LED5
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
VC C
VC C
8
7
6
5
4
3
2
1
6LED4
6LED3
Q6
A1015
Q5
A1015
Q4
A1015
A
B
C
D
E
F
G
H
60PC
VC C
6LED2
6LED1
Q3
A1015
VC C
Q2
A1015
Q1
A1015
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
Trang 126
GVHD:Thc s L nh Kha
BI 4: HIN TH NG H TRN LED 7

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin vic hin th bng cch s dng LED 7 on theo nhiu phng php
khc nhau.
iu khin vic hin th cc thng tin v s liu bng cch s dng cc b hin th
dng LED 7 on.
YU CU:
Bit cch vit cc chng trnh iu khin LED 7 on.
Nm c s v nguyn l hot ng ca khi LED 7 on trn m hnh th
nghim.
Nm c nguyn l iu khin LED 7 on cc ch khc nhau.
Dng dy bus 6 ni Port A vi chn B transistor
Dng dy bus 8 ni Port B vi LED 7.
NG DNG:
Vit chng trnh ng h n gin xut ra led 7(hai led u hin th gi, hai led
k hin th pht , hai led cui hin th giy).
Trang 127
GVHD:Thc s L nh Kha
S MCH :
61
52
43
34
25
16
60PA
6RN3
7
8
9
10
11
12
4.7K
VCC
h
g
f
e
d
c
b
a
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A
B
C
D
E
F
G
H
330
16
15
14
13
12
11
10
9
A
B
C
D
E
F
G
H
6RN2
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
6LED6
A
B
C
D
E
F
G
H
8
7
6
5
4
3
2
1
6LED5
6LED4
Q6
A1015
A
B
C
D
E
F
G
H
60PC
6LED3
6LED2
Q5
A1015
A
B
C
D
E
F
G
H
VCC
6LED1
Q4
A1015
Q3
A1015
Q2
A1015
VCC
Q1
A1015
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
a b c d e f g h
Trang 128
GVHD:Thc s L nh Kha
BI 5: CHNG TRNH N GIAO THNG

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin vic hin th bng cch s dng LED n v LED 7 on.
YU CU:
Nm c s v nguyn l hot ng ca khi mch n giao thng trn m
hnh th nghim.
Nm c nguyn l iu khin mch n giao thng.
TRNH T TIN HNH TH NGHIM
Dng dy bus 6 ni PortA vi cc LED n.
Dng dy bus 8 ni PortB vi LED 7 on pha di.
Dng dy bus 8 ni PortD vi LED 7 on pha trn.
NG DNG:
Vit chng trnh iu khin mch n giao thng c m ngc.
Trang 129
GVHD:Thc s L nh Kha
S MCH :
VCC
4R2
A
B
C
D
E
F
G
H
VCC
PORTB
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
VCC
330
D2
V2
X2
X1
V1
D1
PORTD
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
330
6
5
4
3
2
1
330
PORTA
Trang 130
GVHD:Thc s L nh Kha
BI 6 : CHY CH TRN LED MA TRN

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin vic hin th bng cch s dng LED ma trn.
ng dng thc hin vic hin th cc thng tin tnh v ng trn LED ma trn
dng quang bo.
YU CU:
Bit cch vit cc chng trnh iu khin LED ma trn cc ch khc nhau.
Nm c s v nguyn l hot ng ca khi LED ma trn trn m hnh th
nghim.
Nm c nguyn l iu khin LED ma trn cc ch khc nhau.
Bit cch vit chng trnh quang bo hin th cc thng tin c yu cu
(thng tin dng tnh v dng ng).
Dng dy bus 8 ni PortB vi hng ca Led Ma Trn.
Dng dy bus 8 ni PortC vi ct ca Led Ma Trn 1.
Dng dy bus 8 ni PortD vi ct Led Ma Trn 2.
NG DNG:
Vit chng trnh chy ch KIT THUC TAP PIC KHOA DIEN TU TIN
HOC .
Trang 131
GVHD:Thc s L nh Kha
S MCH :
VCC
b1
b2
Q1
A1015
c1
90PD
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9RN
16
15
14
13
12
11
10
9
b16
b15
b14
b13
b12
b11
b10
b9
16
15
14
13
12
11
10
9
b8
b7
b6
b5
b4
b3
b2
b1
b3
Q2
A1015
c2
b4
Q3
A1015
c3
b5
Q4
A1015
c4
b6
Q5
A1015
c5
Q6 b7
A1015
c6
b8
Q7
A1015
Q8
A1015
c8
c7
VCC
b9
b10
Q9
A1015
c9
Q10 b11
A1015
c10
Q12 b13
A1015
Q11 b12
A1015
c12
c11
Q13 b14
A1015
c13
Q14 b15
A1015
c14
Q15 b16
A1015
c15
Q16
A1015
c16
4k7
1
2
3
4
5
6
7
8
9RN2
4k7
c1c2c3c4c5c6c7c8
9RN3
90PB
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
c11
c12
c13
c14
c16
c9c10
c15
16
15
14
13
12
11
10
9
h8
h7
h6
h5
h4
h3
h2
h1
h8
h7
h6
h5
h4
h3
h2
h1
13
3
4
10
6
11
15
16
MTRAN1
5
2
7
1
12
8
14
9
8
7
6
5
4
3
2
1
5
2
7
1
12
8
14
9
90PC
h8
h7
h6
h5
h4
h3
h2
h1
13
3
4
10
6
11
15
16
MTRAN2
330
Trang 132
GVHD:Thc s L nh Kha
BI 7: HIN TH K T TRN LCD

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
Kho st nguyn l hot ng v nguyn l iu khin LCD.
iu khin hin th cc thng tin trn mn hnh tinh th lng LCD ( loi 2 hng
x 16 k t).
YU CU:
Bit cch vit cc chng trnh iu khin LCD.
Nm c s v nguyn l hot ng ca khi LCD trn m hnh th nghim.
Nm c nguyn l v cc k thut iu khin hin th cc thng tin trn
LCD.
Bit cch vit cc chng trnh ng dng hin th cc dng thng tin khc nhau
trn LCD ty theo nhu cu s dng.
Dng dy bus 3 ni PortE vi RS,RW,E ( RS = RE0, RW = RE1, E = RE2 )
Dng dy bus 8 ni PortB vi D0 n D7.
NG DNG:
Vit chng trnh xut d liu ln LCD
Line 1 : DO AN TOT NGHIEP
Line 2 : KIT THUC TAP PIC 16F877A
Trang 133
GVHD:Thc s L nh Kha
S MCH :
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
D0
D1
D2
D3
D4
D5
D6
D7
VDD
CON8
V0
RS
R/W
E
4
5
6
A
K
15
16
3VR
10K
LCD
J3
VCC
LCD
VSS
5
4
3
2
1
J4
CON5
Trang 134
GVHD:Thc s L nh Kha
BI 8: GIAO TIP BN PHM S HEX HIN TH LCD

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
iu khin thit b ngoi vi bng bn phm (bn phm thit k theo kiu ma trn).
Trnh by k thut qut phm cho dng bn phm ma trn 16 phm ( 4 hng x 4
ct).
Trnh by mt s ng dng trong k thut iu khin bn phm.
YU CU:
Bit cch vit cc chng trnh iu khin bn phm ma trn.
Nm c s v nguyn l hot ng ca khi bn phm ma trn trn m hnh
th nghim.
Nm c nguyn l v k thut qut phm cho cc dng bn phm ma trn.
Bit cch vit cc chng trnh ng dng c s dng bn phm ma trn iu
khin cc thit b ngoi vi khc nhau.
Dng dy bus 3 ni PortE vi RS, RW, E ( RS = RE0, RW = RE1, E = RE2 )
Dng dy bus 8 ni PortB vi D0 n D7
Dng dy bus 8 ni PortD vi bn phm s hex
NG DNG:
Vit chng trnh mi khi c phm nhn th hin th s ln LCD.
Trang 135
GVHD:Thc s L nh Kha
S MCH :
VCC
U1
R7
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10k
1DX
1R46
10K
1C7
1R47
1RS 104
100
VCC
1Y 1
1C8
1C9
33p
33p
1U1
10
9
8
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
23
24
RE2/CSAN7
RB7/PGD
RE1/WR/AN6
RB6/PGC
RB5
RE0/RD/AN5
MCLR/VPP
RB4
RA0/AN0
RB3/PGM
RA1/AN1
RB2
RA2/AN2/VRef -/CVRef
RB1
RA3/AN3/VRef +
RB0/INT
RA4/T0CKI/C1OUT
VDD
GND
RA5/AN4/SS/C2OUT
VDD
RD7/PSP7
GND
RD6/PSP6
OSC1/CLKI
RD5/PSP5
OSC2/CLKO
RD4/PSP4
RC0/T1OSO/T1CKI RD3/PSP3
RC1/T1OSI/CCP2 RD2/PSP2
RC2/CCP1
RD1/PSP1
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RC7/RX/DT
RC5/SDO
RC6/TX/CK
40
39
38
37
36
35
34
33
32
31
30
29
28
27
22
21
20
19
26
25
VCC
lcd
PIC16F877A
R6
R
R5
R
R4
R
R6
R
SW1
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
SW10
SW11
SW12
SW13
SW14
SW15
VCC
Trang 136
GVHD:Thc s L nh Kha
BI 9: IU CHNH ADC HIN TH LED N

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
Gi lp tn hiu tng t cung cp cho khi ADC.
YU CU:
Bit cch vit cc chng trnh iu khin ADC.
Nm c s v nguyn l hot ng ca khi ADC trn m hnh th nghim.
Dng dy bus 2 ni khi ADC vi PortA.0 (chn AN0).
NG DNG:
To mc in p thay i lin tc t 0V n 5V cho VK x l sau hin th ra
LED n.
Trang 137
GVHD:Thc s L nh Kha
S MCH :
L0
VCC
2
L1
1R46
10K
1R47
1DX
1C7
1RS 104
VR 10K
1C8
1C9
33p
33p
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MCLR/VPP
RB7/PGD
RA0/AN0
RB6/PGC
RA1/AN1
RB5
RA2/AN2/VRef -/CVRef RB4
RA3/AN3/VRef + RB3/PGM
RA4/T0CKI/C1OUT
RB2
RA5/AN4/SS/C2OUT
RB1
RE0/RD/AN5
RB0/INT
VDD
RE1/WR/AN6
GND
RE2/CSAN7
VDD
RD7/PSP7
GND
RD6/PSP6
OSC1/CLKI
RD5/PSP5
RD4/PSP4
OSC2/CLKO
RC0/T1OSO/T1CKI RC7/RX/DT
RC1/T1OSI/CCP2 RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL RC4/SDI/SDA
RD0/PSP0
RD3/PSP3
RD1/PSP1
RD2/PSP2
VCC
L2
1U1
VCC 100
1Y1
40
39
38
37
36
35
34
33
32
31 VCC
30
29
28
27
26
25
24
23
22
21
4R2
2
L3
L4
1
L5
1
2
L6
9
8
7
6
5
4
3
2
330
1
L7
2
PIC16F877A
Trang 138
GVHD:Thc s L nh Kha

Ngy Thng.Nm 2008
Sinh Vin Thc Hin :
NH GI - IM
K thut
Thao tc
T chc
NHN XT
MC CH:
o nhit mi trng v khng ch nhit bng VK.
YU CU:
Bit cch vit cc chng trnh ng dng c s dng LM35 iu khin cc
thit b ngoi vi khc nhau.
Nm c s v nguyn l hot ng ca khi o nhit trn m hnh th
nghim.
Nm c nguyn l nguyn l hot ng ca LM35.
Dng dy bus 2 ni chn 2 ca LM35 vi PortA.0 (chn AN0).
Dng dy bus 3 ni PortE vi RS,RW,E ( RS = RE0, RW = RE1, E = RE2 )
Dng dy bus 8 ni PortB vi D0 n D7.
NG DNG:
Vit chng trnh hin th nhit trn LCD.
Trang 139
GVHD:Thc s L nh Kha
S MCH:
VCC
U1403
VDD
VOUT
GND
J2
1
2
3
CON1
LM35
Trang 140
GVHD:Thc s L nh Kha
PHN IV
GII CC BI TP THC HNH

BI 1 : HIN TH TRNG THI PORT TRN LED N.
BI 6: CHY CH TRN LED MA TRN
BI 10: NHIT DNG LM35
Trang 141
GVHD:Thc s L nh Kha

//***********CHUONG TRINH LED DON **********
//***************XUAT RA PORTB ***************
//***********************************************
#include <16f877A.h>
#fuses nowdt,noprotect,nolvp,xt,put
#use delay(clock=4000000)
#use fast_io(b)
void main()
{
set_tris_b(0);
output_b(0);
while(true)
{
output_b(0b11111110);
delay_ms(250);
output_b(0b11111101);
delay_ms(250);
output_b(0b11111011);
delay_ms(250);
output_b(0b11110111);
delay_ms(250);
output_b(0b11101111);
delay_ms(250);
output_b(0b11011111);
delay_ms(250);
output_b(0b10111111);
delay_ms(250);
output_b(0b01111111);
delay_ms(250);
output_b(0b10111111);
delay_ms(250);
output_b(0b11011111);
delay_ms(250);
output_b(0b11101111);
delay_ms(250);
output_b(0b11110111);
delay_ms(250);
output_b(0b11110111);
delay_ms(250);
output_b(0b11111011);
delay_ms(250);
output_b(0b11111101);
Trang 142
GVHD:Thc s L nh Kha
delay_ms(250);
output_b(0b11111110);
delay_ms(250);
output_b(0b01111110);
delay_ms(250);
output_b(0b10111101);
delay_ms(250);
output_b(0b11011011);
delay_ms(250);
output_b(0b11100111);
delay_ms(250);
output_b(0b11011011);
delay_ms(250);
output_b(0b10111101);
delay_ms(250);
output_b(0b01111110);
delay_ms(250);
output_b(0b11111111);
output_b(0b00000000);
}
}
Trang 143
GVHD:Thc s L nh Kha

//********CHUONG TRINH LED DON******
//**********CO THAY DOI DELAY*********
//*********XUAT DU LIEU RA PORTC*****
//***************************************
#include <16f877a.h>
#fuses XT,NOWDT
#use delay(clock = 4000000)
#use fast_io(c)
int a=300;
int i;
void main()
{
set_tris_c(0);
output_c(255);
while (true)
{
for(i=10;i>=1;i--)
{
output_c(0b11111110);
delay_ms(a);
output_c(0b11111100);
delay_ms(a);
output_c(0b11111000);
delay_ms(a);
output_c(0b11110000);
delay_ms(a);
output_c(0b11100000);
delay_ms(a);
output_c(0b11000000);
delay_ms(a);
output_c(0b10000000);
delay_ms(a);
output_c(0x00);
delay_ms(a);
a=a-30;
}
a=300;
for(i=10;i>=1;i--)
{
Trang 144
GVHD:Thc s L nh Kha
output_c(0b01111111);
delay_ms(a);
output_c(0b00111111);
delay_ms(a);
output_c(0b00011111);
delay_ms(a);
output_c(0b00001111);
delay_ms(a);
output_c(0b00000111);
delay_ms(a);
output_c(0b00000011);
delay_ms(a);
output_c(0b00000001);
delay_ms(a);
output_c(0x00);
delay_ms(a);
a=a-30;
}
a=300;
for(i=10;i>=1;i--)
{
output_c(0b01010101);
delay_ms(a);
output_c(0b10101010);
delay_ms(a);
a=a-30;
}
}
}
Trang 145
GVHD:Thc s L nh Kha

//********CHUONG TRINH NGAY, THANG , NAM, SINH***********
//*****************HIEN THI TREN LED 7***********************
//*************QUET PORTA, DU LIEU PORT B*******************
//************************************************************
#include<16f877.h>
#fuses xt,nowdt
#use delay (clock =4000000)
#use fast_io(a)
#use fast_io(b)
int so[] =
{255,255,255,255,255,255,164,176,192,176,128,248,255,255,255,255,255,255};
int a,b,c,d=1,e,f;
void main()
{
set_tris_b(0);
set_tris_a(0);
while (true)
{
a=0;
//*******************kieu_1, nhap nhay 5
lan**************************
while(a<5)
{for (b=0;b<=100;b++)
{ d=1;
for (c=0;c<=5;c++)
{ e=63-d;
output_b(so[c+6]);output_a(e);delay_us(800);output_b(255);
d=d*2;
}
}
delay_ms(200);
a++;
}
//*********************kieu_2; dich so sang trai*****************
f=0;
while(a<12)
{for (b=0;b<=200;b++)
{ d=1;
for (c=0;c<=5;c++)
{ e=63-d;
output_b(so[c+f]);output_a(e);delay_us(800);output_b(255);
Trang 146
GVHD:Thc s L nh Kha
d=d*2;
}
}
a++;
f++;
}
delay_ms(200);
//***************kieu_3; nhap nhay 3 lan*******************
while(a<15)
{for (b=0;b<=100;b++)
{ d=1;
for (c=0;c<=5;c++)
{ e=63-d;
output_b(so[c+6]);output_a(e);delay_us(800);output_b(255);
d=d*2;
}
}
delay_ms(200);
a++;
}
//***************kieu_3; dich so sang phai*******************
f=12;
while(a<21)
{for (b=0;b<=200;b++)
{ d=1;
for (c=0;c<=5;c++)
{ e=63-d;
output_b(so[c+f]);output_a(e);delay_us(800);output_b(255);
d=d*2;
}
}
a++;
f--;
}
}
}
Trang 147
GVHD:Thc s L nh Kha

//***********CHUONG TRINH DONG HO**********
//*************HIEN THI TREN LED 7*************
//*********QUET PORTA, DU LIEU PORTC*********
//***********************************************
#include <16f877A.h>
#use delay (clock=4000000)
#fuses xt,nowdt
#use fast_io(a)
#use fast_io( b)
int a,b,c,d,e,f,g,h;
int const so[]={64,121,36,48,25,18,2,120,0,16};
void main ()
{set_tris_b(0);
set_tris_a(0);
while(true)
{
for (a=0;a<=2;a++)//h
{
for (b=0;b<=h;b++)//h
{
for (c=0;c<=5;c++)//m
{
for (d=0;d<=9;d++)//m
{
for (e=0;e<=5;e++)//s
{
for (f=0;f<=9;f++)//s
{
for (g=0;g<=100;g++)
{
output_b(so[f]);
output_a(0b011111);
delay_us(1500);
output_b(255);
output_b(so[e]);
output_a(0b101111);
delay_us(1500);
output_b(255);
output_b(so[d]);
output_a(0b110111);
Trang 148
GVHD:Thc s L nh Kha
delay_us(1500);
output_b(255);
output_b(so[c]);
output_a(0b111011);
delay_us(1500);
output_b(255);
output_b(so[b]);
output_a(0b111101);
delay_us(1500);
output_b(255);
output_b(so[a]);
output_a(0b111110);
delay_us(1500);
output_b(255);
if (a==2)
h=3;
else
h=9;
}
}
}
}
}
}
}
}
}
Trang 149
GVHD:Thc s L nh Kha

//******CHUONG TRINH DEN GIAO THONG ********
//******QUET PORTA, DU LIEU RTB,PORTD********
//*************************************************
#include <16f877.h>
#fuses NOWDT,XT
#use fast_io(b)
#use fast_io(A)
#use fast_io(d)
int8 i;
int const led_tren[]={0b00001001,0b10011111,0b00110001,
0b00010101,0b10000111 ,0b01000101,0b01000001,
0b00011111,0b00000001,0b00000101};
int const led_duoi[]={0b00001100,0b11001111,0b10011000,
0b10001010,0b01001011,0b00101010,0b00101000,
0b10001111,0b00001000,0b00001010};
void main ()
{ set_tris_A(0);output_A(255);
set_tris_b(0);output_b(255);
set_tris_d(0);output_d(255);
while(true)
{
output_a(0b11011011);
for (i=9;i>=3;i--)
{
output_b(led_duoi[i-3]);
output_d(led_tren[i]);
delay_ms(1500);
output_b(255);
output_d(255);
} //xanh1 + do2
output_a(0b11011101);
for (i=3;i>=1;i--)
{
output_d(led_tren[i-1]);
delay_ms(1500);
output_b(255);
output_d(255);
} //vang1 + do2
if (i=0)
Trang 150
GVHD:Thc s L nh Kha
{
i=9;
}
output_a(0b11110110);
for (i=9;i>=3;i--)
{
output_b(led_duoi[i]);
delay_ms(1500);
output_b(255);
output_d(255);
} //xanh2 + do1
output_a(0b11101110);
for (i=3;i>=1;i--)
{
delay_ms(1500);
output_b(255);
output_d(255);
} //vang2 + do1
}
}
Trang 151
GVHD:Thc s L nh Kha
BI 6: CHY CH TRN LED MA TRN

// DATA PORTB, LED MATRIX 1, 2 PORTD V PORTC
#include <16f877.h>
#fuses xt,nowdt,noprotect
#use delay(clock =4000000)
#use fast_io(a)
#use fast_io(b)
#use fast_io(d)
int16 i,a,b=0,c=1,d,e,f;
int8 const kytu[240] = {
0XFF,0XFF,0XFF,0XFF,0XFF,0XFF
0X80,0XF7,0XEB,0XDD,0XBE,0XFF
//CHU K
0XBE,0XBE,0X80,0XBE,0XBE,0XFF
//CHU I
0XBF,0XBF,0X80,0XBF,0XBF,0XFF
//CHU T
//CHU T
0X80,0XF7,0XF7,0XF7,0X80,0XFF
//CHU H
0X81,0XFE,0XFE,0XFE,0X81,0XFF
//CHU U
0XC1,0XBE,0XBE,0XBE,0XDD,0XFF
//CHU C
//CHU T
0XE0,0XD7,0XB7,0XD7,0XE0,0XFF
//CHU A
0X80,0XB7,0XB7,0XB7,0XCF,0XFF
//CHU P
0X80,0XB7,0XB7,0XB7,0XCF,0XFF
//CHU P
0XBE,0XBE,0X80,0XBE,0XBE,0xFF
//CHU I
0XC1,0XBE,0XBE,0XBE,0XDD,0XFF //CHU
0X80,0XF7,0XEB,0XDD,0XBE,0XFF
//CHU K
0X80,0XF7,0XF7,0XF7,0X80,0XFF
//CHU H
0XC1,0XBE,0XBE,0XBE,0XC1,0XFF //CHU O
0XE0,0XD7,0XB7,0XD7,0XE0,0XFF
//CHU A
0X80,0XBE,0XBE,0XBE,0XC1,0XFF
//CHU D
0XBE,0XBE,0X80,0XBE,0XBE,0XFF //CHU I
0X80,0XB6,0XB6,0XB6,0XBE,0XFF
//CHU E
0X80,0XDF,0XEF,0XF7,0X80,0XFF
//CHU N
//CHU T
0X81,0XFE,0XFE,0XFE,0X81,0XFF
//CHU U
0XFF,0XF7,0XF7,0XF7,0XF7,0XFF
//DAU -
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0XBF,0XBF,0X80,0XBF,0XBF,0XFF //CHU T
0XBE,0XBE,0X80,0XBE,0XBE,0XFF //CHU I
0X80,0XDF,0XEF,0XF7,0X80,0XFF
//CHU N
0X80,0XF7,0XF7,0XF7,0X80,0XFF
//CHU H
0XC1,0XBE,0XBE,0XBE,0XC1,0XFF //CHU O
0XC1,0XBE,0XBE,0XBE,0XDD,0XFF}; //CHU C
void hienthi();
void main()
{
set_tris_b(0); output_b(0);
set_tris_d(0); output_d(0);
set_tris_c(0); output_c(0);
while (1)
{
for (i =0;i<500;i++)
{hienthi();}
if (b==239)
b=0;
else
b++;
}
}
void hienthi()
{
e=255-c;
f=255-d;
output_b(kytu[a]);
output_d(e);
output_c(f);
c=c*2;
d=d*2;
if (c==256)
{
c=0;
d=1;
}
if (d==256)
{
d=0;
c=1;
a=b;
}
if (a==239)
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a=0;
else a++;
delay_us(250);
output_d(255);
output_c(255);
}
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//****CHUONG TRINH CHAY CHU TREN LCD***
//****PORTB DU LIEU, PORTC,PORTD QUET****
//*************************************************
#include <16F877A.h>
#include <DEFS_16F877A.h>
#fuses XT,NOWDT,NOPROTECT
#define RS RE2
#define RW RE1
#define E RE0
#define LCD PORTB
const unsigned char line1[]={'D','O',' ','A','N',' ','T','O','T',' '
, 'N','G','H','I','E','P','#'};
const unsigned char line2[]={'K','I','T',' ','T','H','U','C',' ','T','A','P',' '
,'P','I','C',' ', '1','6','F','8','7','7','A',' ',' ','#'};
const unsigned char line3[]={ ' ',' ','K','H','O','A',' ','D','T',' ','-',' ','T','H','#'};
const unsigned char line4[]={
' ',' ','G','V','H','D',':',' ','L','E',' ','D','I','N','H',' ','K','H','A'
,' ',' ','S','V','T','H',':',' ','T','R','A','N',' ','T','H','A','N','H',' ','T','A','M'
,' ','&',' ','N','G','U','Y','E','N',' ','T','I','E','N',' ','N','G','H','I','A,' ',' ','#'} ;
/**************************/
void command(void)
{
RS = 0; // GHI LENH
RW = 0;
E = 1;
E = 0;
delay_ms(1);
}
/**************************/
void send(void)
{
RS = 1;// GHI DU LIEU
RW = 0;
E = 1;
E = 0;
delay_ms(1);
}
void main(void)
{
while(true)
{
int i = 0, y=0, k=0, z=0, a=0, b=0, c=0;
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set_tris_B(0);
set_tris_E(0);
delay_ms(100);
LCD = 0x38;
command();
LCD = 0x0C;
command();
LCD = 0x80;
command();
while (line1[y]!='#')
{
LCD=line1[y];
send();
delay_ms(100);
y++;
}
lcd=0xC0;
command();
while(i<16)
{
lcd=line2[i];
send();
i++;
delay_ms(200);
}
i=2;
while (line2[z]!='#')
{
LCD = 0x80;
command();
y=0;
while (line1[y]!='#')
{
lcd=line1[y];
send();
y++;
}
lcd=0xc0;
command();
k=i+16;
for(z=i;z<k;z++)
{
lcd=line2[z];
send();
}
delay_ms(100);
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i++;
delay_ms(500);
lcd=0x01;
command();
LCD = 0x82;
command();
}
while (line3[a]!='#')
{
LCD=line3[a];
send();
delay_ms(100);
a++;
}
i=0;
while (line4[b]!='#')
{
LCD = 0x80;
command();
a=0;
while (line3[a]!='#')
{
lcd=line3[a];
send();
a++;
}
lcd=0xc0;
command();
k=i+16;
for(b=i;b<k;b++)
{
lcd=line4[b];
send();
}
delay_ms(100);
i++;
delay_ms(500);
lcd=0x01;
command();
LCD = 0x82;
command();
}
}
}
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// *****GIAO TIEP BAN PHIM VOI LCD***
// RS,RW,E POTRE
// LCD PORT B
// KEYPAD PORT D
//*****************************************
#include "16F877A.h"
#include <DEFS_16f877a.h>
#fuses XT,NOWDT,NOPROTECT,NOLVP
#byte portD=0x08
#byte portB=0x06
#byte portE=0x09
const unsigned char dig[]= {'X','I','N',' ','M','O','I'
,' ','N','H','A','P', ' ','S','O','#'};
int8 i,j,a=0;
void lenh(void)
{
output_low(pin_e0);
output_low(pin_e1);
output_high(pin_e2);
output_low(pin_e2);
delay_ms(6);
}
void du_lieu(void)
{
output_low(pin_e1);
output_low(pin_e2);
delay_ms(6);
}
void main(void)
{
output_b(0x38);
lenh();
output_b(0x0E);
lenh();
output_b(0x80);
lenh();
While (dig[a]!='#')
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{
portb=dig[a];
du_lieu();
delay_ms(100);
a++;
}
output_b(0XC0);
lenh();
delay_ms(100);
output_d(0b11111111);
while(1)
{
//****************************************************
output_d(0b11111110);
delay_ms(10);
if( input(pin_D4)==0 )
{
output_b(0x37); //ghi 7
du_lieu();
delay_ms(150);
}
if( input(PIN_D5)==0 ) //cho khi D5 xuong 0
{
du_lieu();
delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
output_b('A'); // ghi a
du_lieu();
delay_ms(150);
}
//****************************************************
output_D(0b11111101);
delay_ms(10);
{
du_lieu();
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delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
output_b('B'); //ghi b
du_lieu();
delay_ms(150);
}
//****************************************************
output_D(0b11111011);
delay_ms(10);
{
du_lieu();
delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
output_b('C'); //ghi c
du_lieu();
delay_ms(150);
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}
//****************************************************
output_D(0b11110111);
delay_ms(10);
{
output_b('*'); //ghi *
du_lieu();
delay_ms(150);
}
{
du_lieu();
delay_ms(150);
}
{
output_b(0X01); //CLEAR
lenh();
delay_ms(150);
}
{
portb='D'; //ghi d
du_lieu();
delay_ms(150);
}
}
}
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//***********ADC Hien Thi Led Don*************

//*********** Led noi voi portB******************
//**** ********AN0 lay mau tin hieu**************
#include <16F877.h>
#fuses XT,NOWDT,NOPROTECT,NOLVP
#device 16F877*=16 ADC=8
Int8 adc;
main()
{
setup_adc(adc_clock_internal);
setup_adc_ports(AN0);
set_adc_channel(0);
delay_ms(10);
while(true)
{
adc=read_adc();
output_B(adc);
}
}
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//***************Do Nhiet Do Hien Thi LCD******************
//*********** *******LCD noi voi portB*********************
//**** *****************AN0 tin hieu***********************
//********************************************************
#include <16f877.h>
#fuses xt,nowdt
#device *=16 adc =8
#use delay (clock=4000000)
#use fast_io(e)
#use fast_io(b)
#bit rs = 0x09.0
#bit rw = 0x09.1
#bit e = 0x09.2
#byte LCD = 0X06
const char line_1[]="CHUONG TRINH DO NHIET DO SU DUNG LM35 #";
const char line_2[]="000102030405060708091011121314151617181920212223
242526272829303132333435363738394041424344454647484950";
const char line_3[]="NHIET DO:#";
const char line_4[]=" DO C#";
int i,b,a,adc;
//**********************************************
void command()
{
rs = 0;
rw =0;
e=1;
e=0;
Delay_ms(1);
}
//**********************************************
void write_data()
{
rs =1;
rw = 0;
e=1;
e=0;
Delay_ms(1);
}
//**********************************************
void main()
{
Setup_ADC ( ADC_clock_internal ) ;
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Setup_ADC_ports (AN0);
Set_ADC_channel ( 0 ) ;
Delay_us (10 ); // delay 10 us
set_tris_e(0);output_e(0);
set_tris_b(0);output_b(0);
set_tris_c(0);output_c(0);
While(true)
{
lcd=0x38;
command();
lcd =0x0c;
command();
lcd=0X01;
command();
delay_ms(1);
LCD =0xC0;
command();
a=0;
while(line_3[a]!='#')
{
lcd = line_3[a];
write_data();
a++;
}
adc =4* read_adc ( ) ;//doc gia tri adc
lcd=0xc9;
command();
for (i=1;i<=2;i++)
{lcd = line_2[adc];
write_data();
adc++;
}
lcd=0xcb;
command();
a=0;
{
lcd = line_4[a];
write_data();
a++;
}
lcd=0x80;
command();
a=0;
While (a<=16)
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{
LCD = line_1[a];
write_data();
Delay_ms(100);
a++;
}
b=0;
LCD =0xc0;
command();
while (line_1[a]!='#')
{
a=0;
{
lcd = line_3[a];
write_data();
a++;
}
adc = 4*read_adc ( ) ;
lcd=0xc9;
command();
for (i=1;i<=2;i++)
{
lcd = line_2[adc];
write_data();
adc++;
}
lcd=0xcb;
command();
a=0;
{
lcd = line_4[a];
write_data();
a++;
}
b++;
a=b;
i=0;
lcd =0x80;
command();
while (i<=16)
{
lcd = line_1[a];
write_data();
a++;
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i++;
}
delay_ms(300);
}
a=0;
}
}
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PHN V
PH LC
Ph lc 1 : 16F877A.H
Ph lc 2 : DEFS_16F877A.H
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16FF877A.H
//////// Standard Header file for the PIC16F877 device ////////////////
#device PIC16F877
#nolist
//////// Program memory: 8192x14 Data RAM: 367 Stack: 8
//////// I/O: 33 Analog Pins: 8
//////// Data EEPROM: 256
//////// C Scratch area: 77 ID Location: 2000
//////// Fuses: LP,XT,HS,RC,NOWDT,WDT,NOPUT,PUT,PROTECT,PROTECT_5%
//////// Fuses:
PROTECT_50%,NOPROTECT,NOBROWNOUT,BROWNOUT,LVP,NOLVP,CPD
//////// Fuses: NOCPD,WRT,NOWRT,DEBUG,NODEBUG
////////
////////////////////////////////////////////////////////////////// I/O
// Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
//
PORT_x_PULLUPS(), INPUT(),
//
OUTPUT_LOW(), OUTPUT_HIGH(),
//
OUTPUT_FLOAT(), OUTPUT_BIT()
// Constants used to identify pins in the above are:
#define PIN_A0
#define PIN_A1
#define PIN_A2
#define PIN_A3
#define PIN_A4
#define PIN_A5
40
41
42
43
44
45
#define PIN_B0
#define PIN_B1
#define PIN_B2
#define PIN_B3
#define PIN_B4
#define PIN_B5
#define PIN_B6
#define PIN_B7
48
49
50
51
52
53
54
55
#define PIN_C0
#define PIN_C1
#define PIN_C2
#define PIN_C3
#define PIN_C4
#define PIN_C5
56
57
58
59
60
61
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#define PIN_C6 62
#define PIN_C7 63
#define PIN_D0
#define PIN_D1
#define PIN_D2
#define PIN_D3
#define PIN_D4
#define PIN_D5
#define PIN_D6
#define PIN_D7
64
65
66
67
68
69
70
71
#define PIN_E0 72
#define PIN_E1 73
#define PIN_E2 74
////////////////////////////////////////////////////////////////// Useful defines
#define FALSE 0
#define TRUE 1
#define BYTE int
#define BOOLEAN short int
#define getc getch
#define fgetc getch
#define getchar getch
#define putc putchar
#define fputc putchar
#define fgets gets
#define fputs puts
////////////////////////////////////////////////////////////////// Control
// Control Functions: RESET_CPU(), SLEEP(), RESTART_CAUSE()
// Constants returned from RESTART_CAUSE() are:
#define WDT_FROM_SLEEP 3
#define WDT_TIMEOUT 11
#define MCLR_FROM_SLEEP 19
#define MCLR_FROM_RUN 27
#define NORMAL_POWER_UP 24
#define BROWNOUT_RESTART 26
////////////////////////////////////////////////////////////////// Timer 0
// Timer 0 (AKA RTCC)Functions: SETUP_COUNTERS() or SETUP_TIMER_0(),
//
SET_TIMER0() or SET_RTCC(),
//
GET_TIMER0() or GET_RTCC()
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// Constants used for SETUP_TIMER_0() are:

#define RTCC_INTERNAL 0
#define RTCC_EXT_L_TO_H 32
#define RTCC_EXT_H_TO_L 48
#define RTCC_DIV_1
#define RTCC_DIV_2
#define RTCC_DIV_4
#define RTCC_DIV_8
#define RTCC_DIV_16
#define RTCC_DIV_32
#define RTCC_DIV_64
#define RTCC_DIV_128
#define RTCC_DIV_256
8
0
1
2
3
4
5
6
7
#define RTCC_8_BIT
// Constants used for SETUP_COUNTERS() are the above

// constants for the 1st param and the following for
// the 2nd param:
////////////////////////////////////////////////////////////////// WDT
// Watch Dog Timer Functions: SETUP_WDT() or SETUP_COUNTERS() (see above)
//
RESTART_WDT()
//
#define WDT_18MS
#define WDT_36MS
#define WDT_72MS
#define WDT_144MS
#define WDT_288MS
#define WDT_576MS
#define WDT_1152MS
#define WDT_2304MS
0x8008
9
10
11
12
13
14
15
////////////////////////////////////////////////////////////////// Timer 1
// Timer 1 Functions: SETUP_TIMER_1, GET_TIMER1, SET_TIMER1
// (or (via |) together constants from each group)
#define T1_DISABLED
0
#define T1_INTERNAL
0x85
#define T1_EXTERNAL
0x87
#define T1_EXTERNAL_SYNC 0x83
#define T1_CLK_OUT
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#define T1_DIV_BY_1
#define T1_DIV_BY_2
#define T1_DIV_BY_4
#define T1_DIV_BY_8
GVHD:Thc s L nh Kha
0
0x10
0x20
0x30
////////////////////////////////////////////////////////////////// Timer 2
// Timer 2 Functions: SETUP_TIMER_2, GET_TIMER2, SET_TIMER2
#define T2_DISABLED
0
#define T2_DIV_BY_1
4
#define T2_DIV_BY_4
5
#define T2_DIV_BY_16
6
////////////////////////////////////////////////////////////////// CCP
// CCP Functions: SETUP_CCPx, SET_PWMx_DUTY
// CCP Variables: CCP_x, CCP_x_LOW, CCP_x_HIGH
// Constants used for SETUP_CCPx() are:
#define CCP_OFF
0
#define CCP_CAPTURE_FE
4
#define CCP_CAPTURE_RE
5
#define CCP_CAPTURE_DIV_4
6
#define CCP_CAPTURE_DIV_16
7
#define CCP_COMPARE_SET_ON_MATCH
8
#define CCP_COMPARE_CLR_ON_MATCH
9
#define CCP_COMPARE_INT
0xA
#define CCP_COMPARE_RESET_TIMER
0xB
#define CCP_PWM
0xC
#define CCP_PWM_PLUS_1
0x1c
0x2c
0x3c
long CCP_1;
#byte CCP_1 =
0x15
#byte CCP_1_LOW=
0x15
#byte CCP_1_HIGH=
0x16
long CCP_2;
#byte CCP_2 =
0x1B
#byte CCP_2_LOW=
0x1B
#byte CCP_2_HIGH=
0x1C
////////////////////////////////////////////////////////////////// PSP
// PSP Functions: SETUP_PSP, PSP_INPUT_FULL(), PSP_OUTPUT_FULL(),
//
PSP_OVERFLOW(), INPUT_D(), OUTPUT_D()
// PSP Variables: PSP_DATA
// Constants used in SETUP_PSP() are:
#define PSP_ENABLED
0x10
#define PSP_DISABLED
0
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#byte PSP_DATA=
GVHD:Thc s L nh Kha
////////////////////////////////////////////////////////////////// SPI
// SPI Functions: SETUP_SPI, SPI_WRITE, SPI_READ, SPI_DATA_IN
// Constants used in SETUP_SPI() are:
#define SPI_MASTER
0x20
#define SPI_SLAVE
0x24
#define SPI_L_TO_H
0
#define SPI_H_TO_L
0x10
#define SPI_CLK_DIV_4 0
#define SPI_CLK_T2
3
#define SPI_SS_DISABLED 1
#define SPI_SAMPLE_AT_END 0x8000
#define SPI_XMIT_L_TO_H 0x4000
////////////////////////////////////////////////////////////////// UART
// Constants used in setup_uart() are:
// FALSE - Turn UART off
// TRUE - Turn UART on
#define UART_ADDRESS
2
#define UART_DATA
4
////////////////////////////////////////////////////////////////// ADC
// ADC Functions: SETUP_ADC(), SETUP_ADC_PORTS() (aka SETUP_PORT_A),
//
SET_ADC_CHANNEL(), READ_ADC()
// Constants used for SETUP_ADC() are:
#define ADC_OFF
0
// ADC Off
#define ADC_CLOCK_DIV_2 0x100
#define ADC_CLOCK_INTERNAL 0xc0
// Internal 2-6us
// Constants used in SETUP_ADC_PORTS() are:
#define NO_ANALOGS
7 // None
#define ALL_ANALOG
0 // A0 A1 A2 A3 A5 E0 E1 E2
#define AN0_AN1_AN2_AN4_AN5_AN6_AN7_VSS_VREF 1 // A0 A1 A2 A5 E0
E1 E2 VRefh=A3
#define AN0_AN1_AN2_AN3_AN4
2 // A0 A1 A2 A3 A5
#define AN0_AN1_AN2_AN4_VSS_VREF
3 // A0 A1 A2 A4 VRefh=A3
#define AN0_AN1_AN3
4 // A0 A1 A3
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#define AN0_AN1_VSS_VREF
5 // A0 A1 VRefh=A3
#define AN0_AN1_AN4_AN5_AN6_AN7_VREF_VREF 0x08 // A0 A1 A5 E0 E1 E2
VRefh=A3 VRefl=A2
#define AN0_AN1_AN2_AN3_AN4_AN5
0x09 // A0 A1 A2 A3 A5 E0
#define AN0_AN1_AN2_AN4_AN5_VSS_VREF 0x0A // A0 A1 A2 A5 E0
VRefh=A3
#define AN0_AN1_AN4_AN5_VREF_VREF
0x0B // A0 A1 A5 E0 VRefh=A3
VRefl=A2
#define AN0_AN1_AN4_VREF_VREF
0x0C // A0 A1 A4 VRefh=A3
VRefl=A2
#define AN0_AN1_VREF_VREF
0x0D // A0 A1 VRefh=A3 VRefl=A2
#define AN0
0x0E // A0
#define AN0_VREF_VREF
0x0F // A0 VRefh=A3 VRefl=A2
#define ANALOG_RA3_REF
0x1
//!old only provided for compatibility
#define A_ANALOG
0x2
#define A_ANALOG_RA3_REF
0x3
#define RA0_RA1_RA3_ANALOG 0x4
#define RA0_RA1_ANALOG_RA3_REF 0x5
//!old only provided for
compatibility
#define ANALOG_RA3_RA2_REF
0x8 //!old only provided for compatibility
#define ANALOG_NOT_RE1_RE2
0x9 //!old only provided for compatibility
#define ANALOG_NOT_RE1_RE2_REF_RA3 0xA //!old only provided for
compatibility
#define ANALOG_NOT_RE1_RE2_REF_RA3_RA2 0xB //!old only provided for
compatibility
#define A_ANALOG_RA3_RA2_REF
0xC //!old only provided for
compatibility
#define RA0_RA1_ANALOG_RA3_RA2_REF 0xD //!old only provided for
compatibility
#define RA0_ANALOG
0xE //!old only provided for compatibility
#define RA0_ANALOG_RA3_RA2_REF
0xF //!old only provided for
compatibility
// Constants used in READ_ADC() are:
#define ADC_START_AND_READ 7 // This is the default if nothing is specified
#define ADC_START_ONLY
1
#define ADC_READ_ONLY
6
////////////////////////////////////////////////////////////////// INT
// Interrupt Functions: ENABLE_INTERRUPTS(), DISABLE_INTERRUPTS(),
//
EXT_INT_EDGE()
//
// Constants used in EXT_INT_EDGE() are:
Trang 173
GVHD:Thc s L nh Kha
#define L_TO_H
0x40
#define H_TO_L
0
// Constants used in ENABLE/DISABLE_INTERRUPTS() are:
#define GLOBAL
0x0BC0
#define INT_RTCC
0x0B20
#define INT_RB
0xFF0B08
#define INT_EXT
0x0B10
#define INT_AD
0x8C40
#define INT_TBE
0x8C10
#define INT_RDA
0x8C20
#define INT_TIMER1
0x8C01
#define INT_TIMER2
0x8C02
#define INT_CCP1
0x8C04
#define INT_CCP2
0x8D01
#define INT_SSP
0x8C08
#define INT_PSP
0x8C80
#define INT_BUSCOL
0x8D08
#define INT_EEPROM
0x8D10
#define INT_TIMER0
0x0B20
#list
Trang 174
GVHD:Thc s L nh Kha
DEFS_16F877A.H
//========================= Register Definitions
==========================
//-----Register Files-----------------------------------------------------#byte PORTA = 0x05
#byte PORTB = 0x06
#byte PORTC = 0x07
#byte PORTD = 0x08
#byte PORTE = 0x09
#byte EEDATA = 0x10C
#byte EEADR = 0x10D
#byte EEDATH = 0x10E
#byte EEADRH = 0x10F
#byte EECON1 = 0x18C
#byte EECON2 = 0x18D
#byte PR2
= 0x92
#bit RA4
#bit RA3
#bit RA2
#bit RA1
#bit RA0
= 0x05.4
= 0x05.3
= 0x05.2
= 0x05.1
= 0x05.0
#bit RB7
#bit RB6
#bit RB5
#bit RB4
#bit RB3
#bit RB2
#bit RB1
#bit RB0
= 0x06.7
= 0x06.6
= 0x06.5
= 0x06.4
= 0x06.3
= 0x06.2
= 0x06.1
= 0x06.0
#bit RC7
#bit RC6
#bit RC5
#bit RC4
#bit RC3
#bit RC2
#bit RC1
#bit RC0
= 0x07.7
= 0x07.6
= 0x07.5
= 0x07.4
= 0x07.3
= 0x07.2
= 0x07.1
= 0x07.0
Trang 175
#bit RD7
#bit RD6
#bit RD5
#bit RD4
#bit RD3
#bit RD2
#bit RD1
#bit RD0
= 0x08.7
= 0x08.6
= 0x08.5
= 0x08.4
= 0x08.3
= 0x08.2
= 0x08.1
= 0x08.0
#bit RE2
#bit RE1
#bit RE0
= 0x09.2
= 0x09.1
= 0x09.0
GVHD:Thc s L nh Kha
//----- INTCON ------------------------------------------------------------#bit

#bit
#bit
#bit
#bit
#bit
#bit
#bit
GIE = 0x0b.7
PEIE = 0x0b.6
TMR0IE = 0x0b.5
INTE = 0x0b.4
RBIE = 0x0b.3
TMR0IF = 0x0b.2
INTF = 0x0b.1
RBIF = 0x0b.0
//----- PIR1 --------------------------------------------------------------#bit PSPIF = 0x0c.7

#bit ADIF = 0x0c.6
#bit RCIF = 0x0c.5
#bit TXIF = 0x0c.4
#bit SSPIF = 0x0c.3
#bit CCP1IF = 0x0c.2
#bit TMR2IF = 0x0c.1
#bit TMR1IF = 0x0c.0
//----- PIR2 --------------------------------------------------------------#bit CMIF
#bit EEIF
#bit BCLIF
#bit CCP2IF
= 0x0d.6
= 0x0d.4
= 0x0d.3
= 0x0d.0
//----- PIE1 --------------------------------------------------------------#bit PSPIE
= 0x8c.7
Trang 176
GVHD:Thc s L nh Kha
#bit ADIE = 0x8c.6

#bit RCIE = 0x8c.5
#bit TXIE = 0x8c.4
#bit SSPIE = 0x8c.3
#bit CCP1IE = 0x8c.2
#bit TMR2IE = 0x8c.1
#bit TMR1IE = 0x8c.0
//----- PIE2 --------------------------------------------------------------#bit CMIE
#bit EEIE
#bit BCLIE
#bit CCP2IE
= 0x8d.6
= 0x8d.4
= 0x8d.3
= 0x8d.0
Trang 177

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NHN XT CA GIO VIN HNG DN

NHN XT CA GIO VIN PHN BIN

Thy : PHAN DUY ANH

Sinh vin thc hin

Ngy nay Khoa hc K thut pht trin mnh m,

n Tt Nghip Kha 2005 2008

PHN I KHO ST VI IU KHIN PIC 16F877A .............. 12

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

CHNG IV B BIN I ADC 10 BIT............................................................. 55

PHN II CC THNH PHN CA KIT THC TP

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

HIN TH LED N....................................................................... 68

1.1. Gii thiu chung ......................................................................................................... 68

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

5.1. Gii thiu chung v LCD .......................................................................................... 87

GIAO TIP I2C........................................................................ 107

8.1. Gii thiu chung v I2C .......................................................................................... 107

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

8.2.3. EEPROM 24C04 ....................................................................................... 115

PHN III CC BI TP THC HNH .................................. 120

PHN VI GII CC BI TP THC HNH ........................ 141

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

BI 10 O NHIT .......................................................................................... 163

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

KHO ST VI IU KHIN PIC

: CU TRC PHN CNG CA PIC16F877A

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

CHNG I : CU TRC PHN CNG CA

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

PIC16F877A l h vi iu khin c 40 chn, mi chn c mt chc nng khc

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

1.3 Mt s im c bit ca CPU:

Trong cc ch LP, XT v HS chng ta

Vic la chn t trong dao ng thch anh da vo bng sau:

* Cch tnh chu k my:

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

1.3.5 Ch ngun thp Sleep (Power down Mode) :

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

Do khi ch sleep dng cung cp cho VK l rt nh nn ta cn thc hin cc

SVTH :Trn Thnh Tm & Nguyn Tin Ngha

n Tt Nghip Kha 2005 2008

1.4 T chc b nh: