Bn dch Datasheet ca vi iu khin AVR Atmega 128 Created by Le Duy Khanh Date : 06/02/2010

I . c im , tnh nng ( Features ) :

+ Hiu sut cao , tit kim in + Hon thin cu trc RISC - 133 lnh hiu qu - thc thi tt c cc chu k ng h n - 32 *8 thanh ghi chung a nng + cc thanh ghi iu khin ngoi vi - y cc qu trnh iu khin tnh - Nng ln 16 MIPS d liu ti 16 MHz - Chip 2 nhn + bn , sc chu ng cao , khng thay i phn vng nh - 128 K Bytes b nh Flash c th lp trnh c trong h thng - 4K Bytes EEPROM - 4K Bytes b nh SRAM bn trong - Chu k ghi/xa : 10000 Flash / 100000 EEPROM - bn d liu 20 nm 85 / 100 nm 25 - on m la chn ch khi ng vi cc bt kha c lp trong chng trnh h thng bi chng trnh khi ng c tht trong khi qu trnh ghi din ra - Ti a 64K Bytes khng gian nh bn ngoi la chn - Lp trnh kha cho phn mm bo mt - Giao din SPI cho lp trnh trong h thng + giao din JTAG ( ph hp vi tiu chun IEEE 1149.1 - Kh nng qut bin theo tiu chun JTAG - H tr ch sa tm ( debug ) trn chip - Lp trnh ca Flash , EEPROM , b bo v ( FUSE) v Bit kha ( Lock Bits) thng qua giao din JTAG + c im ngoi vi - 2 b Timer /counter 8 bit vi b m gp trc ring bit v ch so snh mu - 2 b timer /counter 16 bit m rng vi b m gp trc ch so snh mu v ch thu thp ( bt d liu ) - B counter thi gian thc vi b dao ng ( oscillator ) ring bit - 2 knh PWM 8 bit - 6 knh PWM vi kh nng lp trnh chnh xc t 2 n 16 bit - B iu ch so snh tn hiu ra - 8 knh , 10 bit ADC : 8 knh u cui n , 7 knh khc nhau ( vi phn ) , 2 knh khc nhau vi b khuych i lp trnh c ti 1x , 10x ,200x - Bit nh hng vi 2 dy giao din ni tip

- Lp trnh kp cc USARTs ni tip - Giao din ni tip SPI ch t - Lp trnh timer Watchdog vi b dao ng trn chip - B so snh tng t trn chip + cc tnh nng c bit ca b vi x l - thit lp bt li ngun v lp trnh li khi pht hin ngun yu (brown-out) - hiu chnh b dao ng RC bn trong - Ngt ngun trong v ngoi - 6 ch ch ( sleep ) : Idle ngh , gim n ADC , tit kim in ( power saver) , ngt in , ch ch ( standby ) , ch ch m rng - Phn mm la chn tn s xung nhp - La chn ch so snh Atmega 103 bi b cu ch Fuse - V hiu ha dng li ton b + cng vo ra v dng ng gi - 53 ng vo ra lp trnh c - 64 chn TQFP v 64 khi QFN/MLF + in p hot ng - 2,7 5,5 V Atmega 128L - 4,5 5,5 V Atmega 128 + Mc tc xung nhp - 0 8 MHz Atmega 128L - 0 16 Mhz Atmega 128

II . Cu hnh chn ( pin configurations )

Hnh 1 : chn ra ca Atmega 128 Atmega 128 l mt b vi x l CMOS in p thp da trn nn kin trc AVR RISC nng cao . Bng cch thi hnh cc lnh mt cch mnh m trong mt chu k ng h duy nht , Atmega128 c th cho php tc t uc l 1 MPIS trn 1 MHz t n gip ngi thit k h thng c kh nng ti u ho in nng s dng so vi tc s l.

S khi ( Block Diagram)

Li AVR bao gm 1 tp hp cc lnh ci t vi 32 thanh ghi chung a nng . Tt c 32 thanh ghi th c ni trc tip vi khi s hc v logic (ALU ) n cho php 2 thanh ghi c lp c truy cp trong 1 lnh thc thi trong mt chu k qut xung ng h . kt qu ca cu trc ny l c nhiu kiu ch hiu qu hn trong khi vn t c tc ti a nhanh hn 10 ln cc b vi s l CISC thng thng . Atmega 128 cng cung cp cc tnh nng sau y : 128K bytes ca b nh lp trnh Flash trong h thng vi kh nng c trong khi ang ghi , 4 K bytes EEPROM , 4 K bytes SRAM , 53 ng vo ra a nng , 32 thanh ghi chung a nng , b m thi gian thc , 4 b timer /counter tin dng vi kiu so snh v PWM , 2 USART , 1 bit nh hng 2 dy giao din ni tip , 8 knh , 10 bit ADC vi cc la chn cc cng vo ring bit vi kh nng lp trnh khuych i , lp trnh timer Watchdog vi b to dao ng bn trong , 1 cng SPI ni tip , ph hp vi chun IEEE 1149.1 , giao din kim tra JTAG , cng s dng truy cp vo ch sa tm h thng trn chip v h tr lp trnh , v 6 phn mm c th la chn ch tit kim in . Ch ri IDLE dng CPU trong khi cho php SRAM , Timer/counter , cng SPI , v cc ngt h thng tip tc vn hnh . Ch tt ngun tit kim dung lng ca thanh ghi nhng n lm ng bng b to dao ng (oscillator ) bn trong , v hiu ha tt c cc chc nng ca chip cho n khi c ngt k tip hoc l reset li phn cng (reset hardware ) . Trong ch tit kim in timer d b vn tip tc chy , iu ny cho php ngi s dng bo dng trong mt thi gian trong khi phn cn li ca thit b ang trong qu trnh ngh ( ng ) sleeping. Kiu gim nhiu ADC dng CPU v tt c cc modul vo ra tr cc timer d b v ADC , lm cc tiu nhiu chuyn mch trong sut qu trnh chuyn i ADC . Trong ch ch Standby b to dao ng thch anh v cng hng ang chy trong khi phn cn li ca thit b ang trong trng thi ng . iu ny cho php rt nhiu cc khi to nhanh c ng thi tiu th in thp . Trong ch ch m rng , c hai b to dao ng chnh v cc timer d b vn tip tc chy Thit b ny c sn xut da trn cng ngh chp nh c cao ca ATMEL . B nh flash ISP trn chip cho php b nh chng trnh c lp trnh li trong h thng thng qua 1 giao din ISP ni tip , bng mt chng trnh lp trnh b nh c nh thng thng hoc bng mt chng trnh khi ng ang chy trong li ca AVR . Chng trnh khi ng c th s dng bt c giao din no ti cc chng trnh ng dng vo trong b nh cc chng trnh ng dng ( Flash ) . Phn mm trong phn vng khi ng ca b nh Flash s tip tc chy trong khi cc ng dng trong phn vng ny c cp nht , cung cp hot ng c trong khi ghi . Bng vic kt hp 1 CPU- cu trc 8 bit RISC vi b nh flash lp trnh h thng trn 1 chip n , Atmega 128 l mt vi s l mnh , n cung cp 1 s linh hot cao v mi trng lm vic c ch cho rt nhiu cc ng dng iu khin nhng . Atmega 128 c h tr vi 1 s thch hp y ca chng trnh v cc cng c pht trin h thng bao gm : trnh bin dch C , cc macro Asemmbler , cc chng trnh chy th v m phng , 1 b m phng mch in , v cc cng c nh gi so snh

S tng thch ca Atmega 128 v Atmega 103 Atmega 128 l mt vi x l c phc tp cao m s u vo ra c tch hp rt nhiu ln n 64 a ch vo ra c d tr sn trong cc lnh ci t . m bo tng thch vi Atmega 103 th tt c cc a ch vo ra hin nay trong Atmega 103 u ging a ch ca Atmega 128 . Tt c cc a ch I/O thm vo th c thm vo trong mt khng gian a ch I/O m rng bt u t $60 n $FF ( trong Atmega 103 th cha trong khng gian ca RAM trong ) . Nhng a ch ny c th c gi bng vic ch s dng cc lnh LD/LDS/LDD v ST/STS/STD , khng phi s dng cc lnh IN hoc OUT . Vic t li cc a ch trong RAM ca Atmega 103 c th vn l mt vn cho ngi s dng . Ngoi ra , s gia tng v s lng cc vecto ngt c th l mt vn nu cc m s dng l a ch tuyt i . gii quyt vn ny , mt s tng thch ca Atmega 103 c th c la chn bi vic lp trnh cho Fuse M103C . Trong ch ny , khng c chc nng no trong khng gian I/O m rng c s dng , v vy RAM trong c t a ch nh ca Atmega 103 . Ngoi ra , cc vecto ngt m rng c g b . Atmega 128 th thch hp 100 % vi Atmega 103 , v c th thay th cho Atmega 103 trn cng mt bo mch in hin hnh . ch ng dng s thay th Atmega 103 bng Atmega 128 m t ci m ngi s dng nn nhn bit s thay th ca Atmega 103 bng Atmega 128 . Kiu tng thch ca Atmega 103 Bng vic lp trnh M130C , Atmega 128 s tng thch vi Atmega 103 RAM , chn I/O v cc vecto ngt c miu t nh di y . Tuy nhin , mt vi c im Atmega 128 th khng c ch trong ch tng thch ny , nhng c im c lit k di y . - Mt USART thay v 2 , ch trong ch d b . Ch c 8 bt c ngha nh nht ca thanh ghi Baud Rate l c ch . - Giao din 2 dy ni tip th khng c h tr . - Cng C ch l cng ra - Cng G ch phc v chc nng xoay chiu ( lun phin ) - Cng F phc v ch nh l mt u vo k thut s thm vo u vo tng t ti b chuyn i ADC - B ti khi ng ( Boot Loader ) khng c h tr - Khng th iu chnh tn s ca b hiu chnh dao ng k RC ( oscillator ) bn trong . - Giao din b nh bn ngoi c th khng gii phng bt c chn a ch cho cng I/O chung , khng phi cu hnh cc ch ch khc nhau n cc khu vc a ch nh bn ngoi . Thm vo , c mt vi im khc bit nh lm nn kh nng tng thch vi Atmega 103 - ch EXTRF v PORF ra trong MCUCSR - kt qu thi gian th khng cn thit cho timer vWatch dog chuyn i thi gian ch

- chn ngt ngoi 3 0 phc v ch cc mc ngt - USART khng c b m FIFO , nhng d liu vn vt qua n sm hn - Nhng bt I/O khng s dng trong Atmega 103 nn c vit l O bo m rng hot ng ging nh Atmega 128 M t ngha cc chn ( Pin descipsions )
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VCC : chn cp ngun GND : Chn ni t Port A (PA7...PA0) : Cng A l mt cng vo ra hai hng 8 bit vi in tr hm bn trong (c la chn cho mi bit ). B m u ra ca cng A c c tnh i xng vi c 2 tn nhit ngun cp . Port B (PB7...PB0) : cng B l mt cng vo ra 2 hng vi in tr hm ( la chn cho mi bit ). B m cng B c tnh i xng vi 2 tn nhit v ngun cp . Port C (PC7...PC0) : cng C l mt cng vo ra 2 hng . B m u ra ca cng C c tnh i xng Port D (PD7...PD0) : cng D tng t nh cng D Port E tng t nh cng E Port F : tr gip ging nh nhng cng vo tong t analog cho b chuyn i A/D . cng F cng l mt cng vo ra 2 hng nu nh b chuyn i A/D khng c s dng . Cc chn ca cng ny c cc tr khng hm oc la chn cho mi bit. Chn TDO l chn c 3 ch tr khi ch TAP xut tn hiu ra c bt. . Cng F cng tr gip chc nng ca giao din JTAG Port G (PG4...PGO) : cng G l mt cng vo ra 5 bit 2 hng vi in tr hm ( c la chn cho tng bit ). B m cng G c tnh i xng vi tn nhit v ngun cp . Cng G cng cung cp nhng tnh nng c bit . Cc chn ca cng G l cc cng c 3 ch khi m iu kin reset c kch hot d l ng h khng chy RESET : u ra reset . cp cho php trn chn ny th di hn di xung ti thiu s pht ra tn hiu reset , cho d ng h khng chy . XTAL1 : u vo b khuych i dao ng v u vo cho cc ng h m bn trong mch in iu khin XTAL2 u ra cho b khuych i dao ng AVCC : l chn ngun p cp cho cng F v cc b chuyn i A/D . N nn l chn ni vi VCC , d l ADC khng c s dng . Nu ADC c s dng , n nn c ni vi chn VCC thng qua 1 b lc thp tn AREF : l chn tham kh cho b chuyn i A/D PEN : l chn c kch hot trnh cho kiu lp trnh ni tip SPI , v cc tn hiu vo c ko ln cao . Bng vic gi chn ny mc thp trong sut qu trnh khi ng li ngun ( Power on Reset ) , thit b ny s nhp vo cng lp trnh ni tip SPI . PEN khng c chc nng g trong qu trnh iu khin .

S duy tr d liu Kt qu ca s thm nh bn ch ra rng tc hng d liu th nh hn 1 PPM trn 20 nm nhit 85 C hoc 100 nm 25 C V cc v d mu : datasheet ny bao gm cc v d code mu theo mt cch ngn gn ch ra cch s dng cc phn khc nhau ca thit b ny. Cc on code mu ny gi thit rng cc phn xc nh tiu ca file th c ci t sn trc khi c bin dch . nhn bit rng khng phi tt c cc trnh bin dch C c cung cp bao gm cc bit c xc nh tiu ca file v cc qu trnh ngt trong C th ph thuc vo trnh bin dch .xem thm trong ti liu ca trnh bin dch C bit thm chi tit. S xc nh cc v tr ca cc thanh ghi vo ra trong bn I/O , IN , OUT , SBIC , CBI, v SBI cc lnh phi c thay th vi cc lnh c cho php truy cp trong phn I/O m rng . Thng thng , LDS v STS c kt hp vi SBRS , SBRC, SBR , CBR.

III .AVR CPU core : Li CPU ca AVR

Gii thiu : Phn ny gii thiu v cu trc chung ca li AVR . Chc nng chnh ca li CPU l m bo thc hin ng chng trnh . CPU v vy phi c th truy cp , qun l b nh , tin hnh tnh ton , iu khin ngoi vi v x l cc ngt Tng quan cu trc : hnh 3 l s khi cu trc ca AVR

c c hiu nng cao nht v kh nng lm vic song song , AVR s dng cu trc Harvard vi s phn chia b nh v cc bus cho chng trnh v d liu . Cc lnh

trong b nh chng trnh th c thc thi vi 1 cp s l lin lnh n . Trong khi lnh c ang c x l th lnh tip theo c np tip t b nh chng trnh . Khi nim ny kch hot lnh thc thi trong mi chu k xung nhp ng h . B nh chng trnh l b nh flash c th lp trnh li c trong h thng . S truy cp nhanh vo file ca thanh ghi th bao gm 32*8 bt thanh ghi a nng vi 1 chu k xung nhp qun l thi gian . iu ny cho php iu khin trong mt chu k n ca n v s l s hc ALU . Thng thng trong hot ng ca ALU , 2 ton hng a ch c xut ra t file thanh ghi , qu trnh iu khin c thc thi v kt qu c lu tr li trong thanh ghi file trong mi chu k xung nhp . 6 trong 32 thanh ghi c th c s dng nh l 3 a ch 16 bit gin tip cho vng d liu a ch - kch hot a ch c hiu lc trong tnh ton . 1 trong nhng con tr a ch ny c th c s dng nh l mt con tr a ch cho vic tm kim cc bng trong b nh chng trnh Flash . Cc thanh ghi chc nng c thm vo l thanh ghi 16 bit thanh ghi X , Y , Z s c miu t sau trong phn ny . n v s l s hc v logic ALU h tr qu trnh iu khin s hc v logic gia cc thanh ghi hoc gia cc i lng khng i v cc thanh ghi . Cc thanh ghi iu khin qu trnh n c th cng c thi hnh trong ALU . Sau mt qu trnh iu khin s hc , trng thi ca cc thanh ghi c cp nht phn nh thng tin v kt qu ca qu trnh iu khin . Dng chng trnh th c cung cp bi cc lnh nhy c iu kin v khng c iu kin v cc lnh gi (call instructions ) , c th l cc a ch trc tip trong ton b khng gian a ch . Hu ht cc lnh ca AVR u c nh dng l 16 bit t n . Mi b nh a ch chng trnh th bao gm 16 hoc 32 bit lnh Khng gian nh Flash c chia ra lm 2 phn ., phn chng trnh khi ng v phn chng trnh ng dng . C 2 phn ny u c cc bit kha ring cho s bo v ghi v c/ghi . Lnh SPM c vit vo trong b nh ng dng Flash phi c thng ch trong khu vc khi ng chng trnh . Trong sut qu trnh ngt v gi cc chng trnh con, s hon tr a ch ca b m chng trnh c lu trong ngn xp (Stack ) . Ngn xp ( stack ) c cch gn hiu qu trong SRAM d liu chung , v hiu qu ca ngn xp ( stack ) th ch b gii hn bi ln ca SRAM v s s dng ca SRAM . Tt c cc chng trnh s dng phi c khi to SP trong chng trnh con reset ( trc khi chng trnh con hoc cc ngt c thc thi ) . Con tr ngn xp ( SP- stack pointer ) l qu trnh truy cp c/ghi trong khng gian a ch I/O. SRAM d liu c th d dng c truy cp n thng qua 5 kiu a ch khc nhau c h tr trong cu trc ca AVR . Khng gian nh trong cu trc ca AVR th u tuyn tnh v u l cc vng nh thng thng . Mt module ngt linh hot c cc thanh ghi iu khin ca n trong khng gian I/O vi 1 bit ngt kch hot chung c thm vo trong thanh ghi trng thi . Tt c cc ngt u c mt vc t phn chia ngt trong cc bng vecto ngt . Cc ngt th c quyn u tin ph hp vi v tr cc vecto ngt ca chng . cc vecto ngt mc thp , cc vecto ngt mc cao c u tin hn . Vng khng gian a ch nh I/O bao gm 64 a ch ci m c th c truy cp trc tip ,hoc cc v tr lu d liu theo cc thanh ghi t $20- $5F ,. Thm vo Atmega 128 cn c thm khng gian a ch I/O m rng t $60 - $FF trong SRAM ni m ch c cc lnh nh ST/STS/STD hoc LD/LDS/LDD c th c s dng .

ALU n v s l s hc v logic Hiu sut cao ca n v s l logic ca AVR iu khin mt cch trc tip vic kt ni vi tt c 32 thanh ghi a nng chung . Trong vng mt chu k xung nhp ng h , qu trnh iu khin s hc gia cc thanh ghi a nng tng hp hoc gia cc thanh ghi v 1 s kin ang c thc thi ngay lc . Qu trnh iu khin ALU th c chia ra lm 3 nhm s hc , logic , v bit chc nng ( bit functions ) . Vi ci t ca cu trc cng cung cp nhng s tr gip a nhim mnh m cho c 2 loi tn hiu/khng tn hiu php nhn v nh dng phn s . xem thm phn ci t lnh c miu t chi tit hn . Thanh ghi trng thi status registers Thanh ghi trng thi bao gm nhng thng tin v kt qu ca tt c cc lnh s hc c thc thi gn nht . Thng tin ny c th c s dng cho s thay i cc dng chng trnh m thc hin cc iu kin ca qu trnh iu khin . Ch rng thanh ghi trng thi c cp nht sau qu trnh iu khin ALU nh l c xc nh trong phn tham kho ci t lnh . iu ny s c g b trong nhiu trng hp khi cn thit phi s dng cc lnh so snh ring , kt qu ca vic ny l ta c cc on m nhanh hn v cht ch hn . Thanh ghi trng thi khng t ng lu khi nhp vo 1 chng trnh con ngt v s khi phc khi phn hi t 1 ngt . iu ny phi c iu khin bi phn mm Thanh ghi trng thi SREG- c xc nh nh l :

Bit 7- I Bit ngt kch hot chung: phi c ci t cho cc ngt c kch hot . S iu khin kch hot cc ngt ring l sau c s dng trong 1 thanh ghi iu khin s phn chia . Nu ton b thanh ghi kch hot ngt b xa , th khng c bt c ngt no c kch hot c lp trong s cc ngt ring r c ci t kch hot . Bt I b xa bng phn cng sau khi 1 ngt gp s c , v c ci t bng lnh RETI kch hot li cc chng trnh con phc v ngt . Bit I cng c th c ci t hoc b xa trong phn mm vi lnh SEI v CLI nh l c m t trong phn tham kho lnh ci t - Bt 6 T : bit sao chp kho d liu Bt lnh copy BLD (bit LoaD ) v BST ( bit STore) s dng Bit T nh l ngun hoc ch n ca bit iu khin . Mt bit t mt thanh ghi trong file thanh ghi c th c sao chp vo trong Bit T bng lnh BST , v mt bit trong T c th c sao chp vo trong mt bit trong thanh ghi ca thanh ghi file bng lnh BLD - Bit 5 H : c bo 1 na ( half carry flag ) Bt c bo 1 na H hin th 1 na s nh trong vi qu trnh tnh ton s hc . bit ny th rt l hu dng trong i s BCD ( xem phn m t ci t lnh bit thm chi tit )
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- Bit 4 S : bt bo hiu ( sign bit ) , S = N+V Bit S th lun lun l ring bit hoc gia 2 c m N v dng trn b sung ca c V . xem phn m t lnh ci t bit thm chi tit . - Bit 3 V : c bo trn b sung ca 2 C bo trn b sung 2 V h tr phn b s hc ca 2 . xem phn m t lnh bit thm chi tit - Bit 2 N : c bo m C bo m N hin th 1 kt qu m trong mt qu trnh tnh ton s hc hoc logic . xem thm phn m t lnh bit thm chi tit . - Bit 1 Z : c khng ( zero ) C khng Z hin th mt kt qu zro trong mt qu trnh tnh ton logic hoc s hc . xem phn m t ci t lnh bit thm chi tit - Bit 0 C c mang : C mang C hin th mt s mang trong 1 qu trnh tnh ton logic v s hc File ng k a nng dng chung ( general purpose register file ) File ng k c ti u ha cho AVR c tng cng nh vic ci t lnh RISC. t c hiu sut v linh hot cn thit , cc gin u vo ra (input/output ) sau y dng h tr file ng k : - 1 ton hng u ra 8 bit v 1 kt qu u vo 8 bit - 2 ton hng u ra 8 bit v 1 kt qu u vo 8 bit - 2 ton hng u ra 8 bit v 1 kt qu u vo 16 bit - 1 ton hng u ra 16 bit v 1 kt qu u vo 16bit Hnh 4 ch ra cu trc ca 32 thanh ghi a nng dng chung trong CPU

Hu ht cc lnh iu khin trong file ng k u c th truy cp trc tip vo tt c thanh ghi v hu ht cc lnh trong chng u thc hin trong mt chu k xung nhp. Nh l c ch ra trong hnh 4 mi thanh ghi cng c gn a ch vng nh d liu , s sp xp trc tip vo trong 32 v tr u tin ca khng gian d liu ngi dng . Mc d thit b vt l nh l c nh v trong SRAM , s t chc vng nh ny cung cp s linh

hot trong truy cp vo cc thanh ghi , Nh l cc con tr thanh ghi X, Y ,Z c th c ci t trong bng ca bt c thanh ghi no trong file Thanh ghi X , thanh ghi Y , thanh ghi Z Thanh ghi R26...R31 c mt vi chc nng c thm vo cc vng nh a nng ca chng . Cc thanh ghi l cc con tr a ch 16 bit cho vic t a ch mt cch gin tip trong vng d liu . C 3 thanh ghi a ch gin tip X, Y , Z th c miu t trong hinh 5

Trong cc kiu t a ch khc nhau c nhiu thanh ghi a ch c cc chc nng nh l s thay th c nh , t ng gia tng ,v t ng gim ( xem thm phn tham kho ci t lnh bit thm chi tit ) Stack pointer : con tr ngn xp Ngn xp th c s dng chnh cho vic lu tr d liu tm thi , cho vic lu tr cc bin a phng v vic lu tr cc a ch phn hi sau khi gi cc chng trnh ngt v cc chng trnh con. Thanh ghi con tr ngn xp lun lun ghi trn nh ca ngn xp (Stack ). Ch rng Ngn xp c ci t nh l pht trin t nhng v tr nh cao hn n cc v tr nh thp hn .iu ny gi rng Ngn xp y cc lnh c rt ngn xung con tr ngn xp Con tr ngn xp ch vo ngn xp d liu SRAM ni m cc chng trnh con v cc ngn xp ngt c t . Khng gian ngn xp trong SRAM phi c xc nh bng chng trnh trc khi bt c lnh gi chng trnh con no c thc thi hoc l cc ngt c kch hot . Con tr ngn xp phi c ci t im trn $60 . Con tr ngn xp b suy gim bng 1 khi d liu b y ln ngn xp khi dng lnh PUSH , v suy gim bng 2 khi s phn hi a ch b y vo trong ngn xp vi s gi cc chng trnh con hoc cc ngt. Con tr ngn xp tng ln bng 1 khi d liu b trn ra khi ngn xp vi lnh POP , v n tng ln 2 khi d liu b trn khi ngn xp vi s phn hi t chng trnh con RET hoc phn hi t ngt RETI Con tr ngn xp ca AVR c ci t nh l 2 thanh ghi 8 bit trong khng gian vo ra I/O . S cc bit thc s c dng th ph thuc vo s ci t trc . Ch rng khng

gian d liu trong mt vi s ci t trc ca cu trc ca AVR th nh n ni m ch cn SPL. Trong trng hp ny , thanh ghi SPH s khng c trnh by

Thanh ghi la chn RAM page Z - RAMPZ

- Bit 7...1 RES : bit d tr ( Reserved Bits ) C cc bt d tr v s lun lun c c l 0 . Khi vit vo cc v tr a ch ny vit nhng bit l khng cho s tng thch vi cc thit b trong tng lai. - Bit 0 RAM PZ0 : extended RAM page Z pointer Thanh ghi RAMPZ thng c s dng chn la ci m 64K RAM page c truy cp bng con tr Z . V Atmega 128 khng h tr nhiu hn 64K ca b nh SRAM , thanh ghi ny ch c s dng la chn ci trang m trong b nh chng trnh c truy cp vo khi m lnh ELMP/SPM c s dng. S ci t khc nhau ca Bit RAMPZ0 cho ta cc hiu ng di y : RAMPZ0 = 0 a ch nh chng trnh l t $0000 - $7FFF ( thp hn 64K bytes ) c truy cp bi ELPM/SPM RAMPZ0 = 1 a ch nh chng trnh t $8000 - $FFFF ( cao hn 64K bytes) th c truy cp biELPM/SPM Ch rng LPM th khng c nh hng bng vic ci t RAMPZ Lnh thc thi nh thi (instruction execution timing) Phn ny miu t khi nim v s qun l truy cp b nh thi cho s thc thi cc lnh . CPU ca AVR c iu khin bng b nh thi trong CPU , n c sinh ra trc tip t ngun pht xung ng h c chn n chip . Khng c s chia b m thi gian bn trong no c s dng . Hnh 6 ch ra cc lnh truy cp ng thi v cc lnh thc thi c kch hot bng cu trc Havard v khi nim file ng k truy cp nhanh . y l khi nim x l lin lnh c bn thu c trn 1 MIPS trn MHz vi kt qu duy nht tng thch vi cho chc nng trn gi thnh , chc nng trn 1 xung nhp v chc nng trn n v ngun in Hnh 6 : lnh truy cp ng thi v lnh thc thi

Hnh 7 ch ra khi nim b nh thi bn trong cho file ng k . Trong mt chu k xung nhp n ca 1qua trnh tnh ton ALU th c 2 thanh ghi c thc thi , v kt qu c lu li trong thanh ghi ch n

Qu trnh iu khin ALU trong mt chu k n Khi ng li v iu khin ngt AVR cung cp a dng cc ngun ngt khc nhau . Cc ngt ny v mi vecto phn chia ngt c mt vecto chng trnh ngt trong vng nh chng trnh . Tt c cc vecto ngt u c gn vi cc bit ring r ci m phi c vit l mc logic 1 cng vi cc bit kch hot ngt chung trong thanh ghi trng thi m kch hot cc ngt . Ph thuc vo gi tr ca b m chng trnh , cc ngt c th t ng v hiu ha khi m bt kha khi ng BLB02 hoc BLB12 c lp trnh . c im ci thin tnh bo mt ca phn mm . xem thm phn b nh chng trnh trang 286 bit thm chi tit . Mc a ch thp nht trong vng nh chng trnh th c t l mc nh nh l RESET v cc vecto ngt . Mt danh sch y ca cc vecto ngt c ch ra trang 60 . Danh sch cng xc nh r cc cp u tin ca cc ngt khc nhau. Cc a ch thp hn cc a ch cao th l cc cp u tin . RESET c mc u tin cao nht v tip theo l INT0 truy vn ngt ngoi . Cc vec to ngt c th c di chuyn bt u cho vng Flash khi ng bng vic ci t bit IVSEL trong thanh ghi iu khin MCU (MCUCR) . Tham kho phn ngt trang 60 bit thm thng tin . Vecto reset c th cng c di chuyn bt u vng Flash khi ng bng cch lp trnh BOOTRST fuse , xem thm phn h tr ti qu trnh khi ng trang 273 Khi mt ngt xut hin , Bit I kch hot ngt chung b xa v tt c cc ngt b v hiu ha . Phn mm ngi s dng c th vit mc logic 1 vo bit I kch hot khi ngt . Tt c cc ngt kch hot c th ngt chng trnh con phc v ngt hin hnh . Bt I t ng ci t khi c mt phn hi t lnh ngt RETI c thc thi . y l c s ca 2 loi ngt . Loi th nht th c khi ng bng mt s kin ci m ci t c bo ngt . Vi nhng ngt ny , b m chng trnh c vecto ha n cc vecto ngt thc s m thc thi vic iu khin cc chng trnh con phc v ngt , v phn cng

xa cc c ngt tng ng . C ngt cng c th c xa bng vic vit mc logic 1 ln bit v tr c ngt b xa . Nu 1 iu kin ngt xut hin trong khi bit kch hot ngt tng ng b xa ,c ngt s ci t v c ghi nh cho n khi qu trnh ngt c kch hot , hoc c ngt b xa bng phn mm . Tng t , nu mt hoc nhiu iu kin ngt xut hin trong khi bit kch hot ngt chung b xa, c bo ngt tng ng s c ci t v ghi nh cho n khi bt kch hot ngt chung c ci t v s thc thi sau bng th t u tin . Loi th 2 ca cc ngt s khi ng ch cn iu kin ngt c a ra . Nhng ngt ny khng cn thit phi c c bo ngt . Nu iu kin ngt bin mt trc khi cc ngt ny c kch hot cc ngt ny s khng khi ng . Khi AVR thot ra t mt ngt , n s lun lun phn hi t chng trnh chnh v thc hin 1 hoc nhiu lnh trc khi bt c ngt ang tr hon no c x l . Ch rng thanh ghi trng thi th khng t ng lu tr khi nhp vo mt chng trnh con phc v ngt hoc c khi phc li khi s phn hi t mt chng trnh con phc v ngt . iu ny phi c iu khin bng phn mm . Khi s dng lnh CLI lm bin mt cc ngt , cc ngt s bin mt ngay lp tc . khng c ngt no s c thc thi sau khi c lnh CLI , d l n xut hin ng thi vi lnh CLI . V d di y ch ra cch ny c th s dng trnh cc ngt trong sut dy ghi thi gian ca EEPROM

Khi vic s dng lnh SEI kch hot cc ngt , cc lnh SEI di y s thc thi trc khi bt c ngt b tr hon nh l c ch trong v d ny

Thi gian p ng cc ngt p ng cc ngt thc thi cho tt c cc ngt ca AVR ti thiu trong 4 chu k xung nhp ng h . Sau 4 xung nhp ng h , vec to a ch chng trnh ca cc chng trnh con phc v ngt c thc thi . Trong sut 4 chu k xung nhp ny , b m chng trnh b y vo trong ngn xp . Vecto ny thng c nhy trong cc chng trnh con phc v ngt , v cc lnh nhy ny to ra 3 chu k xung nhp. Nu 1 ngt xut hin trong sut qu trnh thc thi ca mt lnh nhiu chu k , lnh ny s hon thnh sau trc khi ngt c x l . Nu 1 ngt xut hin khi MCU trong ch ng Sleep mode , thi gian p ng thc thi ngt th c gia tng bng 4 chu k xung nhp . S gia tng ny dn n thm vo thi gian khi ng t qu trnh ng la chn Sleep mode Mt s phn hi t vic iu khin chng trnh con phc v ngt to ra 4 chu k xung nhp . Trong sut 4 chu k xung nhp, b m chng trnh ( 2 Bytes) c trn ra t ngn xp , con tr ngn xp c gia tng bng 2 ,v Bit I trong SREG c ci t .

IV . Cc b nh ca AVR Atmega 128

Phn ny miu t cc b nh khc nhau trong Atmega 128. Cu trc AVR c 2 khng gian nh chnh , b nh d liu v b nh chng trnh . Thm vo , c im ca Atmega 128 l mt b nh EEPROM cho kho lu tr d liu . Tt c 3 vng nh th u di v n nh B nh chng trnh flash co th lp trnh li trong h thng Atmega 128 bao gm 128K bytes b nh chng trnh c th lp trnh li trn chip dng lu tr chng trnh . T khi tt c cc lnh ca AVR c rng l 16 v 32 bit , b nh Flash c t chc nh l 64K*16 . bo mt phn mm , khng gian b nh chng trnh Flash c chia thnh 2 phn , l phn chng trnh khi ng v phn chng trnh ng dng B nh Flash c mt bn lu l trn 10000 chu k ghi xa . B m chng trnh (PC )ca Atmega 128 l 16 bit di , vic t a ch ny cho 64K c nh v trong b nh chng trnh . Hot ng ca khu vc chng trnh khi ng cn c kt hp vi cc bit kha qu trnh khi ng v s bo v phn mm c m t mt cch chi tit trong phn h

tr ti qu trnh khi ng trang 273 v lp trnh b nh trang 286. bo gm nhng m t chi tit v lp trnh cho b nh Flash trong SPI , JTAG , hoc kiu lp trnh song song. Bng hng s c th c gn bn trong khng gian a ch b nh chng trnh( xem thm LPM load program memory v ELPM Extended load program Memory instruction description ) Gin thi gian cho vic ci t lnh v thc thi lnh c gii thiu trong phn lnh thc thi thi gian trang 14 .

Hnh 8 : bn b nh chng trnh

B nh d liu SRAM : SRAM Data Memory Atmega 128 h tr 2 cu hnh khc nhau cho b nh d liu SRAM nh c lit k trong bng 1

Hnh 9 : ch ra cch m b nh SRAM ca Atmega 128 c t chc Atmega 128 l 1 vi x l linh hot vi rt nhiu n v ngoi vi hn nn c th h tr 64 v tr d tr trong m hot ng ca cc lnh IN v OUT . V khng gian a ch I/O m rng t $60 n $FF trong SRAM , ch cc lnh ST/STS/STD v LD/LDS/LDD mi c th c s dng . Khng gian a ch I/O khng th xut ra khi m Atmega 128 trong trng thi tng thch vi Atmega 103 Trong ch thng thng a ch v tr d liu u tin 4352 c hai file ng k , b nh u vo ra I/O v d liu trong SRAM . 32 v tr a ch u tin ca thanh ghi file , tip theo l 64 v tr b nh I/O tiu chun , sau l 160 v tr ca cc vng nh I/O m rng v tip theo l 4096 v tr a ch ca SRAM d liu . Trong ch tng thch vi Atmega 103 , u tin l 4096 v tr a ch vng d liu c hai file ng k , vng nh I/O v SRAM d liu bn trong . u tin l 32 v tr a ch ca file ng k , tip theo l 64 v tr ca vng nh I/O chun , v tip theo l 4000 v tr a ch ca SRAM bn trong . Mt ty chn SRAM d liu bn ngoi na c th c s dng vi Atmega 128 . SRAM ny s chim mt vng trong vung a ch cn li ca khng gian a ch 64K. Vng ny bt u a ch bn di trong SRAM . Thanh ghi file , I/O , I/O m rng v SRAM trong chim cc bit thp nht 4352 bytes ch bnh thng , v chim 4096bytes thp nht trong ch tng thch vi Atmega 103 (I/O m rng khng c cp y ) , v vy khi s dng 64KB(65536 Bytes ) ca b nh ngoi , 61184 Bytes ca b nh ngoi s d trong ch bnh thng , v 61440 Bytes trong ch tng thch vi Atmega 103. xem phn giao din b nh bn ngoi trang 26 thm chi tit Khi s truy cp a ch trong b nh SRAM vt qu v tr b nh d liu bn trong , SRAM d liu bn ngoi c truy cp s dng cc lnh ging nhau v phn truy cp b nh d liu bn trong . Khi cc b nh d liu bn trong c truy cp , cc chn phn tch qu trnh c v ghi (PG0 v PG1) th khng hot ng trong khi tt c truy cp 1 chu k . Qu trnh iu khin SRAM ngoi th c kch hot bng vic ci t cc bit SRE trong thanh ghi MCUCR S truy cp SRAM ngoi to ra 1chu k xung nhp thm vo trn 1byte c so snh vi s truy cp vo SRAM trong . C ngha l cc lnh LD , ST , LDS , STS , LDD , STD , PUSH, v POP to thm 1 chu k xung nhp na . Nu ngn xp c t trong SRAM ngoi, cc ngt , s gi cc chng trnh con , v cc phn hi to ra 3 xung nhp b xung , bi v b m chng trnh 2 bytes b y ln v trn ra , v vic truy cp vo b nh ngoi khng to ra s thun li cho s truy cp b nh pipe-line bn trong .Khi giao din SRAM ngoi c s dng vi trng thi ch ( wait- state ) , s truy cp 1 byte ngoi to ra 2 , 3 , 4 xung nhp thm vo cho 1 , 2 , 3 trng thi ch tng ng . Cc ngt , cc chng trnh con , v phn hi s cn 5 , 7 , 9 xung nhp nhiu hn l c xc nh trong hng dn ci t lnh cho 1 ,2, 3 trng thi ch . Nm kiu t a ch cho b nh d liu bao gm : trc tip , gin tip km thay th , gin tip , gin tip km tin gim bt , v gin tip km post increment . Trong B ghi file , thanh ghi R26 v R31 c c im l thanh ghi con tr a ch gin tip . Cch nh a ch trc tip hng ti khng gian a ch trn vn Cch nh a ch gin tip km theo thay th hng ti 63 v tr a ch t cc i ch c s c a ra bi thanh ghi Y v Z

Khi s dng kiu nh a ch thanh ghi gin tip km theo t ng thay th v post increment , a ch thanh ghi X , Y , Z c gia tng hoc gim bt 32 thanh ghi lm vic a nng chung , 64 thanh ghi I/O v 4096 Bytes ca SRAM d liu ngoi trong Atmega 128 u c truy cp thng qua tt c cc kiu t a ch trn . b ghi file c miu t trong b ghi file a nng dng chung trang 12

Hnh 9 bn b nh d liu

Thi gian truy cp d liu b nh : Data memory Access Times Phn ny miu t khi nim thi gian truy cp ni chung ca s truy cp b nh trong . S truy cp b nh d liu trong SRAM c biu th trong 2 xung cklCPU nh l c miu t trong hnh 10

B nh d liu EEPROM Atmega 128 bao gm 4K bytes ca b nh d liu EEPROM . N c t chc nh l s phn chia khng gian d liu , trong mi bit n c th c c v ghi . B nh EEPROM c bn l trn 100000 chu k ghi xa . Qu trnh truy cp gia EEPROM v CPU c miu t di y , vic xc nh a ch thanh ghi a ch EEPROM , thanh ghi d liu EEPROM , v cc thanh ghi iu khin EEPROM Lp trnh b nh trang 286 bao gm nhng miu t chi tit v lp trnh EEPROM trong SPI , JTAG , hoc kiu lp trnh ng thi . Truy cp c v ghi ca EEPROM Cc thanh ghi qun l vic truy cp EEPROM c qun l trong khng gian I/O . Thi gian truy cp ghi cho EEPROM c a ra trong Bng 2 . chc nng t nh thi , tuy nhin , phn mm ngi dng t d khi byte k tip c ghi . Nu m m ngi dng bao gm cc lnh m c vit vo EEPROM , th mt vi s phng nga phi c a ra . Trong b ngun cung cp c lc k , VCC c kh nng tng hoc gim chm khi bt hoc tt ngun . V nguyn nhn ny nn thit b trong vi chu trnh thi gian chy 1 in p thp hn c xc nh v tn s xung nhp c s dng . Xem thm phn gii thiu s sai hng EEPROM trang 25 bit thm chi tit trnh cc vn c th xy ra trong cc trng hp . m trnh s ngn cn v tnh EEPROM vit , 1 bin php vit xc nh phi c tun theo . Tham kho phn miu t v thanh ghi iu khin EEPROM bit thm chi tit . Khi m EEPROM c c , CPU tm dng trong khong 4 chu k xung nhp trc khi lnh c thc thi Thanh ghi a ch EEPROM EEARH v EEARL

Bit 15...12 Res : bt d tr

y l cc bt v lun lun c c l 0 . Khi vit n cc v tr a ch ny , vit cc bit ny l 0 tng thch vi cc thit b trong tng lai Bt 11...0 EEAR11..0 : a ch EEPROM Thanh ghi a ch EEPROM EEARH v EEARL xc nh cc a ch ca EEPROM trong khng gian 4K bytes EEPROM . Bytes d liu ca EEPROM c nh a ch thuc trong khong gia 0 v 4096. Gi tr ban u ca EEAR th khng c xc nh . Gi tr chnh xc phi c vit trc khi EEPROM c th c truy cp . Thanh ghi d liu EEPROM EEDR

Bt 7...0 EEDR7.0 . d liu EEPROM phc v cho qu trnh ghi EEPROM , thanh ghi EEDR bao gm d liu c vit vo EEPROM cc a ch c a bi thanh ghi EEAR . phc v qu trnh c EEROM , thanh ghi EEDR bao gm cc d liu a ra t EEPROM ti a ch c a ra bi EEAR. Thanh ghi iu khin EEPROM EECR

Bt 7...4 Res : cc bit d tr Cc bit ny l cc bit d tr trong Atmega 128 v s lun lun c c l 0 . Bt 3 EERIE : sn sng kch hot cc ngt EEPROM Vic vit EERIE kch hot mt ngt sn sng ca EEPROM nu bt I ca SREG c ci t . Vit EERIE l 0 v hiu ha ngt . thanh ghi ngt sn sng ca EEPROM sinh ra 1 ngt khng i khi EEWE b xa Bt 2 EEMWE : bt kch hot vit chnh ca EEPROM Bt EEMWE quyt nh c ci t EEWE l 1nguyn nhn gy ra EEPROM c ghi d liu vo. Khi m EEMWE c vit l 1 , vic vit EEWE l 1 trong vng 4 chu k xung nhp s vit d liu vo EEPROM cc a ch c la chn . Nu EEMWE l 0 , vic vit EEWE l 1 s khng c hiu lc . Khi EEMWE c vit l 1 bi phn mm, th phn cng s xa bit v 0 sau 4 chu k xung nhp. Xem thm phn miu t ca bit EEWE cho 1 quy trnh vit vo EEPROM Bit 1- EEWE : Kch hot vic vit EEPROM Tn hiu EEWE kch hot vic ghi vo EEPROM th c phn tch trong EEPROM. Khi a ch v d liu c ci t chnh xc , bit EEWE phi c ci t vit gi tr vo trong EEPROM . Bit EEMWE phi c ci t khi mc logic 1 c vit vo

bit EEWE , theo cch khc th vic vit vo EEPROM khng xy ra . Quy trnh di y nn c tun theo khi ghi vo EEPROM ( th t ca bc 3 v 4 l khng cn thit ) 1. i cho n khi EEWE tr thnh 0 2. i cho n khi bit SPMEN trong thanh ghi SPMCSR tr thnh 0 3. Vit a ch mi ca EEPROM ti EEAR ( la chn ) 4. Vit d liu mi ca EEPROM ti EEDR ( la chn ) 5. Vit mc logic 1 ti bit EEMWE trong khi vit mc logic 0 ti bit EEWE thanh ghi EECR 6. Trong 4 chu k xung nhp sau khi ci t EEMWE , vit mc logic 0 vo EEWE B nh EEPROM khng th b lp trnh trong sut qu trnh m CPU ghi vo trong b nh Flash . Phn mm phi kim tra xem chng trnh trong b nh Flash c hon thin trc khi khi u 1 ln ghi EEPROM . Bc 2 ch thc s cn thit nu nh phn mm bao gm 1 b ti qu trnh khi ng (boot loader ) ang cho php CPU lp trnh vo trong b nh Flash. Nu nh b nh Flash khng bao gi c cp nht bi CPU th bc 2 c th c b qua . xem phn h tr ti qu trnh khi ng trang 273 bit thm chi tit v s lp trnh khi ng Cnh bo : mt s gin on gia bc 5 v bc 6 s lm hng 1 chu k ghi , t khi bit kch hot qu trnh ghi chnh ca EEPROM s b ht thi gian ch . Nu nh 1chng trnh con phc v ngt ang truy cp vo ang c ngt bi mt s truy cp vo EEPROM khc , thanh ghi EEAR v thanh ghi EEDR s b sa i , nguyn nhn ca qu trnh ngt EEPROM b hng . N th c ngh phi c c bo ngt chung c xa trong sut 4 bc cui trnh cc vn trn . Khi thi gian truy cp vit tri qua , bit EEWE b xa bi phn cng . Phn mm ngi dng c th thm d bit ny v i n khi l 0 trc khi vit byte k tip . Khi EEWE c ci t , CPU b dng li trong 2 chu k xung nhp trc khi lnh tip theo c thc thi. Bit 0 EERE : kch hot qu trnh c EEPROM Tn hiu EERE kch hot vic c EEPROM th c qu trnh c phn tch trong EEPROM . Khi a ch chnh xc c ci t trong thanh ghi EEAR , bit EERE phi c vit l mc logic 1 ti b kch hot trong qu trnh c EEPROM . Qu trnh c EEPROM to ra mt lnh , v c truy vn d liu c gi tr ngay lp tc . Khi EEPROM c c, CPU b dng li trong 4 chu k xung nhp trc khi lnh k tip c thc thi Ngi s dng nn thm d bit EEWE trc khi bt u qu trnh c . Nu 1 qu trnh vit ang c tin hnh , n cng khng th c c bi EEPROM , v cng khng thay i thanh ghi EEAR S iu chnh b to dao ng thng c s dng trong qu trnh truy cp EEPROM . Bng 2 lit k cc thi gian chng trinh thng thng cho s truy cp EEPROM t CPU

Cc on code mu di y ch dng cc hm ca C v ASSEMBLY vit vo EEPROM.

Cc v d ny tha nhn rng cc ngt c iu khin ( v d bng cch v hiu ha cc ngt 1 cch chung )v th m khng c ngt no xut hin trong sut qu trnh thc thi cc hm trn . Cc v d ny cng tha nhn rng khng c b ti qu trnh khi ng no b ngn cn trong phn mm . Nu nh on code b ngn cn , th hm vit EEPROM cng phi i trong khi bt c lnh SPM no ang din ra hon thnh

Cc v d mu k tip ch ra cc hm C v assembly dng cho qu trnh c EEPROM . Cc v d ny cng tha nhn rng cc ngt c iu khin v th m khng c ngt no xut hin trong sut qu trnh thc thi ca cc hm trn.

Qu trnh vit trong sut ch ng ngt in (EEPROM Write During Power- down Sleep Mode ) Khi ng nhp vo trong ch ng ngt in trong khi 1 qu trnh vit EEPROM ang hot ng , qu trnh vit EEPROM vn tip tc v s hon thnh trc thi gian s truy cp ghi c chuyn tip . Tuy nhin , khi qu trnh vit c hon thnh , b to dao ng vn tip tc chy , v nh 1 h qu , thit b ny khng truy nhp vo ch ngt ngun mt cch trn vn . V vy n c ngh kim tra li rng qu trnh vit EEPROM c hon thnh trc khi c s truy nhp vo ch ngt ngun . S ngn cn vic sai hng EEPROM Trong sut qu trnh VCC mc thp , d liu ca EEPROM c th b h hng bi v in p ngun cp th qu thp cho CPU v EEPROM lm vic bnh thng . Nhng kt qu ny th ging nh l v phn EEPROM s dng cc bc trong bo mch h thng , v gii php thit k nn c p dng . Mt s h hng d liu ca EEPROM c th b gy ra trong hai trng hp khi m in p qu thp . u tin , mt qu trnh ghi lin tc thng thng ti EEPROM cn c 1 in p cc tiu iu khin ng . Th 2 , bn thn CPU thc hin cc lnh khng ng , nu nh ngun cung cp qu thp .

S h hng d liu ca EEPROM c th d dng trnh c bng cc khuyn co trnh by di y : Gi cho hot ng RESET (low) ca AVR trong sut giai on thiu in p ngun cp . iu ny c th lm c bng vic kch hot b d st p bn trong (BOD) . Nu 1 tn hiu RESET xut hin trong khi 1 qu trnh ghi ang tin hnh , qu trnh ghi s c hon thnh vi iu kin l in p ngun cp ang b thiu ht . B nh vo/ra : I/O Memory Vng nh I/O xc nh trong Atmega 128 th c ch ra trong phn chi tit thanh ghi trang 362 Tt c cc cng vo ra v cc ngoi vi ca Atmega 128 u c t trong vng khng gian nh I/O . Tt c cc v tr I/O c th c truy cp bng lnh LD/LDS/LDD v ST/STS/STD , s chuyn d liu gia 32 thanh ghi a nng lm vic chung v khng gian I/O . Thanh ghi I/O trong phm vi cc cp a ch $00 - $1F u l cc bit c th truy cp trc tip bng vic s dng lnh SBI v CBI . Trong cc thanh ghi , gi tr ca cc bit n c th c kim tra bng cch s dng cc lnh SBIS v SBIC . Tham kho phn ci t lnh bit thm chi tit . Khi s dng I/O xc nh lnh IN v OUT th cc a ch I/O $00 - $3F phi c s dng. Khi vic t a ch thanh ghi cng nh l vng d liu s s dng cc lnh LD v ST , $20 phi c thm vo cc a ch . Atmega 128 l mt vi s l linh hot vi rt nhiu n v ngoi vi cn c h tr trong phm vi 64 v tr d tr trong m hot ng (opcode )cho cc lnh IN v OUT . Cho phn vng nh I/O m rng t $60 - $FF trong SRAM, ch cc lnh ST/STS/STD v LD/LDS/LDD mi c th c s dng . Vng khng gian I/O m rng th c thay th vi cc v tr ca SRAM khi m Atmega 128 trong ch tng thch vi Atmega 103 tng thch vi cc thit b trong tng lai , cc bt d tr nn c vit l 0 nu c truy nhp. Cc a ch I/O d tr khng bao gi nn vit vo Mt vi trng thi ca c bo b xa bng vic vit mc logic 1 ln chng . Ch rng cc lnh CBI v SBI s iu khin tt c cc bit trn thanh ghi I/O, s vit 1 li vo trong bt c c c c no nh l c ci t , do c s xa cc c. Cc lnh CBI v SBI ch lm vic vi cc thanh ghi t $00 n $1F. Cc thanh ghi ngoi vi v cc thanh ghi iu khin ngoi vi th c din gii trong cc phn sau . Giao din b nh ngoi : External Memory Interface Vi tt c cc tnh nng m b nh ngoi cung cp , n th rt ph hp iu khin nh l mt giao din n cc b nh thit b nh l SRAM ngoi v b nh Flash , v cc ngoi vi nh l b hin th LCD , chuyn i A/D , D/A . Cc tnh nng chnh l - Ci t 4 ch ch khc nhau ( bao gm No wait state ) - Khng ph thuc vo vic ci t cc trng thi ch cho cc phn b nh ngoi ( cu hnh cc c ca sector ) - S ca cc bit ring n cc a ch ca cc bit cao c la chn - B gi cc bus trn ng d liu ti s trit tiu cc dng in cc tiu ( la chn)

Tng quan : Overview Khi cc b nh ngoi (XMEM ) c kch hot , khng gian a ch bn ngoi ca SRAM trong tr thnh vic s dng c ch cc chn ring ca b nh ngoi ( xem hnh 1 trang 2 , bng 27 trang 73 v bng 33 trang 77 , bng 45 trang 85 . Cu hnh b nh th c ch ra trong hnh 11 >

Ch : Atmega 128 khng trong ch tng thch vi Atmega 103 : cu hnh b nh A l kh dng ( cu hnh b nh B N/A ) Atmega 128 trong ch tng thch vi Atmega 103 : cu hnh b nh B l kh dng ( cu hnh b nh A N/A) Ch tng thch vi Atmega 103 C hai thanh ghi iu khin b nh ngoi ( XMCRA v XMCRB ) u c t trong khng gian I/O m rng . Trong ch tng thch vi Atmega 103 , cc thanh ghi ny khng c kh dng , v tnh nng ny c la chn bi cc thanh ghi khng kh dng . Thit b ny vn trong ch tng thch vi Atmega 103 , ging nh nhng tnh nng ny khng thot ra trong Atmega 103 . S gii hn trong ch tng thch vi Atmega 103 l - ch c ci t 2 trng thi ch ( wait state ) l kh dng (SRW1n = 0b00 v SRW1n = 0b01) - S ca cc bit m c truy cp n cc a ch byte cao c sa cha . - Phn b nh bn ngoi khng th b phn chia vo trong cc phn nh sector vi s ci t cc trng thi ch khc nhau - Bus keeper th khng kh dng - Cc chn RD , WR v ALE ch l u ra ( cng G trong Atmega 128 )

Vic s dng giao din b nh ngoi : Using the External Memory Interface Giao din bao gm : - AD7:0 nhiu bus a ch thp v bus d liu - A15:8 Bus a ch cao ( c th cu hnh th t ca bit ) - ALE : kch hot a ch then cht - RD : Phn tch s c - WR: phn tch s ghi Bt iu khin ca giao din b nh ngoi c t trong3 thanh ghi , thanh ghi iu khin MCU MCUCR , thanh ghi iu khin b nh ngoi A XMCRA , v thanh ghi iu khin b nh bn ngoi B XMCRB Khi giao din XMEM c kch hot , giao din XMEM s ghi ln qu trnh ci t trong thanh ghi nh hng d liu ci m tng ng vi cc cng ring ti giao din XMEM . bit thm chi tit v phn cng ghi xem phn chc nng lun phin ca cng I/O trang 86 . Giao din XMEM s t ng d mt s truy cp l vo trong hay ra ngoi d c hay khng . Nu nh s truy cp ny l bn ngoi th giao din XMEM s xut a ch ra , d liu , v cc tn hiu iu khin trn cc cng theo hnh 13 ( hnh ny ch ra dng sng thiu trng thi ch vWait state ) . Khi ALE i t cao n thp c 1 gi tr a ch trn AD7:0. ALE thp trong sut qu trnh truyn d liu . Khi giao din XMEM c kch hot cng c 1 s truy cp vo trong s l gy ra hot ng trn a ch , d liu , v cng ALE , nhng s phn tch RD v WR khng b dch chuyn trong sut qu trnh truy nhp vo trong .Khi giao din b nh ngoi b v hiu ha , cc chn bnh thng v vic ci t bit nh hng d liu c s dng . Ch rng khi m giao din XMEM b v hiu ha , khng gian a ch bn di ca b SRAM nh phn bn trong khng c v vo trong SRAM bn trong . Hnh 12 minh ha cch kt ni mt SRAM ngoi vi AVR bng vic s dng 1 bit then ci 8 bit (an octal latch ) ( thng l 74*573 hoc lng tng ng ) ci m trong sut khi cng G mc cao

S cn thit ca Cht a ch ( Address Latch Requirements ) Do qu trnh iu khin ca giao din XRAM c tc cao , s cht a ch phi c la chn cn thn cho cc tn s ca h thng di 8 MHz @4V v 4MHz @ 2.7V . Khi qu trnh iu khin di cc tn s trn , cc series cht 74HC c thng thng tr nn khng ph hp. Giao din b nh ngoi c thit k ph hp vi cc series cht 74HC . Tuy nhin , hu ht cc latch c th c s dng ch cn chng tun theo cc tham s thi gian chnh , cc tham s thi gian chnh cho cc cht a ch l : - D n Q lan truyn tr ( tPD) - Ci t d liu thi gian trc khi G thp ( tSU ) - Thi gian treo d liu ( a ch ) sau khi G thp (TH) Giao din b nh ngoi c thit k m bo thi gian treo a ch nh nht sau khi G c xc nhn mc thp ca th = 5 ns . Tham kho thm tLAXX_LD /tLLAXX_ST trong phn biu b nh d liu ngoi bng 137 n bng 144 trang 328 -330. S lan truyn tr t D n Q ( tPD ) phi c a vo xem xt khi m s tnh ton thi gian

truy cp l cn thit ca cc thnh phn bn ngoi . Thi gian ci t d liu trc khi G thp (tSU ) phi khng c vt qu gi tr a ch ALE thp (tAVLLC ) gi tr PCB m ca s tr hon qu trnh vit ( ph thuc vo dung lng ca ti )

Hnh 12 : SRAM ngoi c kt ni vi AVR S dng li v b gi Bus ( Pull up and Bus keeper ) Cc b dng trn cng AD7:0 c th c hot ng nu thanh ghi cng tng ng c vit l 1 . gim lng tiu th in trong ch Sleep mode , n c khuyn co v hiu ha b dng pull up bng vic vit thanh ghi cng l 0 trc khi ng nhp vo ch ng sleep . Giao din XMEM cng cung cp 1 b gi Bus keeper trn cc ng AD7:0 . B Bus keeper ny c th b v hiu ha v kch hot bng phn mm , nh l c miu t trong phn External Memory Control Register B XMCRB trang 33 . Khi c kch hot , b gi bus keeper s bo m1 cp logic xc nh (0 hoc 1 ) trn bus AD7:0 khi m cc ng ny s khc 3 trng thi bi giao din XMEM B nh thi Cc thit b nh bn ngoi c nhng i hi cc b nh thi khc nhau . p ng cc i hi ny giao din XMEM ca Atmega 128 cung cp 4 trng thi ch khc nhau c ch ra trong bng 4 . N th rt quan trng v c coi nh l bng c tnh ca b nh thi ca cc thit b nh ngoi trc khi qu trnh la chn cc trng thi ch . Cc tham s quan trng nht l thi gian truy cp cho b nh bn ngoi c so snh vi th tc ci t ca Atmega 128 . Thi gian truy cp b nh ngoi c xc nh bng thi gian t lc chip nhn tn hiu n la chn/nh a ch cho n khi d liu ca cc a ch thc ny c iu khin trn Bus . Thi gian truy nhp ny khng th vt qu thi gian t khi xung ALE phi c xc nhn thp cho n khi d liu n nh trong sut 1 qu trnh c lin tc (xem tLLRL + tRLRH tDVRH trong bng 137 144 trang 328- 330 ) . Cc trng thi ch khc nhau c ci t bng phn mm . Nh l mt tnh nng c thm vo , n c th phn chia b nh ngoi thnh 2 phn nh vi s ci t cc trng thi ring . iu ny lm n c kh nng kt ni vi 2 thit b nh khc nhau vi cc yu cu v nh thi khc nhau ging nh giao din XMEM . bit thm chi tit v b nh thi ca giao din XMEM , tham kho bng 137 -144 v hnh 157-160 trong phn b nh thi b nh d liu gn ngoi trang 328

Ch rng giao din XMEM l d b v dng sng trong hnh di y th c lin h vi ng h xung nhp bn trong h thng . lch gia xung nhp trong v xung nhp ngoi (XTAL 1 ) th c bo m ( s khc nhau gia nhit ca cc thit b v ngun cp ) . Kt qu ca vic ny , giao din XMEM khng c thch hp vi qu trnh iu khin d b .

Hnh 13 : chu k xung nhp b nh d liu ngoi thiu ch ch

Miu t thanh ghi XMEM (XMEM register Description ) Thanh ghi iu khin MCU MCUCR ( MCU Control Register )

Bit 7 SRE : kch hot SRAM/XMEM bn ngoi Bng vic vit SRE l 1 kch hot giao din b nh ngoi . Cc chn chc nng AD7:0 , A15:8 , ALE , WR , v RD c kch hot nh l cc chn chc nng lun phin . Bt SRE

ghi ln bt c s ci t chn nh hng trong cc thanh ghi nh hng d liu tng ng. Vic vit SRE l 0 , v hiu ha giao din b nh ngoi v cc chn thng thng v s ci t nh hng d liu c s dng . Bit 6 SRW10 : bit la chn trng thi ch c mt miu t chi tit khng phi trong ch tng thch vi Atmega 103 , xem phn m t chung cho cc bit SRWn bn di (XMCRA miu t ) . Trong ch tng thch vi Atmega 103 , vic vit SRW10 l 1 kch hot trng thi ch v mt chu k xung nhp c thm vo trong sut qu trnh phn tch c /vit nh l c ch ra trong hnh 14 Thanh ghi iu khin b nh ngoi A XMCRA

Bit 7 RES : bit d tr y l mt bit d tr v s lun lun c c l 0 . Khi vic vit vo v tr a ch ny , vit bit ny l 0 tng thch vi cc thit b trong tng lai Bt 6..4 SRL2 , SRL1 , SRL0 : gii hn vng trng thi ch N c th dng cu hnh cc trng thi ch khc nhau cho cc a ch b nh bn ngoi . Khng gian a ch b nh bn ngoi c th c phn chia vo trong 2 khu vc ci m va phn chia cc bit trng thi ch . Cc bit SLR2 , SLR1 , v SLR0 c t l 0 v khng gian a ch b nh bn ngoi nguyn c s l nh l mt khu vc . Khi ton b khng gian a ch ca SRAM c cu hnh nh l mt khu , cc trng thi ch c cu hnh bang cc bit SRW11 v SRW10.

Bit 1 v bit 6 MCUCR SRW11 , SRW10 : cc bit la chn trng thi ch cho cc khu vc cao Cc bit iu khin SRW11 v SRW10 iu khin th t ca cc trng thi ch cho cc khu vc cao hn trong khng gian a ch b nh ngoi , xem bng 4 .

Bit 3..2 SRW01 , SRW00 : bit la chn cc trng thi ch cho cc khu vc thp hn Cc bit SRW01 v SRW00 iu khin th t ca cc trng thi ch cho cc khu vc thp ca khng gian a ch b nh bn ngoi , xem bng 4

Bt 0 Res : bit d tr y l cc bit d tr v s lun lun c c l 0 . Khi c cc v tr a ch ny, vit cc bit ny l 0 tng thch vi cc thit b trong tng lai Thanh ghi iu khin b nh bn ngoi B - XMCRB

Bt 7 XMBK : kch hot bus- keeper b nh bn ngoi Vic vit XMBK l 1 kch hot cc Bus-keeper trn ng AD7:0 . Khi cc Bus keeper c kch hot , n s m bo 1 mc logic xc nh ( 0 hoc 1 )trn AD7:0 khi chung s khc 3 trng thi . Vic vit XMBK l 0 v hiu ha Bus keeper . XMBK th khng iu kin vi SRE , v vy d l giao din XMEM b v hiu ha , bus keeper th vn hot ng ch cn bit XMBK l 1 Bt 6..4 Res : cc bit d tr y l cc bit d tr v s lun lun c c l 0 . Khi c cc v tr a ch ny, vit cc bit ny l 0 tng thch vi cc thit b trong tng lai Bit 2..0 XMM2 , XMM1, XMM0 : b chn mc cao b nh ngoi Khi b nh ngoi c kch hot , tt c cc chn cng C th c mc nh s dng cho cc byte a ch cao . Nu nh khng gian a ch 60KB y th khng cn thit truy cp vo cc b nh ngoi , mt vi hoc tt c , cc chn cng C c th c gii phng cho chc nng cc chn cng thng thng nh l c m t trong bng 5. Nh c miu t trong phn s dng tt c 64KB v tr ca b nh ngoi trang 35 , n c kh nng s dng cc bit XMMn truy cp tt c 64KB v tr ca b nh ngoi

Vic s dng tt c cc v tr ca b nh ngoi nh hn 64KB K t khi b nh ngoi c v bn sau b nh trong nh l c ch ra trong bng11 , b nh ngoi th khng c nh a ch khi vic nh a ch 4352bytes u tin ca khng gian d liu . C th xut hin 4352 bytes a ch u tin ca b nh ngoi th khng c truy cp ( cc a ch ca b nh ngoi l 0x0000 n 0x10FF ) . Tuy nhin , khi kt ni vi 1 b nh ngoi nh hn 64KB, v d nh 32 KB , cc v tr ny th d dng c truy cp 1 cch n gin bng vic nh a ch t cc a ch 0x8000 n 0x90FF . V rng cc bit a ch A15 ca b nh ngoi th khng c kt ni n cc b nh ngoi , cc a ch t0x0000 n 0x90FF s xut hin nh l cc a ch 0x0000 n 0x10FF ca b nh ngoi . Vic nh cc a ch bn trn a ch 0x90FF th khng c khuyn ngh., v rng iu ny s xut hin 1 v tr b nh ngoi ci m sn sng c truy cp bi cc a ch (thp hn ) khc. n cc phn mm ng dng , 32 KB b nh bn ngoi s xut hin nh l 1 khng gian a ch 32 KB t 0x1100 n 0x90FF . iu ny c minh ha trong hnh 17 . Cu hnh b nh B tham kho trong ch tng thch vi Atmega 103 , cu hnh A th khng c ch tng thch . Khi m thit b c ci t trong ch tng thch vi Atmega 103 , cc khng gian a ch bn trong l 4096 bytes . iu ny ko theo 4096 bytes a ch u tin ca b nh ngoi c th b c truy cp cc a ch 0x8000 n 0x8FFF . v phn Cc phn mm ng dng , b nh ngoi 32 KB s xut hin nh l 1 khng gian a ch t 0x1000 n 0x8FFF

S dng tt c 64KB v tr ca b nh ngoi V rng B nh ngoi c v bn sau b nh trong nh l c ch ra trong hnh 11 , ch c 60KB ca b nh ngoi th c s dng 1 cch mc nh (khng gian a ch 0x0000 n 0x10FF c d tr cho b nh trong ) Tuy nhin n c th to u th cho ton b b nh ngoi bng vic giu cc bit a ch cao l 0 . iu ny c th thc hin bng cch s dng cc bit XMMn v iu khin bng phn mm cc bit c gi tr cao nht ca vng a ch . Bng vic ci t cng C xut ra 0x00 , v s gii phng cc bit c gi tr cao nht cho qu trnh iu khin chn cng bnh thng , giao din b nh s l a ch 0x0000 n 0x1FFF . xem on m mu bn di bit thm chi tit

Phi thc hnh mt cch cn thn vic s dng la chn ny nh hu ht cc b nh c che chn theo cc cch khc nhau .

V. Xung nhp h thng v la chn xung nhp

Xung nhp h thng v s phn b ca chng Hnh 18 gii thiu cc xung h thng c bn trong AVR v s phn b ca chng . Tt c cc xung nhp u cn c kch hot ti mt thi im c a ra . gim s suy gim in p ngun , b nh thi v cc modules ang khng c s dng c th c dng bng cch s dng cc ch ng khc nhau nh l c m t trong phn s qun l

ngun v cc ch ng trang 45 b to xung nhp h thng c m t chi tit nh di y :

Xung nhp CPU clkCPU Xung nhp CPU th c nh v ti 1 phn ca h thng c ha hp vi qu trnh iu khin ca li AVR . V d ca nhng module ny l cc file thanh ghi a nng dng chung , thanh ghi trng thi v b nh d liu ang gi trong con tr ngn xp . Vic dng xung nhp CPU s ngn cn li khi qu trnh tnh ton v iu khin chung ang c tin hnh . Xung nhp I/O clkI/O Xung nhp I/O c s dng bi a s cc module I/O , ging nh Timer/Counter , SPI v USART . Xung nhp I/O cng c s dng bi cc module ngt ngoi , nhng ch rng 1 vi ngt ngoi c d bi cc logic d b , s cho php cc ngt nh vy c tm kim cho d cc xung nhp I/O b tm dng . Cng ch rng cc s nhn bit cc a ch trong module TWI c tin hnh mt cch khng ng b khi m clkI/O b tm dng , ang kch hot s thu nhn a ch TWI trong tt c cc ch sleep . Xung nhp Flash clkFLASH Qu trnh iu khin xung nhp Flash ca giao din Flash . Xung nhp Flash th thng hot ng cng lc vi xung nhp CPU .

Xung nhp ca Timer d b - clkASY Xung nhp ca timer d b cho php cc b timer/counter d b c gi nhp 1 cch trc tip t mt b to xung nhp thch anh 32 kHz bn ngoi. Vng xung nhp xc nh ny cho php vic s dng Timer/counter ny nh l 1 b m thi gian thc ngay c khi thit b ny trong ch ng . Xung nhp ADC clkADC ADC c cung cp vi 1 vng xung nhp ring . iu ny cho php qu trnh dng CPU v cc xung nhp I/O m lm gim nhiu sinh ra bi mch in k thut s . N a ra c nhiu kt qu ng n hn trong qu trnh chuyn i ADC Thanh ghi iu khin chia XTAL XDIV Thanh ghi iu khin phn chia XTAL c s dng phn chia tn s xung nhp ca ngun bng 1 s trong khong 2-129 . Tnh nng ny c th c s dng lm gim s st p khi m c s cn thit cho ngun ang tnh ton th thp .

Bt 7 XDIVEN : Kch hot phn chia XTAL Khi bit XDIVEN c vit l 1 , tn s xung nhp ca CPU v tt c cc ngoi vi ( clkI/O , clkADC , clkCPU , clkFLASH ) c phn chia bng vic xc nh cc h s bng vic ci t ca XDIV6 XDIV0 . Bit ny c th c vit trong thi gian thi hnh lm thay i tn s xung nhp thch hp vi ng dng . Bt 6..0 XDIV0 : Bit 6..0 la chn chia XTAL Cc bit ny xc nh h s ca s chia ci m c p dng khi bit XDIVEN c t l 1 . Nu gi tr ca cc bt c k hiu l d , cng thc di y xc nh kt qu tn s xung nhp ca CPU v cc ngoi vi fCLK : fCLK = xung nhp ngun 129 d Gi tr ca cc bit ny c th ch b thay i khi m bit XDIVEN c t l 0 . Khi m XDIVEN c vit l 1 , gi tr ny c vit ng thi vo trong XDIV6 ...XDIV0 c chia theo h s chia . Khi m XDIVEN c ghi l 0 , gi tr ny c vit ng thi vo XDIV6..XDIV0 c loi b . Nh vy b chia chia xung u vo chnh n MCU , tc ca tt c cc ngoi vi c lm gim xung khi m 1 qu trnh chia theo h s c s dng Khi xung nhp h thng b chia , timer/counter 0 c th c ch s dng vi xung nhp khng ng b ny . Tn s ca xung nhp d b ny phi thp hn1/4 ca tn s ca xung nhp ngun khi (scaled down ) . Theo cch khc , cc ngt c th b mt , v s truy cp vo thanh ghi timer/counter 0 c th b hng .

Xung nhp ngun Thit b ny c cc la chn xung nhp ngun di y , c th la chn bng bt cu ch Flash (Flash Fuse ) nh l c ch ra di y . Xung nhp t ngun c la chn nhp vo b pht xung nhp ca AVR , c nh hng n cc module tng thch .

C nhiu s la chn khc nhau cho mi s la chn xung nhp khc nhau c a ra phn di y . Khi m CPU thc dy t ch ngt in hoc ch tit kim in , ngun xung nhp c la chn th c s dng cho thi gian khi ng , bo m s hot ng n nh ca b to dao ng trc khi lnh c bt u . Khi m CPU khi ng t ch Reset cho php 1 khong thi gian tr thm vo ngun tin n cp n nh trc khi bt u qu trnh hot ng bnh thng . B to dao ng Watchdog c dng nh thi cho phn thi gian thc ca thi gian khi ng . S lng ca cc xung nhp ca b dao ng WDT c s dng cho mi khong thi gian ch c ch ra trong bng 7 . Tn s ca b to dao ng watchdog l in p ph thuc nh l c ch ra trong phn cc ch s thng dng trang 333

Ngun to xung mc nh vn chuyn bi CKSEL = 0001 v SUT = 10. S ci t ngun to xung l mc nh v vy b to dao ng RC bn trong vi khong thi gian khi ng l di nht . S ci t mc nh ny bo m rng ngi s dng c th to ra ngun to xung nhp theo mong mun ca h bng cch s dng mt ng dng trong h thng (in-system ) hoc l mt phn mm lp trnh song song . B to dao ng thch anh XTAL1 v XTAL2 l u vo v u ra , tng thch , ca mt b khuych i ngc ci m c th c cu hnh s dng nh l 1 b to dao ng trn chip , nh l c ch ra

trong hnh 19 . Mt bn tinh th thch anh hoc 1 b cng hng gm c th c s dng . Cu ch CKOPT la chn gia 2 kiu khuych i to dao ng khc nhau . Khi m CKOPT c lp trnh , u ra ca b to dao ng s dao ng v 1 dao ng rail-to-rail u ra . Kiu ny th thch hp khi iu khin trong 1 mi trng nhiu nhiu hoc khi m u ra t XTAL2 iu khin 1 b m xung nhp th 2 . Ch ny c mt khong tn s rng. Khi m CKOPT khng c lp trnh b to dao ng c mt bin dao ng u ra nh . iu ny lm gim mc tiu th ca ngun c th c xt n . Ch ny c mt di tn s gii hn v n khng th c s dng iu khin cc b m xung nhp khc . V b cng hng , tn s ti a l 8 MHz vi CKOPT khng c lp trnh v 16 MHz vi CKOPT c lp trnh . C1 v C2 nn lun lun c tnh ton cho c hai ,b to dao ng thch anh v b cng hng . Gi tr tt nht ca t in ph thuc vo b to dao ng thch anh v b cng hng c s dng , ln ca in dung , v nhiu in t ca mi trng . Mt vi ng dn ban u cho s la chn t in s dng vi cc b to dao ng thch anh c a ra trong bng 8 . V b cng hng gm , cc gi tr ca t c a ra bi nh sn xut nn c s dng.

cc b to dao ng c th c iu khin trong 3 ch khc nhau , mi ch th ti u cho mt di tn s xc nh . Cc ch iu khin th c la chn bng cu ch CKSEL3..1 nh l c ch ra trong bng 8

Bng 9

B to dao ng thch anh tn s thp s dng 1 ng h thch anh 32768 kHz nh l b to xung nhp cho thit b th b to dao ng thch anh tn s thp phi c la chn bng vic ci t cc cu ch CKSEL n 1001. B to dao ng thch anh nn c kt ni nh hnh 19 . Bng vic lp trnh cu ch CKOPT , ngi s dng c th kch hot cc t bn trong trn XTAL1 v XTAL2 , nh vy s g b cc t bn ngoi l cn thit . Cc t bn trong c mt gi tr danh nh l 36pF. Khi b to dao ng ny c la chn , thi gian khi ng th c xc nh r bng cu ch SUT nh bng 10

B to dao ng RC bn ngoi nh thi cc ng dng khng nhy , b to dao ng RC c cu hnh nh hnh 20 c th c s dng . Tn s c c lng mt cch i khi bng cng thc f=1/(3RC) . C nn trn 22pF . Bng vic lp trnh cu ch CKOPT , ngi s dng c th kch hot t 36pF bn trong gia XTAL1 v GND . V vy vic g b b t bn ngoi l cn thit . bit thng tin v qu trnh iu khin b to dao ng v chi tit cch chn R , C , tham kho ch ng dng b to dao ng RC bn ngoi .

B to dao ng c th hot ng trong 4 ch khc nhau , mi 1 ch th ti u cho1 khong tn s xc nh . Ch iu khin th c la chn bng cu ch CKSEL3..0 trong bng 11

Khi b to dao ng ny c la chn , thi gian khi ng th c xc nh r bng cu ch SUT nh bng 12

B to dao ng bn trong hiu chnh B to dao ng bn trong hiu chnh cung cp 1 xung nhp n nh 1.0, 2.0 ,4.0 , 8.0 MHz . Tt c cc tn s l gi tr danh nh 5V v 250C . Xung nhp ny c th c la chn nh xung nhp h thng bng cch lp trnh cu ch CKSEL nh trong bng 13 . Nu c chn la , n s hot ng m khng c b phn bn ngoi no . Cu ch CKOPT nn lun lun khng lp trnh khi s dng la chn xung nhp ny . Trong sut qu trnh Reset , phn cng ti cc byte hiu chnh ny cho 1 b to dao ng 1 MHz trong thanh ghi OSCCAL v do t ng hiu chnh b to dao ng RC . 5V , 25 v tn s b to dao ng1.0MHz c la chn , qu trnh hiu chnh ny a ra 1 tn s trong khong 3% ca tn s danh nh . Vic s dng phng php hiu chnh ny nh c miu t trn vWWW.atmel.com l c th t c chnh xc 1% bt c in p , v nhit no . Khi b to dao ng ny c s dng nh l mt xung nhp ca chip , b to dao ng Watchdog s vn c s dng cho Timer Watchdog v cho thi gian ch reset ( Reset Time-

out ) . bit thm thng tin chi tit v gi tr hiu chnh tin lp trnh , xem phn calibration Byte trang 289

Khi m b to dao ng c la chn , thi gian khi ng c xc nh r bng cu SUT nh bng 14 . XTAL1 v XTAL2 nn c cho php khng kt ni .

Thanh ghi hiu chnh b to dao ng OSCCAL

Ch : thanh ghi OSCCAL th khng kh dng trong ch tng thch vi Atmega103 Bt 7..0 CAL7..0 : gi tr iu chnh ca b to dao ng Vic vit byte hiu chnh vo a ch ny s hon thin b to dao ng trong g b tin trnh bin thin khi tn s b to dao ng Oscillator . Trong sut qu trnh Reset , 1 gi tr hiu chnh 1 MHz ci m c nh v trong dng k hiu byte cao ( a ch 0x00 ) th c ti t ng vo trong thanh ghi OSCCAL . Nu b to dao ng bn trong c s dng ti cc tn s khc , gi tr hiu chnh phi c ti 1 cch th cng bng tay . iu ny c th c thc hin trc tin bng vic c cc dng tn hiu bi 1 lp trnh vin , v sau lu cc gi tr hiu chnh trong b nh Flash v EEPROM . Sau cc gi tr ny c th c c bng phn mm v c ti vo trong thanh ghi OSCCAL . Khi OSCCAL l khng , tn s c ch thp nht c chn . Vic vit cc gi tr khng phi bng khng vo thanh ghi ny s lm tng tn s ca ca b to dao ng bn trong . Vic vit $FF vo thanh ghi s a ra tn s kh dng cao nht . B to dao ng c hiu chnh th c s dng trong thi gian truy cp b nh Flash v EEPROM . Nu EEPROM v Flash c ghi , khng c iu chnh ln hn 10% trn tn s danh nh . Ni cch khc , s ghi EEPROM v Flash c th b hng . Ch rng b to dao ng nhm mc ch iu chnh 1.0 , 2.0 , 4.0 , hoc 8.0 MHz . Vic iu chnh sang cc gi tr khc th khng c bo m , nh l c biu din bng 15

Xung nhp bn ngoi iu khin cc thit b t mt ngun to xung nhp bn ngoi , XTAL1 nn c iu khin nh c ch ra trong hnh 21 . chy thit b ny trn 1 xung nhp ngoi , cu ch CKSEL phi c lp trnh l 0000 . Bng vic lp trnh cu ch CKOPT , ngi s dng c th kch hot 1 b t 36pF bn trong gia XTAL1 v GND

Khi m b to dao ng c la chn , thi gian khi ng c xc nh r bng cu SUT nh bng 16 .

Khi p dng 1 xung nhp bn ngoi , cn thit trnh cc thay i t ngt trong qu trnh p dng tn s xung nhp m bo hot ng n nh ca MCU . Mt s thay i tn s ln hn 2% t 1 chu k xung nhp n xung k tip c th dn n cc trng thi khng th tin on trc . iu ny l cn thit m bo rng MCU c gi ch Reset trong sut qu trnh thay i trong tn s xung nhp . B to dao ng Timer/Counter Vi iu khin AVR vi cc chn ca b to dao ng Timer/Counter (TOSC1 v TOSC2) , b dao ng thch anh c ni trc tip gia cc chn . Khng c cc t ngoi no l cn thit . B to dao ng th ti u cho vic s dng vi b to dao ng theo di thch anh 32.768kHz . Vic p dng 1 ngun xung nhp ngoi n TOSC1 th khng c khuyn co .

Ch : b dao ng Timer/Counter s dng b dao ng thch anh ging nh b dao ng tn s thp v cc t bn trong c cng cc gi tr danh nh l 36pF

VI . Qun l ngun in v cc ch sleep

Ch ch sleep kch hot chng trnh ng dng tt cc module khng s dng trong MCU , so vy tit kim c ngun in . AVR cung cp nhiu ch sleep cho php ngi dng iu chnh s tn hao ngun in p ng i hi ca cc chng trnh ng dng . truy nhp vo bt c ch no trong s 6 ch ch , bit SE trong thanh ghi MCUCR phi c ghi vi bin logic l 1 v 1 lnh SLEEP phi c thc thi . Cc bit SM2 , SM1 , v SM0 trong thanh ghi MCUCR la chn ch ch (Idle , gim nhiu ADC , tt ngun , tit kim in , ch , hoc ch ch m rng ) s c kch hot bng lnh SLEEP . xem bng 17 bit thm chi tit . Nu mt ngt kch hot xut hin trong khi MCU ang trong ch ch , MCU c nh thc. MCU sau c tm dng trong 4 chu k xung nhp trong thi gian khi ng c thm vo , n thc thi chng trnh con phc v ngt , v khi phc li qu trnh thc thi t cc lnh k tip lnh SLEEP . Thnh phn ca thanh ghi file v SRAM th khng b thay i khi m thit b c nh thc t ch ch . Nu nh tn hiu reset xut hin trong sut ch ch , MCU c nh thc v c thc thi t cc vecto Reset . Hnh 18 trn trang 36 gii thiu cc xung nhp h thng khc nhau trong Atmega 128 , v s phn b ca chng . Hnh ny cng rt hu dng trong vic la chn 1 ch ch thch hp. Thanh ghi iu khin MCU Thanh ghi iu khin MCU bao gm cc bit iu khin cho s qun l ngun in

Bit 5 SE : kch hot ch ch Bt SE phi c ghi mc logic 1 truy nhp vo MCU trong ch Ch khi m lnh SLEEP c thc thi . trnh vic truy nhp vo MCU trong ch ch tr phi n l 1 b lp trnh a nng , khuyn ngh vit bit kch hot ch Ch SE l 1 trc khi qu trnh thc hin lnh SLEEP v xa n ngay lp tc khi thc dy Bit 4..2 SM2..0 : Bit 2 ,1 ,0 la chn ch ch Cc bit ny la chn gia 6 trng thi kh dng nh l c ch ra trong bng 17

Idle mode Khi m cc bit SM2..0 c vit l 000 , lnh ng lm cho MCU truy nhp vo ch Idle , vic dng CPU nhng cho php SPI , USART , b so snh tng t , chuyn i ADC giao din 2 dy ni tip , Timer/Counter , Watchdog , v cc ngt h thng tip tc hot ng . Ch ng ny c bn dng clkCPU v clkFLASH trong khi cho php cc xung nhp khc chy . Ch Idle kch hot MCU thc dy t cc b ngt khi ng bn ngoi th tt nh l 1 b phn bn trong ging nh timer trn v cc ngt hon thnh qu trnh chuyn i USART .Nu n thc dy t cc ngt ca b so snh tng t Analog th khng cn thit , b so snh Analog c th tt ngun bng cch ci t cc bit ACD trong b iu khin so snh analog v thanh ghi trng thi ASCR . N s gim nhu cu dng in trong ch Idle . Nu ADC c kch hot , 1 qu trnh chuyn i bt u t ngkhi m ch ny c truy nhp. Ch gim nhiu ADC Khi m bit SM2..0 c t l001 , lnh SLEEP lm cho MCU truy nhp vo ch gim nhiu ADC , vic dng CPU nhng cho php ADC ,cc ngt ngoi , b theo di a ch giao din 2 dy ni tip , Timer/Counter 0 v Watchdog tip tc hot ng ( nu c kch hot). Ch ng ny c bn dng clkI/O , clkCPU v clkFLASH trong khi cho php cc xung nhp khc chy . iu ny ci to mi trng nhiu cho ADC , v lm cho chnh xc ca cc php o cao hn . Nu nh b chuyn i ADC c kch hot th , mt s chuyn i bt u t ng khi m ch ny c truy nhp . Mt phn ngt b sung ca b chuyn i ADC , ch c 1Reset ngoi , 1Reset Watchdog , 1 Reset tt ngun ,1 a ch giao din 2 dy ni tip tng ng vi cc ngt , 1ngt Timer/Counter0 1 SPM/EEPROM sn sng ngt , 1 cp ngt bn ngoi trn INT7:4 , hoc 1 ngt ngoi trn INT3:0 c th nh thc MCU t ch gim nhiu ADC Ch ngt ngun

Khi m cc bit SM2..0 c vit l 010, lnh SLEEP lm cho MCU truy nhp vo ch Tt ngun Power down . Trong ch ny , b to dao ng bn ngoi b dng li , trong khi cc ngt ngoi , ng h a ch giao din 2 dy ni tip , v 1 Watchdog vn tip tc hot ng (nu c kch hot ) . Ch c 1 Reset ngoi , 1 Reset Watchdog , 1 Reset Brown-out , 1 ngt tng ng a ch giao din 2 dy ni tip , 1 cp ngt ngoi trn INT7:4 , hoc 1 ngt ngoi trn INT3:0 c th nh thc MCU. Ch ng ny dng 1 cch c bn tt c cc ngun pht xung nhp , ch cho php cc module d b hot ng Ch rng nu 1 ngt khi ng cp c s dng cho vic nh thc t ch ngt ngun Power-down , s thay i cp phi c gi trong vi giai on nh thc MCU . Tham kho cc ngt ngoi trong trang90 bit thm chi tit . Khi s nh thc t ch ngt ngun Power-down , c 1 s chm tr t trng thi nh thc xut hin cho n khi s nh thc tr nn c hiu lc . iu ny cho php b nh thi khi ng v tr nn n nh sau khi hon thnh qu trnh dng li. Chu k nh thc c nh ngha bi cc cu ch CKSEL ging nhau m xc nh chu k Reset Time-out , nh c miu t trong Clock Sourse trang 37 Ch tit kim in Power-save Khi m cc bit SM2..0 c vit l 011 , lnh SLEEP lm cho MCU ng nhp vo ch tit kim in Power save . Ch ny ging vi ch ngt ngun Power-down , vi 1 im khc sau : Nu Timer/Counter 0 b kha 1 cch khng ng b , v d Bt AS0 trong thanh ghi ASSR c ci t , Timer/Counter0 s chy trong sut qu trnh ng. Thit b ny c th c nh thc t 1 s trn Timer hoc 1 s kin so snh u ra t Timer/Counter0 nu 1 bt kch hot ngt Timer/Counter tng ng c ci t trong TIMSK , v cc bt kch hot ngt chung trong thanh ghi SREG c ci t Nu Timer d b khng b kha d b , ch ngt ngun Power-down c khuyn co thay th cho ch tit kim in PoWer save bi v thnh phn ca cc thanh ghi trong Timer d b nn c coi nh l khng xc nh sau khi nh thc trong ch tit kim in nu AS0 l 0. Ch ng ny dng c bn tt c cc b pht xung nhp tr clkASY ,s cho php hot ng ch trong cc module d b , bao gm cc Timer/Counter 0 nu b kha d b . Ch ch Standby Khi m cc bit SM2..0 c t l 110 v xung nhp ca cc b to dao ng thach anh v b cng hng bn ngoi c la chn , lnh SLEEP lm cho MCU ng nhp vo ch ch Stand by . Ch ny tng t nh ch ngt ngun Power-down vi ngoi l l cc b pht dao ng Oscillator c gi trong qu trnh chy . T ch ch Standby , thit b c nh thc trong 6 chu k xung nhp ng h Ch ch m rng Khi m cc bit SM2..0 c t l 111 v 1 xung nhp ca b to dao ng thch anh/b cng hng c la chn , lnh SLEEP lm cho MCU truy nhp vo ch ch

m rng. Ch ny th ging nh ch tit kim in vi 1 ngoi l l b to dao ng th c gi trong khi ang chy . T ch ch m rng Extended Standby , cc thit b ny c nh thc trong 6 chu k xung nhp.

S ti thiu ha tn hao cng sut ngun C rt nhiu yu t phi xem xt khi c gng lm cc tiu tn hao cng sut ngun trong 1 h thng c iu khin bi AVR . Ni chung ,cc ch ng Sleep nn c s dng ti a c th ,v ch ch nn c la chn v vy mt vi chc nng ca thit b ang hot ng . Tt c cc chc nng khng cn thit th nn b v hiu ha . c bit , cc module di y c th cn s xem xt c bit khi c gng t c s tn hao ngun thp nht c th B chuyn i t Analog sang Digital Nu c kch hot , b chuyn i ADC s c kch hot trong cc ch ng Sleep . tit kim ngun , b ADC nn c v hiu ha trc khi truy nhp vo bt c ch ng Sleep no . Khi b ADC c tt v bt tr li , s chuyn i tip theo s l 1 s chuyn i m rng . Tham kho phn b chuyn i t tng t sang s trang 230 bit thm chi tit hot ng ca ADC . B so snh tng t Khi truy nhp vo ch Idle , b so snh tng t nn c v hiu ha nu c s dng . Khi truy nhp vo ch gim nhiu ADC , b so snh Analog nn c v hiu ha . Trong cc ch ng khc , b so snh Analog b v hiu ha 1 cch t ng . Tuy nhin , nu b so snh Analog c ci t s dng nh l mt in th trong tham chiu nh l u vo , b so snh Analog nn c v hiu ha trong tt c cc ch ng . Ni cch

khc , in p trong tham chiu s c kch hot , ph thuc vo ch ng . Tham kho b so snh Analog trang 227 bit thm chi tit v cch cu hnh b so snh Analog B d s yu ngun Brown-out Nu b d Brown-out l khng cn thit trong ng dng , module nn c tt . Nu b d Brown-out c kch hot bng cu ch BODEN , n s c kch hot trong tt c cc trong tt c cc ch ng , v do , lun lun tiu hao ngun . Trong cc ch ng su hn ( deeper sleep ) , iu ny s ng gp ng k vo tng tn hao cng sut trong mch. Tham kho thm phn Brown-out Detector bit thm chi tit v cch cu hnh b d s yu ngun in p chun bn trong ( Internal Voltage Reference ) in p chun bn trong s c kch hot khi cn bi B d s yu ngun, b so snh tng t , v b chuyn i ADC . Nu cc module ny b v hiu ha nh l c m t trong phn trn , in p tham kho (Internal Voltage Reference ) s b v hiu ha v n s lm tn hao ngun . Khi c bt tr li , ngi s dng phi cho php truy xut khi ng trc khi u ra c s dng . Nu s truy xut ny b gi li trong ch ng th u ra c th c s dng ngay lp tc . Tham kho thm phn Internal Voltage Reference trang 54 bit thm chi tit v thi gian khi ng Timer Watchdog Nu timer watchdog khng cn thit trong chng trnh ng dng th module ny nn c tt . Nu nh Timer watchdog c kch hot, n s c kch hot trong tt c cc ch ng , v do n lun lun tiu hao cng sut ngun , . Trong cc ch ng su hn , iu ny s gp phn ng k vo tng tn hao ca mch in . Tham kho phn Timer watchdog trang 55 bit thm chi tit v cch cu hnh Timer watchdog. Cc chn cng Khi truy nhp vo 1 ch ng , tt c cc chn cng nn c cu hnh ti thiu ha cng sut s dng . iu quan trng nht l sau bo m rng khng c chn no iu khin cc ti thun tr . Trong cc ch ng khi c 2 xung nhp I/O (clkI/O) v xung nhp ADC (clkADC) b dng li th b m u vo ca thit b s b v hiu ha . iu ny m bo rng khng c cng sut ngun b tiu hao bi u vo logic khi khng cn thit. Trong mt vi trng hp, cng vo logic l cn thit cho vic d tm iu kin thc dy (wake-up conditions) v sau n s c kch hot li . Tham kho thm phn u vo s v cc ch ng trang70 bit thm chi tit v cc chn no c kch hot . Nu b m u ra c kch hot v cc tn hiu u vo c g b di ng (floating) hoc c 1 cp tn hiu tng t ng vo chn VCC/2 , th b m u vo s s dng ngun tha . Giao din JTAG v h thng d li trn chip

Nu nh h thng d li trn chip c kch hot bng cu ch OCDEN v chip truy nhp vo ch ngt ngun (Power down) hoc ch ng tit kim in , ngun pht xung nhp chnh cn li c kch hot . Trong cc ch ng khc , iu ny s ng gp ng k vo tng hao ht dng in . C 3 cch khc nhau trnh iu ny : - v hiu ha Cu ch OCDEN - V hiu ha cu ch JTAGEN - Vit 1 vo bit JTD trong thanh ghi MCUCSR Chn TDO th c ri thay i khi m giao din JTAG c kch hot trong khi b iu khin JTAG TAP ang khng chuyn d liu . Nu phn cng c kt ni vi chn TDO khng dng li mt mc logic , s tn hao cng sut ngun s tng ln . Ch rng chn TDI cho thit b tip theo trong 1 chui qut bao gm 1 s dng li trnh cc vn ny . Vic vit bit JTD trong thanh ghi MCUCSR l 1 hoc di chuyn cu ch JTAG khng c lp trnh v hiu ha giao din JTAG

VII . iu khin h thng v Reset ( System Control and Reset )

Qu trnh Reset ca AVR Trong sut qu trnh Reset , tt c cc thanh ghi I/O c ci t n cc gi tr khi u ca chng , v chng trnh bt u thc thi t cc vcto Reset ca chng . Cc lnh c t trong Vecto Reset phi l mt JMP bc nhy hon ton ch dn n cc chng trnh con iu khin qu trnh Reset . Nu nh chng trnh khng bao gi kch hot mt ngun ngt , vc t ngt khng c s dng , v on m chng trnh bnh thng c th c t ti cc v tr khc nhau . y cng l trng hp nu nh vecto Reset ang trong khu vc ng dng trong khi cc vecto ngt ang trong khu vc khi ng (Boot Section) hoc vice versa . Mch in hnh 22 ch ra mc logic Reset . bng 19 xc nh cc tham s in ca mch reset Cc cng I/O ca AVR th reset ngay lp tc v trng thi ban u ca chng khi m ngun reset tin hnh hot ng . Khng cn thit bt c ngun pht xung no chy Sau khi ngun Reset va dng hot ng , mt b m tr c gi ra , ko di Reset bn trong . iu ny cho php ngun hng ti cp n nh trc khi hot ng c bt u . Chu k nh gi ca b m tr c xc nh bng ngi s dng thng qua cc cu ch CKSEL . Cc la chn khc cho cc chu k tr c gii thiu trong clock Sourse trang 37 Cc ngun Reset Atmega 128 c 5 ngun Reset : - Reset bt ngun (Power On Reset). MCU th Reset khi m in p ngun cp thp hn ngng Reset bt ngun (Power On Reset) - Reset ngoi . MCU th Reset khi 1 mc thp c a ra trn chn RESET di hn di xung ti thiu

- Reset Watchdog . MCU th Reset khi m chu k Timer watchdog ht hn (expires ) v watchdog c kch hot - Reset Brown-out .MCU s reset khi in p ngun cp VCC di ngng Reset yu in p Brown-out (VBOT) v b d yu in p (Brown-out Detector ) c kch hot - Reset JTAG AVR . MCU th Reset ch cn c 1 mc logic 1 trn thanh ghi Reset , 1 trong chui qut ca h thng JTAG . Tham kho phn IEEE 1149.1 (JTAG) Boundary scan trang 252 thm chi tit

Reset Power on 1 xung reset bt ngun (POR) (Reset Power on) s c pht ra bi mch d trn chip . Cp pht hin c nh ngha bng 19 . Xung POR c kch hot bt c uVCC cp pht hin thp . Mt mch POR c th c s dng khi ng Reset Start-up , nh l pht hin 1 s hng hc in p ngun cp . Mt mch Reset bt ngun (Reset Power on) (POR) bo m rng cc thit b c reset t lc bt ngun . Khong ngng ca in p Reset bt ngun c a ra trong b m tr , ci m xc nh khong thi gian bao lu thit b c gi trong ch RESET sau khi m VCC tng ln . Tn hiu Reset c kch hot tr li , m khng c bt c tr no , khi m VCC gim di mc pht hin (detection level )

Reset ngoi ( External Reset ) Mt tn hiu Reset ngoi c pht ra bi 1 mc thp trong chn Reset . Xung Reset th di hn rng xung cc tiu (xem bng 19 ) s pht ra tn hiu Reset d l b nh thi khng hot ng . Cc xung ngn hn th khng bo m pht ra tn hiu Reset . Khi tn hiu t tin dn n ngng in p ngng Reset VRST trn sn dng ca n , b m tr khi ng MCU sau khi chu k thi gian ch tTOUT va ht hn .

S d yu in p Atmega 128 c mt mch d yu in p trn chip theo di mc VCC trong sut qu trnh hot ng bng vic so snh n vi mc khi ng . Mc khi ng cho BOD c th c la chn bi cu ch BODLEVEL l 2,7 V (BODLEVEL khng c lp trnh ) hoc 4.0V nu BODLEVEL c lp trnh ) . Cp khi ng s c 1 tr bo m u c lp ca b d in p thp . tr trn cp d nn c din dch nh l VBOT+ = VBOT + VHYST/2 va VBOT- = VBOT VHYST/2 Mch BOT c th c kch hot hoc v hiu ha bng cu ch BODEN . Khi m cu ch BOD c kch hot ( BODEN c lp trnh ) , v VCC gim v gi tr bn di mc khi ng (VBOT- trong hnh 26 ) , Reset yu in p ngay lp tc c hot ng . Khi m VCC tng trn cp khi ng (VBOT+ trong hnh 26 ) , b m thi gian tr khi ng MCU sau chu k thi gian ch tTOUT va ht hn

Mch BOD s ch d 1 s st gim in p VCC nu nh in p di cp khi ng lu hn tBOD c a ra trong bng 19

Reset watchdog Khi watchdog ht thi gian ch , n s pht ra 1 xung Reset ngn ca 1 khong thi gian 1 chu k xung nhp CK.. Trn sn xung ca xung ny thi gian tr bt u vic m chu k thi gian ch tTOUT . Tham kho trang 55 bit thm chi tit v hot ng ca Timer watchdog

Thanh ghi trng thi v iu khin MCU MCUCSR Thanh ghi trng thi v iu khin MCU cung cp thng tin v ngun xung Reset no l nguyn nhn ca mt tn hiu Reset

Ch rng ch EXTRF v PORF l kh dng trong ch tng thch vi Atmega 103 Bit 4 JTRF : c Reset JTAG Bit ny c ci t nu 1 tn hiu reset ang b gy ra bi mt mc logic1 trn thanh ghi Reset JTAG c la chn bi lnh JTAG AVR_RESET . Bit ny c Reset bng 1 tn hiu Reset bt ngun ( power on ) , hoc bng vic vit mc logic 0 ln c

Bit 3 WDRF : c reset Watchdog Bit ny c ci t nu tn hiu Reset Watchdog xut hin . Bit ny c Reset bi1 tn hiu Reset bt ngun (power on) , hoc vit mc logic 0 ln c Bit 2 BORF c Reset yu in p Brown-out Bit ny c reset nu 1 tn hiu reset Brown-out xut hin . Bit ny c Reset bi1 tn hiu Reset bt ngun (power on) , hoc vit mc logic 0 ln c Bit 1 EXTRF : c Reset ngoi Bit ny c ci t nu 1 tn hiu reset ngoi xut hin . Bit ny c Reset bi1 tn hiu Reset bt ngun (power on) , hoc vit mc logic 0 ln c Bit 0 PORF : c Reset bt ngun (Power-on ) Bit ny c ci t nu tn hiu Reset Power-on xut hin . bit ny c reset ch bng vic vit mc logic 0 ln c hiu cch s dng ca cc c Reset vi 1 iu kin Reset ging nhau , ngi s dng nn c v sau reset thanh ghi MCUCSR d dng trong lp trnh . Nu nh thanh ghi b xa trc 1 tn hiu reset khc xut hin , ngun ca tn hiu reset c th c tm thy bng vic kho st cc c reset S tham kho in p bn trong Atmega 128 c 1 vng tham kho bn trong (internal bandgap reference ) . im chun ny c s dng cho s d yu in p (Brown-out Detection) , v n c th c s dng nh l 1 u vo n b so snh tng t hoc b chuyn i ADC . Mc chun 2.56 V n b chuyn i ADC c sinh ra t Vng tham kho bn trong (internal bandgap reference) Tn hiu kch hot in p tham kho v thi gian khi ng ( Voltage Reference Enable Signals and Start-up Time ) Chun in p c 1 thi gian khi ng ci m c th nh hng n phng php n nn c s dng . Thi gian khi ng c a ra trong bng 20 . tit kim in , in p chun th khng lun lun c bt . in p chun th c bt trong sut cc trng hp di y : - Khi m BOD c kch hot ( bng cch lp trnh cu ch BODEN ) - Khi m vng in p chun c kt ni ti b so snh analog ( bng vic ci t bit ACBG trong thanh ghi ACSR ) - Khi m b chuyn i ADC c kch hot Nh vy , khi m BOD khng c kch hot , sau khi ci t bit ACBG hoc kch hot ADC , ngi s dng phi lun lun cho php mc chun (reference ) khi ng trc khi u ra t b so snh tng t hoc b chuyn i ADC c s dng . gim tn hao cng sut trong ch tt ngun , ngi s dng c th trnh 3 iu kin bn di m bo rng mc chun c tt trc khi truy nhp vo ch tt ngun Power- down

Timer watchdog Timer watchdog th b kha t 1 b to dao ng trn chip ring bit ci m chy 1 MHz . y l gi tr in hnh ti VCC = 5V . Xem d liu m t c tnh cho cc gi tr in hnh cc mc VCC khc nhau . Bng vic iu khin b m gp trc ca Timer watchdog , khong Reset watchdog c th c iu chnh nh c ch ra trong bng 22 trang 57 . Bit WDR Watchdog Reset hng dn reset Timer watchdog . Timer watchdog cng c reset khi m n b v hiu ha v khi 1 tn hiu reset chip xut hin. 8 chu k xung nhp khc nhau c th c la chn xc nh chu k reset . Nu chu k reset ht hn m khng c tn hiu Reset watchdog khc , Atmega 128 reset v thc thi t vecto reset . V chi tit b nh thi trn Reset watchdog , tham kho trang 54 ngn cn s v hiu ha v tnh ca watchdog hoc v tnh thay i chu k time-out ,3 cp an ton khc nhau c la chn bng cu ch M103C v WDTON c ch ra trong bng 21 . Mc an ton 0 tng ng ci t trong Atmega 103 . Khng c hn ch no trong vic kch hot WDT trong bt c cp an ton no . Tham kho timed Sequences for Changing the Configuration of the watchdog Timer trang 58 bit thm chi tit

Thanh ghi iu khin Timer watchdog WDTCR

Bit 7..5 Res : cc bit d tr Cc bit ny l cc bit d tr trong Atmega 128 v lun lun c c l 0 . Bit 4 WDCE : kch hot thay i watchdog Bit ny phi c ci t khi m bit WDE c ghi mc logic 0 . Ni cch khc , watchdog s khng b v hiu ha . mi ln vit l 1 , phn cng s xa bit ny sau 4 chu k xung nhp. Tham kho phn miu t ca bit WDE cho v th tc v hiu ha 1 watchdog .Trong cc cp an ton 1 v 2 bit ny cng phi c ci t khi m s thay i cc bit ca b m gp trc (prescaler ) . Xem thm phn timed Sequences for Changing the Configuration of the watchdog Timer) trang 58 bit thm chi tit Bit 3 WDE : kch hot watchdog Khi m WDE c vit l 1, Timer watchdog c kch hot , v nu WDE c vit mc logic 0 , th cc chc nng ca Timer watchdog b v hiu ha . WDE c th ch b xa nu nh WDCE c mc logic l 1 . v hiu ha 1 Timer watchdog c kch hot , cc quy trnh di y phi c tun theo 1. trong s hot ng ging nhau , vit mc logic 1 ln WDCE v WDE . 1 mc logic 1 phi c vit ln WDE cho d n c ci t trc khi hot ng v hiu ha bt u 2. Trong vng 4 chu k xung nhp k tip , vit mc logic 0 ln WDE . iu ny v hiu ha watchdog Trong cp an ton 2 , n khng th thc hin v hiu ha Timer watchdog , thm ch vi thut ton c m t bn di . xem timed Sequences for Changing the Configuration of the watchdog Timer trang 58 . Bit 2..0 WDP2, WDP1 , WDP0 : B m gp trc 2,1,0 ca Timer watchdog Cc bit WDP2, WDP1 , WDP0 xc nh vic m gp trc ca Timer watchdog khi m Timer watchdog c kch hot . Gi tr vic m gp trc khc nhau v cc chu k thi gian ch tng ng ca chng c ch ra trong bng 22

on code v d di y ch ra 1 hm assembly v C cho vic tt WDT . V d ny gi nh rng cc ngt c iu khin ( v d bng cch v hiu ha cc ngt chung ) v vy s khng c ngt no xut hin trong sut qu trnh thc thi cc hm ny .

Cc chui c nh thi cho vic thay i cu hnh ca Timer watchdog Cc chui cho vic thay i cu hnh khc bit khng ng k gia 3 cp an ton . Phng php phn chia th c miu t cho mi cp Cp an ton 0

Ch ny th tng thch vi hot ng ca Timer watchdog c tm thy trong Atmega 103 . Timer watchdog th b v hiu ha t u , nhng khng th c kch hot bng vic ghi bit WDE l 1 m khng c bt c s hn ch no .Chu k thi gian ch c th b thay i ti bt c thi gian no gii hn . v hiu ha mt 1 Timer watchdog kch hot , th quy trnh c miu t trang 56 (s miu t Bit WDE) phi c tun theo . Cp an ton 1 Trong ch ny , Timer watchdog b v hiu ha t u , nhng c th c kch hot bng vic vit bit WDE l 1 d cho bt c s ngn cn no . 1 chui c nh thi l cn thit khi vic thay i chu k thi gian ch ca watchdog hoc vic v hiu ha1 Timer watchdog kch hot. v hiu ha 1 Timer watchdog kch hot,v/hoc thay i thi gian ch watchdog , cc quy trnh di y phi c tun theo : 1. trong hot ng ging nhau , vit mc logic 1 ln bit WDCE v WDE . Mt mc logic 1 phi c ghi bt chp gi tr trc ca bit WDE 2. Trong vng 4 chu k xung nhp k tip , trong cc qu trnh iu khin ging nhau , vit cc bit WDE v WDP nh mun nhng vi bit WDCE c xa Cp an ton 2 Trong ch ny , Timer watchdog lun lun c kch hot , v bit WDE s lun lun c c nh l 1 . mt chui c nh thi l cn thit khi thay i chu k thi gian ch ca watchdog . thay i thi gian ch ca watchdog , cc quy trnh di y phi c tun theo : 1. Trong cc qu trnh iu khin ging nhau , vit mc logic 1 len WDCE v WDE . Cho d WDE lun c ci t , WDE phi c vit l 1 khi ng chui c nh thi 2. Trong vng 4 chu k xung nhp k tip ,trong cc hot ng ging nhau , vit cc bit WDP nh gi tr mong mun , nhng vi bit WDCE c xa. Gi tr c vit ln bit WDE th khng thch hp

VIII . Cc ngt
Phn ny miu t cc c trng ca vic s l ngt nh c chy trong Atmega 128 . cho mt s din t chung v vic s l cc ngt ca AVR , tham kho phn Reset v s l ngt trang 15 Cc vecto ngt trong Atmega 128

Bng 24 ch ras b tr cc vecto ngt v Reset cho s kt hp khc nhau ca vic ci t BOOTRST v IVSEL . Nu chng trnh khng bao gi kch hot 1 ngun ngt , cc vecto ngt th khng c s dng , 1 on code chng trnh thng thng c th c t vo trong cc v tr ny . y cng l trng hp nu vecto Reset trong on chng trnh ng dng trong khi cc vecto ngt th trong khu vc khi ng Boot section hoc vise versa

Cc ci t chng trnh chung v thng dng nht cho vic t a ch cc vecto ngt v vecto Reset ca Atmega 128 l

Khi m cu ch BOOTRST khng c lp trnh , kch c ca khu vc khi ng c ci t ln 8K bytes v bit IVSEL trong thanh ghi MCUCR c ci t trc khi bt c ngt no c kch hot, cc ci t chung v thng dng nht cho cc a ch vecto ngt v Reset l

Khi cu ch BOOTRST c lp trnh v ln khu vc khi ng ci t ln 8K bytes , ci t chng trnh chung v thng dng nht cho cc a ch ca Vecto ngt v Reset l

Khi m cu ch BOOTRST c lp trnh , kch c khu vc khi ng t ln 8K bytes v bit IVSEL trong thanh ghi MCUCR c ci t trc khi cc ngt c kch hot , ci t chng trnh chung v in hnh nht cho cc a ch cc vecto ngt v Reset l

Vic di chuyn cc ngt gia cc chng trnh ng dng v khng gian khi ng ( Moving Interrrupts Between Application and Boot Space ) Thanh ghi iu khin cc ngt chung iu khin vic sp xp v tr ca bng cc vecto ngt .

Thanh ghi iu khin MCU MCUCR

Bit 1 IVSEL : la chn cc vecto ngt Khi m bit IVSEL b xa (0 ) , cc vecto ngt c t vo v tr bt u ca b nh Flash . Khi bit ny c t l 1 , cc vecto ngt c di chuyn n v tr bt u ca khu vc ti ch khi ng trong b nh Flash . a ch hin thi ca v tr bt u ca khu vc khi ng trong b nh Flash (Boot Flash section ) c xc nh bi cc cu ch BOOTSZ . tham kho phn Boot Loader Support v Read-while- write Self-Programming trang 273 thm chi tit . trnh cc thay i v tnh ca cc bng cc vec to ngt , 1 quy trnh ghi c bit phi c tun theo thay i bit IVSEL : 1. Vit bit kch hot thay i vecto ngt (IVCE) l 1 2. Trong vng 4 chu k xung nhp , vit gi tr mong mun ln IVSEL trong khi vit l 0 ln bit IVCE Cc ngt s b v hiu ha 1 cch t ng trong khi chui ny c thi hnh , cc ngt b v hiu ha trong chu k IVCE c ci t . v phn d ca chng b v hiu ha cho n sau khi lnh bn di c vit vo IVSEL. Nu nh IVSEL khng c ghi , cc ngt cn li b v hiu ha trong 4 chu k xung nhp . Bt I trong thanh ghi trng thi th khng b tc ng bi vic v hiu ha t ng Ch rng : Nu cc vecto ngt c t trong khu vc ti qu trnh khi ng v bit kha qu trnh khi ng BLB02 c lp trnh , cc ngt s b v hiu ha trong qu trnh thc thi t khu vc ng dng . Nu cc vecto ngt c t trong khu vc chng trnh ng dng v cc bit kha Boot BLB02 c lp trnh, cc ngt b v hiu ha trong khi qu trnh thc thi t khu vc ti qu trnh khi ng . tham kho thm phn Boot Loader Support trang 273 bit thm chi tit v cc bit kha BOOT Bit 0 IVCE : kch hot thay i cc vecto ngt Bt IVCE phi c ghi ln mc logic 1 kch hot thay i ca bit IVSEL. IVCE th b xa bng phn cng 4 chu k xung nhp sau khi n c vit hoc khi IVSEL c ghi . Vic ci t bit IVCE s v hiu ha cc ngt , nh l c din t trong phn miu t IVSEL bn trn . Xem on code v d bn di

IX . Cc cng vo ra ( I/O port )

Gii thiu

Tt c cc cng vo ca AVR u c chc nng c-sa i-ghi khi c s dng nh l cc cng I/O digital chung . iu ny c ngha l hng ca 1 chn cng c th c thay i m c s thay i hng v tnh no ca bt c chn no khc vi lnh SBI v CBI . Ci ging nh vy c p dng khi thay i gi tr iu khin (nu c cu hnh nh l u ra ) hoc vic kch hot/v hiu ha ca in tr ko ln (nu c cu hnh nh l u vo ) . Mi b m u ra c c tnh iu khin i xng vi c hai tn nhit cao v ngun in dung. B iu khin chn th mnh iu khin b hin th LED 1 cch trc tip . Tt c cc chn cng c in tr ko ln c kh nng la chn ring bit vi 1 tr khng bt bin ca in p ngun cp . Tt c cc chn I/O c cc iode bo v c 2 VCC v chn Ground nh l c hin th trong hnh 29 . Tham kho electrical characteristic trang 318 c bng cc tham s y .

Tt c cc thanh ghi v cc bit tham kho trong phn ny c ghi trong 1 mu chung . Trong mt trng hp thp hn x i din cho numbering letter ca cng , v 1 kt di (lower case ) n i din cho s th t bit . Tuy nhin khi vic s dng cc thanh ghi hoc cc bit xc nh trong 1 chng trnh , mu chnh xc phi c s dng . V d PORTB3 cho bit s 3 trong cng B , c dn chng chung chung nh l PORTxn. Thanh ghi I/O vt l v v tr cc bit c lit k trong Register Description for I/O Ports trang 87. Ba v tr a ch b nh I/O th c phn phi cho mi cng , 1 cho thanh ghi d liu PORTx , Thanh ghi nh hng d liu DDRx , v cc chn u vo ca cng PINx. V tr I/O ca u vo cc chn th ch c c , trong khi thanh ghi d liu v thanh ghi nh hng d liu c c v ghi . Thm vo , bit v hiu ha dng li PUD trong SFIOR v hiu ha chc nng pull-up ca cho tt c cc chn trong tt c cc cng khi c ci t. Vic s dng cc cng vo ra nh l cc cng vo ra s chung c miu t trong Ports as general Digital I/O trang 67 . Hu ht cc chn cng l a hp vi cc hm lun phin (alternate functions) cho cc c tnh ngoi vi trn thit b . Cch m mi hm lun phin gy nhiu vi cc chn cng th c miu t trong alternate port functionstrn trang 71 . Tham kho thm phn module ring bit cho mi cho 1 s miu t y ca cc hm lun phin (Alternate function)

Ch rng vic kch hot hm lun phin ca vi chn cng th khng nh hng n vic s dng cc chn khc trong cng nh l cc cng I/O s chung . Cc cng nh l I/O k thut s chung ( Ports as General Digital I/O) Cc cng l cc cng I/O 2 hng vi xung la chn bn trong (optinal internal pullup) . Hnh 30 ch ra 1 s miu t chc nng ca 1 chn cng I/O , c gi chung l Pxn

Cu hnh cc chn Mi chn cng bao gm 3 bit ng k : DDxn , PORTxn , PINxn . Nh l c ch ra trong Register Description for I/O ports trang 87. Cc bit DDxn c truy nhp ti a ch I/O DDRx , cc bit PORTxn ti a ch I/O PORTx v cc bit PINxn ti a ch I/O PINx Bit DDxn trong thanh ghi DDRx la chn hng ca chn ny . Nu DDxn c vit mc logic 0 , Pxn c cu hnh l nh 1 chn u vo. Nu PORTxn c vit mc logic 1 khi chn ny c cu hnh nh l 1 chn u vo , 1 in tr pull-up c kch hot . tt in tr pull-up , PORTxn phi c vit l mc logic 0 hoc chn phi c cu hnh nh l 1 chn u ra . Cc chn cng th c 3 trng thi khi m iu kin Reset tr nn hot ng , d cho khng c b nh thi no ang chy . Nu PORTxn c vit mc 1 khi m chn ny c cu hnh nh l 1 chn u ra , chn cng c iu khin mc cao (1) . Nu PORTxn c vit mc logic 0 khi m chn c cu hnh nh l chn u ra , chn cng c iu khin mc thp (0)

Khi bt tt gia 3 trng thi ({DDxn , PORTxn})=0b00 ) v u ra cao ({DDxn , PORTxn} = 0b11 , mt trng thi trung gian vi pull-up kch hot ({DDxn , PORTxn}=0b01 ) hoc u ra thp ({DDxn,PORTxn}=0b10 ) phi xut hin . Thng thng , pull-up kch hot trng thi th c th truy nhp y , nh l mt mi trng c tr khng cao s khng nhn bit s khc nhau gia 1 b iu khin mnh v mt pull-up . Nu y khng phi l trng hp ny , bit PUD trong thanh ghi SFIOR c th c vit l 1 v hiu ha tt c cc pull-up trong tt c cc cng . Vic chuyn i gia cng vo vi pull-up v cng ra thp lm ny sinh cc vn ging nhau . Ngi s dng phi s dng 1 trong 3 trng thi({DDxn , PORTxn} = 0b00 ) hoc trng thi u ra mc cao ({DDxn , PORTxn }=0b11 ) nh l cc bc trung gian Bng 25 tm tt cc tn hiu iu khin cho gi tr ca chn

c gi tr cc chn Khng ph thuc vo vic ci t cc bit nh hng d liu DDxn , cc chn cng c th c c thng qua bit thanh ghi PINxn . Nh c ch ra trong hnh 30 , bit thanh ghi PINxn v then ci trc cu to 1 cch ng b . iu ny l cn thit trnh tnh na bn nu nh cc chn vt l thay i gi tr gn sn ca xung nhp bn trong (internal clock ) , nhng n cng gii thiu 1 tr . Hnh 31 ch ra 1 mch b nh thi ca s ng b khi vic c 1 gi tr chn c t bn ngoi . Gi tr cc i v cc tiu ca s tr lan truyn th c k hiu tng ng l tpd,max v tpd,min

Coi nh chu k xung nhp c bt u ngn sau khi sn xung u tin ca xung nhp h thng . Then ci (latch ) th c ng khi m xung nhp thp , v tr thnh trong sut khi

xung nhp mc cao , nh l c hin th bng khong bng ca tn hiu SYNC LATCH . Gi tr tn hiu th c cht (latched ) khi m xung nhp h thng xung mc thp . N b kha bn trong thanh ghi PINxn ti v tr ca sn xung nhp dng k tip . Nh l c hin th bng 2 dng tpd,max v tpd, min , mt tn hiu chuyn tip n trn chn s b tr gia v 1 ca chu k xung nhp h thng ph thuc vo thi gian trn ca s xc nhn . Khi vic c li 1 phn mm xc nhn gi tr ca cc chn , 1 lnh nop phi c chn vo nh l c hin th trong hnh 32 . Lnh Out ci t tn hiu SYNC LATCH ti sn dng ca xung nhp . Trong trng hp ny , thi gian tr tpd thng qua b ng b ha l 1 chu k xung nhp h thng .

on m mu di y ch ra cch ci t cc chn 0 v 1 cao v 2,3 thp ca cng B , v xc nh cc chn cng t 4 n 7 nh l u vo vi cc pull-p c gn vo cc chn 6 v 7. Kt qu cc gi tr ca chn c c tr li , nhng nh l tho lun t trc , mt lnh nop th bao gm cc gi tr hin thi c th c tr li c gn n mt vi chn

Kch hot u vo k thut s v cc ch ng ( Digital Input Enable and Sleep Modes )

Nh l c ch ra trong hnh 30 , tn hiu u vo s c th c kp (clamped ) vi t ti u vo ca mch khi ng schmitt (schmitt trigger ) . Tn hiu c k hiu SLEEP trong hnh v , c ci t bng b iu khin ch ng MCU (MCU sleep controler ) trong ch tt ngun , ch tit kim ngun , ch ch Standby mode , v ch ch m rng Extended Standby , trnh tn hao in p cao nu mt vi tn hiu u vo khng c ni t (left floating ) , hoc c mt tn hiu tng t analog ng ln chn VCC/2 SLEEP c ghi ln cc chn cng kch hot nh l cc chn ngt ngoi (External Interrupt ) . Nu cc truy vn ngt ngoi khng c kch hot , SLEEP cng c kch hot cho cc chn ny . SLEEP th cng c ghi bng nhiu hm chc nng khc nhau nh l c miu t trong Alternate Port Function trn trang 71 . Nu nh mc logic cao (1) c a ra trong1 chn ngt ngoi d b c cu hnh nh l sn ln trn ngt , sn xung trn ngt , hoc bt c s thay i logic no trn chn trong khi ngt ngoi th khng c kch hot , s tng ng ca cc c bo ngt ngoi s c ci t khi tip tc t cc ch ng c ni n trn , nh l km trong cc ch ng gy ra truy vn cc thay i logic Cc chn khng c kt ni Nu mt vi chn khng c s dng , n c khuyn co m bo rng cc chn ny c mt cp xc nh . Mc d tt c cc u vo s b v hiu ha trong cc ch ng nh l c miu t trn , vic ni t cc u vo nn c trnh gim cc dng in tn hao trong tt c cc ch khc nhau ni m cc u vo s c kch hot (Reset , Active mode v Idle mode) Phng php n gin nht m bo 1 cp xc nh ca 1 chn khng s dng , l kch hot pull-up bn trong . Trong trng hp ny , pull-up s b v hiu ha trong sut qu trnh Reset. Nu s tn hao ngun thp trong sut qu trnh Reset l quan trng , n c khuyn co s dng 1 pull-up ngoi hoc 1 pull-down . Vic kt ni cc chn khng s dng mt cch trc tip n VCC v GND th khng c khuyn khch , t khi vic ny gy ra dng in tha nu chn ny c cu hnh ngu nhin nh l 1 u ra . Chc nng cng lun phin Tt c cc chn cng u c chc nng lun phin b sung vo tr thnh cc I/O s chung . Hnh 33 ch ra cch 1 chn cng iu khin cc tn hiu rt gn t hnh 30 c th c ghi bng cc cng chc nng lun phin (alternate Functions ) . S ghi tn hiu c th khng c a ra trong tt c cc chn cng , nhng hnh ny phc v nh l mt s miu t chung c th p dng ln tt c cc chn cng trong h vi iu khin AVR

Bng 26 tng kt chc nng ca cc tn hiu ghi (Overriding signals ) . Cc danh mc cc chn v cng t hnh 33 th khng c ch ra trong cc bng k tip . Cc tn hiu ghi th c sinh ra bn trong cc module c chc nng lun phin ( alternate Function )

Vng nh bn di miu t chc nng lun phin cho mi cng , v c lin quan n cc tn hiu ghi ln cc chc nng lun phin . Tham kho thm phn m t chc nng lun phin bit thm chi tit Thanh ghi IO ch nng c bit SFIOR

Bit 2 PUD : v hiu ha pull-up Khi bit ny c vit l 1 , pull-up trong cc cng I/O b v hiu ha d l thanh ghi DDxn v PORTxn c cu hnh kch hot pull-ups ({DDxn , PORTxn }=0b01 ). Xem phn cu hnh cc chn trang 67 bit thm chi tit v c im ny . Chc nng lun phin ca cng A Cng A c 1 hm lun phin Alternate Function nh l a ch byte thp v dng d liu cho giao din b nh ngoi .

Bng 28 v 29 lin quan n hm lun phin ca cng A n cc tn hiu ghi c ch ra trong hnh 33 trang 71.

Chc nng lun phin ca cng B : Alternate Functions of Port B

Chn lun phin c cu hnh nh bn di :

OC2/OC1C , bit 7 OC2 , u ra so snh ghp vi u ra : chn PB7 c th phc v nh l mt u ra bn ngoi cho u ra so snh Timer/Counter 2. Chn ny c cu hnh nh l mt cng ra (DDB7 t l 1 ) phc v chc nng ny . Chn OC2 cng l u ra cho chc nng timer mode ca PWM . OC1C , u ra ghp vi u ra C . Chn PB7 c th phc v nh l mt u ra bn ngoi cho u ra so snh C ca Timer/Counter1 . Chn ny c th c cu hnh nh l 1 u ra (DDB7 c t l 1 ) phc v chc nng ny . Chn OC1C cng l u ra cho chc nng timer PWM . OC1B , bit 6 OC1B , u ra so snh ghp u ra B : Chn PB6 c th phc v nh l 1 u ra bn ngoi cho u ra so snh B ca Timer/Counter 1 . Chn ny phi c cu hnh nh l 1 u ra (DDB6 t l 1 ) phc v chc nng ny . Chn OC1B cng l chn ra cho chc nng PWM mode timer OC1A , bit 5 OC1A , u ra so snh ghp u ra A : chn PB5 c th phc v nh l mt cng ra bn ngoi cho Timer/Counter 1 u ra so snh A . Chn ny phi c cu hnh nh l 1 cng ra ( DDB5 t l 1 ) phc v chc nng ny . Chn OC1A cng l chn u ra cho chc nng PWM mode timer . OC0 , Bit 4 OC0 , u ra so snh ghp vi u ra : Chn PB4 c th phc v nh l 1 u ra bn ngoi cho u ra so snh Timer/Counter 0 . Chn ny phi c cu hnh nh l 1 u ra (DDB4 t l 1 ) phc v cho chc nng ny . Chn OC0 cng l u ra cho chc nng PWM mode timer. MISO cng B , bit 3 MISO : chn Master Data input , Slave Data output cho knh SPI . Khi m SPI c kch hot nh l mt master , chn ny c cu hnh nh l 1 u ra m khng quan tm n vic ci t ca DDB3 . Khi SPI c kch hot nh l 1 slave , s nh hng d liu ca chn ny c iu khin bi DDB3 . Khi m chn ny b p buc lm 1 u vo , pull-up c th vn c iu khin bng bit PORTB3 MOSI Cng B , bit 2 MOSI : SPI Master Data ouput , Slave Data input cho knh SPI . Khi m SPI c kch hot nh l slave , chn ny c cu hnh nh l mt u vo bt chp s ci t ca DDB2 . Khi SPI c cu hnh nh 1 master , s nh hng d liu ca chn ny c iu khin bng DDB2 . Khi chn ny b p buc lm 1 u vo , pull-up c th vn c iu khin bi bit PORTB2 . SCK cng B , bit 1 SCK : Master Clock output , Slave Clock input cho knh SPI . Khi m SPI c kch hot nh l slave , chn ny c cu hnh nh l mt u vo bt chp vic ci t ca DDB1. Khi SPI c kch hot nh l mt master , s nh hng d liu ca chn ny c

iu khin bng DDB1. Khi chn ny b p buc lm 1 u vo , pull-up c th vn c iu khin bng bit PORTB1 SS cng B ,bit 0 SS : Slave Port Select input . Khi m SPI c kch hot nh l 1 slave , chn ny c cu hnh nh l 1 u vo bt chp vic ci t ca DDB0 . Nh l 1 slave , SPI c kch hot khi chn ny b ng mc thp . Khi SPI c kch hot nh l mt master , s nh hng d liu ca chn ny c iu khin bi DDB0 . Khi chn ny b p buc lm mt u vo, pull-up c th vn c iu khin bng bit PORTB0 Bng 31 v 32 c lin quan n chc nng lun phin ca cng B ln cc tn hiu ghi c ch ra trong bng 33 trang 71 . SPI MSTR INPUT v SPI SLAVE OUTPUT cu thnh tn hiu MISO , trong khi MOSI b chia ra trong SPI MSTR OUTPUT v SPI SLAVE INPUT

Chc nng lun phin ca cng C Trong ch tng thch vi Atmega 103 , cng C ch l cng ra . Atmega 128 th vn chuyn mc nh ( default shipped ) trong ch tng thch . V vy , nu cc phn khng

c lp trnh trc khi chng c t trn PCB , PORTC s l cng ra trong sut qu trnh bt ngun u tin , v cho n khi ch tng thch vi Atmega 103 b v hiu ha . Cng C c hm chc nng lun phin (alternate Function ) nh l cc byte a ch cao cho giao din b nh ngoi

Bng 34 v 35 lin quan n chc nng lun phin ca cng C n vic ghi tn hiu c ch ra trong hnh 33 trang 71

Chc nng lun phin ca cng D (alternate Functions oi Port D )

Cc chn cng D vi cc chc nng lun phin c ch ra trong bng 36

Cu hnh cc chn lun phin th c ch ra di y : T2 cng D , bit 7 T2 , ngun b m Timer/Counter 2 T1 Cng D , bit 6 T1, ngun b m Timer/Counter 1 XCK1 Cng D ,bit 5 XCK1 , xung nhp ngoi USART1 . Thanh ghi nh hng d liu (DDD4)iu khin 1 trong hai xung nhp l u ra (DDD4 c t ) hoc l u vo (DDD4 b xa ). Chn XCK1 th hot ng ch khi UART1 hot ng trong ch ng trong ch ng b ha . ICP1 cng D ,bit 4 ICP1 Input Capture Pin1 : Chn PD4 c th ng vai tr nh l mt chn thu thp u vo cho Timer/Counter 1 INT3/TXD1 Cng D , bit 3 INT3 , External Interrupt sourse 3 : Chn PD3 c th phc v nh l 1 ngun ngt ngoi n MCU TXD1 , Transmit Data (chn u ra d liu cho UART1 ) . Khi m b chuyn pht USART1 c kch hot , chn ny c cu hnh nh l mt u ra bt chp gi tr ca DDD3 INT2/RXD1 cng D , bit 2 INT2 , External Interrupt sourse 2 . Chn PD2 c th phc v nh l 1 ngun ngt ngoi n MCU RX D1 , Receive Data ( chn u vo d liu cho USART1 ) . Khi m b thu USART1 c kch hot , chn ny c cu hnh nh l 1 u vo bt chp gi tr ca DDD2. Khi USART bt p chn ny tr thnh 1 u vo , pull-up c th vn c iu khin bi bit PORTD2 INT1/SDA cng D , bit 1 INT1 , External Interrupt sourse 1 . Chn PD1 c th phc v nh l 1 ngun ngt ngoi n MCU SDA , Two-wire Serial Interface Data : khi m bit TWEN trong thanh ghi TWCR c t l 1 kch hot giao din 2 dy ni tip , chn PD1 th b ngt kt ni khi cng v tr thnh chn I/O d liu ni tip cho giao din ni tip 2 dy . Trong ch ny , c 1 b lc

xung nhiu trn chn kh cc tn hiu ngn hn 50ns trn tn hiu u vo , v chn ny c iu khin bi 1 b iu khin knh m vi s gii hn tc quay . INT0/SCL Cng D , bit 0 INT0 , External Interrupt source 0 . Chn PD0 c th phc v nh l 1 ngun ngt bn ngoi n MCU SCL , Two-wire Serial Interface Clock : Khi m TWEN trong TWCR c t l 1 kch hot giao din 2 dy ni tip , chn PD0 b ngt kt ni khi cng v tr thnh cng I/O xung nhp ni tip cho giao din 2 dy ni tip . Trong ch ny , c mt b lc xung nhiu trn chn kh cc xung nhiu ngn hn 50ns trn tn hiu u vo v chn ny c iu khin bi 1 b iu khin knh m vi s gii hn tc quay . Bng 37 v 38 lin quan n chc nng lun phin ca cng D n tn hiu ghi c ch ra trong bng 33 trang 71

Chc nng lun phin ca cng E ( Alternate Functions of Port E )

Cc chn cng E vi chc nng lun phin c ch ra trong bng 39

INT7/ICP3 cng E , bit 7 INT7 , External Interrupt source 7 : Chn PE7 c th phc v nh l mt ngun ngt ngoi. ICP3 Input Capture Pin 3 : Chn PE7 c th ng vai tr nh l mt chn thu thp u vo cho Timer/Counter 3 INT6/T3 Cng E ,bit 6 INT6 , External Interrupt source : chn PE6 c th phc v nh l 1 ngun ngt ngoi T3 , ngun b m Timer/Counter 3 INT5/OC3C Cng E , bit 5 INT5 , External Interrupt source 5 : Chn PE5 c th phc v nh l mt ngun ngt ngoi OC3C , Output Compare Match C ouput ( u ra so snh tng ng u ra C ) : chn PE5 c th phc v nh l mt u ra bn ngoi cho u ra so snh cng C Timer/Counter 3 . Chn ny phi c cu hnh nh l mt u ra (DDE5 t l 1 ) phc v chc nng ny . Chn OC3C cng l chn u ra cho chc nng Timer trong ch PWM INT4/OC3B Cng E ,bit 4 INT4 , External Interrupt source 4 : chn PE4 c th phc v nh l 1 ngun ngt ngoi OC3B , u ra so snh ghp u ra B : Chn PE4 c th phc v nh l mt u ra bn ngoi cho u ra so snh B ca Timer/Counter 3 . Chn ny phi c cu hnh nh l mt cng ra (DDE4 t l 1 ) phc v chc nng ny . Chn OC3B cng l chn u ra cho chc nng timer trong ch PWM . AIN1/OC3A cng E ,bit 3 AIN1 Analog Comparator Negative Input . Chn ny c ni trc tip n u vo m ca b so snh tng t (analog Comparator ) OC3A , u ra so snh ghp u ra A : Chn PE3 c th phc v nh l 1 u ra bn ngoi cho u ra so snh A ca Timer/Counter 3 . Chn ny c cu hnh nh l 1 u ra (DDE3 t l 1 ) phc v chc nng ny . Chn OC3A cng l chn ra cho chc nng timer trong ch PWM AIN0/XCK0 cng E , bit 2

AIN0 Analog Comparator Positive input (u vo dng ca b so snh Analog ) : chn ny c ni trc tip vi u vo dng ca b so snh analog XCK0 , USART0 External Clock ( xung nhp ngoi ca USART0) . Thanh ghi nh hng d liu (DDE2) iu khin 1 trong 2 xung nhp l u ra (DDE2 c t ) hoc l u vo (DDE2 b xa ) . Chn XCK0 ch hot ng khi USART0 iu khin trong ch ng b ha PDO/TXD0 Cng E ,bit 1 PDO , SPI Serial Programming Data Output (u ra d liu lp trnh ni tip SPI) . Trong sut qu trnh ti v chng trnh ni tip , chn ny c s dng nh l 1 dng u vo d liu cho Atmega 128 RXD0 , USART0 Receive Pin ( chn d liu u vo n USART0) . Khi b thu tn hiu USART0 c kch hot chn ny c cu hnh l 1 nh l mt u vo bt chp gi tr ca DDRE0 . Khi USART0 bt chn ny l mt u vo , 1 mc logic 1 trong PORTE0 s bt pull-up bn trong ln Bng 40 v 41 lin quan n chc nng lun phin ca cng E ti vic ghi tn hiu c ch ra trong hnh 33 trang 71

Chc nng lun phin ca cng F ( alternate Functions of port F )

Cng F c mt chc nng lun phin nh l u vo tng t cho b chuyn i ADC nh l c ch ra trong bng 42 . Nu mt vi chn ca cng F c cu hnh nh l nhng u ra , iu ny l cn thit v khng c b chuyn mch khi 1 qu trnh chuyn i ang c tin hnh . iu ny c th lm hng kt qu ca qu trnh chuyn i . Trong ch tng thch vi Atmega 103 th ch cng F c s dng. Nu nh giao din JTAG c kch hot , in tr pull-up trn chn PF7 (TDI) , PF5(TMS) v PF4(TCK) s c kch hot tr khi tn hiu Reset xut hin

TDI, ACD7 cng F , bit 7 ACD7 , b chuyn i tng t sang s , knh 7 TDI , JTAG Test Data In : d liu cng vo ni tip c shifted trong thanh ghi lnh ca thnh chi d liu ( cc chui qut ). Khi m giao din JTAG c kch hot , chn ny c th khng c s dng nh l mt chn I/O TDO,ADC6 cng F ,bit 6 ADC6 , b chuyn i tng t sang s , knh 6 TDO, JTAG Test Data Out : d liu u vo ni tip t thanh ghi lnh hoc thanh ghi d liu . Khi giao din JTAG c kch hot, chn ny khng th c s dng nh l mt chn I/O Chn TDO c 3 trng thi tr phi cc trng thi TAP shift d liu ngoi c truy nhp TMS, ADC5 cng F , bit 5 ADC5 , b chuyn i tng t sang s , knh 5 TMS , la chn ch kim tra JTAG : chn ny c s dng cho s nh hng thng qua b iu khin TAP trng thi my (TAP-controller state machine ). Khi giao din JTAG c kch hot chn ny khng th c s dng nh l 1 chn I/O TCK, ACD4 cng F ,bit 4 ACD4 , b chuyn i tng t sang s ,knh 4 TCK , xung nhp kim tra JTAG : qu trnh iu khin JTAG l ng b ha ln TCK . Khi m giao din JTAG c kch hot , chn ny khng th s dng nh l mt chn I/O ADC3 ADC0 cng F , bit 3..0 B chuyn i tng t sang s , knh 3...0

Chc nng lun phin ca cng G Trong ch tng thch vi Atmega 103 , ch ch lun phin l mc nh cho cng G , v cng G khng th c s dng nh l cc chn cng s chung . Cu hnh cc chn lun phin nh l c bn di :

TOSC1 cng G , bit 4 TOSC1 , chn b to dao ng Timer : khi m bit AS0 trong thanh ghi ASSR c t l 1 kch hot b nh thi d b ca Timer/Counter 0 , chn PG3 b ngt kt ni khi cc cng , v tr thnh u ra cho b khuych i ca b khuych i dao ng k (Oscillator amplifier ) . Trong ch ny , 1 b to dao ng thch anh c kt ni vi cc chn ny , v cc chn ny khng c s dng nh l 1 chn vo ra I/O TOSC2 cng G , bit 3 TOSC2 , chn 2 ca b to dao ng ca Timer : Khi bit AS0 trong thanh ghi ASSR c t l 1 kch hot b nh thi d b ca Timer/Counter 0 , chn PG3 b ngt kt ni

khi cng , v tr thnh u ra khuych i ca b khuych i ca b to dao ng . Trong ch ny , 1 b to dao ng thch anh c kt ni vi chn ny ,v chn ny khng th c s dng nh l mt chn vo ra . ALE cng G , bit 2 ALE l b nh d liu bn ngoi Address Latch Enable signal RD cng G , bit 1 RD l b nh d liu bn ngoi c iu khin phn tch WR cng G , bit 0 WR l b nh d liu bn ngoi vit iu khin phn tch Bng 46 v 47 lin quan n chc nng lun phin ca cng G ti vic ghi tn hiu c ch ra trong hnh 33 trang 71

S m t thanh ghi cho cc cng I/O Thanh ghi d liu cng A - PORTA

Thanh ghi nh hng d liu cng A DDRA

a ch cc chn u vo cng A - PINA

Thanh ghi d liu cng B PORTB

Thanh ghi nh hng d liu cng B DDRB

a ch cc chn u vo B PINB

Thanh ghi d liu cng C PORTC

Thanh ghi nh hng d liu cng C DDRC

a ch cc chn u vo C PINC

Trong ch tng thch vi Atmega 103 , thanh ghi DDRC v PINC c khi to y v ko ( Push Pull )u ra Zero . Cc chn cng gi s gi tr khi to ca chng , cho d b nh thi ang khng hot ng . Ch rng cc thanh ghi DDRC v PINC th khng kh dng trong ch tng thch vi Atmega 103 v nn khng c s dng cho ch tng thch pha sau . Thanh ghi d liu cng D PORTD

Thanh ghi nh hng d liu cho cng D DDRD

a ch cc chn u vo ca cng D

Thanh ghi d liu cho cng E PORTE

Thanh ghi nh hng d liu cho cng E DDRE

a ch cc chn cng u vo cng E PINE

Thanh ghi d liu cng F PORTF

Thanh ghi nh hng d liu cng F DDRF

a ch cc chn u vo PINF

Thanh ghi d liu cng G PORTG

Thanh ghi nh hng d liu cng G DDRG

a ch cc chn u vo cng G PING

Ch rng PORG , DDRG , v PING u khng kh dng trong ch tng thch vi Atmega 103 . Trong ch tng thch vi Atmega 103 cng G phc v ch lun phin ca n ch c ( TOSC1 , TOSC2 , WR , RD , ALE )

X . Cc ngt ngoi
Cc ngt ngoi c khi ng bng cc chn INT7:0 . Ch rng , nu c kch hot , cc ngt s khi ng d cho cc chn INT7..0 c cu hnh nh l cc u ra . c im ny cung cp 1 cch sinh ra 1 phn mm ngt . Cc ngt ngoi c th c khi ng bng vic sn xung hoc bt sn ln hoc l mt mc logic thp . iu ny c ci t nh th hin trong bng c tnh k thut ca thanh ghi iu khin cc ngt ngoi EICRA (INT3:0) v EICRB( INT7:4). Khi cc ngt ngoi c kch hot c cu hnh nh l 1 cp khi ng , cc ngt s khi ng ch cn chn c gi mc thp . Ch rng s nhn bit vic bt sn xung v bt sn ln ca cc ngt trn chn INT7:4 cn s c mt ca 1 b nh thi I/O , c miu t trong phn Clock System and their Distribution trang 36 . Cc ngt cp thp v cc sn ngt trn INT3:0 c d mt cch d b . iu ny ng rng cc ngt ny c th c s dng cho vic bc (walking ) ca phn cng t cc ch ng khc hn ch Idle . B nh thi I/O c dng trong tt c cc ch ng tr ch Idle . Ch rng nu 1 mc ngt khi ng c s dng cho vic nh thc t ch ngt ngun , mc thay i phi c gi trong 1 khong thi gian nh thc MCU .

iu ny lm cho MCU gim s nhy cm vi cc nhiu . Mc thay i c ly mu 2 ln bng b nh thi to dao ng watchdog . Chu k ca b to dao ng watchdog l 1 s (thng thng ) 5V v 25 C . Tn s ca b to dao ng watchdog th ph thuc vo in p nh l c ch ra trong phn electrical characteristics trang 318 . MCU s c nh thc nu u vo c mc cn thit trong sut qu trnh ly mu hoc nu n c gi cho n khi kt thc thi gian khi ng . Thi gian khi ng c xc nh bng cu ch SUT nh l c miu t trong phn Clock System and their Distribution trang 36. Nu nh mc c ly mu 2 ln bng b to dao ng watchdog nhng bin mt trc khi kt thc thi gian khi ng, MCU s vn c nh thc , nhng khng c ngt no s c sinh ra . Mc cn thit phi c gi di cho MCU hon thnh vic nh thc khi ng mc ngt Thanh ghi iu khin ngt ngoi A EICRA

Thanh ghi ny c th khng c hng ti trong ch tng thch vi Atmega 103 , nhng gi tr khi u ca n xc nh INT3:0 nh l cc ngt mc thp , nh trong Atmega 103 . Bit 7..0 ISC31 , ISC30 ISC00 , ISC00 : ngt ngoi 3 cc bit iu khin nhy 0 Cc ngt ngoi 3-0 th c kch hot bng cc chn bn ngoi INT3:0 nu nh c I SREG v ngt tng ng che trong EIMSK c ci t . Mc v cc sn trn cc chn bn ngoi ci m kch hot cc ngt c xc nh trong bng 48 . Cc sn trn INT3..INT0 th c ng k 1 cch d b . Cc xung trn cc chn INT3:0 rng hn rng xung cc tiu c a ra trong bng 49 s sinh ra mt ngt . Cc xung ngn hn th khng bo m sinh ra 1 ngt . Nu mc ngt thp c la chn , mc thp phi c gi cho n khi hon tt lnh ang thc thi hin thi sinh ra mt ngt . Nu c kch hot , 1 mc ngt khi ng se pht sinh ra 1 yu cu ngt ch cn chn ny c gi mc thp . Khi s thay i bit ISCn , 1 ngt c th xut hin . V vy , n c khuyn co v hiu ha u tin INTn bng vic xa bit kch hot ngt ca n trong thanh ghi EIMSK . Sau , bit ISCn c th c thay i Cui cng , c ngt INTn nn c xa bng cch vit mc logic 1 ln bit c ngt ca n (INTFn ) trong thanh ghi EIFR trc khi ngt c kch hot li.

Thanh ghi iu khin ngt ngoi B EICRB

Bit 7..0 ISC71, ISC70 ISC41, ISC40 : cc bit iu khin nhy ngt ngoi 7-4 Cc ngt ngoi 7 4 c kch hot bng cc chn ngoi INT7:4 nu nh c I SREG v cc ngt tng ng che trong qu trnh EIMSK c ci t . Mc v cc sn trn cc chn ngoi ci m kch hot cc ngt th c xc nh trong bng 50 . Gi tr trn cc chn INT7:4 c ly mu trc khi d cc sn xung . Nu sn hoc khuu ngt c la chn , cc xung cui m di hn 1 chu k xung nhp s sinh ra 1 ngt . Cc xung ngn hn th khng m bo pht ra 1 ngt . V vy , tn s xung nhp CPU c th thp hn tn s XTAL nu nh b chia XTAL c kch hot . Nu cc mc ngt thp hn c la chn , mc thp phi c gi cho n khi hon tt qu trnh thc hin lnh hin hnh sinh ra 1 ngt . Nu c kch hot , 1 mc ngt khi ng s sinh ra 1 yu cu ngt ch cn n c gi mc thp .

Thanh ghi che ngt ngoi EIMSK

Bit 7...0 INT7 INT0 : kch hot truy vn ngt ngoi 7 0 Khi 1 bit INT7 INT0 c ghi l 1 v bit I trong thanh ghi trng thi (SREG)c t l 1 , chn ngt ngoi tng ng c kch hot . Cc bit iu khin nhy ngt trong thanh ghi iu khin ngt ngoi EICRA v EICRB c xc nh bng 1 trong 2 cch , ngt ngoi c kch hot trn sn ln hoc sn xung hoc mc nhy ( level sensed ). Hot ng trn bt c mt chn no s khi ng mt yu cu ngt d cho chn ny c kch hot nh l mt u ra . iu ny cung cp 1 cch ca vic sinh ra phn mm ngt . Thanh ghi c ngt ngoi EIFR (external interrupt flag register )

Bit 7...0 INTF7 INTF0 : c ngt ngoi 7 0 Khi mt sn hoc thay i bin logic trn chn INT7:0 khi ng mt yu cu ngt . . INTF7:0 s c ci t l 1 .Nu bit I trong SREG v bit kch hot ngt tng ng , INT7:0 trong thanh ghi EIMSK c ci t l 1 , MCU s nhy ti vec to ngt. C b xa khi mt chng trnh con phc v ngt c thc thi . Nh mt s la chn, c c th b xa bng vic vit mc logic 1 ln n . Cc c th lun c xa khi m INT7:0 c cu hnh nh l mt mc ngt . Ch rng khi truy nhp vo ch sleep vi cc ngt INT3:0 v hiu ha , cc b m u vo trn cc chn ny s b v hiu ha . iu ny c th gy ra 1 s thay i bin logic trong tn hiu bn trong ci m s c ci t cc c INT3:0 . Xem thm Digital Input Enable and Sleep Modes trang 70 bit thm thng tin

XI . 8-bit Timer/Counter 0 vi PWM and Asynchronous Operation ( Timer/Counter 8 bit vi PWM v iu khin d b )
Timer/Counter0 l mt module Timer/Counter 8 bit , knh n , a nng dng chung . Cc c im chnh l : - B m knh n - Xa Timer trn b so snh tng ng ( t ng ti li ) - Khng c nhiu sc ngang , iu ch rng xung ng pha (PWM) - My pht tn s - B m gp trc xung nhp 10 bit - Dng trn (overflow) v cc ngun ngt ghp so snh (TOV0 v OCF0 ) - Cho php b nh thi t bn ngoi 32kHz ng h thch anh ph thuc vo xung nhp I/O Tng quan

Mt s khi rt gn ca 1 Timer/Counter 8bit c a ra trong hnh 34 . V s sp t hin ti ca cc chn I/O , tham kho phn cu hnh chn trang 2 . CPU c th truy nhp cc thanh ghi I/O , bao gm cc bit I/O v cc chn I/O , c in m . Thanh ghi I/O ca thit b xc nh v v tr cc bit c lit k trong phn 8-bit Timer/Counter Register Description trang 104

Cc thanh ghi Timer/Counter (TCNT0 ) v cc thanh ghi so snh u ra (OCR0 ) l cc thanh ghi 8 bit. Cc tn hiu Yu cu ngt ( vit tt l Int.Req. ) th u c nhn thy trong trong thanh ghi c ngt Timer (TIFR) . Tt c cc ngt u c che ring vi thanh ghi che ngt Timer (TIMSK ) . TIFR v TIMSK u khng c ch ra trong hnh t cc thanh ghi ny c chia s bng cc b phn timer khc . Timer/Counter c th b kha bn trong , nh b m gp trc hoc b kha mt cch khng ng b khi cc chn TOSC1/2 , nh c miu t chi tit trong cc phn sau . Qu trnh iu khin d b c iu khin bi thanh ghi trng thi d b (ASSR) . Khi logic la chn xung nhp iu khin ci m ngun xung nhp Timer/Counter s dng lm tng hoc gim gi tr ca n . Timer/Counter th khng hot ng khi khng c ngun pht xung nhp no c la chn . u ra t b nh thi la chn mc logic c hng dn nh l mt xung nhp timer (clkT0) Thanh ghi so snh u ra (OCR0)lu trong b m kp th c so snh vi gi tr ca Timer/Counter ti tt c cc thi gian . Kt qu ca php so snh c th c s dng my pht dng sng pht ra xung PWM hoc u ra tn s bin thin trn chn so snh u ra

OC0). Xem thm Output Compare Unit trn trang 95 bit thm chi tit . B so snh ghp s kin cng s ci t c so snh (OCF0) ci m c th c s dng sinh ra 1 yu cu ngt so snh u ra Cc nh ngha Nhiu thanh ghi v cc bit tham kho trong ti liu ny c vit theo mu chung . Mt trng hp thp n c thay th cho s th t ca Timer/Counter , trong trng hp ny l 0 . Tuy nhin , khi s dng thanh hgi hoc bit xc nh trong 1 chng trnh , mt mu chnh xc phi c s dng ( v d TCNT0 cho vic truy nhp Timer/Counter 0 m gi tr ) nh ngha bng 51 th cng c s dng mt cch rng ri xuyn sut ti liu ny

Cc ngun xung nhp Timer/Counter Timer/Counter c th b kha bng vic 1 b ng b bn trong hoc mt ngun xung nhp d b bn ngoi . Ngun xung nhp clkT0 th bng s tnh ton mc nh ln xung nhp MCU , clkI/O . Khi m bit AS0 trong thanh ghi ASSR c vit mclogic 1 , ngun pht xung nhp c to ra t b to dao ng ca Timer/Counter c kt ni vi TOSC1 v TOSC2. thm chi tit v qu trnh iu khin d b xem thm Asynchronous Status Register ASSR trang 107, bit thm chi tit v ngun pht xung nhp v b m gp trc xem phn Timer/Counter Prescaler trang 110 n v ca b m Phn chnh ca Timer/Counter 8 bit th c th c lp trnh thnh phn b m 2 hng . Hnh 35 ch ra 1 s khi ca 1 counter v mi trng xung quanh ca n

M t tn hiu ( tn hiu bn trong ) Count tng hoc gim TCNT0 bng 1 Direction la chn gia vic tng v gim Clear xa TCNT0 (t tt c cc bit l 0 ) ClkT0 xung nhp Timer/Counter Top c ch rng TCNT0 vn ti gi tr cc i Bottom c ch rng TCNT0 vn ti gi tr cc tiu Ph thuc vo ch iu khin c s dng , b m b xa , c lm tng hoc gim ti mi xung nhp thi gian (clkT0 ) . clkT0 c th c sinh ra t1 ngun pht xung nhp bn ngoi hoc bn trong , c la chn bng cc bit la chn xung nhp (CS02:0) . Khi khng c ngun xung nhp no c la chn (CS02:0=0) timer c dng li . Tuy nhin , gi tr TCNT0 c th c truy nhp bng CPU , bt chp vic xung clkT0 c a ra hay khng . 1 CPU vit ghi ln (c quyn u tin trn ) xa tt c cc counter hoc l cc qu trnh iu khin s m . S m cc chui c xc nh r bng vic ci t ca cc bit WGM01 v WGM00 c t trong thanh ghi iu khin Timer/Counter (TCCR0). C cc kt ni ng gia cch cc b m vn hnh v cch cc dng sng c sinh ra trn u ra so snh u ra OC0 . bit thm chi tit v s m chui hon thin v s sinh ra cc dng sng , xem thm phn Modes oh Operation trn trang 98 C bo Dng trn ca Timer/Counter c ci t theo ch iu khin c la chn bng cc bit WGM01:0 . TOV0 c th c s dng cho vic pht ra cc ngt ca CPU Cc b phn so snh u ra (Output Compare Unit ) Mt b so snh 8 bit lin tc so snh TCNT0 vi thanh ghi so snh u ra (OCR0). Bt c ni no TCNT0 tnh ton OCR0 , b so snh bo hiu 1 match . Mt match s ci t c bo u ra so snh (OCF0) chu k xung nhp timer tip theo . Nu c kch hot (OCIE0=1) , c bo u ra so snh sinh ra 1 ngt u ra so snh . C OCF0 b xa 1 cch t ng khi m ngt c thc thi . Nh mt s la chn , c OCF0 c th c xa bng phn mm bng cch vit mc logic 1 ln v tr bit I/O ca n . B pht dng sng s dng tn hiu ghp sinh ra 1 u vo theo ch iu khin c ci t bi cc bit WGM01:0 v cc bit ch u o so snh (COM01:0) . Tn hiu max v bottom th c s dng bi my pht dng sng cho qu trnh x l trong trng hp c bit ca gi tr cc bin trong mt vi ch iu khin modes of Operation trang 98 . Hnh 36 ch ra s khi ca b phn so snh u ra .

Thanh ghi OCR0 th c lu vo b nh m kp khi s dng bt c xung no ca ch iu ch rng xung (PWM) ..V cc ch iu khin bnh thng v ch so snh trn timer xa , b m kp b v hiu ha . Vic cp nht b m kp ng b ha ca thanh ghi so snh OCR0 hoc l trn top hoc l bottom ca chui m . Vic ng b ha d liu ngn cn s xut hin ca cc di l ( Odd-length ) v cc xung PWM khng i xng , bng cch to ra cc u ra khng c nhiu sc ngang . D liu Thanh ghi OCR0 c th dng nh phc tp , nhng khng phi trong trng hp ny . Khi m b m kp c kch hot , CPU truy nhp vo b m ca thanh ghi OCR0 , v nu b m kp b v hiu ha th CPU s truy nhp trc tip vo OCR0 u ra so snh cng bc trong ch khn phi ch pht dng sng PWM , cng ra ghp ca b so snh c th b cng p bng vic vit l 1 ln bit so snh u ra cng bc (Force Ouput Compare bit FOC0). Vic cng p so snh ghp s khng ci t c OCF0 hoc ti li/xa Timer , nhng chn OC0 s c cp nht li nh l 1 ghp so snh thc xut hin (cc bit COM01:0 ci t xc nh chn OC0 c ci t , b xa hoc dch chuyn ) S kha ghp so snh bng vic vit bit TCNT0 Compare Match Blocking by TCNT0 Write Tt c cc qu trnh vit ca thanh ghi ti thanh ghi TCNT0 s kha bt c ghp so snh no ci m xut hin trong chu k xung nhp k tip , thm ch c khi Timer b dng li . c im ny cho php OCR0 c khi to n cc gi tr ging nh TCTN0 m khng khi ng 1 ngt khi m ng h Timer/Counter c kch hot Using the Output Compare Unit : Vic s dng b phn so snh u ra T khi vic vit TCTN0 trong bt c ch iu khin no s kha tt c cc ghp so snh cho 1 chu k xung nhp timer , c nhng nguy c c hm cha khi s thay i TCNT0

khi s dng knh so snh u ra , iu ny ph thuc vo Timer/Counter ang chy hay khng . Nu gi tr c vit ln TCNT0 bng gi tr OCR0, ghp so snh s b li , kt qu l s pht dng sng khng ng. Mt cch tng t , khng c vit gi tr ca TCNT0 bng vi gi tr BOTTOM khi m counter ang m xung ( m li ) S ci t OC0 nn c thi hnh trc khi vic ci t thanh ghi nh hng d liu cho cc chn cng ln cng ra . Cch d nht cua vic ci t gi tr ca OC0 l s dng u ra so snh cng bc (FOC0) phn tch bit trong ch thng . Thanh ghi OC0 gi gi tr ca n d cho khi thay i gia cc ch pht dng sng (wareform generation modes ) Phi nhn thc rng cc bit COM01:0 th khng c ghi vo b m kp cng nhau vi cc gi tr so snh . Vic thay i cc bit COM01:0 s to hiu qu ngay lp tc Thnh phn u ra ghp so snh Compare Match Output Unit Cc bit ch u ra so snh (COM01:0 ) c hai chc nng . My pht dng sng s dng cc bit COM01:0 xc nh trng thi u ra so snh (OC0 ) ti ghp so snh tip theo (compare match ) . cc bit COM01:0 cng iu khin cc chn ngun u ra OC0. Hnh 37 ch l s rt gn ca cc bit b h hng ca vic ci t bit COM01:0 . Thanh ghi I/O , cc bit I/O , v cc chn I/O trong hnh v c in m . Ch c nhng phn ca thanh ghi iu khin cng I/O chung (DDR v PORT ) ci m b h hng bi cc bit COM01:0 c ch ra . Khi tham kho trng thi OC0 , s tham kho cho thanh ghi OC0 bn trong khng phi l chn OC0 .

Chc nng ca cc chn I/O chung c ghi bi bit so snh u ra (OC0) t my pht dng sng nu mt trong 2 bit COM01:0 c ci t . Tuy nhin , hng ca chn OC0 (u vo hoc u ra th vn c iu khin bi thanh ghi nh hng d liu DDR cho cc chn cng . Bit thanh ghi nh hng d liu cho chn OC0 (DDR_OC0) phi c ci t nh l u ra trc khi gi tr OC0 c nhn thy trn chn . Chc nng ghi cng th ph thuc vo ch pht dng sng Thit k ca chn so snh u ra logic cho php vic khi to ca trng thi OC0 trc khi u ra c kch hot. Ch rng vi vic ci t cc bit COM01:0 l d tr cho cc ch

 bin c bit ca qu trnh iu khin . Xem 8bit Timer/Counter Register Description trang 104 Ch u ra so snh v my pht dng sng My pht dng sng s dng cc bit COM01:0 khc nhau trong cc ch bnh thng , CTC , PWM . Vi tt c cc ch , vic ci t COM01:0 ni cho my pht dng sng rng khng c hnh ng no trn thanh ghi OC0 c tin hnh trn ghp so snh k tip . V phn cc nh hng u ra so snh trong cc ch khng phi PWM tham kho bng 53 trang 105 . Cho cc ch PWM nhanh , tham kho bng 54 trang 105 , v PWM ng pha tham kho bng 55 trang 106 Mt thay i ca trng thi cc bit COM01:0 s c hiu lc ti ghp so snh u tin sau khi cc bit c vit . Cho cc ch khng phi PWM , hot ng c th c cng p c hiu qu ngay lp tc bng vic s dng cc bit phn tch FOC0 Cc ch iu khin Cc ch ca qu trnh iu khin , v d nh trng thi ca Timer/Counter v cc chn so snh u ra th c xc nh bng cch kt hp ch pht dng sng (WGM01:0 ) v ch u ra so snh cc bit (COM01:0). Cc bit ch u ra so snh th khng c nh hng n vic m cc chui trong khi cc bit ch pht dng sng lm vic . Cc bit COM01:0 iu khin u ra PWM c sinh ra nn c khuych i hoc khng (inverted or non-inverted PWM) . V cc ch khng phi PWM , cc bit COM01:0 iu khin hoc u ra nn c ci t , b xa , hoc b dch chuyn ti 1 ghp so snh ( xem bng Compare Match Output Unit trang 97 ) bit thm chi tit tham kho Timer/Counter Timing Diagrams trang 102 Ch bnh thng Ch n gin nht ca qu trnh iu khin l ch bnh thng (normal ) (WGM01:0 = 0 ) . Trong ch ny vic m nh hng th lun hng ln trn ( Incrementing) , v khng c xa b m no c thi hnh . B m n gin trn qua khi n vt qu gi tr cc i 8 bit ca n (TOP=0xFF) v sau khi ng t mc bottom (0x00) . Trong qu trnh iu khin thng thng c bo trn Timer/Counter (TOV0) s c ci t trong cc chu k xung nhp ging nhau nh l TCNT0 tr thnh 0. C TOV0 trong trng hp ny thc hin ging nh 1 bit th 9 , ngoi l l n ch c ci t , khng b xa . Tuy nhin , c ni vi cc cc ngt trn Timer ci m t ng xa c TOV0 , chnh xc ca timer c th c tng ln bng phn mm . Khng c trng hp c bit no xt n trong ch bnh thng , 1 gi tr b m mi c th c vit vo bt c thi gian no . B phn u vo so snh c th c s dng pht ra cc ngt ti mt vi thi gian c a ra trc . Vic s dng so snh u ra pht dng sng trong ch bnh thng th khng c khuyn co , t khi iu ny s chim qu nhiu thi gian ca CPU Xa timer trn ch ghp so snh (Clear Timer on Compare Match Mode CTC )

Trong ch xa Timer trong ch so snh hoc l CTC mode (WGM01:0=2), thanh ghi OCR0 c s dng iu khin chnh xc ca b m . Trong ch CTC b m c xa l 0 khi gi tri ca b m (TCNT0) tng ng vi OCR0 . OCR0 xc nh gi tr nh ca b m , do cng l thay i chnh xc cu n . Ch ny cho php iu khin ln hn ca tn s u ra so snh . N cng rt gn qu trnh iu khin ca vic m cc s kin bn ngoi Gin thi gian cho ch CTC c ch ra trong hnh 38 . Gi tr ca b m(TCNT0) c tng cho n khi 1 ghp so snh xut hin gia TCNT0 v OCR0 v sau b m TCNTO b xa .

Mt ngt c th c sinh ra mi ln m gi tr ca b m vn ti gi tr TOP bng vic s dng c OCF0 . Nu nh ngt c kch hot , cc chng trnh con iu khin ngt c th c s dng cp nht gi tr TOP . Tuy nhin , vic thay i TOP n 1 gi tr ng Bottom khi m b m ang chy vi 0 hoc 1 gi tr thp ca b m gp trc phi c lm vi s cn thn t khi ch CTC c c im l b m kp . Nu gi tr mi c vit ln OCR0 thp hn gi tr hin thi ca TCNT0 , b m s b li ghp so snh . B m sau phi m t gi tr cc i ca n (0xFF) v bc xung quanh im khi u 0x00 trc khi ghp so snh c th xut hin . V vic pht ra mt dng sng u ra trong CTC mode , u ra OC0 c th c ci t di chuyn mc logic ca n trn mi ghp so snh bng vic ci t cc bit ch u ra so snh ti ch Toggle (COM01:0=1 ). Gi tr OC0 s khng c nhn thy trn chn cng tr phi vic nh hng d liu cho cc chn c ci t ti u ra . Dng sng c pht ra s c mt tn s cc i ca fOC0 = fclk_I/O/2 khi m OCR0 c ci t l 0 (0x00) . Tn s dng sng c xc nh bng cng thc di y : Bin N c trnh by theo t l cho trc (1,8, 32,64,128,256, hoc 1024) Cho ch thng ca qu trnh iu khin , c TOV0 c ci t trong cc chu k xung nhp khc nhau ci m b m m t MAX n 0x00 Ch Fast PWM : xung PWM c nh

 rng xung iu ch c nh hoc ch Fast PWM (WGM01:0 = 3 ) cung cp 1 s la chn pht dng sng PWM tn s cao . Ch fast PWM khc cc la chn PWM khc bng cc ch iu khin sn n . B m m t mc BOTTOM n MAX sau khi ng li t BOTTOM . Trong ch u ra so snh khng o , bit so snh u ra (OC0) b xa trn ghp so snh gia TCNT0 v OCR0 , v t BOTTOM . tng xng vi ch iu khin sn n , qu trnh iu khin tn s ca ch fast PWM c th c cao gp i nh l cc pha ng ca ch PWM ci m c s dng qu trnh iu khin 2 sn . Tn s cao ny lm cho ch fast PWM ph hp vi s iu chnh ngun , s chnh lu v cc ng dng DAC . Tn s cao ny cho php cc thnh phn vt l c nh (cun dy , t in ) v v vy gim gi thnh ca h thng . Trong ch Fast PWM , b m c lm tng cho n khi gi tr ca b m tng ng vi gi tr MAX . B m th sau c xa ti chu k xung nhp timer bn di . Gin thi gian cho ch Fast PWM c a ra trn hnh 39 . Gi tr ca TCNT0 trong gin thi gian ch ra nh l 1 biu minh ha cho qu trnh iu khin sn n . Gin bao gm cc u ra PWM o v khng o .ng nm ngang nh nh du trn cc sn TCNT0 c a ra cc ghp so snh gia OCR0 v TCNT0

C bo trn Timer/Counter TOV0 c ci t mi ln b m tin ti gi tr MAX nu nh ngt c kch hot , chng trnh con iu khin ngt c th c s dng cho vic cp nht cc gi tr so snh Trong ch Fast PWM , b phn so snh cho php vic pht ra cc dng sng PWM trn chn OC0 . Vic ci t cc bit COM01:0 ln 2 s gy ra 1 xung PWM khng o v 1 u ra PWM o c th c pht ra bng vic ci t COM01:0 ln 3 ( xem bng 54 trang 105 ) . Gi tr thc ca OC0 s ch c nhn thy trn chn cng nu nh hng d liu cho chn cng c ci t nh l cng ra . Dng sng PWM c pht ra bng vic ci t hoc (xa ) thanh ghi OC0 ti ghp so snh gia OCR0 v TCNT0 , v vic xa (hoc ci t ) thanh ghi OC0 ti thi gian chu k xung nhp b m c xa ( thay i t MAX n BOTTOM ) Tn s PWM cho u ra c th c tnh bng cng thc sau y:

Bin N c a ra theo t l xch (1 , 8 , 32 , 64 , 128, 256, 1024 ) Gi tr cc i ca thanh ghi OCR0 c a ra trong cc trng hp c bit khi m s pht ra mt dng sng u ra PWM trong ch Fast PWM . Nu nh OCR0 c ci t bng gi tr BOTTOM , u ra s l cc nh nhn v hp cho mi mt chu k xung nhp MAX+1 . Vic ci t OCR0 bng MAX s l hiu qu trong 1 u ra c gi tr cao hoc thp l hng s ( s ph thuc vo phn cc ca u ra c ci t bng cc bit COM01:0 ) Mt tn s (vi 50% ti lm vic ) ca dng sng u ra trong ch PWM c th t c bng vic ci tOC0 di chuyn cc mc logic ca n trn mi ghp so snh (COM01:0 =1) . Dng sng c pht ra s c 1 gi tr cc i ca fOC0 = fclk_I/O/2 khi m OCR0 c ci t l 0 . c im ny th tng t nh s di chuyn OC0 trong ch CTC . , ngoi tr c im ca b m kp ca b phn so snh u ra c kch hot trong ch fast PWM Ch PWM ng pha Ch PWM ng pha (WGM1:0 =1) cung cp 1 s la chn pht cc dng sng PWM ng pha c chnh xc cao . Ch ng pha PWM c bn l qu trnh iu khin xung n . B m m lp li t BOTTOM n MAX v sau t MAX n BOTTOM . Trong ch u ra so snh khng o , so snh u ra (OC0) c xa trn cc ghp so snh gia TCNT0 v OCR0 trong qu trnh m ln , v c ci t trn ghp so snh trong khi m xung . Trong ch so snh u ra o , qu trnh iu khin c o .Qu trnh iu khin 2 sn c tn s hot ng ln nht thp hn qu trnh iu khin sn n . Tuy nhin , so c tnh i xng ca cc ch PWM 2 sn , cc ch ny c a thch hn trong cc ng dng iu khin ng c . chnh xc ca PWM cho ch PWM ng pha l 8 bit bn vng . Trong ch PWM ng pha b m c lm tng cho n khi gi tr ca b m tng ng viMAX khi m b m tin ti MAX , n thay i hng m . Gi tr TCNT0 s bng vi MAX cho 1 chu k xung nhp thi gian . Gin thi gian cho ch PWM ng pha c a ra trong hnh 40 . Gi tr TCNT0 trong gin thi gian ch ra nh l 1 biu minh ha cho qu trnh iu khin 2 sn . Gin bao gm cc u vo PWM o v khng o . ng nm ngang nh nh du sn TCNT0 c a ra trn ghp so snh gia OCR0 v TCNT0.

C bo trn Timer/Counter c t mi ln b m tin ti BOTTOM . C ngt c th c s dng sinh ra 1 ngt mi ln b m tin ti gi tr BOTTOM . Trong ch PWM ng pha , b phn so snh cho php pht sinh ra cc dng sng PWM trn chn OC0 . Vic ci t cc bit COM01:0 ln 2 s gy ra 1 xung PWM khng o. Mt u ra PWM o c th c sinh ra bng vic ci t COM01:0 ln 3 ( xem bng 55 trang 106 ) . Gi tr thc s ca OC0 s ch c nhn thy trn chn cng nu nh s nh hng d liu cho cc chn cng c ci t nh l u ra . Dng sng PWM c sinh ra bng cch xa (hoc ci t ) thanh ghi OC0 ti ghp so snh gia OCR0 v TCNT0 khi m b m tng v vic ci t ( hoc xa ) thanh ghi OC0 ti ghp so snh gia OCR0 v TCNT0 khi m b m gim . Tn s ca PWM cho u ra khi vic s dng ch PWM ng pha c th c tnh ton bng cng thc di y :

Bin N c a ra theo t l xch (1 , 8 , 32, 64 , 128 , 256, 1024 ) Gi tr cc bin ca thanh ghi OCR0 c a ra trong trng hp c bit khi m s sinh ra 1 u ra dng sng PWM trong ch PWM ng pha . Nu nh OCR0 c ci t bng BOTTOM , u ra s tip tc mc thp v nu n ci t bng MAX th u ra s tip tc mc cao cho ch PWM khng o . V ch PWM o th u ra s c cc gi tr logic i lp mi im bt u ca chu k 2 trong hnh 40 Ocn c s chuyn i t cao xung thp mc d khng c ghp so snh no . im nh du ca s thay i ny c m bo i xng xung quanh BOTTOM . C hai trng hp c a ra 1 s chuyn i m khng ghp so snh : - OCR0 thay i gi tr ca n t MAX , ging nh hnh 40 . Khi m gi tr ca OCR0 l MAX , gi tri ca chn Ocn th ging nh kt qu ca vic m xung ghp so snh . m bo tnh i xng xung quanh BOTTOM , gi tr Ocn tiMAX phi c tng ng vi kt qu ca vic m ln ghp so snh . - Timer bt u m t gi tr cao hn v gi tr thp hn trong OCR0 , v v l do ny cc li ca ghp so snh v do OCn thay i ci m s xy ra trong chiu ln .

Gin thi gian ca Timer/Counter Hnh 41 v hnh 42 bao gm d liu thi gian cho qu trnh iu khin Timer/Counter . Timer/Counter th c thit k ng b v cc xung nhp timer (clkT0) do vy c ch ra nh l 1 xung nhp kch hot tn hiu. Hnh ny ch ra chui m ln cc gi tr MAX . Hnh 43 v 44 ch ra cc d liu thi gian ging nhau , nhng vi cc b m gp trc c kch hot . Cc hnh cng minh ha khi cc c ngt c ci t . Cc hnh bn di ch ra Timer/Counter trong ch ng b , v xung nhp timer (clkT0) th do vy c ch ra nh l 1 xung kch hot cc tn hiu . Trong ch d b , clkI/O nn c thay th bng xung nhp ca b to dao ng Timer/Counter . Cc hnh bao gm thng tin v khi cc c bo ngt c ci t . Hnh 44 bao gm d liu thi gian cho qu trnh iu khin Timer/Counter c bn . Hnh ny cng ch ra cc chui m ng ln gi tr MAX trong tt c cc ch khc hn ch PWM ng pha

Hnh 42 ch ra cc d liu thi gian ging nhau , nhng vi cc b m gp trc kch hot

Hnh 43 ch ra cch ci t OCF0 trong tt c cc ch tr ch CTC

Hnh 44 ch ra cch ci t ca OCF0 v xa TCNT0 trong ch CTC

S miu t cc thanh ghi ca Timer/Counter 8 bit 8bit Timer/Counter Register Description Thanh ghi iu khin Timer/Counter TCCR0

Bit 7 FOC0 : Force Output Compare ( so snh u ra cng bc )

Bit FOC0 ch c hot ng khi m cc bit WGM xc nh1 ch khng phi l PWM . Tuy nhin , m bo tnh tng thch vi cc thit b trong tng lai , bit ny phi c ci l 0 khi m TCCR0 c vit khi hot ng trong ch PWM . Khi vic vit mt mc logic 1 ln bit FOC0 , 1 ghp so snh trung gian b cng bc trn b phn pht dng sng . u ra OC0 b thay i theo vic ci t cc bit COM01:0 ca n . Ch rng bit FOC0 c ci t nh l 1 strobe . Do vy n l 1 gi tr a ra trong cc bit COM01:0 ci m xc nh r hiu lc ca vic so snh cng bc . 1 s phn tch FOC0 s khng sinh ra bt c ngt no , hoc n s xa cc timer trong ch CTC s dng OCR0 nh l TOP . Bit FOC0 th lun c c nh l 0 Bit 6, 3 WGM01:0 : ch pht sinh dng sng Cc bit ny iu khin cc chui m ca b m , ngun cho gi tr m cc i (TOP), v loi no ca s sinh ra cc dng sng c s dng . Cc ch iu khin c h tr bi Timer/Counter l : Normal mode , Clear Timer on Compare match (CTC) mode , v 2 loi ca ch iu ch rng xung PWM .Xem thm bng 52 v modes of Operation trang 98

Bit 5 ,4 - COM01:0 : ch u ra ghp so snh Cc bit ny iu khin vic x l cc chn so snh u ra (OC0) . Nu 1 hoc c hai trong cc bit COM01:0 c ci t , u ra OC0 ghi ln cng chc nng thng thng ca chn I/O c kt ni vi n . Tuy nhin , ch rng bit thanh ghi nh hng d liu (DDR ) tng ng vi chn OC0 phi c ci t m kch hot b iu khin u ra Khi m OC0 c kt ni ti chn , chc nng ca cc bit COM01:0 ph thuc vo vic ci t cc bit WGM01:0 . Bng 53 ch ra cc bit chc nng COM01:0 khi m cc bit WGM01:0 c ci t ln mt ch normal hoc ch CTC mode ( khng phi PWM)

Bng 54 ch ra cc bit chc nng COM01:0 khi m cc bit WGM01:0 c ci t trong ch fast PWM

Bng 55 ch ra bit chc nng COM01:0 khi m WGM01:0 c ci t trong ch PWM ng pha

Bit 2:0 : la chn ch kha Cc bit la chn ch kha ngun kha c s dng bi Timer/Counter xem bng 56

Thanh ghi Timer/Counter - TCNT0

Thanh ghi Timer/Counter a ra s truy nhp trc tip , c hai qu trnh iu khin c v ghi , ln b m 8bit ca Timer/Counter . Vic vit ln cc kha thanh ghi (g b ) ghp so snh trn cc xung nhp timer di y . S thay i ca b m (TCNT0) trong khi b m ang chy , a ra 1 nguy c ca vic li 1 ghp so snh gia TCNT0 v thanh ghi OCR0 Thanh ghi so snh u ra - OCR0

Thanh ghi so snh u ra bao gm 1 gi tr 8 bit m c th tip tc c so snh vi gi tr ca b m ( TCNT0) . Mt s ghp c th c s dng sinh ra 1 ngt so snh u ra , hoc sinh ra 1 u ra dng sng trn chn OC0 S hot ng khng ng b ca Timer/Counter Thanh ghi trng thi khng ng b - ASSR

Bit 3 AS0 : Timer/Counter0 d b Khi AS0 c vit l 0 , Timer/Counter 0 b kha khi xung nhp I/O , clkI/O. Khi AS0 c vit l 1 , Timer/Counter b kha khi 1 b to dao ng thch anh c kt ni vi chn ca b to dao ng timer 1 (TOSC1 ) . Khi m gi tr ca AS0 b thay i , thnh phn ca TCNT0 , OCR0 v TCCR0 c th b h hng Bit 2 TCN0UB : Timer/Counter cp nht cc trng thi bn (Timer/Counter0 Update Busy ) Khi Timer/Counter0 hot ng mt cch d b v TCNT0 c ghi , bt ny c ci t . Khi TCNT0 c cp nht t thanh ghi lu tr tm thi , bit ny c xa bng phn cng . 1 mc logic 0 trong bit ny hin th ci m TCNT0 sn sng c cp nht vi 1 gi tr mi . Bit 1 OCR0UB : thanh ghi 0 cp nht trng thi bn so snh u ra Khi Timer/Counter 0 hot ng mt cch d b v bit OCR0 c ghi , bit ny c ci t . Khi OCR0 c cp nht t thanh ghi lu tr tm thi , bit ny c xa bng phn cng . 1 mc logic 0 trong bit ny hin th ci m OCR0 sn sng c cp nht vi 1 gi tr mi . Bit 0 TCR0UB Thanh ghi0 iu khin Timer/Counter cp nht trng thi bn Khi Timer/Counter 0 hot ng mt cch d b v bit TCCR0 c ghi , bit ny c ci t . Khi TCCR0 c cp nht t thanh ghi lu tr tm thi , bit ny c xa bng phn cng . 1 mc logic 0 trong bit ny hin th ci mTCCR0 sn sng c cp nht vi 1 gi tr mi Nu 1 qu trnh ghi c tin hnh ln bt c ci no trong 3 thanh ghi ca Timer/Counter0 trong khi c cp nht ch bn c ci t , gi tr cp nht c th c h hng v gy ra vic 1 ngt v tnh xut hin . B phn cho vic c TCNT0 , OCR0 v TCCR0 th khc nhau . Khi vic c TCNT0, gi tr timer thc c c . Khi c OCR0 hoc TCCR0 , gi tr trong thanh ghi lu tr tm thi c c Qu trnh iu khin d b ca Timer/Counter0

Khi Timer/Counter 0 hot ng d b , 1 vi s ch n phi c xem xt - Cnh bo : khi chuyn mch gia cc b nh thi ng b v khng ng b ca Timer/Counter0 , thanh ghi Timer TCNT0 , OCR0 v TCCR0 c th h hng . Mt quy trnh an ton cho vic chuyn mch cc ngun xung nhp l : 1. V hiu ha cc ngt ca Timer/Counter0 bng vic xa OCIE0 v TOIE0 2. la chn ngun pht xung nhp bng vic ci t AS0 nh c ph chun 3. vit gi tr mi ln TCNT0 , OCR0 , v TCCR0 4. chuyn mch sang qu trnh iu khin d b : i TCN0UB , OCR0UB , TCR0UB 5. xa cc c ngt ca Timer/Counter0 6. Kch hot cc ngt nu thy cn thit - B to dao ng th c ti u cho vic s dng vi ng h thch anh 32.768 kHz . Vic p dng mt xung nhp ngoi ln chn TOSC1 c th c kt qu sai trong qu trnh iu khin Timer/Counter 0 . Tn s Xung nhp chnh ca CPU phi ln hn 4 ln tn s ca b to dao ng - Khi vit ti 1 trong s cc thanh ghi TCNT0 , OCR0 v TCCR0 , gi tr c chuyn vo trong 1 thanh ghi tm thi , v c cht sau 2 sn dng trn TOSC1 . Ngi s dng khng nn vit 1 gi tr mi trc khi dung lng ca thanh ghi tm thi c chuyn n ch n ca n . Mi 1 thanh ghi trong 3 thanh ghi c ni n u c thanh ghi ring bit ca chng , iu ny c ngha l v d : vic vit ln TCNT0 khng gy nhiu 1 qu trnh ghi trong OCR0 ang c tin hnh . d 1 s chuyn n thanh ghi ch xy ra hay cha , th thanh ghi trng thi d b - ASSR phi c ci t . - Khi truy nhp vo ch Power-save hoc ch Extended Standby sau khi ang c vit ln TCNT0 , OCR0 hoc TCCR0 ,ngi s dng phi i cho n khi thanh ghi c vit c cp nht nu Timer/Counter0 c s dng nh thc thit b . Ni cch khc MCU s truy nhp vo ch ng trc khi cc s thay i c hiu lc . iu ny th c bit quan trng nu nh b ngt so snh u ra 0 c s dng nh thc thit b ny , t khi chc nng so snh u ra c v hiu ha trong sut qu trnh vit ln OCR0 hoc TCNT0 . Nu chu k vit khng hon thnh , v MCU truy nhp vo ch ng trc khi bit OCR0UB c tr li l 0 , thit b ny s khng bao gi nhn ngt ghp so snh , v MCU s khng c nh thc. - Nu Timer/Counter0 c s dng nh thc thit b t ch Power-save hoc ch Extended Standby , 1 s phng nga phi c thc hin nu ngi s dng mun truy nhp li vo 1 trong cc ch ny : Mc logic ngt cn thit1 chu k xung TOSC1 Reset . Nu thi gian gia qu trnh nh thc v truy nhp li cc ch ng nh hn 1 chu k TOSC1 , ngt s khng xut hin v thit b s b li khi ng . Nu ngi s dng nghi ng 1 trong 2 khong thi gian trc khi ng nhp li vo ch Power-save hoc ch Extended Standby l ch n nh hay khng, thut ton di y c th c s dng m bo rng 1 chu k TOSC1 c kt thc . 1. Vit 1 gi tr ln TCCR0 , TCNT0 hoc OCR0 2. i cho n khi c cp nht trng thi bn tng ng trong thanh ghi ASSR l 0

3. truy nhp vo ch Power-save hoc ch Extended Standby - Khi m qu trnh iu khin d b c la chn , b to dao ng 32.768 kHz cho Timer/Counter0 lun ang chy , ngoi tr trong ch Power-downhoc ch Standby . Sau khi 1 s Reset bt ngun hoc nh thc t ch Power-down hoc ch Standby , ngi s dng nn nhn bit 1 cch chnh xc rng b to dao ng c th ly i ch cn 1s n nh . Ngi s dng th c khuyn i trong khong thi gian nh hn 1s trc khi s dng Timer/Counter 0 sau khi bt ngun hoc nh thc t ch ngt ngun hoc ch ch . Dung lng ca tt c cc thanh ghi phi c xt n tn tht trc sau khi c nh thc t ch ngt ngun hoc ch ch xng vi tn hiu xung nhp khng n nh trn start up . Thc cht ch mt trong 2 th l b to dao ng c s dng hoc tn hiu xung nhp ng h c p dng cho chn TOSC1 - S miu t ca vic nh thc t ch Power-save hoc ch Extended Standby khi c kha d b : khi iu kin ngt c ph hp , tin trnh nh thc c khi ng trn cc chu k ca xung nhp timer bn di , ci m Timer lun c hon thin bi di 1s trc khi b x l c th c cc gi tr ca b m . Sau khi nh thc , MCU b dng trong 4 chu k xung nhp , n thc thi cc chng trnh con phc v ngt , v ni tip cc s thc thi t cc lnh di lnh SLEEP - Qu trnh c ca thanh ghi TCNT0 ngn sau khi c nh thc t ch tit kim ngun c th a ra 1 kt qu khng chnh xc . T khi TCNT0 b kha trn kha khng ng b TOSC , vic c TCNT0 phi c thc hin thng qua 1 thanh ghi c ng b ha ti cc vng xung nhp I/O bn trong . Qu trnh ng b phi c xy ra cho mi sn ln ca TOSC1 . Khi m s nh thc khi ch Power-save , v cc xung nhp I/O hot ng tr li , TCNT0 s c c nh l gi tr trc( trc khi truy nhp vo ch ng ) cho n khi c sn ln tip theo ca TOSC1 . Pha ca xung nhp TOSC sau qu trnh nh thc t ch tit kim ngun th khng th tin on trc mt cch c bn , nh n ph thuc vo thi gian nh thc . Quy trnh c ngh cho vic c TCNT0 th c ch ra di y : 1. Vit bt c gi tr no ti 1 trong 2 thanh ghi OCR0 hoc TCCR0 2. i cho c cp nht trng thi bn tng ng c xa 3. c TCNT0 - trong sut qa trnh iu khin d b, s ng b ho ca cc c ngt trong khong thi gian d b to ra ba chu k xung nhp ca b vi s l nhiu hn trong 1 chu k. B nh thi do vy c nng cao bi mt b phn trc khi b vi s l c th c gi tr thi gian ca vic ci t cc c ngt. Cc chn so snh cng ra c thay i trn cc b nh thi v khng c ng b ha ti cc xung nhp ca b vi s l thanh ghi che cc ngt ca Timer/Counter TIMSK

Bit 1 OCIE0 : kch hot cc ngt ghp so snh u ra Timer/Counter0

Khi m bit OCIE0 c vit l 1 , v bit I trong thanh ghi trng thi c t l 1 , ngt ghp so snh Timer/Counter 0 c kch hot . Ngt tng ng c thc thi nu 1 ghp so snh trong Timer/Couter0 xut hin v d nh khi bit OCF0 c ci t trong thanh ghi c bo ngt Timer/Counter TIFR Bit 0 TOIE0 : kch hot ngt trn Timer/Couter0 Khi m bit TOIE0 c vit l 1 , v bit I trong thanh ghi trng thi c ci t l 1 , ngt dng trn Timer/Couter0 c kch hot v d nh khi bit TOV0 c ci t trong thanh ghi c bo ngt TIFR Thanh ghi c bo ngt Timer/Counter TIFR

Bit 1 OCF0 : c bo so snh u ra 0 Bit OCF0 c ci t l 1 khi 1 ghp so snh xut hin gia Timer/Counter 0 v d liu trong OCR0 Output Compare Register 0 . OCF0 b xa bng phn cng khi m s thc thi cc vec to iu khin ngt tng ng. Nh mt s la chn , OCF0 b xa bng vic vit 1 mc logic 1 ln c . Khi m bit I trong SREG, OCIE0 (kch hot ngt ghp so snh Timer/Counter 0 ) , v OCF0 c ci t l 1 , ngt ghp so snh Timer/Counter 0 c thc thi Bit 0 TOV0 : c bo trn Timer/Counter0 Bit TOV0 c ci t l 1 khi 1 dng trn xut hin trong Timer/Counter 0. TOV0 b xa bng phn cng khi m vic thc thi cc vec t iu khin cc ngt tng ng . Nh mt s la chn , TOV0 b xa bng vic vit 1 mc logic 1 ln c . Khi m Bit I SREG ,TOIE0 (kch hot c bo ngt trn Timer/Counter ), v TOV0 c ci t l 1 , ngt trn Timer/Counter 0 c thc thi . Trong ch PWM , bit ny c ci t khi Timer/Counter 0 thay i hng m ti $00 B m gp trc Timer/Counter Timer/Counter Prescaler

Ngun pht xung nhp cho Timer/Counter0 c t tn l clkT0 . clkT0 th c mc nh kt ni ti xung nhp chnh ca h thng clkI/O . Bng vic ci t bit AS0 trong ASSR , Timer/Counter0 c kha 1 cch d b t chn TOSC1 . iu ny kch hot s dng ca Timer/Counter0 nh l mt b m thi gian thc (Real Time Counter RTC ) . Khi bit AS0 c ci t , cc chn TOSC1 v TOSC2 c ngt kt ni khi cng C . Mt b to dao ng thch anh c th sau c kt ni gia cc chn TOSC1 v TOSC2 phc v nh l 1 ngun pht xung nhp c lp cho Timer/Counter0 . B to dao ng th c ti u ha s dng vi b to dao ng thch anh 32.768 kHz . Vic p dng mt ngun pht xung nhp ngoi ln TOSC1 th khng c khuyn khch . V Timer/Counter0 , s la chn t l l c th : clkTOS/8 , clkTOS/32 , clkTOS/64 , clkTOS/128 , clkTOS/256 , clkTOS/1024 . Thm na , clkTOS cng nh 0 (stop) c th c la chn . Vic ci t bit PSR0 trong SFIOR khi ng li b m gp trc . iu ny cho php ngi s dng iu khin vi 1 b m gp trc c th tin on trc Thanh ghi I/O chc nng c bit - Special Function I/O Register SFIOR

Bit 7 TSM : ch ng b ha Timer/Counter Vic vit bit TSM ln 1 kch hot ch ng b ha Timer/Counter . Trong ch ny , gi tr m c vit ln PSR0 v PSR321 th c gi , d cho vic gi cc b m gp trc tng ng s reset cc tn hiu c xc nhn . iu ny cng m bo rng cc b Timer/Counter tng ng c dng v c th c cu hnh ti cc gi tr ging nhau m khng c nguy c hng ca mt trong s chng trong sut qu trnh cu hnh . Khi bit TSM c vit l 0 , cc bit PSR0 v PSR321 b xa bi phn cng , v Timer/Counter bt u qu trnh m 1 cch lin tc. Bit 1 PSR0 : b m gp trc reset Timer/Counter0

Khi bit ny l 1 , b m gp trc ca Timer/Counter s c reset . Bit ny th thng c xa ngay lp tc bng phn cng . Nu bit ny c vit trong khi Timer/Counter ang hot ng trong ch d b , bit ny s cn li 1 cho n khi b m gp trc c reset xong . bit ny s khng c xa bng phn mm nu bit TSM c ci t .

XII . Timer/Counter 16 bit (Timer/Counter 1 v Timer/Counter 3)

B phn Timer/Counter 16 bit cho php nh thi gian cc qu trnh thc thi chng trnh mt cch chnh xc (qun l s kin ) , pht sinh ra cc sng , v o thi gian tn hiu .Cc c im chnh l - Thit k 16 bit tht (v d ,cho php 16bit PWM ) - 3 b phn so snh u ra c lp - Cc thanh ghi so snh u ra c ghi vo b m kp - B phn bt u vo - Kha ct nhiu u vo - Xa timer trn ghp so snh (t ng ti li ) - Khng c nhiu sc ngang , iu ch rng xung ng pha ( PWM ) - Chu k PWM thay i - My pht tn s - B m s kin bn ngoi - 10 ngun ngt c lp (TOV1 , OCF1A , OCF1B , OCF1C , ICF1 , TOV3 , OCF3A , OCF3B , OCF3C , ICF3 ) S hn ch trong ch tng thch vi Atmega 103 Ch rng trong ch tng thch vi Atmega 103 , ch c 1 Timer/Counter 16 bit l kh dng(Timer/Counter 1) . Cng ch thm rng trong ch tng thch vi Atmega 103 , Timer/Counter 1 c hai thanh ghi so snh( compare A v compare B ) Tng quan Tt c cc thanh ghi v cc bit tham kho trong phn ny c vit theo dng chung . 1 trng hp thp hn n thay th cho th t ca Timer/Counter , v mt trng hp thp hn na x thay th cho knh b phn so snh u ra . Tuy nhin , khi s dng thanh ghi hoc bit xc nh trong mt chng trnh , mt mu chnh xc phi c s dng v d nh TCNT1 cho vic truy nhp vogi tr b m Timer/Counter 1. Mt s khi rt gn ca Timer/Counter 16 bit c ch ra trong hnh 46. V v tr tht s ca cc chn I/O tham kho phn Pin Configurations trang 2 . CPU c th truy nhp vo cc thanh ghi I/O, bao gm cc bit I/O , c in m . Thanh ghi I/O xc nh thit b v cc bit v tr c lit k trong 16bit Timer/Counter Register Description trang 133.

Cc thanh ghi Timer/Counter (TCNTn), thanh ghi so snh u ra (OCRnA/B/C), v thanh ghi bt tn hiu u vo (ICRn) tt c u l cc thanh ghi 16 bit . Cc quy trnh c bit phi c tun theo khi truy nhp vo cc thanh ghi 16bit. Cc quy trnh ny c miu t trong phn Accessing 16bit Register trang 115 . Cc thanh ghi iu khin Timer/Counter (TCCRnA/B/C)l cc thanh ghi 8 bit v khng c s hn ch i vi quyn truy nhp ca CPU . Cc tn hiu yu cu ngt (vit tt Int.Req.) u c nhn thy trong thanh ghi c bo ngt Timer (TIFR)v thanh ghi c bo ngt Timer m rng (ETIFR). Tt c cc ngt u c che ring bit vi thanh ghi che ngt Timer (TIMSK) v thanh ghi che ngt Timer m rng (ETIMSK) . (E)TIFR v (E)TIMSK u khng c ch ra trong hnh v t khi cc thanh ghi ny c chia s bi cc b phn Timer khc . Timer/Counter c th b kha bn trong , bng b m gp trc hoc bng1 ngun xung nhp ngoi trn chn Tn. Khi logic la chn xung nhp iu khin ci m ngun pht xung nhp v sn ca Timer/Counter s dng lm tng (hoc gim ) gi tr ca n . Timer/Counter th khng hot ng khi khng c ngun pht xung nhp no c la chn . u ra t logic la chn xung nhp c tham kho nh l 1 xung nhp Timer (clkTn) Cc thanh ghi so snh u ra c ghi vo b m kp (OCRnA/B/C) th c so snh vi gi tr ca Timer/Counter tt c cc thi im . Kt qu ca vic so snh c th c s

dng bi my pht dng sng pht ra 1 PWM hoc l 1 u ra tn s thay i trn chn so snh u ra (OcnA/B/C) Xem thm phn Output Compare Units trang 121 . s kin ghp so snh cng s t c ghp so snh (OCFnA/B/C ) ci m c th c s dng sinh ra 1 yu cu ngt so snh u ra . Thanh ghi bt u vo c th bt gi tr ca Timer/Counter ti 1 v tr c a ra bn ngoi (sn khi ng ) s kin trn chn bt tn hiu cng ra (ICPn) hoc trn cc chn ca b so snh tng t (xem Analog Comparatortrn trang 227 . B phn bt tn hiu u vo bao gm 1 b lc s ( b ct nhiu ) cho vic gim cc thay i ca vic bt cc nh nhiu . Gi tr TOP , hoc gi tr cc i Timer/Counter , c th trong 1 vi ch ca qu trnh iu khin c xc nh bng thanh ghi OCRnA ,hoc ICRn , hoc bng vic ci t mt gi tr n nh . Khi vic s dng OCRnA nh l gi tr TOP trong ch PWM , thanh ghi OCRnA khng th c s dng cho vic pht sinh ra 1 u ra PWM . Tuy nhin , gi tr TOP trong trng hp ny s c ghi vo b m kp cho php gi tr TOP c thay i trong thi gian chy . Nu nh gi tr TOP n nh l cn thit , thanh ghi ICRn c th c s dng nh l mt s lun phin , s t do ca thanhnh OCRnA c s dng nh l u ra PWM . Cc nh ngha Cc nh ngha di y c s dng 1 cch rng ri xuyn sut ti liu ny .

S tng thch Timer/Counter 16bit c nhiu cp nht v ci tin t cc phin bn trc ca Timer/Counter 16bit ca AVR . Timer/Counter 16 bit ny c th tng thch y vi cc phin bn sm hn . - Tt c cc Timer/Counter 16bit u lin quan n cc v tr a ch thanh ghi I/O , bao gm cc thanh ghi ngt timer - Cc v tr bit bn trong tt c cc thanh ghi Timer/Counter 16bit , bao gm cc thanh ghi ngt Timer - Cc vc t ngt Cc bit iu khin di y c thay i tn , nhng c cng chc nng v v tr cc thanh ghi - PWMn0 c chuyn thnh WGMn0 - PWMn1 c chuyn thnh WGMn1 - CTCn c chuyn thnh WGMn2

Cc thanh ghi di y th c thm vo Timer/Counter 16bit : - Thanh ghi iu khin Timer/Counter C (TCCRnC) - Thanh ghi so snh u ra C , OCRnCH v OCRnCL , c ni vi OCRnC Cc bt di y c thm vo thanh ghi iu khin Timer/Counter 16bit - COM1C1:0 c thm vo TCCR1A - FOCnA , FOCnB v FOCnC c thm vo thanh ghi mi TCCRnC - WGMn3 c thm vo TCCRnB C ngt v cc bit che cho b phn so snh u ra C c thm vo Timer/Counter 16bit c s hon thin m s c hiu lc tng thch trong vi trng hp c bit Cc thanh ghi 16 bit truy nhp Accessing 16bit Registers TCNTn , OCRnA/B/C , v ICRn u l cc thanh ghi 16bit ci m c th c truy nhp bi CPU AVR thng qua bus d liu 8bit . Thanh ghi 16bit phi c nh a ch byte s dng 2 qu trnh c v ghi . Mi Timer 16bit c 1 thanh ghi n 8bit cho vic lu tr tm thi ca cc byte cao ca vic truy nhp 16bit . Thanh ghi tm thi ging nhau c chia s gia tt c cc thanh ghi 16bit trong mi timer 16bit . S truy nhp cc byte thp khi ng qu trnh c v ghi 16bit . Khi byte thp ca thanh ghi 16bit c vit bi CPU , byte cao c lu tr trong thanh ghi tm thi , v byte thp vit c hai c sao chp vo trong thanh ghi 16 bit trong chu k xung nhp ging nhau . Khi byte thp ca 1 thanh ghi 16bit c c bi CPU , byte cao ca thanh ghi 16bit c sao chp vo trong thanh ghi tm thi trong chu k xung nhp ging nhau nh lfa byte thp c c Khng phi tt c cc s truy nhp 16bit s dng thanh ghi tm thi cho byte cao . Vic c cc thanh ghi OCRnA/B/C th khng bao hm vic s dng thanh ghi tm thi (Temporary Register) lm vic vit 16bit , byte cao phi c vit trc byte thp . V 1 qu trnh c 16bit , byte thp phi c c trc byte cao on code mu di y ch ra cch truy nhp cc thanh ghi 16bit Timer gi nh rng khng c ngt no c cp nht vo thanh ghi tm thi . Nguyn tc ging nh vy c th c s dng 1 cch trc tip cho vic truy nhp cc thanh ghi OCRnA/B/C v cc thanh ghi ICRn . Ch rng khi s dng C , trnh bin dch iu khin s truy nhp 16bit

N th rt quan trng nhn bit rng vic truy nhp cc thanh ghi 16bit l qu trnh hot ng nguyn t . Nu nh mt ngt xut hin gia 2 lnh truy nhp thanh ghi 16bit , v m ngt cp nht thanh ghi tm thi bng vic truy nhp cc thanh ghi Timer ging nhau hoc bt c thanh ghi timer no khc , sau kt qu ca vic truy nhp bn ngoi cc ngt s b h hng . V vy , khi c hai on m chnh v s cp nht cc ngt vo thanh ghi tm thi, on m chnh phi v hiu ha cc ngt trong sut s truy nhp 16bit on m mu di y ch ra cch lm 1 qu trnh c nguyn t ca cc thnh phn ca thanh ghi TCNTn .Vic c bt c thanh ghi OCRnA/B/C hoc ICRn c th thc hin bng cch s dng cc nguyn tc ging nhau .

V d on m Assembly tr li gi tr ca TCNTn trong cp thanh ghi r17:r16 on m mu di y ch ra cch lm 1 qu trnh vit nguyn t ca cc thnh phn ca thanh ghi TCNTn . Vic vit bt c cc thanh ghi OCRnA/B/C hoc ICRn c th c thc hin bng cc nguyn l ging nhau .

Kh nng dng li ca thanh ghi byte cao tm thi . Nu vic vit vo nhiu hn 1 thanh ghi 16bit ni m cc byte cao th ging nhau cho tt c cc thanh ghi c vit , sau cc byte cao ch cn c vit 1 ln . Tuy nhin , ch rng nguyn tc ging nhau ca qu trnh iu khin nguyn t c miu t trc cng c p dng trong trng hp ny . Cc ngun pht xung nhp Timer/Counter Timer/Counter c th b kha bng ngun pht xung nhp bn trong hoc bn ngoi. Ngun pht xung nhp c la chn bng mc logic la chn xung nhp ci m c iu khin bng cc bit la chn xung nhp(CSn2:0 ) c t trong thanh ghi iu khin Timer/CounterB (TCCRnB) . bit thm chi tit trn ngun pht xung nhp v cc b m gp trc xem thm cc b m gp trc Timer/Counter3 ,Timer/Counter2, v Timer/Counter1 trang 144 Thnh phn b m Counter Unit Cc phn chnh ca Timer/Counter16bit th c th lp trnh thnh phn b m 16 bit 2 hng . Hnh 47 ch ra 1 s khi ca cc b m v cc thnh phn xung quanh n .

B m 16bit c v bn vo trong 2 v tr b nh I/O 8 bit : B m cao (TCNTnH) bao gm nhiu hn 8bit ca b m , v b m thp (TCNTnL) bao gm thp hn 8bit . Thanh ghi TCNTnH c th c truy nhp mt cch trc tip bi CPU . Khi m CPU thc hin mt truy nhp n a ch I/O TCNTnH , CPU truy nhp byte cao trong thanh ghi tm thi (TEMP) . Thanh ghi tm thi th c cp nht vi gi tr TCNTnH khi m TCNTnL c c , v TNCTnH th c cp nht vi gi tr ca thanh ghi tm thi khi m TCNTnL c ghi . iu ny cho php CPU c hoc v ghi gi tr trn vn ca b m 16 bit trong vng 1 chu k xung nhp thng qua bus d liu 8 bit . N th thc s quan trng nhn bit rng c nhng trng hp c bit ca vic vit ln cc thanh ghi TCNTn khi m b m ang m ci m s a ra nhng kt qu khng th tin on trc c . Nhng trng hp c bit ny th c miu t trong cc phn quan trng pha sau . Ph thuc vo cc kiu iu khin c s dng , cc b m b xa , c lm tng , hoc gim ti mi xung nhp Timer (clkTn ) . clkTn c th c sinh ra t 1 ngun pht xung nhp ngoi hoc bn trong , c la chn bi cc bit la chn xung nhp (CSn2:0) . Khi khng c ngun pht xung nhp no c la chn (CSn2:0 = 0) b timer c dng li . Tuy nhin, gi tr TCNTn c th c truy nhp bi CPU, s c lp ca clkTn th c a ra hoc khng . 1 CPU ghi (c quyn u tin trn ) ln tt c cc b m xa hoc cc qu trnh m . Cc chui m th c xc nh bng vic ci t ca cc bit ch pht sinh dng sng (WGMn3:0) c t trong thanh ghi iu khin Timer/Counter A v B (TCCRnA v TCCRnB). C cc kt ni ng gia cch cc b m c x l (m ) v cch m cc dng sng c pht ra trn cc u ra so snh u ra Ocnx . bit thm chi tit v chui m hon thin v my pht dng sng , xem thm bng cc ch iu khin trn trang 124. C bo dng trn Timer/Counter (TOVn) th c ci t theo ch iu khin c la chn bng cc bit WGM3:0 . TOVn c th c s dng pht sinh ra cc ngt CPU.

B phn bt tn hiu u ra Input Capture Unit Timer/Counter th khng chnh xc l 1 b phn bt tn hiu u vo ci m c th bt cc s kin bn ngoi v a chng vo 1 khun thi gian hin th thi gian ca cc s c . Tn hiu bn ngoi hin th 1 s kin , hoc nhiu s kin , c th c p dng thng qua chn ICPn hoc 1 cch lun phin , ch Timer/Counter 1 , thng qua b phn so snh tng t. Khun thi gian c th sau c s dng tnh ton tn s , chu k vng ti duty-cycle , v cc tnh nng khc ca cc tn hiu c p dng . Nh mt s la chn , khun thi gian c th c s dng cho vic to ra 1 biu ca cc s kin . B phn bt tn hiu vo th c minh ha nh c ch ra trong hnh 48 . Cc thnh phn ca s khi ci m khng trc tip l 1 phn ca b phn bt tn hiu u vo th c bi xm . Ch n nh trong thanh ghi v cc tn bit c hin th trong s th t ca Timer/Counter .

Khi 1 s thay i ca mc logic (1 bin c ) xut hin trn chn bt tn hiu u ra (ICPn), nh mt s la chn trn u ra ca b so snh tng t (ACO) , v thay i ny chng thc ti vic ci t ca cc b d sn xung , 1 capture s c khi ng . Khi 1 b bt tn hiu c khi ng , gi tr 16 bit ca b m (TCNTn) c vit ti cc thanh ghi bt tn hiu u vo (ICRn) . Cc c bt tn hiu u vo (ICFn) c ci t cc xung nhp h thng ging nhau nh l cc gi tr ca TCNTn c sao chp vo trong thanh ghi ICRn . Nu c kch hot(TICIEn = 1 ) c bo bt tn hiu u vo sinh ra 1 ngt bt tn hiu u vo (Input Capture interrupt ) . C ICFn s c xa 1 cch t ng khi m ngt c thc thi . Nh mt s la chn c ICFn c th b xa bng phn mm bng vic vit 1 mc logic 1 ln v tr bit I/O ca n . Vic c gi tr 16 bit trong thanh ghi bt tn hiu u vo (ICRn) c thc hin trc ht bng vic c byte thp (ICRnL) v sau l cc byte cao (ICRnH ) . Khi byte thp c

c , byte cao c sao chp vo trong thanh ghi d liu tm thi byte cao (TEMP) . Khi m CPU c vng I/O ICRnH n s truy nhp thanh ghi TEMP Thanh ghi ICRn c th ch c vit khi s dng 1 ch pht dng sng ci m dng thanh ghi ICRn cho vic xc nh gi tr TOP ca b m . Trong trng hp ny, cc bit ch pht dng sng (Wareform Generation mode ) (WGMn3:0) phi c ci t trc khi gi tr TOP c th c vit ti thanh ghi ICRn . Khi vic vit thanh ghi ICRn cc byte cao phi c vit ln vng I/O ICRnH trc khi byte thp c vit ti ICRnL thm thng tin v cch truy nhp thanh ghi 16bit tham kho Accessing 16bit Registers trn trang 115 . Ngun chn bt tn hiu u vo Ngun khi ng chnh cho b phn bt tn hiu u vo l chn bt tn hiu u vo (ICPn ) . Timer/Counter1 c th s dng lun phin u ra b so snh tng t nh l 1 ngun khi ng cho b phn bt tn hiu u vo . B so snh tng t th c la chn nh l ngun khi ng bng cch ci t bit bt tn hiu b so snh tng t (ACIC) trong thanh ghi trng thi v iu khin b so snh tng t (ACSR) . nhn bit ngun khi ng s thay i c th khi ng1 capture . C bo bt tn hiu u ra do vy phi c xa sau khi thay i . C hai chn bt tn hiu u vo (ICPn) v u vo ca u ra b so snh tng t (ACO) th c ly mu s dng cc cng ngh ging nhau nh chn Tn (hnh 59 trang 144) . B d sn th cng ging nhau . Tuy nhin , khi m b kha ct nhiu c kch hot , thm vo mc logic c chn vo trc b d sn xung (edge detector ) , ci m tng tr bng 4 chu k xung nhp h thng . Ch rng u vo ca kha ct nhiu v b d sn th lun c kch hot tr phi Timer/Counter c ci t trong 1 ch pht dng sng ci m s dng ICRn xc nh gi tr TOP Mt b bt tn hiu u ra c th c khi ng bng phn mm bi vic iu khin cng ca chn ICPn Kha ct nhiu Noise Canceler Mt b kha ct nhiu nng cao vic gim nhiu bng vic s dng 1 s b lc s n gin . u vo b kha ct nhiu th c iu chnh qua 4 qu trnh ly mu , v tt c 4 ln phi bng nhau cho vic thay i u ra ci m ln lt c s dng bi b d sn xung . B kha ct nhiu th c kch hot bng vic ci t bit kha ct nhiu bt tn hiu u vo (ICNCn) trong thanh ghi iu khin Timer/Counter B (TCCRnB ) . Khi kch hot kha ct nhiu a vo 4 chu k xung nhp h thng thm vo ca tr t 1 thay i c p dng ln u vo , cp nht thanh ghi ICRn . Kha ct nhiu s dng xung nhp h thng v v vy n khng b nh hng n b m gp trc .

Vic s dng b phn bt tn hiu u vo

S th thch chnh ca vic s dng b phn bt tn hiu u vo l gn dung lng ca b nh cho vic iu khin cc bin c n . Khong thi gian gia cc bin c th c tnh quyt nh . Nu b vi x l khng phi c gi tr bt c trong thanh ghi ICRn trc khi bin c tip theo xut hin , ICRn s c ghi vi gi tr mi . Trong trng hp ny kt qu ca vic truy bt s b sai . Khi s dng ngt bt tn hiu u vo (Input Capture ) , thanh ghi ICRn nn c c sm trong chng trnh con phc v ngt nu c th . D vy ngt ca b truy bt tn hiu u vo c quyn u tin cao 1 cch tng i , thi gian p ng ngt cc i th ph thuc vo s ln nht ca chu k xung nhp n ly i iu khin bt c 1 yu cu ngt no khc . Vic s dng b phn bt tn hiu u ra trong bt c mt ch iu khin no khi m gi tr TOP c thay i mt cch ch ng trong sut qu trnh hot ng , th khng c khuyn ngh . Vic o ca mt chu k ti ca1 tn hiu bn ngoi ci m cn thit khi ng sn th c thay i sau mi ln truy bt. Vic thay i s ly mu sn (Edge sensing) phi c thc hin sm nht c th sau khi thanh ghi ICRn va c c . Sau 1 s thay i ca sn xung , c bo bt tn hiu u vo (ICFn) phi c xa bng phn mm (vit mc logic 1 ln vng a ch bit I/O) . V vic ch o tn s , qu trnh xa ca c ICFn th khng cn thit (nu mt iu khin ngt c s dng ) Cc b phn so snh u ra Output Compare Units B so snh 16 bit tip tc so snh TCNTn vi thanh ghi so snh u ra (OCRnx ). Nu nh TCNT bng OCRnx , cc tn hiu ca b so snh c mt s tng ng . Mt match s c ci t c so snh u ra (OCFnx) ti chu k xung nhp tip theo . Nu c kch hot (OCIEnx = 1 ) c bo so snh u ra sinh ra 1 ngt so snh u ra . C OCFnx th t ng c xa khi ngt c thc thi . Nh mt s la chn , c OCFnx c th b xa bng phn mm bi vic vit mt mc logic 1 ln vng a ch bit I/O ca n . My pht dng sng s dng tn hiu ghp pht ra 1 tn hiu u ra theo ch iu khin ci t bngcc bit ch pht dng sng (vWGMn3:0) v cc bit ch u ra so snh (COMnx1:0) . Tn hiu TOP v BOTTOM c s dng bng my pht dng sng iu khin cc trng hp c bit ca cc gi tr cc bin trong mt vi ch iu khin ( Xem bng ch iu khin trn trang 124 ) Mt tnh nng c bit ca b phn u ra so snh cho php n xc nh gi tr TOP ca Timer/Counter (v d chnh xc ca b m ) . Thm vo chnh xc ca b m , gi tr TOP xc nh chu k thi gian cho dng sng c pht bng my pht dng sng . Hnh 49 ch ra 1 s khi ca b phn so snh u ra . Ch n nh trong thanh ghi v cc tn bit hin th s th t ca thit b (n = n ca Timer/Counter n ) , v x hin th b phn u ra so snh (A/B/C) . Thnh phn ca s khi ci m khng trc tip l 1 phn ca b phn u ra so snh th c bi xm .

Thanh ghi OCRnx th c ghi vo b m kp khi s dng bt c 1 trong 12 ch iu ch rng xung (PWM) . V ch iu khin bnh thng v ch so snh trn xa timer- Clear Timer on Compare mode (CTC ) , s ghi vo b m kp th b v hiu ha. S ghi vo b m kp th ng b ha vic cp nht ca thanh ghi so snh OCRnx n 1 trong 2 gi tr ca chui m l TOP v BOTTOM . S ng b ha ngn cn s xut hin ca oddlength , v cc xung PWM khng i xng , do to ra cc u ra khng c nhiu sc ngang . S truy nhp thanh ghi OCRnx c th dng nh phc tp , nhng khng phi l trng hp ny . Khi b m kp (double buffering ) c kch hot , CPU va truy cp ln thanh ghi b m OCRnx , v nu b m kp b v hiu ha CPU s truy nhp vo OCRnx 1 cch trc tip . Thnh phn ca thanh ghi OCR1x (b m hoc b so snh ) ch b thay i bng mt qu trnh vit (Timer/Counter th khng cp nht thanh ghi 1 cch t ng nh l cc thanh ghi TCNTn v ICRn ). V vy OCRnx th khng c c thng qua thanh ghi tm thi byte cao (TEMP) . Tuy nhin , n l 1 s thc hnh tt c byte thp trc tin nh khi truy nhp vo cc thanh ghi 16bit khc . Qu trnh vit cc thanh ghi OCRnx phi c thc hin thng qua thanh ghi TEMP t khi qu trnh so snh ca tt c cc thit b 16bit th c thc hin 1 cch lin tc . Byte cao (OCRnxH) c ghi trc tin . Khi vng a ch I/O byte cao c ghi bi CPU , thanh ghi TEMP s c cp nht bi gi tr c vit . Sau khi byte thp (OCRnxL ) c ghi ln cc thp hn 8bit , byte cao s c sao chp vo trong upper 8bit ca 1 trong 2 thanh ghi b m OCRnx hoc thanh ghi so snh OCRnx trong cng mt chu k xung nhp h thng . thm thng tin v cch truy nhp vo cc thanh ghi 16bit tham kho thm Accessing 16bit Registers trn trang 115

So snh u ra cng bc Trong cc ch khng phi l ch pht dng sng PWM , u ra ghp (match output) ca b so snh c th b cng bc bi vic vit mt mc logic 1 ln bit so snh u ra cng bc (FOCnx ) . Vic ghp so snh cng bc s khng ci t c OCFnx hoc reload/clear Timer , nhng chn Ocnx s c cp nht nh l nu 1 ghp so snh xut hin( cc bit COMnx1:0 ci t xc nh rng chn Ocnx c ci t , b xa hoc di chuyn ) Qu trnh kha ghp so snh bng vic vit TCNTn Tt c qu trnh vit ca CPU ln thanh ghi TCNTn s kha bt c ghp so snh no ci m xut hin trong chu k xung nhp tip theo , d cho khi Timer c dng li . c im ny cho php OCRnx c khi to li n gi tr ging nh TCNTn m khng khi ng 1 ngt khi m kha Timer/Counter c kch hot . Vic s dng b phn so snh u ra T khi vic vit TCNTn trong bt c ch iu khin no s kha tt c cc ghp so snh trong 1 chu k xung nhp timer , c nhng nguy c c ko theo khi s thay i TCNTn khi s dng bt c cc knh so snh u ra no , s ph thuc ca vic la chn Timer/Counter ang chy hay khng . Nu gi tr c vit ln TCNTn bng gi tr OCRnx , ghp so snh s b khng ng , kt qu trong vic pht ra dng sng khng ng . Khng c vit TCNTn bng gi tr TOP trong ch PWM vi cc gi tr TOP thay i . Ghp so snh cho TOP s c b qua v b m s tip tc ln 0xFFFF . Mt cch tng t , khng c vit gi tr TCNTn bng gi tr BOTTOM khi m b m ang m xung S ci t ca Ocnx nn c tin hnh trc khi vic ci t thanh ghi nh hng d liu cho chn cng ln cng ra . Cch d nht ci t gi tr Ocnx l s dng cc bit phn tch so snh u ra (FOCnx) trong ch bnh thng (normal). Thanh ghi Ocnx gi gi tr ca n d khi thay i gia cc ch pht dng sng nhn ra rng cc bit COMnx1:0 th khng c ghi vo b m kp cng nhau vi gi tr so snh . S thay i cc bit COMnx s to hiu lc ngay lp tc . B phn ghp u ra so snh Cc bit ch u ra so snh (COMnx1:0) c hai chc nng . My pht dng sng s dng cc bit COMnx1:0 cho vic xc nh trng thi so snh u ra (OCnx) ti ghp so snh tip theo . Th hai l cc bit COMnx1:0 iu khin chn OCnx ngun u ra . Hnh 50 ch ra s c rt gn ca s h hng logic bi vic ci t bit OCMnx 1:0 . Cc thanh ghi I/O , cc bit I/O v cc chn I/O trong hnh th c bi m. Ch cc phn ca cc thanh ghi iu khin cng I/O chung (DDR v PORT) ci m b hng bi cc bit COMnx1:0 c ch ra . Khi tham kho n cc trng thi ca OCnx , s tham chiu th cho thanh ghi OCnx bn trong , khng phi cho cc chn OCnx . Nu tn hiu Reset xut hin , thanh ghi OCnx c reset v 0

Chc nng ca cc cng I/O chung th c ghi bng bit so snh u ra (OCnx ) t my pht dng sng nu 1 trong 2 bit COMnx1:0 c ci t . Tuy nhin , s nh hng chn OCnx ( u vo hoc u ra ) th vn c iu khin bi thanh ghi nh hng d liu (DDR) cho chn cng . Bit thanh ghi nh hng d liu cho chn OCnx (DDR_OCnx) phi c ci t nh cng ra trc khi gi tr ca OCnx c nhn thy trn chn . Chc nng ghi cng l nguyn tc c lp ca ch pht dng sng , nhng c 1 vi ngoi l . Tham kho bng 58 bng 59 v 60 bit thm chi tit . Thit k ca chn logic so snh cng ra cho php vic khi to ca trng thi OCnx trc khi cng ra c kch hot . Ch rng s ci t bit COMnx1:0 c d tr cho cc ch bit ca qu trnh iu khin . Xem m t thanh ghi Timer/Counter 16bit trn trang 133 Cc bit COMnx1:0 khng c hiu lc trn b phn bt tn hiu u vo Ch u ra so snh v s pht sinh dng sng My pht dng sng s dng cc bit COMnx1:0 1 cch khc nhau trong ch thng thng , v cc ch PWM . Cho tt c cc ch , vic ci t cc bit COMnx1:0 = 0 ni cho my pht bit rng khng c hnh ng no trn thanh ghi OCnx c tin hnh trong ghp so snh tip theo . Cho cc hot ng u ra so snh trong cc ch khng phi PWM tham kho bng 58 trang 133 . V ch fast PWM tham kho bng 59 trang 134 , v cho ch PWM ng tn s v PWM ng pha tham kho bng 60 trang 134 Mt s thay i trng thi cc bit COMnx1:0 s c hiu lc ti ghp so snh u tin sau khi cc bit c ghi . V cc ch khng phi PWM , hot ng c th b cng p c hiu lc ngay lp tc bng vic s dng bit phn tch FOCnx Cc ch ca qu trnh iu khin Ch ca qu trnh iu khin v d nh s x l ca Timer/Counter v cc chn so snh u ra , c xc nh bng vic kt hp ca ch d pht dng sng (WGMn3:0) v cc bit u ra so snh (COMnx1:0) . Cc bit ch u ra so snh th khng nh hng n cc

chui m , trong khi cc bit ch pht dng sng th nh hng . Cc bit COMnx1;0 iu khin la chn u ra PWM c pht ra nn c o hay khng ( xung PWM o hoc khng o ) . Cho cc ch khng phi PWM cc bit COMx1:0 iu khin u ra la chn nn c ci t , b xa hay di chuyn ti 1 ghp so snh ( xem compare match output unit trn trang 123 ) bit thm chi tit v thng tin nh thi tham kho Timer/Counter Timing Diagrams trn trang 131 . Ch bnh thng Normal mode Ch bnh thng Ch n gin nht ca qu trnh iu khin l ch bnh thng (WGMn3:0) = 0. Trong ch ny vic nh hng m th lun lun l ln trn (tng dn), v khng c s xa b m no c tin hnh. B m n gin nht b trn khi m n vt qua gi tr cc i 16 (MAX = 0xFFFF ) v sau khi ng li t ch BOTTOM (0x0000) Trong ch iu khin bnh thng c bo trn Timer/Counter (TOVn) s c ci t trong cng chu k xung nhp nh l TCNTn tr thnh 0 . C bo TOVn trong trng hp ny c x l nh l bit th 17 , ngoi l l n ch c ci t , khng b xa . Tuy nhin , c kt hp vi ngt bo trn timer ci m t ng xa c TOVn , chnh xc ca timer c th c tng ln bng phn mm . Khng c trng hp c bit no c xt n trong ch bnh thng , 1 gi tr b m mi c th c ghi bt c thi gian no . B phn truy bt tn hiu u ra, th rt d c s dng trong ch bnh thng. Tuy nhin vic quan st gi tr cc i bn trong gia cc bin c bn ngoi phi khng c vt qu chnh xc ca b m. Nu gi tr bn trong ca cc bin c qu di, c bo ngt trn tham m hoc b m gp trc ca timer phi c s dng m rng chnh xc ca b phn truy bt tn hiu u vo. Cc b phn so snh u ra c th c s dng pht ra cc ngt ti mt vi thi im nh trc .Vic s dng so snh u ra pht cc xung trong ch bnh thng th khng c khuyn co , do iu ny s lm tiu tn nhiu thi gian ca CPU Ch CTC Clear Timer on Compare Match Trong ch CTC (WGMn3:0=4 hoc 12), thanh ghi OCRnA hoc ICRn c s dng iu khin chnh xc ca b m. Trong ch CTC b m b xa v 0 khi m gi tr ca b m (TCNTn) tng ng vi mt trong hai bit OCRnA (WGMn3:0=4)hoc ICRn (WGMn3:0=12). Thanh ghi OCRnA hoc ICRn xc nh gi tr TOP cho b m ,v cng l chnh xc ca n. Ch ny cho php vic iu khin ca tn s u ra ghp so snh tt hn. N cng l qu trnh iu khin n gin nht ca vic m cc s kin bn ngoi. Biu thi gian cho ch CTC c ch ra trn hnh 51. Gi tr ca b m (TCNTn) lm tng cho n khi mt ghp so snh xut hin vi mt trong hai thanh ghi OCRnA hoc ICRn , v sau b m b xa

Mt ngt c th c sinh ra ti mi ln m gi tr ca b m t n gi tr TOP bng vic s dng c OCFnA hoc ICFn theo thanh ghi c s dng xc nh gi tr TOP . Nu ngt c kch hot , chng trnh con iu khin ngt c th c s dng cho vic cp nht gi tr TOP . Tuy nhin , vic thay i gi tr TOP n 1 gi tr ng ln BOTTOM khi m b m ang chy vi 1 hoc 0 mc thp ca b m gp trc phi c thc hin vi s cn thn do ch CTC khng ctnh nng b m kp .Nu mt gi tr mi c ghi ln thanh ghi OCRnA hoc thanh ghi ICRn thp hn gi tr hin hnh ca TCNTn , b m s b li ghp so snh . B m sau s phi m t gi tr cc i ca n (0xFFFF) v vng xung quanh gi tr khi ng ti 0x0000 trc khi ghp so snh c th xut hin. Trong nhiu trng hp tnh nng ny khng c xt n . 1 s o ngc sau s s dng ch fast PWM s dng OCRnA cho vic xc nh gi tr TOP (WGMn3:0=15) do OCRnA sau s c ghi vo b m kp V vic pht ra 1 u ra dng sng trong ch CTC , u ra OcnA c th c ci t di chuyn mc logic ca n trn mi ghp so snh bng vic ci t cc bit ch u ra so snh thay i ch (COMnA1:0)=1 . Gi tr ca OCnA s khng c nhn thy trn chn cng tr phi s nh hng d liu cho chn cng c ci t ln u ra (DDR_OCnA =1). Dng sng c pht ra s c tn s ln nht ca fOCnA = fclk_I/O/2 khi m OCRnA c ci t l 0 (0x0000) . Tn s dng sng c xc nh bi cng thc di y :

Bin N c a ra theo t l (1 , 8, 64 , 256 , 1024 ) Nh trong ch iu khin bnh thng , c TOVn c ci t trong cng chu k xung nhp m b m m t gi tr Max v 0x0000 Ch fast PWM Ch iu ch rng xung nhanh hay fast PWM (WGMn3:0 = 5,6,7,14 hoc 15 ) cung cp s mt s pht dng sng tn s cao ty chn . Ch fast PWM khc vi cc ch PWM khc bi qu trnh iu khin sn n ca n . B m m t BOTTOM n TOP sau khi ng li t BOTTOM Trong ch u ra so snh khng o , u ra so snh (OCnx) b xa trn ghp so snh gia TCNTn v OCRnx , v ci t BOTTOM . Trong ch u ra so snh o c ci t trn ghp so snh v b xa BOTTOM . Tng xng vi qu trnh iu khin sn n , tn s hot ng ca ch fast PWM c th cao gp i cc ch PWM ng pha ng tn s v ch PWM ng pha ci m s dng qu trnh iu

khin 2 sn . Tn s cao ny lm cho ch fast PWM thch hp tt vi cc ngun thng thng , ngun chnh lu v cc ng dng DAC . Tn s cao ny cho php cc thnh phn vt l c nh bn trong (cun dy , v t in ...) , t gim gi thnh h thng . chnh xc ca xung PWM cho ch fast PWM c th n nh 8,9 hoc 10bit , hoc c xc nh bng thanh ghi ICRn hoc OCRnA . chnh xc cc tiu cho php l 2 bit (ICRn hoc OCRnA t l 0x0003) , v chnh xc cc i l 16bit (ICRn hoc OCRnA t l MAX) . chnh xc ca PWM trong cc bit c th c tnh ton bng vic s dng cng thc di y : Trong ch fast PWM b m th c lm tng cho n khi gi tr ca b m tng ng vi 1 trong nhng gi tr n nh 0x00FF , 0x01FF , hoc 0x03FF (WGM3:0 =5,6,7 ) , gi tr trong ICRn (WGM3:0 =14) , hoc gi tr trong OCRnA (WGM3:0 = 15) . B m sau b xa ti chu k xung nhp timer tip theo . Biu thi gian cho ch fast PWM c ch ra trong hnh 52 . Hnh ny ch ra ch PWM khi m cc bit OCRnA hoc ICRnA c s dng xc nh gi tr TOP . Gi tr ca TCNTn trong gin thi gian c ch ra nh 1 biu minh ha cho qu trnh iu khin sn n . S bao gm cc u ra o v khng o . ng nm ngang nh du trn sn TCNTn a ra trn cc ghp so snh OCRnx v TCNTn . Cc c bo ngt OCnx s c ci t khi 1 ghp so snh xut hin .

C bo trn Timer/Counter (TOVn) c ci t mi ln b m t n BOTTOM . Khi mt trong hai thanh ghi OCRnA hoc ICRn c s dng cho vic xc nh gi tr TOP , c ICFn hoc OCnA c ci t ti cng chu k xung nhp nh l cc thanh ghi c cp nht vi gi tr ca b m kp (TOP) . Cc c bo ngt c th c s dng sinh ra mt ngt mi ln b m t n gi tr TOP hoc BOTTOM . gia Khi thay i gi tr TOP chng trnh phi m bo rng gi tr TOP mi cao hn hoc bng gi tr TOP ca tt c cc thanh ghi so snh . Nu gi tr TOP thp hn bt c thanh ghi so snh no , 1 ghp so snh s khng bao gi xut hin TCNTn v OCRnx . Ch rng khi s dng cc gi tr TOP n nh , cc bit khng c s dng b che bi 0 khi bt c thanh

ghi OCRnx no c ghi . Nh l chu k th 3 c ch ra trong hnh 53 , vic thay i gi tr TOP tch cc trong khi Timer/Counter ang chy trong ch ng pha c th gy ra trong mt u ra khng i xng . Kt qu ca vic ny c th c tm thy trong thi gian ca vic cp nht cho thanh ghi OCRnx . Do s cp nht thanh ghi OCRnx ti gi tr TOP , chu k PWM bt u v kt thc ti gi tr TOP . iu ny a n chiu di ca sn xung c xc nh bng gi tr TOP trc , trong khi di ca sn ln c xc nh bng gi tr TOP mi . Khi c hai gi tr ny khc nhau trn 2 sn khc nhau ca chu k s khc nhau v di . S khc nhu v di a ra kt qu khng i xng trn u ra . N th c khuyn co s dng ch ng pha v ng tn s thay th cho ch ng pha khi thay i gi tr TOP trong khi Timer/Counter ang chy . Khi s dng 1 gi tr TOP c nh thc t khng c s khc nhau gia hai ch ca qu trnh iu khin . Trong ch PWM ng pha , cc b phn so snh cho php vic pht ra cc xung PWM trn cc chn OCnx . Vic ci t cc bit COMnx1:0 ln 2 s lm gim 1 xung PWM khng o v mt u ra PWM c th c sinh ra bng vic ci t bit OCMnx1:0 ln 3 (xem bng 60 trn trang 134 ). Gi tr tht ca OCnx s ch c nhn thy trn chn cng nu s nh hng d liu cho chn cng c ci t nh l u ra (DDR_OCnx) . Dng xung PWM c sinh ra bng vic ci t (hoc xa ) thanh ghi OCnx ghp so snh gia OCRnx v TCNTn khi b m tng , v b xa (hoc ci t ) khi thanh ghi OCnx ti ghp so snh gia OCRnx v TCNTn khi b m gim dn . Tn s xung PWM cho u ra khi ci s dng ch PWM ng pha c th c tnh bng cng thc di y : Bin N c a ra theo t l (1 , 8 , 64 , 256 , 1024) Gi tr cc bin ca thanh ghi OCRnx a ra trong trng hp c bit khi m s pht 1 u ra xung PWM trong ch PWM ng pha . Nu thanh ghi OCRnx c ci t bng gi tr BOTTOM , u ra s tip tc mc thp v nu ci t bng gi tr TOP th u ra s tip tc mc cao cho ch PWM khng o . Cho ch PWM o , u ra s c cc gi tr logic i lp . Nu OCnA c s dng xc nh gi tr TOP (WMGn3:0 = 11) v OCMnA1:0=1 ,u ra OCnA s di chuyn vi 1 chu k ti 50% Ch PWM ng pha v ng tn s iu ch rng xung ng pha ng tn s ,(WGM3:0 =8 hoc 9 )cung cp dng xung PWM la chn ng pha ng tn s . Ch PWM ng pha ng tn s th ging ch PWM ng pha , u da trn qu trnh iu khin 2 sn . B m m lp li t BOTTO (0x0000) n TOP v sau m t TOP v BOTTOM . Trong ch u ra so snh khng o , u ra so snh (OCnx) b xa trn ghp so snh gia TCNTn v OCRnx trong khi ang m ln , v t trn ghp so snh trong khi ang m xung . Trong ch u ra so snh o , qu trnh iu khin b o ngc . Qu trnh iu khin 2 sn a ra 1 c tnh i xng ca cc ch PWM hai sn , cc ch ny c a thch dng cho cc ng dng iu khin ng c S khc nhau chnh gia ch ng pha v ch ng pha, ng tn s l thi gian m thanh ghi OCRnx c cp nht bng thanh ghi b m OCRnx (xem hnh 53 v hnh 54 )

 chnh xc ca ch ng pha , ng tn s c th c xc nh bng 1 trong 2 ICRn hoc OCRnA . chnh xc cc tiu cho php l 2-bit (ICRn hoc OCRnA t l 0x0003) v chnh xc ln nht l 16bit (ICRn v OCRnA t l MAX ) . chnh xc ca PWM trong cc bit c th c tnh ton bng cng thc di y :

Trong ch ng pha, ng tn s , b m m tng dn cho n khi gi tr ca b m tng ng vi 1 trong 2 gi tr trong ICRn (WGMn3:0 =8 ) hoc gi tr trong OCRnA (WGMn3:0 = 9 ) . B m sau khi va t n gi tr TOP v chuyn hng m . Gi tr ca TCNTn s bng vi TOP trong 1 chu k xung nhp . Biu thi gian cho ch PWM ng pha v ng tn s c ch ra trong hnh 54 . Hnh v ch ra ch ng pha , ng tn s khi m OCRnA hoc ICRn c s dng xc nh gi tr TOP . Gi tr ca TCNTn trong gin thi gian c ch ra nh mt biu minh ha cho qu trnh iu khin 2 sn . Gin bao gm cc u ra PWM o v khng o . ng nm ngang nh nh du trn sn TCNTn a ra trn ghp so snh gia OCRnx v TCNTn . C bo ngt OCnx s c ci t khi m ghp so snh xut hin .

C bo trn Timer/Counter (TOVn) c ci t ti cng chu k xung nhp nh l thi gian cc thanh ghi c cp nht vi gi tr b m kp ( BOTTOM ) . Khi mt trong 2 bit OCRnA v ICRnx c s dng cho vic xc nh gi tr TOP , c OCnA v ICFn ci t khi TCNTn t n gi tr TOP . Cc c bo ngt sau c th c s dng snh ra 1 ngt mi ln m timer t n gi tr TOP v BOTTOM Khi thay i gi tr TOP chng trnh phi m bo rng gi tr TOP mi cao hn hoc bng gi tr ca tt c cc thanh ghi so snh . Nu gi tr TOP thp hn bt c gi tr so snh thanh ghi no , 1 ghp so snh s khng bao gi xut hin gia cc TCNTn v OCRnx Nh hnh 54 ch ra u ra c sinh ra , trong s tng phn vi ch PWM ng pha , s i xng trong tt c cc chu k . Do cc thanh ghi OCRnx c cp nht ti

BOTTOM , di ca sn ln v xung s lun lun bng nhau . iu ny a cc xung u ra i xng v v vy tn s ng . Vic s dng cc thanh ghi ICRn cho vic xc nh gi tr TOP tt khi s dng gi tr n nh . Bng vic s dng ICRn , thanh ghi OCRnA th t do s dng cho vic pht ra 1 xung PWM trn u ra OCnA . Tuy nhin nu tn s PWM c bn c thay i bi bng vic thay i gi tr TOP , vic s dng OCRnA nhu l gi tr TOP ro rng l mt la chn tt hn d cho c tnh b m kp ca n . Trong ch ng pha v ng tn s , cc b phn so snh cho php vic pht ra ca cc xung PWM trn cc chn OCnx . Vic ci t cc bit OCMnx1:0 ln 2 s gy ra 1 1 xung PWM khng o v o c th c sinh ra bng vic ci t COMnx1:0 ln 3 (xem bng 60 trang 134). Gi tr tht ca OCnx s ch c nhn thy trn chn cng nu s nh hng d liu cho chn cng c ci t nh l cng ra (DDR_OCnx ) . Dng sng PWM c sinh ra bng vic ci (hoc xa) thanh ghi OCnx ti ghp so snh gia OCRnx v TCNTn khi b m tng dn , v vic xa (hoc ci t ) thanh ghi OCnx ti ghp so snh gia OCRnx v TCNTn khi b m gim dn . Tn s PWM cho u ra khi s dng ch ng pha , ng tn s c th c tnh bng cng thc di y : Gi tr cc bin ca thanh ghi OCRnx a ra trong trng hp c bit khi m s pht 1 u ra xung PWM trong ch PWM ng pha . Nu thanh ghi OCRnx c ci t bng gi tr BOTTOM , u ra s tip tc mc thp v nu ci t bng gi tr TOP th u ra s tip tc mc cao cho ch PWM khng o . Cho ch PWM o , u ra s c cc gi tr logic i lp . Nu OCnA c s dng xc nh gi tr TOP (WMGn3:0 = 11) v OCMnA1:0=1 ,u ra OCnA s di chuyn vi 1 chu k ti Gin thi gian ca Timer/Counter Timer/Counter l thit k ng b v chu k xung nhp timer (clkTn0)v vy c ch ra nh tn hiu kch hot xung nhp trong hnh di y . Hnh v bao gm thng tin khi cc c bo ngt kch hot , v khi thanh ghi OCRnx c cp nht vigi tr b m OCRnx (ch trong cc ch s dng b m kp ) Hnh 55 ch ra 1 gin thi gian cho vic ci t ca OCFnx

Hnh 57 ch ra chui m ng TOP ln cc gi tr thay i . Khi s dng ch PWM ng pha ng tn s , cc thanh ghi OCRnx c cp nht tiBOTTOM . gin thi gian s ging nhau , Nhng gi tr TOP nn c thay i bng BOTTOM , TOP-1 v BOTTOM+1 . S ging nhau cn li p dng cho cc ch m ci t c TOVn ti BOTTOM

S miu t thanh ghi ca Timer/Counter 16 bit Thanh ghi A iu khin Timer/Counter 1 TCCR1A

Thanh ghi A iu khin Timer/Counter 3 TCCR3A

Bit 7:6 COMnA1:0 : ch u ra so snh cho knh A Bit 5:4 COMnB1:0 : ch u ra so snh cho knh B Bit 3:2 ComnC 1:0 : ch u ra so snh cho knh C COMnA1:0 , COMnB 1:0 , v COMnC1:0 iu khin cc chn so snh u ra (OcnA , OcnB , v OcnC tng ng ) . Nu 1 hoc c hai trong s cc bit COMnA1:0 c ghi l 1 , u ra OcnA ghi ln cng chc nng ca chn I/O m n c kt ni n . Nu 1 hoc c hai trong s cc bit COMnB1:0 c ghi l 1 , u ra OCnB ghi ln cng chc nng ca chn I/O m n c kt ni n . Nu 1 hoc c hai trong s cc bit COMnC1:0 c ghi l 1 , u ra OCnC ghi ln cng chc nng ca chn I/O m n c kt ni n . Tuy nhin , ch rng bit thanh ghi nh hng d liu (DDR) tng ng vi OcnA , OcnB hoc chn OcnC phi c ci t theo th t kch hot b iu khin u ra Khi OCnA , OCnB , v OCnC c ni vi chn chc nng ca cc bit COMnx1:0 th ph thuc vo vic ci t cc bit WGMn3:0 . Bng 58 ch ra bit chc nng COMnx1:0 khi

cc bit WGMn3:0 c ci t ti mt ch bnh thng hoc ch CTC (khng phi PWM)

Bng 59 ch ra cc bit chc nng COMnx1:0 khi cc bit WGMn3:0 c ci t trong ch fast PWM .

Bng 60 ch ra cc bit chc nng COMnx1:0 khi cc bit WGMn3:0 c ci t trong ch PWM ng pha v ng tn s

Bit 1:0 - WGMn1:0 : ch pht dng sng Vic kt hp vi cc bit WGMn3:2 c tm thy trong thanh ghi TCCRnB , cc bit ny iu khin cc chui m ca b m , ngun cho gi tr b m cc i (TOP) , v loi dng sng pht ra c s dng , xem bng 61 . Cc ch iu khin c h tr bng cc b phn Timer/Counter l : Ch normal (counter ) , CTC mode (Clear Timer on Compare match ) , v 3 loi ca ch iu ch rng xung PWM ( xem Modes of Operation trang 124)

Thanh ghi B iu khin Timer/Counter 1 TCCR1B

Thanh ghi B iu khin Timer/Counter 3 TCCR3B

Bit 7 ICNCn : kha ct nhiu b bt tn hiu u vo Vic ci t bit ny (l 1 ) s kch hot kha ct nhiu b bt tn hiu u vo . Khi kha ct nhiu (Noise Canceler) c kch hot , u vo t chn bt tn hiu u vo (ICPn) c lc . Chc nng ca b lc l cn thit 4 qu trnh ly mu bng nhau lin tip ca chn ICPn cho vic thay i u ra ca n . B bt tn hiu u vo do vy b tr bi 4 chu k xung nhp ca b to dao ng khi m kha ct nhiu c kch hot Bit6 ICESn : la chn sn ca b bt tn hiu u vo Bit ny la chn sn no trn chn cng ca b bt tn hiu u vo (ICPn ) ci m c s dng khi ng 1 s kin truy bt tn hiu . Khi bit ICESn c ghi l 0 , 1 sn xung (m ) c s dng nh l khi ng , v khi bit ICESn c vit l 1 , 1 sn ln (dng) s khi ng b bt tn hiu

Khi 1 b bt tn hiu c khi ng theo vic ci t bit ICESn , gi tr ca b m c sao chp vo trong thanh ghi truy bt tn hiu u vo (ICRn) . Bin c cng s c ci t c bo truy bt tn hiu u vo(ICFn), v iu ny c th c s dng gy ra ngt truy bt tn hiu u vo , nu ngt ny c kch hot Khi ICRn c s dng nh gi tr TOP ( xem s m t ca cc bit WGMn3:0 t trong thanh ghi TCCRnA v TCCRnB ) , ICPn c ngt kt ni v do chc nng truy bt tn hiu u ra b v hiu ha . Bit 5 bit d tr Bit ny c d tr cho vic s dng trong tng lai . m bo tng thch vi cc thit b trong tng lai, bit ny phi c vit l 0 khi m thanh ghi TCCRnB c ghi Bit 4:3 - WGMn3:2 : ch pht dng sng Xem phn m t thanh ghi TCCRnA Bit2:0 CSn2:0 : la chn xung nhp 3 bt la chn xung nhp la chn ngun xung nhp c s dng bi Timer/Counter , xem hnh 55 v 56

Nu cc ch chn bn ngoi c s dng cho Timer/Counter , s chuyn tip trn cc chn Tn s kha b m d cho chn c cu hnh nh l 1 u ra . c im ny cho php phn mm iu khin vic m Thanh ghi C iu khin Timer/Counter 1 TCCR1C

Thanh ghi C iu khin Timer/Counter 3 TCCR3C

Bit 7 FOCnA : so snh u ra cng bc cho knh A Bit 6 FOCnB : so snh u ra cng bc cho knh B Bit 5 FOCnC : so snh u ra cng bc cho knh C Cc bit FOCnA , FOCnB , FOCnC ch hot ng khi cc bit WGMn3:0 xc nh 1 ch khng phi l PWM . Khi vic vit 1 mc logic 1 ln cc bit FOCnA , FOCnB , FOCnC ,

1 ghp so snh trung gian b cng p trn b phn pht dng sng . u ra FOCnA , FOCnB , FOCnC b thay i theo vic ci t cc bit WGMn1:0 ca n . Ch rng cc bit FOCnA , FOCnB , FOCnC c ci t nh l u o (strobe) . V vy n l gi tr a ra trn cc bit OCMnx1:0 ci m xc nh nh hng ca so snh cng bc . 1 u d FOCnA , FOCnB , FOCnC s khng sinh ra bt c ngt no n s xa Timer trong ch CTC mode bng vic s dng OCRnA nh l gi tr TOP . Cc bit FOCnA , FOCnB , FOCnC th lun c l 0 Bit 4:0 cc bit d tr Cc bit ny c d tr cho vic s dng trong tng lai . m bo tng thch vi cc thit b trong tng lai, bit ny phi c vit l 0 khi m thanh ghi TCCRnC c ghi Timer/Counter1 TCNT1H v TCNT1L

Timer/Counter 3 TCNT3H v TCNT3L

Hai vng a ch I/O Timer/Counter (TCNTnH v TCNTnL , c kt hp TCNTn) a ra s truy nhp trc tip , c hai u phc v cho qu trnh c v ghi , ti b phn Timer/Counter ca b m 16bit . m bo rng cc byte cao v thp c c v ghi mt cch ng thi khi CPU truy cp vo cc thanh ghi ny , s truy nhp c tin hnh s dng 1 thanh ghi byte cao tm thi 8bit (TEMP) . Thanh ghi tm thi ny c chia s bi tt c cc thanh ghi 16bit . Xem Accessing 16bit Register trn trang 115 . S sa i b m (TCNTn) trong khi b m ang chy s a ra 1 nguy c ca vic li 1 ghp so snh gia TCNTn v 1 trong cc thanh ghi OCRnx Vic vit thanh ghi TCNTn kha (g b ) ghp so snh trn cc xung nhp timer di y cho tt c cc b phn so snh . Thanh ghi so snh u ra 1A OCR1AH v OCR1AL

Thanh ghi so snh u ra 1B OCR1BH v OCR1BL

Thanh ghi so snh u ra 1C OCR1CH v OCR1CL

Thanh ghi so snh u ra 3 A OCR3AH v OCR3AL

Thanh ghi so snh u ra 3B OCR3BH v OCR3BL

Thanh ghi so snh u ra 3C OCR3CH v OCR3CL

Cc thanh ghi so snh u ra bao gm 1 gi tr 16bit m c so snh lin tip vi gi tr m (TCNTn) . Mt ghp c th c s dng pht ra 1 ngt so snh u ra , hoc pht ra 1 u ra dng sng trn chn Ocnx . Cc thanh ghi so snh u ra l c 16 bit . m bo rng cc byte cao v thp c c v ghi mt cch ng thi khi CPU truy cp vo cc thanh ghi ny , s truy nhp c tin hnh s dng 1 thanh ghi byte cao tm thi 8bit (TEMP) . Thanh ghi tm thi ny c chia s bi tt c cc thanh ghi 16bit . Xem Accessing 16bit Register trn trang 115 . Thanh ghi1 truy bt tn hiu u vo ICR1H v ICR1L

Thanh ghi truy bt tn hiu u vo 3 ICR3H v ICR3L

B truy bt tn hiu u vo c cp nht vi gi tr b m (TCNTn) mi ln m bin c xut hin trn chn ICPn ( hoc la chn trn u ra b so snh tng t cho

Timer/Counter1) . B truy bt tn hiu u vo c th c s dng xc nh gi tr TOP ca b m . Thanh ghi truy bt tn hiu u vo l c 16bit . m bo rng cc byte cao v thp c c v ghi mt cch ng thi khi CPU truy cp vo cc thanh ghi ny , s truy nhp c tin hnh s dng 1 thanh ghi byte cao tm thi 8bit (TEMP) . Thanh ghi tm thi ny c chia s bi tt c cc thanh ghi 16bit . Xem Accessing 16bit Register trn trang 115 . Thanh ghi che ngt Timer/Counter TIMSK

Bit 5 TICIE1 : Timer/Counter 1 , kch hot ngt b truy bt tn hiu vo Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt kch hot chung ) , Timer/Counter 1 ngt b truy bt tn hiu u vo c kch hot . Cc vecto ngt tng ng (xem Interrupt trang 60 ) c thc thi khi c bo ICF1 ,t trong thanh ghi TIFR c ci t Bit 4 OCIE1A : Timer/Counter 1 , kch hot ngt ghp so snh u ra A Khi bit ny c ghi l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot ) , Ngt ghp so snh u ra A Timer/Counter1 c kch hot . Cc vec t ngt tng ng ( xem trang 60 ) c thc thi khi c bo OCF1A , t trong thanh ghi TIFR c ci t . Bit 3 OCIE1B : kch hot ghp so snh u ra B , Timer/Counter1 Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot ) 1 ngt ghp so snh u ra B Timer/Counter1 c kch hot . Cc vecto ngt tng ng c thc thi khi m c bo OCF1A , t trong TIFR c ci t Bit 2 TOIE1 : kch hot ngt trn , Timer/Counter1 Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot) , ngt trn Timer/Counter1 c kch hot . Cc vecto ngt tng ng (xem trang 60 ) c thc thi khi c bo TOV1 , t trong thanh ghi TIFR c ci t . Thanh ghi che ngt Timer/Counter m rng ETIMSK

Bit 7:6 cc bit d tr Cc bit ny c d tr cho vic s dng trong tng lai . m bo tng thch vi cc thit b trong tng lai, bit ny phi c vit l 0 khi m thanh ghi ETIMSK c ghi Bit 5 TICIE3 : kch hot ngt b truy bt tn hiu u vo Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot) , ngt truy bt tn hiu u ra Timer/Counter3 c kch hot . Cc vecto

ngt tng ng (xem trang 60 ) c thc thi khi c bo ICF3, t trong thanh ghi ETIFR c ci t . Bit4 OCIE3A : Timer/Counter3 , kch hot ngt ghp u ra so snh A Khi bit ny c ghi l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot ) , Ngt ghp so snh u ra A Timer/Counter3 c kch hot . Cc vec t ngt tng ng ( xem trang 60 ) c thc thi khi c bo OCF3A , t trong thanh ghi ETIFR c ci t . Bit 3 OCIE3B : Timer/Counter3 , kch hot ngt ghp u ra so snh B Khi bit ny c ghi l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot ) , Ngt ghp so snh u ra B Timer/Counter3 c kch hot . Cc vec t ngt tng ng ( xem trang 60 ) c thc thi khi c bo OCF3B , t trong thanh ghi ETIFR c ci t Bit 2 TOIE3 , Timer /Counter3 , kch hot ngt trn Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot) , ngt trn Timer/Counter3 c kch hot . Cc vecto ngt tng ng (xem trang 60 ) c thc thi khi c bo TOV3 , t trong thanh ghi ETIFR c ci t . Bit 1 OCIE3C : Timer /Counter3 , kch hot ngt ghp so snh u ra C Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot) , ngt ghp so snh u ra C ca Timer/Counter3 c kch hot . Cc vecto ngt tng ng (xem trang 60 ) c thc thi khi c bo OCF3C , t trong thanh ghi ETIFR c ci t . Bit 0 OCIE1C : Timer/Counter1 , kch hot ngt ghp so snh u ra C Khi bit ny c vit l 1 , v c I trong thanh ghi trng thi c ci t ( cc ngt chung kch hot) , ngt ghp so snh u ra C ca Timer/Counter1 c kch hot . Cc vecto ngt tng ng (xem trang 60 ) c thc thi khi c bo OCF1C , t trong thanh ghi ETIFR c ci t Thanh ghi c bo ngt Timer/Counter TIFR

Bit 5 ICF1 : Timer/Counter 1 , c bo truy bt tn hiu u ra C ny c ci t khi 1 b truy bt bin c xut hin trn chn ICP1 . Khi m thanh ghi truy bt tn hiu u vo (ICR1) c ci t bi bit WGMn3:0 c s dng nh l gi tr TOP , c ICF1 c ci t khi b m tin ti gi tr TOP ICF1 b xa 1 cch t ng khi vcto ngt truy bt u vo c thc thi . Nh mt s la chn , ICF1 c th b xa bng vic vit 1 mc logic 1 ln vng nh bit ca n . Bit 4 OCF1A : Timer/Counter1 , c ghp so snh u ra A C ny c ci t trong chu k xung nhp timer sau khi gi tr ca b m tng xng vi thanh ghi so snh u ra A (OCR1A ) Ch rng 1 u d so snh u ra cng bc (FOC1A) s khng ci t c OCF1A

OCF1A b xa 1 cch t ng khi m vecto ngt ghp u ra so snh A c thc thi . Nh mt s la chn, OCF1A c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n . Bit 3 OCF1B : Timer/Counter1 , c bo ghp so snh u ra B C ny c ci t trong chu k xung nhp timer sau khi gi tr b m (TCNT1) tng ng vi thanh ghi so snh u ra B (OCR1B) Ch rng u d so snh u ra cng bc (FOC1B ) s khng ci t c OCF1B OCF1B b xa 1 cch t ng khi m vecto ngt ghp u ra so snh B c thc thi . Nh mt s la chn, OCF1B c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n . Bit 2 TOV1 : Timer/Counter1 , c trn Vic ci t c ny th ph thuc vo vic ci t ca cc bit WGMn3:0 . Trong ch thng thng v ch CTC , c TOV1 c ci t khi timer b trn . Tham kho thm bng 61 trang 135 v x l c trn TOV1 khi vic s dng cc ci t bit WGMn3:0 khc . TOV1 th t ng b xa khi m vec t ngt bo trn Timer/Counter1 c thc thi . Nh mt s la chn , TOV1 c th c xa bng vic vit mt mc logic 1 ln vng nh bit ca n Thanh ghi c ngt Timer/Counter m rng ETIFR

Bit 7:6 cc bit d tr Cc bit ny c d tr cho vic s dng trong tng lai . m bo tng thch vi cc thit b trong tng lai, bit ny phi c vit l 0 khi m thanh ghi ETIFR c ghi Bit 5 ICF3 : Timer/Counter3 , c bo truy bt tn hiu u vo C ny c ci t khi 1 b truy bt bin c xut hin trn chn ICP3 . Khi m thanh ghi truy bt tn hiu u vo (ICR3) c ci t bi bit WGMn3:0 c s dng nh l gi tr TOP , c ICF3 c ci t khi b m tin ti gi tr TOP ICF3 b xa 1 cch t ng khi vcto ngt truy bt u vo3 c thc thi . Nh mt s la chn , ICF3 c th b xa bng vic vit 1 mc logic 1 ln vng nh bit ca n Bit 4 OCF3A : Timer/Counter 3 , c ghp so snh u ra A C ny c ci t trong chu k xung nhp timer sau khi gi tr ca b m tng xng vi thanh ghi so snh u ra A (OCR3A ) Ch rng 1 u d so snh u ra cng bc (FOC3A) s khng ci t c OCF3A OCF1A b xa 1 cch t ng khi m vecto ngt ghp u ra so snh3 A c thc thi . Nh mt s la chn, OCF3A c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n . Bit 3 OCF3B : Timer/Counter3 , c bo ghp so snh u ra B C ny c ci t trong chu k xung nhp timer sau khi gi tr b m (TCNT3) tng ng vi thanh ghi so snh u ra B (OCR3B) Ch rng u d so snh u ra cng bc (FOC3B ) s khng ci t c OCF3B

OCF3B b xa 1 cch t ng khi m vecto ngt ghp u ra so snh3 B c thc thi . Nh mt s la chn, OCF3B c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n . Bit 2 TOV3 : Timer/Counter3 , c trn Vic ci t c ny th ph thuc vo vic ci t ca cc bit WGMn3:0 . Trong ch thng thng v ch CTC , c TOV3 c ci t khi timer b trn . Tham kho thm bng 52 trang 105 v x l c trn TOV3 khi vic s dng cc ci t bit WGMn3:0 khc . TOV3 th t ng b xa khi m vec t ngt bo trn Timer/Counter3 c thc thi . Nh mt s la chn , TOV3 c th c xa bng vic vit mt mc logic 1 ln vng nh bit ca n Bit 1 OCF3C :Timer/Counter3 , c ghp so snh u ra C C ny c ci t trong 1 chu k xung nhp timer sau khi gi tr ca b m (TCNT3) tng ng vi thanh ghi so snh u ra C(OCR3C) Ch rng 1 u d so snh u ra cng bc (FOC3C) s khng ci t OCF3C OCF3C th t ng c xa khi vecto ngt ghp so snh u ra 3 C c thc thi . Nh mt s la chn, OCF3C c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n Bit 0 OCF1C : Timer/Counter1 , c ghp so snh u ra C C ny c ci t trong mt chu k xung nhp sau khi gi tr b m (TCNT1) tng ng vi thanh ghi so snh u ra C (OCR1C) Ch rng mt u d so snh u ra cng bc s khng ci t c OCF1C OCF1C s t ng b xa khi m vecto ngt ghp so snh u ra 1 C c thc thi . Nh mt s la chn , OCF1C c th b xa bng vic vit mt mc logic 1 ln vng nh bit ca n .

XIII . Cc b m gp trc ca Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1

Cc Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1 chia s module b m gp trc ging nhau , nhng cc Timer/Counter c s ci t b m gp trc khc nhau . S miu t pha di c p dng cho tt c cc Timer/Counter c ni n . Ngun xung nhp bn trong Timer/Counter c th b kha trc tip bng xung nhp h thng( bng vic ci t CSn2:0 =1) . iu ny cung cp s iu khin nhanh nht , vi 1 tn s xung nhp Timer/Counter cc i bng vi tn s xung nhp h thng(fCLK_I/O) . Nh mt s la chn, 1 trong 4 u ra t b m gp trc c th c s dng nh l mt ngun pht xung nhp . B m gp . Xung nhp ca b m gp trc c tn s l 1 trong s fCLK_I/O/8 , fCLK_I/O/64 , fCLK_I/O / 256 , fCLK_I/O /1024 Reset b m gp trc

B m gp trc th ang chy t do , v d nh qu trnh hot ng c lp ca bin logic la chn xung nhp ca Timer/Counter , v b chia s bi Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1 . T khi b m gp trc th khng b h hng bi vic la chn xung nhp ca Timer/Counter , trng thi ca b m gp trc s ph thuc vo cc tnh hung ni m xung nhp ca b m gp trc c s dng . Mt v d ca vic m gp trc gi to xut hin khi m timer c kch hot v c kha bi b m gp trc( 6>CSn2:0>1 ) . H s ca cc chu k xung nhp h thng t khi timer c kch hot n kt qu m u tin xut hin c th l t 1 n N + 1 chu k xung nhp h thng, khi N bng b chia t l ( 8, 64,256 ,1024 ) Nu c th s dng reset b m gp trc cho vic ng b ha Timer/Counter n qu trnh thc thi cc chng trnh . Tuy nhin , s cn thn phi c tin hnh nu Timer/Counter khc ci m chia s cng 1 b m gp trc cng s dng t l . 1 Reset b m gp trc s nh hng n chu k m gp trc cho tt c cc Timer/Counter c kt ni vi n . Ngun xung nhp bn ngoi Mt ngun xung nhp bn ngoi p t ln cc chn Tn c th c s dng nh l xung nhp Timer/Counter (clkT1 , clkT2 , clkT3 ) . Chn Tn th c ly mu 1 ln trn mi chu k xung nhp h thng bng chn ng b ha logic . Tn hiu ng b ha (c ly mu ) th sau vt qua sn ca b d xung . Hnh 59 ch ra mt s khi 1chc nng tng ng ca b ng b ha Tn v my d sn xung. Cc thanh ghi b kha sn dng ca xung nhp h thng bn trong (clkI/O) . Then ci th c chuyn vo trong chu k cao ca xung nhp h thng bn trong . B d sn pht ra 1 xung clkT1 , clkT2 , clkT3 cho mi sn dng (CSn2:0 = 7) v m (CSn2:0 = 6 ) ca n c d thy

B ng b ha v cc my d sn logic a ra 1 tr ca 2.5 n 3.5 ln chu k xung nhp h thng t mt sn c th p t ln chn Tn ca b m c cp nht . Vic kch hot v v hiu ha ca xung nhp bn trong phi c thc hin khi m Tn c trng thi n nh trong 1 khong thi gian nh hn 1 chu k xung nhp h thng , ni cch khc n l 1 nguy c ci m 1 xung nhp Timer/Counter hng c sinh ra . Mi mt na chu k xung nhp bn ngoi c p dng phi di hn1 chu k xung nhp h thng m bo vic ly mu chnh xc . Xung nhp bn ngoi phi m bo nh hn tn s na chu k xung nhp h thng (fExtClk < fclk_I/O/2) a ra 50/50 chu k ti . V rng b d sn xung s dng vic ly mu , tn s cc i ca mt xung bn ngoi ca n c th c d thy l 1 na tn s ly mu (nguyn l Nyquist ) . Tuy nhin , s thay i ca tn s xung

nhp h thng v chu k ti gy ra bi ngun b to dao ng(thch anh , b cng hng , v t in ) , n c khuyn co rng tn s ln nht ca 1 ngun pht xung nhp bn ngoi th nh hn fclk_I/O/2.5 Mt ngun pht xung nhp ngoi khng th c m gp trc

Thanh ghi IO chc nng c bit

Bit 7 TSM : ch ng b ha Timer/Counter Vic vit bit TSM l 1 kch hot ch ng b ha Timer/Counter . Trong ch ny, gi tr m c vit ln cc bit PSR0 v PSR321 th c gi , do vic gi cc tn hiu reset b m tng ng c gn . iu ny m bo rng cc Timer/Counter tng ng c dng v c th c cu hnh ln cc gi tr ging nhau m khng c nguy c ca 1 trong s chng trong sut qu trnh cu hnh . Khi m bit TSM c vit l 0 , cc bit PSR0 v PSR321 b xa bng phn cng , v cc Timer/Counter bt u vic m 1 cch ng thi . Bit 0 PSR321 : b m gp trc Reset Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1 Khi m bit ny l 1 , b m gp trc Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1 s c reset . Bit ny thng thng c xa ngay lp tc bng phn cng , ngoi tr nu bit TSM c ci t . Ch rng Timer/Counter 3 ,Timer/Counter 2 v Timer/Counter 1 chia s b m gp trc ging nhau v 1 Reset ca b m gp trc ny s h hng trong 3 Timer

XIV . Timer/Counter 2 8bit vi ch PWM

Timer/Counter 2 l 1 module Timer/Counter 2 a nng dng chung , knh n . Cc c im chnh l : - B m knh n - Clear Timer on Compare Match (Auto reload ) - Khng nhiu sc ngang , iu ch rng xung ng pha ( PWM) - My pht tn s

- B m bin c bn ngoi - B m gp trc xung nhp 10bit - Cc ngun ngt ghp so snh v ngt trn (TOV2 v OCF2 ) Tng quan Mt s khi c rt gn ca Timer/Counter 8bit c ch ra trong hnh 61 . V s ci t ca cc chn I/O , tham kho pin Configurations trn trang 2 .CPU c th truy cp vo cc thanh ghi I/O bao gm cc bit I/O v cc chn I/O , c in m . Thanh ghi xc nh thit b v cc vng bit c lit k trong phn m t Timer/Counter 8bit trang 157 .

Cc thanh ghi Timer/Counter (TCNT2) v thanh ghi so snh u ra (OCR2) l cc thanh ghi 8bit .tn hiu Yu cu ngt (vit tt l Int.Req trong hnh v ) th c nhn thy trong thanh ghi c bo ngt Timer (TIFR) . Tt c cc ngt c che ring bit vi thanh ghi che ngt Timer (TIMSK) . TIFR v TIMSK th khng c ch ra trong hnh v do cc thanh ghi ny c chia s bi cc b phn timer khc . Timer/Counter c th b kha bn trong , thng qua b m gp trc , hoc bng mt ngun xung nhp bn ngoi trn chn T2 . Khi logic la chn xung nhp iu khin ngun xung nhp v sn Timer/Counter s dng tng (hoc gim ) gi tr ca n . Timer/Counter th khng c kch hot khi m khng c ngun xung nhp no c la chn . u ra t khi logic la chn xung nhp th c tham kho nh l mt xung nhp timer (clkT2 ) Thanh ghi so snh u ra c ghi vo b m kp (OCR2) th c so snh vi gi tr ca Timer/Counter ti tt cc thi im . Kt qu ca vic so snh c th c s dng bi

my pht dng sng pht ra 1 PWM hoc 1 u ra tn s thay i trn chn so snh u ra (OC2) . Xem Output Compare Unit trn trang 148 bit thm chi tit . Bin c ghp so snh cng s ci t c so snh (OCF2) ci m c th c s dng pht ra 1 yu cu ngt so snh u ra . Cc nh ngha Nhiu thanh ghi v cc bit tham chiu trong ti liu ny c vit theo mu chung . Mt trng hp thp n thay th cho s th t ca Timer/Counter , trong trng hp 2 . Tuy nhin khi s dng thanh ghi hoc bit xc nh trong 1 chng trnh , mu chnh xc phi c s dng (v d nh TCNT2 cho vic truy nhp vo gi tr b m Timer/Counter 2 ) Cc nh ngha trong bng 63 th cng c s dng 1 cch rng ri xuyn sut ti liu ny

Cc ngun pht xung nhp Timer/Counter Timer/Counter c th b kha bn trong bi 1 ngun xung nhp trong hoc ngoi . Ngun xung nhp c la chn bng khi logic la chn xung nhp ci m c iu khin bi cc bit la chn xung nhp(CS22:0) t trong thanh ghi iu khin Timer/Counter (TCCR2) . thm chi tit v ngun xung nhp v b m gp trc , xem thm phn cc b m gp trc trang 144 Thnh phn b m Thnh phn chnh ca b m 8bit l cc b phn m 2 hng lp trnh c. Hnh 62 ch ra s khi ca 1 b m v cc th xung quanh n

Miu t tn hiu (cc tn hiu bn trong ) Count tng hoc gim TCNT2 bng 1 Direction la chn gia tng v gim

Clear ClkTn Top Bottom

xa TCNT2 ( ci t tt c cc bit v 0) xung nhp Timer/Counter , tham kho nh l clkT0 di tn hiu rng TCNT2 va t gi tr cc i tn hiu rng TCNT2 va t gi tr cc tiu (0)

S ph thuc ca ch iu khin c s dng, b m c xa , lm tng , hoc lm gim ti mi chu k xung nhp timer (clkT2) . clkT2 c th c sinh ra t mt ngun xung nhp ngoi v bn trong , c la chn bng cc bit la chn xung nhp (CS22:0) . Khi khng c ngun xung nhp no c la chn (CS22:0 = 0 ) Timer b dng li . Tuy nhin , gi tr ca TCNT2 c th c truy nhp bng CPU , bt chp vic clkT2 c a ra hay khng . Mt CPU ghi ln (c quyn u tin cao hn ) tt c cc b m xa hoc iu khin qu trnh m . Chui m th c xc nh bng vic ci t ca cc bit WGM01:0 t trong thanh ghi iu khin Timer/Counter (TCCR2) . C nhiu kt ni ng gia cch m b m c x l v cch m dng sng c sinh ra trn u ra so snh u ra OC2 . bit thm chi tit 1 cch hon thin v cc chui m v cc b pht dng sng , xem cc ch iu khin trn trang 150 C bo trn Timer/Counter (TOV2) c ci t ln ch iu khin c la chn bng cc bit WGM2:0 . TOV2 c th c s dng cho vic pht ra 1 ngt CPU B phn so snh u ra B so snh 8bit so snh 1 cch lin tc TCNT2 vi thanh ghi so snh u ra (OCR2) . bt c u TCNT2 bng OCR2 , cc tn hiu so snh c 1 s tng ng . Mt s thch ng s ci t c bo so snh u ra (OCF2) ti chu k xung nhp tip theo . Nu c kch hot (OCIE2=1 v cc c ngt chung trong thanh ghi SREG c ci t ) , c bo so snh u ra pht ra 1 ngt so snh u ra . C bo OCF2 t ng b xa khi m ngt c thc thi . Nh mt s la chn , c OCF2 c th b xa bng phn mm bi vic vit 1 mc logic 1 ln vng bit I/O ca chng . My pht dng sng s dng cc tn hiu tng ng pht 1 u ra theo ch iu khin c ci bng cc bit WGM2:1 v cc bit ch u ra so snh (COM21:0). Cc tn hiu max v bottom th c s dng bi my pht dng sng cho vic iu khin trong cc trng hp c bit ca cc gi tr cc bin trong mt vi ch ca qu tnh iu khin (xem bng Cc ch iu khin trn trang 150) Hnh 63 ch ra s khi ca b phn so snh u ra .

Thanh ghi OCR2 c ghi vo b m kp khi s dng bt c ch iu ch rng xung no (PWM) . V cc ch bnh thng v ch iu khin CTC , b m kp c v hiu ha . B m kp ng b ha vic cp nht thanh ghi so snh OCR2 ln 1 trong 2 chui m TOP v BOTTOM . S ng b ha ny ngn cn s xut hin ca odd-length , cc xung PWM khng i xng , do vy lm cho u ra khng c nhiu sc ngang . S truy nhp thanh ghi OCR2 c th dng nh kh phc tp , nhng khng phi trong trng hp ny . Khi m b m kp c kch hot , CPU va truy nhp vo b m ca thanh ghi OCR2 , v nu b m kp b v hiu ha CPU s truy nhp OCR2 mt cch trc tip . So snh u ra cng bc Trong cc ch pht dng sng khng phi PWM , u ra tng ng ca b so snh c th b cng bc bi vic vit 1 mc logic 1 ln bit so snh u ra cng bc (FOC2) . Ghp so snh u ra cng bc ny s khng ci t c OCF2 hoc reload/clear timer , nhng chn OC2 s c cp nht nu nh 1 ghp so snh c xut hin ( vic ci t cc bit COM21:0 xc nh trng thi chn OC2 c ci t , b xa hoc di chuyn ) S kha ghp so snh bng vic vit TCNT2 Tt c cc qu trnh vit ln thanh ghi TCNT2 s kha bt k ghp so snh no ci m xut hin trong chu k xung nhp ti , d khi timer b dng li . c im ny cho php OCR2 c khi to v gi tr ging nh TCNT2 m khng khi ng 1 ngt khi xung nhp Timer/Counter c kch hot Vic s dng b phn so snh u ra Do vic vit TCNT2 trong bt c ch iu khin no s kha tt c cc ghp so snh cho 1 chu k xung nhp , c nhiu nguy c c ko theo khi thay i TCNT2 khi s dng

knh so snh u ra, s ph thuc ca trng thi Timer/Counter chy hoc khng . Nu gi tr c vit ln TCNT2 bng gi tr OCR2 , ghp so snh s b li , kt qu l qu trnh pht dng sng khng chnh xc . Mt cch tng t , khng vit gi tr TCNT2 bng gi tr BOTTOM khi m b m ang m xung Vic ci tOC2 nn c tin hnh trc vic ci t thanh ghi nh hng d liu cho chn cng ln cng ra . Cch d nht ci t gi tr OC2 l s dng cc bit u d so snh u ra cng bc trong ch bnh thng . Thanh ghi OC2 gi gi tr ca n d khi thay i gia cc ch pht dng sng nhn thy rng cc bit COM21:0 th khng c ghi vo b m cng nhau vi gi tr so snh . Vic thay i cc bit COM21:0 s to ra nh hng ngay lp tc B phn u ra ghp so snh Cc bit ch u ra so snh (COM21:0) c 2 chc nng . B pht dng sng s dng cc bit COM21:0 cho vic xc nh trng thi u ra so snh (OC2) ti ghp so snh tip theo . Cc bit COM21:0 cng iu khin chn ngun u ra OC2 . Hnh 64 ch ra mt s logic rt gn ca logic hng bng vic ci t COM21:0 . Cc thanh ghi I/O , cc bit I/O , v cc chn I/O trong hnh th c in m . Ch c cc phn ca cc thanh ghi iu khin cng I/O chung (DDR v PORT) ci m b nh hng bi cc bit COM21:0 l c ch ra . Khi tham kho ln cc trng thi ca OC2 , s tham kho l cho cc thanh ghi OC2 bn trong , khng phi cc chn OC2 . Nu tn hiu Reset h thng xut hin , thanh ghi OC2 c Reset v 0

Cc cng I/O chc nng chung c ghi bng so snh u ra (OC2) t my pht dng sng nu nh 1 trong s cc bit COM21:0 c ci t . Tuy nhin , chn nh hng OC2 ( u ra hoc u vo ) th vn c iu khin bng thanh ghi nh hng d liu (DDR) cho chn cng . Bit thanh ghi nh hng cho d liu cho chn OC2 (DDR_OC2) phi c ci t nh l u trc khi gi tr ca OC2 c nhn thy trn cng . Chc nng cng ghi th c lp trong ch pht dng sng .

Thit k ca chn logic so snh u ra cho php vic khi to ca trng thi OC2 trc khi u ra c kch hot . Ch rng vi vic ci t cc bit COM21:0 l d tr cho cc ch iu khin no . Xem bng miu t thanh ghi ca Timer/Counter 8bit trn trang 157 S pht dng sng v ch u ra so snh My pht dng sng s dng cc bit CON21:0 theo cc cch khc nhau trong ch bnh thng , CTC , v cc ch PWM. Cho tt c cc ch , vic ci t COM21:0 ni cho my pht dng sng rng khng c hnh ng no trn thanh ghi OC2 c tin hnh trn ghp so snh tip theo . V cc u ra so snh hot ng trong cc ch khng phi l PWM tham kho bng 65 trn trang 158 . V cc ch PWM , tham kho bng 66 trang 158, v cc ch PWM ng pha tham kho bng 67 trn trang 158 . Mt s thay i trng thi ca cc bit COM21:0 s c hiu lc ti ghp so snh u tin sau khi cc bit c ghi . V cc ch khng phi PWM , cc hot ng c th b cng bc c hiu lc ngay lp tc bng vic s dng cc bit phn tch FOC2 Cc ch ca qu trnh iu khin Cc ch iu khin , v d nh qu trnh x l ca Timer/Counter v cc chn so snh u ra , c xc nh bng vic kt hp ca ch Pht dng sng (WGM21:0) v cc bit ch so snh u ra (COM21:0) . Cc bit Ch u ra so snh th khng nh hng n cc chui m trong khi cc bt ch pht dng sng th c nh hng . Cc bit COM21:0 iu khin u ra ca PWM l o hay khng o (PWM o hay l khng o ) . V cc ch khng phi l PWM cc bit COM21:0 iu khin u ra nn c ci t , c xa , hoc di chuyn ti 1 ghp so snh (xem phn Compare Match Output Unit trn trang 149 . bit thm chi tit v thng tin b nh thi tham kho hnh 68 , hnh 69 , hnh 70 , hnh 71 trong cc s b nh thi Timer/Counter trang 155 Ch bnh thng Ch n gin ca qu trnh iu khin l ch normal (WGM21:0=0) . Trong ch ny vic nh hng m th lun lun ln trn (tng dn) , v khng c xa b m no c tin hnh . B m n gin trn khi n vt qua gi tr 8bit max (TOP=0xFF) v sau khi ng li t gi tr bottom (0x00) . Trong qu trnh iu khin thng thng,c bo trn Timer/Counter (TOV2) s c ci t trong cng 1 chu k xung nhp timer nh l TCNT2 tr v 0 . C bo TOV2 trong trng hp ny hnh ng nh 1 bit th 9 , ngoi tr vic n ch c ci t , khng b xa . Tuy nhin , c kt ni vi ngt trn Timer ci m t ng xa c TOV2 , chnh xc ca Timer c th c tng ln bng phn mm . Khng c trng hp c bit no c xt n trong ch bnh thng , 1 gi tr b m mi c th c vit bt c thi gian no Clear Timer on Compare Match (CTC) Mode Trong ch CTC (WGM21:0=2) , thanh ghi OCR2 c s dng iu khin chnh xc ca b m . Trong ch CTC b m b xa v 0 khi m gi tr b m (TCNT2)

tng ng vi chn OC2 . Chn OC2 xc nh gi tr TOP cho b m , do cng thay i chnh xc ca n . Ch ny cho php iu khin tt hn tn s u ra ca ghp so snh . N cng lm n gin qu trnh iu khin ca vic m cc bin c bn ngoi . Gin thi gian ca ch CTC c ch ra trong hnh 65 . Gi tr ca b m (TCNT2) tng ln cho n khi 1 ghp so snh xut hin gia TCNT2 v OCR2 v sau b m (TCNT2 ) b xa

Mt ngt c th c sinh ra mi ln m gi tr b m tin n gi tr TOP bng vic s dng c OCF2 . Nu ngt c kch hot , cc chng trnh con iu khin ngt c th c s dng cho vic cp nht gi tr TOP . Tuy nhin , vic thay i TOP ti 1 gi tr n ln BOTTOM khi m b m ang chy vi gi tr b m gp trc thp hoc khng c th phi c thc hin 1 cch thn trng t m ch CTC khng c c tnh b m kp . Nu gi tr mi c ghi ln OCR2 thp hn gi tr TCNT2 hin thi , b m s b li ghp so snh . B m sau s phi m n gi tr cc i ca n (0xFF) v bao quanh gi tr bt u ti 0x00 trc khi ghp so snh c th xut hin . vic pht ra mt u ra dng sng trong ch CTC , u ra OC2 c th c ci t di chuyn mc logic trn mi ghp so snh bng vic ci t cc bit ch u ra so snh ln ch di chuyn (COM21:0=1). Gi tr OC2 s khng th nhn thy trn chn cng tr khi s nh hng d liu cho chn c ci t ln u ra . Dng sng c pht ra s c gi tr tn s ln nht ca fOC2=fclk_I/O/2 khi m OCR2 c ci t v 0(0x00) . Tn s sng pht ra c xc nh bng cng thc di y

Bin N c a ra theo t l (1 , 8 , 64, 256 , 1024) Nh l trong ch normal , c bo TOV2 c ci t trong cng mt chu k xung nhp timer ci m b m m t gi tr MAX v 0x00 Ch fast PWM Ch iu ch rng xung nhanh hay fast PWM (WGM21:0=3) cung cp mt la chn pht dng sng PWM tn s cao . Ch fast PWM khc vi cc ch PWM khc bi qu trnh iu khin sn n ca n . B m m t BOTTOM n MAX sau bt u li t ch BOTTOM . Trong ch u ra so snh khng o , u ra so snh (OC2) b xa trn ghp so snh gia TCNT2 v OCR2 , v c ci t BOTTOM . Trong ch u ra so

snh o , u ra c ci t trn trn ghp so snh v b xa BOTTOM . D cho ch iu khin sn n , tn s iu khin ca ch fast PWM c th cao gp i ch PWM ng pha s dng ch iu khin 2 sn . Tn s cao ny lm cho ch fast PWM ph hp vi s iu chnh ngun in , s chnh lu v cc ng dng DAC . Tn s cao cho php cc thnh phn vt l c nh bn ngoi (dy cun , t in ) , v v vy gim gi thnh h thng Trong ch fast PWM , b m c lm tng cho n khi gi tr ca b m tng ng vi gi tr max. B m sau c xa ti chu k xung nhp k tip . Gin thi gian cho ch fast PWM c ch ra nh trong hnh 66 . Gi tr ca TCNT2 trong gin thi gian c ch ra nh 1 biu minh ha cho qu trnh iu khin sn n . Gin bao gm cc u ra PWM o v khng o . ng thng ng nh nh du trn sn TCNT2 a ra cc ghp so snh gia OCR2 v TCNT2

C bo trn Timer/Counter (TOV2) th c ci t mi ln m b m t ti gi tr Max nu ngt c kch hot , cc chng trnh con iu khin ngt c th c s dng cho vic cp nht cc gi tr mi . Trong ch fast PWM , b phn so snh cho php qu trnh pht ra cc dng sng PWM trn chn OC2 . Vic ci t cc bit COM21:0 ln 2 s gy ra 1 u ra PWM khng o v 1 u ra PWM o c th c sinh ra bng vic ci t cc bit COM21:0 ln 3 (xem bng 66 trang 158) Gi tr tht ca OC2 s ch c nhn thy trn chn cng nu s nh hng d liu cho cc chn cng c ci t nh l u ra . Dng sng PWM c sinh ra bng vic ci t (hoc xa ) thanh ghi OC2 ti chu k xung nhp m b m b xa (thay i t MAX n BOTTOM) Tn s PWM cho u ra c th c tnh ton bng cng thc di y : Gi tr ca bin N theo t l xch sau (1, 8, 64 , 256 , 1024) Gi tr cc bin cho thanh ghi OCR2 c a ra trong cc trng hp c bit khi m qu trnh 1 dng sng u ra PWM trong ch fast PWM . Nu OCR2 c ci t bng BOTTOM , u ra s l 1 nh hp cho mi chu k xung nhp MAX+1 . Vic ci t OCR2

bng gi tr MAX s cho kt qu l mt gi tr cao khng i hoc u ra thp (ph thuc vo phn cc ca u ra c ci t bng cc bit COM21:0) Mt tn s (vi 50% chu k ti ) dng sng u ra trong ch fast PWM c th t c bng vic ci t OC2 ln cp logic ca n di chuyn trn mi cp so snh (COM21:0 = 1 ). Dng sng c sinh ra s c tn s max ca fOC2 = fclk_I/O/2 khi m OCR2 c ci t l 0 . c im ny th tng t nh s di chuyn OC2 trong ch CTC mode , ngoi tr c im b m kp ca b phn u ra so snh c kch hot trong ch fast PWM Ch PWM ng pha Ch PWM ng pha (WGM21:0 = 1 ) cung cp mt chnh xc cao la chn pht dng sng PWM ng pha . Ch PWM ng pha th c bn da trn qu trnh iu khin 2 sn. B m m lp li t BOTTOM n MAX v sau t MAX n BOTTOM. Trong ch u ra so snh khng o , u ra so snh (OC2) b xa trn ghp so snh gia TCNT2 v OCR2 trong khi ang m ln . v ci t trn ghp so snh trong khi ang m xung . Trong ch so snh u ra o , qu trnh iu khin ny b o ngc . Ch iu khin 2 sn c tn s cc i ca qu trnh iu khin thp hn ch iu khin sn n . Tuy nhin , d cho c tnh i xng ca cc ch PWM 2 sn , cc ch ny c a thch hn cho cc ng dng iu khin ng c chnh xc ca PWM cho ch PWM ng pha l c nh 8bit Trong ch PWM ng pha , b m c lm tng cho n khi gi tr b m max khi m b m t ti gi tr MAX , n thay i hng m . Gi tr TCNT2 s bng gi tr MAX trong mi chu k xung nhp timer . Gin thi gian cho ch PWM ng pha c ch ra trong hnh 67. Gi tr TCNT2 trong gin thi gian ch ra 1 biu minh ha cho qu trnh iu khin sn kp . Biu bao gm cc u ra PWM o v khng o . . ng thng ng nh nh du trn sn TCNT2 a ra cc ghp so snh gia OCR2 v TCNT2

C bo trn Timer/Counter (TOV2) c ci t mi ln b m vn ti gi tr BOTTOM . C ngt c th c s dng pht ra mt ngt mi ln b m t ti gi tr BOTTOM. Trong ch PWM ng pha , b phn so snh cho php qu trnh pht ra cc dng sng PWM trn chn OC2 . Vic ci t cc bit COM21:0 ln 2 s gy ra 1 u ra PWM khng o v 1 u ra PWM o c th c sinh ra bng vic ci t cc bit COM21:0 ln 3 (xem bng 66 trang 158) Gi tr tht ca OC2 s ch c nhn thy trn chn cng nu s nh hng d liu cho cc chn cng c ci t nh l u ra . Dng sng PWM c sinh ra bng vic ci t (hoc xa thanh ghi OC2 ti ghp so snh gia OCR2 v TCNT2 khi m b m tnng ln , v vic ci t (hoc xa )thanh ghi OC2 ti ghp so snh gia OCR2 v TCNT2 khi m b m gim . Tn s PWM cho u ra khi s dng ch PWM ng pha c th c tnh ton bng cng thc di y

Gi tr ca bin N theo t l xch sau (1, 8, 64 , 256 , 1024) Gi tr cc bin ca thanh ghi OCR2 a ra trong cc trng hp c bit khi m vic pht ra cc u ra dng sng trong ch PWM ng pha . Nu OCR2 c ci t bng BOTTOM, u ra s lin tip mc thp v nu ci t bng MAX , u ra s tip tc mc cao trong ch PWM khng o . V cc ch PWM o u ra s c gi tr i lp li . Ti mi im bt u ca chu k 2 trong hnh 67 Ocn c 1 s chuyn i t mc cao xung mc thp d cho khng c ghp so snh no . im nh du s chuyn i ny m bo tnh i xng xung quanh BOTTOM . C 2 trng hp c s chuyn i m khng c ghp so snh : - OCR2A chuyn gi tr ca n t MAX , ging nh hnh 67 . Khi gi tr ca OCR2A l MAX , gi tr chn OCn th ging nh kt qu ca 1 ghp so snh m xung . m bo tnh i xng xung quanh BOTTOM , gi tr ca OCn ti MAX phi tng ng vi kt qu ca mt ghp so snh m ln . - Timer bt u m t 1 gi tr cao hn 1 trong OCR2A , v v l do ny m cc li ca ghp do snh v do OCn thay i cch m n xut hin trn ng ln . Gin thi gian ca Timer/Counter Timer/Counter l mt thit k ng b v xung nhp timer (clkT2) v vy c ch ra nh l 1 tn hiu kch hot xung nhp trong cc hnh di y . Cc hnh bao gm cc d kin khi m cc c ngt c ci t . Hnh 88 bao gm d liu thi gian cho qu trnh iu khin Timer/Counter c bn . Hnh ch ra cc chui m ng n cc gi tr MAX trong tt c cc ch khc hn l ch PWM ng pha

S miu t thanh ghi Timer/Counter 8bit Thanh ghi iu khin Timer/Counter TCCR2

Bit 7 FOC2 : so snh u ra cng bc Bit FOC2 ch hot ng khi bit WGM20 xc nh ch khng phi PWM . Tuy nhin , m bo tnh tng thch vi cc thit b trong tng lai , bit ny phi c ci t l 0 khi m TCCR2 c ghi khi hot ng trong ch PWM . Khi vit 1 mc logic 1 ln bit FOC2 , 1 ghp so snh ngay trung gian b cng bc trn b phn pht dng sng . u ra

OC2 b thay i theo vic ci t cc bit COM21;0 ca n . Ch rng bit FOC2 th thc hin nh l 1 u d(strobe) . V vy n l gi tr c a ra trong cc bit COM21:0 ci m xc nh nh hng ca so snh cng bc Mt u d FOC2 s khng pht ra bt c ngt no , cng s khng xa Timer trong ch CTC s dng OCR2 nh l gi tr TOP. Bit FOC2 th lun c c l 0 Bit 6,3 WGM21:0 : ch pht dng sng Cc bit ny iu khin chui m ca b m , ngun cho gi tr m cc i TOP , v loi m pht dng sng c s dng . Cc ch iu khin h tr bi b phn Timer/Counter l : Ch Normal , ch CTC , v 2 loi ca cc ch iu ch rng xung PWM , xem bng 64 v cc ch iu khin trang 150

Bit 5:4 COM21:0 : ch u ra ghp so snh Cc bit ny iu khin chn x l so snh u ra (OC2) . Nu 1 trong 2 bit COM21:0 c ci t , u ra OC2 ghi ln cng chc nng thng thng ca chn I/O m n c ni n . Tuy nhin , ch rng bit thanh ghi nh hng d liu (DDR) tng ng n chn OC2 phi c ci t theo th t kch hot b iu khin u ra Khi OC2 c ni vi chn , chc nng ca cc bit COM21:0 ph thuc vo vic ci t bit WGM21:0 . Bng 65 ch ra chc nng ca bit COM21:0 khi cc bit WGM21:0 c ci t n ch bnh thng hoc ch CTC (khng phi PWM)

Bng 66 ch ra cc bit chc nng COM21:0 khi m cc bit WGM21:0 c ci t trong ch fast PWM

Bng 67 ch ra chc nng ca bit COM21:0 khi m cc bit WGM21:0 c ci t trong ch PWM ng pha

Bit 2:0 CS22 : la chn xung nhp C 3 bit la chn xung nhp la chn ngun xung nhp s c s dng bi Timer/Counter

Nu cc ch chn ngoi c s dng cho Timer/Counter 2 th vic chuyn i trn chn T2 s kha b m d nu chn c cu hnh nh l 1 u ra . c im ny cho php phn mm iu khin vic m Thanh ghi Timer/Counter TCNT2

Thanh ghi Timer/Counter a ra s truy cp trc tip , c hai qu trnh c v ghi ln b m Timer/Counter 8 bit . Vic vit thanh ghi TCNT2 kha (g b ) ghp so snh trn cc xung nhp k tip . Qu trnh sa i b m (TCNT2) trong khi b m ang chy , a ra 1 nguy c li ghp so snh gia thanh ghi TCNT2 v OCR2 Thanh ghi so snh u ra OCR2

Thanh ghi so snh u ra bao gm 1 gi tr 8bit ci m c so snh 1 cch lin tc vi gi tr b m (TCNT2) . Mt ghp c th c s dng sinh ra 1 ngt so snh u ra , hoc pht ra 1 u ra dng sng trn chn OC2 Thanh ghi che ngt Timer/Counter - TIMSK

Bit 7 OCIE2 : kch hot ngt ghp so snh u ra Timer/Counter Khi bit OCIE2 c ghi l 1 , v bit I trong thanh ghi trng thi c t l 1 , ngt ghp so snh Timer/Counter 2 c kch hot . Ngt tng ng c thc thi nu 1 ghp so snh trong Timer/Counter xut hin v d khi bit OCF2 c ci t trong thanh ghi c bo ngt Timer/Counter TIFR Bit 6 TOIE2 : kch hot ngt trn Timer/Counter2 Khi bit TOIE2 c ghi l 1 , v bit I trong thanh ghi trng thi c ci t l 1 , ngt trn Timer/Counter 2 c kch hot . Ngt tng ng c thc thi nu 1 c bo trn trong Timer/Counter 2 xut hin vdu , khi bit TOV2 c ci t trong thanh ghi c bo ngt Timer/Counter TIFR Thanh ghi c bo ngt Timer/Counter TIFR

Bit 7 OCF2 : c ghp so snh 2 Bit OCF2 c ci t l 1 khi 1 ghp so snh xut hin gia Timer/Counter v d liu trong OCR2 thanh ghi so snh u ra 2 . OCF2 b xa bng phn cng khi qu trnh thc thi cc vecto iu khin ngt tng ng . Nh mt s la chn , OCF2 b xa bng vic vit 1 mc logic 1 ln c . Khi m bit I trong SREG , OCIE2 ( kch hot ngt ghp so snh Timer/Counter2) v OCF2 c t l 1 , ngt ghp so snh Timer/Counter 2 c thc thi . Bit 6 TOV2 : c bo trn Timer/Counter 2 Bit TOV2 c ci t l 1 khi 1 s trn xut hin trong Timer/Counter 2 , TOV2 b xa bng phn cng khi m vic thc thi cc vecto iu khin cc ngt tng ng . Nh mt s la chn , TOV2 b xa bng vic vit mt mc logic 1 ln c . Khi m bit I trong SREG , TOIE2 (kch hot ngt trn Timer/Counter 2 ) v TOV2 c ci t l 1 , ngt trn Timer/Counter 2 c thc thi . Trong ch PWM , bit ny c ci t khi Timer/Counter 2 thay i vic m hng m ti $00

XV . Khi module so snh u ra (OCM1C2) Output Compare Modulator Tng qut Module so snh u ra (OCM) cho php qu trnh pht sinh ca sng iu ch vi 1 tn s mang . B iu ch s dng cc u ra t b phn so snh u ra C ca Timer/Counter1 -16bit v b phn so snh u ra ca Timer/Counter2- 8bit . bit thm chi tit v cc Timer/Counter xem 16bit Timer/Counter (Timer/Counter 1 v Timer/Counter 3 ) trang 112 v Timer/Counter2 8bit vi ch PWM trang 146 . Ch rng c im ny th khng kh dng trong ch tng thch vi Atmega 103 .

Khi b iu ch c kch hot , 2 knh so snh u ra th c iu ch cng nhau nh c ch trong s khi (hnh 72) Miu t B phn so snh u vo 1C v so snh u vo 2 chia s chn cng PB7 nh l cng ra . u ra ca cc b so snh u ra (OC1C v OC2) ghi ln thanh ghi cng PORTB7 thng thng khi m 1 trong s chng c kch hot (V d : khi m bt COMnx1 : 0 khng bng 0 ) khi c 2 b so snh ngoi . OC1C v OC2 c kch hot trong cng 1 thi gian , b iu ch s t ng c kch hot S chc nng tng ng ca b iu ch c ch ra trong hnh 73 . S th bao gm cc phn ca b Timer/Counter v mch iu khin u ra chn s 7 ca cng B

Khi m b iu ch c kch hot loi ca s iu ch (cc bin logic And v Or ) c th c la chn bng thanh ghi PORTB7 . Ch rng thanh ghi DDRB7 iu khin hng ca cng ph thuc vo vic ci t bt COMnx1 :0 V d v gin thi gian : Timing Example Hnh 74 minh ha 1 b iu ch ng hot ng . Trong v d ny b Timer/Counter 1 c ci t iu khin trong ch Fast PWM ( khng o) v b Timer/Counter 2 s dng ch pht xung CTC vi ch u ra so snh di chuyn (Bt COMnx1 :0 = 1 )

Trong v d ny , Timer/Counter 2 cung cp 1 sng mang , trong khi tn hiu iu ch c sinh ra bi b phn so snh u ra C ca Timer/Counter 1 chnh xc ca tn hiu PWM (OC1C ) th b suy gim bi qu trnh iu ch . T l suy gim th bng s th t ca cc chu k xung nhp h thng ca 1 chu k ca sng mang (OC2) .Trong ch ny , chnh xc b suy gim bi 1 t l vi 2 . Nguyn nhn ca s suy gim ny c minh ha trong hnh 74 chu k th 2 v th 3 ca u ra PB7 khi m bt PORTB7 = 0 . Thi gian cao hn chu k th 2 l 1 chu k xung nhp di hn trong thi gian cao ca chu k th 3 , nhng kt qu thu c trn cng ra PB7 th bng c 2 chu k u .

XVI . Giao din ngoi vi ni tip Serial peripheral interface SPI

Giao din ngoi vi ni tip (SPI) cho php chuyn d liu ng b tc cao giao Atmega128 v cc thit b ngoi vi hoc gia nhiu thit b AVR vi nhau . Giao din ngoi vi ni tip (SPI) bao gm cc c im di y - Full duplex (Truyn song cng ) , chuyn d liu ng b 3 dy (Three wire) - Ch iu khin Master / Slave - Chuyn d liu MSB First hoc LSB First - 7 bt rate c th lp trnh - C ngt cui ch truyn ti

- Write Collision Flag Protection - nh thc khi ch ch Idle - Ch SPI Master (CK/2 ) Tc kp

Kt ni gia cc CPU Slave v master vi SPI c ch ra trong hnh 76 . H thng th bao gm 2 thanh ghi Shift v b to xung nhp Master . SPI Master khi to 1 chu k giao tip khi m c sn xung xung ca Slave la chn chn SS ca Derised Slave . Master v Slave chun b d liu gi vo cc thanh ghi Shift tng ng ca chng , v master sinh ra 1 xung nhp cn thit trn nhnh SCK chuyn tip d liu . D liu th c chuyn t Master sang Slave trn u ra Master Out -> u vo Slave In , MOSI , cc nhnh , v t Slave n Master bng chn Master In -> Slave Out , MISO , line . Sau mi gi d liu , Master s ng b ha vi Slave bng 1 xung cao la chn Slave , Bt SS , Line . Khi c cu hnh nh l 1 Master , giao din SPI khng c s t ng iu khin ca ng SS . Vic ny phi c iu khin bng phn mm ngi s dng trc khi qu trnh giao tip c th bt u . Khi n c thc hin vic vit 1 Byte ln thanh ghi d liu SPI s khi ng b to xung nhp SPI v phn cng s di chuyn 8 bt d liu vo trong Slave . Sau khi di chuyn 1 Byte , b to xung nhp SPI dng li , vic ci t c bo kt thc qu trnh chuyn d liu (SPIF) . Nu nh ngt SPI kch hot bt (SPIE ) trong thanh ghi SPCR c ci t , 1 ngt c truy vn . Master c th tip tc chuyn byte d liu tip theo bng vic vit vo trong SPDR hoc tn hiu kt thc ca gi d liu bng xung cao c Slave la chn

, nhnh SS . Byte n cui cng s c gi trong b m ca thanh ghi cho ln s dng cui cng . Khi c cu hnh nh l Slave , giao din SPI s remain sleeping vi 3 trng thi MISO ch cn chn SS c iu khin mc cao . Trong trng thi ny , phn mm c th cp nht cc thanh ghi d liu SPI SPDR , nhng d liu s khng c dy chuyn ra ngoi bng nhng xung nhp n trn chn SCK cho n khi chn SS c iu khin mc thp . 1 byte va hon thnh s di chuyn th c bo kt thc s di chuyn SPIF c ci t . Nu nh ngt SPI kch hot bt SPIE trong thanh ghi SPCR c ci t , 1 ngt c yu cu . Slave c th tip tc t d liu mi gi vo trong thanh ghi SPDR trc khi qu trnh c d liu n tip tc . Byte n cui cng s c d trong b m ca thanh ghi sau ln s dng .

H thng c ghi vo b m n trong qu trnh nh hng chuyn d liu v c ghi vo b m kp trong qu trnh nh hng d liu n . iu ny c ngha l cc byte c di chuyn khng th c ghi vo thanh ghi d liu SPI trc khi ton b chu k chuyn di c hon thnh . Khi d liu ang n , tuy nhin 1 k t n phi c c t thanh ghi d liu SPI trc khi k t tip theo c di chuyn vo trong hon ton . Ni cch khc bt u tin b mt . Trong ch SPI Slave qu trnh iu khin logic s ly mu tn hiu n ca chn SCK m bo vic ly mu chnh xc ca tn hiu xung nhp mc thp cc tiu v mc cao ca chu k nn l : - Chu k thp : ngn hn 2 ln chu k xung nhp CPU - Chu k cao : di hn 2 ln chu k xung nhp CPU Khi m SPI c kch hot , hng d liu ca cc chn MOSI , MISO ,SCK , SS c ghi theo bng 69 . bit thm chi tit v cng t ng ghi tham kho phn Alternate Port Function trn trang 71

on code mu di y ch ra cch khi to 1 SPI nh l 1 Master v cch tin hnh 1 qu trnh chuyn d liu n gin . DDR_SPI trong cc v d phi c thay i bng cc chn SPI iu khin thanh ghi nh hng d liu tht s . DD_MOSI , DD_MISO v DD_SCK phi c thay th bng cc bt nh hng d liu tht s cho cc chn ny . V d : nu nh MOSI c t ln chn PB5 , thay th DD_MOSI vi DDB5 v DDR_SPI vi DDRB

on code mu di y ch ra cch khi to SPI nh l 1 Slave v cch tin hnh 1 qu trnh tip nhn n gin

Chc nng ca chn SS Ch Slave Khi SPI c cu hnh nh l 1 Slave , chn la chn Slave (SS) th lun lun l u vo . Khi SS c d mc thp SPI c kch hot v MISO tr thnh 1 u ra nu c cu hnh bi ngi s dng . Tt c cc chn khc u l u vo . Khi SS c iu khin mc cao , tt c cc u vo chp nhn MISO ci m c th c ngi s dng cu hnh nh l 1 u ra v SPI b ng , iu ny ngha l n s khng nhn tn hiu n . Ch rng SPI s c reset 1 ln khi chn SS mc cao . Chn SS th hu dng cho vic ng b ha cc gi v cc bt gi bt Slave ca b n d b vi b to xung nhp Master . Khi m chn SS mc cao , SPI Slave s ngay lp tc c Reset gi v nhn cc gi tr Logic , v th bt c phn d liu n vo trong thanh ghi Shift . Ch Master

Khi SPI c cu hnh nh l 1 Master (Bit MSTR trong thanh ghi STCR c ci t = 1 ) ngi s dng c th xc nh hng ca cng SS Nu chn SS c cu hnh nh l 1 u ra chn ny l 1 u ra chung ci m khng gy nh hng n h thng SPI . Thng thng chn ny s c iu khin trong ch SPI Slave Nu SS c cu hnh nh l 1 u vo , n phi c gi mc cao m bo cho qu trnh iu khin SPI Master . Nu nh SS c iu khin mc thp bng cc mch ngoi vi khi m SPI c cu hnh nh l 1 Master vi chn SS c xc nh nh l , h thng SPI s bin dch iu ny nh l 1 Master khc la chn SPI nh l 1 Slave v n c khi ng gi d liu vo trong n . trnh vic tranh ginh bus , h thng SPI to ra cc hnh ng di y - Bit MSTR trong thanh ghi STCR b xa v h thng SPI tr thnh 1 Slave . Nh l kt qu ca vic SPI tr thnh Slave cc chn MOSI v SCK tr thnh 1 u vo - C SPIF trong thanh ghi SPSR c ci t , v nu ngt ca SPI c kch hot , bt I trong SREG c ci t th cc chng trnh con phc v ngt c thc thi V vy , khi ngt iu khin qu trnh chuyn d liu SPI c s dng trong ch Master , v kh nng tn ti ca chn SS mc thp , cc ngt nn lun lun c kim tra xem l bt MSTR vn c ci t hay khng . Nu bt MSTR va b xa bng chn la chn ch Slave (Slave Select ) , n phi c ci t bng ngi s dng kch hot li ch SPI Master . Thanh ghi iu khin SPI_SPCR Bt 7_SPIE : kch hot ngt SPI Bt ny gy ra gy ra ngt SPI thc thi nu bt SPIF trong thanh ghi SPSR c t v nu cc bt kch hot chung trong thanh ghi SREG c t Bt 6_SPE : kch hot SPI Khi bt SPE c khi l 1 th SPI c kch hot . Bt ny phi c ci t kch hot bt c qu trnh iu khin SPI no Bt 5_DODR : th t d liu Khi bt DODR c ghi l 1 LSB (bt thp nht) ca t d liu (data word ) c di chuyn u tin Khi bt DODR c khi l 0 MSB (bt cao nht) ca t d liu (data word ) c di chuyn u tin Bt 4_MSTR : la chn ch Master Slave Bt ny la chn ch Master SPI khi n c ghi l 1 v ch Slave SPI khi n c ghi l 0 . Nu chn SS c cu hnh nh l 1 u vo v c iu khin mc thp trong khi bt MSTR c ci t th MSTR s b xa v bt SPIF trong thanh ghi SPSR s c ci t . Ngi s dng sau s phi ci t bt MSTR kch hot li ch SPI Master Bt 3_CPOL : Clock polarity .

Khi bt ny c vit l 1 , SCK mc cao khi trong ch Idle . Khi CPOL c vit l 0 th SCK mc thp khi bn . Tham kho hnh 77 . 78 nh l 1 v d . Chc nng ca CPOL c lit k chi tit bn di

Bt 2_CPHA : Pha xung nhp Vic ci t bt CPHA xc nh nu d liu c ly mu trn sn u tin hoc sn cui cng ca SCK .Tham kho hnh 77 , 78 . Chc nng ca CPHA c lit k bn di

Bt 1,0_SPR1,SPR0 : la chn tc xung nhp SPI 1 hoc 0 Hai bt ny iu khin tc SCK ca 1 thit b c cu hnh nh l 1 Master . SPR1 v SPR0 khng c hiu lc trong ch Slave . S lin quan gia SCK v tn s xung nhp ca b to giao ng fOCS c ch ra trong bng di y

Thanh ghi trng thi SPI Bt 7_SPIF : C ngt SPI Khi 1 s chuyn dch ni tip c hon thnh, c SPIF c ci t . Mt ngt c sinh ra nu SPIE trong thanh ghi SPCR c ci t v cc ngt chung c kch hot . Nu nh SS l 1 u vo v c iu khin mc thp khi m SPI trong ch Master , iu ny cng s ci t c SPIF . SPIF b xa bng phn cng khi m ang thc thi cc Vector iu khin ngt tng ng . Nh 1 s la chn , bt SPIF b xa bng qu trnh c u tin ca thanh ghi trng thi SPI vi SPIF c ci t , sau khi vic truy nhp vo thanh ghi SPI (SPDR ) Bt 6_WCOL : Vit c Collision

Bt WCOL c ci t nu thanh ghi d liu SPI (SPDR) c vit trong sut qu trnh chuyn i d liu . Bt WCOL (v bt SPIF ) b xa bi qu trnh c u tin ca thanh ghi trng thi SPI vi WCOL c ci t v sau truy nhp vo thanh ghi trng thi SPI . Bt 51_RES : cc bt d tr Cc bt ny l cc bt d tr trong Atmega128 v s lun lun c c l 0 Bt 0_SPI2X : Bt tc SPI kp Khi bt ny c ghi l 1 , tc ca SPI (tn s SCK) s c gp li khi m SPI trong ch Master (xem bng 72) . iu ny c ngha l chu k SCK cc tiu s bng 2 ln chu k xung nhp ca CPU . Khi SPI c cu hnh nh l Slave , SPI ch m bo lm vic ti tn s fOSC /4 hoc thp hn Giao in SPI trong Atmega 128 cng c s dng cho b nh chng trnh v vic download v upload d liu ca EEPROM . Xem bng 300 them chi tit v phn lp trnh ni tip SPI v s xc minh (Verification ) Thanh ghi d liu SPI_SPDR Thanh ghi d liu SPI l 1 thanh ghi Read Write c s dng cho vic chuyn d liu gia cc file ng k v cc thanh ghi Shift SPI vic ghi ln cc thanh ghi s bt u 1 qu trnh chuyn d liu . Vic c cc thanh ghi gy ln vic b m d liu m trong thanh ghi Shift c c Cc ch d liu C 4 s kt hp ca pha SCK v polarity vi s tn trng n cc d liu ni tip, ci m c xc nh bng cch bt iu khin CPHA v CPOL . nh dng chuyn d liu SPI th c ch ra trong hnh 77 , 78 . Cc bt d liu c di chuyn ra ngoi v c cht sn i din ca tn hiu SCK m bo thi gian cho cc tn hiu tr v trng thi n nh . iu ny r rng c nhn thy bng 70 . 71

XVII . USART
B chuyn pht v thu nhn ni tip ng b d b vn nng ( Uinversal Synchronous and Asychronous serial Receiver and Transmitter USART l 1 thit b truyn thng ni tip c linh hot cao . Cc c im chnh l : - Hot ng song cng (full duplex) ( ph thuc vo cc thanh ghi chuyn pht v thu nhn ni tip ) - Hot ng ng b hoc d b - Hot ng ng b ha kha Master hoc Slave - My pht tc Baud chnh xc cao - H tr truyn cc khung ni tip vi 5 ,6 ,7, 8 hoc 9 bit d liu v 1 hoc 2 bit stop - S to bc chn hoc l v h tr kim tra tnh chn l bng phn cng . - S d trn d liu - D li khung truyn - B lc di thp k thut s v s d bit khi ng li bao gm b lc nhiu . - 3 ngt ring bit trn trn b TX , trng thanh ghi d liu TX , trn b RX - Ch truyn thng nhiu b s l - Ch truyn thng d b tc kp USART kp Dual USART Atmega 128 c 2 b USART , l USART0 v USART1 . Chc nng ca c hai b USART th c miu t bn di . USART0 v USART1 c cc thanh ghi I/O khc nhau c ch ra trong phn Register Summary trang 362 . Ch rng trong ch tng thch vi Atmega 103 , USART1 th khng kh dng , ch c cc thanh ghi l UBRR0H v UCRS0C . iu ny c ngha l trong ch tng thch vi Atmega 103 , Atmega 128 h tr cc qu trnh iu khin d b ca ch USART0 Tng quan Mt s khi rt gn ca b chuyn pht USART c ch ra trong hnh 79 . CPU c th truy nhp vo cc thanh ghi v cc chn I/O c in m

Cc hp nt t trong s khi phn chia thnh 3 phn chnh ca USART (c lit k t trn xung ) : b pht xung nhp , b chuyn pht , b thu nhn tn hiu . Cc thanh ghi iu khin th b chia s bi tt c cc b phn . Khi logic pht xung nhp th bao gm khi logic ng b cc u vo xung nhp bn ngoi c s dng bi qu trnh iu khin Slave ng b , v my pht baud rate . Chn XCK (xung nhp chuyn ) th ch c s dng bi ch truyn ng b . B chuyn pht bao gm 1 b m ghi n , 1 thanh ghi Shift ni tip , my pht tng t (Parity) v khi iu khin logic cho vic iu khin cc dng khung ni tip khc nhau . B m ghi cho php 1 s truyn lin tip ca d liu m khng c bt c1 tr no gia cc khung . B thu nhn (Receiver) l b phn phc tp nht ca module USART v xung nhp ca v cc b phn phc hi d liu. Cc b phn khi phc (Recovery) c s dng cho vic thu nhn d liu 1 cch d b . Thm vo khi phc cc b phn ny , b thu nhn bao gm b kim tra parity , khi logic iu khin , 1 thanh ghi Register v 1 b m thu nhn 2 cp (UDR) . B thu nhn tn hiu h tr cc dng khung ging nhau nh l b chuyn pht , v c th d li khung , trn d liu v cc li parity .

AVR USART v AVR UART ch tng thch USART th tng thch y vi AVR UART bt chp : - a ch bit bn trong ca cc thanh ghi USART - S pht Baud Rate - Chc nng b m chuyn pht - Qu trnh thu nhn tn hiu Tuy nhin , b m ca b thu nhn c 2 s ci tin rng s nh hng n s tng thch trong mt vi trng hp c bit : - 1 thanh ghi b m th 2 va c thm vo . 2 thanh ghi b m hot ng nh 1 b m FIFO vng trn . V vy UDR ch phi c mt ln cho mi d liu n . Quan trng hn l nu l cc c bo li (FE v DOR) v bit d liu th 9 (RXB8) c ghi vo b m vi d liu trong b m ca b thu tn hiu . V vy cc bit trng thi phi lun c c trc khi thanh ghi UDR c c . Ni cch khc trng thi li s mt do trng thi b m b mt . - 1 thanh ghi Shift ca b thu c th ng vai tr nh mt mc m th 3 . iu ny c thc hin bng vic cho php d liu n ti v tr cn li trong thanh ghi Shift ni tip (xem hnh 79 ) Nu cc thanh ghi b m b y , cho n khi 1 bit khi ng c tm ra . USART v vy cc iu kin chng trn d liu (DOR) bn vng hn . Cc bit iu khin di y c thay i tn , nhng c chc nng ging v cng a ch thanh ghi : - CHR9 c i thnh UCSZ2 - OR c i thnh DOR Qu trnh pht xung nhp Khi logic pht xung nhp pht ra cc xung nhp c bn cho cc b chuyn pht v b thu nhn tn hiu . USART h tr 4 ch ca qu trnh iu khin xung nhp : d b thng thng , d b tc kp , Master ng b , v slave ng b . Bit UMSEL trong thanh ghi C trng thi v iu khin USART (UCSRC) la chn gia qu trnh iu khin ng b v d b . Tc kp (ch trong ch d b ) th c iu khin da trn U2X trong thanh ghi UCSRA . Khi vic s dng ch ng b (UMSEL=1) , thanh ghi nh hng d liu cho chn XCK (DDR_XCK) iu khin la chn ngun xung nhp l bn trong (Master Mode) hay bn ngoi (Slave Mode ) . Chn XCK ny th ch hot ng khi s dng ch ng b .

S miu t tn hiu : - txclk : xung nhp b chuyn pht .(tn hiu bn trong ) - rxclk : xung nhp c bn ca b thu nhn tn hiu . (tn hiu bn trong ) - xcki : u vo t chn XCK (tn hiu bn trong ) . c s dng cho qu trnh iu khin slave ng b - xcko : xung nhp u ra ti chn XCK (tn hiu bn trong ) . c s dng cho qu trnh iu khin ng b - fosc : tn s chn XTAL ( xung nhp h thng ) S pht xung nhp bn trong my pht Baud rate S pht xung nhp bn trong c s dng cho cc ch master ng b ha v d b ca qu trnh iu khin . S miu t trong phn ny tham kho hnh 80 Thanh ghi Baud rate USART (UBRR) v b m xung c kt ni vi ti cng chc nng ca n nh l mt b m gp trc c th lp trnh c hoc my pht baud rate . B m xung (down counter), ang chy tn s xung nhp h thng (fOCS) , c ti vi gi tr ca UBRR mi ln m b m va m xung n 0 hoc khi thanh ghi UBRRL c ghi . 1 xung nhp c pht ra mi ln m b m t n gi tr 0 . Xung nhp ny l u ra my pht baud rate (=fOSC/UBRR+1) . B chuyn pht chia u ra xung nhp my pht baud rate thnh 2, 8 , 16 ph thuc vo ch . u ra my pht Baud rate c s dng 1 cch trc tip bi xung nhp ca b thu nhn v cc b phn khi phc d liu . Tuy nhin , cc b phn khi phc d liu s dng mt state machine ci m s dng 2 , 8, 16 trng thi ph thuc vo ch c ci t bng trng thi ca cc bit UMSEL , U2X v DDR_XCK Bng 74 bao gm cc cng thc tnh ton baud rate (in bits per second ) v cho vic tnh ton gi tr ca UBRR cho mi ch ca qu trnh iu khin ca 1 ngun xung nhp c pht ra bn trong .

Vi v d ca cc gi tr UBRR cho vi tn s xung nhp h thng c tm ra trong bng 82 (Xem bng 194) Qu trnh iu khin tc kp (U2X) Tc chuyn d liu c th c nhn i bng vic ci t bit U2X trong thanh ghi UCSRA . Vic ci t bit ny ch gy nh hng cho qu trnh iu khin d b . Ci t bit ny l 0 khi s dng ch iu khin ng b Vic ci t bit ny s gim c chia ca b chia baud rate t 16 xung 8 , nhn i 1 cch hiu qu tc truyn d liu cho ch truyn thng khng ng b . Tuy nhin ch rng b thu tn hiu trong trng hp ny s ch s dng 1 na cc ly mu (gim t 16 xung 8 ) cho vic ly mu d liu v khi phc xung nhp , v vy vic ci t baud rate chnh xc hn v xung nhp h thng l cn thit khi m ch khi ch ny c s dng . V cc b chuyn i , khng c downside no . Xung nhp bn ngoi Xung nhp bn ngoi c s dng bi qu trnh iu khin slave ng b . S miu t trong phn ny tham kho hnh 80 bit thm chi tit Du vo xung nhp bn ngoi t chn XCK th c ly mu bng thangh ghi ng b ha lm cc tiu xc xut ca s mt n nh (meta-stability). u ra t thanh ghi ng b ha phi c i qua 1 b d sn trc khi n c th c s dng bi b chuyn pht v b thu nhn tn hiu . Qu trnh ny a vo trong 2 tr ca chu k xung nhp CPU v vy tn s xung nhp XCK bn ngoi cc i th c gii hn bi cng thc sau Ch rng fOSC ph thuc vo n nh ca ngun pht xung nhp h thng . V vy n c khuyn co thm vo vi bin trnh cc s mt mt c th ca s bin thin tn s d liu .

Diu khin xung nhp mt cch ng b Khi ch ng b c s dng (UMSEL =1) , chn XCK s c s dng nh l u vo xung nhp (slave ) hoc u ra xung nhp (Master). S ph thuc gia cc sn xung v s ly mu d liu hoc s thay i d liu l ging nhau . Nguyn tc c bn l ci m d liu u vo (on RxD ) c ly mu ti v tr i din ca sn xung XCK ca sn u vo d liu(TxD) b thay i .

Cc bit UCPOL v Bit UCRSC la chn ci m sn xung XCK c s dng cho vic ly mu d liu v ci m c s dng thay i d liu . Nh hnh 81 ch ra , khi UCPOL l 0 th d liu s b thay i ti sn ln ca xung XCK v c ly mu ti sn xung ca xung XCK . Nu UCPOL c ci t , d liu s b thay i ti sn xung ca xung XCK v c ly mu ti sn ln ca xung XCK Cc dng khung d liu Frame Formats Mt lot cc khung c xc nh bng 1 k t ca cc bit d liu vi cc bit ca b ng b ha (cc bit start v stop ) , v mt s la chn ca cc bit chn l cho vic kim tra cc li . USART chp nhn tt c 30 s kt hp k tip nh l cc dng khung c hiu lc - 1 bit start - 5 ,6 ,7 ,8 hoc 9 bit d liu - Khng c , hoc c cc bit chn l - 1 hoc 2 bit stop 1 khung bt u vi bit start c theo sau l bit d liu c ngha b nht . Sau tip theo l cc bit d liu , nng tng s ln 9 bit , v k tip , kt thc l bit c trng s cao nht . Nu c kch hot , bit chn l c chn sau cc bit d liu , trc cc bit stop . Khi 1 khung hon thnh c chuyn i , n c th c dn theo mt khung mi , hoc 1 ng giao tip na c th c ci t trong trng thi Idle (high ) Hnh 82 minh ha s kt hp c th ca cc dng khung truyn . Cc bit trong ngoc l la chn .

St bt start , lun lun mc thp (n) cc bit d liu (t 0 n 8 ) P bit chn l . c th l l hoc chn Sp bit Stop , lun mc cao IDLE : khng c qu trnh chuyn pht no trn ng giao tip d liu (RxD hoc TxD). Mt ng IDLE phi mc cao Dng khung truyn c s dng bi USART c ci t bng bit UCSZ2:0, UPM1:0 v cc bit USBS trong thanh ghi UCSRB v UCSRC . B thu nhn v chuyn pht s dng cc ci t ging nhau . Ch rng vic thay i s ci t ca bt c bit no trong s cc bit ny s lm hng tt c cc giao tip ang tin hnh ca c b thu nhn v chuyn pht . Cc bit kch c k t ca USART la chn s lng ca cc bit d liu trong mt khung. Cc bit Ch USART tng ng (UPM1:0) kch hot v ci t cc loi ca bit chn l . S la chn gia 1 hoc 2 bit Stop c thc hin bng bit la chn bit Stop (USBS). B thu nhn b qua bit stop th hai . Mt li khung truyn (FE) v vy ch c tm ra trong cc khung ni m bit stop u tin l 0 S tnh ton bit chn l - Parity Bit Calculation Bit chn l th c tnh ton bng vic exclusive-or ca tt c cc bit d liu . Nu bit l c s dng, kt qu ca qu trnh exclusive-or b o ngc . S lin quan gia bit chn l v cc bit d liu nh bn di : Peven bit chn l s dng bc chn Podd bit chn l s dng bc l dn bit d liu n ca chui k t Nu c s dng, bit chn l c t gia bit d liu cui v bit stop u tin ca chui khung S khi to USART USART phi c khi to trc khi bt c mt giao tip no c th xy ra . Qu trnh khi to thng thng bao gm vic ci t cc baud rate , vic ci t cc dng khung v kch hot cc b thu nhn v chuyn pht ph thuc vo yu cu s dng. V hot ng ca cc ngt iu khin USART , c bo ngt chung nn b xa (v cc ngt chung b v hiu ha ) khi ang trong qu trnh khi to Trc khi thc hin 1 s khi to li vi cc baud rate c thay i hoc l cc dng khung truyn khc , phi m bo rng khng c qu trnh truyn pht no ang tin hnh trong sut giai on m thanh ghi b thay i . C TXC c th c s dng kim tra rng b chuyn pht va hon thnh tt c cc s di chuyn , v c RXC c th c s dng

 kim tra rng khng c d liu cha c c trong b m ca b thu nhn. Ch rng c TXC phi c xa trc mi qu trnh truyn d liu(trc UDR c ghi ) nu n c s dng cho chc nng ny on m mu v s khi to USART n gin bn di ch ra mt hm C v assembly ci m bng nhau v chc nng . Cc v d th gi nh rng ch iu khin d b s dng ch hi theo vng(Polling) (khng c ngt no c kch hot )v 1 dng khung truyn n nh . Baud rate th c a ra nh l 2 tham s chc nng. V on m Assembly , tham s baud rate th c gi nh l c lu tr trong thanh ghi r17:r16

S truyn d liu b chuyn pht USART Mt b chuyn pht USART c kch hot bng vic ci t bit kch hot di chuyn (TXEN) trong thanh ghi UCSRB . Khi b chuyn pht c kch hot , ch iu khin cng bnh thng ca chn TxD b ghi bng USART v a ra cc chc nng nh l cc cng ra ni tip ca b chuyn pht . Baud rate , ch iu khin v cc dng khung truyn phi c ci t ln mt ln trc khi thc hin qu trnh truyn d liu . Nu ch iu

khin ng b c s dng , xung nhp trn chn XCK s b ghi v c s dng nh l xung nhp ca qu trnh truyn d liu Vic gi cc khung vi 5 dn 8 bit d liu Mt qu trnh truyn d liu c khi to bng vic ti b m pht vi d liu c pht . CPU c th ti b m d liu bng vic vit ln vng I/O UDR . D liu c ghi vo b m trong b m pht s b di chuyn vo thanh ghi Shift khi m thanh ghi Shift sn sng gi 1 khung mi . Thanh ghi Shift c ti vi cc d liu mi nu n trong trng thi Idle(khng c s chuyn pht d liu no ang tin hnh ) hoc ngay lp tc sau khi bit stop cui cng ca khung trc c pht i . Khi thanh ghi Shift c ti vi d liu mi, n s pht 1 khung truyn hon chnh ti tc c a ra bng thanh ghi baud , bit U2X hoc bng XCK ph thuc vo ch iu khin c s dng Cc on code mu di y ch ra mt hm truyn USART c bn da trn s hi vng ca c bo trng thanh ghi d liu (UDRE). Khi s dng cc khung vi it hn 8 k t , cc bit c trng s cao nht c vit ln UDR c b qua . USART phi c khi to trc khi chc nng c s dng . V on m Assembly , d liu gi th c coi nh c lu vo trong thanh ghi R16

Chc nng n gin i b m pht tr nn trng bng vic kim tra c UDRE , trc khi ti n vi d liu mi c pht i . Nu cc ngt bo trng thanh ghi d liu c s dng , cc chng trnh con phc v ngt s vit d liu ln b m Vic gi cc khung vi 9 bit d liu Nu chui k t 9 bit c s dng (UCSZ = 7), bit th 9 phi c ghi ln bit TXB8 trong UCSRB trc khi byte thp ca chui c ghi ln UDR . on code mu di y ch ra mt chc nng chuyn pht ci m iu khin chui k t 9bit . V code Assembly , d liu c gi th c gi nh l c lu tr trong cc thanh ghi R17:R16

Bit th 9 c th c s dng cho vic hin th 1 khung a ch khi s dng ch giao tip nhiu vi x l hoc cho cc giao thc iu khin khc nh l qu trnh ng b ha . C bo v ngt ca b chuyn pht Cc b chuyn pht USART c 2 c hin th trng thi ca n : bo trng thanh ghi d liu USART (UDRE) v hon thnh qu trnh chuyn pht (TXC) . C hai c c th c s dng cho vic sinh ra cc ngt . C bo trng thanh ghi d liu (UDRE0 hin th khi m b m chuyn pht sn sng nhn d liu mi .Bit ny c ci t khi m b m pht trng , v b xa khi m b m chuyn pht bao gm d liu chuyn i ci m va b di chuyn vo trong thanh ghi Shift . tng thch vi cc thit b trong tng lai , lun vit bit ny l 0 khi vit thanhg hi UCSRA Khi c bo ngt trng thanh ghi d liu kch hot (UDRIE) trong UCSRB c ghi l 1 , ngt trng thanh ghi d liu USART s c thc thi ch cn UDRE c ci t( cung cp cc ngt chung c ci t ) UDRE b xa bng vic vit UDR. Khi ngt iu khin ch chuyn pht c s dng, chng trnh con phc v ngt bo trng thanh ghi d liu phi

c vit gi tr mi ln UDR xa UDRE hoc v hiu ha ngt bo trng thanh ghi d liu , ni cch khc 1 ngt mi s xut hin mi ln m cc ngt c kt thc Bit c bo hon thnh chuyn pht (TXC) c t l 1 khi m khung truyn trn vn trong thanh ghi chuyn pht Shift va c di chuyn ra ngoi v khng c ngt hin hnh no c a ra trong b m chuyn pht . bit C TXC th t ng c xa khi m ngt hon thnh chuyn pht c thc thi , hoc n c th b xa bng vic vit l 1 ln bit a ch ca n . C TXC th c ch trong cc giao din truyn thng bn song cng (ging nh chun RS485) , 1 ng dng chuyn pht phi c ng nhp vo ch nhn v gii phng bus truyn thng ngay lp tc sau khi hon thnh qu trnh chuyn pht . Khi bit kch hot ngt hon thnh chuyn pht (TXCIE) trong thanh ghi UCSRB c ci t , ngt hon thnh chuyn pht USART s c thc thi khi m c TXC tr thnh c ci t , (c cung cp khi m cc ngt chung kch hot ) Khi ngt hon thnh qu trnh chuyn pht c s dng , cc chng trnh con iu khin ngt khng phi xa c TXC , iu ny c thc hin mt cch t ng . Parity Generator (My pht chn l ) My pht chn l tnh ton bit chn l cho cc khung truyn d liu ni tip . Khi m bit chn l c kch hot (UPM1=1) , b logic iu khin chuyn pht chn cc bit chn l gia cc bit d liu cui v bit stop u tin ca cc khung truyn ci m c gi . S v hiu ha chuyn pht S v hiu ha ca qu trnh chuyn pht (ci t TXEN l 0 ) s khng c hiu lc cho n khi qu trnh chuyn pht ang chy v ang ch c hon thnh . v d : khi m thanh ghi shift chuyn pht v thanh ghi b m chuyn pht khng bao gm d liu c chuyn pht . Khi v hiu ha , b chuyn pht s khng ghi ln chn TxD S thu nhn d liu b thu USART B thu USART c kch hot bng cch vit ln bit kch hot b thu (RXEN) trong thanh ghi UCSRB l 1 . Khi b thu c kch hot , qu trnh iu khin chn thng thng ca chan RxD c ghi bi USART v a ra cc chc nng nh chn u vo ni tip ca b thu pht . Baud rate , ch iu khin v dng khung truyn phi c ci t mt ln trc khi bt c s thu nhn ni tip no c th thc hin . Nu ch ng b ha c s dng , xung nhp trn chn XCk s c s dng nh l xung chuyn pht . S thu nhn cc khung truyn vi 5 n 8 bit d liu B thu pht bt u qu trnh nhn d liu khi m n d thy 1 bit khi ng c hiu lc . Mi bit ci m theo sau bit khi ng s c ly mu ti baud rate hoc xung nhp XCK , v c chuyn vo trong thanh ghi di chuyn nhn cho n khi bit stop u tin ca khung c nhn . 1 bt stop th 2 s b b qua bi b thu nhn . Khi bit stop u tin c nhn v d : 1 khung ni tip hon chnh c a ra trong thanh ghi di chuyn nhn , thanh phn ca

thanh ghi shift s b di chuyn vo trong b m nhn . B m nhn c th c c sau bi vic c vng nh vo ra UDR on code mu di y ch ra nh l mt b thu nhn USART n gin chc nng c xy dng trn c s vic hi vng (Polling) ca c bo hon thnh chuyn pht (RXC) . Khi s dng cc khung truyn vi t hn 8 bt , cc bit c trng s cao nht ca d liu c c t UDR s c che ln 0 . USART c khi to trc khi chc nng c th c s dng

S thu nhn cc khung vi 9 bit d liu Nu chui k t 9-bit c s dng (UCSZ = 7) bit th 9 phi c c t bit RXB8 trong thanh ghi UCSRB trc khi vic c cc bit thp t UDR . Nguyn tc ny p dng ln cc c bo trng thi FE, DOR ,v UPE rt tt . c trng thi t UCSRA , sau d liu t UDR . Vic c vng a ch nh UDR s thay i trng thi ca b m nhn FIFO v tip theo lcc bit TXB8 , FE , DOR , UPE , tt c c lu tr trong FIFO s b thay i . on code mu di y s ch ra v d n gin v chc nng thu nhn ca USART ci m iu khin c hai chui k t 9 bit v cc bit trng thi .

Ngt v c bo hon thnh nhn B nhn USART c mt c ci m hin th trng thi nhn tn hiu C bo hon thnh vic nhn tn hiu ( RXC) hin th nu c d liu khng c c a ra trong b m nhn . C ny l 1 khi d liu khng c c c xut ra trong b m nhn , v 0 khi b m nhn trng (v d khng cha bt c d liu khng c c no ). Nu b thu nhn b v hiu ha (RXEN = 0 ) th b m thu nhn s b xa sch v tip theo bit RXC s tr thnh 0 Khi m bit kch hot ngt hon thnh nhn(RXCIE) trong thanh ghi UCSRB c ci t , ngt hon thnh nhn USART s c thc thi ch cn c RXC c ci t (c cung cp khi cc ngt chung c kch hot ) Khi ngt iu khin nhn d liu c s dng , chng trnh con hon thnh nhn phi c d liu n t UDR xa c RXC , ni cch khc 1 ngt mi s xut hin mi ln m chng trnh con phc v ngt hon thnh .

C bo li nhn tn hiu B nhn USART c 3 c bo li : li khung truyn (FE) , bo trn d liu (DOR) v bo li chn l (UPE) . Tt c c th c truy cp bng cach c thanh ghi UCSRA . Thng thng cc c bo l ci m chng c t trong b m nhn cng vi khung truyn cho cc trng thi li ca chng c hin th . D cho b m ca cc c bo li , UCSRA phi c c trc khi b m nhn (UDR), tip theo vic c vng a ch I/O UDR thay i b m c vng d liu . S tng ng khc cho cc c bo li l ci m chng khng th b thay i bng phn mm ang thc hin 1 qu trnh vit ln vng a ch ca c bo . Tuy nhin , tt c cc c phi c ci t l 0 khi m UCSRA c vit cho cc s tng thch ca pha sau ca cc s ci t USART trong tng lai . Khng c cc c bo li no c th sinh ra cc ngt C bo li khung truyn (FE) hin th trng thi ca bit STOP u tin ca khung truyn c th c k tip c lu tr trong b m nhn . C FE l 0 khi bit Stop khng c c ng (nh l 1 ) , v c bo FE s l 1 khi bit stop khng ng (0) . C ny c th c s dng cho vic d cc iu kin out-of-sync , d cc iu kin break , v cc giao thc iu khin . C FE th khng b nh hng bi vic ci t ca bit USBS trong thanh ghi UCSRC do b thu nhn b qua tt c , ngoi tr cc bit u tin v cc bit Stop . tng thch vi cc thit b trong tng lai , lun ci t bit ny l 0 khi c UCSRA C bo trn d liu (DOR) hin th vic mt d liu d cho b m d liu iu kin. Mt c bo trn d liu xut hin khi b m thu y(2 chui k t ) , n l 1 chui k t mi ang i trong thanh ghi Shift Receiver , v 1 bit start mi c tm thy . Nu c DOR c ci t c mt hoc nhiu khung truyn ni tip mt gia khung cui cng c c t UDR , v khung tip theo c t UDR . tng thch vi cc thit b trong tng lai , lun vit bit ny l 0 khi vit ln UCSRA . C bo DOR b xa khi khung nhn c di chuyn thnh cng khi thanh ghi Shift ln b m nhn . C bo li chn l (UPE) hin th ci m khung truyn tip theo trong b m nhn c mt li chn l khi nhn . Nu s kim tra khng c kch hot , bit UPE s lun c c l 0 . tng thch vi cc thit b tng lai , lun ci t bit ny l 0 khi vit ln UCSRA . bit thm chi tit xem Parity Bit Calculation trang 176 v Parity checker trang 184 . B kim tra li chn l B kim tra li chn l c hot ng khi bit ch chn l USART cao (UPM1) c ci t . Loi ca s kim tra chn l c tin hnh (l hoc chn) c la chn bng bit UPM0 . Khi kch hot , b kim tra bit chn l tnh ton chn l ca cc bit d liu trn cc khung truyn ang n v so snh kt qu vi bit chn l t khung truyn ni tip . Kt qu ca s kim tra c lu tr trong b m nhn cng vi d liu n v cc bit stop .C bo li chn l (UPE) sau c th c bng phn mm kim tra nu khung truyn c 1 li chn l . Bit UPE c ci t nu chui k t tip theo ci m c th c c t b m nhn c mt li chn l khi nhn v vic kim tra li chn l c kch hot ti im (UPM1 =1 ) . Bit ny th c hiu lc cho n khi b m nhn(UDR) c c .

V hiu ha b thu nhn Tri ngc vi b chuyn pht , vic v hiu ha ca b thu nhn s l tc thi . D liu thu nhn ang n s v vy m b mt . Khi v hiu ha (v d : it RXEN c t l0 ) b thu nhn s khng ghi ghi ln chc nng thng thng ca cng RxD na . B m nhn FIFO s b xa sch khi b thu nhn b v hiu ha . D liu cn li trong b m s b mt Xa b m thu nhn B m thu nhn FIFO s b xa khi m b thu nhn b v hiu ha , v d : b m s b lm trng ht d liu ca n . Cc d liu cha c c s b mt . Nu b m phi b xa trong sut qu trnh iu khin thng thng (normal ) , do v d ca mt li trng thi , c vng nh I/O UDR cho n khi c RXC b xa . on m mu di y ch ra cch xa b m nhn .

S khi phc xunh nhp d b Khi logic khi phc xung nhp ng b xung nhp bn trong vi cc khung truyn ni tip ang n. Hnh 83 minh ha qu trnh ly mu ca bit start ca mt khung truyn ang n . Tc ly mu l 16 ln baud rate vi ch normal , v 8 ln baud rate vi ch tc kp . Cc mi tn nm ngang minh ha qu trnh ng b ha lch ca qu trnh ly mu . Ch lch thi gian ly mu rng hn khi s dng ch tc kp (U2X = 1 ) ca qu trnh iu khin . Cc mu k hiu l 0 l cc mu thc hin khi m ng RxD b Idle (khng c hot ng truyn thng )

Khi khi logic khi phc xung nhp d thy 1 s chuyn tip t mc cao (idle ) sang mc thp (start) trn ng RxD, qu trnh d bit start k tip s c khi to . K hiu ln ly mu 1 l ln u tin mu -0 nh c ch ra trong hnh . Khi logic khi phc xung nhp sau s s dng cc mu 8 ,9 ,10 cho ch normal , v cc mu 4 ,5, 6 cho ch tc kp ( hin th vi s th t cc mu bn trong cc hp trn hnh v , quyt nh nu 1 bit start c hiu lc c nhn . Nu nhiu hn 2 hoc 3 mu c cc mc logic cao , bit start c gii phng nh l 1 nh nhiu v b thu nhn bt u tm 1 s chuyn tip t mc cao xung mc thp . Tuy nhin , nu 1 bit start c hiu lc c d thy , khi logic khi phc xung nhp c ng b ha v qu trnh khi phc d liu c th bt u . Qu trnh ng b ha c lp li cho mi bit start Khi phc d liu d b Khi xung nhp b thu c ng b ha vi bit start , s khi phc d liu c th bt u . B phn khi phc d liu c th s dng mt my pht trng thi ( state machine ) ci m c 16 trng thi cho mi bit trong ch bnh thng v 8 trng thi cho mi bit trong ch tc kp . Hnh 84 ch ra qu trnh ly mu ca cc bit d liu v cc bit chn l . Mi mu th a ra 1 s th t ci m bng trng thi ca b phn khi phc .

S quyt nh ca cc mc logic ca bit thu nhn c a ra bng vic thc hin 1 qu trnh b phiu a s ca gi tr logic ln 3 mu trong trung tm cu cc bit nhn . Cc mu trung tm c lm ni bt trong hnh v bng vic cho cc s th t ly mu vo trong cc hp. Qu trnh b phiu ly a s c thc hin nh sau : Nu 2 hoc tt c 3 mu c cc mc logic cao , cc bit nhn c ng k ln mt mc logic 1 . Nu 2 hoc tt c 3 mu c cc mc logic thp , cc bit nhn c ng k ln mt mc logic 0 . Qu trnh b phiu ly a s ny ng vai tr nh l 1 b lc thng thp cho cc tn hiu n trn chn RxD . Qu trnh khi phc sau c lp li cho n khi mt khung truyn hon chnh c nhn . Bao gm c bit stop u tin .Ch rng b nhn ch s dng bit stop u tin ca mt khung truyn , Hnh 85 ch ra qu trnh ly mu ca bit stop v s bt u sm nht c th ca bit start ca khung k tip .

Qu trnh b phiu a s cng c thc hin ln bit stop nh thc hin vi cc bit khc trong khung truyn . Nu bit stop c ng k li c gi tr logic 0 ,c bo li khung truyn s c ci t . Mt qu trnh chuyn dch t cao xung thp mi ang hin th bit start ca 1 khung truyn mi c th n sau khi bit cui cng c s dng cho qu trnh b phiu a s . i vi ch tc bnh thng , mu mc thp u tin c th c nh du im A trong hnh v . i vi ch tc kp , mc thp u tin phi c lm tr l B. (C) nh du 1 bit stop di . S d bit start sm nh hng n di hot ng ca b thu nhn. Di hot ng d b Di hot ng d b ca b thu nhn th ph thuc vo s khng khp gia tc bit nhn v baudrate pht ra bn trong .Nu b thu pht ang gi cc khung ti cc tc bit qu nhanh hoc qu chm , hoc baud rate c pht ra bn trong ca b thu nhn khng c mt s tng ng (xem bng 75) v tn s c bn , B thu nhn s khng th ng b ha cc khung vi bit start Cng thc di y c th c s dng tnh ton h s ca tc d liu ang n v tc b nhn bn trong :

S khuyn co i vi li tc baud rate cc i c a ra vi gi thit rng b thu v b pht c chia bng nhau tng cc i cc li C hai ngun c th gy ra li baudrate cc b thu nhn . Xung nhp h thng ca b thu nhn (XTAL) s lun c vi trng thi nh nht trn gii in p ngun cp v gii nhit cho php. Khi s dng mt b to dao ng thch anh pht ra xung nhp h thng, iu ny him khi c vn nhng mt b khuych i dao ng h thng c th ln hn 2% ph thuc vo sai s cho php ca b khuych i dao ng. Nguyn nhn th 2 cho li ny l c th iu khin hn. My pht dao ng khng th lun thc hin mt php chia chnh xc cho tn s h thng c c tc mong mun. Trong trng hp ny ,mt gi tr UBRR c a ra mt gi tr c th chp nhn , li thp c th c s dng nu c th Ch truyn thng a vi x l Vic ci t truyn thng a vi x l (MPCM) Trong thanh ghi UCSRA kch hot mt chc nng kch hot ca cc khung truyn n nhn bi b thu USART. Cc khung ny ci m khng bao gm thng tin a ch s c b qua v khng c t vo trong b m thu . Hiu qu ca vic ny lm gim s lng ca cc khung truyn n ci m phi c iu khin bi CPU , trong h thng vi nhiu MCU m giao tip thng qua cc bit ni tip ging nhau . B chuyn pht th khng b nh hng bi vic ci t MPCM , nhng phi c s dng khc nhau khi n l 1 phn ca h thng ang dng ch truyn thng a vi x l . Nu b thu nhn c ci t ln cc khung truyn nhn m bao gm 5 n 8 bit d liu , sau bit stop u tin hin th nu khung truyn bao gm d liu hoc thng tin a ch . Nu b thu nhn c ci t cho cc khung vi 9 bit d liu , sau bit th 9 (RXB8) c

s dng cho vic t a ch ring v cc khung d liu . Khi bit loi khung (bit stop u tin hoc bit d liu th 9 ) l 1 , khung truyn bao gm 1 a ch . Khi bit loi khung l 0 th khung l 1 khung d liu . Ch truyn thng a vi x l kch hot hng lot MCU slave ti d liu nhn t mt MCU master . iu ny c thc hin bi m dch u tin 1 khung truyn a ch tm ra ci m MCU c t a ch . Nu 1 MCU slave c bit va c t a ch , n s nhn khung d liu tip theo nh thng thng , trong khi cc MCU slave khc s b qua cc khung truyn nhn cho n khi khung truyn a ch khc c nhn S dng MPCM Mt MCU ng vai tr nh l 1 MCU master , n c th s dngdng khung chui k t 9 bit (UCSZ =7). Bit th 9 (TXB8) phi c ci t khi mt khung a ch (TXB8=1) hoc b xa khi 1 khung d liu (TXb=0) ang c chuyn pht . Cc MCU slave phi trong trng hp phi c ci t ln dng khung truyn chui k t 9 bit Quy trnh sau y nn c s dng chuyn i d liu tng ch truyn thng a vi x l ; - Tt c cc MCU slave u trong ch truyn thng a vi x l (MPCM trong thanh ghi UCSRA c ci t 0 - MCU master gi 1 khung a ch , v tt c cc slave nhn v c khung truyn ny . Trong cc MCU slave , c RXC trong thanh ghi UCSRA s c ci t nh thng thng . - Mi MCU slave c thanh ghi UDR v xc nh nu n va c la chn . V vy nu n xa bit MPCM trong thanh ghi UCSRA , ni cch khc , n i cho byte a ch k tip v gi vic ci t MPCM - Vic t a ch MCU s nhn tt c cc khung truyn d liu cho n khi 1 khung truyn a ch mi c nhn. Cc MCU slave khc , ci m vn c bit MPCM c ci t , s b qua cc khung truyn d liu . - Khi m cc khung truyn d liu c nhn bi cc MCU t a ch , cc MCU t a ch ci t bit MPCM v i mt khung truyn a ch mi t master . Qu trnh ny sau c lp li t bc 2 Vic s dng bt c cc dng khung truyn chui k t t 5 n 8 bit l c th , nhng khng thc t do cc b thu phi c thay i gia vic s dng cc dng khung truyn chui k t n v n+1 . iu ny lm cho qu trnh iu khin song cng kh khn hn do b thu nhn v chuyn pht s dng s ci t cc c khung truyn ging nhau . Nu cc khung truyn chui k t t 5 n 8 bit c s dng , b chuyn pht phi c ci t s dng 2 bit stop (USBS = 1) do bit stop u tin c s dng hin th cc dng khung truyn ging nhau Khng s dng lnh read-modify-write (SBI v CBI) ci t hoc xa bit MPCM . Bit MPCM chia s cc vng a ch I/O nh l c TXC v iu ny c th xy ra bin c b xa khi s dng lnh CBI v SBI

S miu t thanh ghi USART Thanh ghi d liu vo ra USARTn

Cc thanh ghi b m d liu pht USARTn v cc thanh ghi b m d liu thu nhn chia s cc a ch vo ra ging nhau c tham chiu nh l thanh ghi b m d liu USART hoc UDRn . Thanh ghi b m d liu chuyn pht (TXBn) s nh hng n cho d liu c vit ln vng nh thanh ghi UDRn . Vic c vng nh thanh ghi UDRn s hon tr cc thnh phn ca thanh ghi b m d liu thu nhn V cc chui k t 5 , 6 ,7 bit hoc nhiu bit khng c s dng s b b qua bi b chuyn pht v c t l 0 bng b thu nhn . B m pht c th ch c vit khi c bo UDREn trong thanh ghi UCSRAn c t . D liu c vit ln thanh ghi UDRn khi m c bo UDREn khng c ci t , s b b qua bi b chuyn pht USARTn . Khi d liu c vit vit ln b m pht , v b chuyn pht c kch hot , b chuyn pht s ti d liu vo troang thanh ghi Shift ca b chuyn pht khi m thanh ghi Shift cn trng . Sau d liu s c pht ni tip trn chn TxDn B m thu nhn th bao gm 1 FIFO 2 mc . FIFO s thay i trng thi ca n ni m b m thu nhn c truy cp n . D cho qu trnh x l ca b m ny , khng s dng c thay cho cc lnh vit (SBI v CBI ) trong vng nh ny . Phi cn thn khi s dng cc lnh kim tra bit (SBIC v SBIS) , do cc bit ny cng s thay i trng thi ca FIFO Thanh ghi A trng thi v iu khin USART UCSRnA

Bit 7 RCXn : hon thnh thu nhn tn hiu Bit c ny c ci t khi c cc d liu khng c c trong b m nhn v b xa khi b m nhn trng (v d khng bao gm bt c bit cha c c no ) . Nu b thu nhn b v hiu ha , b m thu s b xa sch v tip theo bit RXCn sec tr thnh 0. C bo RXCn c th c s dng pht ra 1 ngt bo hon thnh nhn (xem miu t ca bit RXCIEn ) Bit 6 TXCn : hon thnh chuyn d liu USART Bit c ny c ci t m bo rng khung trong thanh ghi Shift chuyn pht va c nn li v khng c d liu mi hin hnh no c a ra trong b m chuyn pht (UDRn) . Bt c bo TXCn th t ng c xa khi m ngt bo chuyn pht hon thnh c thc thi hoc n c th b xa bng vic vit bit 1 mc logic mt ln vng bit nh ca n . C bo TXCn c th pht ra 1 ngt bo hon thnh chuyn pht (xem miu t ca bit TXCIEn )

Bit 5 UDREn : bo trng thanh ghi d liu USART C bo UDREn hin th nu b m pht (UDRn) sn sang nhn d liu mi . Nu UDREn l mt , b m l trng , v v vy sn sng c ghi . C bo UDREn c th sinh ra mt ngt bo trng thanh ghi d liu(xem miu t ca bit UDRIEn ) UDREn c ci t sau khi 1 reset hin th rang b chuyn pht sn sng Bit 4 Fen : li khung truyn Bit ny c ci t nu chui k t tip theo trong b m nhn c li khung truyn khi c nhn tn hiu v d nh khi bit stop u tin ca chui k t tip theo trong b m nhn l 0 . Bit ny th c hiu lc cho n khi b m nhn c c . Bit Fen l 0 khi bit stop ca d liu nhn l 1 . Lun ci t bit ny l 0 khi vit UCSRnA Bit 3 DORn : bo trn d liu Bit 4 Fen : li khung truyn Bit ny c ci t nu chui k t tip theo trong b m nhn c li khung truyn khi c nhn tn hiu v d nh khi bit stop u tin ca chui k t tip theo trong b m nhn l 0 . Bit ny th c hiu lc cho n khi b m nhn c c . Bit Fen l 0 khi bit stop ca d liu nhn l 1 . Lun ci t bit ny l 0 khi vit UCSRnA Bit 3 DORn : bo trn d liu Bit ny c ci t nu mt iu kin trn d liu c tm thy . Mt bo trn d liu xut hin khi b m thu b y (2 chui k t) , n l 1 chui k t mi i trong thanh ghi Shift thu nhn , v mt bit khi ng mi c tm thy . Bit ny c hiu lc cho n khi b m nhn (UDRn) c c . Lun ci t bit ny l 0 khi vit ln UCSRnA Bit 2 UPEn : li chn l Bit ny c ci t nu chui k t tip theo trong b m nhn c li chn l khi nhn v s kim tra chn l c kch hot ti im ny (UPMn1=1) . Bit ny c hiu lc cho n khi b m nhn (UDRn) c c . Lun ci bit ny l 0 khi vit ln UCSRnA Bit 1 U2Xn: tc truyn d liu USART kp Bit ny ch c hiu lc trong ch iu khin d b . Vit bit ny l 0 khi s dng ch ng b . Vit bit ny l 1 s gim h s chia ca b chia baud rate t 16 xung 8 c tc dng nhn i tc truyn d liu cho ch truyn thng d b Bit 0 MPCMn : ch truyn thng a vi x l Bit ny kch hot ch truyn thng a vi x l . Khi bit MPCMn c vit l 1 , tt c cc khung truyn n c nhn bng b thu nhn USART ci m khng bao gm thng tin a ch s b b qua . B chuyn pht th khng b nh hng bi vic ci t MPCMn . bit thm chi tit xem (trang 187) Thanh ghi B trng thi v iu khin USARTn USARTnB

Bit 7 RXCIEn : kch hot ngt hon thnh RX

Vic vit bit ny l 1 kch hot ngt trn c RXC . 1 ngt hon thnh nhn USART s ch c sinh ra nu bit RXCIE c vit l 1 , cc c bo ngt chung trong thanh ghi SREG c vit l 1 v bit RXC trong thanh ghi UCSRnA c ci t . Bit 6 TXCIE : kch hot ngt hon thnh TX Vic vit bit ny kch hot ngt trn c TXCn . 1 ngt hon thnh qu trnh chuyn USART s ch c sinh ra nu bit TXCIE c vit l 1 , cc c bo ngt chung trong thanh ghi SREG th c vit ln 1 v bit TXCn trong thanh ghi UCSRnA c ci t . Bit 5 UDRIEn : kch hot ngt trng thanh ghi d liu USART Vic vit bit ny ln 1 kch hot cc ngt trn c UDREn . 1 ngt trng thanh ghi d liu s ch c sinh ra nu bit UDRIEn c vit ln 1 , c ngt chung trong thanh ghi SREG c vit ln 1 v bit UDREn trong UCSRnA c ci t Bit 4 RXENn : kch hot b thu tn hiu Vic vit cc bit ny ln 1 kch hot b thu USARTn . B thu s ghi ln qu trnh iu khin cng thng thng cho chn RxDn khi c kch hot . Vic v hiu ha b thu s xa sch b m thu nhn khng c hiu lc Fen , v cc c DORn v UPEn Bit 3 TXENn : kch hot b chuyn pht Vic vit bit ny l 1 kch hot b chuyn pht USARTn . B chuyn pht s ghi ln cng iu khin thng thng cho chn TxDn khi kch hot . S v hiu ha ca b chuyn pht (vit TXENn l 0 ) s khng tr nn c hiu lc cho n khi ang c tin hnh v qu trnh truyn d liu c hon thnh . v d nh Khi thanh ghi Shift chuyn pht thanh ghi b m pht khng cha d liu c chuyn . Khi v hiu ha , b chuyn pht s ghi lu hn ln cng TxDn Bit 2 UCSZn2 : kch c chui k t Cc bit UCSZn2 c kt hp vi bit UCSZn1:0 trong thanh ghi UCSRnC ci t s lng bit d liu (kch c chui k t ) trong mt khung truyn m b thu nhn v b pht s dng Bit 1 RXB8n : bit 8 d liu n RXB8n l bit d liu th 9 ca chui k t n khi m hot ng vi cc khung ni tip vi 9 bit d liu . Phi c c trc khi tin hnh vic c cc bit thp hn t UDRn Bit 0 TXB8n : bit 8 d liu chuyn pht TXB8n l bit d liu th 9 trong chui k t c chuyn pht khi m hot ng vi cc khung truyn ni tip vi 9 bit d liu . Phi c ghi trc khi vic ghi cc bit thp ln UDRn c tin hnh Thanh ghi C trng thi v iu khin USARTn UCSRnC

Ch rng thanh ghi ny khng kh dng trong ch tng thch vi Atmega 103 Bit 7 bit d tr Bit ny th c d tr cho vic s dng trong tng lai . tng thch vi cc thit b trong tng lai , cc bit ny phi c ghi l 0 khi m UCSRnC c ghi Bit 6 UMSELn : la chn ch USART

Bit ny la chn gia ch iu khin ng b v d b

Bit 5:4 UPMn1:0 : ch chn l Cc bit ny kch hot v ci t loi ca s pht v kim tra bit chn l . Nu c kch hot , b chuyn pht s t ng sinh ra v gi i cc bit d liu chuyn pht chn l trong mi khung truyn . B thu nhn s sinh ra 1 gi tr chn l cho d liu n v so snh n vi vic ci t UPMn0 . Nu s khng tng xng c tm ra , c bo UPEn s c ci t

Bit 3 USBSn : la chn bit stop Bit ny la chn s lng bit stop c chn vo bi b chuyn pht . B thu nhn b qua vic ci t ny

Bit 2:1 UCSZn1:0 : kch c chui k t Cc bit UCSZn1:0 c kt hp vi UCSZn2 trong thanh ghi UCSRnB ci t s lng ca cc bit d liu ( kch c chui k t) trong mt khung truyn m b thu nhn v b chuyn pht s dng

Bit 0 UCPOLn : cc xung nhp Bit ny c ch s dng cho ch ng b . Vit bit ny l 0 khi ch d b c s dng . bit UCPOLn ci t quan h gia s thay th u ra d liu v ly mu u vo d liu , v xung nhp ng b (XCKn)

Cc thanh ghi Baud Rate USART UBRRnL v UBRRnH

UBRRnH th khng kh dng trong ch tng thch vi Atmega 103 Bit 15:12 Cc bit d tr Cc bit ny c d tr cho vic s dng trong tng lai . tng thch vi cc thit b trong tng lai , cc bit ny phi c vit l 0 khi m UBRRnH c ghi Bit 11:0 UBRRn11:0 : thanh ghi baud rate USARTn y l 1 12 thanh ghi bao gm baud rate USARTn . UBRRnH bao gm 4 bit c trng s cao nht , v UBRRnL bao gm 8 bit c trng s thp nht ca baud rate USARTn . qu trnh chuyn d liu ang tin hnh bi b chuyn pht v b thu s b lm hng nu baud rate b thay i . Vic vit UBRRnL s khi ng mt cp nht trung gian ca b m gp trc Baudrate V d v vic ci t Baudrate

XVIII. Giao din hai dy tun t _ Two wire Serial Inteface

c im - n gin nhng mnh m v giao din truyn thng linh hot , ch cn thit 2 ng bus - H tr c ch iu khin Master v Slave - Thit b c th hot ng nh mt b chuyn pht hoc mt b thu - Khng gian a ch 7-bit cho php nng ln 128 a ch Slave khc nhau - H tr phn nh ch Master slave - Nng ln tc chuyn d liu l 400 kHz - Cc b iu khin u vo gii hn tc quay - Mch loi b nhiu loi b nh nhn trn cc ng bus - y cc a ch slave lp trnh c vi s h tr gi chung - S nhn ra a ch gy ra nh thc khi AVR trong cc ch sleepmode S nh ngha bus giao din tun t hai dy Giao din tun t hai dy (TWI) l b cng c l tng cho cc ng dng vi iu khin thng thng . Giao thc TWI cho php ngi thit k h thng lin kt trn 128 thit b khc nhau s dng ch 2 ng bus 2- hng , 1 cho xung nhp (SCL) v 1 cho d liu (SDA) . Ch cn phn cng bn ngoi iu khin bus nh l 1 b in tr pull-up n cho mi dy trong ng bus TWI . Tt c cc thit b c kt ni ln bus c a ch ring , v dn ng cho b nh phn gii bn trong giao thc TWI

Thut ng ca TWI Cc nh ngha sau y c bt gp thng xuyn trong phn ny .

Lin kt in Nh c miu t trong hnh 86 , c hai ng bus u c kt ni n chn in p dng ca ngun cp thng qua cc in tr Pull-up . Cc b iu khin bus ca tt c cc thit b ph hp vi TWI l open drain v open collector . iu ny ci t 1 chc nng wried AND ci m cn thit n hot ng ca giao din . Mt mc logic thp trn 1 ng bus TWI c sinh ra khi 1 hoc nhiu hn cc u ra thit b TWI l 0 . Mt mc cao l u ra khi tt c cc thit b TWI 3 trng thi ca cc u ra ca chng , s cho php ca cc in tr pull-up ko ln mc cao . Ch rng tt c cc thit b AVR c kt ni n cc bus TWI phi c cp in theo th t cho php bt c s iu khin cc bus S lng ca cc thit b ci m c th kt ni ti bus ch b gii hn bng bus in dung gii hn ca 400pF v khng gian a ch slave 7-bit . Mt bng thng s chi tit ca cc c trng ca TWI c a trong phn Two-wire Serial Interface Characteristics trn trang 322 . Hai s ci t khc nhau ca cc c tnh c a ra , 1 thng tin thch hp cho cc tc bus di 100 kHz , v 1 gi tr cho tc bus trn 400kHz Chuyn d liu vo dng khng chuyn Qu trnh chuyn cc bt Mi bt d liu c chuyn trn bus TWI c km theo mt xung trn ng truyn xung nhp. Cp ca ng d liu phi n nh khi n xung nhp mc cao. Ch ngoi tr nguyn tc ny cho vic pht ra cc iu kin khi ng v dng. Hnh 87 Cc iu kin khi ng v dng Master khi to v kt thc mt qu trnh chuyn d liu. Qu trnh chuyn d liu c khi to khi Master a ra mt iu kin bt u trn bus, v n b kt thc khi master a ra mt iu kin stop. Gia mt iu kin start v stop, bus ang c xt n bn, v khng c Master no khc ang c gng iu khin bus d liu. Mt trng hp c bit xut hin khi mt iu kin start mi c a ra gia mt iu kin start v stop c. iu ny c tham chiu nh l mt iu kin start lp li ( REPEATED START ) v c s dng khi Master c yu cu khi to mt qu trnh chuyn pht mi m thiu i qu trnh iu khin relinquishing ca bus. Sauk hi mt ( REPEATED START ), bus c xt n bn cho n khi c iu kin stop tip theo. y l iu kin ring x l bit start, v v vy bit start c s dng miu t c hai trng thi START v ( REPEATED START) cho cc phn

cn li trong ti liu ny, tr khi c ch khc. Nh gin bin di, cc iu kin start v stop c k hiu bng cch thay i mc ca dng SDA, khi m dng SCL mc cao. Hnh 88 Dng ng gi a ch Tt c cc gi a ch c truyn trn bus TWI l 9 bit di, bao gm 7 bit a ch, mt bit iu khin c ghi, v mt bit nhn bit. Nu bit c ghi c ci t, mt qu trnh c c tin hnh, ni cch khc mt qu trnh vit nn c tin hnh. Khi mt slaver nhn ra rng n ang c nh a ch. N nn c nhn bit rng vic ko SDA mc thp trong bit th 9 SCL ( ACK). Nu nh slaver c nh a ch ang bn hoc mt vi l do khc c th khng phc vu truy vn ca Master. Dng SDA nn c chuyn n mc cao trong chu k xung nhp ACK. Master sau c th chuyn mt iu kin stop, mt ( REPEATED START) khi to mt qu trnh chuyn pht mi. Mt gi a ch th bao gm mt a ch slaver v mt bit c hoc ghi c gi l SLA+R v SLA+W mt cch tng ng. MSB ca byte a ch c chuyn u tin. a ch salver u tin c th c t mt cch t do bi ngi thit k nhng a ch 0000000 l d tr cho cc php gi chung. Khi mt php gi chung c a ra, tt c cc slaver nn p ng bng cch ko dng SDA trong chu k ACK. Mt s gi chung c s dng khi m mt master yu cu chuyn mt tin nhn ging nhau n cc slaver ni tip trong h thng. Khi gi a ch chung c theo bi mt bit ghi c chuyn trn bus truyn, tt c cc slaver ci t trn s gi chung s ko dng SDA xung mc thp trong chu k hi. Cc gi d liu tip theo ca s gi chung c nhn bi tt c cc slaver m hiu bit c cc tn hiu . Ch rng qu trnh cc lnh gi a ch chung c km theo bi mt bit c th khng c ngha, iu ny s gy ra h hng nu cc slaver ni tip c bt u truyn cc d liu khc nhau. Tt c cc a ch ca dng 1111 xxx nn c d tr cho cc tnh nng trong tng lai. Hnh 89 Dng gi d kiu Tt c cc gi d liu c truyn trn bus TWI c di 9 bit bao gm 1 byte v mt bit nhn bit. Trong sut mt qu trnh chuyn d liu, master sinh ra mt xung nhp v cc iu kin start stop, trong khi nhn mt p ng cho qu trnh nhn bit tn hiu n. Mt tn hiu nhn bit ( ACK) c nhn bit bng cch ko xung tn hiu trn dng SDA mc thp trong sut chu k SCL th 9. Nu nh b thu nhn chuyn dng SDA ln mc cao, mt NACK c nhn ra. Khi b nhn nhn c bus cui cung, hoc mt vi l do khng th nhn thm bt c bus no na, n nn dng byet cui cng. Bng cch chuyn NACK sau byet cui cng. MSB ca byet d liu th c chuyn u tin. Hnh 90 Vic ni cc a ch v ng gi d liu trong mt qu trnh chuyn pht. Mt qu trnh chuyn pht c bn bao gm mt iu kin start, mt SLA+R/W, mt hoc nhiu gi d liu v mt iu kin stop. Mt tin nhn trng, bao gm mt iu kin start km theo bi mt iu kin stop mt cch ng thi. Ch rng Wired-ANDing ca dng

SCR c th c s dng ci t handshaking gia master v slaver. Slaver c th m rng chu k dng thp SCL bng cch ko dong SCL mc thp. iu ny th c ch nu tc xung nhp ci t bi Master l qu nhanh cho slaver, hon slaver cn thm thi gian cho tin trnh gia cc qu trnh truyn d liu. Vic m rng slaver trong chu k SCL thp s khng nh hng n SCL cao, ci m xc nh bi master. Nh mt ni tip, slaver c th gim tc chuyn d liu TWI bng prolonging chu k SCL. Hnh 91 ch ra mt qu trnh chuyn pht thng thng. cc byet d liu ni tip c th c truyn gia SLA+R/W v iu kin stop, ph thuc vo giao thc phn mm c ci t bi phn mm ng dng. Hnh 91 Cc h thng bus nhiu master. Giao thc TWI cho php bus h thng vi nhiu master ni tip cc trng hp c bit l c th xy ra m bo rng qu trnh chuyn pht c thc thi nh thng thng, nu 2 hoc nhiu master khi to mt qu trnh truyn pht ti cng mt thi im. 2 vn ny sinh trong cc h thng nhiu master: - Mt thut ton phi c ci t ch cho php mt trong s cc master hon thnh qu trnh chuyn pht. Tt c cc master khc ang truyn d liu, khi chng pht hin ra rng d liu ca chng b mt trong cc qu trnh c la chn. cc qu trnh la chn ny c gi l arbitration. Khi mt master ang truyn d liu pht hin ra rng n b mt qu trnh arbitration, n s ngay lp tc chuyn mch sang ch slaver kim tra qu trnh nh a ch ca n bi cc master c u th hn. Chnh xc l, cc master va khi ng qu trnh truyn pht ti cng mt thi im nn khng th d thy cc slaver ( v d: d liu ang c chuyn trn bus khng phi b gin on). - Cc master ring bit c th s dng cc tn s SCL ring bit. Mt s c chia ra ng b ha cc xung ni tip t tt c cc master, bt u mt qu trnh truyn pht trong mt lockstep fashion. iu ny s khi phc mt qu trnh arbitrabion. Wired-ANDing ca cc ng bus c s dng khc phc cc vn ny. Cc xung nhp ni tip t tt c cc master s c Wired-ANDing, yielding mt kt ni xung nhp vi mt chu k cao bng mt trong s cc master vi chu k cao ngn nht. Chu k thp ca xung nhp kt ni th bng vi chu k thp ca master vi chu k thp di nht. Ch rng tt c cc master lng nghe dng lnh SCL vic bt u mt cch hiu qu m cc chu k time-out thp v cao SCL khi cc dng kt ni SCL mc cao hoc thp, mt cch tng ng. Hnh 92 Arbitration c mang ra ngoi bi tt c cc master mt cch lin tc quan st dng SDA sau khi xut u ra d liu. Nu gi tr c c t dng SDA th khng tng ng vi gi tr m master c u ra, n va b mt Arbitration. Ch rng mt master ch c th b mt Arbitration khi cc u ra ca n gi tr SDA cao trong khi cc u ra ca cc master khc gi tr thp vic mt d liu ca master nn chuyn sang ch slaver ngay lp tc, vic kim tra nu n ang c nh a ch bi master c quyn u tin cao hn. Dng SDA nn c chuyn ln cao nhng cc master b mt

d liu th c cho php pht ra mt tn hiu xung nhp cho n khi kt thc d liu hin hnh hoc gi a ch hin hnh. Arbitration s tip tc cho n khi ch cn li mt master, iu ny c th to ra nhiu bit hn. Nu cc master ni tip ang c gng nh a ch slaver ging nhau, Arbitration s tip tc in vo trong gi d liu. Hnh 93 Ch rng Arbitration th khng c cho php gia. - Mt iu kin REPEATED START . - Mt iu kin stop v mt bit d liu - REPEATED START v iu kin stop y l s tng ng ca phn mm ngi dng m bo rng illegal Arbitration khng bao gi xut hin. iu ny m bo rng trong mt h thng nhiu master, tt c cc s chuyn pht d liu phi s dng cc thnh phn ca SLA+R/W v cc gi d liu. trong cc dng t khc: tt c cc qu chuyn pht phi bao gm cc s ging nhau ca cc gi d liu, ni cch khc kt qu ca Arbitration l khng xc nh. Tng quan ca module TWI Module TWI c bao gm rt nhiu modile bn trong nh c ch ra trong hnh 94. Tt c cc thanh ghi c v bng mt nt mnh th c truy nhp thng qua bus d liu AVR. Hinh 94 Cc chn Scl v SDA Cc chn giao din AVR TWI vi cc chn ngh h thng MCU u ra ca b iu khin bao gm mt b gii hn slew-rate m ph hp vi cc c im k thut ca TWI. Cc cng u ra bao gm mt b phn loi tr sung g b cc tn hiu sung ngn hn 50 ns. Ch rng cc xung pull-p bn trong AVR c th c kch hot bng vic ci t cc bt cng PORT tng ng ln cc chn SCL v SDA nh c din t trong phn cng I/O. Cc xung pull-p bn trong c th trong mt vi h thng trit tiu l cn thit cho cc thit b bn ngoi. B phn my pht bitrate B phn ny iu khin chu k ca SCL khi hot ng trong ch Master . Chu k SCL c iu khin bng vic ci t trong thanh ghi bit Rate TWI (TWBR) v cc bit ca b m gp trc trong thanh ghi trng thi TWI (TWSR) . Slave hot ng khng ph thuc vo bit Rate hoc vic ci t b m gp trc , nhng tn s xung nhp trong ch slave phi c di 16 ln cao hn tn s SCL . Ch rng cc slave c th m rng chu k thp SCL , v vy vic lm gi tr trung bnh chu k xung nhp bus TWI . Tn s SCL c pht ra theo cng thc di y : Cng thc - TWBR = gi tr ca thanh ghi Bit Rate TWI - TWPS = gi tr ca cc bit ca b m gp trc trong thanh ghi trng thi TWI

Ch rng : gi tr i tr Pull-up nn c la chn theo tn s xung nhp ca v dung lng ti trn bus . xem bng 133 trn trang 322 cho gi tr ca in tr pull Thnh phn giao din bus Thnh phn ny bao gm cc thanh ghi shift a ch v d liu (TWDR,mt b iu khin STAR STOP v phn cng d ARBITRATION . TWDR bao gm cc bai a ch v cc bai d liu c chuyn pht hoc cc bai a ch hoc cc bai d liu c nhn thm vo o 8 bit TWDR , b phn giao din bus cng bao gm mt thanh ghi cha bit NACK truyn hoc nhn d liu . thanh ghi NACK ny th khng th truy nhp trc tip bng cc phn mm ng dng . Tuy nhin , khi ang nhn n c th c ci t hoc b xa bng vic iu khin thanh ghi iu khin TWI . Khi trong ch chuyn pht , gi tr ca bit (N)ACK nhn c th xc nh bng gi tr trong TWSR B iu khin START/STOP th phi chu trch nhim cho qu trnh pht v qu trnh d ca cc iu kin START , v REPEATED START , v STOP . B iu khin START/STOP th c th d cc iu kin START v STOP d khi MCU ca AVR ang trong mt ch ng no , vic kch hot MCU nh thc nu c nh a ch bi Master Nu TWI va c khi to 1 qu trnh chuyn pht nh l master , phn cng d tm kim nh tip tc quan st qu trnh truyn d liu ang c gng xc nh nu s kim nh ca n ang tin hnh . Nu TWI va mt mt s kim nh , b phn iu khin th c truyn d liu . Mt hnh ng ng sau c th hnh ng v mt code trng thi tng ng c th c snh ra . B phn ghp a ch B phn ghp a ch kim tra nu nh cc byte a ch nhn tng ng vi a ch 7 bit trong thanh ghi a ch TWI (TWAR) Nu nh bit kch hot s nhn din lnh gi chung TWI (TWGCE) trong TWAR c vit l 1 , tt c cc bit a ch n cng s c so snh li vi a ch gi chung . Trn mt ghp a ch , b phn iu khin c th c thng bo, vic cho php cc hnh ng ng c xy ra . TWI c th hoc khng th nhn ra a ch ca n ph thuc vo vic ci t trong TWCR . B phn ghp a ch c th so snh a ch khi MCU ca AVR trong ch ng , vic kch hot MCU nh thc nu c nh a ch bi mt Master . Nu cc ngt khc (v d INT0) xut hin trong sut qu trnh ghp a ch Power-down TWI v nh thc CPU , TWI b qua qu trnh iu khin v tr v trng thi idle ca n . Nu iu ny gy ra bt c vn no, m bo rng ghp a ch TWI th ch c kch hot ngt khi ang truy nhp vo ch Power-down B phn iu khin B phn iu khin gim st bus TWI v sinh ra nhng p ng tng ng ci t trong thanh ghi iu khin TWI (TWCR) . Khi mt s kin ang cn thit phi ch n ca cc ng dng xut hin trong bus TWI , c ngt TWI (TWINT) c xc nhn . Trong chu k xung nhp tip theo , thanh ghi trng thi TWI (TWSR) c cp nht vi mt m trng thi ring bit ca s kin . TWSR ch bao gm cc thng tin trng thi xc ng khi cc c ngt TWI c xc nhn . Ti tt c cc thi im khc TWSR bao gm 1 m trng thi c bit

ang hin th rng khng c thng tin trng thi xc ng l kh dng . Ch cn TWINT c ci t , ng SCL c gi mc thp . iu ny cho php phn mm ng dng hon thnh nhim v ca n trc khi cho php qu trnh truyn TWI tip tc C TWINT c ci t trong cc trng hp di y - Sau khi TWI va c chuyn pht 1 iu kin START/REPEATED START - Sau khi TWI va c chuyn SLA+R/W - Sau khi TWI va c chuyn 1 byte a ch - Sau khi TWI va mt qu trnh kim nh - Sau khi TWI va c nh a ch bng cc a ch Slave ring hoc gi a ch chung - Sau khi TWI va nhn 1 byte d liu - Sau khi iu kin STOP hoc REPEATED START va c nhn trong khi vn nh a ch nh l mt slave - Khi mt li bus va c xut hin d cho 1 iu kin START v STOP khng hp l S miu t thanh ghi TWI Thanh ghi Bit Rate TWI TWBR

Bit 7..0 thanh ghi Bit Rate TWI TWBR la chn t l chia cho my pht tc bit Rate . My pht Bit Rate th mt b chia tn s ci m sinh ra xung nhp SCL trong cc ch Master . Xem Bit Rate Generator Unit trn trang 204 v vic tnh ton bit Rate Thanh ghi iu khin TWI TWCR

TWCR th c s dng iu khin hot ng ca TWI .N c s dng kch hot TWI , khi to mt s truy nhp master bng vic t mt iu kin START ln bus , sinh ra 1 b thu nhn bit c sinh ra 1 iu kin STOP , v iu khin vic dng ca bus trong khi d liu c vit ln bus c ghi ln thanh ghi TWDR . N cng hin th 1 s xung t nu d liu c c gng ghi ln TWDR trong khi thanh ghi khng th truy nhp . Bit 7 TWINT : c ngt TWI Bit ny c ci t bng phn cng khi TWI va hon thnh cng vic hin hnh ca n v i phn mm ng dng p ng . Nu bit I trong SREG v TWIE trong TWCR c ci t , MCU s nhy ti vec t ngt TWI . Trong khi c TWINT c ci t th chu k SCL mc thp b ko di C TWINT phi b xa bng phn mm bng vic vit mc logic 1 ln n . Ch rng c ny khng t ng b xa bng phn cng khi ang thc thi chng trnh con phc v

ngt . Cng ch rng vic xa c ny bt u hot ng ca TWI l, v vy tt c cc s truy nhp ti thanh ghi a ch TWI (TWAR), v thanh ghi trng thi TWI (TWSR), v thanh ghi d liu TWI (TWDR) phi c hon thnh trc khi xa c ny . Bit 6 TWEA : bit nhn bit kch hot TWI TWEA iu khin s sinh ra ca xung nhn bit . Nu bit TWEA c vit l 1 , xung ACK c sinh ra trn bus TWI nu cc iu kin sau y c p ng : - a ch slave ca thit b va c nhn n - mt lnh gi chung va c nhn , trong khi bit TWGCE trong TWAR c ci t - mt byte a ch va c nhn trong b thu nhn Master v ch thu nhn slave bng vic vit TWEA l 0 , thit b c th ngt kt ni o khi bus TWI mt cch tm thi . S nhn din a ch sau c th khi phc li bng vic vit bit TWEA l 1 mt ln na Bit 5 TWSTA : bit iu kin khi ng TWI ng dng vit bit TWSTA l 1 khi m n mun tr thnh mt master trn bus TWI . Phn cng TWI kim tra nu bus l kh dng , v sinh ra mt iu kin START trn bus nu nh n t do . Tuy nhin , nu bus khng t do th TWI phi i cho n khi iu kin STOP c d thy , v sau sinh ra 1 iu kin START mi khng ngh v trng thi ca bus Master. TWSTA phi c xa bng phn mm khi m iu kin START va c truyn Bit 4 TWSTO : bit iu kin STOP TWI Vic vit bit TWSTO ln 1 trong ch Master s sinh ra 1 iu kin STOP trn bus TWI . Khi iu kin STOP c thc thi trn bus , bit TWSTO b xa 1 cch t ng . Trong ch Slave , vic ci t bit TWSTO c th c s dng khi phc t mt iu kin li . iu ny s khng sinh ra mt iu kin STOP , nhng TWI tr li nh l mt ch slave cha c nh a ch (a well-defined unaddressed )v gii phng ng SCL v SDA ln trng thi tr khng cao Bit 3 TWWC c bo vit xung t vit TWI TWWC c ny c ci t khi ang c gng vit ln thanh ghi d liu TWI TWDR khi m TWINT mc thp . C ny b xa bng vic vit ln thanh ghi TWDR khi m TWINT mc cao Bit 2 TWEN : bit kch hot TWI TWEN kch hot hot ng TWI v kch hot giao din TWI . Khi TWEN c vit l ln 1 , TWI iu khin qua cc chn I/O c kt ni n cc chn SCL v SDA , vic kch hot b gii hn slew-rate v b lc nhiu . Nu bit ny c vit l 0 , TWI b tt v tt c cc qu trnh chuyn TWI u kt thc bt chp bt c hot ng iu khin no ang tin hnh Bit 1 Res : bit d tr Bit ny l mt bit d tr v s lun c c l 0 Bit 0 TWIE : kch hot ngt TWI Khi bit ny c vit l 1 , v bit I trong thanh ghi SREG c ci t , yu cu ngt TWI s c kch hot ch khi m c TWINT mc cao Thanh ghi trng thi TWI TWSR

Bit 7..3 TWS : trng thi TWI y l 5 bit phn nh trng thi ca logic TWI v bus hai dy tun t . Cc m trng thi khc nhau c miu t sau trong phn ny . Ch rng gi tr c t TWSR cha c hai gi tr trng thi 5bit v gi tr b m gp trc 2bit .Ngi thit k ng dng nn che cc bit b m gp trc ln 0 khi ang kim tra cc bit trng thi . iu ny to ra vic kim tra trng thi c lp vi vic ci t b m gp trc . iu ny ging nh c s dng trong datasheet ny , tr phi c ch khc . Bit 2 Res : bit d tr Bit ny l bit d tr v lun c c l 0 Bit 1..0 TWPS : cc bit m gp trc TWI Cc bit ny c th c c v vit , v iu khin m gp trc bit rate

tnh ton cc bit rate , xem b phn pht Bit Rate trn trang 204 . Gi tr ca TWPS1 ..0 c s dng trong cng thc Thanh ghi d liu TWI TWDR

Trong ch chuyn pht , TWDR cha byte k tip c truyn pht . Trong ch nhn , TWDR bao gm byte cui cng c nhn . N khng th c vit trong khi TWI khng trong qu trnh ang di chuyn 1 byte . iu ny xut hin khi m c bo ngt TWI (TWINT)c ci t bng phn cng .Ch rng thanh ghi d liu khng th c khi to bng ngi s dng trc khi ngt u tin xut hin . D liu trong TWDR cn li n nh ch cn TWINT c ci t . Trong khi d liu c di chuyn ra ngoi , d liu trn bus c di chuyn vo trong mt cch ng thi . TWDR lun cha byte cui cng a ra trn bus, ngoi tr sau khi c mt s nh thc t trng thi ng bng ngt TWI . Trong trng hp ny , thnh phn ca TWDR l khng xc nh. Trong trng hp ca vic mt s kim nh trn bus , khng c d liu no b mt trong qu trnh chuyn t Master xung Slave . Vic iu khin ca bit ACK c iu khin mt cch t ng bng logic TWI , CPU khng th truy nhp vo bit ACK mt cch trc tip Bit 7...0 TWD : thanh ghi d liu TWI Tm bit ny cu thnh byte d liu k tip c chuyn pht , hoc byte d liu cui cng c nhn trn bus 2 dy tun t

Thanh ghi a ch TWI (Slave ) TWAR

TWAR nn c ti vi 7 bit a ch slave (trong 7 bit c trng s cao nht ca TWAR ) ln ci m TWI s p ng khi c lp trnh nh l mt b chuyn pht v thu nhn slave , v khng cn thit trong cc ch master . Trong h thng nhiu master , TWAR phi c ci t trong master ci m c th c nh a ch nh cc slave bi cc master khc LSB ca TWAR c s dng kch hot qu trnh nhn bit ca a ch gi chung ($00) . C mt b so snh ghp a ch ci m tm kim a ch slave (hoc a ch gi chung c kch hot) trong a ch ni tip nhn . Nu 1 ghp tng ng c tm thy , mt yu cu ngt c sinh ra. Bit 7..1 TWA : thanh ghi a ch TWI (slave ) 7 bit ny cu thnh nn a ch slave ca b phn TWI Bit 0 TWGCE : bit kch hot nhn din gi chung TWI Nu c ci t , bit ny kch hot qu trnh nhn din ca 1 lnh gi chung c a ra qua bus 2 dy tun t Vic s dng TWI AVR TWI l byte nh hng v ngt c s . Cc ngt c ban hnh sau khi tt c cc bus s kin , ging nh s thu nhn ca 1 byte hoc qu trnh truyn pht ca mt iu kin START . Bi v TWI l mt ngt c s , phn mm ng dng l t do tip tc cc hot ng khc trong sut 1 qu trnh truyn byte TWI . Ch rng bit kch hot ngt TWI l (TWIE) trong TWCR cng vi bit kch hot ngt chung trong thanh ghi SREG cho php ng dng quyt nh hoc khng c s xc nhn ca c bo TWINT nn sinh ra mt yu cu ngt . Nu bit TWIE b xa , ng dng phi c hi vng c TWINT d tm hnh ng trn bus TWI Khi c bo TWINT c xc nhn , TWI va hon thnh mt qu trnh iu khin v ang i ng dng p ng . Trong trng hp ny thanh ghi trng thi TWI (TWSR) cha mt gi tr ang hin th trng thi hin hnh ca bus TWI . Phn mm ng dng sau c th quyt nh cch m TWI nn tin hnh trong bus TWI k tip bng vic x l TWCR v cc thanh ghi TWDR Hnh 95 l mt v d mu ca cch m ng dng c th giao din vi phn cng TWI . Trong v d ny , mt master mun chuyn 1 byte d liu n n 1 slave . S miu t ny l kh tm tt , mt s din t chi tit hn s phn sau ca phn ny . 1 chng trnh mu v s ci t mun tin hnh th cng c a ra .

1. Bc u tin trong qu trnh truyn pht TWI th truyn mt iu kin START .

2.
3.

4.

5.

iu ny c thc hin bi vic vit mt gi tr xc nh vo trong TWCR , s hng dn cho phn cng TWI truyn mt iu kin START . Ci m gi tr vit th c miu t sau . Tuy nhin , n th quan trng ci m bit TWINT c ci t trong gi tr c vit . Vic vit l mt ln bit TWINT xa c . TWI s khng bt u bt c qu trnh iu khin no ch cn bit TWINT trong thanh ghi TWCR c ci t . Ngay lp tc sau khi ng dng va c xa TWINT , TWI s khi to qu trnh truyn d liu ca iu kin START Khi iu kin START va c truyn i , c bo TWINT trong thanh ghi TWCR c ci t , v TWSR c cp nht vi m trng thi hin th rng iu kin START va c gi thnh cng. Phn mm ng dng nn kim tra gi tr ca TWSR by gi , m bo rng iu kin START va c chuyn thnh cng. Nu TWSR hin th theo cch khc , phn mm ng dng c th to ra vi hnh ng c bit , ging nh vic gi 1 chng trnh con b li . Gi nh rng m trng thi th c mong i , ng dng phi ti SLA+W vo trong TWDR. Nh rng TWDR c s dng cho c a ch v d liu. Sau khi TWDR va c ti vi SLA+W xc nh , 1 gi tr xc nh phi c vit ln TWCR , hng dn phn cng TWI truyn SLA+W a vo trong TWDR . Gi tr vit th c xc nh sau . Tuy nhin , quan trng l bit TWINT c ci t trong gi tr c ghi . Vic vit l 1 ln TWINT xa c . TWI s khng bt u bt c hot ng ch cn bit TWINT trong TWCR c ci t . Ngay lp tc sau khi ng dng va xa TWINT , TWI s khi to qu trnh chuyn d liu ca gi a ch . Khi gi d liu va c chuyn , c bo TWINT trong TWCR c ci t , v TWSR c cp nht vi m trng thi hin th rng gi a ch va c chuyn thnh cng . M trng thi s phn nh rng 1 slave nhn bit gi d liu hoc l khng phn mm ng dng nn kim tra gi tr ca TWSR ngay by gi , m bo rng gi a ch c chuyn thnh cng, v gi tr ca bit ACK nh mong i . Nu TWSR hin th theo cch khc , phn mm ng dng c th to ra vi hnh

ng c bit , ging nh lnh gi mt chng trnh con li . Gi nh rng m trng thi th nh mong i , ng dng phi ti 1 gi d liu vo trong TWDR . Sau , mt gi tr xc nh phi c vit ln TWCR , hng dn phn cng TWI chuyn mt gi d liu a vo trong TWDR. Gi tr m vit ln th c miu t trong phn sau . Tuy nhin , ci quan trng l TWINT c ci t trong gi tr c vit . Vic vit l 1 ln TWINT xa c . TWI s khng khi ng bt c qu trnh no ch cn TWINT trong TWCR c ci t . Ngay lp tc sau khi ng dng va xa TWINT , TWI s khi to mt qu trnh truyn ca mt gi d liu 6. Khi mt gi d liu va c chuyn , c TWINT trong thanh ghi TWCR c ci t , v TWSR c cp nht m trng thi hin th m gi d liu va c chuyn thnh cng . M trng thi cng s phn nh 1 s nhn bit slave l gi hoc khng 7. Phn mm ng dng nn c kim tra gi tr ca TWSR , m bo rng gi d liu va c chuyn pht thnh cng , v ci m gi tr ca bit ACK c mong i . Nu TWSR hin th theo cch khc , phn mm ng dng c th to ra mt vi hnh ng c bit , ging nh vic gi mt chng trnh con b li . Gi nh rng m trng thi nh l mong i , ng dng phi vit mt gi tr xc nh ln TWCR , hng dn phn cng truyn iu kin STOP . Gi tr c vit th c miu t sau . Tuy nhin , quan trng l bit TWINT c ci t trong gi tr c ghi . Vic vit l 1 ln TWINT xa c bo . TWI s khng bt u bt c hnh ng no ch cn TWINT trong TWCR c ci t . Ngay lp tc sau khi ng dng va xa TWINT , TWI s khi to qu trnh chuyn pht ca iu kin STOP . CH rng TWINT th khng c ci t sau mt iu kin STOP va c gi Mc d v d ny l n gin , n cng ch ra nguyn tc c bao hm trong tt c cc qu trnh truyn TWI . Nhng iu ny c th c lit k chi tit nh bn di : - Khi m TWI va hon thnh 1 hot ng v ch i p ng ca ng dng , c TWINT c ci t . ng SCL c ko xung mc thp cho n khi TWINT b xa . - Khi m c TWINT c ci t , ngi s dng phi cp nht tt c cc thanh ghi TWI vi gi tr xc ng cho chu k bus TWI . Nh mt v d , TWDR phi c ti vi gi tr c truyn trong chu k bus tip theo . - Sau khi thanh ghi TWI cp nht v cc phn mm ng dng ang ch khc lm nhim v va hon thnh , TWCR c vit . Khi vic vit TWCR , bit TWINT nn c ci t . Vic vit l 1 ln TWINT xa c . TWI sau s bt u thc thi ci m qu trnh iu khin xc nh bng vic ci t TWCR Bn di l mt on m chng trnh C v Assembly ca v d c a ra . ch rng m bn di c xc nh bng nhiu nh ngha va c to cho v d bng vic s dng cc file bao gm .

Cc ch truyn pht d liu TWI c th hot ng trong mt trong 4 ch chnh . Chng c tn l Master Transmitter (MT) , Master Receiver (MR) , Slave Transmitter (ST ) , Slave Receiver (SR). Mt vi trong s nhng ch c th c s dng trong nhng ng dng ging nhau . Nh l mt v d , TWI c th s dng ch MT vit d liu vo trong TWI EEPROM , ch MR c d liu tr li t EEPROM . Nu cc Master khc c a ra trong h thng , mt vi trong s chng c th chuyn d liu n TWI , v sau ch SR s c s dng . N l phn mm ng dng m quyt nh ch no c s dng Phn tip theo miu t cc ch ny . M trng thi c th c miu t cng vi cc hnh v chi tit ca qu trnh truyn d liu trong mi ch . Cc hnh v ny bao gm cc k hiu vit tt bn di : S : iu kin START Rs : iu kin REPEATED START R : bit c (mc cao ti SDA )

W : Bit vit (mc thp ti SDA ) A : bit nhn bit (mc thp ti SDA ) A : bit khng nhn bit (mc cao ti SDA) Data : byte d liu 8 bit P : iu kin STOP SLA : a ch Slave Trong hnh 97 n hnh 103 , vng trn c s dng hin th rng c TWINT c ci t . S ca vng trn ch ra m trng thi c gi trong TWSR , vi cc bit b m gp trc c che bi 0 . Ti cc im ny , hnh ng phi c thc hin bng ng dng tip tc hoc hon thnh qu trnh truyn TWI . Qu trnh chuyn TWI c hon cho n khi c TWINT b xa bng phn mm . Khi c TWINT c ci t , m trng thi trong TWSR c s dng xc nh thch ng vi hnh ng ca phn mm . Cho mi trng m trng thi , hnh ng cn thit ca phn mm v chi tit ca qu trnh truyn d liu ni tip bn di c a ra trong bng 88 n 91 . Ch rng cc bit ca b m gp trc c che l 0 trong cc bng ny Ch b chuyn pht Master (Master Transmitter Mode ) Trong ch b chuyn pht Master , 1 s cc bit ca cc byte d liu c chuyn ti mt b thu nhn slave (xem hnh 96) . truy nhp vo ch Master , mt iu kin START phi c chuyn pht i . Dng ca cc gi a ch k tip c xc nh ch chuyn pht Master hoc ch thu nhn Master c truy nhp . Nu SLA+W c chuyn , ch MT c truy nhp , nu SLA+R c chuyn pht , ch MR c truy nhp . Tt c cc m trng thi c ni n trong phn ny gi nh rng cc bit b m gp trc l 0 hoc c che bi 0 .

Mt iu kin START c gi bng cch vit gi tr di y ln TWCR

TWEN phi c ci t kch hot giao din 2 dy tun t , TWSTA phi c ghi l 1 chuyn mt iu kin START v TWINT phi c vit l 1 xa c TWINT . TWI sau s kim tra bus 2 dy tun t v sinh ra mt iu kin START ch cn bus tr nn rnh ri . Sau khi mt iu kin START va c chuyn i , c bo TWINT c ci t bng phn cng , v m trng thi trong TWSR s l $08 (xem bng 88) . truy nhp vo ch MT th SLA+W phi c chuyn i . iu ny c thc hin bng cch vit SLA+W ln

TWDR . Sau bit TWINT nn c xa (bng vic vit n l 1) tip tc truyn d liu . iu ny c hon thnh bng vic vit gi tr k tip ln TWCR Khi SLA+W va hon thnh vic chuyn pht , 1 gi d liu nn c chuyn pht . iu ny c thc hin bng cch vit byte d liu ln TWDR . TWDR ch phi vit khi TWINT mc cao . Nu khng , s truy cp s b hy b , v bit xung t vit (TWWC) s c ci t trong thanh ghi TWCR . Sau khi cp nht TWDR , bit TWINT nn b xa (bng vic vit n l 1 ) tip tc qu trnh chuyn pht . iu ny c hon thnh bng vic vit gi tr sau ln TWCR S ny c lp li cho n khi byte cui cng va c gi v qu trnh chuyn pht kt thc bng vic sinh ra 1 iu kin STOP hoc lp li iu kin STOP . 1 iu kin STOP c sinh ra bng vic vit gi tr di y ln TWCR : Mt iu kin REPEATED START c sinh ra bng vic vit gi tr di y ln TWCR Sau khi mt s lp li iu kin START (trng thi $10) giao din 2 dy tun t c th truy nhp slave ging nhau li , hoc 1 slave mi thiu qu trnh truyn mt iu kin STOP . Lp li START kch hot master chuyn mch gia cc slave , ch my pht Master v ch b thu nhn Master thiu mt vic iu khin ca bus.

Ch b thu nhn Master (Master Receiver Mode ) Trong ch b thu nhn Master , 1 s ca cc byte d liu nhn t 1 b chuyn pht slave (xem hnh 98) . truy nhp vo ch Master , 1 iu kin START phi c chuyn pht . . Dng ca cc gi a ch k tip c xc nh ch chuyn pht Master hoc ch thu nhn Master c truy nhp . Nu SLA+W c chuyn , ch MT c truy nhp , nu SLA+R c chuyn pht , ch MR c truy nhp . Tt c cc m trng thi c ni n trong phn ny gi nh rng cc bit b m gp trc l 0 hoc c che bi 0 . Hnh 98 . chuyn d liu trong ch b thu nhn Master

Mt iu kin START c gi bng vic vit gi tr di y ln TWCR :

TWEN phi c vit l 1 kch hot giao din 2 dy tun t , TWSTA phi c ghi l 1 chuyn iu kin START v TWINT phi c ci t xa c TWINT . TWI sau s kim tra bus 2 dy tun t v sinh ra mt iu kin START ch cn bus tr nn t do . Sau khi iu kin START va c chuyn i , c TWINT c ci t bng phn cng , v m trng thi trong TWSR s l $08 (xem bng 88). truy nhp vo ch MR , SLA+R phi c chuyn i . iu ny c thc hin bng vic vit SLA+R ln TWDR . Sau bit TWINT nn b xa (bng vic vit n l 1) tip tc chuyn d liu . iu ny c thc hin bng vic vit gi tr di y ln TWCR : Khi SLA+R va c chuyn v mt bit nhn bit va c nhn , TWINT c ci t li v 1 s ca cc m trng thi trong thanh ghi TWSR l c th . M trng thi c th trong ch Master l $38 , $40 , $48 . Hnh ng thch ng c xy ra khi cho mi mt trong cc m trng thi thanh ghi c lit k chi tit trong bng 97 . Tn hiu nhn c th c c t thanh ghi TWDR khi m c TWINT c ci t mc cao bi phn cng . S ny c lp li cho n khi byte cui cng c nhn . Sau khi byte cui cng va c nhn , MR nn c thng bo ST bng vic gi 1 NACK sau khi byte d liu cui cng c nhn. S chuyn pht phi c kt thc bng vic sinh ra mt iu kin STOP hoc 1 iu kin START c lp li . Mt iu kin STOP c sinh ra bng vic vit gi tr di y ln TWCR Mt iu kin REPEATED START c sinh ra bng vic vit gi tr di y ln TWCR : Sau khi lp li iu kin START (trng thi $10)giao din 2 dy tun t c th truy nhp li vo slave ging nhau , hoc 1 slave mi thiu s truyn pht 1 iu kin STOP . Lp li iu kin START kch hot master chuyn mch gia cc Slave , ch truyn pht Master v thu nhn Master thiu vng s mt d liu iu khin trn bus

Ch b thu nhn slave (slave Receiver Mode ) Trong ch b thu nhn Slave , 1 s ca cc byte d liu c nhn t 1 b chuyn pht master(xem hnh 100) . Tt c cc m trng thi c ni n trong phn ny gi nh rng cc bit b m gp trc l 0 hoc b che bi 0 .

 khi to ch b thu nhn Slave , TWAR v TWCR phi c khi to nh bn di : Hn 7 bit th c nh a ch ti ci m giao din 2 dy tun t s p ng khi c nh a ch bi master . Nu nh LSB c ci t , TWI s p ng nh a ch gi chung ($00) , ni cch khc n s b qua a ch gi chung . TWEN phi c ghi l 1 kch hot TWI . bit TWEA phi c ghi l 1 kch hot s tha nhn ca a ch slave ca ring thit b hoc a ch gi chung . TWSTA v TWSTO phi c ghi l 0 . Khi TWAR v TWCR va c khi to , TWI i cho n khi n c nh a ch bi slave ring ca n (hoc a ch lnh gi chung nu c kch hot ) c theo bi bit nh hng d liu . Nu bit nh hng l 0 (ghi ) , TWI s hot ng trong ch SR , ni cch khc ch ST c truy nhp .Sau khi a ch slave ring ca n v bit ghi va c nhn , c bo TWINT c ci t v mt m trng thi c hiu lc c th c t TWSR . M trng thi c s dng xc nh hnh ng thch ng ca phn mm . Hnh ng thch ng ca phn mm to ra trong mi m trng thi c nu chi tit trong bng 90 . Ch b nhn Slave cng c th c truy nhp nu nh qu trnh gim nh b mt trong khi TWI trong ch master (xem cc trng thi $68 v $78) Nu bit TWEA c reset trong sut mt qu trnh chuyn pht , TWI s phn hi mt Not Acknowledge 1 ti SDA sau khi byte d liu tip theo c nhn . iu ny c th c s dng hin th rng Slave th khng th nhn bt c byte no nhiu hn .Trong khi TWEA l 0 , TWI khng nhn ra a ch slave ring ca n . Tuy nhin , bus 2 dy tun t vn c quan st v s nhn din a ch c th khi phc ti bt c thi gian no bng vic ci t TWEA . iu ny ng rng bit TWEA c th c s dng ngt tm thi TWI khi bus 2 dy tun t Trong tt c cc ch ng khc hn l ch Idle , xung nhp h thng ti TWI th c tt .Nu bit TWEA c ci t , giao din c th vn nhn ra c a ch slave ca ring n hoc a ch gi chung bng cch s dng xung nhp bus 2 dy tun t nh l mt ngun xung nhp . B phn sau s nh thc khi ch sleep v TWI s gi xung nhp SCL thp trong sut qu trnh nh thc v cho n khi c bo TWINT b xa (bng vic vit n ln 1) S nhn d liu khc s c tip tc nh bnh thng , vi cc xung nhp AVR ang chy nh bnh thng . Ch rng nu AVR c ci t vi mt thi gian khi ng

di , ng SCL c th c gi mc thp trong mt thi gian di , vic kha cc qu trnh chuyn d liu khc Ch rng thanh ghi d liu giao din 2 dy tun t - TWDR khng phn nh byte cui cng c a ra trn bus khi ang nh thc t cc ch ng .

Ch b chuyn pht Slave ( Slave Transmitter Mode) Trong ch b chuyn pht Slave , 1 s ca cc byte d liu c chuyn pht ti mt b thu master (xem hnh 102 ) . Tt c cc m trng thi c ni n trong phn ny gi nh rng cc bit b m gp trc l 0 hoc b che ln 0 .

khi to ch b chuyn pht Slave , TWAR v TWCR phi c khi to nh di y :

Hn 7 bit th c nh a ch ti ci m giao din 2 dy tun t s p ng khi c nh a ch bi master . Nu nh LSB c ci t , TWI s p ng nh a ch gi chung ($00) , ni cch khc n s b qua a ch gi chung TWEN phi c ghi l 1 kch hot TWI . bit TWEA phi c ghi l 1 kch hot s tha nhn ca a ch slave ca ring thit b hoc a ch gi chung . TWSTA v TWSTO phi c ghi l 0 . Khi TWAR v TWCR va c khi to , TWI i cho n khi n c nh a ch bi slave ring ca n (hoc a ch lnh gi chung nu c kch hot ) c theo bi bit nh hng d liu . Nu bit nh hng l 1 (c ) , TWI s hot ng trong ch ST , ni cch khc ch SR c truy nhp .Sau khi a ch slave ring ca n v bit ghi va c nhn , c bo TWINT c ci t v mt m trng thi c hiu lc c th c t TWSR . M trng thi c s dng xc nh hnh ng thch ng ca phn mm . Hnh ng thch ng ca phn mm to ra trong mi m trng thi c nu chi tit trong bng 91 . Ch b nhn Slave cng c th c truy nhp nu nh qu trnh gim nh b mt trong khi TWI trong ch master (xem cc trng thi $B0) Nu bit TWEA c vit l 0 trong sut 1 qu trnh chuyn pht , TWI s chuyn byte d liu cui cng ca qu trnh chuyn pht . Trng thi $C0 v trng thi $C8 s c truy nhp , ph thuc vo b nhn master chuyn pht 1 NACK v ACK sau khi byte kt thc . TWI c chuyn mch ti ch slave khng c nh a ch , v s b qua master nu n tip tc truyn pht . V vy b thu nhn master nhn tt c 1 nh l d liu ni tip . Trng thi $C8 c truy nhp nu cc byte d liu thm vo s yu cu master (bng vic truyn bit ACK), mc d slave va truyn byte cui cng (TWEA l 0 v ang mong i NACK t master) Trong khi TWEA l 0 , TWI khng p ng ti a ch slave ca ring n . Tuy nhin , bus 2 dy ni tip vn c gim st v s nhn din a ch c th khi phc ti bt c thi gian no bng vic ci t TWEA . iu ny tc l TWEA c th s dng ngt tm thi TWI khi bus 2 dy tun t . Trong tt c cc ch ng khc hn l ch Idle , xung nhp h thng ti TWI th c tt .Nu bit TWEA c ci t , giao din c th vn nhn ra c a ch slave ca ring n hoc a ch gi chung bng cch s dng xung nhp bus 2 dy tun t nh l mt ngun xung nhp . B phn sau s nh thc khi ch sleep v TWI s gi xung nhp SCL thp trong sut qu trnh nh thc v cho n khi c bo TWINT b xa (bng vic vit n ln 1) S nhn d liu khc s c tip tc nh bnh thng , vi cc xung nhp AVR ang chy nh bnh thng . Ch rng nu AVR c ci t vi mt thi gian khi ng di , ng SCL c th c gi mc thp trong mt thi gian di , vic kha cc qu trnh chuyn d liu khc Trong tt c cc ch ng khc hn l ch Idle , xung nhp h thng ti TWI th c tt .Nu bit TWEA c ci t , giao din c th vn nhn ra c a ch slave ca ring n hoc a ch gi chung bng cch s dng xung nhp bus 2 dy tun t nh l mt ngun xung nhp . B phn sau s nh thc khi ch sleep v TWI s gi xung nhp SCL thp trong sut qu trnh nh thc v cho n khi c bo TWINT b xa (bng vic vit n ln 1) S nhn d liu khc s c tip tc nh bnh thng , vi cc xung nhp AVR ang chy nh bnh thng .

Ch rng nu AVR c ci t vi mt thi gian khi ng di , ng SCL c th c gi mc thp trong mt thi gian di , vic kha cc qu trnh chuyn d liu khc

Cc trng thi hn hp

Trng thi $F8 hin th rng khng c thng tin xc ng no l kh dng bi v c bo TWINT khng c ci t . iu ny xut hin gia cc trng thi khc , v khi TWI khng c cha trong mt qu trnh chuyn pht ni tip Trng thi $00 hin th rng 1 bus li va xut hin trong sut qu trnh chuyn d liu ca bus 2 dy tun t . 1 bus li xut hin khi khi m 1 iu kin START hoc STOP xut hin ti mt v tr khng hp l trong dng khung truyn . Cc mu ca cc v tr khng hp l trong sut qu trnh chuyn d liu ni tip ca mt byte a ch , mt byte d liu, hoc mt bit nhn bit . Khi mt bus li xut hin , TWINT c ci t . khi phc t mt bus li , c TWSTO phi c ci t v TWINT phi b xa bng vic vit mc logic 1 ln n . iu ny gy ra TWI truy nhp vo ch Slave khng a ch xa c TWSTO (khng c bit no khc trong TWCR b nh hng ) . Cc ng SDA v SCL c gii phng, v khng c iu kin STOP no c chuyn i

Vic kt ni nhiu ch TWI ni tip Trong mt vi trng hp , cc ch TWI phi c kt ni vi nhau hon thnh cc hnh ng thm . Coi nh vic c d liu t 1 nhiu b nh EEPROM . Thng thng , nh l mt qu trnh chuyn pht cha cc bc di y : 1. S chuyn pht phi c khi to 2. EEPROM phi c hng dn vng a ch m nn c 3. qu trnh c phi c tin hnh 4. qu trnh chuyn pht phi c kt thc ch rng d liu c chuyn t master n slave v qua vice versa . Master phi hng dn slave vng a ch m n mun c , s cn thit phi s dng ca ch d MT . Nh mt s xy ra sau , d liu phi c c t slave , v tin hnh s dng ch MR . V vy , hng chuyn d liu phi c thay i . Master phi gi s iu khin bus trong sut nhng bc tip theo , v cc bc ny nn c tip tc nh mt qu trnh iu khin nguyn t . Nu nguyn tc ny b vi phm trong mt h thng nhiu master, cc master khc sau c th nh du d liu trong EEPROM gia bc 2 v bc 3 , v master s c vng a ch d liu sai . Nh l s thay i trong hng chuyn d liu th c hon thnh bng vic chuyn 1 iu kin REPEATED START gia s chuyn pht ca byte a ch v s tip nhn d liu . Sau mt REPEATED START, master gi quyn s hu ca bus . Hnh di y ch ra dng trong vic chuyn pht ny .

H thng nhiu master v s kim nh Trong mt h thng nhiu master c kt ni n cc bus ging nhau , cc qu trnh truyn c th khi to mt cch ng thi bng 1 hoc nhiu trong s chng .TWI tiu chun m bo rng nh cc trng hp c iu khin trong 1 cch m 1 trong s nhiu master s cho php tin hnh vi s chuyn pht , v khng c d liu no b mt trong tin trnh . Mt v d ca mt s tnh hung kim nh c miu t bn di , ni m 2 master ang c gng chuyn d liu n mt slave

Nhiu tnh hung khc nhau c th pht sinh trong qu trnh kim nh , nh l c miu t di y - 2 hoc nhiu master c ang s dng truyn thng ring bit vi cc slave ging nhau . Trong trng hp ny , hoc l slave hoc l bt c master no s bit v s tranh chp b nh - 2 hoc nhiu master ang truy nhp vo slave ging nhau vi d liu khc nhau hoc bit nh hng . Trong trng hp ny , s kim nh s xut hin , hoc l trong bit c/vit hoc l trong cc bit d liu . Cc master ang c gng xut ra 1 trn SDA trong khi cc u ra master khc l 0 s lm mt s kim nh . S mt mt ca master s chuyn mch ti ch slave khng a ch hoc i cho n khi bus l t do v truyn mt iu kin START mi , ph thuc vo hnh ng ca phn mm ng dng . - 2 hoc nhiu master ang truy nhp vo cc slave ging nhau . Trong trng hp ny , qu trnh kim nh s xut hin trong cc bit SLA . Cc master ang c gng xut ra mt tn hiu 1 trn SDA trong khi cc u ra master khc l 0 s lm mt mt d liu .S mt kim nh ca cc master trong SLA s chuyn n ch slave kim tra nu chng ang c nh a ch bi master chin thng. Nu c nh a ch , chng s chuyn ti ch SR hoc ST , ph thuc vo gi tr ca bit

READ/WRITE . Nu chng ang c nh a ch , chng s chuyn ti ch Slave khng nh a ch hoc i cho n khi bus ri v chuyn pht mt iu kin START mi, ph thuc vo hnh ng ca phn mm ng dng . iu ny c m t chi tit trong hnh 106. gi tr trng thi c th c a ra trong vng trn

XX . Analog comparator
B so snh tng t so snh cc gi tr ca u vo trn chn dng AIN0 v chn m AIN1 . Khi in p trn chn dng AIN0 cao hn in p trn chn m AIN1 , u ra ca b so snh tng t ACO c ci t . u ra ca b so snh c th c ci t khi ng chc nng truy bt tn hiu u vo ca Timer/Counter 1 . Thm vo , b so snh c th khi ng 1 ngt ring bit , dnh ring cho b so snh tng t . Ngi s dng c th la chn khi ng ngt ca b so snh u ra tng, gim hoc di chuyn. Mt s khi ca b so snh v cc khi logic xung quanh n c ch ra hnh 107 .

Thanh ghi IO chc nng c bit_SFIOR Bit3_ACME : Kch hot b dn knh ca b so snh tng t Khi bt ny c vit l 1 v b chuyn i ADC c tt (Bt ADEN trong thanh ghi ADCSRA l 0 ) , b dn knh ADC la chn u vo m ln b so snh tng t . Khi bt ny c vit l 0 , AIN1 c t ln u vo m ca b so snh tng t bit thm chi tit ca bt ny xem trang 228 Thanh ghi trng thi v iu khin b so snh tng t ACSR Bt 7_ACD : V hiu ha b so snh tng t Khi bt ny c vit l 1 , ngun cung cp ti b so snh tng t b ngt . Bt ny c th c ci t ti bt c thi im no tt b so snh tng t. iu ny s lm gim tn hao ngun trong cc ch Active v Idle . Khi thay i bt ACD , cc ngt ca b so snh tng t phi c v hiu ha bng vic xa bt ACIE trong thanh ghi ACSR . Ni cch khc, 1 ngt c th xut hin khi bt ny b thay i Bt 6_ACBG : La chn khe song (bandgap ) ca b so snh tng t Khi bt ny c ci t , mt bandgap n nh in p tham chiu thay th u vo dng n b so snh tng t . Khi bt ny b xa , AIN0 c t ln u vo dng ca b so snh tng t . Xem thm phn Internal Voltage Reference trang 54 Bt 5_ACO : u vo ca b so snh tng t u vo ca b so snh tng t c ng b ha v sau c ni trc tip ti ACO , s ng b ha ny gy ra 1 tr trong 1 hoc 2 chu k xung nhp

Bt 4_ACI : C bo ngt b so snh tng t Bt ny c ci t bng phn cng khi m 1 bin c u ra ca b so snh khi ng 1 ch ngt c xc nh bi bt ACIS1 v ACIS0 . Chng trnh con phc v ngt b so snh tng t c thc thi nu bt ACIE c ci t v bt I trong thanh ghi SGDN c ci t . Bt ACI b xa bng phn cng khi m vic thc thi cc vector iu khin ngt tng ng c hon thnh . Nh 1 s la chn , ACI c xa bng cch vit mc logic 1 ln c ngt Bt 3_ACIE : Kch hot ngt b so snh tng t Khi m bt ACIE c vit l 1 v bt I trong thanh ghi trng thi c ci t , ngt ca b so snh tng t c kch hot . Khi c vit l 0 th ngt c v hiu ha Bt 2_ ACIC : Kch hot truy bt tn hiu u vo ca b so snh tng t Khi c vit l 1 bt ny kch hot chc nng truy bt tin hiu u vo trong Timer/Counter 1 khi ng bng b so snh tng t . u ra b so snh trong trng hp ny c ni trc tip n cng logic front-end ca b truy bt tn hiu u vo lm cho b so snh tn dng cc kha ct nhiu v tnh nng la chn sn ca ngt truy bt tn hiu u vo Timer/Counter 1 . Khi c vit l 0 , khng c kt ni no gia b so snh tng t v u ra ca khi chc nng truy bt tn hiu u vo . lm cho b so snh khi ng ngt truy bt tin hiu u vo timer/counter 1 . Bt TICIE1 trong thanh ghi che ngt Timer (TIMSK) phi c ci t Bt 1,0 : La chn ch ngt so snh tng t Cc bt ny xc nh ci m cc bin c ca b so snh tng t khi ng cc ngt ca b so snh tng t . Vic ci t khc nhau c minh ha bng 93

Khi thay i cc bt ACIS1/ACIS0 cc ngt ca b so snh tng t phi c v hiu ha bng vic xa cc bt kich hot ngt ca n trong thanh ghi ACSR , ni cch khc, 1 ngt c th xut hin khi m cc bt ny c th b thay i u vo dn knh ca b so snh tng t C th la chn bt c chn no trong cc chn ADC7..0 thay th u vo m n b so snh tng t . B dn knh ADC c s dng la chn u vo ny ko theo vic ADC phi c tt dng tnh nng ny . Nu nh bt kch hot b dn knh ca b so snh tng t (ACME trong SFIOR) c ci t v b chuyn i ADC c tt (Bt ADEN trong thanh ghi ADCSRA l 0 ) , cc bt MUX2..0 trong thanh ghi ADMUX la chn cc chn vo ny thay th chn vo m n b so snh tng t , c ch ra trong bng 94 .

Nu ACME b xa hoc ADEN c ci t , bt AIN1 c t ln u vo m ti b so snh tng t

XXI . B chuyn i tng t sang s (Analog to Digital Converter )

Cc c im : - chnh xc 10 bt - 0.5 LSB Integral Non-Linearity - Khong tuyt i 2 LSB - Thi gian chuyn i t 13 - 260s - Nng ln 76,9 kSPS ( Nng ln 15 kSPS ) chnh xc cc i - 8 knh multiplexed single ended input - 7 knh u vo ring bit - 2 knh u vo ring bit vi cc khuych i - S iu chnh dy chuyn , la chn cho kt qu c bn ngoi ADC - 0_VCC di in p u vo ADC - C th la chn 2,56V in p tham chiu ADC - Ch chuyn i n hoc chy t do - Ngt trn hon thnh qu trnh chuyn i ADC - Kha ct nhiu ch ng (Sleep mode ) Cc tnh nng ca Atmega128 c 1 b ADC sp x lien tip 10 bt . B ADC c kt ni n 1 b dn knh tng t 8 knh, ci m cho php 8 u vo in p Singel ended . Cc u vo in p single ended c t l 0 (chn GND) Thit b ny cng h tr 16 kt ni u vo in p ring bit , 2 cp u vo ring bit (ADC1 , ADC0 v ADC3, ADC2) c trang b vi 1 cng khuyech i c th lp trnh , vic cung cp cc bc khuyech i l 0dB (1x) , 20dB(10x) , 46dB(200x)

trn cc cng in p ring bit trc khi c qu trnh chuyn i A/D . 7 knh u vo tng t ring bit chia s 1 u cui m chung (ADC1) , trong khi bt c cc u vo ADC khc u c th c la chn nh l 1 u cui u vo dng . Nu khuyech i 1x hoc 10x c s dng , chnh xc 8 bt c th c ch i . Nu khuyech i 200x c s dng , chnh xc 7bit c th c ch i . B ADC bao gm 1 mch ly mu v mch gi mc ci m m bo rng in p u vo n ADC c gi 1 mc khng i trong sut qu trnh chuyn i . S khi ca 1 b ADC c ch ra trong hnh 108 B ADC c 1 chn in p ngun cp tng t ring bit , AVCC . AVCC phi khc bit hn 0,3V t chn VCC . Xem phn kha ct nhiu ADC trn trang 236 bit cch kt ni cc chn ny . Cc in p tham chiu bn trong ca in p thng thng 2,56V hoc AVCC c cung cp trn chip . in ap tham chiu c th tch ri ti chn AREF bng 1 t c c cc ng c tnh nhiu tt hn

Hot ng

B ADC chuyn i 1 in p u vo tng t thnh 1 gi tr s 10 bt thng qua cc php tnh xp x lien tip . Gi tr cc tiu a ra chn GND v gi tr cc i ca in p trn chn AREF ti thiu l 1 LSB . S la chn gia AVCC hoc 1 in p tham chiu bn trong 2,56 V c th c kt ni n chn AREF bng vic vit ln cc bt RESFn trong thanh ghi ADMUX . in p tham chiu bn trong c th c tch ri bng 1 t bn ngoi chn AREF ci thin cc nhiu . Knh u vo tng t v cc h s khuyech i ring bit bng vic vit ln cc bt MUX trong thanh ghi ADMUX bt c chn no trong s cc chn u vo ADC nh l chn GND v in p tham chiu bandgap n nh , u c th c la chn nh l cc u vo Singel ended ln cc chn ADC , 1 s la chn ca cc chn u vo ADC c th c la chn nh l chn m v dng ln cch b khuyech i ring bit Nu cc knh ring bit c la chn , cng khuyech i ring bit s khuyech i s chnh lch in p gia cc cp knh u vo c la chn bng vic la chn h s khuyech i . gi tr c khuyech i sau c tr thnh u vo tng t trong ADC . Nu cc knh single ended c s dng th cc b khuyech i c chuyn qua cng nhau . B ADC c kch hot bng cch ci t cc bt kch hot ADC (ADEN trong ADCSRA). in p tham chiu v s la chn knh u vo s khng c gy nh hng vo bn trong cho n khi bt ADEN c ci t b ADC th khng tiu hao ngun khi m bt ADEN b xa v vy n c khuyn co ngt cc b ADC trc khi truy nhp vo ch b tit kim in trong cc ch ng B ADC pht ra 1 kt qu 10 bt , ci m c a ra trong thanh ghi d liu ADC (ADCH v ADCL ) . Nh mc nh , kt qu ny c a ra 1 s iu chnh ng nhng n c th la chn c a ra s iu chnh di chuyn bng vic ci t bt ADLAR trong thanh ghi ADMUX . Nu nh kt qu c iu chnh di chuyn v khng cn chnh xc ln hn 8 bt . N s c tin hnh c trong ADCH , ni cch khc ADCL c th c c u tin sau ADCH c c , m bo rng cc thnh phn ca cc thanh ghi d liu thuc v cc qu trnh chuyn i ging nhau . Mi ln ADCL c c th b ADC truy cp vo cc thanh ghi d liu b kha . iu ny c ngha l nu ADCL va c c v 1 qu trnh chuyn i hon thnh trc khi ADCH c c th thanh ghi c cp nht d liu v kt qu t qu trnh chuyn i b mt . Khi m ADCH c c ADC truy cp n cc thanh ghi ADCL ADCH kch hot li . B ADC c cc ngt ring ca n , ci m c th c khi ng khi m c 1 s chuyn i hon thnh . Khi b ADC truy nhp vo cc thanh ghi d liu b ngn cm gia qu trnh c ca ADCH v ADCL , cc ngt s khi ng d nu kt qu b mt Khi ng 1 qu trnh chuyn i 1 qu trnh chuyn i n c khi ng bng vic vit mc logic 1 ln bt khi ng chuyn i ADC (ADSC ) . Bt ny mc cao ch cn qu trnh chuyn i ang tin hnh v s b xa bng phn cng khi m qu trnh chuyn i hon thnh . Nu nh 1 knh d liu khc c la chn trong khi 1 qu trnh chuyn i ang tin hnh, b ADC s kt thc qu trnh chuyn i hin ti trc khi s l thay i knh .

Trong ch chy t do, b ADC ly mu v cp nht thanh ghi d liu ADC . Ch chy t do c la chn bng vic vit bt ADFR trong thanh ghi ADCSRA l 1 . Qu trnh chuyn i u tin phi c bt u bng vic vit mc logic 1 ln bt ADSC trong thanh ghi ADCSRA . Trong ch ny , b ADC s tin hnh cc qu trnh chuyn i lien tip ph thuc vo trng thi ca c ngt ADC (ADIF ) b xa hay khng . S m gp trc v gin thi gian ca qu trnh chuyn i

Theo mc nh cc mch tnh sp x lin tip cn thit 1 tn s xung nhp u vo trong khong 50 KHz 200 KHz t chnh xc cc i . Nu 1 chnh xc thp hn 10 bt l cn thit , tn s xung nhp u vo ln ADC c th cao hn 200KHz c 1 tc b ly mu cao hn Modul ADC bao gm 1 b m gp trc , ci m pht ra 1 tn s xung nhp ADC c th chp nhn c t bt c 1 tn s CPU no di 100KHz . S m gp trc c ci t bng cc bt ADPS trong thanh ghi ADCSRA . B m gp trc bt u m t lc m b ADC b ct bng vic ci t bt ADEN trong thanh ghi ADCSRA . B m gp trc vn gi ang chy ch cn bt ADEN c ci t v lin tc khi ng li khi ADEN mc thp Khi khi to 1 chuyn i single ended bng vic ci t bt ADSC trong thanh ghi ADCSRA , qu trnh chuyn i bt u t sn ln k tip ca chu k xung nhp ADC . Xem phn differential gain chanel trn trang 235 bt thm chi tit v gin thi gian ca qu trnh chuyn i ring bit Mt qu trnh chuyn i thng tng to ra 13 chu k xung nhp ADC . Chu k xung nhp u tin sau khi ADC c ng (ADEN trong ADCSRA c ci t ) to ra 25 xung nhp ADC theo th t khi to mch tng t . Thc t qu trnh ly mu v gi mc xy ra trong 1,5 chu k xung nhp ADC sau khi bt u 1 qu trnh chuyn i thng thng v 13,5 xung nhp ADC sau khi bt u 1 qu trnh chuyn i u tin . Khi 1 qu trnh chuyn i c hon thnh , kt qu c vit ln cc thanh ghi d liu ADC v ADIF c ci t .Trong ch chuyn i n , ADSC c xa 1 cch ng thi . Phn mm sau c th ci t ADSC tr li v 1 qu trnh chuyn i mi s c khi to trn sn ln u tin ca sn xung nhp ADC .

Trong ch chy t do , 1 qu trnh chuyn i mi s c bt u ngay lp tc sau khi qu trnh chuyn i hon thnh trong khi ADSC vn cn li mc cao . Cho 1 s lit k chi tit v thi gian chuyn i xem bng 95

Cc knh khuych i ring bit Khi s dng cc knh khuych i ring bit khc nhau , cc dng bit ca qu trnh chuyn i cn c to ra trong qu trnh xem xt . Cc qu trnh chuyn i ring bit th c ng b ha n xung nhp bn trong CKADC2 bng chu k xung nhp ADC .Qu trnh ng b ny c thc hin 1 cch t ng bng giao din ADC theo 1 cch m qu trnh ly mu v gi mc xut hin ti 1 sn xc nh ca CKADC2 . . Mt qu trnh khi ng c khi to bng ngi s dng (Tt c cc qu trnh chuyn i n , v qu trnh chuyn i chy t do u tin ) . Khi m CKADC2 mc thp s to ra cc khong thi gian ging nhau nh l qu trnh chuyn i single ended (13 xung nhp ADC t chu k xung nhp c m gp trc tip theo ) 1 qu trnh chuyn i c khi to bi ngi s dng khi m CKADC2 mc cao s ly mt 14 chu k xung nhp t b phn ng b ha . Trong ch chy t do 1 qu trnh chuyn i mi c khi to ngay lp tc sau khi qu trnh trc c hon thnh , v do CKADC2 mc cao ti thi im ny , tt c cc ch chy t do c khi ng 1 cch t ng s mt 14 chu k xung nhp ADC Cng khuych i c ti u ha cho di tn s ca 4KHz ti tt c cc ch ci t khuy ch i. Cc tn s cao hn c th c xc nh ln qu trnh khuy ch i khng tuyn tnh . 1 b lc thng thp (low - pass) ln c s dng nu tn hiu u ra bao gm cc thnh phn tn s cao hn di sng cng khuy ch i ch rng tn s xung nhp ADC th ph thuc vo gii hn di tn ca cng khuy ch i . V d : chu k xung nhp ADC c th l 6s , cho php 1 knh c ly mu ti 12kSPS , bt chp di tn ca knh ny . S thay i knh hoc la chn mc chun Cc bt MUXn v REFS 1:0 trong thanh ghi ADMUX c ghi vo b m n thng qua 1 thanh ghi tm thi ln ci m CPU s truy cp ngu nhin . iu ny m bo rng cc knh v s la chn mc chun ch c th xy ra ti 1 im an ton trong sut qu trnh chuyn i . Knh m s la chn mc chun th tip tc c cp nht cho n khi 1 qu trnh chuyn i c bt u . Mi mt qu trnh chuyn i c bt u, cc knh v b la chn mc chun b kha m bo rng khong thi gian ly mu cho ADC l ti u . Vic cp nht lin tip khi phc trong chu k xung nhp ADC cui cng trc khi m qu trnh chuyn i c hon thnh (ADIF trong ADCSRA c ci t ) . Ch rng qu trnh chuyn i ny bt u trn sn ln tip theo ca xung nhp ADC sau khi ADSC c vit .

Ngi s dng do vy c khuyn l khng c vit knh mi hoc cc gi tr la chn mc chun mi ln ADMUX cho n khi 1 chu k xug nhp ADC sau khi ADSC c vit. Trng hp c bit ny nn c to ra khi qu trnh chuyn i cc knh ring bit . Cc knh ring bit va c la chn , cng khuy ch i s tiu tn nhiu hn 125s t c gi tr n nh ca n v vy qu trnh chuyn i ny khng nn c bt u sau khi vic la chn 1 knh ring bit mi . Nh 1 s la chn , kt qu ca qu trnh ny t c trong vng chu k ny ln c b i . Thi gian n nh ging nhau ln c quan st trong qu trnh chuyn i ring bit u tin sau khi s thay i mc chun ADC (bng vic thay i cc bt REFS 1:0 trong thanh ghi ADMUX ) Nu nh giao din JTAG c kch hot , chc nng ca cc knh ADC trn cng PORT7:4 c ghi . Tham kho bng 42 trang 83

Cc knh u vo ADC Khi vic la chn thay i cc knh , ngi s dng ln quan st cc hng dn bn di m bo rng vic la chn cc knh c chnh xc trong ch chuyn i n , lun lun la chn cc knh trc khi khi ng 1 qu trnh chuyn i. S la chn knh c th b thay i trong 1 chu k xung nhp ADC sau khi vit l 1 ln bt ADSC . Tuy nhin , phng php n gin nht l i cho n khi qu trnh chuyn i c hon thnh trc khi thay i la chn knh . Trong ch chy t do , lun la chn cc knh trc khi bt u qu trnh chuyn i u tin . Sa la chn knh ny phi c thay i trong 1 chu k xung nhp ADC sau khi vit l 1 ln bt ADSC . Tuy nhin , Tuy nhin , phng php n gin nht l i cho n khi qu trnh chuyn i c hon thnh trc khi thay i la chn knh . Do qu trnh chuyn i tip theo s sn sang c bt u 1 cch t ng , kt qu tip theo s c phn x vo trong la chn knh trc . Qu trnh chuyn i k tip s phn x 1 s la chn knh mi Khi qu trnh chuyn mch ti 1 knh khuy ch i ring bit, KQ ca qu trnh chuyn i u tin c th km chnh xc do s cn thit ca thi gian lng trong 1 mch kha offset t ng , Ngi s dng ln b qua ca qu trnh u tin in p tham chiu ADC in p tham chiu ca ADC (VREF) hin th 1 di gi tr ca qu trnh chuyn i cho b ADC . Cc knh single ended ci m vt tri hn gi tr (VREF) th s gy ra 1 on m ng ln gi tr 0x3FF . (VREF) c th c la chn gia cc gi tr AVcc, in p tham chiu bn trong 2,56V hoc chn VREF bn ngoi AVCC c ni vi b ADC thng qua 1 b chuyn mch b ng . in p tham chiu 2,56V bn trong c pht ra t in p tham chiu bandgap bn trong (VBG) thng qua 1 b khuy ch i bn trong , trong trng hp ny chn AREF bn trong

c ni trc tip n b ADC , v in p tham chiu c th c min nhim vi nhiu hn bng vic ni 1 t in gia chn AREF v chn GND . VREF c th cng c o ti chn AREF vi 1 vn k c tr khng cao . Ch rng VREF l 1 ngun tr khng cao v ch l 1 ti in dung ln c kt ni vo 1 h thng Nu ngi s dng c 1 ngun in p n nh c kt ni n chn AREF , ngi s dng khng th la chn cc in p tham chiu khc , trong cc ng dng do h s rt ngn (shorted) in p bn ngoi . Nu khng c ngun in p bn ngoi no c t vo chn AREF ngi s dng c th chuyn mch gia AVCC v 2,56V nh l 1 la chn in p tham chiu . KQ ca qu trnh chuyn i ADC sau khi vic chuyn mch ngun in p tham chiu c th khng chnh xc , v ngi s dng c khuyn l khng chp nhn kt qu ny Nu cc knh khc nhau c s dng , in p tham chiu c la chn s b ng ln chn AVCC nh c hin th trong bng 136 trang 326 Kha ct nhiu ADC ADC c 1 kha ct nhiu , ci m kch hot qu trnh chuyn i trong sut ch ng gim nhiu c a ra t li ca CPU v cc ngoi vi IO khc . Kha ct nhiu c th c s dng vi ch gim nhiu ADC v ch bn Idle s dng tnh nng ny , 1 quy trnh di y ln c s dng - m bo rng b ADC c kch hot v khng c qu trnh chuyn i no ang bn . Ch chuyn i n phi c la chn v cc ngt hon thnh b chuyn i ADC phi c kich hot - Vic truy nhp vo ch gim nhiu ADC hoc ch Idle . B ADC s bt u 1 qu trnh chuyn i mi ln m CPU b tm dng - Nu nh khng c ngt no khc xut hin trc khi qu trnh chuyn i ADC hon thnh cc ngt ca ADC s nh thc CPU v cc chng trnh con phc v ngt hon thnh qu trnh chuyn i ADC . Nu 1 ngt khc nh thc CPU trc khi qu trnh chuyn i ADC hon thnh , ngt s c thc thi , v 1 yu cu ngt hon thnh chuyn i ADC s c sinh ra khi m qu trnh chuyn i ADC hon thnh . CPU s phc hi trong ch hot ng cho n khi 1 lnh sleep mi c thc thi Ch rng :b ADC s khng c tt 1 cch t ng khi truy nhp vo cc ch ng khc 2 ch Idle v gim nhiu ADC . Ngi s dng c khuyn l nn vit mc Zero ln bt Adle trc khi qu trnh truy nhp vo nhiu ch ng khc nhau trnh tn hao in p on mch. Nu nh b ADC c kch hot trong nhiu ch ng v ngi s dng mun tin hnh cc qu trnh chuyn i khc , ngi s dng c khuyn l tt ADC v sau nh thc li t ch ng yu cu 1 qu trnh chuyn i m rng ly 1 kt qu hp l

Mch u vo tng t
Mch u vo tng t cho cc knh single ended c minh ha trong hnh 113 . 1 ngun tng t t ln ADCn subjected ln chn ca t v input leakage ca chn , bt chp vic knh c la chn nh l 1 u vo cho b ADC . Khi 1 knh c la chn, ngun phi iu khin t S/H thng qua b in tr (c kt hp cc in tr trong ng dn vo ) . B ADC c ti u ha cho tt c cc tn hiu tng t vi tr khng u ra khong 10K hoc nh hn . Nu nh 1 ngun c s dng , thi gian ly mu s khng ng k . Nu 1 ngun vi tr khng cao hn c s dng , thi gian ly mu s ph thuc vo khong thi gian m ngun cn np vo t S/H , v c th bin i rng . Ngi s dng c khuyn co ch s dng cc ngun tr khng thp vi cc tn hiu bin i chm , do iu ny lm cc tiu thi gian np vo t S/H . Nu cc knh c khuy ch i khc c s dng , mch u ra s nhn thy 1 s im khc bit mc d cc ngun tr khng 1 vi trm K hoc nh hn c khuyn dng Cc thnh phn ca tn hiu cao hn tn s Nyquist (fADC/2) nn khng c a ra cho cc loi knh khc . trnh bin dng mo t unpredictable signal convolution . Ngi s dng c khuyn ln g b cc thnh phn tn s co bng 1 b lc thng thp trc khi vic p dng cc tn hiu nh l cc u vo ti b ADC

Cng ngh kha ct nhiu Analog Mch s bn trong v bn ngoi ca thit b pht ra EMI ci m c th nh hng ti chnh xc ca b do tng t . Nu chnh xc ca qu trnh chuyn i l quan trng , mc nhiu c th c gim bng cch p dng k thut di y : - Gi cho cc ng dn tn hiu tng t ngn nht c th . m bo rng cc Analog track chy qua mt t , v gi chng trnh xa b chuyn mch digital track tc cao

- Chn AVCC trn thip b nn c kt ni vi in p ngun cp s Vcc nh l 1 mng NC c ch ra trong hnh 114 - s dng chc nng kha ct nhiu lm gim nhiu t CPU - Nu bt c chn cng no ca ADC c s dng nh l 1 u ra s iu thit yu l s khng c s chuyn mch no trong khi 1 qu trnh chuyn i ang tin hnh

Mch b Offset Cng khuy ch i c 1 mch kh build-in offset , ci m trit tiu offset ca cc b o ring bit nhiu nht c th . Cc offset cn li trong ng dn tng t c th c o trc tip bng vic la chn cc knh ging nhau cho c 2 loi u vo ring bit . Cc phn d offset ny c th c loi tr bng phn mm khi kt qu ca vic o . Vic s dng loi phn mm sa li offset c bn ny , offset v cc knh khc c th c lm gim bn di 1 LSB Xc nh chnh xc ca ADC

1 n-bit single ended ADC chuyn i 1 di in p gia chn GND v chn VREF trong 2 bc (LSBs) . on m thp nht c c l 0 , on m cao nht c l 2n-1 . Hng lot tham s c miu t lch l tng t qu trinh tin hnh - Offset : lch ca qu trnh di chuyn u tin ( t 0x000 n 0x001 ) c so snh vi qu trnh di chuyn l tng ( 0,5 LSB) . Gi tr l tng l 0 LSB
n

Li khuy ch i : Sau khi qu trnh iu khin Offset li khuy ch i

c tm thy trong lch di chuyn cui cng (0x3FE n 0x3FF ) c so snh vi s di chuyn l tng ( 1,5 LSB bn di mc cc i ) . Gi tr l tng l 0 LSB

Integral non-linearity (INL) : sau qu trnh iu chnh ca Offset , v li

khuy ch i , INL l lch cc i ca qu trnh di chuyn hin thi c s snh vi 1 qu trnh di chuyn l tng . Gi tr l tng l 0LSB

- Differential non-linearity (DNL) : lch cc i ca actual code width (on gia 2 s di chuyn k cn ) t ideal code width . Gi tr l tng l 0LSB

Li lng t ha : d cho s lng t ha ca in p u vo l 1 s hu hn ca cc m , 1 khong gi tr ca in p u vo (1LSB) s vit cc gi tr ging nhau : lun lun l 0,5 LSB . chnh xc tuyt i : lch cc i ca 1 qu trnh di chuyn thc s (khng c iu chnh ) c so snh vi 1 s di chuyn l tng cho bt c m no . iu ny l nh hng phc tp ca Offset li khuy ch i , cc li khc Non-liearity , li lng t ha . Gi tr l tng l 0,5 LSB Kt qu ca qu trnh chuyn i ADC Sauk hi qu trnh chuyn i c hon tt (ADIF mc cao ) , KQ ca qu trnh chuyn i c th c tm thy trong thanh ghi Kt qu ADC (ADCH v ADCL ) Vi qu trnh chuyn i single ended , kt qu l :

Ni m VIN l in p trn chn u vo c la chn v VREF c la chn t in p tham chiu (Xem bng 97 . 98 trang 242 ) . Bt 0x000 c ni vi t v 0x3FF c ni vi in p tham chiu c la chn nh hn 1 LSB . Nu cc knh khc c s dng kt qu l :

Ni m VPOS l in p trn chn u vo dng , VNEG l in p trn chn u vo m GAIN c la chn l t l khuy ch i , v VREF c la chn in p tham chiu . Kt qu c a ra bng 2 dng , t 0x200 (-512d ) thng qua 0x1FF (+ 511d ) . Ch rng nu ngi s dng mun tin hnh 1 qu trnh kim tra nhanh ca kt qu , n phi c c MSB ca kt qu bt cao nht (ADC9 trong ADCH ) . Nu bt ny c vit l 1 kt qu l m , nu n l 0 kt qu l dng . Hnh 119 ch ra b gii m ca di tn hiu u vo khc nhau Bng 96 ch ra kt qu ca cc m u vo , nu nh cc cp knh u vo khc nhau (ADCn ADCm ) c la chn vi 1 h s khuy ch i GAIN ln v in p tham chiu VREF

Chng trnh mu Thanh ghi la chn ghp knh ADC_ADMUX

Bits7:6_REFS 1: 0 . Cc bt la chn in p tham chiu Cc bt ny la chn in p tham chiu cho b ADC , nh c ch ra trong bng 97 . Nu cc bt ny b thay i trong sut qu trnh chuyn i , s thay i s khng c nh hng cho n khi qu trnh chuyn i c hon thnh (ADIF trong thanh ghi ADCSRA c ci t) . Cc in p tham chiu bn trong c th s dng nu 1 in apt ham chiu bn ngoi ang c t ln chn AREF

Bt 5_ADNAR : kt qu iu chnh di chuyn ADC Bt ADNAR nh hng vi s biu din ca kt qu s chuyn i ADC trong thanh ghi d liu ADC . Vit mc 1 ln ADNAR iu chnh di chuyn sang tri kt qu . Ni cch khc kt qu ny c iu chnh ng . Vic thay i bt ADNAR s nh hng n thanh ghi d liu ADC ngay lp tc , bt chp bt c qu trnh chuyn i no ang hot ng . c 1 s miu t hon chnh v bt ny xem thanh ghi d liu ADC_ADCH v ADCL trang 245 Bt 4..0_ MUX4 : 0 bt la chn h s khuy ch i v tng t . Gi tr ca cc bt ny la chn s kt hp ca cc u vo tng t c kt ni ti ADC . Cc bt ny cng la chn cc h s khuy ch i cho cc knh khc nhau . Xem bng 98 . Nu cc bt ny b thay i trong sut qu trnh chuyn i . S thay i s khng c hiu lc cho n khi qu trnh chuyn i ny c hon thnh (ADIF trong ADCSRA c ci t )

Thanh ghi trng thi v iu khin ADC_ADCSRA

Bits7_ADEN : Kch hot ADC Vic t bt ny =1 s kch hot ADC . Nu =0 th ADC b tt . Qu trnh iu khin ADC tt trong khi 1 s chuyn i ang tin hnh s kt thc qu trnh chuyn i ny . Bt 6 _ADSC : Bt u qu trnh chuyn i ADC Trong ch chuyn i n , vit bt ny l 1 khi ng mi qu trnh chuyn i . Trong ch chy t do vit bt ny l 1 khi ng qu trnh chuyn i u tin . Qu trnh chuyn i u tin sau khi bt ADSC c vit sau khi ADC c kch hot , hoc ADSC c vit cng thi im vi ADC c kch hot s ly mt 25 chu k xung nhp ADC thay th cho ch thng thng l 13 . Qu trnh chuyn i u tin ny tin hnh khi to ADC

ADSC s c l 1 ch cn 1 qu trnh ang tin hnh . Khi qu trnh chuyn i c hon thnh n tr v khng . Vic vit l 0 ln bt ny th s khng c hiu lc g Bt 5_ADSR : La chn ch chy t do ADC Khi bt ny c vit l 1 ADC hot ng trong ch chy t do . Trong ch ny , ADC ly mu v cp nht thanh ghi d liu lin tip . Vit bt ny l 0 s kt thc ch chy t do . Bt 4_ADIF : C bo ngt ADC Bt ny c ci t khi 1 qu trnh chuyn i ADC c hon thnh v cc thnh ghi d liu c cp nht cc ngt bo hon thnh qu trnh chuyn i ADC c thc thi nu bt ADIE v bt I trong thanh ghi SREG c t . ADIF b xa bng phn cng khi thc thi xong cc vector iu khin ngt tng ng . Nh 1 s la chn , ADIF b xa bng vic vit mc logic 1 ln c . Ch rng nu ang thc hin 1 qu trnh Read-modify-Write trn thanh ghi ADCSRA , 1 ngt ang tin hnh c th b v hiu ha . iu ny cng xy ra nu cc lnh SBI v CBI c s dng Bt 3_ADIE : Kch hot cc ngt ADC Khi bt ny l 1 v bt I trong thanh ghi SREG c t th c bo ngt hon thnh qu trnh chuyn i ADC c kch hot Bt 2..0_ADPS 2:0 . Bt la chn b m gp trc ADC Cc bt ny xc nh h s chia gia tn s XTAL v cc xung nhp u vo ln b ADC

Thanh ghi d liu ADC _ ADCH , ADCL

Khi qu trnh chuyn i ADC c hon thnh , kt qu c tm thy trong 2 thanh ghi . Nu 2 knh ring bit c s dng kt qu c a ra trong 2 dng hon ton khc nhau . Khi ADCL c c thanh ghi d liu ADC khng c cp nht cho n khi ADCH c cp nht . Nu kt qu c di chuyn v khng cn chnh xc 8 bt , n iu kin c ADCH . Ni cch khc ADCL phi c c u tin sau l ADCH . Bt ADLAR trong thanh ghi ADMUX v cc bt MUXn trong thanh ghi ADMUX nh hng ln cch m kt qu c c t cc thanh ghi . Nu ADLAR c t kt qu c iu chnh di di . Nu ADLAR b xa (nh mc nh ) . Kt qu l ng Bt ADC9:0 . Kt qu ca qu trnh chuyn i . Cc bt ny a ra kt qu ca qu trnh chuyn i nh c a ra bng 241

XXII . Giao din JTAG v h thng hiu chnh li trn chip

c im - giao din JTAG ( ph hp vi tiu chun IEEE 1149 ) - kh nng Qut gii hn bin (boundary scan ) theo chun IEEE1149 (JTAG) - B hiu chnh li truy nhp ti + Tt c cc thnh phn ngoi vi bn trong + RAM trong v ngoi + File thanh ghi bn trong + b m chng trnh + Cc b nh EEPROM v b nh chng trnh - H tr hiu chnh li trn chip m rng cho cc iu kin ngt (break) bao gm

+ lnh ngt AVR + dng trn qu trnh thay i ca dng nh chng trnh + Bc dng n (Single Step Break ) + lp trnh im ngt b nh trn a ch n hoc di a ch - Lp trnh Flash , EEPROM , cu ch , v cc bit kha thng qua giao din JTAG - h tr vic hiu chnh trn Chip bi AVR studio Tng quan AVR ph hp vi tiu chun IEEE 1149 giao din JTAG c th c s dng cho : - qu trnh kim tra PCBs bng cch s dng kh nng qut bin JTAG - lp trnh cc b nh khng th thay i , cc bit cu ch v bit kha - Qu trnh hiu chnh trn chip Mt s miu t ngn gn c a ra trong cc phn bn di . Cc s miu t chi tit sau cho vic lp trnh giao din JTAG , v s dng chui qut bin c th c tm thy trong phn Programming Via the JTAG Interface trn trang 305 v IEEE 1149.1(JTAG) Boundary scan trn trang 252 . S h tr hiu chnh li trn chip ang c xt n cc lnh JTAG ring , v c phn phi trong khun kh ATMEL v ch c la chn 3 i l cung cp Hnh 120 ch ra mt s khi ca giao din JTAG v h thng hiu chnh li trn chip. B iu khin TAP l mt b my trng thi (state machine ) c iu khin bi cc tn hiu TCK v TMS . B iu khin TAP la chn hoc l thanh ghi lnh JTAG hoc l 1 trong s rt nhiu thanh ghi d liu nh l mt chui qut (Shift Register) gia u vo TDI v u ra TDO . Thanh ghi lnh gi cc lnh JTAG iu khin s tin hnh x l ca mt thanh ghi d liu . Thanh ghi ID , thanh ghi Bypass , v chui qut bin l cc thanh ghi d liu c s dng cho qu trnh kim tra board level .Lp trnh gio din JTAG (thc s bao gm nhiu thanh ghi vt l v thanh ghi d liu o ) c s dng cho lp trnh ni tip thng qua giao din JTAG . Cc chui qut v im dng chui qut bn trong ch c s dng cho vic hiu chnh li trn chip. Cng truy nhp kim tra Test Access Port TAP Giao din JTAG c truy nhp thng qua 4 chn ca AVR . Trong cng ngh ca AVR , cc chn ny cu thnh cng truy nhp kim tra TAP . cc chn l : - TMS : la chn ch kim tra . Chn ny c s dng cho vic nh hng thng qua thit b trng thi b iu khin - TCK : kim tra xung nhp . Hot ng ca JTAG th ng b ha ln chn TCK - TDI : kim tra d liu vo . d liu cng vo ni tip c di chuyn vo trong thanh ghi lnh hoc thanh ghi d liu (chui qut ) - TDO : kim tra d liu ra . D liu u ra ni tip t thanh ghi lnh v thanh ghi d liu Tiu chun IEEE 1149 cng xc nh mt la chn tn hiu TAP , TRST Test ReSeT ci m khng c cung cp .

Khi m cu ch JTAGEN khng c lp trnh , 4 chn TAP ny l chn cng bnh thng v b iu khin TAP th trong ch reset . Khi c lp trnh v bit JTD trong thanh ghi MCUCSR b xa ,cc tn hiu u vo TAP c ko vo trong mc cao v JTAG c kch hot cho chui qut bin (boundary scan ) v qu trnh lp trnh . Trong trng hp ny , u ra TAP l (TDO ) c di chuyn thay i trong trng thi m b iu khin JTAG TAP ang khng di chuyn d liu , v v vy phi c ni n mt in tr pull-up hoc phn cng khc c tnh nng pull-up (chng hn nh u vo TDI ca thit b tip theo trong chui qut ) . Thit b c di chuyn vi cu ch c lp trnh . V h thng sa li trn chip , thm vo ti cc chn giao din JTAG , chn RESET c quan st bi b hiu chnh li c th d ti cc ngun Reset bn ngoi . B hiu chnh li cng c th ko chn RESET xung mc thp reset ton b h thng , gi s rng ch m cc collector trn ng Reset l c s dng trong ng dng ny .

Hnh 121 : s trng thi b iu khin TAP

B iu khin TAP B iu khin TAP l mt c cu trng thi hu hn 16 trng thi m iu khin hot ng ca mch chui qut bin , mch lp trnh JTAG , hoc h thng sa li trn chip . S chuyn i trng thi c m t trong hnh 121 ph thuc vo tn hiu c a ra trn chn TMS (ch ra bn cnh mi s thay i trng thi ) ti thi im ca sn ln TCK . Trng thi khi to sau mt Reset Power-on l Reset kim tra logic Nh c nh ngha trong ti liu ny , LSB c di chuyn vo trong v ra ngoi trc tin cho tt c cc thanh ghi Shift Gi thit rng Run-Test/Idle l trng thi c a ra , Mt chui s kin bnh thng cho vic s dng giao din JTAG l : - Ti u vo TMS , p dng lin tip 1, 1, 0 , 0 ti cc sn ln ca TCK nhp vo thanh ghi lnh Shift Shift - state . Trong khi trong trng thi ny , di chuyn 4 bit ca lnh JTAG vo trong thanh ghi lnh JTAG t u vo TDI ti sn ln cu TCK . u vo TMS phi c gi mc thp trong sut u vo cu 3 LSB theo th t cn li trong trng thi Shift IR . MSB ca lnh c di chuyn trong khi trng thi ny c di chuyn bng cch ci t

TMS mc cao . Trong khi lnh c di chuyn t trong TDI , trng thi IRstate bt c di chuyn ra ngoi trn chn TDO . Lnh JTAG la chn thanh ghi d liu ring nh ng dn gia TDI v TDO v iu khin cc mch xung quanh thanh ghi c la chn - p dng lin tip 1 ,1 ,0 truy nhp li vo trng thi Run-Test/Idle . Lnh c cht trong u ra song song t ng dn thanh ghi Shift trong trng thi Update-IR . Trng thi Exit-IR , Pause IR , v Exit2-IR ch c s dng cho vic nh hng c cu la chn trng thi - Ti u vo TMS , t lin tip 1 , 0 , 0 ti sn ln ca xung TCK truy nhp thanh ghi d liu Shift Shift-DR . Trong trng thi ny , cp nht thanh ghi d liu c la chn (c la chn bng lnh JTAG c a ra trong thanh ghi lnh JTAG )t u vo TDI ti sn ln ca TCK . m gi nguyn trong trng thi Shift-DR , u vo TMS phi c gi thp trong sut u vo ca tt c cc bt ngoi tr MSB . MSB ca d liu c di chuyn trong khi trng thi ny c di chuyn bng vic ci t TMS mc cao . Trong khi thanh ghi d liu c di chuyn khi chn TDI , cc u vo song song n thanh ghi d liu truy bt trong trng thi Capture-DR c di chuyn ra ngoi trn chn TDO - p dng TMS lin tip 1, 1 ,0 truy nhp li trng thi Run-Test/Idle . Nu thanh ghi d liu la chn c mt u ra song song c cht , qu trnh cht s xy ra trong trng thi Update-DR . Cc trng thi Exit-IR , Pause IR , v Exit2-IR ch c s dng cho vic nh hng c cu trng thi . Nh c ch ra trong s trng thi , trng thi Run-Test/Idle khng cn c truy nhp gia vic la chn lnh JTAG v vic s dng cc thanh ghi d liu , v vi lnh JTAG c th la chn cc hm chc chn tin hnh x l trong trng thi RunTest/Idle , lm n khng thch hp nh l mt trng thi Idle Ch : ph thuc vo vic khi to ca b iu khin TAP , trng thi TestLogic-Reset c th lun c truy nhp bng vic gi TMS mc cao trong 5 chu k xung nhp TCK thm thng tin chi tit v cc c im ca JTAG , tham kho thm phn bibliography trang 251 S dng chui qut bin (Boundary scan chain ) Mt s miu t hon thin ca kh nng qut bin c a ra trong phn IEEE 1149.1 (JTAG) Boundary scan . trn trang 252 S dng h thng hiu chnh li trn chip Nh ch ra trong hnh 120 phn cng h tr cho qu trnh hiu chnh li trn chip bao gm cc thnh phn chnh sau : - 1 chui qut (scan chain) trn giao din gia CPU AVR bn trong v cc thnh phn ngoi vi bn ngoi . - Thnh phn im dng (break point ) - Giao din truyn thng gia CPU v h thng JTAG .

Tt c cc qu trnh c hoc sa i /ghi cn thit cho qu trnh thc thi ca b hiu chnh li u c thc hin bng vic t cc lnh AVR thng qua chui qut AVR CPU . CPU gi kt qu n n mt b nh I/O c nh v trong vng nh m l 1 phn ca giao din truyn thng gia CPU v h thng JTAG Thnh phn im dng (Break point ) x l dng trn im thay i ca dng chng trnh , bc dng n , 2 im dng b nh chng trnh , v 2 im dng c ni . Cng vi , 4 im dng cng c th c cu hnh nh sau : - 4 im dng b nh chng trnh n - 3 im dng b nh chng trnh n + 1 im dng b nh d liu n - 2 im dng b nh chng trnh n +2 im dng b nh d liu n - 2 im dng b nh d liu n +1 im dng b nh d liu vi mask (khong im dng ) - 2 im dng b nh d liu n + 1 im dng b nh d liu vi mask (khong im dng ) Mt b hiu chnh li , ging nh AVR studio , tuy c th s dng mt hoc nhiu hn cc ngun ti nguyn cho cc mc ch bn trong n , truyn ti d dng n ngi s dng cui Mt danh sch ca cc c tnh hiu chnh trn chip ca cc lnh JTAG c a ra trong On-chip Debug Specific JTAG Instructions trang 250 Cu ch JTAGEN phi c lp trnh kch hot cng truy nhp kim tra JTAG . Thm vo , cu ch OCDEN phi c lp trnh v khng c bit kha no phi c ci dt cho h thng hiu chnh li trn chp hot ng . Nh mt tnh nng bo mt , h thng sa li trn chip b v hiu ha khi bt c bit kha no c ci t . Ni cch khc , h thng sa li trn chip s cung cp 1 ca sau (back-door) vo trong thit b c nh (secured device ) AVR studio kch hot mt ngi s dng iu khin y qu trnh thc thi ca chng trnh trn mt thit b AVR vi tnh nng sa li trn chip , B m phng mch in trong AVR , hoc b m phng ci t lnh buil-in trong AVR . AVR Studio h tr ngun thc thi ca chng trnh Assembly c thc thi vi Atmel Copporations AVR Assembler v cc chng trnh C trnh bin dch vi trnh cc trnh bin dch Vendor AVR studio chy di cc h iu hnh ca window nh XP , NT , 2000 V mt s miu t y cho AVR Studio , lm n tham kho thm phn hng dn s dng AVR Studio c th tm thy trn mc online help trong phn mm AVR Studio . Ch c cc im quan trng c a ra trong ti liu ny . Tt c cc lnh thc thi cn thit th u c th s dng trong AVR Studio , c hai ngun level v khng phi Assembly . Ngi s dng c th thc thi chng trnh , bc n thng qua on m bng vic v vo trong (tracing) hoc nhy qua cc chc nng , Cc lnh hiu chnh xc nh JTAG trn chip Hiu chnh trn chip h tr c coi nh cc lnh JTAG chuyn dng v c s dng trong khun kh ca ATMEL v la chn third-party vendors . Cc lnh c lit k cho s tham kho PRIVATE0;$8 PRIVATE1;$9 lnh JTAG ring cho s truy nhp h thng hiu chnh li trn chip lnh JTAG ring cho s truy nhp h thng hiu chnh li trn chip

PRIVATE2;$A PRIVATE3;$B

lnh JTAG ring cho s truy nhp h thng hiu chnh li trn chip lnh JTAG ring cho s truy nhp h thng hiu chnh li trn chip

Hiu chnh li trn chp lin quan n thanh ghi trong vng nh I/O Thanh ghi hiu chnh trn chip OCDR Thanh ghi Thanh ghi OCDR cung cp mt knh truyn thng t chng trnh ang chy trong vi iu khin n b hiu chnh li .CPU c th chuyn mt byte d liu n b hiu chnh li bng vic vit ln vng nh ny .Ti cng thi im ny ,mt c bn trong ,thanh ghi hiu chnh I/O diri IDRD- c ci t n b hiu chnh m thanh ghi c vit . Khi CPU t thanh ghi OCDR 7LSP s t thanh ghi OCDR .Trong khi MSB l bt IDRD. B hiu chnh xa bt IDRD khi n va c thng tin Trong mt vi thit b AVR ,thanh ghi ny c chia s vi mt vng nh I/O chun .Trong trng hp ny thanh ghi OCDR c th ch c truy cp nu cu ch ODCEN c lp trnh ,v b hiu chnh kch hot s truy nht n thanh ghi OCDR .Trong tt c cc trng hp khc ,vng nh I/O chun c truy nhp . Tham kho ti liu hng dn s dng b hiu chnh, bit them thng tin v cc s dng thanh ghi ny . S dng tnh nng lp trnh JTAG . Vic lp trnh ca cc phn AVR thng qua giao din JTAG c tin hnh thng qua 4 chan cng JTAG, TCK ,TMS, TDI,TDO. Ch c cc chn cng m cn thit lp trnh tin hnh lp trnh JTAG (thm vo cc chn ngun ). Nu nh khng cn thit t in p 12v bn ngoi .Cu ch JTAGEN phi c lp trnh va bit JTD trong thanh ghi MCUCSR phi c xa kch hot cng truy nhp kim tra JTAG Tnh nng lp trnh JTAG h tr : - Lp trnh Flash v qu trnh phn tch - Lp trnh EEPROM v qu trnh phn tch - Lp trnh cu ch v qu trnh phn tch - Lp trnh bit kha qu trnh phn tch Bt kha an ton th chnh xc nh trong ch lp trnh song song .Nu nh cc bt kha LB1 v LB2 c lp trnh ,cu ch ODCEN khng th c lp trnh tr khi hnh ng u tin ca chip b xa .y l mt c tnh bo mt m m bo rng khng c ca ra back door cho vic c ngoi cc thnh phn ca thit b . Chi tit trn vic lp trnh thng qua giao din JTAG v cc lnh xc nh JTAG c ua ra trong phn Lp trnh thng qua giao din JTAG trang 305. Th mc thm thng tin chung v chui qut bin ,tham kho cc tiu chun sau: IEEE 1149 (JTAG) qut bin

c im - Giao din JTAG (ph hp vi tiu chun IEEE 1149) - Tnh nng qut bin theo chun JTAG - Qut y tt c cc cng chc nng tt nh mch tng t c kt ni Off- chip - H tr la chn lnh IDCODE - Thm vo lnh AVR_RESET reset AVR Tng quan h thng Chui qut bin c tnh nng ca qu trnh iu khin v quan st cc mc logic trn cc chn I/O s. tt nh bin gia cng logic s v tng t cho cc mch tng t c kt ni OFF chip .Ti mc h thng, tt c IC C tnh nng JTAG c ni ni tip vi cc tn hiu TDITDO ti dng mt thanh ghi sip di .Mt b iu khin bn ngoi ci t thit b iu khin gi tr ti cc chn u ra ca chng ,v quan st cc gi tr u vo c nhn t cc thit b khc .B iu khin so snh cc d liu nhn vi cc kt qu mong mun .Theo cch ny chui qut bin cung cp mt cng c cho vic kim tra cc lin kt v cc d liu ca cc thnh phn trn bo mch in bng cch s dng 4 tn hiu TAP 4 tiu chun IEEE 1149.1 xc nh cc lnh JTAG bt buc :IDCODE ,BYPASS,SAMPLE/PRE LOAD,va EXTEST ,nh l nhng lnh thng dng xc nh AVR _RESET c th c s dng cho vic kim tra bo mch in .Khi to mt qu trnh qut ca ng dn thanh ghi d liu s ch ra m ID ca thit b .Do m IDCODE l lnh mch inh ca JTAG .N c th khng c xt n c mt thit b c reset trong ch kim tra .Nu khng reset cc u vo ti thit b c th b kt thc bng qu trnh qut ,v phn mm bn trong c th trong mt trng thi khng xc nh khi thot ra khi ch kim tra .Nhp lnh reset ,cc u vo ca bt c mt chn cng no s truy nhp ngay vo trnh thi tr khng cao, lm cho lnh HIGHZ b tha .Nu cn lnh BYPASS c th c th c ban hnh lm cho chui qut ngn nht c th i qua thit b ,thit b c th ci t trong trng thi reset bng vic ko chn reset ngoi xung mc thp hoc a ra lnh AVR_RESET vi s ci t ca thanh ghi d liu reset Lnh EXTEST c s dng cho cc chn ly mu bn ngoi v cc chn ti d liu ra .D liu t ch cht u ra s c iu khin ra bn ngoi trn cc chn ngay khi lnh EXTEST c ti vo trong thanh ghi IR JTAG .v vy cc lnh SAMPLE /PRELOAD cng nn c s dng cho vic ci t khi to cho cc gi tr n vng qut , trnh s h hng cho bo mch khi a ra lnh EXTEST trong ln u tin. Cc lnh SAMPLE /PRELOAD cng c th c s dng to ra mt snatshot ca cc chn bn ngoi trong sut qu trnh hot ng bnh thng ca cc b phn. Cu ch JTAGEN phi c lp trnh v bt JTD trong thanh ghi I/O MCUCSR phi b c xa kch hot truy nhp kim tra JTAG . Khi s dng giao din JTAG cho vic qut bin ,vic s dng mt tn s xung nhp JTAGTCK cao hn tn s ca chip bn trong l c th c .Xung nhp ca chp th khng th chy . Cc thanh ghi d liu

Cc thanh ghi d liu xc ng cho qu trnh iu khin qut bin l ; - Thanh ghi Bypass - Thanh ghi nhn dng thit b - Thanh ghi Reset - Chui qut bin Thanh ghi Bypass Thanh ghi bypass bao gm 1 cng thanh ghi Shift n . Khi thanh ghi Bypass c la chn nh ng dn gia TDI v TDO , thanh ghi c reset ln 0 khi di chuyn trng thi b iu khin DR-Capture . Thanh ghi bypass c th c s dng rt ngn chui qut trn h thng khi m cc thit b khc c kim tra Thanh ghi nhn dng thit b Hnh 122 ch ra cu trc ca thanh ghi nhn dng thit b Hnh 122 : dng ca thanh ghi nhn dng thit b Version

XXIII . H tr b ti chng trnh mi lp trnh read while write

H tr ti chng trnh mi cung cp 1 c cu lp trnh cho vic cp nht v np ln on m chng trnh bng chnh MCU . c im ny cho php ng dng cc phn mm ng dng cp nht c iu khin bi MCU bng cch s dng mt chng trnh ti chng trnh boot lu tr trong b nh Flash . Chng trnh ti boot c th s dng bt c bt c giao

din d liu kh dng no v giao thc lin kt no c m v vit chng trnh bn trong b nh Flash , hoc c code t

XXIV . Lp trnh b nh - Memory Programming

Cc bit kha d liu b nh v chng trnh

Atmega 128 cung cp 6 bit kha ci m c th ci m khng th lp trnh (1) hoc c th c lp trnh ( 0 ) t c cc c tnh c thm vo nh c lit k trong bng 116 . Cc bit kha ch c th b xa ln 1 vi lnh xa chip chip eraser command

Cc bit cu ch - Fuse bits Atmega 128 c 3 byte cu ch . Bng 117 119 miu t ngn gn chc nng ca tt c cc bit cu ch v cch chng c v bn bn trong bytes cu ch . Ch rng cc cu ch c c nh l mc logic 0 , nu chng c lp trnh .

Trng thi ca cc bit cu ch th khng b nh hng bi lnh xa chip . Ch rng cc bit cu ch b kha nu bit kha 1 (LB1) c lp trnh . Lp trnh cc bit cu ch trc khi lp trnh cc bit kha . Qu trnh cht cc bit cu ch Cc gi tr ca cu ch c cht khi thit b truy nhp vo ch lp trnh v cc thay i gi tr ca cc cu ch s khng c hiu lc cho n khi phn ri khi ch lp trnh . iu ny khng c p dng ln cu ch EESAVE ci m s lm nh hng mi ln n c lp trnh . Cc cu ch th cng b cht power- up trong ch bnh thng

Cc byte k hiu Tt c cc vi iu khin ca Atmel c 3 byte m k hiu ci m dng nhn ra thit b M ny c th c c trong 2 ch ni tip v song song , cng c khi m thit b b kha . 3 bytes ny lu tr trong 1 khng gian a ch ring bit V cho Atmega 128 th cc byte k hiu l : 1. $000:$1E ( chng t rng c thit k bi Atmel ) 2. $001:$97 ( chng t rng c 128KB b nh Flash 0 3. $002:$02( hin th rng thit b l Atmega 128 khi $001 l $97) Byte hiu chnh Calibration Byte Atmega 128 lu 4 gi tr hiu chnh khc nhau cho b to xung nhp RC bn trong . Cc byte ny lu tr trong cc byte k hiu cao ca cc a ch 0x000 , 0x0001, 0x0002 , v 0x0003 cho cc th t nh sn 1 , 2 , 4 , 8 MHz . Trong sut qu trnh Reset , gi tr 1 MHz th t ng c ti vo trong thanh ghi OSCCAL . Nu cc tn s khc c s dng , gi tr hiu chnh phi c ti mt cch thng thng, xem phn thanh ghi hiu chnh b to dao ng OSCCAL trn trang 42 bit thm chi tit . Cc tham s ca qu trnh lp trnh song song , cc chn nh du , v cc lnh Phn ny miu t cch lp trnh song song v kim tra li b nh Flash chng trnh , b nh d liu EEPROM , cc bit kha b nh , v cc bit cu ch trong Atmega 128 . Cc xung c gi nh l di 250ns tr phi c ch khc . Tn cc tn hiu Trong phn ny , vi chn ca Atmega 128 c tham chiu bi cc tn hiu c miu t cc chc nng ca chng trong sut qu trnh song song , xem hnh 135 v bng 120. cc chn th khng c miu t trong bng tip theo c tham chiu bi tn cc chn Cc chn XA1/XA0 xc nh hnh ng c thc thi khi m chn XTAL1 c a ra 1 xung dng . S m ha bit c ch ra trong bng 122 Khi pht xung WR v OE , lnh c ti xc nh hnh ng c thc thi . Cc lnh khc c ch ra trong 123 .

Lp trnh song song

Truy nhp vo ch lp trnh song song Thut ton tip theo,t thit b vo trong ch lp trnh song song: 1. p dng 4,5-5,5V gia chn VCC va chn GND,v i di mc 100micro giy 2. ci t RESET l 0 di chuyn XTAL1 di 6 ln 3. ci t prog_kch hot cc chn c lit k trong bng 121 trang 291 ln gi tr 0000 v i trong khong d 100 nano giy 4. p dng in p 11 n 12,5V ln chn RESET.bt c hnh ng prog no kch hot cc chn trong vng 100nano giy sau khi in p +12v c t ln chn RESET,s gy ra s sai hng ca thit b khi truy nhp vo ch lp trnh. Ch rng,b to xung nhp thch anh bn ngoi hoc b to dao ng RC bn ngoi c la chn,nu n khng th t ln xung chun XTAL1.trong trng hp nh th,thut ton sau y phi c tun theo: 1. t prog_kch hot cc chn bng 291 ln 0000. 2. t in p 4,5-5,5V gia chn VCC v chn GND ng thi nh l in p 11 n 12,5V ln chn RESET. 3. i 100nano giy 4. lp trnh li cc cu ch m bo rng cc xung nhp bn ngoi c la chn nh l cc ngun xung nhp(CKSEL3:0=0b0000) nu cc bit kha c lp trnh,mt lnh xa chip phi c thc thi trc khi thay i cc bit cu ch 5. khi thot ra khi ch lp trnh bng vic tt ngun ca thit b hoc mang chn RESET ln gi tr 0b0 6. truy nhp vo ch lp trnh vi cc thut ton chnh thc nh l c miu t bn di. s xt n ca vic lp trnh lnh ti v cc i ch c lu li trong thit b ny trong sut qu trnh lp trnh. tin cho vic lp trinh,cc bc bn di y nn c xt n - cc lnh ch cn c ti mi ln khi vit hoc c nhiu vng nh khc nhau. - Vic gi qu trnh vit cc gi tr d liu $FF,ci m bao gm cc gi tr c lu tr trong EEPROM( tr phi cu ch EESAVE c lp trnh) v b nh flash sau khi c lnh xa chip. - Cc byte c a ch cao ch cn c load trc khi lp trnh hoc c mt t mi c 256 byte trong b nh flash hoc EEPROM.iu ny cng c xt n c cc byte k hiu. Xa chip Lnh xa chip s xa b nh flash v b nh EEPROM v cc bit kha.cc bit kha th khng c reset cho n khi b nh chng trnh c xo hon ton.cc bit cu ch th khng b thay i.mt lnh xa chip phi c tin hnh trc khi b nh flash hoc EEPROM c lp trnh li.

Ch :b nh EEPROM c phc v trc trong sut qu trnh xa chip nu nh cu ch EESAVE c lp trnh. Qu trnh ti lnh xa chip 1. t XA1,XA0 ln 10.iu ny kch hot vic ti lnh 2. t BS1 l 0 3. t DATA ln 1000 0000.y l lnh xa chip 4. a XTAL1 l mt xung dng.iu ny ti lnh 5. a WR l mt xung m.iu ny bt u lnh xa chip 6.i cho n khi RDY/BSY ln cao trc khi ti mt lnh mi Lp trnh b nh flash B nh flash c t chc theo dng trang,xem bng 123 trang 291.khi lp trnh b nh flash,d liu chng trnh c cht trong b m ca trang.iu ny cho php 1 trang ca d liu chng trnh c lp trnh mt cch ng thi.cc quy trnh sau miu t cch lp trnh cho b nh flash: A.ti lnh vit flash 1.t XA1,XA0 ln 10.iu ny kch hot vic ti lnh 2.t BS1 ln 0 3.t DATA ln 0001 0000.y l lnh cho vic vit flash 4.a XTAL1 ln mt sn dng.iu ny ti lnh B.ti a ch byte thp 1.t XA1,XA0 ln 00.iu ny kch hot vic ti a ch 2.t BS1 la 0.iu ny la chn a ch thp 3.t DATA bng a ch byte thp($00-$FF)a ch thp 4.a XTAL1 ln mt sn dng.iu ny ti cc byte a ch thp C.ti d liu byte thp 1.t XA1,XA0 ln 01.iu ny kch hot vic ti d liu byte thp 2.t DATA bng byte d liu thp 3.a XTAL1 ln mt sn dng.iu ny ti byte d liu D.ti byte d liu cao 1.t BS1 ln 1.iu ny la chn byte d liu cao 2.t XA1,XA0 ln 01.iu ny kch hot vic ti byte d liu cao 3.t DATA bng byte d liu cao.($00-$FF) 4.a XTAL1 ln mt sn dng.iu ny ti byte d liu E.cht d liu 1.t BS1 ln 1.iu ny la chn byte d liu cao 2.a PAGEL ln mt sn dng.iu ny cht cc byte a ch.(xem hnh 137v dng cc sng tn hiu) F.lp li bc B cho n bc E cho n khi b m c in y hoc cho n khi d liu trong trang c ti. Trong khi cac bit thp trong a ch c v bn ln cc t trong mt trang,cc bit a ch cao hn ca trang trong b nh flash.iu ny c minh ha trong hnh 136 trang 294.ch rng nu mt t nh hn 8 bit l cn thit nh a ch t trong trang(PAGE

SIZE<256)c bit c trng s cao trong cc byte c a ch thp c s dng nh a ch cho trang khi tin hnh mt qu trnh vit trang G.ti a ch byte cao 1.t XA1,XA0 ln 00..iu ny kch hot vic ti a ch. 2.t BS1 ln 1.iu ny la chn cc a ch mc cao 3.t DATA bng a ch byte cao ($00-$FF). 4.a XTAL1 ln mt sn dng.iu ny ti cc a ch byte cao. H.lp trnh trang 1.t BS1 =0 2.a WR ln mt sn m.iu ny bt u lp trnh d liu ca trang.RDY/BSY mc thp. 3.i cho n khi RDY/BSY ln cao(xem hnh 137 bit dng tn hiu) I.lp li t bc B n bc H cho n khi b nh c lp trnh hoc cho n khi tt c cc d liu c lp trnh. J.kt thc vic lp trnh trang 1.ci XA1,XA0 ln 10.iu ny kch hot vic ti lnh. 2.t DATA ln 00000000.y l lnh cho khng ch iu khin. 3.a XTAL1 ln mt sn dng.iu ny ti lnh,v cc tn hiu c vit bn trong c reset.

Lp trnh cho EEPROM EEROM c t chc di dng trang nh , xem bng 124 trang 292 . Khi lp trnh cho EEPROM , d liu chng trnh c cht vo bn trong b m trang nh . iu ny cho php 1 trang nh ca d liu c lp trnh mt cch ng thi . Thut ton lp trnhcho b nh d liu EEPROM th c theo nh l (tham kho phn lp trnh Flash trang 293 thm chi tit v cc lnh , a ch v vic ti d liu ): 1. A : ti lnh 0001 0001 2. G : ti a ch Byte cao ($00 - $FF) 3. B : ti a ch Byte thp ($00 - $FF) 4. C : ti d liu ($00 - $FF) 5. E : cht d liu ( a PAGEL 1 xung dng ) K : lp li t bc 3 n bc 5 cho n khi ton b b m c in y . L : chng trnh trang EEPROM 1. t BS1 l 0 2. a WR 1 xung m . iu ny khi ng mt qu trnh lp trnh ca trang nh EEPROM . RDY/BSY a v mc thp 3. i cho n khi RDY/BSY n mc cao trc khi lp trnh trang k tip (xem bng 138 v dng xung tn hiu )

c b nh Flash Thut ton c b nh Flash c cho nh bn di ( tham kho phn lp trnh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0000 0010 2. G : ti a ch Byte cao ($00 - $FF) 3. B : ti a ch Byte thp ($00 - $FF) 4. t OE ln 0 v BS1 ln 0 . Cc byte thp t Flash c th c DATA 5. t BS1 ln 1 . Cc byte cao ca t Flash c th c DATA . 6. t OE ln 1 c b nh EEPROM Thut ton c b nh EEPROM nh l bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0000 0011 2. G : ti a ch Byte cao ($00 - $FF) 3. B : ti a ch Byte thp ($00 - $FF) 4. t OE ln 0 v BS1 ln 0 . Byte d liu EEPROM c th c c ti DATA . 5. t OE ln 1 lp trnh cc bit thp cu ch thut ton lp trnh cho cc bit thp cu ch nh bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0100 0000 2. C : ti byte d liu thp . Bit n = 0 v bit n =1 xa cc bit cu ch .

3. t BS1 ln 0 v BS2 ln 0 4. a vo WR 1 xung m v i cho RDY/BSY ln cao lp trnh cc bit cu ch cao Thut ton cho vic lp trnh cc bit cu ch cao nh bn di (tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A ti lnh 0100 0000 2. C : ti byte d liu thp . Bit n = 0 chng trnh v bit n = 1 xa cc bit cu ch . 3. t BS1 ln 1 v BS2 ln 0 . iu ny la chn byte d liu cao . 4. a vo WR mt xung m v i cho n khi i cho RDY/BSY ln cao 5. t BS1 ln 0 . iu ny la chn Byte d liu thp Lp trnh cc byte cu ch m rng Thut ton cho vic lp trnh cc bit cu ch m rng th nh bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0100 0000 2. C : ti byte d liu thp . Bit n = 0 v bit n = 1 xa bit cu ch 3. t BS1 ln 1 v BS2 ln 0 . iu ny la chn byte d liu cao . 4. a vo WR mt xung m v i cho n khi i cho RDY/BSY ln cao 5. t BS2 ln 0 . iu ny la chn byte d liu .

Lp trnh cc bit kha Thut ton lp trnh cho cc bit kha nh bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0010 0000 2. C : ti cc byte d liu thp . Bit n = 0 lp trnh cc bit kha . 3. a vo WR mt xung m v i cho n khi RDY/BSY ln cao cc bit kha ch c th b xa bng vic thc hin lnh xa chip

c cc bit kha v bit cu ch Thut ton cho vic c cc bit cu ch v cc bit kha nh sau (( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0000 0100 2. t OE ln 0 v BS2 ln 0 , v BS1 ln 0 . Trng thi ca cc bit thp cu ch c th c c by gi ti DATA ( 0 ngha l lp trnh ) 3. t OE ln 0 , BS2 ln 1 , v BS1 ln 1 . Trng thi ca cc bit cu ch cao c th c c by gi ti DATA ( 0 ngha l lp trnh ) 4. t OE ln 0 , BS2 ln 1 , v BS1 ln 0 . Trng thi ca cc bit cu ch m rng c th c c ti DATA ( 0 ngha l lp trnh ) 5. t OE ln 0 , BS2 ln 0 , v BS1 ln 1 . Trng thi ca cc bit kha c th c c ti DATA ( 0 ngha l lp trnh 0 6. t OE l 1

c cc byte k hiu Thut ton cho vic c cc byte k hiu th nh bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A ti lnh 0000 1000 2. B : ti cc a ch Byte thp ($00 - $02) 3. t OE ln 0 v BS1 ln 0 . Cc byte k hiu la chn c th c c ti DATA 4. t OE ln 1 c byte hiu chnh Thut ton dng c cc byte hiu chnh nh bn di ( tham kho phn lp trnh b nh Flash trn trang 293 bit thm chi tit v qu trnh ti lnh v a ch ) 1. A : ti lnh 0000 1000 2. B : ti cc byte a ch thp 3. t OE l 0 v BS1 l 1 . Byte hiu chnh c th c c ti DATA 4. t OE ln 1

Cc thng s lp trnh song song Hnh 141 . gin thi gian lp trnh song song , bao gm b nh thi chung cn thit

Hnh 142 . gin thi gian lp trnh song song , qu trnh ti lin tip vi cc yu cu nh thi

Hnh 143 . gin thi gian ca lp trnh song song , vic c lin tip (trong trang ging nhau ) vi i hi nh thi .

Bng 126 . Cc thng s k thut ca lp trnh song song , VCC = 5V 10%

Qu trnh ti ni tip C hai b nh Flash v EEPROM c th c lp trnh s dng bus SPI ni tip trong khi RESET c ko vo GND . Giao din ni tip th bao gm cc chn ca SCK, MOSI (u vo) v MISO (u ra) . Sau khi RESET mc thp , lnh kch hot lp trnh cn c thc thi trc tin trc khi hot ng lp trnh/xa c th c thc thi . Ch rng, trong bng 127trang 300 , s v bn chn cho lp trnh SPI c lit k . Khng phi tt c cc phn ca cc chn SPI u phc v cho cho giao din SPI bn trong . Ch rng thng qua vic miu t v vic ti ni tip , MOSI v MISO c s dng miu t d liu ni tip vo v d liu ni tip ra mt cch tng ng . Vi Atmega 128 , cc chn ny c maped ln PDI v PDO . Qu trnh v bn chn lp trnh ni tip SPI

Mc d giao din lp trnh SPI s dng trc (re uses) cc module I/O SPI , c mt im khc bit quan trng : cc chn MOSI/MISO m c v bn ln PB2 v PB3 trong module I/O ca SPI th khng c s dng trong giao din lp trnh . thay v , PE0 v PE1 c s dng cho d liu trong ch lp trnh SPI nh c ch ra trong hnh 127

Khi lp trnh EEPROM , 1 chu k t ng xa c xy dng bn trong qu trnh lp trnh t nh thi (seft-timed) ( ch trong ch ni tip ) v khng cn thit thc thi u tin lnh xa chip . Qu trnh xa chp chuyn hng thnh phn ca cc vng nh trong c hai b nh EEPROM trong $FF Ph thuc vo cc cu ch CKSEL , 1 xung nhp c hiu lc phi c a ra . Chu k thp v cao nh nht chou vo xung nhp (SCK ) c xc nh nh di : Thp : > 2 chu k xung nhp CPU cho fCk<12MHz , 3 chu k xung nhp cho fCk <12MHz Cao : > 2 chu k xung nhp CPU cho fCk<12MHz , 3 chu k xung nhp cho fCk <12MHz Thut ton lp trnh ni tip SPI Khi vit d liu ni tip ln Atmega 128 , d liu b xa trn sn ln ca xung SCK Khi c d liu t Atmega 128 , d liu b kha trn sn xung ca SCK . xem hnh 145 v chi tit b nh thi . D lp trnh v kim tra li Atmega 128 trong ch lp trnh ni tip SPI , cc chui k tip sau y c khuyn co ( xem cc dng lnh 4 byte trn bng 145)

1. chui cp in ( Power up sequence )

t ngun in gia VCC v GND trong khi chn RESET v SCK t l 0 . Trong vi h thng , ngi lp trnh khng th m bo rng SCK c gi mc thp trong sut qu trnh cp in . Trong trng hp ny , RESET phi c a vo 1 xung dng trong khong di 2 chu k xung nhp CPU sau khi SCK va c t l 0 Nh mt s la chn s dng tn hiu RESET , chn PEN c th c gi thp trong sut qu trnh Reset bt ngun trong khi SCK t l 0 . Trong trng hp ny , ch c gi tr ca PEN ti reset bt ngun l quan trng . Nu ngi lp trnh khng th m bo rng SCK c gi mc thp trong sut qu trnh cp in (power up) , phng php PEN c th c s dng . Thit b phi c ngt in theo th t bt u qu trnh hot ng bnh thng khi s dng phng php ny . 2 . i trong khong di 20ms v kch hot lp trnh ni tip SPI bng vic gi lnh lp trnh kch hot ni tip ln chn MOSI 3. Cc lnh lp trnh ni tip SPI s khng lm vic nu nh qu trnh truyn thng ra ngoi qu trnh ng b ha . Khi trong ch sync byte th 2 ($53), s phn hi li khi s a ra byte th 3 ca lnh kch hot lp trnh . La chn phn hi l ng hoc sai , tt c 4 byte ca lnh phi c c chuyn pht . Nu $53 khng phn hi li , a chn RESET 1 xung dng v da ra 1 lnh kch hot lp trnh mi . 4. B nh Flash c lp trnh mi trang nh ti mt thi im . C ca trang th c tm thy trong bng 124 trn trang 292 . Trang nh th c ti mt byte ti 1 thi im bng vic cung cp 7 LSB ca a ch v d liu cng vi lnh ti chng trnh trang nh. m bo qu trnh ti ng cc trang nh , cc byte d liu thp phi c ti trc byte d liu cao c p dng cho cc a ch c a ra . Cc trang nh chng trnh c lu tr bng vic ti lnh vit chng trnh trang nh vi 9 MSB ca a ch . Nu qu trnh hi vng khng c s dng, ngi s dng phi i trong khong thi gian tWD_FLASH trc khi a ra trang mi. (xem bng 128) Ch : nu cc lnh khc hn qu trnh hi vng c t trc bt c qu trnh vit no (Flash , EEPROM , cc bit kha , Cu ch ) c hon thnh , c th gy ra s lp trnh khng ng .
5. Mng nh EEPROM th c lp trnh mt byte ti mt thi im bng vic cp

a ch v d liu cng vi lnh vit c chp thun . 1 vng nh EEPROM c xa trc tin mt cch t ng trc khi mt d liu mi c vit . Nu s hi vng khng c s dng , ngi s dng phi i trong khong tWD_EEPROM trc khi xut ra byte trc . ( xem bng 128) . Trong mt thit b c xa , khng c $FF trong cc file d liu cn thit c lp trnh . 6. bt c vng nh no c th c kim tra bng vic s dng cc lnh c , ci m phn hi li thnh phn ti a ch c la chn ti cc u ra ni tip MISO 7. ti phn kt thc ca phn lp trnh , RESET c th c ci t mc cao bt u hot ng bnh thng 8. Power OFF k tip ( nu cn thit ) t chn RESET l 1

Chuyn VCC sang tt ngun S hi vng Flash Khi mt trang nh ang c lp trnh vo trong b nh Flash , vic c mt vng a ch trong trang ang c lp trnh s a ra gi tr $FF . Ti thi im m thit b sn sng cho 1 trang nh mi , gi tr lp trnh s c c mt cch chnh xc . iu ny thng c xc nh khi trang k tip c th c vit . Ch rng ton b trang nh c vit 1 cch ng thi v bt c a ch no trong trang c th c s dng cho s hi vng . S hi vng d liu ca b nh Flash s khng lm vic vi gi tr $FF , v vy khi lp trnh gi tr ny , ngi s dng s phi i trong khong thi gian tWD_FLASH trc khi lp trnh trang k tip . Nh l mt thit b xa chip bao gm $FF trong tt c cc vng a ch , s lp trnh ca a ch m bao gm $FF , c th b gi li . Xem bng 128 v gi tr ca tWD_FLASH S hi vng d liu EEPROM Khi mt byte mi va c vit v ang c lp trnh vo trong EEPROM , vic c cc vng a ch ang c lp trnh s a ra gi tr $FF . Ti thi im m thit b sn sng c lp trnh cho 1 byte mi , gi tr c lp trnh s c c mt cch chnh xc . iu ny thng c xc nh khi byte k tip c th c . iu ny s khng lm vic cho gi tr $FF trong tt c cc vng nh , nhng ngi s dng nn c cc tng sau :Nh l mt thit b xa chp bao gm $FF trong tt c cc vng nh ,vic lp trnh cho cc a ch ny bao gm $FF ,c th c gi .iu ny khng p dng nu nh EEPROM c lp trnh li m thiu thit b xa chp .Trong trng hp ny ,qu trnh hi vng gi liu khng th c s dng cho gi tr $FF ,v ngi s dng s phi i trong khong thi gian tWD_EEPROM trc khi lp trnh byte k tip .Xem bng 128, bit gi tr tWD_EEPROM

Thng s k thut ca lp trnh SPI V thng s k thut ca modun SPI, xem thng s k thut gin thi gian SPI. Lp trnh thng qua giao din JTAG.. Lp trnh thng qua giao din JTAG cn thit iu khin bn chn xc nh JTAG: TCK, TMS, TDI, TDO. Qu trnh iu khin ca chn reset v cc chn ng h l khng cn thit. C th s dng giao din JTAG, cu ch JTAGEN phi c lp trnh. Thit b ny c nn mc nh vi cu ch c lp trnh. Thm vo , bit JTD trong thanh ghi MCUCSR phi c xa. Nh mt s la chn, nu bit JTD c ci t, reset ngoi c th t mc thp. Sau bit JTD c th c xa, sau 2 chu k xung nhp ca chip, v cc chn JTAG th kh dng trong ch lp trnh. iu ny cung cp mt kh nng s dng chn JTAG nh l cc cng thng thng trong ch ang chy trong khi vn cho php lp trnh trong h thng thng qua giao din JTAG. Ch rng k thut ny c th khng c s dng khi dng cc chn JTAG cho ch qut th cp v ch hiu chnh li trn chip. Trong cc trng hp ny cc chn JTAG phi c s dng cho cc chc nng ny.

Nh l c xc nh trong ti liu ny, LSB c nn vo trong v ra ngoi u tin ca thanh ghi Shift. Cc lnh lp trnh xc nh JTAG. Thanh ghi cc lnh th c rng l 4 bit, c h tr ln n 16 lnh. Cc lnh JTAG hu dng th c lit k bn di. Bit OPCODE cho mi lnh c ch ra ng sau cc lnh trong nh dng hex. S miu t cc thanh ghi d liu c la chn nh l mt phn gia cc bit TDI v TDO cho mi lnh. Trng thi Run-Test/idle ca b iu khin TAP c s dng pht ra cc xung nhp bn trong. N cng c th c s dng nh trng thi IDLE gia cc JTAG ni tip. Cc my pht trng thi k tip cho s thay i cc t lnh c ch ra trong hnh 146.

AVR_RESET ( $C).

AVR xc nh cc lnh JTAG chung cho vic ci t cc thit b AVR trong ch reset hoc a cc thit b ra khi ch reset. B iu khin TAP th khng c reset bng lnh ny. Mt thanh ghi reset c la chon nh l mt thanh ghi d liu. Ch rng lnh reset ny s hot ng ch cn c mt mc logic 1 trn chn RESET chain. u ra t chain ny th khng b cht. Cc trng thi hot ng l: - Shift-DR: Thanh ghi reset c Shift bi u vo TCK. PROG_ENABLE ($4) AVR xc nh lnh JTAG chung kch hot lp trnh thng qua cng JTAG. Thanh ghi kch hot lp trnh 16 bit c la chn nh l thanh ghi d liu. Cc trng thi hot ng th c ch ra nh bn di: - Shift-DR: Tn hiu kch hot lp trnh c Shift bn trong thanh ghi d liu. - Update DR: Tn hiu kch hot lp trnh c so snh vi gi tr chun, v ch lp trnh c truy nhp nu nh tn hiu ca n c hiu lc. PROG_COMMANDS ($5) AVR xc nh cc lnh JTAG truy nhp cc lnh lp trnh thng qua cng JTAG. Thanh ghi lnh lp trnh 15 bit c la chn nh l thanh ghi d liu. Cc trng thi hot ng c lit k nh bn di: -Capture-DR: Kt qu ca lnh trc c ti vo thanh ghi d liu -shift DR: Thanh ghi d liu c Shift bi u vo TCK, c nn vo kt qu ca lnh trc v nn vo lnh mi -Update-DR: Lnh lp trnh c t vo cc u vo flash - Run-Test/idle: Mt chu k xung nhp c pht ra, ang thc thi mt lnh c p dng. PROG_PAGELOAD ($6) AVR xc nh cc lnh JTAG chung ti trc tip trang d liu flash thng qua cng JTAG. Thanh ghi ti trang flash o bit 2048 c la chn nh l mt thanh ghi d liu. y l mt vng qut o vi di bng s th t ca cc bit trong trang flash. Bn trong thanh ghi shift l 8 bit. Khng ging nh tt c cc lnh trong JTAG, trng thi Capture-DR khng c s dng chuyn d liu vo thanh ghi shift. D liu t ng c chuyn t cc bite b m trang flash bng bite trong trng thi shift DR bng mt my to xung trng thi bn trong. y ch l cc trng thi: - Shift-DR: D liu flash c nn vo trong t TDI bng u vo TCK, v t ng c ti vo trong trang flash mi bite 1 ln. Ch : Lnh JTAG,PROG_PAGELOAD ($6) ch c th c s dng nu thit b AVG l thit b u tin trong chui qut JTAG. Nu nh AVG khng th l thit b u tin trong chui qut, bite-wise thut ton lp trnh phi c s dng.

PROG_PAGEREAD ($7). -AVR xc nh cc lnh JTAG chung c mt trang d liu flash y thng qua cng JTAG. Thanh ghi c trang flash o 2056 bite c la chon nh mt thanh ghi trang thi. y l mmotj chui qut o vi di bng s lng cc bit trong mt trang flash. Bn trong thanh ghi shift l 8 bit. Khng ging nh hu ht cc lnh JTAG khc, trng thi capture-DR khng uwocj s dng chuyn d liu vo thanh ghi shift. D liu th c t ng chuyn t b m trang flash bng bite trong trng thi shift-DR bng mt my pht trng thi bn trong. y ch l cc trng thi haotj ng: - Shift-DR: D liu flash c t ng c mi bite mt ln v c nn ra ngoi trn chn TDO bng u vo TCK. u vo TDI c b qua. Cc thanh ghi d liu Cc thanh ghi d liu c la chn bng cc thanh ghi lnh JTAG c miu t trang 305. Cc thanh ghi d liu hu ch cho hot ng lp trnh l: - thanh ghi reset - Thanh ghi kch hot lp trnh - Thanh ghi lnh lp trnh - Thanh ghi ti trang flash o - Thanh ghi c trang flash o Thanh ghi reset - Thanh ghi reset l mt thanh ghi kim tra d liu c s dng reset mt b phn trong sut qu trnh lp trnh. N th cn thit reset mt b phn trc khi truy nhp vo ch lp trnh. - Mt gi tr cao trong thanh ghi reset tng ng ko reset bn ngoi xung mc thp. Phn ny dc reset ch cn c mt gi tr cao a ra trong thanh ghi reset. S ph thuc vo s ci t bit cu ch cho s la chn xung nhp, b phn cn li s reset cho mt chu k reset time out (Tham kho trang 37 ) sau khi gii phng thanh ghi reset. u ra t thanh ghi d liu ny khng b cht, v vy qu trnh reset s xy ra ngay lp tc nh c ch ra trong hnh 123 trang 254. Thanh ghi kch hot chng trnh.

Thanh ghi kch hot chng trnh l mt thanh ghi 16 bit. Thnh phn ca thanh ghi ny c so snh vi tn hiu kch hot lp trnh, m nh phn 1010_0011_0111_0000. Khi cc thnh phn ca thanh ghi ny bng vi tn hiu kch hot lp trnh, lp trnh thng qua cng JTAG c kch hot. Thanh ghi c reset v khng trong ch reset power on, v nn lun lun c reset khi ri khi ch lp trnh.

Thanh ghi lnh lp trnh Thanh ghi lnh lp trnh l mt thanh ghi 15 bit. Thanh ghi ny c s dng nn lin tip trong cc lnh lp trnh, v c nn ra ngoi lin tip cho kt qu ca cc lnh pha trc. Lnh lp trnh JTAG c ci t nh c ch ra trong bng 130. Trng thi k tip khi ang shift cc lnh lp trnh c minh ha trong cc hnh 149.

Thanh ghi ti trang flash o. Thanh ghi ti trang flash o l mt chui qut o vi di bng s lng cc bit trong mt trang flash. Thanh ghi shift bn trong l 8 bit, v d liu c chuyn mt cch t ng n bite b m trang flash bng bite. Shift vo trong tt c cc t lnh trong mt trang, vic bt u cc bit LSB ca mt lnh u tin trong mt trang v kt thc vi bit MSB ca lnh cui cng trong trang. iu ny cung cp mt cch thun tin ti trn vn b m trang flash trc khi vic thc thi lnh vit trang.

Thanh ghi c trang flash o. Thanh ghi c trang flash o l mt chui qut o vi di bng s lng cc bit trong mt trang flash thanh ghi shift bn trong l 8 bit, v d liu c chuyn mt cch t ng n bite b m trang flash bng bite. 8 chu k u tin c s dng chuyn bite u tin vo trong thanh ghi shift, v cc bit m c shift ra ngoi trong sut trong 8 chu k nn c b qua. Tip theo qua trnh khi to ny, d liu c shift li bt u bite LFB ca lnh u tin trong trang v kt thc vi lnh MSb ca lnh cui cng trong trang. iu ny cung cp mt cch thun tin c mt chng trnh trong trang flash.

Thut ton lp trnh Tt c cc mu tham kho bn di ca loi 1a , 1b , tham kho trang 130 S truy nhp vo ch lp trnh

1. Nhp lnh JTAG AVR_RESET v di chuyn 1 trong thanh ghi Reset . 2. Nhp lnh PROG_ENABLE v di chuyn 1010_0011_0111_0000 trong thanh ghi kch hot lp trnh S di khi ch lp trnh 1. nhp lnh JTAG PROG_COMMANDS 2. V hiu ha tt c cc lnh lp trnh bng vic s dng lnh khng hot ng 11a 3. nhp lnh PROG_ENABLE v di chuyn 0000_0000_0000_0000 trong thanh ghi kch hot lp trnh 4. nhp lnh JTAG AVR_RESET v di chuyn 0 trong thanh ghi Reset Tin hnh vic xa chip 1. nhp lnh JTAG PROG_COMMANDS 2. bt u xa chip s dng lnh lp trnh 1a 3. kim tra vng ca vic xa chip s dng lnh lp trnh 1b , hoc i cho tvWLRH_CE ( tham kho bng ch trn trang 299) Lp trnh FLASH Trc khi lp trnh Flash 1 xa chip (the Flash a chip erase ) phi c tin hnh . Xem vic tin hnh xa trn 315 1. nhp lnh JTAG PROG_COMMANDS 2. kch hot s ghi Flash s dng lnh lp trnh 2a 3. ti byte a ch cao s dng lnh lp trnh 2b 4. ti byte a ch thp s dng lnh lp trnh 2c 5. ti d liu s dng lnh lp trnh 2d , 2e , v 2f 6. lp li bc 4 v 5 cho tt c cc t lnh trong trang 7. vit trang s dng lnh lp trnh 2g 8. hi vng cho s hon thnh ghi Flash s dng lnh lp trnh 2h , hoc i cho tWLRH (tham kho bng ch : trn trang 299) 9. lp li bc 3 n 7 cho n khi tt c cc d liu c lp trnh Mt s chuyn pht d liu hiu qu hn c th c s dng t c bng vic s dng lnh PROG_PAGELOAD : 1. nhp lnh JTAG PROG_COMMANDS 2. kch hot vic ghi Flash bng vic s dng lnh lp trnh 2a 3. ti a ch trang s dng lnh lp trnh 2b v 2c . PCWORLD ( tham kho bng 123 trang 291) c s dng nh a ch trong vng 1 trang v phi c ghi l 0 4. nhp lnh JTAG PROG_PAGELOAD 5. ti ton b trang bng vic di chuyn trong tt c cc t lnh trong trang , bt u vi LSB ca lnh u tin trong trang v kt thc vi MSB ca lnh cui cng trong trang 6. nhp lnh JTAG PROG_COMMANDS 7. vit trang s dng lnh lp trnh 2g

8. hi vng ghi Flash hon thnh bng vic s dng lnh lp trnh 2h , hoc i tWLRH

(tham kho bng ch trn trang 299) 9. lp li t bc 3 n bc 8 cho n khi tt c d liu c lp trnh . Vic c d liu Flash 1. Nhp lnh JTAG PROG_COMMANDS 2. Kch hot c Flash s dng lnh lp trnh 3a 3. ti a ch s dng lnh lp trnh 3b v 3c 4. c d liu s dng lnh lp trnh 3d 5. lp li t bc 3 v 3 cho n khi tt c d liu c c Mt s chuyn pht d liu hiu qu hn c th t c bng vic s dng PROG_PAGELOAD : 1. nhp lnh JTAG PROG_COMMANDS 2. kch hot c Flash s dng lnh lp trnh 3a 3. ti a ch trang bng cch s dng lnh lp trnh 3b v 3c . PRWORD (tham kho bng 123 trang 291 ) c s dng n a ch trong vng 1 trang v phi c ghi l 0 4. nhp lnh JTAG PROG_PAGEREAD 5. c ton b trang bng vic di chuyn ra ngoi tt c cc t lnh trong trang , bt u vi LSB ca lnh u tin trong trang v kt thc vi MSB ca lnh cui cng trong trang . Nh rng 8 bit u tin c di chuyn ra ngoi nn c b qua . 6. nhp lnh JTAG PROG_COMMANDS 7. lp li bc 3 n 6 cho n khi tt c d liu c lp trnh Lp trnh EEPROM Trc khi lp trnh EEPROM 1 s xa chip phi c tin hnh . Xem phn performing chip erase trn trang 315 1. nhp lnh JTAG PROG_COMMANDS 2. kch hot vit EEPROM bng vic s dng lnh lp trnh 4a 3. ti byte a ch cao s dng lnh lp trnh 4b 4. ti byte a ch thp s dng lnh lp trnh 4c 5. ti d liu s dng lnh lp trnh 4d v 4e 6. lp li bc 4 v 5 cho tt c cc byte d liu trong trang 7. vit d liu s dng lnh lp trnh 4f 8. hi vng hon thnh vic vit EEPROM s dng lnh lp trnh 4g , hoc i tWLRH (tham kho bng ch : trn trang 299) 9. lp li cc bc t 3 n 8 cho n khi tt c d liu c lp trnh ch rng lnh PROG_PAGELOAD khng th c s dng khi lp trnh EEPROM c EEPROM 1. Nhp lnh JTAG PROG_COMMANDS 2. Kch hot c EEPROM s dng lnh lp trnh 5a

3. Ti a ch s dng cc lnh lp trnh 5b v 5c 4. c d liu s dng lnh lp trnh 5d 5. Lp li bc 3 v 4 cho n khi tt c d liu c c Ch rng lnh PROG_PAGELOAD khng th c s dng khi c EEPROM Lp trnh cc cu ch 1. Nhp lnh JTAG PROG_COMMANDS 2. Kch hot ghi Cu ch s dng lnh lp trnh 6a 3. Ti byte d liu s dng lnh lp trnh 6b . Mt gi tr bit ca 0 s lp trnh cu ch tng ng . Mt gi tr 1 s lp khng lp trnh cu ch 4. Vit byte cu ch m rng s dng lnh lp trnh 6c 5. Hi vng cho vic ghi cu ch hon thnh s dng lnh lp trnh 6d , hoc i tWLRH (tham kho bng ch trn trang 299) 6. Ti byte a ch s dng lnh lp trnh 6e . Mt gi tr bit ca 0 s lp trnh cu ch tng ng , mt gi tr 1 s khng lp trnh cu ch 7. Vit cu ch byte cao s dng lnh lp trnh 6f 8. Hi vng vic hon thnh ghi cu ch s dng lnh lp trnh 6g , hoc i tWRLH (tham kho bng ch trn trang 299) 9. Ti byte d liu s dng cc lnh lp trnh 6h . Mt gi tr 0 s lp trnh cu ch , mt gi tr 1 s khng lp trnh cu ch 10.Vit byte thp cu ch s dng lnh lp trnh 6i 11. Hi vng hon thnh vic ghi cu ch s dng lnh lp trnh 6j , hoc i tWRLH (tham kho bng ch trn trang 299) Lp trnh cc bit kha 1. Nhp lnh JTAG PROG_COMMANDS 2. Kch hot ghi cc bit kha s dng lnh lp trnh 7a 3. Ti d liu s dng lnh lp trnh 7b , Mt gi tr ca 0 s lp trnh bit kha tng ng , mt gi tr 1 s di chuyn bit kha khng c np 4. Vit cc bit kha s dng lnh lp trnh 7c 5. Hi vng cho vic hon thnh ghi bit kha s dng lnh lp trnh 7d , hoc i tWRLH (tham kho bng ch trang 299) c cc bit cu ch v cc bit kha 1. Nhp lnh JTAG PROG_COMMANDS 2. Kch hot c bit cu ch/bit kha s dng lnh lp trnh 8a 3. c tt c cc bit cu ch v bit kha s dng lnh lp trnh 8f Ch c cc bit cu ch m rng s dng lnh lp trnh 8b Ch c cc byte cao cu ch , s dng lnh lp trnh 8c Ch c cc byte cu ch thp s dng lnh lp trnh 8d Ch c cc bit kha , s dng lnh lp trnh 8e

c cc byte k hiu 1. 2. 3. 4. 5. Nhp lnh JTAG PROGCOMMANS Kch hot c cc byte k hiu s dng lnh lp trnh 9a Ti a ch $00 s dng lnh lp trnh 9b c byte k hiu u tin s dng lnh lp trnh 9c Lp li t bc 3 v 4 vi a ch $01 v $02 c byte k hiu th 2 v 3 mt cch tng ng

c byte hiu chnh 1. 2. 3. 4. Nhp lnh JTAG PROG_COMMANDS Kch hot vic c byte hiu chnh s dng lnh lp trnh 10a Ti a ch $00 s dng lnh lp trnh 10b c byte hiu chnh s dng lnh lp trnh 10c

XXV . Cc c tnh in
Ch : cc gi tr thng thng cha trong data sheet ny c xy dng trn c s s m phng v cc c tnh ca vi iu khin AVR c ch to trn cc qu trnh cng ngh ging nhau . Cc gi tr Min v Max s c th s dng sau khi thit b c tiu chun ha Ch s cc i tuyt i

Thng bo : cc gi tr ngoi gii hn c lit k trong Bng ch s cc i tuyt i bn di c th gy ra hng hc vnh vin cho thit b . y ch l mt gi tr gii hn v chc nng iu khin ca thit b ti cc iu kin ny hoc cc iu kin khc bn ngoi cc thng s sau th khng c s dng . S a ra ca cc iu kin ch s cc i tuyt i cho chu k m rng c th nh hng n cc thit b lin quan .

Ch : 1. Max c ngha l gi tr cao nht chn c m bo c c nh l mc thp

2. Min ngha l gi tr thp nht m chn c m bo c c nh l mc cao 3. Mc d mi cng I/O c th tn nhit nhiu hn iu kin kim nh ( 20 mA at VCC = 5V, 10 mA at VCC = 3V) di cc iu kin trng thi n nh ( khng c qu ) , cc iu bn di y phi c quan st : 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. 4. Mc d mi cng I/O c th tn nhit nhiu hn iu kin kim nh ( 20 mA at VCC = 5V, 10 mA at VCC = 3V) di cc iu kin trng thi n nh ( khng c qu ) , cc iu bn di y phi c quan st : 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA. 5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. dc tc Hnh 152 : Tn s cc i v VCC

Dng xung iu khin xung nhp bn ngoi

iu khin xung nhp bn ngoi

Bng 132 : b to dao ng RC bn ngoi , tn s thng thng Thng s k thut ca giao din 2 dy ni tip Bng 133 miu t cc thit b cn thit kt ni vi bus 2 dy ni tip . Giao din 2 dy ni tip ca Atmega 128 bng hoc vt qu cc yu cu ny di cc iu kin c ch . Cc k hiu thi gian c tham chiu n bng 154

Ch : 1. trong Atmega 128 , tham s ny c chun ha v khng c kim tra 100% 2. ch cn thit cho fSCL >100 kHZ 3. Cb = in dung ca mt ng line trong pF 4. cc yu cu ny phi c p dng cho tt c cc qu trnh iu khin giao din 2 dy ni tip cho Atmega 128 5. fCK = tn s xung nhp CPU 6. chu k thp tht s sinh ra bi giao din 2 dy ni tip Atmega 128 th (1/fSCL 2/fCK ) d cho fCK phi ln hn 6 MHz cho thi gian cn thit t n fSCL = 100kHZ 7. cc chu k thp tht s c sinh ra bi giao din ni tip ca Atmega 128 l (1/fSCL 2/fCK ) d cho thi gian thp cn thit s khng c gp chnh xc cho fSCL >308kHz . cc thit b Atmega 128 c kt ni n bus c th giao tip tt c cc tc (400kHz) vi cc thit b Atmega 128 khc , tt nh bt c cc thit b khc vi bn thn tLOW

Cc c tnh ca b nh thi SPI

Hnh 155 : cc iu kin cn ca giao din SPI (ch Master )

Hnh 156 : cc iu kin cn ca giao din SPI (ch Slave )

Cc ch s ADC Bng 135 : cc ch s ADC , cc knh single ended

Bng 136 : cc ch tiu ADC , cc knh ring bit

S nh thi b nh d liu bn ngoi Bng 137: cc ch s b nh d liu bn ngoi , 4,5 n 5,5 V , khng c trng thi ch

Bng 138 cc ch tiu b nh d liu bn ngoi , 4,5 -5,5 V , 1 chu k trng thi ch

Bng 139 : ch s b nh d liu bn ngoi , 4,5-5,5 V , SRWn1 =1 , SRWn0 =0

Bng 140 : cc ch s b nh d liu bn ngoi 4,5 5,5V , SRWn1 =1 , SRWn0 =1

Bng 141 : ch s b nh d liu ngoi , 2,7 5,5 V , khng c trng thi ch

Bng 142 : cc ch s b nh d liu bn ngoi , 2,7 5,5 V SRWn1 =1 , SRWn0 =1

Bng 143 : cc ch s b nh d liu bn ngoi ,2,7 5,5 V SRWn1 =1 , SRWn0 =0

Bng 144 : cc ch s b nh d liu bn ngoi ,2,7 5,5 V SRWn1 =1 , SRWn0 =0

Hnh 157 : gin thi gian b nh d liu bn ngoi (SRWn1 = 0 , SRWn0 = 0

Hnh 158 : gin thi gian ca b nh bn ngoi (SRWn1 = 0 , SRWn0 = 0 )

Hnh 159 : gin thi gian b nh bn ngoi (SRWn1 = 0 , SRWn0 = 0 )

Hnh 160 : gin thi gian b nh bn ngoi (SRWn1 = 0 , SRWn0 = 0 )

Cc ch s thng thng Cc th di y ch ra cc x l thng thng . Cc hnh ny khng c kim tra trong sut qu trnh sn xut . Tt c cc php o dng in tn hao c tin hnh vi tt c cc chn I/O c cu hnh nh l cc u ra v vi cc xung ln bn trong (Pull ups) kch hot . Mt my pht sng dng sin vi u ra rail to rail c s dng nh l mt ngun pht xung nhp . Cng sut tn hao trong ch Power down th ph thuc vo s la chn xung nhp Cc dng in tn hao th l 1 hm ca nhiu bin t l nh l : in p hot ng , tn s iu khin , ti trn cc chn I/O , tc chuyn mch ca cc chn I/O , on m c thc thi v nhit lm vic , cc h s u th ang iu khin in p v tn s Dng in ko t cc chn ti dung khng c th c c lng (cho mt chn ) nh l CL*VCC*f CL = in dung ti , Vcc = in p hot ng v f = tn s chuyn mch trung bnh ca chn I/O Cc phn c k hiu quy c ti nhng tn s cao hn nhng gii hn kim tra . Cc phn th khng c m bo cho cc chc nng thng thng ti cc tn s cao hn th t cc m hin th

S khc nhau gia dng in tn hao trong ch Power down vi cc timer watchdog kch hot v ch Power-down vi cc Timer Watchdog v hiu ha a ra cc dng in khc nhau c ko bi Timer Watchdog Dng in ngun cp hot ng (Active Supply Current ) Hnh 161 : dng in cung cp hot ng v tn s (0.1 1.0 MHz)

Hnh 162 : dng in cung cp hot ng v tn s (1 20 MHz)

Hnh 163 : dng in cung cp hot ng v VCC (b to dao ng RC bn trong , 1MHz)

Hnh 164 : dng in cung cp hot ng v VCC (b to dao ng RC bn trong, 2MHz )

Hnh 165 : dng in cung cp ti bn trong v VCC (b to dao ng bn trong 4MHz)

Hnh 166 : dng in cung cp ti hot ng v VCC (b to dao ng bn trong 8MHz)

Hnh 167 : dng in cung cp hot ng v VCC (32kHz b to dao ng bn ngoi )

Dng in cung cp Idle (Idle supply current ) Hnh 168 : dng in ngun cp Idle v tn s (0,1 1,0MHz)

Hnh 169 : dng in ngun cp Idle v tn s (1-20MHz)

Hnh 170 : dng in ngun cp Idle v VCC ( b to dao ng RC bn trong , 1MHz)

Hnh 171 : dng in ngun cp Idle v VCC(b to dao ng RC bn trong 2MHz)

Hnh 172 : dng in ngun cp Idle v VCC(b to dao ng RC bn trong 4MHz)

Hnh 173 : dng in ngun cp Idle v VCC(b to dao ng RC bn trong 8MHz)

Hnh 174 : dng in ngun cp Idle v VCC (b to dao ng ngoi 32kHz )

Dng in ngun cp Power-down (Power down Supply Current )

Hnh 175 : dng in ngun cp Power down v VCC (Timer watchdog b v hiu ha )

Hnh 176 : dng in ngun cp Power down v VCC (Timer watchdog kch hot )

Dng in ngun cp Power save (Power save supply current ) Hnh 177 : dng in ngun cp Power save v VCC (Timer watchdog b v hiu ha )

Dng in ngun cp Stanby (Standby supply current ) Hnh 178 : Dng in ngun cp Stanby v VCC

Hnh 179 : Dng in ngun cp Stanby v VCC (CKOPT lp trnh )

Chn pull up

Hnh 180 dng in in tr Pull up chn I/O v in p u vo (VCC = 5V )

Hnh 181 : dng in in tr Pull up chn I/O v in p u vo (VCC = 2,7V )

bn b iu khin chn Hnh 182 : dng din ngun chn I/O v in p u ra (VCC = 5V)

Hnh 183 . dng in ngun chn I/O v in p u ra (VCC = 2,7V)

Hnh 184 : dng in tn chn I/O v in p u ra (VCC =5V)

Hnh 185 : dng in tn chn I/O v in p u ra , VCC = 2.7 V

Cc ngng gii hn chn v s tr t

Hnh 186 : in p ngng gii hn u vo chn I/O v Vcc (VIH , c chn I/O nh l 1)

Hnh 187 : in p ngng u vo chn I/O v VCC (VIH , c chn I/O nh l 0)

Hnh 188 : tr u vo chn I/O v VCC

Ngng BOD v b so snh tng t Offset Hnh 189 : ngng BOD v nhit (BODLEVEL l 4 V )

Hnh 190 : ngng BOD v nhit (BODLEVEL l 2.7V )

Hnh 191 : in p bandgap v in p iu khin

Tc ca b to dao ng bn trong Hnh 192 : tn s b to dao ng watchdog v VCC

Hnh 193 : tn s b to dao ng RC 1MHz hiu chnh v nhit

Hnh 194 : tn s b to dao ng RC 1MHz hiu chnh v VCC

Hnh 195 : tn s b to dao ng RC 1MHz v gi tr Osccal

Hnh 196 : tn s b to dao ng RC 2MHz hiu chnh v nhit

Hnh 197 : : tn s b to dao ng RC 2MHz hiu chnh v VCC

Hnh 198 : tn s b to dao ng RC 2MHz v gi tr Osccal

Hnh 199 : tn s b to dao ng RC 4MHz hiu chnh v nhit

Hnh 200 : tn s b to dao ng RC 4MHz hiu chnh v VCC

Hnh 201 : tn s b to dao ng RC 4MHz v gi tr Osccal

Hnh 202 : tn s b to dao ng RC 8MHz hiu chnh v nhit

Hnh 203 : tn s b to dao ng RC 8MHz hiu chnh v VCC

Hnh 204 : tn s b to dao ng RC 8MHz v gi tr Osccal

Dng in tn hao ca cc thnh phn ngoi vi Hnh 205 : dng in my d yu ngun in v VCC

Hnh 206 : dng in ADC v AVCC (ADC 50kHz)

Hnh 207 : dng in ADC v AVCC (ADC 1 MHz )

Hnh 208 : dng in b so snh tng t v VCC

Hnh 209 : dng in lp trnh v VCC

Dng in tn hao trong khi reset v rng xung reset Hnh 210 : dng in ngun cp Reset v VCC (0,1 1,0 MHz k, ;bao gm dng in thng qua chn reset pull-up )

Hnh 211 : dng in ngun cp Reset v VCC (1 20 MHz , bao gm dng in thng qua chn Reset pull- up )

Hnh 212 : dng in in tr pull-up Reset v in p chn reset (VCC = 5.0 V )

Hnh 213 : dng in in tr pull-up Reset v in p chn reset (VCC = 2.7 V )

Hnh 214 : in p ngng u vo Reset v VCC (VIH , c chn Reset l 1)

Hnh 215 : in p ngng u vo Reset v VCC (VIL , c chn Reset l 0)

Hnh 216 : tr chn u vo Reset v VCC

Hnh 217 : rng xung Reset v VCC (xung nhp bn ngoi , 1MHz)

Bng k chi tit thanh ghi