Giao Trinh Vi Dieu Khien Pic 16F877A

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MC LC
CHNG 1: TNG QUAN V VI IU KHIN PIC 16F877A..................2
1. TNG QUAN V H VI IU KHIN PIC.....................................................................2 2. GII THIU V PIC16F8XX v PIC16F877A...................................................................4
CHNG 2: T CHC B NH - CC THANH GHI CHC NNG......6

2.1. S CHN VI IU KHIN PIC16F877A................................................................7 2.2. MT VI THNG S V VI IU KHIN PIC16F877A............................................9 2.3. S KHI VI IU KHIN PIC16F877A.................................................................11 2.4. T CHC B NH..........................................................................................................12 2.4.1. B NH CHNG TRNH.................................................................................12 2.4.2. B NH D LIU...............................................................................................13 2.5. CC THANH GHI NNG C BIT ...........................................................................14 2.6. STACK................................................................................................................................16
CHNG 3: TP LNH - CU TRC CHNG TRNH..........................17

3.1. TP LNH..........................................................................................................................17 3.1.1. NHM LNH DI CHUYN ................................................................................17 3.1.2. NHM LNH S HC........................................................................................18 3.1.3. NHM LNH LOGIC ..........................................................................................19 3.1.4. NHM LNH R NHNH..................................................................................22 3.2. TO TR BNG DNG LP..........................................................................................25 3.3. CU TRC CHNG TRNH.........................................................................................26 3.4. CC KHI GIAO TIP.....................................................................................................31 3.4.1. GIAO TIP VI LED 7 OAN............................................................................31 3.4.2 GIAO TIP VI BN PHM HEX.......................................................................35 3.4.3 GIAO TIP VI LED MA TRN.........................................................................37 3.4.4 GIAO TIP VI LCD............................................................................................40
CHNG 4: CC KHI CHC NNG........................................................46

4.1.B NH THI................................................................................................................46 4.1.1. TIMER 0...................................................................................................................46 4.1.2. TIMER1....................................................................................................................49 4.1.3. TIMER2....................................................................................................................52 4.2. ADC ...................................................................................................................................53 4.3.PMW_ IU CH RNG XUNG..............................................................................58
CHNG 5: CNG NI TIP.......................................................................67

5.1. USART................................................................................................................................67 5.2.CH LM VIC...........................................................................................................68 5.2.1. TRUYN D LIU BT NG B....................................................................68 5.2.2. NHN D LIU BT NG B........................................................................71
CHNG 6: NGT INTERRUPT..............................................................80

6.1 KHI NIM.........................................................................................................................80 6.2 NGT RB0...........................................................................................82 6.3. NGT PORTB......................................................................................84 6.4. NGT TIMER.......................................................................................85 6.5. NGT ADC..........................................................................................86 6.6. NGT PORT NI TIP..........................................................................88 * PH LC: GII THIU LP TRNH CCS...................................94
* PH LC: CC THANH GHI CHC NNG..............................105
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CHNG 1
TNG QUAN V VI IU KHIN PIC

1.1. TNG QUAN V H VI IU KHIN PIC PIC l mt h vi iu khin RISC c sn xut bi cng ty Microchip Technology. Dng PIC u tin l PIC1650 c pht trin bi Microelectronics Division thuc General_Instrument. PIC bt ngun t ch vit tt ca Programmable Intelligent Computer (My tnh kh trnh thng minh) l mt sn phm ca hng General Instruments t cho dng sn phm u tin ca h l PIC1650. Lc ny, PIC 1650 c dng giao tip vi cc thit b ngoi vi cho my ch 16 bit CP1600, v vy, ngi ta cng gi PIC vi tn Peripheral Interface Controller (B iu khin giao tip ngoi vi). CP1600 l mt CPU tt, nhng li km v cc hot ng xut nhp, v v vy PIC 8-bit c pht trin vo khong nm 1975 h tr hot ng xut nhp cho CP1600. PIC s dng microcode n gin t trong ROM, v mc d, cm t RISC cha c s dng thi by gi, nhng PIC thc s l mt vi iu khin vi kin trc RISC, chy mt lnh mt chu k my (4 chu k ca b dao ng). Nm 1985 General Instruments bn b phn vi in t ca h, v ch s hu mi hy b hu ht cc d n lc qu li thi. Tuy nhin, PIC c b sung EPROM to thnh 1 b iu khin vo ra kh trnh. Ngy nay rt nhiu dng PIC c xut xng vi hng lot cc module ngoi vi tch hp sn (nh USART, PWM, ADC), vi b nh chng trnh t 512 Word n 32K Word. 1.1.1 Mt s c tnh ca Vi iu khin PIC Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng chng ta c th im qua mt vi nt nh sau :
8/16 bit CPU, xy dng theo kin truc Harvard c sa i Flash v ROM c th tu chn t 256 byte n 256 Kbyte Cc cng Xut/ Nhp (I/ O) (mc logic thng t 0V n 5.5V, ng vi logic 0 v logic 1) 8/16 bit Timer Cc chun giao tip ni tip ng b/ khung ng b USART B chuyn i ADC Analog-to-digital converters, 10/12 bit B so snh in p (Voltage Comparator) Cc module Capture/ Compare/ PWM LCD MSSP Peripheral dng cho cc giao tip I2C, SPI. B nh ni EPROM c th ghi/ xo ln ti 1 triu ln Module iu khin ng c, c encoder H tr giao tip USB
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H tr giao tip CAN H tr giao tip LIN H tr giao tip IrDA Mt s dng c tch hp b RF (PIC16f639, v RFPIC) KEELOQ m ho v gii m DSP nhng tnh nng x l tn hiu s (dsPIC) c im thc thi tc cao ca RISC CPU ca h vi diu khin PIC16F87XA : Ch gm 35 lnh n. Tt c cc lnh l 1chu k ngoi tr chng trnh con l 2 chu k. Tc hot ng : + DC- 20MHz ng vo xung clock. + DC- 200ns chu k lnh. rng ca b nh chng trnh Flash l 8K x 14word, ca b nh d liu (RAM) l 368 x 8bytes, ca b nh d liu l EPROM l 256 x 8bytes.
1.1.2. Nhng c tnh ngoi vi - Timer0 : 8- bit nh thi/ m vi 8- bit prescaler - Timer1 : 16- bit nh thi/ m vi prescaler, c th c tng ln trong sut ch Sleep qua thch anh/ xung clock bn ngoi. - Timer2 : 8- bit nh thi/m vi 8- bit, prescaler v postscaler - Hai module Capture, Compare, PWM * Capture c rng 16 bit, phn gii 12.5ns * Compare c rng 16 bit, phn gii 200ns * phn gii ln nht ca PWM l 10bit. - C 13 ng I/O c th iu khin trc tip - Dng vo v dng ra ln : * 25mA dng vo cho mi chn * 20mA dng ra cho mi chn 1.1.3. c im v tng t - 10 bit, vi 8 knh ca b chuyn i tng t sang s (A/D). - Brown out Reset (BOR). - Module so snh v tng t. * Hai b so snh tng t. * Module in p chun VREF c th lp trnh trn PIC. - C th lp trnh ng ra vo n t nhng ng vo ca PIC v trn in p bn trong. - Nhng ng ra ca b so snh c th s dng cho bn ngoi. 1.1.4. Cc c im c bit : - C th ghi/ xo 100.000 ln vi kiu b nh chng trnh Enhanced Flash.
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- 1.000.000 ghi/ xo vi kiu b nh EPROM. - EPROM c th lu tr d liu hn 40 nm. - C th t lp trnh li di s iu khin ca phn mm. - Mch lp trnh ni tip qua 2 chn. - Ngun n 5V cp cho mch lp trnh ni tip. - Watchdog Timer (WDT) vi b dao ng RC tch hp sn trn Chip cho hot ng ng tin cy. - C th lp trnh m bo v. - Tit kim nng lng vi ch Sleep. - C th la chn b dao ng. - Mch d sai (ICD : In- Circuit Debug) qua 2 chn 1.1.5. Cng ngh CMOS - Nng lng thp, tc cao Flash/ cng ngh EPROM - Vic thit k hon ton tnh -Khong in p hot ng t 2V n 5.5V -Tiu tn nng lng thp. 1.2. GII THIU V PIC16F8XX v PIC16F877A PIC16F8X l nhm PIC trong h PIC16XX ca h Vi iu khin 8-bit, tiu hao nng lng thp, p ng nhanh, ch to theo cng ngh CMOS, chng tnh in tuyt i. Nhm bao gm cc thit b sau: PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 - Tt c cc PIC16/17 u c cu trc RISC. PIC16CXX cc c tnh ni bc, 8 mc ngn xp Stack, nhiu ngun ngt tch hp bn trong ln ngoi. C cu trc Havard vi cc bus d liu v bus thc thi chng trnh ring bit nhau cho php di 1 lnh l 14-bit v bus d liu 8-bit cch bit nhau. Tt c cc lnh u mt 1 chu k lnh ngoi tr cc lnh r nhnh chng trnh mt 2 chu k lnh. Ch c 35 lnh v 1 lng ln cc thanh ghi cho php p ng cao trong ng dng. - H PIC16F8X c nhiu tnh nng c bit lm gim thiu cc thit b ngoi vi, v vy kinh t cao, c h thng ni bt ng tin cy v s tiu th nng lng thp. y c 4 s la chn b dao dng v ch c 1 chn kt ni b dao ng RC nn c gii php tit kim cao. Ch SLEEP tit kim ngun v c th c nh thc bi cc ngun reset. V cn nhiu phn khc c gii thiu bn trn s c ni r cc phn k tip. - PIC16F877A c 40/44 chn vi s phn chia cu trc nh sau : + C 5 port xut/nhp
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+ C 8 knh chuyn i A/D 10-bit + C 2 b PWM + C 3 b nh thi: Timer0, timer1 v timer2 + C giao tip truyn ni tip: chun RS 232, I2C + C giao tip LCD
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CHNG 2
T CHC B NH - CC THANH GHI CHC NNG

2.1 S CHN VI IU KHIN PIC16F877A
Hnh 2.1: S chn v hnh dng ca Pc 16F877A
Gio trnh Vi iu Khin Chc nng cc chn :
Chn 1 2 3 4 5 6 7
Tn /VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/TOCKI/C1OUT RA5/AN4/ /C2OUT
Chc nng : Hot ng Reset mc thp - VPP : ng vo p lp trnh - RA0 : xut/nhp s - AN0 : ng vo tng t - RA1 : xut/nhp s - AN1 : ng vo tng t - RA2 : xut/nhp s - AN2 : ng vo tng t - VREF -: ng vo in p chun (thp) ca b A/D - RA3 : xut/nhp s - AN3 : ng vo tng t - VREF+ : ng vo in p chun (cao) ca b A/D - RA4 : xut/nhp s - TOCKI : ng vo xung clock bn ngoi cho timer0 - C1 OUT : Ng ra b so snh 1 - RA5 : xut/nhp s - AN4 : ng vo tng t 4 - SS : ng vo chn la SPI ph - C2 OUT : ng ra b so snh 2 - RE0 : xut nhp s - RD : iu khin vic c port nhnh song song - AN5 : ng vo tng t - RE1 : xut/nhp s - WR : iu khin vic ghi port nhnh song song - AN6 : ng vo tng t - RE2 : xut/nhp s - CS : Chip la chn s iu khin port nhnh song song - AN7 : ng vo tng t Chn ngun ca PIC. Chn ni t Ng vo dao ng thch anh hoc xung clock bn ngoi. - OSC1 : ng vo dao ng thch anh hoc xung clock bn ngoi. Ng vo Schmit trigger khi c cu to ch RC ; mt cch khc ca CMOS. - CLKI : ng vo ngun xung bn ngoi. Lun c kt hp vi chc nng OSC1. Ng vo dao ng thch anh hoc xung clock - OSC2 : Ng ra dao ng thch anh. Kt ni n thch anh hoc b cng hng. - CLKO : ch RC, ng ra ca OSC2, bng tn s
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8 9 10
RE0/ RE1/ RE2/
/AN5 /AN6 /AN7
11 12 13
VDD VSS OSC1/CLKI
14
OSC2/CLKO
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15 16
RC0/T1 OCO/T1CKI RC1/T1OSI/CCP2
17 18
RC2/CCP1 RC3/SCK/SCL
19 20 21 22 23 24 25 26 27 28 29 30 31 32
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD4/PSP RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD
ca OSC1 v ch ra tc ca chu k lnh. - RC0 : xut/nhp s - T1OCO : ng vo b dao ng Timer 1 - T1CKI : ng vo xung clock bn ngoi Timer 1 - RC1 : xut/nhp s - T1OSI : ng vo b dao ng Timer 1 - CCP2 : ng vo Capture 2, ng ra compare 2, ng ra PWM2 - RC2 : xut/nhp s - CCP1 : ng vo Capture 1, ng ra compare 1, ng ra PWM1 - RC3 : xut/nhp s - SCK : ng vo xung clock ni tip ng b/ng ra ca ch SPI - SCL : ng vo xung clock ni tip ng b/ ng ra ca ch I2C - RD0 : xut/nhp s - PSP0 : d liu port nhnh song song - RD1 : xut/nhp s - PSP1 : d liu port nhnh song song - RD2 : xut/nhp s - PSP2 : d liu port nhnh song song - RD3: xut/nhp s - PSP3 : d liu port nhnh song song - RC4 : xut/nhp s - SDI : d liu vo SPI - SDA : xut/nhp d liu vo I2C - RC5 : xut/nhp s - SDO : d liu ra SPI - RC6 : xut/nhp s - TX : truyn bt ng b USART - CK : xung ng b USART - RC7 : xut/nhp s - RX : nhn bt ng USART - DT : d liu ng b USART - RD4: xut/nhp s - PSP4 : d liu port nhnh song song - RD5: xut/nhp s - PSP5 : d liu port nhnh song song - RD6: xut/nhp s - PSP6 : d liu port nhnh song song - RD7: xut/nhp s - PSP7 : d liu port nhnh song song Chn ni t Chn ngun ca PIC.
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33 34 35 36 37 38 39 40
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD
- RB0 : xut/nhp s - INT : ngt ngoi xut/nhp s xut/nhp s - RB3 : xut/nhp s - Chn cho php lp trnh in p thp ICPS - xut/nhp s - Ngt PortB - xut/nhp s - Ngt PortB - RB6 : xut/nhp s - PGC : mch vi sai v xung clock lp trnh ICSP - Ngt PortB - RB7 : xut/nhp s - PGD : mch vi sai v d liu lp trnh ICSP - Ngt PortB
2.2 MT VI THNG S V VI IU KHIN PIC16F877A
y l vi iu khin thuc h PIC16Fxxx vi tp lnh gm 35 lnh c di 14 bit. Mi lnh u c thc thi trong mt chu k xung clock. Tc hot ng ti a cho php l 20 MHz vi mt chu k lnh l 200ns. B nh chng trnh 8Kx14 bit, b nh d liu 368x8 byte RAM v b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O l 5 vi 33pin I/O. Cc c tnh ngoi vi bao gmcc khi chc nng sau: Timer0: b m 8 bit vi b chia tn s 8 bit. Timer1: b m 16 bit vi b chia tn s, c th thc hin chc nng m da vo xung clock ngoi vi ngay khi vi iu khin hot ng ch sleep. Timer2: b m 8 bit vi b chia tn s, b postcaler. Hai b Capture/so snh/iu ch rng xung. Cc chun giao tip ni tip SSP (Synchronous Serial Port), SPI v I2C. Chun giao tip ni tip USART vi 9 bit a ch. Cng giao tip song song PSP (Parallel Slave Port) vi cc chn iu khin RD, WR, CS bn ngoi. Cc c tnh Analog: 8 knh chuyn i ADC 10 bit. Hai b so snh. Bn cnh l mt vi c tnh khc ca vi iu khin nh: B nh flash vi kh nng ghi xa c 100.000 ln. B nh EEPROM vi kh nng ghi xa c 1.000.000 ln. D liu b nh EEPROM , c 256 byte (c a ch 00hFFh), c th lu tr trn 40 nm.
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Gio trnh Vi iu Khin
Kh nng t np chng trnh vi s iu khin ca phn mm. Np c chng trnh ngay trn mch in ICSP (In Circuit Serial Programming) thng qua 2 chn. Watchdog Timer vi b dao ng trong. Chc nng bo mt m chng trnh. Ch Sleep. C th hot ng vi nhiu dng Oscillator khc nhau.
2.3 S KHI VI IU KHIN PIC16F877A
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Hnh 2.2: Cu trc bn trong ca Pic 16F877A
Nh ni trn , vi iu khin PIC c kin trc Harvard, trong CPU truy cp chng trnh v d liu c trn hai bus ring bit, nn lm tng ng k bng thng so vi kin trc Von Neumann trong CPU truy cp chng trnh v d liu trn cng mt bus. Vic tch ring b nh chng trnh v b nh d liu cho php s bit ca t lnh c th khc vi s bit ca d liu. PIC 16F877A, t lnh di 14 bit , t d liu 8 bit. PIC 16F877A cha mt b ALU 8 bit v thanh ghi lm vic WR (working register). ALU l n v tnh ton s hc v logic, n thc hin cc php tnh s v i s Boole trn thanh ghi lm vic WR v cc thanh ghi d liu. ALU c th thc hin cc php cng, tr, dch bit v cc php ton logic
2.4 T CHC B NH
a.B NH CHNG TRNH
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Gio trnh Vi iu Khin
B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b nh 8K word (1 word = 14 bit) v c phn thnh nhiu trang (t page0 n page 3) .Nh vy b nh chng trnh c kh nngcha c 8*1024 = 8192 lnh (v mt lnh sau khi m ha s c dung lng 1 word (14bit). m ha c a ch ca 8K word b nh chng trnh, b m chng trnh c dung lng 13 bit (PC<12:0>). Khi vi iu khin c reset, b m chng trnh s ch n a ch 0000h (Resetvector). Khi c ngt xy ra, b m chngtrnh s ch n a ch 0004h (Interruptvector). B nh chng trnh khng bao gm b nh stack v khng c a ch ha bi b m chng trnh. B nh stack s c cp c th trong phn sau.
Hnh 2.3: B nh chng trnh ca Pic

b. B NH D LIU
B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i vi PIC16F877A b nh d liu c chia ra lm 4 bank. Mi bank c dung lng 128 byte, bao gm cc thanh ghi c chc nng c bit SFG (Special Function Register) nm cc vng a ch thp v cc thanh ghi mc ch chung GPR (General Purpose Register) nm vng a ch cn li trong bank. Cc thanh ghi SFR thng xuyn c s dng (v d nh thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong
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Gio trnh Vi iu Khin
qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu PIC16F877A nh sau:
Hnh 2.4: B nh b nh ca Pic
2.5 CC THANH GHI C BIT - THANH GHI FSR V INDF

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Gio trnh Vi iu Khin
Hnh 2.5: S thanh ghi FSR Thanh ghi FSR cha a ch con tr ch n, thanh ghi INDF cha ni dung c a ch nm trong thanh ghi FSR. V d: Thanh ghi 22H c gi tr l 10. Nu FSR =22H th INDF =10. Tm li, Thanh ghi INDF khng phi l mt thanh ghi vt l. N cha gi tr ca thanh ghi c a ch nm thanh ghi FSR. -THANH GHI STATUS
Thanh ghi trng thi cha cc trng thi s hc ca b ALU, trng thi Reset v cc bit chn Bank ca b nh d liu. Bit 7 IRP: Bit la chn bank thanh ghi (S dng cho nh a ch gin tip). 1 = Bank 2, 3 (100h 1FFh ) 0 = Bank 0, 1 (00h FFh) Bit 6 5: RP1 RP0: Bit la chn bank thanh ghi (Dng trong nh i ch trc tip). 11 = Bank 3 ( 180h 1FFh) 10 = Bank 2 (100h 17Fh) 01 = Bank 1 (80h FFh) 00 = Bank 0 (00h 7Fh) Each bank is 128 bytes Bit 4 TO: Bit bo hiu hot ng ca WDT.
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Gio trnh Vi iu Khin
1: Lnh xa WDT hoc Sleep xy ra. 0: WDT hot ng. Bit 3 PD: Bit bo cng sut thp ( Power down bit). 1: Sau khi ngun tng hoc c lnh xa WDT. 0: Thc thi lnh Sleep. Bit 2 Z: bit Zero 1: Khi kt qu ca mt php ton bng 0. 0: Khi kt qu ca mt php ton khc 0. Bit 1 DC: Digit Carry 1: C mt s nh sinh ra bi php cng hoc php tr 4 bit thp. 0: Khng c s nh sinh ra. Bit 0 C: c nh (Carry Flag)/ borrow 1: C mt s nh sinh ra bi php cng hoc php tr 4 bit cao. 0: Khng c s nh sinh ra. V d: Nu A B < 0 th C = 0 ngc li C = 1 - THANH GHI IU KHIN NGT INTCON (Interrupt Control Register)
Bit 7 GIE: Bit cho php ngt ton cc 1: Cho php ngt ton cc 0: Khng cho php ngt Bit 6 PEIE: Bit cho php ngt khi ghi vo EEPROM hon tt. 1: Cho php ngt ghi vo EEPROM hot ng 0: Khng cho php ngt ghi vo EEPROM hot ng Bit 5 TMR0IE: Bit cho php ngt khi timer 0 trn 1: Cho php ngt khi timer 0 trn 0: Khng cho php ngt khi timer 0 trn Bit 4 INTE: Bit cho php ngt ngoi vi trn chn RB0/INT 1: Cho php ngt ngoi vi 0: Khng cho php ngt ngoi vi Bit 3 RBIE: Cho php ngt khi trng thi PORTB thay i 1: Cho php 0: Khng cho php Bit 2 TMR0IF: C bo ngt Timer 0 1: Timer 0 trn
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Gio trnh Vi iu Khin
0: Timer 0 cha trn Bit 1 INTF:C bo ngt ngoi RB0/INT 1: C ngt 0: Khng xy ra ngt. Bit 0 RBIF:C bo ngt khi c thay i trng thi PORTB 1: C thay i 0: Khng c thay i xy ra trn PORTB * Ngoi ra cn mt s thanh ghi chc nng khc nh: Thanh ghi PIE1 (a ch 8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng ngoi vi. Thanh ghi PIR1 (a ch 0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1. Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM. Thanh ghi PIR2 ( 0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2. Thanh ghi PCON ( 8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin. bit them chi tit xem phn Ph luc 2.6 STACK Stack cho php 8 lnh gi chng trnh con v ngt hot ng. Stack cha a ch m chng trnh chnh s quay v thc hin t sau chng trnh con hay ngt. i vi PIC16F877A Stack c su 8 lp. Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng c vi iu khin ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh theo ng qui trnh nh trc. B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a ch v hot ng theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tri6 ct vo Stack ln th 2. Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit c khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin bi CPU.
CHNG 3
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Gio trnh Vi iu Khin
TP LNH - CU TRC CHNG TRNH

3.1. TP LNH 3.1.1. NHM LNH DI CHUYN 1. Lnh MOVLW C php: MOVLW k (0 k 255) Tc dng: em gi tr k vo thanh ghi W V d: gin cho thanh ghi W mt gi tr c th l 20H ta lm nh sau: MOVLW 20H MOVLW B0010 0000 MOVLW D32 2. Lnh MOVWF C php: MOVWF f (0 f 255) Tc dng: em gi tr ca thanh ghi W vo thanh ghi f gin cho thanh ghi mt gi tr c th, u tin a gi tr cn gin cho thanh ghi W, sau ta thc hin lnh MOVWF di chuyn gi tr trong thanh ghi W sang thanh ghi cn gin. V d: MOVLW D15; W=15 MOVWF PORTB; PORTB =15 Tuy nhin, cn c cch khc thng qua thanh ghi con tr FSR, khi thanh ghi con tr FSR tr n byte c a ch no th ni dung ca thanh ghi di chuyn vo thanh ghi INDF. hiu mt cch n gin ta hiu thanh ghi FSR cha a ch cn thanh ghi INDF cha ni dung. V d: MOVLW 30H MOVWF FSR MOVLW D20 MOVWF INDF lnh u tin W=30H, sau gin gi tr 30H vo thanh ghi FSR tc l con tr ch n byte c a ch 30H. Khi gi tr ca thanh ghi c a ch 30H c cha trong thanh ghi INDF. Nh vy sau khi gin gi tr 20 vo thanh ghi INDF tc l gin gi tr vo thanh ghi c a ch 30H. Vy sau khi thc hin on chng trnh trn (30H) = 20, tc l byte c a ch 30H c gi tr l 20. c th hn chng ta xt v d sau: MOVLW D5
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Gio trnh Vi iu Khin
MOVWF PORTB Thng qua 2 lnh trn PORTB = 5, nhng ta c th vit li: MOVLW 06H MOVWF FSR MOVLW D5 MOVWF INDF Vy sau khi thc hin on chng trnh trn (06H) = 5, tc l byte c a ch 06H (PORTB) c gi tr l 5. 3. Lnh MOVF C php: MOVF f,W f (0 f 255) Tc dng: em gi tr ca thanh ghi f vo thanh ghi W di chuyn gi tr thanh ghi COUNT1 sang thanh ghi COUNT2 th ta bt buc qua thanh ghi trung gian W thng qua lnh MOVF. Vid: MOVF COUNT1,W MOVWF CONT2 u tin em gi tr c c thanh ghi COUNT1 vo W, sau thng qua lnh MOVWF em gi tr c c thanh ghi W vo COUNT2. 3.1.2. NHM LNH S HC 4. Lnh ADDLW C php: ADDLW k Tc dng: Cng gi tr k vo thanh ghi W,kt qu c cha trong thanh ghi W. Bit trng thi: C, DC, Z V d: MOVLW D200; W=200 ADDLW D55 MOVWF PORTB; PORTB = 255 5.Lnh ADDWF C php: ADDWF f,d (d [0,1]). Tc dng: Cng gi tr hai thanh ghi W v thanh ghi f. Kt qu c cha trong thanh ghi W nu d = 0 hoc thanh ghi f nu d =1. Bit trng thi: C, DC, Z 6. Lnh SUBLW C php: SUBLW k Tc dng: Ly gi tr k tr gi tr trong thanh ghi W. Kt qu c cha trong thanh ghi W.
18
Gio trnh Vi iu Khin
Bit trng thi: C, DC, Z V d: MOVLW D100; W=100 SUBLW D155 MOVWF PORTB; PORTB =55 7. Lnh SUBWF C php: SUBWF f,d ( d [0,1]) Tc dng: Ly gi tr trong thanh ghi f em tr cho thanh ghi W. Kt qu c lu trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: C, DC, Z 8. Lnh INCF C php: INCF f,d (d [0,1]) Tc dng: Tng gi tr thanh ghi f ln 1 n v. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: Z V d: MOVLW D10 MOVWF COUNT; COUNT =10 INCF COUNT,1; COUNT =11 9. Lnh DECF C php: DECF f,d (d [0,1]). Tc dng: Gi tr thanh ghi f c gim i 1 n v. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: Z V d: MOVLW D10 MOVWF COUNT; COUNT =10 DECF COUNT,1; COUNT =9 3.1.3. NHM LNH LOGIC 10. Lnh BCF C php: BCF f,b (0b7) Tc dng: Xa bit b trong thanh ghi f v gi tr 0. Bit trng thi: khng c. V d:
19
Gio trnh Vi iu Khin
BCF PORTB,2; RB2 =0 11. Lnh BSF C php: BSF f,b (0b7) Tc dng: Set bit b trong thanh ghi f. Bit trng thi: khng c V d: BSF PORTB,2;RB2 =1 12. Lnh CLRW C php CLRW Tc dng: Xa thanh ghi W v bit Z c set. Bit trng thi: Z 13. Lnh CLRF C php CLRF f Tc dng: Xa thanh ghi f v bit Z c set. Bit trng thi: Z 14. Lnh CLRWDT C php: CLRWDT Tc dng: Reset Watchdog Timer, ng thi prescaler cng c reset, cc bit v c set ln 1. 15. Lnh ANDLW C php: ANDLW k Tc dng: Thc hin php ton AND gia thanh ghi v gi tr k, kt qu c cha trong thanh ghi W. Bit trng thi: Z Ch : And cc bit tng ng V d: MOVLW B1111 0000 ANDLW B0011 1111; W = B0011 0000 16. Lnh ANDWF C php: ANDWF f,d (d [0,1]). Tc dng: Thc hin php ton AND gia cc gi tr cha trong hai thanh ghi W v f. Kt qu c a vo thanh ghi W nu d=0 hoc thanh ghi f nu d = 1. Bit trng thi: Z 17. Lnh IORLW C php: IORLW k
20
Gio trnh Vi iu Khin
Tc dng: Thc hin php ton OR gia thanh ghi W v gi tr k. Kt qu c cha trong thanh ghi W. Bit trng thi: Z 18. Lnh IORWF C php: IORWF f,d (d[0,1]) Tc dng: Thc hin php ton OR gia hai thanh ghi W v f. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d=1. Bit trng thi: Z 19. Lnh XORLW C php: XORLW k Tc dng: Thc hin php ton XOR gia gi tr k v gi tr trong thanh ghi W. Kt qu c lu trong thanh ghi W. Bit trng thi: Z 20. Lnh XORWF C php: XORWF f,d Tc dng: Thc hin php ton XOR gia hai gi tr cha trong thanh ghi W v thanh ghi f. Kt qu c lu vo trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: Z 21. Lnh SWAPF C php: SWAPF f,d (d[0,1]) Tc dng: o 4 bit thp vi 4 bit cao trong thanh ghi f. Kt qu c cha trong thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: khng c 22. Lnh RLF C php: RLF f,d (d[0,1]) Tc dng: Dch tri cc bit trong thanh ghi f qua c carry. Kt qu c lu trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: C 23. Lnh RRF C php: RRF f,d (d[0,1]) Tc dng: Dch phi cc bit trong thanh ghi f qua c carry. Kt qu c lu trong thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: C
21
Gio trnh Vi iu Khin
24. Lnh COMF C php: COMF f,d (d[0,1]). Tc dng: o cc bit trong thanh ghi f. Kt qu c a vo thanh ghi W nu d =0 hoc thanh ghi f nu d=1. Bit trng thi: Z 3.1.4.NHM LNH R NHNH 25. Lnh BTFSS C php: BTFSS f,b (0b7) Tc dng: Kim tra bit b trong thanh ghi f. Nu bit b bng 0, lnh tip theo c thc thi. Nu bit b bng 1, lnh tip theo c b qua v thay vo l lnh NOP. Bit trng thi: khng c V d: BTFSS PORTB,1 LNH 1 LNH 2 1 y l v tr bt c kim tra ca portB. Nu bt ny mc cao th s b qua lnh 1 thc thi lnh 2. Ngc lai, mc thp s thc thi lnh 1 26. Lnh BTFSC C php: BTFSC f,b (0b7) Tc dng: kim tra bit b trong thanh ghi f. Nu bit b bng 1, lnh tip theo c thc thi. Nu bit b bng 0, lnh tip theo c b qua v thay vo l lnh NOP. Bit trng thi: khng c 27. Lnh DECFSZ C php: DECFSZ f,d (d [0,1]) Tc dng: ga tr thanh ghi f c gim 1 n v. Nu kt qu sau khi gim khc 0, lnh tip theo c thc thi, nu kt qu bng 0, lnh tip theo khng c thc thi v thay vo l lnh NOP. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: khng c V d: DECFSZ DEM,1 LNH 1 LNH 2
22
Gio trnh Vi iu Khin
Sauk khi gim gi tr trong thanh ghi DEM xung 1 n v, nu cha bng 0 th thc thi LNH 1. Ngc li, thc thi LNH 2 28. Lnh INCFSZ C php: INCFSZ f,d (d [0,1]) Tc dng: tng gi tr thanh ghi f ln 1 n v. Nu kt qu khc 0, lnh tip theo c thc thi, nu kt qu bng 0, lnh tip theo c thay bng lnh NOP. Kt qu s c a vo thanh ghi f nu d=1 hoc thanh ghi W nu d = 0. Bit trng thi: khng c. 29. Lnh GOTO C php: GOTO k (0k2047) Tc dng: nhy ti mt label c nh ngha bi tham s k v 2 bit PCLATH <4:3>. Bit trng thi: khng c. 30. Lnh CALL C php: CALL k (0k2047) Tc dng: gi mt chng trnh con. Trc ht a ch quay tr v t chng trnh con (PC+1) c ct vo trong Stack, gi tr a ch mi c a vo b m gm 11 bit ca bin k v 2 bit PCLATH<4:3>. Bit trng thi: khng c 31. Lnh RETURN C php: RETURN Tc dng: quay tr v chng trnh chnh t mt chng trnh con Bit trng thi:khng c Ngoai cac lenh tren con co mot so lenh dung trong chng trnh nh: 32 Lnh #DIFINE C php: #DEFINE <text1> <text2> Tc dng: thay th mt chui k t ny bng mt chui k t khc, c ngha l mi khi chui k t text1 xut hin trong chng trnh, trnh bin dch s t ng thay th chui k t bng chui k t <text2>. 33. Lnh INCLUDE C php: #INCLUDE <filename> hoc #INCLUDE "filename" Tc dng: nh km mt file khc vo chng trnh, tng t nh vic ta copy file vo v tr xut hin lnh INCLUDE. Nu dng c php <filename> th file nh km l file h thng (stem file), nu dng c php "filename" th file nh km l file ca ngi s dng. Thng thng chng trnh c nh km theo mt "header file" cha cc thng tin nh ngha cc bin (thanh ghi W, thanh ghi F,..) v cc a ch cu cc thanh ghi chc nng c
23
Gio trnh Vi iu Khin
bit trong b nh d liu. Nu khng c header file, chng trnh s kh c v kh hiu hn. 34 .Lnh CONSTANT C php: CONSTANT <name>=<value> Tc dng: Khai bo mt hng s, c ngha l khi pht hin chui k t "name" trong chng trnh, trnh bin dch s t ng thay bng chui k t bng gi tr "value" c nh ngha trc . 35. Lnh VARIABLE C php: VARIABLE <name>=<value> Tc dng: Tng t nh lnh CONSTANT, ch c im khc bit duy nht l gi tr "value" khi dng lnh VARIABLE c th thay i c trong qu trnh thc thi chng trnh cn lnh CONSTANT th khng. 36. Lnh SET C php: <name variable> SET <value> Tc dng: Gn gi tr cho mt tn bin. Tn ca bin c th thay i c trong qu trnh thc thi chng trnh. 37 Lnh EQU C php: <name constant> EQU <value> Tc dng: Gn gi tr cho tn ca tn ca hng s. Tn ca hng s khng thay i trong qu trnh thc thi chng trnh. 38. Lnh ORG C php: ORG <value> Tc dng: nh ngha mt a ch cha chng trnh trong b nh chng trnh ca vi iu khin. 39. Lnh END C php: END Tc dng: nh du kt thc chng trnh. 40. Lnh __CONFIG Tc dng: Thit lp cc bit iu khin cc khi chc nng ca vi iu khin c cha trong b nh chng trnh (Configuration bit). 41. Lnh PROCESSOR C php: PROCESSOR <processor type> Tc dng: nh ngha vi iu khin no s dng chng trnh.
3.2. TO TR BNG VNG LP

24
Gio trnh Vi iu Khin
Thc cht ca chng trnh DELAY l cho vi iu khin lm mt cng vic v ngha no trong mt khong thi gian nh trc. Khong thi gian ny c tnh ton da trn qu trnh thc thi lnh, hay c th hn l da vo thi gian ca mt chu k lnh. C th vit chng trnh DELAY da trn on chng trnh sau: DELAY MOVLW D5 MOVWL DEM LOOP DECFSZ DEM GOTO LOOP RETURN By gi ta tnh ton xem on chng trnh trn to tr bao lu? (Hai lnh u xem nh b qua, tnh t ngay nhn LOOP cho n lnh RETURN) 5 4 ; 3 chu k my 4 3; 3 chu k my 3 2; 3 chu k my 2 1; 3 chu k my 1 0; 4 chu k my i vi cc lnh trong Pic nhng lnh thng thng khi thc thi tn 1 chu k my, cc lnh nhy tn 2 chu k my. Ring cc lnh: BTFSS, BTFSC, DECFSZ Khi cha nhy cng tn 1 chu k my, khi tha iu kin th nhy th tn 2 chu k my. Do , vng lp u tin lnh DECFSZ tn 1 chu k my, lnh GOTO tn 2 chu k my. vng lp cui, sau khi thc thi xong lnh DECFSZ gi tr trong thanh ghi DEM gim t 1 0 th nhy qua khi lnh GOTO tn 2 chu k my nhng gp lnh RETURN l lnh nhy tn 2 chu k my. Do , vng lp cui tn 4 chu k my. Td = (3DEM+1)Ti 3DEM. Vi: Ti = 4/ fOSC DEM 255: Gi tr cy vo m Td: Thi gian to tr. V d: Vit chng trnh to tr 500s, thch anh 4Mhz Tac: Td = 500s, Ti = 4/fOSC =1s => DEM = 500/3 = 167 DELAY MOVLW D167 MOVWL DEM LOOP DECFSZ DEM
25
Gio trnh Vi iu Khin
GOTO LOOP RETURN Nhn xt: Nu dng thch anh 4Mhz th Td t gi tr ti a l 765 s. Vy tng thi gian Td chng ta dng 2 vng lp lng vo nhau: DELAY MOVLW D255 MOVWF DEM1 LOOP DECFSZ DEM1 GOTO LOOP1 GOTO THOAT LOOP1 MOVLW D255 MOVWF DEM2 LOOP2 DECFSZ DEM2 GOTO LOOP2 GOTO LOOP THOAT NOP RETURN Vi on chng trnh trn ta tnh c: Td 3*DEM2*DEM1. = 3.255.255= 172125 s 0.196S 3.3. CU TRC CHNG TRNH ; Khng c s dng ngt, nu c s dng ngt xem chng 6 PROCESSOR 16F877A ; Khai bo dng VI IU KHIN g? # INCLUDE <P 16F877A.INC> ; nh km file c sn trong th vin. ORG 0000H ; a ch Vect Reset - CHN BANK ; Da vo thanh ghi Status chn bank ph hp - CHN I/O ;Da vo mc ch thit k, chn ng vo/ra ; ph hp. MAIN ;Bt u vit chng trnh ; Thc thi chng trnh
26
Gio trnh Vi iu Khin
; Vng lp v hn END ; Kt thc chng trnh V d: Vit chng trnh xut ra chn RB7 mc cao. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 ; Chn bank0 BCF STATUS,5 ; Chn bank0 CLRF PORTB ; Xa PORTB BSF STATUS,5 ; Chn bank1 BCF TRISB,7 ; Khai bo RB7 l output BCF STATUS,5 ; Tr li bank0 BSF PORTB,7 ; Set RB7 mc cao GOTO $ ; To vng lp v hn END bit khai bo I/O nh th no? chng ta c th nm cch thc khai bo I/O c th nh sau: - Thanh ghi TRISA chn tnh I/O cho PORTA - Thanh ghi TRISB chn tnh I/O cho PORTB - Thanh ghi TRISC chn tnh I/O cho PORTC - Thanh ghi TRISD chn tnh I/O cho PORTD - Thanh ghi TRISE chn tnh I/O cho PORTE Cch chn cng kh n gin: Mun xc lp chc nng ca mt chn trong PORTA l input, ta "set" bit iu khin tng ng vi chn trong thanh ghi TRISA v ngc li, mun xc lp chc nngca mt chn trong PORTA l output, ta "clear" bit iu khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu khin tng ng TRIS (i vi PORTA l TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l TRISD vi vi PORTE l TRISE). V d: Chng ta mun RA1 l output, RA0 l input BCF TRISA,1 BSF TRISA,0 Tng t, RB5 l input, RB7 l output BSF TRISB,5 BCF TRISB,7
27
GOTO $
Gio trnh Vi iu Khin
BI TP THAM KHO Bi tp 1: Vit chng trnh to xung vung ti chn RB7, c tn s f = 50hz (thch anh 4Mhz) Ta c: T= 1/f = 20.000S =>Td = 10.000 S PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM2 EQU 20H DEM1 EQU 21H ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 BCF TRISB,7 BCF STATUS,5 MAIN BSF PORTB,7 CALL DELAY BCF PORTB,7 CALL DELAY GOTO MAIN DELAY MOVLW D'33' MOVWF DEM1 LOOP DECFSZ DEM1 GOTO LOOP1 GOTO THOAT LOOP1 MOVLW D'100' MOVWF DEM2 LOOP3 DECFSZ DEM2 GOTO LOOP3 GOTO LOOP THOAT NOP RETURN END Bi tp 2: Vit chng trnh iu khin n: trng thi ban u n tt, nhn N bung ra n sang. Nu n ang sang nhn N bung ra n tt v ngc li.
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Gio trnh Vi iu Khin

5 V
R R N
1 L E R B 0 P I C R B 7 1 6 F 8 7 7 A R D
Hnh 3.1 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 BSF TRISB,0 BCF TRISB,7 BCF STATUS,5 MAIN BTFSS PORTB,0 GOTO LOOP1 GOTO MAIN LOOP1 BTFSC PORTB,0 GOTO LOOP2 GOTO LOOP1 LOOP2 BTFSS PORTB,7 GOTO ON GOTO OFF OFF BCF PORTB,7 GOTO MAIN ON BSF PORTB,7 GOTO MAIN END Bi tp 3: Vit chng trnh iu khin n cu thang: Nu n ang tt nhn N1(hoc N2), ri bung ra n sng v ngc li.
29
Gio trnh Vi iu Khin
V c c
5 V
HI
R N 1
R R A 0 P I C R A 2 1 6 F 8 7 7 A R Q 1
2 2 0 V
R A 1
Hnh 3.2 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF BSF BSF BSF BCF BCF MAIN BTFSC GOTO GOTO LOOP1 BTFSS GOTO GOTO KT_1 BTFSS GOTO GOTO KT_2 BTFSS GOTO GOTO ON/OFF BTFSS GOTO GOTO
STATUS,6 STATUS,5 PORTA STATUS,5 TRISA,0 TRISA,1 TRISA,2 STATUS,5 PORTA,0 LOOP1 KT_1 PORTA,1 KT_2 MAIN PORTA,0 KT_1 ON/OFF PORTA,1 KT_2 ON/OFF PORTA,2 ON OFF
30
Gio trnh Vi iu Khin
ON BSF GOTO OFF BCF GOTO END PORTA,2 MAIN PORTA,2 MAIN
3.4. CC KHI GIAO TIP 3.4.1. GIAO TIP VI LED 7 OAN
Trong cc thit b, bo trng thi hot ng ca thit b cho ngi s dng vi thng s ch l cc dy s n thun, thng ngi ta s dng "led 7 on". Led 7 on c s dng khi cc dy s khng i hi qu phc tp, ch cn hin th s l , chng hn led 7 on c dng hin th nhit phng, trong cc ng h treo tng bng in t, hin th s lng sn phm c kim tra sau mt cng on no ... Led 7 on c cu to bao gm 7 led n c dng thanh xp theo hnh v c thm mt led n hnh trn nh th hin du chm trn gc di, bn phi ca led 7 on. Tm led n trn led 7 on c Anode(cc +) hoc Cathode(cc -) c ni chung vi nhau vo mt im, c a chn ra ngoi kt ni vi mch in. 8 cc cn li trn mi led n c a thnh 8 chn ring, cng c a ra ngoi kt ni vi mch in. Nu led 7 on c Anode(cc +) chung, u chung ny c ni vi +Vcc, cc chn cn li dng iu khin trng thi sng tt ca cc led n, led ch sng khi tn hiu t vo cc chn ny mc 0. Nu led 7 on c Cathode(cc -) chung, u chung ny c ni xung Ground (hay Mass), cc chn cn li dng iu khin trng thi sng tt ca cc led n, led ch sng khi tn hiu t vo cc chn ny mc 1.
c h u n g
c h u n g
Hnh 3.3 V led 7 on cha bn trong n cc led n, do khi kt ni cn m bo dng qua mi led n trong khong 10mA-20mA bo v led. Nu kt ni vi ngun 5V c th hn dng bng in tr 330 trc cc chn nhn tn hiu iu khin S v tr cc led c trnh by nh hnh bn: Cc in tr 330 l cc in tr bn ngoi c kt ni gii hn dng in qua led nu led 7 on c ni vi ngun 5V.
31
Gio trnh Vi iu Khin
Chn nhn tn hiu a iu khin led a sng tt, ng vo b iu khin led b. Tng t vi cc chn v cc led cn li
Hnh 3.4:K hiu Led 7 on
Hnh 3.5: Dng s hin th ln Led 7 on
Hnh 3.6: Hnh dng Led 7 on Bi tp 1: Vit chng trnh hin th s 3
32
Gio trnh Vi iu Khin
V c c
H I
V C C
P
1 2 3 4 5 6 7 8 9 M R R R R R R R R R V G O O R R R R R R C A A A A A A E E E D N S S C C C C D D L 0 1 2 3 4 5 0 1 2 D D C C 0 1 2 3 0 1 R / / / / / / / / /
I C
1 6 F 8 7 7 A
g f e d c b a
1 1 1 1 1 1 1 1 1 1 2
0 1 2 3 4 5 6 7 8 9 0
4 0 / V P P R B 7 / P G 9D 3 A N 0 R B 6 / P G 8C 3 A N 1 R B 53 7 A N 2 / V R e R f - B / C4 3 V 6 R e f A N 3 / V R R B e 3f +/ P G 5 M 3 T 0 C K I / C 1R O B U 2 3 T 4 A N 4 / S S / CR 2 B O 1 3 U 3 T R D / A N R 5 B 0 / I N3 2T W R / A N 6 V D D 3 1 C S A N 7 G N D 3 0 R D 7 / P S 2 P9 7 R D 6 / P S 2 P8 6 1 / C L K R I D 5 / P S 2 P7 5 2 / C L K R O D 4 / P S 2 P6 4 / T 1 O S R O C / T7 1/ RC XK 2 / I 5 D T / T 1 O S R I / CC 6 C / T X2 2/ C4 K P / C C P 1 R C 5 / S D 3O 2 / S C KR / C C / L S D I 2/ S2 D A S 4 / P S P 0 R D 3 / P S 2 P1 3 / P S P 1 R D 2 / P S P 2
Hnh 3.7 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF BCF CLRF CLRF BSF CLRF BCF BCF MAIN BSF MOVLW MOVWF GOTO PORTC,4 B011 0000 PORTB $
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 STATUS,5
END Bi tp 2: Tuy nhin, hin th 2 s v d nh 37 chng ta khng nht thit phi dng 2 port, m c th ghp song song 2 led 7 on. hin th s 37, ti mt thi im ta cho mt con Led sng. Thi gian chp tt lin tc (tn s khong 40 Hz) lm cho mt ta c cm gic nh 2 Led ang sng lin tc. Phng php ny gi l qut led
33
A B C D E F G H
V C C
Gio trnh Vi iu Khin
V c c
H I
V C C
V C C
V C C
P
1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 0 1 2 3 4 5 6 7 8 9 0 M R R R R R R R R R V G O O R R R R R R C A A A A A A E E E D N S S C C C C D D L 0 1 2 3 4 5 0 1 2 D D C C 0 1 2 3 0 1 R / / / / / / / / /
I C
1 6 F
8 7 7 A
g f e d c b a
4 0 / V P P R B 7 / P G 9D 3 A N 0 R B 6 / P G 8C 3 A N 1 R B 53 7 A N 2 / V R e R f -B / C 3 V6 R e f 4 A N 3 / V R R B e 3 f /+ P G 5 M 3 T 0 C K I / C 1 O B U2 3 T 4 R A N 4 / S S / C 2B O1 3 U 3 T R R D / A N R 5 B 0 / I N 2T 3 W R / A N 6 V D D 3 1 C S A N 7 G N D3 0 R D 7 / P S2 P 7 9 R D 6 / P S2 P 6 8 1 / C L K R I D 5 / P S2 P 5 7 2 / C L K R O D 4 / P S2 P 4 6 / T 1 O S R O C / T7 1/ RC X K2 / 5D T I / T 1 O S R I / C C 6 C / TP X 2 2 / C4 K / C C P 1 R C 5 / S 2 3O D / S C KR / CS 4 / LS D I 2/ S2 D A C / P S P 0 R D 3 / P S2 P 3 1 / P S P 1 R D 2 / P S P 2
A B C D E F G H
Hnh 3.8 PROCESSOR 16F877A #INCLUDE <P16F877A.INC>

DEM1 DEM2 EQU EQU 20H 21H
ORG 0000H BCF BCF CLRF CLRF BSF CLRF BCF BCF BCF MAIN BSF BCF MOVLW MOVWF PORTC,4 PORTC,5 B0110000 PORTB
34
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 TRISC,5 STATUS,5
A B C D E F G H
V C C
Gio trnh Vi iu Khin
CALL BCF BSF MOVLW MOVWF CALL GOTO DELAY_10ms MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END
DELAY_10ms PORTC,4 PORTC,5 B1111000 PORTB DELAY_10ms MAIN D'33' DEM1 DEM1 LOOP1 THOAT D'100' DEM2 DEM2 LOOP3 LOOP
3.4.2. GIAO TIP VI BN PHM HEX
Khi giao tip vi bn phm Hex nh hnh 3.9 ta chn RB0RB3 l output, RB4RB7 l input. Ban u ta cho RB3RB2RB1RB0=1110 sau chng ta kim tra ng vo t RB4RB7 xc nh ti v tr no mc thp tng ng vi nt nhn c tc ng. Nu RB4=0 tc l vi tr s 0 c nhn, tng t RB5=0 th s 1 c nhn. .... Tip theo ta cho RB3RB2RB1RB0=1101, khi kim tra nu RB4 =0 th nt s 4 th c nhn.....
35
Gio trnh Vi iu Khin
R1
470
R2
470
R3
470
R4
470
RB0 4 5 6 7 RB1 8 9 A B RB2 C D E F RB3
RB4
RB5
RB6
Hnh 3.9
RB7
DOC_BP MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW B1110 PORTB PORTB,4 D'0' PORTB,5 D'1' PORTB,6 D'2' PORTB,7 D'3'
36
Gio trnh Vi iu Khin MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW MOVLW MOVWF BTFSS RETLW BTFSS RETLW BTFSS RETLW BTFSS RETLW RETURN B1101 PORTB PORTB,4 D'4' PORTB,5 D'5' PORTB,6 D'6' PORTB,7 D'7' B1011 PORTB PORTB,4 D'8' PORTB,5 D'9' PORTB,6 0AH PORTB,7 0BH B0111 PORTB PORTB,4 0CH PORTB,5 0DH PORTB,6 0EH PORTB,7 0FH
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Gio trnh Vi iu Khin 3.4.3. GIAO TIP VI LED MA TRN
Hnh 3.10
H1 H2 H3 H4 H5 H6 H7 H8
C1
C2
C3
Hnh 3.11
C4
C5
C6
C7
C8
Led matrn hin th 1 k t chng ta dng phng php qut, cng nh qut led 7 on, y chng ta dng cch qut ct. Tc l ti mt thi im ch cho 1 ct ct sng bng cch tc ng cho hng v ct tch cc hp l.
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Gio trnh Vi iu Khin
V d: iu khin hng l portb (RB0H1, RB1H2 ........ RB7H8), iu khin ct l portd (RD0C1, RD1C2 ........ RD7C8). hin ch N ta vit nh sau: MAIN MOVLW B11111111 MOVWF PORTB MOVLW B11111110 MOVWF PORTD CALL DELAY MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW B11111111 PORTB B11111101 PORTD DELAY B00000011 PORTB B11111011 PORTD DELAY B00000110 PORTB B11110111 PORTD DELAY B00001100 PORTB B11101111 PORTD DELAY B00011000 PORTB B11011111 PORTD DELAY B11111111 PORTB B10111111 PORTD DELAY B11111111 PORTB B01111111
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Gio trnh Vi iu Khin
MOVWF CALL GOTO ; TAO TRE 2.5mS = 2500uS DELAY MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END
3.4.4 GIAO TIP VI LCD
PORTD DELAY MAIN D'8' DEM1 DEM1 LOOP1 THOAT D'104' DEM2 DEM2 LOOP3 LOOP
Hnh 3.12
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Gio trnh Vi iu Khin
Bn trong LCD c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor Register) v thanh ghi d liu DR (Data Register) Thanh ghi IR : iu khin LCD Nh vy iu khin LCD chng ta cn a m lnh iu khin thch hp vo thanh ghi IR thng qua bng m sau: Bng m lnh
M S Hex 01 02 04 06 05 07 08 0A 0C 0E 0F 10 14 18 1C 80 C0 38 Lnh n Thanh Ghi Ca LCD Xa mn hnh hin th Tr v u dng Gim con tr (dch con tr sang tri) Tng con tr (dch con tr sang phi) Dch hin th sang phi Dch hin th sang tri Tt con tr, tt hin th Bt con tr, tt hin th Tt con tr, bt hin th Nhp nhy con tr, bt hin th Tt con tr, nhp nhy con tr Dch v tr con tr sang tri Dch v tr con tr sang phi Dch ton b hin th sang tri Dch ton b hin th sang phi a con tr v u dng th nht a con tr v u dng th hai Ci LCD chy ch 2 dng v dng ma trn 5 x 7
V d: Mun xa mn hnh chng ta cn a gi tr 01H vo IR Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM DDRAM hoc CGRAM (ch ghi) hoc dng cha d liu t 2 vng RAM ny gi ra cho MCU ( ch c). DR cng l thanh Ram cha d liu cn hin th ln LCD. V d: hin th ln LCD ch A chng ta a gi tr 65 vo DR (m ascii ca A l 65) a gi tr thch hp vo IR hoc DR thng qua 3 chn iu khin: E, RS v RW Bng chc nng chn
S Chn 1 2 3 4 Tn Gi VSS VDD VEE RS Chc Nng Chn ni t cho LCD, khi thit k mch ta ni chn ny vi GND ca mch iu khin. Chn cp ngun cho LCD, khi thit k mch ta ni chn ny vi VCC=5V ca mch iu khin. Chn ny dng iu chnh tng phn ca LCD. Khi thit k ni chn ny vi chn iu chnh ca bin tr khong 5K n 10k. Chn chn thanh ghi (Register select). Ni chn RS vi logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi. + Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh 41
Gio trnh Vi iu Khin IR ca LCD ( ch ghi - write) hoc ni vi b m a ch ca LCD ( ch c - read) + Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn trong LCD. Chn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0 LCD hot ng ch ghi, hoc ni vi logic 1 LCD ch c. Chn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1 xung cho php ca chn E (xung ny c rng hn >= 4us). + ch ghi: D liu bus s c LCD chuyn vo (chp nhn) thanh ghi bn trong n khi pht hin mt xung (high-to-low transition) ca tn hiu chn E. + ch c: D liu s c LCD xut ra DB0DB7 khi pht hin cnh ln (low-to-high transition) chn E v c LCD gi bus n khi no chn E xung mc thp. Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch s dng 8 ng bus ny : + Ch 8 bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7. 7 --> 14 D0 --> D7 + Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l DB7. Chi tit s dng 2 giao thc ny c cp phn sau. 15 16 A K Chn dng (+) ca n nn LCD. Chn m (-) ca n nn LCD.
R/W
V d: Cho s nh hnh 3.13. Vit chng trnh cho LCD hin th s 0 gia hng th nht.
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Gio trnh Vi iu Khin

LCD2
LM016L
VSS VD D VEE
RS R W E 4 5 6
1 2 3
U1
13 14 2 3 4 5 6 7 8 9 10 1 OSC1/CLKIN OSC2/CLKOUT RB0/INT RB1 RB2 RB3/PG M RB4 RB5 RB6/PG C RB7/PG D 33 34 35 36 37 38 39 40 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30
RA0/AN 0 RA1/AN 1 RA2/AN2/VREF-/C EF VR RA3/AN3/VR EF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2O UT RC0/T1OSO/T1CKI RE0/AN5/R D RC1/T1OSI/CCP2 RE1/AN 6/WR RC2/CC P1 RE2/AN7/C S RC3/SCK/SCL RC4/SDI/SD A MCLR/Vpp/T HV RC5/SD O RC6/TX/C K RC7/RX/DT RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PIC16F877A
Hnh 3.13
PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TAM EQU 20H DEM1 EQU 21H DEM2 EQU 22H DEM3 EQU 23H ORG 0000H BSF BCF CLRF CLRF BCF CLRF CLRF MAIN MOVLW MOVWF CALL CALL 01h ; Dua 01h vo IR, xa mn hnh TAM KHOITAO DELAY; Tao tre
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STATUS,5 STATUS,6 TRISB TRISE STATUS,5 PORTB PORTE
7 8 9 10 11 12 13 14
D0 D1 D2 D3 D4 D5 D6 D7
Gio trnh Vi iu Khin
MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL MOVLW MOVWF CALL CALL GOTO XUATLCD MOVLW MOVWF MOVF MOVWF MOVLW MOVWF RETURN KHOITAO MOVLW MOVWF MOVF MOVWF MOVLW MOVWF RETURN DELAY MOVLW MOVWF LOOP DECFSZ GOTO GOTO LOOP1 MOVLW MOVWF
38h; Dua 38h vo IR, khoi tao LCD 2 hang TAM KHOITAO DELAY 0Eh ; ; Dua 0eh vo IR, nhap nhay con tro, bat hien thi TAM KHOITAO DELAY 87h TAM KHOITAO DELAY D'48' TAM XUATLCD DELAY $ B'101' ; E=1, RW=0, RS=1 PORTE TAM,0 PORTB B'001' ; E=0 tao canh xuong PORTE B'100'; ; E=1, RW=0, RS=0 PORTE TAM,0 PORTB B'000' PORTE D'20' DEM1 DEM1 LOOP1 THOAT D'100' DEM2
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Gio trnh Vi iu Khin
LOOP3 DECFSZ GOTO GOTO THOAT NOP RETURN END DEM2 LOOP3 LOOP
CHNG 4
CC KHI CHC NNG

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Gio trnh Vi iu Khin 4.1.B NH THI 4.1.1.TIMER 0
y l mt trong ba b m hoc b nh thi ca vi iu khin PIC16F877A. Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer0 cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer0 s xut hin khi Timer0 b trn. Bit TMR0IE (INTCON<5>) l bit iu khin ca Timer0.TMR0IE=1 cho php ngt Timer0 tc ng, TMR0IF= 0 khng cho php ngt Timer0 tc ng. S khi ca Timer0 nh sau:
Hnh 4.7: Cu trc bn trong ca b nh thi Timer0 Mun Timer0 hot ng ch Timer ta clear bit TOSC (OPTION_REG<5>), khi gi tr thanh ghi TMR0 s tng theo tng chu k xung ng h (tn s vo Timer0 bng tn s oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ngt Timer0 s xut hin.Thanh ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt Timer0 xut hin mt cch linh ng. Mun Timer0 hot ng ch counter ta set bit TOSC (OPTION_REG<5>). Khi
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Gio trnh Vi iu Khin
xung tc ng ln b m c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG<4>) cho php la chn cnh tc ng vo bt m. Cnh tc ng s l cnh ln nu TOSE=0 v cnh tc ng s l cnh xung nu TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON<2>) s c set. y chnh l c ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc hin li qu trnh m. Ngt Timer0 khng th "nh thc" vi iu khin t ch sleep. B chia tn s (prescaler) c chia s gia Timer0 v WDT (Watchdog Timer). iu c ngha l nu prescaler c s dng cho Timer0 th WDT s khng c c h tr ca prescaler v ngc li. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3>) xc nh i tng tc ng ca prescaler. Cc bit PS2:PS0 (OPTION_REG<2:0>) xc nh t s chia tn s ca prescaler. Xem li thanh ghi OPTION_REG xc nh li mt cch chi tit v cc bit iu khin trn. Cc lnh tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler. Khi i tng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay i i tng tc ng ca prescaler. Khi i tng tc ng l WDT,lnh CLRWDT s xa prescaler, ng thi prescaler s ngng tc v h tr cho WDT Ch : * Thanh ghi lin quan n Timer0: TMR0 (a ch 01h, 101h) : cha gi tr m ca Timer0. (chi tit xem bng ph lc trang 96 ) *Thanh ghi iu khin Timer0: OPTION_REG (a ch 81h, 181h): iu khin prescaler. Thanh ghi ny cho php c v ghi, cho phpiu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc tham s v xung tcng, cnh tc ng ca ngt ngoi vi v b m Timer0.Thanh ghi ty chn cha cc bit iu khin cu hnh cho cc cha nng nh: ngt ngoi, Timer 0 chc nng ko ln Vdd ca cc chn Port B, v thi gian ch ca WDT.
Bit 7 RBPU : Bit cho php PORTB c ko ln ngun. 1: Khng cho php PORTB ko ln ngun. 0: Cho php PORTB ko ln ngun. Bit 6 INTEDG: Bt la chn cnh tc ng ngt (INTERRUPT EDGE) 1: Ngt s c tc ng bi cnh ln ca chn RB0/INT
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Gio trnh Vi iu Khin
0: Ngt s c tc ng bi cnh xung ca chn RB0/INT Bit 5 T0CS: Bit la chn ngun xung Clock cho Timer 0 1: Xung Clock cung cp bi ngun ngoi qua chn RA4/T0CKI 0: Xung Clock cung cp bi ngun dao ng ni. Bit 4 T0SE: Bit la chn cnh no ca xung clock (bn ngoi) tc ng ln timer 0 1: Cnh xung 0: Cnh ln Bit 3 PSA: Bit quyt nh tc m PS2:PS0 s tc ng ln Timer 0 hay WDT 1: Tc m PS2:PS0 s tc ng ln WDT 0: Tc m PS2:PS0 s tc ng ln Timer 0 Bit 2-0 PS2:PS0: Dng la chn tc m ca timer hay WDT
Ch 1: Cc bc vit chng trnh Delay dng Timer0 + Chn chia tn OPTION_REG <20 > + t gi tr vo thanh ghi TMR0 + Cho php b nh thi Timer0 hot ng (cho bit OPTION_REG <5> =0) + Kim tra m xong cha? Kim tra c trn. Ch 2: Cc bc vit chng trnh c xung dng Timer0 a. khng c chia tn (c 1 xung th gi tr trong TRM0 tng 1 n v) BSF OPTION_REG,4; chn tc ng cnh xung BSF OPTION_REG,5 BSF OPTION_REG,3 b. c chia tn (c nhiu xung th gi tr trong TRM0 tng 1 n v, ty thuc vo gi tr chia tn. nu chia tn 1:8 th c 8 xung c v TM0 tng 1 n v) BSF OPTION_REG,4; chn tc ng cnh xung BCF OPTION_REG,3 + thc hin chia tn OPTION_REG <20 >
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Gio trnh Vi iu Khin
BSF
OPTION_REG,5; cho php c xung
V du1: Vit chng trnh con to tr 40ms, thch anh 4Mhz

DELAY BSF BCF BCF BCF BCF BSF BCF MOVLW MOVWF BATDAU MOVLW MOVWF BSF BCF BCF LOOP BTFSS GOTO BCF DECFSZ GOTO RETURN INTCON,2; LOOP INTCON,2; DEM,1; BATDAU m xong cha? Xa c trn Gim gi tr m 1 n v D'55' TMR0; TMR0= 55 STATUS,5 OPTION_REG,5; Cho php b nh thi hot ng STATUS,5 STATUS,5; Chn bank 1 STATUS,6; Chn bank1 OPTION_REG,3 ; Kt qu tc ng ln TMR0 OPTION_REG,2; Chn chia tn 1:4 OPTION_REG,1 OPTION_REG,0 STATUS,5; Tr li bank0 D'50' DEM; Gin gi tr DEM=50
4.1.2.TIMER1 Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh ghi (TMR1H:TMR1L). C ngt ca Timer1 l bit TMR1IF (PIR1<0>). Bit iu khin ca Timer1 s l TMR1IE (PIE<0>).Tng t nh Timer0, Timer1 cng c hai ch hot ng: ch nh thi (timer)vi xung kch l xung clock ca oscillator (tn s ca timer bng tn s ca oscillator) v ch m (counter) vi xung kch l xung phn nh cc s kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI (cnh tc ng l cnh ln). Vic la chn xung tc ng (tng ng vi vic la chn ch hot ng l timer hay counter) c iu khin bi bit TMR1CS (T1CON<1>). Sau y l s khi ca Timer1:
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Gio trnh Vi iu Khin
Hnh 4.8: Cu trc bn trong ca b nh thi Timer1 Ngoi ra Timer1 cn c chc nng reset input bn trong c iu khin bi mt trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set, Timer1 s ly xung clock t hai chn RC1/T1OSI/CCP2 v RC0/T1OSO/T1CKI lm xung m. Timer1 s bt u m sau cnh xung u tin ca xung ng vo. Khi PORTC s b qua s tc ng ca hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit T1OSCEN Timer1 s ly xungm t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 c hai ch m l ng b (Synchronous) v bt ng b (Asynchronous). Ch m c quyt nh bi bit iu khin (T1CON<2>). Khi =1 xung m ly t bn ngoi s khng c ng b ha vi xung clock bn trong, Timer1 s tip tc qu trnh m khi vi iu khin ang ch sleep v ngt do Timer1 to ra khi b trn c kh nng "nh thc" vi iu khin. ch m bt ng b,Timer1 khng th c s dng lm ngun xung clock cho khi CCP(Capture/Compare/Pulse width modulation). Khi =0 xung m vo Timer1 s c ng b ha vi xung clock bn trong. ch ny Timer1 s khng hot ng khi vi iu khin ang ch sleep. Ch : *Cc thanh ghi lin quan n Timer1 bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE). PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF). PIE1( a ch 8Ch): cho php ngt Timer1 (TMR1IE). TMR1L (a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1. TMR1H (a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1. Cc thanh ghi trn chi tit xem bng ph lc trang 96 *Thanh iu khin Timer1:
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Gio trnh Vi iu Khin
T1CON (a ch 10h): xc lp cc thng s cho Timer1.
Bit 7,6 Khng s dng, c l 0. Bit 5,4 T1CKPS1 : T1CKPS0 : Cc bit chn t l xung ng vo cho Timer1. 11 1 : 8 gi tr t l 10 1 : 4 gi tr t l 01 1 : 2 gi tr t l 00 1 : 1 gi tr t l Bit 3 T10SCEN : Bit cho php b dao ng Timer 1 Oscillator 1 : Cho php dao ng 0 : Khng cho php dao ng Bit 2 T1SYNC : Bit la chn ng b ha xung clock ngoi ca Timer 1 (Ch : Bit ny ch c tc dng khi bit TMR1CS = 1) 1: Khng ng b ha xung clock ngoi 0: ng b ha xung clock ngoi. Bit 1 TMR1CS : Bit chn ngun xung clock cho Timer 1 1: Chn xung clock ngoi qua chn T1OSC/T1CKI ( tc ng cnh ln) 0: Chn xung clock ni (Fosc/4) Bit 0 TMR1ON: Bit cho php ngoc ngng Timer 1 1: Cho php 0: Khng cho php Chi tit v cc thanh ghi khc s c trnh by c th trong ph lc 2. Ch : Cc bc vit chng trnh Delay dng Timer1: + Chn chia tn thng qua thanh ghi T1CON + t gi tr vo thanh ghi TMR1 ( 8 bit cao a vo TMR1H, 8 bit thp a vo TMR1L) + Cho php b nh thi Timer0 hot ng (set bit T1CON<0>) + Kim tra m xong cha? Kim tra c trn. V du: Vit chng trnh con to tr 1s, thch anh 4Mhz DELAY BCF STATUS,5 MOVLW b'00000000'; Chn chia tn 1:1 MOVWF T1CON
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Gio trnh Vi iu Khin
MOVLW MOVWF BATDAU MOVLW MOVWF MOVLW MOVWF BSF LOOP BTFSS GOTO BCF DECFSZ GOTO RETURN
d'20'; DEM 3CH TMR1H; AFH TMR1L; T1CON,0; PIR1,0 LOOP PIR1,0 DEM,1; BATDAU
DEM=20
TMR1H=B0011 1100 TMR1L=B1010 1111 => TMR1=15535 Cho php b nh thi hot ng
;m xong cha? Gim gi tr m 1 n v
4.1.3.TIMER2 Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler va postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc ng l TMR2ON (T2CON<2>). C ngt ca Timer2 l bit TMR2IF (PIR1<1>). Xung ng vo (tn s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit (vi cc t s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0 (T2CON<1:0>)).
Hnh 4.9: Cu trc bn trong ca b nh thi Timer2 Timer2 cn c h tr bi thanh ghi PR2. Gi tr m trong thanh ghi TMR2 s tng
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Gio trnh Vi iu Khin
t 00h n gi tr cha trong thanh ghi PR2, sau c reset v 00h. Khi reset thanh ghi PR2 c nhn gi tr mc nh FFh. Ng ra ca Timer2 c a qua b chia tn s postscaler vi cc mc chia t 1:1 n 1:16. Postscaler c iu khin bi 4 bit T2OUTPS3:T2OUTPS0. Ng ra ca postscaler ng vai tr quyt nh trong vic iu khin c ngt. Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn ng vai tr to ra xung clock ng b cho khi giao tip SSP. Ch : *Cc thanh ghi lin quan n Timer2 bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ngt (GIE v PEIE). PIR1 (a ch 0Ch): cha c ngt Timer2 (TMR2IF). PIE1 (a ch 8Ch): cha bit iu khin Timer2 (TMR2IE). TMR2 (a ch 11h): cha gi tr m ca Timer2. Cc thanh ghi trn chi tit xem bng ph lc trang 96 *Thanh iu khin Timer2: T2CON (a ch 12h): xc lp cc thng s cho Timer2.
Bit 7: khng s dng Bit 6:3 TOUTPS3:TOUTPS0: Bit chn t l ng ra ca Timer 2 0000: 1:1 T l ng ra 0001: 1:2 T l ng ra . 1111: 1:16 T l ng ra Bit 2 TMR2ON: Bit cho php hot ng ca Timer 2 1: Cho php 0: Khng cho php. Bit 1:0 T2CKPS1:T2CKPS0: Bit chn t l ng vo ca Timer 2 00 : Prescaler 1 01 : Prescaler 4 1x : Prescaler 16 4.2. ADC ADC (Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t v s. PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hiu in th chun VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn RA2
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Gio trnh Vi iu Khin
v RA3. Kt qu chuyn i t tn tiu tng t sang tn hiu s l 10 bit s tng ng v c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dng b chuyn i ADC, cc thanh ghi ny c th c s dng nh cc thanh ghi thng thng khc. Khi qu trnh chuyn i hon tt, kt qu s c lu vo hai thanh ghi ADRESH:ADRESL, bit ADCON0<2>) c xa v 0 v c ngt ADIF c set.
Hnh 4.10: S khi b chuyn i ADC:
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Gio trnh Vi iu Khin
Hnh 4.11: cch lu kt qu chuyn i AD: Qui trnh chuyn i t tng t sang s bao gm cc bc sau: Bc 1: Chn s ng vo, in p chun Uc. Bc 2: Chn ng vo c th. Bc 3: Chn tn s chuyn i Bc 4: Chn ni cha kt qu chuyn i. Bc 5: Bt b chuyn i, cho php b chuyn i hot ng Bc 6 :Kim tra chuyn i xong cha? c kt qu v. Nu mun tip tc th tr li bc 5. Ch : * Cc thanh ghi lin quan n b chuyn i ADC bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt (cc bit GIE, PEIE). PIR1 (a ch 0Ch): cha c ngt AD (bit ADIF). PIE1 (a ch 8Ch): cha bit iu khin AD (ADIE). ADRESH (a ch 1Eh) v ADRESL (a ch 9Eh):thanh ghi cha kt qu. PORTA (a ch 05h) v TRISA (a ch 85h): lin quan n I/O PORTE (a ch 09h) v TRISE (a ch 89h): lin quan n I/O Cc thanh ghi trn chi tit xem bng ph lc trang 96 * Thanh ghi iu khin ADC: ADCON0 (a ch 1Fh) v ADCON1 (a ch 9Fh): xc lp cc thng s cho b chuyn i AD. - Thanh ghi iu khin ADCON0:
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Gio trnh Vi iu Khin
Bit 7:6 ADCS1:ADCS0: Cc bit la chn tn s chuyn i A/D 00 =FOSC/2 01 =FOSC/4 10 =FOSC/32 11 =FRC (xung clock c ly t dao ng ni RC) Bit 5:3 CHS2:CHS0: Cc bit la chn knh Analog 000: Knh 0, (AN0) 001: Knh 1, (AN1) 010: Knh 2, (AN2) 011: Knh 3, (AN3) 100: Knh 4, (AN4) 101: Knh 5, (AN5) 110: Knh 6, (AN6) 111: Knh 7, (AN7) Bit 2 GO/ DONE: Bit bo trng thi chuyn i A/D Khi bit ADON = 1 1: Qu trnh A/D ang thc hin (Khi chng ta set bit ny ln th qu trnh chuyn i s xy ra, khi qu trnh kt thc n s t ng c xa bng phn mm). 0: Qu trnh A/D khng xy ra hoc hon tt. Bit 1 Khng s dng, gi tr l 0 Bit 0 ADON : Bit cho php module A/D hot ng. 1: Ngun c cung cp cho A/D 0: Ngng cung cp ngun cho A/D - Thanh ghi iu khin ADCON1:
Bit 7 ADFM: Bit la chn nh dng kt qu A/D 1: Canh phi, 6 bit cao nht ca thanh ghi ADRESH c gi tr 0 0: Canh tri, 6 bit thp nht ca thanh ghi ADRESL c gi tr 0 Bit 6 ADCS2: Bit la chn clock chuyn i A/D
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Gio trnh Vi iu Khin
Bit 5,4 khng s dng Bit 3:0 PCFG3:PCFG0: Cc bit iu khin cu hnh cc chn ADC
Chi tit v cc thanh ghi khc s c trnh by c th ph lc trang 94. V du: Vit chng trnh con c ADC t ng RA1, Kt qu c v (8 bit c lu trong ADRESH) Uc =5v, tc chuyn i 1Mhz, thch anh 4Mhz. DOC_ADC BSF STATUS,5 BCF STATUS,6 ;.Chn s ng vo BCF ADCON1,3 BSF ADCON1,2 BCF ADCON1,1 BCF ADCON1,0
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Gio trnh Vi iu Khin
BCF STATUS,5 ;.Chn ng vo BCF ADCON0,5 BCF ADCON0,4 BSF ADCON0,3 ;Chn tn s ly mu. BCF ADCON0,7 BCF ADCON0,6 BSF STATUS,5 BSF ADCON1,6 ;...Chn ni lu kt qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuyn i ADC hot ng. BSF ADCON0,0 BSF ADCON0,2 ;.Chuyn i xong cha? LOOP BCF STATUS, 5 BTFSC ADCON0 ,2 GOTO LOOP RETURN 4.3. PWM_ IU CH RNG XUNG Khi hot ng ch PWM (Pulse Width Modulation _ khi iu ch rngxung), tn hiu sau khi iu ch s c a ra cc pin ca khi CCP (cn n nh cc pin ny l output). Cc bc ci t b PWM: 1. Thit lp thi gian ca 1 chu k ca xung iu ch cho PWM (period) bng cch a gi tr thch hp vo thanh ghi PR2. 2. Thit lp rng xung cn iu ch (duty cycle) bng cch a gi tr vo thanh ghi CCPRxL v cc bit CCP1CON<5:4>.. 3. Thit lp gi tr b chia tn s prescaler ca Timer2 v cho php Timer2 hot ng bng cch a gi tr thch hp vo thanh ghi T2CON. 4. Cho php CCP hot ng ch PWM
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Gio trnh Vi iu Khin
Hnh 4.12: S ca b PWM Trong gi tr 1 chu k (period) ca xung iu ch c tnh bng cng thc: PWM period = [(PR2)+1]*4*TOSC*(gi tr b chia tn s ca TMR2). B chia tn s prescaler ca Timer2 ch c th nhn cc gi tr 1,4 hoc 16 (xem li Timer2 bit thm chi tit). Khi gi tr thanh ghi PR2 bng vi gi tr thanh ghi TMR2 th qu trnh sau xy ra: Thanh ghi TMR2 t ng c xa. Pin ca khi CCP c set. Gi tr thanh ghi CCPR1L (cha gi tr n nh rng xung iu ch duty cycle) c a vo thanh ghi CCPRxH. rng ca xung iu ch (duty cycle) c tnh theo cng thc: PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gi tr b chia tn s TMR2) Nh vy 2 bit CCPxCON<5:4> s cha 2 bit LSB. Thanh ghi CCPRxL cha byte cao ca gi tr quyt nh rng xung. Thanh ghi CCPRxH ng vai tr l buffer cho khi PWM. Khi gi tr trong thanh ghi CCPRxH bng vi gi tr trong thanh ghi TMR2 v hai bit CCPxCON<5:4> bng vi gi tr 2 bit ca b chia tn s prescaler, pin ca khi CCP li c a v mc thp, nh vy ta c c hnh nh ca xung iu ch ti ng ra ca khi PWM nh hnh 4.12 Mt s im cn ch khi s dng khi PWM: Timer2 c hai b chia tn s prescaler v postscaler. Tuy nhin b postscaler khng c s dng trong qu trnh iu ch rng xung ca khi PWM. Nu thi gian duty cycle di hn thi gian chu k xung period th xung ng ra tip tc c gi mc cao sau khi gi tr PR2 bng vi gi tr TMR2. Ch : *Cc thanh ghi lin quan:
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Gio trnh Vi iu Khin
Thanh ghi PIR2: a ch 0Dh TMR2 (a ch 11h): cha gi tr m ca Timer2. T2CON (a ch 12h): xc lp cc thng s cho Timer2 Cc thanh ghi trn chi tit xem bng ph lc trang 96 * Thanh ghi iu khin b PWM Thanh ghi CCP1CON v thanh ghi CCP2CON: a ch 17h (CCP1CON) va 1Dh
(CCP2CON)
CCPXX
CCPXY CCPXMP3 CCPXMP2 CCPXMP1 CCPXMP0 0
Bit 7,6 Khng c tc dng v mc nh mang gi tr 0. Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (cc bit ny khng c tc dng ch Capture v Compare). ch PWM, y l 2 bit MSB cha gi tr tnh rng xung (duty cycle) ca khi PWM (8 bit cn li c cha trong thanh ghi CCPRxL). Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit Cc bit dng xc lp cc ch hot ng ca khi CCPx 0000 khng cho php CCPx (hoc dng reset CCPx) 0100 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh xung ti pin dng cho khi CCPx. 0101 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln ti pin dng cho khi CCPx. 0110 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln th 4 ti pin dng cho khi CCPx. 0111 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln th 16 ti pin dng cho khi CCPx. 1000 CCPx hot ng ch Compare, ng ra c a ln mc cao v bit CCPxIF c set khi cc gi tr cn so snh bng nhau. 1001 CCPx hot ng ch Compare, ng ra c xung mc thp v bit CCPxIF c set khi cc gi tr cn so snh bng nhau. 1010 CCPx hot ng ch Compare, khi cc gi tr cn so snh bng nhau, ngt xy ra, bit CCPxIF c set v trng thi pin output khng b nh hng. 1011 CCPx hot ng ch Compare, khi cc gi tr cn so snh bng nhau, xung trigger c bit (Trigger Special Event) s c to ra, khi c ngt CCPxIF c set, cc pin output khng thay i trng thi, CCp1 reset Timer1, CCP2 reset Timer1 v khi ng khi ADC.
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Gio trnh Vi iu Khin
11xx CCPx hot ng ch PWM. V d1: Vit chng trnh xut ra xung vung ti chn RC2 c tn s 1Khz (thch anh 4Mhz) PWM period = [(PR2)+1]*4*TOSC*(gi tr b chia tn s ca TMR2). = 1000S Ta c: TOSC = 0.25 S, chn gi tr b chia tn s ca TMR2 =1: 4 => PR2 = 250 PWM duty cycle = (CCPR1L:CCP1CON<5:4>)*TOSC*(gi tr b chia tn s TMR2) = 500S => (CCPR1L:CCP1CON<5:4>) = 500= B0111110100 => (CCP1CON<5:4>) = B00 => CCP1L =B01111101 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTC ;..Bc 1.. BSF STATUS,5 BCF TRISC,2 ;..Bc 2.. MOVLW D250 MOVWF PR2 ;..Bc 3. MOVLW B01111101 MOVWF CCPR1L BCF CCP1CON,5 BCF CCP1CON,4 ;..Bc4.. BCF T2CON,1 BSF T2CON,0 BSF T2CON,2; ;Bc5.. BSF CCP1CON,3 BSF CCP1CON,2
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Gio trnh Vi iu Khin
GOTO $ END BI TP THAM KHO CHNG 4 Bi 1: Vit chng trnh iu khin xung vung ti chn RC2 nh sau:Nu nhn nt N1 th xut ra chn RC2 tn s 1Khz, nhn N2 th xut ra chn RC2 tn s 2Khz, nhn N3 th tn s xut ra l 3Khz. (thch anh 4Mhz).
5 V
R N 1 R B 0 P I C N 2 R B 1 1 6 F 8 7 7 A R C 2
R B 2
Hnh 4.13 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H DEM1 EQU 21H ORG 0000H BCF BCF CLRF CLRF BSF BCF BSF BSF BSF MAIN BCF STATUS,5;
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STATUS,6 STATUS,5 PORTC PORTB STATUS,5; TRISC,2 TRISB,0 TRISB,1 TRISB,2 BANK1
BANK0
Gio trnh Vi iu Khin
BTFSS GOTO BTFSS GOTO BTFSS GOTO GOTO KT_0 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO KT_1 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO KT_2 BTFSS GOTO MOVLW MOVWF MOVLW MOVWF GOTO TAO_XUNG
PORTB,0 KT_0 PORTB,1 KT_1 PORTB,2 KT_2 MAIN PORTB,0 KT_0 D'250' DEM D'127' DEM1 TAO_XUNG PORTB,1 KT_1 D'125' DEM D'64' DEM1 TAO_XUNG PORTB,2 KT_2 D'63' DEM D'32' DEM1 TAO_XUNG
;.BUOC2. BCF STATUS,5; MOVF DEM,0 BSF STATUS,5 MOVWF PR2

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BANK1
Gio trnh Vi iu Khin
;.BUOC3. BCF STATUS,5; BANK0 MOVF DEM1,0 MOVWF CCPR1L BCF CCP1CON,5 BCF CCP1CON,4 ; BUOC4. BCF T2CON,1 BSF T2CON,0 BSF T2CON,2; CHO TIMER2 HOAT DONG ;.. BUOC5. BSF CCP1CON,3 BSF CCP1CON,2 GOTO MAIN END Bi 2: Vit chng trnh m xung (t chn RA4),sau mi giy ri xut ra portB PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 22H ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 CLRF TRISB BCF STATUS,5 CLRF TMR0 BSF STATUS,5 MAIN BSF OPTION_REG,4 ; tac dong canh xuong BSF OPTION_REG,5 BSF OPTION_REG,3 LOOP CALL DELAY_1S BCF STATUS,5 MOVF TMR0,W
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Gio trnh Vi iu Khin
MOVWF CLRF GOTO DELAY_1S BCF MOVLW MOVWF MOVLW MOVWF BATDAU MOVLW MOVWF MOVLW MOVWF BSF LOOP1 BTFSS GOTO BCF DECFSZ GOTO RETURN END
PORTB TMR0 LOOP STATUS,5 B'00100000' T1CON D'20' DEM 3CFH TMR1H 0AFH TMR1L T1CON,0 PIR1,0 LOOP1 PIR1,0 DEM,1 BATDAU
Bi 3: Vit chng trnh c ADC t ng RA0, Kt qu c v (8 bit cao c lu trong ADRESH, Uc = 4.5V, tc chuyn i 1Mhz, thch anh 4Mhz) xut ra portB. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB BSF STATUS,5 CLRF TRISB MAIN CALL DOC_ADC MOVF ADRESH,0
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Gio trnh Vi iu Khin
MOVWF GOTO DOC_ADC
PORTB MAIN
BSF STATUS,5 BCF STATUS,6 ;.Chn s ng vo BCF ADCON1,3 BCF ADCON1,2 BCF ADCON1,1 BSF ADCON1,0 BCF STATUS,5 ;.Chn ng vo BCF ADCON0,5 BCF ADCON0,4 BCF ADCON0,3 ;Chn tn s ly mu. BCF ADCON0,7 BCF ADCON0,6 BSF STATUS,5 BSF ADCON1,6 ;...Chn ni lu kt qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuyn i ADC hot ng. BSF ADCON0,0 BSF ADCON0,2 ;.Chuyn i xong cha? LOOP BCF STATUS, 5 BTFSC ADCON0 ,2 GOTO LOOP RETURN END
CHNG 5
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Gio trnh Vi iu Khin
CC CNG NI TIP
5.1. USART USART (Universal Synchronous Asynchronous Receiver
Transmitter) la mot trong hai chuan giao tiep noi tiep.USART con c goi la giao dien giao tiep noi tiep noi tiep SCI (Serial Communication Interface). Co the s dung giao dien nay cho cac giao tiep vi cac thiet b ngoai vi, vi cac vi ieu khien khac hay vi may tnh. Cac dang cua giao dien USART ngoai vi bao gom: Bat ong bo (Asynchronous). ong bo_ Master mode. ong bo_ Slave mode. Hai pin dung cho giao dien nay la RC6/TX/CK va e truyen xung clock
RC7/RX/DT, trong o RC6/TX/CK dung
(baud rate) va RC7/RX/DT dung e truyen data. Trong trng hp nay ta phai set bit TRISC<7:6> va SPEN (RCSTA<7>) c0e cho phep giao dien USART. PIC16F877A c tch hp san bo tao toc o baud BRG (Baud Rate Genetator) 8 bit dung cho giao dien USART. BRG thc chat la mot bo em co the c s dung cho ca hai dang ong bo va bat ong bo va c ieu khien bi thanh ghi PSBRG. dang bat ong bo, BRG con c ieu khien bi bit BRGH ( TXSTA<2>). dang ong bo tac ong cua bit BRGH c bo qua. Toc o baud do BRG tao ra c tnh theo cong thc sau:
Trong o X la gia tr cua thanh ghi RSBRG ( X la so nguyen va 0<X<255). Cac thanh ghi lien quan en BRG bao gom: TXSTA (a ch 98h): chon che o ong bo hay bat ong bo ( bit SYNC) va chon mc toc o baud (bit BRGH). RCSTA (a ch 18h): cho phep hoat ong cong noi tiep (bit SPEN).
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Gio trnh Vi iu Khin
RSBRG (a ch 99h): quyet nh toc o baud.
5.2. CH LM VIC 5.2.1. TRUYN D LIU BT NG B Thnh phn quan trng nht ca khi truyn d liu l thanh ghi dch d liu TSR (Transmit Shift Register). Thanh ghi TSR s ly d liu t thanh ghi m dng cho qu trnh truyn d liu TXREG. D liu cn truyn phi c a trc vo thanh ghi TXREG. Ngay sau khi bit Stop ca d liu cn truyn trc c truyn xong, d liu t thanh ghi TXREG s c a vo thanh ghi TSR, thanh ghi TXREG b rng, ngt xy ra v c hiu TXIF (PIR1<4>) c set. Ngt ny c iu khin bi bit TXIE (PIE1<4>). C hiu TXIF vn c set bt chp trng thi ca bit TXIE hay tc ng ca chng trnh (khng th xa TXIF bng chng trnh) m ch reset v 0 khi c d liu mi c a vo thanhh ghi TXREG.
Hnh 5.1: S ca b truyn ni tip Trong khi c hiu TXIF ng vai tr ch th trng thi thanh ghi TXREG th c hiu TRMT (TXSTA<1>) c nhim v th hin trng thi thanh ghi TSR. Khi thanh ghi TSR rng, bit TRMT s c set. Bit ny ch c v khng c ngt no c gn vi trng thi ca n. Mt im cn ch na l thanh ghi TSR khng c trong b nh d liu v ch c iu khin bi CPU. Khi truyn d liu c cho php hot ng khi bit TXEN (TXSTA<5>) c set. Qu trnh truyn d liu ch thc s bt u khi c d liu trong thanh ghi TXREG v xung truyn baud c to ra. Khi khi truyn d liu c khi ng ln u tin, thanh ghi TSR rng. Ti thi im , d liu a vo thanh ghi TXREG ngay lp tc c load vo thanh ghi TSR v thanh ghi TXREG b rng. Lc ny ta c th hnh thnh mt chui d liu lin tc cho qu trnh truyn d liu. Trong qu trnh truyn d liu nu bit TXEN
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Gio trnh Vi iu Khin
b reset v 0, qu trnh truyn kt thc, khi truyn d liu c reset v pin RC6/TX/CK chuyn n trng thi high-impedance. Trong trng hp d liu cn truyn l 9 bit, bit TX9 (TXSTA<6>) c set v bit d liu th 9 s c lu trong bit TX9D (TXSTA<0>). Nn ghi bit d liu th 9 vo trc, v khi ghi 8 bit d liu vo thanh ghi TXREG trc c th xy ra trng hp ni dung thanh ghi TXREG s c load vo thanh ghi TSG trc, nh vy d liu truyn i s b sai khc so vi yu cu. Tm li, truyn d liu theo giao din USART bt ng b, ta cn thc hin tun t cc bc sau: 1. To xung truyn baud bng cch a cc gi tr cn thit vo thanh ghi SPBRG v bit iu khin mc tc baud BRGH. 2. Cho php cng giao din ni tip ni tip bt ng b bng cch clear bit SYNC v set bit PSEN. 3. a 8 bit d liu cn truyn vo thanh ghi TXREG. 4. Set bit TXIE nu cn s dng ngt truyn. 5. Set bit TX9 nu nh dng d liu cn truyn l 9 bit. 6. Set bit TXEN cho php truyn d liu (lc ny bit TXIF cng s c set). 7. Nu nh dng d liu l 9 bit, a bit d liu th 9 vo bit TX9D. 8. Nu s dng ngt truyn, cn kim tra li cc bit GIE v PEIE (thanh ghi INTCON) Ch : * Cc thanh ghi lin quan: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php tt c cc ngt. Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt truyn TXIE. Thanh ghi RCSTA (a ch 18h): cha bit cho php cng truyn d Thanh ghi TXREG (a ch 19h): thanh ghi cha d liu cn truyn. Thanh ghi SPBRG (a ch 99h): quyt nh tc baud. Chi tit xem bng ph lc trang 96 * Thanh ghi iu khin b truyn ni tip: Thanh ghi PIR1 (a ch 0Ch): cha c hiu TXIF Thanh ghi TXSTA (a ch 98h): Thanh ghi cha cc bit trng thi v iu khin vic truyn d liu thng qua chun giao tip USART. CSRC Bit 7 TX-9 TXEN SYNC BRGH TRMT TX9D Bit 0
Bit 7 CSRC Clock Source Select bit ch bt ng b: khng cn quan tm. ch ng b: CSRC = 1 Master mode (xung clock c ly t b to xung BRG).
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Gio trnh Vi iu Khin
CSRC = 0 Slave mode (xung clock c nhn t bn ngoi). Bit 6 TX-9 9-bit Transmit Enable bit TX-9 = 1 truyn d liu 9 bit. TX-9 = 0 truyn d liu 8 bit. Bit 5 TXEN Transmit Enable bit TXEN = 1 cho php truyn. TXEN = 0 khng cho php truyn. Bit 4 SYNC USART Mode Select bit SYNC = 1 dng ng b SYNC = 0 dng bt ng b. Bit 3 Khng cn quan tm v mc nh mang gi tr 0. Bit 2 BRGH High Baud Rate Select bit, Bit ny ch c tc dng ch bt ng b. BRGH = 1 tc cao. BRGL = 0 tc thp. Bit 1 TRMT Transmit Shift Register Status bit TRMT = 1 thanh ghi TSR khng c d liu. TRMT = 0 thanh ghi TSR c cha d liu. Bit 0 TX9D Bit ny cha bit d liu th 9 khi d liu truyn nhn l 9 bit. V d: Vit on chng trnh nhn d liu t PORTB sau xut ra Port ni tip, ch 8 bit, Baud rate =9600, Fosc = 4Mhz. TRUYEN_NOI_TIEP ;Chn baud rate BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRG ;Cho php cng ni tip hot ng.. BCF TXSTA, SYNC BSF RCSTA, SPEN ;Xut gi tr cn truyn vo thanh ghi TXREG. LOOP MOVF PORTB,W MOVWF TXREG ;Cho php truyn BSF TXSTA, TXEN
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Gio trnh Vi iu Khin
;Truyn xong cha? LOOP1 BTFSS PIR1,TXIF GOTO LOOP1 NOP GOTO LOOP RETURN 5.2.2. NHN D LIU BT NG B D liu c a vo t chn RC7/RX/DT s kch hot khi phc hi d liu. Khi phc hi d liu thc cht l mt b dch d liu ctc cao va c tn s hot ng gp 16 ln hoc 64 ln tn s baud. Trong khi tc dch ca thanh thanh ghi nhn d liu s bng vi tn s baud hoc tn s ca oscillator.
Hnh 5.2: S ca b truyn ni tip Bit iu khin cho php khi nhn d liu l bit RCEN (RCSTA<4>). Thnh phn quan trng nht ca khi nhn d liu l thsnh ghi nhn d liu RSR (Receive Shift Register). Sau khi nhn din bit Stop ca d liu truyn ti, d liu nhn c trong thanh ghi RSR s c a vo thanh ghi RCGER, sau c hiu RCIF (PIR1<5>) s c set v ngt nhn c kch hot. Ngt ny c iu khin bi bit RCIE (PIE1<5>). Bit c hiu RCIF l bit ch c v khng th c tc ng bi chng trnh. RCIF ch reset v 0 khi d liu nhn vo thanh ghi RCREG c c v khi thanh ghi RCREG rng. Thanh ghi RCREG l thanh ghi c b m kp (double-buffered register) v hot ng theo c ch FIFO (First In First Out) cho php nhn 2 byte v byte th 3 tip tc c a vo thanh ghi RSR. Nu sau khi nhn c bit Stop ca byte d liu th 3 m thanh ghi
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Gio trnh Vi iu Khin
RCREG vn cn y, c hiu bo trn d liu (Overrun Error bit) OERR(RCSTA<1>) s c set, d liu trong thanh ghi RSR s b mt i v qu trnh a d liu t thanh ghi RSR vo thanh ghi RCREG s b gin on. Trong trng hp ny cn ly ht d liu thanh ghi RSREG vo trc khi tip tc nhn byte d liu tip theo. Bit OERR phi c xa bng phn mm v thc hin bng cch clear bit RCEN ri set li. Bit FERR (RCSTA<2>) s c set khi pht hin bit Stop da d liu c nhn vo. Bit d liu th 9 s c a vo bit RX9D (RCSTA<0>). Khi c d liu t thanh ghi RCREG, hai bit FERR v RX9D s nhn cc gi tr mi. Do cn c d liu t thanh ghi RCSTA trc khi c d liu t thanh ghi RCREG trnh b mt d liu. Tm li, khi s dng giao din nhn d liu USART bt ng b cn tin hnh tun t cc bc sau: 1. Thit lp tc baud (a gi tr thch hp vo thanh ghi SPBRG v bit BRGH. 2. Cho php cng giao tip USART bt ng b (clear bit SYNC v set bit SPEN). 3. Nu cn s dng ngt nhn d liu, set bit RCIE. 4. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 5. Cho php nhn d liu bng cch set bit CREN. 6. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot (nu bit RCIE c set). 7. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu trnh nhn d liu c b li khng. 8. c 8 bit d liu t thanh ghi RCREG. 9. Nu qu trnh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 10. Nu s dng ngt nhn cn set bit GIE v PEIE (thanh ghi INTCON). Ch : * Cc thanh ghi lin quan: Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php ngt Thanh ghi PIE1 (a ch 8Ch): cha bit cho php ngt RCIE. Thanh ghi RCREG (a ch 1Ah): cha d liu nhn c. Thanh ghi TXSTA (a ch 98h): cha cc bit iu khin SYNC v BRGH. Thanh ghi SPBRG (a ch 99h): iu khin tc baud. Chi tit cc thanh ghi xem bng ph lc trang 96 * Thanh ghi iu khin b nhn ni tip: Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. Thanh ghi RCSTA: (a ch 18h)Thanh ghi cha cc bit trng thi v cc bit iu khin qu trnh nhn d liu qua chun giao tip USART. SPEN Bit 7 RX9 SREN CREN ADDEN
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FERR
OERR
RX9D Bit 0
Gio trnh Vi iu Khin
Bit 7 SPEN Serial Port Enable bit SPEN = 1 Cho php cng giao tip USART (pin RC7/RX/DT v RC6/TX/CK). SPEN = 0 khng cho php cng giao tip USART. Bit 6 RX9 9-bit Receive Enable bit RX9 = 1 nhn 9 bit d liu. RX9 = 0 nhn 8 bit d liu. Bit 5 SREN Single Receive Enable bit ch USART bt ng b: bit ny khng cn quan tm. ch USART Master ng b: SREN = 1 cho php chc nng nhn 1 byte d liu (8 bit hoc 9 bit). SREN = 0 khng cho php chc nng nhn 1 byte d liu. Bit 4 CREN Continous Receive Enable bit ch bt ng b: CREN = 1 cho php nhn 1 chui d liu lin tc. CREN = 0 khng cho php nhn 1 chui d liu lin tc. ch bt ng b: CREN = 1 cho php nhn d liu cho ti khi xa bit CREN. CREN = 0 khng cho php nhn chui d liu. Bit 3 ADDEN Address Detect Enable bit ch USART bt ng b 9 bit ADDEN = 1 cho php xc nhn a ch, khi bit RSR<8> c set th ngt c cho php thc thi v gi tr trong buffer c nhn vo. ADDEN = 0 khng cho php xc nhn iz5 ch, cc byte d liu c nhn vo v bit th 9 c th c s dng nh l bit parity. Bit 2 FERR Framing Eror bit FERR = 1 xut hin li "Framing" trong qu trnh truyn nhn d liu. FERR = 0 khng xut hin li "Framing" trong qu trnh truyn nhn d liu. Bit 1 OERR Overrun Error bit, OERR = 1 xut hin li "Overrun" OERR = 0 khng xut hin li "Overrun" Bit 0 RX9D Bit ny cha bit d liu th 9 ca d liu truyn nhn V d: Vit on chng trnh c d liu t Port ni tip, sau xut g tr c v ra PORTD Baud rate =9600, Fosc = 4Mhz.
NHAN_NOI_TIEP
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Gio trnh Vi iu Khin
; Chn baud rate . BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRG ; Cho php cng ni tip hot ng BCF TXSTA, SYNC BSF RCSTA, SPEN ;Cho php nhn d liu BAT_DAU BSF RCSTA,CREN ;Nhn xong cha?.. LOOP BTFSS PIR1, RCIF GOTO LOOP ;C li khng? BTFSS RCSTA, OERR GOTO DOC_VE BCF RCSTA, CREN GOTO BAT_DAU ;c kt qu v DOC_VE MOVF RCREG,W MOVWF PORTD GOTO LOOP RETURN BI TP THAM KHO CHNG 5 Bi 1: Vit chng trnh c d liu t Port ni tip ( Baud rate =9600, ch 8 bit, thch anh = 4Mhz), kim tra kt qu c v. Nu l s l th xut ra PortB, ngc li khng xut. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TEMP EQU 20H ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB CLRF PORTC
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BSF CLRF BCF BCF MAIN CALL BTFSS GOTO MOVF MOVWF GOTO LOOP1
STATUS,5 TRISB TRISC,6 TRIC,7 DOC_NOI_TIEP TEMP,0 LOOP1 TEMP,0 PORTB MAIN
CLRF RCREG GOTO MAIN DOC_NOI_TIEP ; Chn baud rate . BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRG ; Cho php cng ni tip hot ng BCF TXSTA, SYNC BSF RCSTA, SPEN ;Cho php nhn d liu BAT_DAU BSF RCSTA,CREN ;Nhn xong cha?.. LOOP BTFSS PIR1, RCIF GOTO LOOP ;C li khng? BTFSS RCSTA, OERR GOTO DOC_VE BCF RCSTA, CREN GOTO BAT_DAU ;c kt qu v DOC_VE MOVF RCREG,W
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Gio trnh Vi iu Khin
MOVWF RETURN END
TEMP
Bi 2: Vit on chng trnh xut 30byte trong Ram ni, byte u tin c a ch 22H ra Port ni tip (Baud rate =9600, ch 8 bit, thch anh = 4Mhz) PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H TEMP EQU 21H ORG 0000H BCF STATUS,6 BCF STATUS,5 CLRF PORTB CLRF PORTC BSF STATUS,5 BCF TRISC,6 BCF TRIC,7 BCF STATUS,5
MAIN MOVLW MOVWF MOVLW MOWF BAT_DAU MOVF MOVWF CALL DECFSZ GOTO GOTO TIEP INCF GOTO THOAT NOP GOTO TRUYEN_NOI_TIEP $ FSR,1 MAIN INDF,0 TEMP TRUYEN_NOI_TIEP DEM TIEP THOAT D30 DEM 22H FSR
;Chn baud rate

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LOOP1
BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRG ;Cho php cng ni tip hot ng.. BCF TXSTA, SYNC BSF RCSTA, SPEN ;Xut gi tr cn truyn vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truyn BSF TXSTA, TXEN ;Truyn xong cha? BTFSS PIR1,TXIF GOTO LOOP1 NOP RETURN
END
Bi 3: Vit chng trnh xut kim tra trong Ram ni (bank0) nu k t ch hoa (A, B,CZ) th xut ra Port ni tip ( Baud rate =19200, ch 8 bit, thch anh = 4Mhz).Ngc li, khng xut. Bit ch A c m ASCH l 65. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> TEMP EQU A1H DEM EQU A0H ORG 0000H BCF BCF CLRF CLRF BSF CLRF BSF BSF
MAIN MOVLW MOVWF MOVLW D97 DEM 20H 77
STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,6 TRIC,7
Gio trnh Vi iu Khin MOVWF LOOP DECFSZ GOTO GOTO MOVF MOVWF MOVLW SUBWF BTFSS GOTO INCF GOTO TIEP MOVLW SUBWF BTFSS GOTO GOTO BO_QUA INCF GOTO XUAT FSR,1 LOOP D92 TEMP,0 STATUS,0 BO_QUA XUAT FSR DEM BAT_DAU $ INDF,0 TEMP D65 TEMP,0 STATUS,0 TIEP FSR,1 LOOP
BAT_DAU
BCF TXSTA, BRGH MOVLW D12 MOVWF SPBRG ;Cho php cng ni tip hot ng.. BCF TXSTA, SYNC BSF RCSTA, SPEN ;Xut gi tr cn truyn vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truyn BSF TXSTA, TXEN ;Truyn xong cha? LOOP1 BTFSS PIR1,TXIF
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Gio trnh Vi iu Khin
GOTO INCF GOTO END
LOOP1 FSR,1
LOOP
CHNG 6
NGT - INTERRUPT
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6.1 KHI NIM 6.1.1. GII THIU u tin, Ngt (interrupt) l ci g?, n tht s c ngha ging nh tn gi ca n, mt Interrupt l mt tc v x l hay l mt tn hiu x l m n c th bt con Pic dng li nhng g ang lm lm mt cng vic khc. Mt v d d hiu, hy ly sinh hot hng ngy ca bn, gi s bn ang ngi nh, ri bn ang tn gu vi ai ,thnh lnh chung in thoi reo, bn ngng cuc ni chuyn li, nht in thoi ln v ni chuyn vi ngi gi n. Khi bn kt thc cuc ni chuyn bng in thoi bn li quay tr v v tip tc tn gu vi ngi ni chuyn vi bn trc khi in thoi reo.By gi bn hy tng tng, chng trnh chnh l qu trnh tn gu ca bn vi ngi bn ngi nh, in thoi reo to ra mt Interrupt v th tc (routine) Interrups l cuc ni chuyn vi ngi u dy bn kia, khi kt thc cuc ni chuyn bng in thoi bn quay v chng trnh chnh tip tc tn gu. V d ny gii thch chnh xc mt Interrups to ra mt tin trnh x l nh th no. Mt chng trnh chnh ang chy, thc hin mt vi chc nng no trn mch in, nhng khi Interrupt xy ra chng trnh chnh s tm ngng v ngay lc mt th tc khc c thc hin, khi th tc ny kt thc con Pic s li quay v chng trnh chnh. Con Pic c 15 ngun ngt, khi ngt c xy ra cn: khai bo ngt (Set cc bit iu khin IE tng ng) v c c ngt tc ng (IF), bit ngt nh th no chng ta cn xem s sau:
Hnh 6.1: Gin ngt Ch thch:
Cc Bt iu khin ngt + Bt GIE: INTCON<7> Cho php ngt ton cc

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+ Bt PEIE: INTCON<6> Cho php ngt ngoi vi + Bt RBIE: INTCON<3> Cho php ngt PortB + Bt INTE: INTCON<4> Cho php ngt RB0 + Bt TMR0IE: INTCON<3> Cho php ngt Timer0 + Bt FEIE: PIE2<4> Cho php ngt EFROM + Bt PSPIE: PIE1<7> Cho php ngt truyn song song + Bt ADIE: PIE1<6> Cho php ngt chuyn i ADC + Bt RCIE: PIE1<5> Cho php ngt nhn ni tip + Bt TXIE: PIE1<4> Cho php ngt truyn ni tip + Bt SSPIE: PIE1<3> Cho php ngt truyn nhn ni tip ang bn + Bt CCP1IE: PIE1<2> Cho php ngt b CCP1 + Bt TMR1IE: PIE1<0> Cho php ngt Timer1 + Bt TMR2IE: PIE1<1> Cho php ngt Timer2 + Bt CCP2IE: PIE2<0> Cho php ngt b CCP2 + Bt BCLIE: PIE2<3> Cho php ngt truyn nhn ni xy ra + Bt CMIE: PIE2<6> Cho php ngt b so snh Cc Bt c ngt + Bt RBIF: INTCON<0> C ngt PortB + Bt INTF: INTCON<1> C ngt RB0 + Bt TMR0IF: INTCON<2> C ngt Timer0 + Bt FEIF: PIR2<4> C ngt EFROM + Bt PSPIF: PIR1<7> C ngt truyn song song + Bt ADIF: PIR1<6> C ngt chuyn i ADC + Bt RCIF: PIR1<5> C ngt nhn ni tip + Bt TXIF: PIR1<4> C ngt truyn ni tip + Bt SSPIF: PIR1<3> C ngt truyn nhn ni tip ang bn + Bt CCP1IF: PIR1<2> C ngt b CCP1 + Bt TMR1IF: PIR1<0> C ngt Timer1 + Bt TMR2IF: PIR1<1> C ngt Timer2 + Bt CCP2IF: PIR2<0> C ngt b CCP2 + Bt BCLIF: PIR2<3> C ngt truyn nhn ni xy ra + Bt CMIF: PIR2<6> C ngt b so snh Gi s trong chng trnh chnh chng ta c s dng Timer0. khi chng trnh ang thc thi, nu b nh thi Timer0 m xong s bo cho chng ta bit thng qua c trn TR0IF. Vy n chng ta dng ngt Timer0 th chng ta cn SET bit TMR0IE v SET bit GIE. Tng t nu chng ta cn dng ngt ngoi vi RB th cn SET bit RBIE v
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SET bit GIE. Tuy nhin, chng ta cn ngt Timer1 th ngoi vic cn SET bit TMR1IE v SET bit GIE v cn SET thm bit PEIE =>Da vo s trn chng ta cn Set bit no khi khai bo ngt. 6.1.2. CU TRC CHNG TRNH C DNG NGT ORG 0000H ; a ch RESET GOTO MAIN ; Nhy vo chng trinh chnh ;..INTERRUPT ROUTINE. ORG 04H ; a ch vect ngt Lu cc gi tr tm thi vo Ram ni ( Nu cc gi tr ny thay i khi thc thi chng trnh ngt)
Thc thi chng trnh ngt Thot ngt - Tr cc gi tr t Ram ni vo cc thanh ghi lu - Xa c ngt RETFIE ; kt thc chng trnh ngt ; MAIN PROGRAM.
MAIN
Khai bo ngt (Chng ta khai bo l ngt g? Ngt ngoi vi, ngt timer hay ngt ADC.) Thc thi chng trnh chnh Vng lp v hn
END
on chng trnh trn ta thy, khi bt u ngay im nhp RESET gp lnh Goto MAIN khi chng trnh thc thi chng trnh chnh. Trong sut qu trnh thc thi nu c ngt xy ra ( ging nh bn ang tn gu vi ai ,thnh lnh chung in thoi reo) th chng trnh lp tc tm ngng tr v a ch vect ngt ORG 04H thc thi chng trnh ngt (bn ngng cuc ni chuyn li, nht in thoi ln vni chuyn vi ngi gi n). Khi kt thc chng trnh ngt gp lnh RETFIE th chng trnh tr li ni n ra i (ging nh bn nghe in thoi xong tr li vi tn gu tip cu chuy c dang d). 6.2 NGT RB0 Ngt ny da trn s thay i trng thi ca pin RB0/INT. Cnh tc ng gy ra ngt c th l cnh ln hay cnh xung v c iu khin bi bit INTEDG (thanh ghi OPTION_REG <6>). Khi c cnh tc ng thch hp xut hin ti pin RB0/INT, c ngt INTF c set bt chp trng thi cc bit iu khin GIE v PEIE. Thanh ghi OPTION chnh l thanh ghi thit lp ch cho Interrupt tch cc cnh ln hay cnh xung ca tn hiu vo, Bit 6 ca thanh ghi OPTION c gi l INTEDG, nu Set Bit6 s thit lp interrupt tch cc cnh ln ca tn hiu vo (trng thi
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default), nu Clear Bit6 s thit lp interrupt tch cc cnh xung ca tn hiu vo. Mc nhin sau khi bt ngun con Pic s thit lp ch Interrupt cnh ln, c ngha l interrup xy ra khi tn hiu vo thay i t thp ln cao (cnh ln). V d: Cho s nh hnh v, vit chng trnh cho tha: Mi ln nhn nt N, bung ra gi tr trn Led 7 on tng 1 n v
Hnh 6.2 PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H ORG 0000H GOTO MAIN ORG 04H MOVWF TEMP INCF DEM,1 MOVLW D'10' XORWF DEM,0 BTFSC STATUS,2 CLRF DEM MOVF TEMP,W BCF INTCON,1 RETFIE MAIN
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BSF BSF BCF BSF CLRF BCF CLRF LOOP MOVF MOVWF GOTO END
6.3. NGT PORTB
INTCON,7 INTCON,4 STATUS,6 STATUS,5 TRISD STATUS,5 DEM DEM,W PORTD LOOP
Tng t nh ngt RB0, nhng da vo s bin i trng thi ca cc chn t RB4RB7. Tc l khi RB4RB7 c s bin i trng thi th c ngt RBIF tch cc mc cao. Vy s dng ngt PortB trong chng trnh chnh chng ta cn Set bit RBIE (INTCON<4>) v Set bit GIE (INTCON<7>) V d: Vit chng trnh cho mch chng trm, 4 ng vo (RB4RB7), 1 ng ra (RA0). Mt trong 4 ng vo c tc ng ng ra tch cc mc cao. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO MAIN ORG 04H GOTO NGAT MAIN BSF INTCON,7 BSF INTCON,3 BCF BSF BCF GOTO NGAT BCF BCF STATUS,6 STATUS,5
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STATUS,6 STATUS,5 TRISA,0 $
Gio trnh Vi iu Khin
BSF BCF RETFIE END

6.4. NGT TIMER
PORTA,0 INTCON,0
Nh chng ta bit, gi tr trong b Timer s tng theo mi xung nhp tc ng, i vi Timer0 v Timer2 th khi thanh ghi TMR0 hoc TMR2 t gi tr FFH (255) th khi c trn TMR0IF hoc TMR2IF s tch cc mc cao. Ring i vi Timer1 c trn TMR1IF t gi tr tch cc mc cao th gi tr trong thanh TMR1 (16 Bit gm 2 thanh ghi TMR1H v TMR1L) phi t gi tr l FFFFH (65535) s dng ngt TIMER chng ta bit r mnh s dng Timer no m Set Bit TMRXIE tng ng khi khai bo, ng thi Set Bit PEIE v Bit GIE (ring i Timer0 th khng cn Set Bit PEIE) V d: Vit chng trnh to xung vung ti chn RD0, tn s f=10hz, dng ngt PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO MAIN ORG 04H BCF STATUS,6 BCF STATUS,5 MOVLW B'00000001' XORWF PORTD,1 BCF PIR1,0 MOVLW 3CH MOVWF TMR1H MOVLW 0AFH MOVWF TMR1L RETFIE MAIN BSF INTCON,7 BSF INTCON,6 BCF STATUS,6 BSF STATUS,5 BSF PIE1,0 BCF STATUS,6
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BCF CLRF BSF BCF BCF LOOP MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF GOTO END
6.5. NGT ADC
STATUS,5 PORTD STATUS,5 TRISD,0 STATUS,5 B'00000000' T1CON 3CH TMR1H 0AFH TMR1L T1CON,0 $
i vi b chuyn i ADC sau khi thit lp cc ch (Chn ng vo, in p chun, tn s chuyn i) xong, sau cho b chuyn i ADC bt u hot ng thng qua bit ADON (ADCON0 <2>). Mt thi gian sau, khong vi trm S th qu trnh chuyn i hon tt, khi c ngt ADIF c Set ln mc cao. Nu chng ta Set cc Bit ADIE, PEIE v Bit GIE th khi ngt s xy ra. V d: Lm li bi tp 3 chng 4 (trang 67), dng ngt PROCESSOR 16F877A #INCLUDE <P16F877A.INC> ORG 0000H GOTO MAIN ORG 04H GOTO NGAT_ADC MAIN BSF INTCON,7 BSF INTCON,6 BSF PIE1,6 BSF STATUS,5 BCF STATUS,6 ;.Chn s ng vo BCF ADCON1,3 BCF ADCON1,2
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BCF ADCON1,1 BSF ADCON1,0 ;.Chn ng vo BCF STATUS,5 BCF ADCON0,5 BCF ADCON0,4 BCF ADCON0,3 ;Chn tn s ly mu. BCF ADCON0,7 BCF ADCON0,6 BSF STATUS,5 BSF ADCON1,6 ;...Chn ni lu kt qu BCF ADCON1,7 BCF STATUS,5 ; Cho php b chuyn i ADC hot ng. STAR BSF ADCON0,2 BSF ADCON0,0 ;.Chuyn i xong cha? BCF STATUS, 5 LOOP BTFSC PIR1,6 GOTO LOOP NOP GOTO STAR NGAT_ADC MOVF ADRESH,0 MOVWF PORTB BCF PIR1,6 RETFIE END
6.6. NGT PORT NI TIP
Tng t nh ngt ADC, i vi truyn nhn ni tip, khi truyn (nhn) xong 1 byte th c ngt Set ln mc cao. ngt xy ra ta Set cc Bit iu khin tng ng, i vi truyn ni tip chng ta cn Set 3 Bit iu khin trong khi khai bo:GIE, PEIE v TXIE. Cn i vi nhn ni tip th cc Bt cn Set: GIE, PEIE v RCIE V d: Lm li bi tp 2 chng 5 (trang 78), dng ngt
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PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 20H TEMP EQU 21H ORG 0000H GOTO MAIN ORG 04H GOTO NGAT_TRUYEN
MAIN
BSF BSF BSF BCF BCF CLRF BSF BCF BCF BCF
MOVLW MOVWF MOVLW MOWF TRUYEN_NOI_TIEP
INTCON,7 INTCON,6 PIE1,4 STATUS,6 STATUS,5 PORTC STATUS,5 TRISC,6 TRIC,7 STATUS,5
D30 DEM 22H FSR
;Chn baud rate.. BSF TXSTA, BRGH MOVLW D25 MOVWF SPBRGN ; Cho php cng ni tip hot ng.. BCF TXSTA, SYNC BSF RCSTA, SPEN ;Xut gi tr cn truyn vo thanh ghi RCREG MOVF TEMP,0 MOVWF TXREG ;Cho php truyn BSF TXSTA, TXEN ;Truyn xong cha? Nu truyn xong th vo ngt, ri tr li, truyn tip.
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LOOP1 BTFSS GOTO NOP GOTO NGAT_TRUYEN

DECFSZ GOTO GOTO TIEP INCF MOVF MOVWF BCF RETFIE END FSR,1 INDF,0 TEMP PIR1,4
PIR1,TXIF LOOP1
TRUYEN_NOI_TIEP DEM TIEP $
BI TP THAM KHO CHNG 6 Bi 1: Nu RB0 tc ng cnh ln th xut ra chn RC2 mt chui xung c tn s f=1Khz trong 3 giy. PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU 22H ORG 0000H GOTO MAIN ORG 04H GOTO NGAT MAIN BCF STATUS,6 BCF STATUS,5 BSF INTCON,7 BSF INTCON,4 GOTO $ NGAT ;To xung dng khi PWM, c tn s 1Khz ;.........Buoc 1.......... BSF STATUS,5 BCF TRISC,2
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;.........Buoc 2.......... MOVLW D'250' MOVWF PR2 ;..........Buoc 3......... BCF STATUS,5 MOVLW D'127' MOVWF CCPR1L BCF CCP1CON,5 BCF CCP1CON,4 ;..........Buoc4.......... BCF T2CON,1 BSF T2CON,0 BSF T2CON,2; CHO TIMER2 HOAT DONG ;...........Buoc5......... BSF CCP1CON,3 BSF CCP1CON,2 ;.........TAO TRE......... MOVLW D'100' MOVWF DEM MOVLW B'00000000' MOVWF T1CON STAR MOVLW MOVWF MOVLW MOVWF BSF TEMPS BTFSS PIR1,0 GOTO TEMPS BCF PIR1,0 DECFSZ DEM GOTO STAR ;.........TT XUNG........ BCF STATUS,5 CLRF CCPR1L BCF CCP1CON,5
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3CH TMR1H 0AFH TMR1L T1CON,0
Gio trnh Vi iu Khin
BCF BSF BSF BCF RETFIE END
CCP1CON,4 CCP1CON,3 CCP1CON,2 INTCON,1
Bi 2: Vit chng trnh iu khin ng c: (hnh 6.3)

5 V V c c
R N 1 R B 0 P I C N 2 R B 4 R B 4 R B 5 Q 1 1 6 F 8 7 7 A
R B 5
Hnh 6.3 Nt N1 (nt ON/OFF): Khi nhn N1 nu ng c ang hot ng th ngng v ngc li Nt N2 (thun): Nhn nt N2 ng c quay thun, cng chiu kim ng h. Nt N3 (ngc): Nhn nt N3 ng c quay ngc, ngc chiu kim ng h. Khi ng c ngng (khng hot ng, nt N2, N3 khng c tc dng
PROCESSOR 16F877A #INCLUDE <P16F877A.INC> DEM EQU ORG 0000H GOTO ORG 04H GOTO MAIN BSF BSF BSF BCF
20H MAIN NGAT INTCON,7 INTCON,4 INTCON,3 STATUS,6 91
Gio trnh Vi iu Khin BSF BCF BCF BCF CLRF CLRF STAR BTFSS GOTO GOTO ON BSF GOTO STOP BCF BCF BCF GOTO NGAT BTFSC GOTO MOVLW XORWF BCF RETFIE NGAT_2 BTFSS GOTO BTFSS GOTO GOTO THUAN BSF BCF GOTO NGHICH BCF BSF BTFSS GOTO PORTD,7 PORTD,0 PORTB,4 X 92 PORTD,7 PORTD,0 X DEM,1 X PORTB,5 THUAN NGHICH INTCON,0 NGAT_2 B'00000001' DEM,1 INTCON,1 PORTD,0 PORTD,7 DEM,1 STAR DEM,1 STAR DEM,0 STOP ON STATUS,5 TRISD,0 TRISD,7 STATUS,5 PORTD DEM
Gio trnh Vi iu Khin Y BTFSS GOTO BCF RETFIE END PORTB,5 Y INTCON,0
PH LC: GII THIU LP TRNH CCS
Chong I: Tp Lnh Trong CCS

I.1. Cc Php Ton Trong CCS
I.1.1. Cch Khai Bo Bin, Hng, Mng I.1.1.1.Cac loai bien sau c ho tr : int1 so 1 bit = true hay false ( 0 hay 1) int8 so nguyen 1 byte ( 8 bit) int16 so nguyen 16 bit
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int32 so nguyen 32 bit char ky t 8 bit float so thc 32 bit short mac nh nh kieu int1 byte mac nh nh kieu int8 int mac nh nh kieu int8 long mac nh nh kieu int16 Them signed hoac unsigned pha trc e ch o la so co dau hay khong dau .Khai bao nh tren mac nh la khong dau . 4 khai bao cuoi khong nen dung v de nham lan . Thay vao o nen dung 4 khai bao au . VD : Signed int8 a ; // so a la 8 bit dau ( bit 7 la bit dau ). Signed int16 b , c , d ; Signed int32 , . . . Pham vi bien : Int8 :0 , 255 signed int8 : -128 , 127 Int16 : 0 ,215-1 signed int16 : -215 , 215-1 Int32 : 0 , 232-1 signed int32 : -231 , 231-1 Khai bao hang : VD : Int8 const a=231 ; I.1.1.1.Khai bao 1 mang hang so : VD : Int8 const a[5] = { 3,5,6,8,6 } ; //5 phan t , ch so mang bat au t 0 : a[0]=3 Mot mang hang so co kch thc toi a tuy thuoc loai VK: NeuVK la PIC 14 ( VD :16F877 ) : ban ch c khai bao 1 mang hang so co kch thc toi a la256 byte .Cac khai bao sau la hp le. Int8 const a[5]={ . . .}; // s dung 5 byte , dau . . . e ban ien so vao Int8 const a[256]={ . . .}; // 256 phan t x 1 byte = 256 byte Int16 const a[12] = { . . . }; // 12 x 2= 24 byte Int16 const a[128] = { . . . }; // 128 x 2= 256 byte I.1.2. Cc php ton s hc + Cng ++ Tng 1 n v Tr -Gim 1 n v * Nhn / Chia % Chia ly d = Bng, thc hin gin I.1.3. Cc php ton Logic && Php ton AND || Php ton OR >> Dch phi << Dch tri ! o bit
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~ Ly b & AND tng bit | Or tng bit I.1.4. Cc php ton so snh == So snh bng > Ln hn. >= Ln hn hoc bng. < Nh hn <= Nh hn hoc bng != Khc
I.2. Cc Kiu iu Khin Trong CCS

I.2.1. Kiu: If Else C php: If ( iu kin) { Nhng lnh tha iu kin; } Else { Nhng lnh tha iu kin; } I.2.2. Kiu: While C php: While ( iu kin) { Nhng lnh tha iu kin; } Ch : Trong vng lp While iu kin lun c kim tra I.2.3. Kiu: Do While C php: Do { Nhng lnh ; } While ( iu kin) I.2.4. Kiu: For C php: For (biu thc khi to; biu thc iu kin;biu thc tc ng) { lnh;} I.2.5. Kiu: witchcase switch (biu thc) { case gi tr 1: { lnh 1; break; } case gi tr 2:
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lnh 2; break;
} . default: { lnh ; break ; } } I.3. Cu Trc Chng Trnh V D: Vit chng trnh ti RB0 mc cao #include <16f877a.h> #fuses nowdt,noprotect,nolvp,xt,put #use delay(clock=4000000) #use fast_io(b) #byte portb = 0x6 #bit b0 = portb.0 void main( ) { set_tris_b(0b0); while (true) { b0=1; } }
Chng II: S Dng Cc Khi Chc Nng.

II.1. S Dng Hm Delay III.1.1. Delay_cycles (count ) Count : hang so t 0 255 , la so chu ky lenh .1 chu ky lenh bang 4 chu ky may . ham khong tra ve tr . Ham dung delay 1 so chu ky lenh cho trc . VD : delay_cycles ( 25 ) ; // vi OSC = 20 Mhz , ham nay delay 5 us
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III.1.2.Delay_us ( time ) Time : la bien so th = 0 255 , time la 1 hang so th = 0 -65535 . Ham khong tra ve tr .Ham nay cho phep delay khoang thi gian dai hn theo n v us .Quan sat trong C / asm list ban se thay vi time dai ngan khac nhau , CSS sinh ma khac nhau . III.1.3.Delay_ms (time ) Time = 0-255 neu la bien so hay = 0-65535 neu la hang so . Ham khong tra ve tr . Ham nay cho phep delay dai hn na . VD : Int a = 215; Delay_us ( a ) ; // delay 215 us Delay_us ( 4356 ) ; // delay 4356 us Delay_ms ( 2500 ) ; // delay 2 . 5 s II.2. S Dng Khi ADC. Bng khai bo s dng s ng vo Analog: - ALL_ANALOGS : dung tat ca chan sau lam analog : A0 A1 A2 A3 A5 E0 E1 E2 (Vref=Vdd) - NO_ANALOG : khong dung analog , cac chan o se la chan I /O . - AN0_AN1_AN2_AN4_AN5_AN6_AN7_VSS_VREF : A0 A1 A2 A5 E0 E1 E2 VRefh=A3 - AN0_AN1_AN2_AN3_AN4 : A0 A1 A2 A3 A5 - AN0_AN1_AN3 : A0 A1 A3 , Vref = Vdd - AN0_AN1_VSS_VREF : A0 A1 VRefh = A3 - AN0_AN1_AN4_AN5_AN6_AN7_VREF_VREF : A0 A1 A5 E0 E1 E2 VRefh=A3 , VRefl=A2 . - AN0_AN1_AN2_AN3_AN4_AN5 : A0 A1 A2 A3 A5 E0 - AN0_AN1_AN2_AN4_AN5_VSS_VREF : A0 A1 A2 A5 E0 VRefh=A3 - AN0_AN1_AN4_AN5_VREF_VREF : A0 A1 A5 E0 VRefh=A3 VRefl=A2 - AN0_AN1_AN4_VREF_VREF : A0 A1 A5 VRefh=A3 VRefl=A2 - AN0_AN1_VREF_VREF : A0 A1 VRefh=A3 VRefl=A2 - AN0 : A0 - AN0_VREF_VREF : A0 VRefh=A3 VRefl=A2
* Chng trnh s dng c ADC: Void Doc_ADC() { setup_ADC(ADC_clock_internal); // div_by_2 setup_ADC_ports(AN0); set_ADC_channel(0); delay_us(800);
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} II.3. S Dng PWM. Void Xuat_xung() { setup_ccp1(CCP_PWM); set_pwm1_duty(150); // TH=150*4 setup_timer_2(t2_div_by_4,200,1); // T=200*4 } II.4. Truyn Ni Tip II.4.1. Chun RS232 a. GETC(), GETCH(), GETCHAR(): Hm ny c dng i nhn 1 k t t pin RS232 RCV. Nu khng mun i k t gi v. + C php:: ch = getc() ch = getch() ch = getchar() + Tr tr v: k t 8 bit + Yu cu: #use rs232 V d: #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) char answer; void main() { printf("Continue (Y,N)?"); answer=getch(); } while(answer!='Y' && answer!='N'); b. GETS(), Hm ny c dng c cc k t (dng GETC()) trong chui cho n khi gp lnh RETURN + C php:: gets(char *string) + Tham s: string l con tr (pointer) ch n dy k t + Yu cu: #use rs232 V d: #include <16f877.h> #include <string.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) char string[30]; void main() { printf("Input string: "); gets(string); printf("\n\r"); printf(string); } c. PUTC(), PUTCHAR():
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Hm ny c dng gi mt k t thng qua pin RS232 XMIT. Phi dng #USE RS232 trc khi thc hin lnh ny xc nh tc (baud rate) v pin truyn. + C php: putc(cdata) putchar(cdata) + Tham s: cdata l k t 8 bit + Tr tr v: khng + Yu cu: #use rs232 V d: #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) int i; char string[10]; void main() { strcpy(string,"Hello !"); //copy Hello ! to string for(i=0; i<10; i++) putc(string[i]); //put each charater of string onto screen } d. PUTS(): Hm ny c dng gi mi k t trong chui n pin RS232 dng PUTC(). Sau khi chui c gi i th RETURN (13) v LINE-FEED (10) uc gi i. Lnh printf() thng dng hn lnh puts(). + C php: puts(string) + Tham s: string l chui hng (constant string) hay dy k t (character array) + Tr tr v: khng + Yu cu: #use rs232 V d: Dng PUTS() #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) void main() { puts(" ------------- "); puts(" | Hello | "); puts(" ------------- "); } Dng PRINTF() #include <16f877.h> #use delay(clock=20000000) #use rs232(baud=9600,parity=N,xmit=PIN_C6,rcv=PIN_C7) void main() { printf(" ------------- \n\r"); printf(" | Hello | \n\r"); printf(" ---------------"); } e. KBHIT(): Hm ny c dng bo nhn c bit start. + C php:: value = kbhit()
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+ Tham s: khng + Tr tr v: 0 (hay FALSE) nu getc() cn phi i nhn 1 k t t bn Phm 1 (hay TRUE) nu c 1 k t sn sng nhn bng getc(). + Yu cu: #use rs232 f. PRINTF(): Hm ny c dng xut mt chui theo chun RS232 hoc theo mt hm xc nh. D liu c nh dng ph hp vi i s ca chui. Cc nh dng d liu nh sau: C Kiu k t S Chui hoc k t U S nguyn khng du x Hex int (xut ch thng) X Hex int (xut ch hoa) D s nguyn c du e S thc nh dng kiu s m f Kiu du chm ng Lx Hex long int (ch thng) LX Hex long int (ch hoa) Iu s thp phn khng du Id S thp phn c du. % Du % + C php: printf(string) printf(cstring, values...) printf(fname, cstring, values...) + Tham s: String l mt chui hng Hoc mt mng k t khng xc nh. Values l danh sch cc bin phn cch nhau bi du , , fname is l tn hm dng xut d liu (mc nhin l putc()). + Tr tr v: khng + Yu cu: #use rs232 g. SET_UART_SPEED(): Hm ny c dng t tc truyn d liu thng qua cng RS232. + C php:: set_uart_speed(baud) + Tham s: baud l hng s tc truyn (bit/giy) t 100 n 115200. + Tr tr v: khng + Yu cu: #use rs232 V d: // Set baud rate based on setting of pins B0 and B1 switch(input_b() & 3) { case 0 : set_uart_speed(2400); break; case 1 : set_uart_speed(4800); break; case 2 : set_uart_speed(9600); break; case 3 : set_uart_speed(19200); break; } II.4.2. Chun I2C a. #USE I2C(): Th vin I2C gm cc hm dng cho I2C bus. #USE I2C dng vi cc lnh I2C_START,I2C_STOP, I2C_READ, I2C_WRITE and I2C_POLL. Cc hm phn mm c to ra tr khi dng lnh FORCE_HW. + C php: #use i2c(mode,SDA=pin,SCL=pin[options])
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+ Tham s: mode: master/slave - t master/slave mode SCL=pin ch nh pin SCL (pin l bit address) SDA=pin ch nh pin SDA options nh sau ADDRESS=nn : ch nh a ch slave mode FAST : s dng fast I2C specification SLOW : s dng slow I2C specification RESTART_WDT : khi ng li WDT trong khi ch c I2C_READ FORCE_HW : s dng chc nng I2C phn cng (hardware I2C functions) b. I2C_START(): Hm ny c dng Khi ng start bit (bit khi ng) I2C master mode. Sau khi khi ng start bit, xung clock mc thp ch n khi lnh I2C_WRITE() c thc hin. Ch I2C protocol ph thuc vo thit b slave. + C php:: i2c_start() + Tham s: khng + Tr tr v: khng + Yu cu: #use i2c V d: i2c_start(); i2c_write(0xa0); //Device address i2c_write(address); //Data to device i2c_start(); //Restart i2c_write(0xa1); //to change data direction data=i2c_read(0); //Now read from slave i2c_stop(); c. I2C_STOP(): Hm ny c s dng tt s dng I2C master mode. + C php: i2c_stop() + Tham s: khng + Tr tr v: khng + Yu cu: #use i2c V d: i2c_start(); //Start condition i2c_write(0xa0); //Device address i2c_write(5); //Device command i2c_write(12); //Device data i2c_stop(); //Stop condition d. I2C_POLL(): Hm ny c dng hi vng I2C, hm ny ch c dng khi SSP c dng. Hm ny trv gi tr TRUE nu nhn c gi tr b m. Khi hm ny ln TRUE, nu dng hm I2C_READ th ta c gi tr c v. + C php: i2c_poll() + Tham s: khng + Tr tr v: 1 (TRUE) hay 0 (FALL) + Yu cu: #use i2c V d: i2c_start(); //Start condition i2c_write(0xc1); //Device address/Read count=0; while(count!=4) { while(!i2c_poll()) ; buffer[count++]= i2c_read(); //Read Next
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} i2c_stop(); // Stop condition e. I2C_READ(), I2CREAD(ACK): Hm ny c dng c mt byte qua cng I2C thit b master: lnh ny to xung clock v thet b claver, lnh ny ch c xung clock. There is no timeout for the slave, use I2C_POLL to prevent a lockup. Use ESTART_WDT in the #USE I2C to strobe the watch-dog timer in the slave mode while waiting. C php: i2c_stop() i2c_stop(ack) Tham s: ty chn, mc nh l 1 ack = 0: khng kim tra trng thi thu gi tn hiu (ack: acknowlegde) ack = 1: kim tra trng thi thu gi tn hiu Tr tr v: 8 bit int Yu cu: #use i2c V d: i2c_start(); i2c_write(0xa1); data1 = i2c_read(); data2 = i2c_read(); i2c_stop(); f. I2C_WRITE(): Hm ny c dng Gi tng byte thng qua giao din I2C. ch ch s pht ra xung Clock vi d liu v ch Slave s ch xung Clock t con ch truyn v. Khng t ng m ngoi l iu kin ca lnh ny. Lnh ny s tr v bit ACK. Pht LSB trc khi truyn khi xc nh hng truyn ca d liu truyn (0 cho master sang slave). Ch chun giao tip I2C ph thuc vo thit b slave. + C php: i2c_write(data) + Tham s: data: 8 bit int + Tr tr v: Lnh ny tr v bit ACK ack = 0: khng kim tra trng thi thu gi tn hiu (ack: acknowlegde) ack = 1: kim tra trng thi thu gi tn hiu + Yu cu: #use i2c V d: long cmd; ... i2c_start(); //Start condition i2c_write(0xa0); //Device address i2c_write(cmd); //Low byte of command i2c_write(cmd>>8); //High byte of command i2c_stop(); //Stop condition
Chng III: S Dng Ngt

III.1. Cu Trc Chng Trnh C S Dng Ngt.
III.1.1. Khai Bo Ngt. Enable_interrupts(int_EXT);// Cho php ngt ngoi Enable_interrupts(global); // Cho php ngt ton cc #INT_AD : chuyen oi A /D a hoan tat , thng th khong nen dung #INT_CCP1 : co Capture hay compare tren CCP1 #INT_CCP2 : co Capture hay compare tren CCP2
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#INT_COMP : kiem tra bang nhau tren Comparator #INT_EXT : ngat ngoai #INT_I2C : co hoat ong I 2C #INT_LCD : co hoat ong LCD #INT_PSP : co data vao cong Parallel slave #INT_RB : bat ky thay oi nao tren chan B4 en B7 #INT_RDA : data nhan t RS 232 san sang #INT_RTCC : tran Timer 0 #INT_SSP : co hoat ong SPI hay I 2C #INT_TBE : bo em chuyen RS 232 trong #INT_TIMER0 : mot ten khac cua #INT_RTCC #INT_TIMER1 : tran Timer 1 #INT_TIMER2 : tran Timer 2 III.1.2 Cu Trc Chng Trnh #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP #use delay(clock=4000000) #INT_x void ngat(); void main() { enable_interrupts(int_x);// Khai bo ngt g? enable_interrupts(global); // Cho php ngt ton cc Chng trnh chnh; } void ngat() { X l ngt; } III.2. S Dng Ngt III.2.1. Ngt RB0 #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP #use delay(clock=4000000) #use fast_io(b) #byte portb=0x6 #bit b7=portb.7 #INT_EXT void ngat() { b7=!b7; } void main() { enable_interrupts(int_EXT); enable_interrupts(global); set_tris_b(0b00000001); portb=0;
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While (1) {} } III.2.2. Ngt Timer #include <16F877a.h> #fuses XT,NOWDT,NOPROTECT,NOLVP #use delay(clock=4000000) #use fast_io(b) #byte portb=0x6 #bit b0=portb.0 int16 time; #INT_TIMER1 void Ngat_timer1(); void main() { enable_interrupts(int_timer1);//Ngat Timer1 enable_interrupts(global); // Ngat toan cuc setup_timer_1(t1_INTERNAL|t1_div_by_4); // Chia tan set_timer1(55535);//Cai gia tri cho Timer1 set_tris_b(0b0); While (1) {} } #INT_TIMER1 void Ngat_timer1() { set_timer1(55535);//Cai gia tri cho Timer1 b0=!b0; }
PH LC: CC THANH GHI CHC NNG

1. Thanh ghi TMR0: a ch 01h, 101h. Thanh ghi 8 bit cha gia tr cua bo nh thi Timer0. 2. Thanh ghi PCL: a ch 02h, 82h, 102h, 182h. Thanh ghi cha 8 bit thap cua bo em chng trnh (PC) 3. Thanh ghi STATUS: a ch 03h, 83h, 103h, 183h
IPR Bit 7
RP1
RP0
TO
PD
DC
C Bit 0
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Gio trnh Vi iu Khin
Thanh ghi trng thi cha cc trng thi s hc ca b ALU, trng thi Reset v cc bit chn Bank ca b nh d liu. Bit 7 IRP: Bit la chn bank thanh ghi (S dng cho nh a ch gin tip). 1 = Bank 2, 3 (100h 1FFh ) 0 = Bank 0, 1 (00h FFh) Bit 6 5 RP1 RP0: Bit la chn bank thanh ghi (Dng trong nh i ch trc tip). 11 = Bank 3 ( 180h 1FFh) 10 = Bank 2 (100h 17Fh) 01 = Bank 1 (80h FFh) 00 = Bank 0 (00h 7Fh) Each bank is 128 bytes Bit 4 TO: Bit bo hiu hot ng ca WDT. 1: Lnh xa WDT hoc Sleep xy ra. 0: WDT hot ng. Bit 3 PD: Bit bo cng sut thp ( Power down bit). 1: Sau khi ngun tng hoc c lnh xa WDT. 0: Thc thi lnh Sleep. Bit 2 Z: bit Zero 1: Khi kt qu ca mt php ton bng 0. 0: Khi kt qu ca mt php ton khc 0. Bit 1 DC: Digit Carry 1: C mt s nh sinh ra bi php cng hoc php tr 4 bit thp. 0: Khng c s nh sinh ra. Bit 0 C: c nh (Carry Flag) 1: C mt s nh sinh ra bi php cng hoc php tr 4 bit cao. 0: Khng c s nh sinh ra.
4. Thanh ghi FSR: a ch 04h. Thanh ghi cha con tro a ch gian tiep cua bo nh d lieu. 5. Thanh ghi PORTA: a ch 05h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTA. 6. Thanh ghi PORTB: a ch 06h, 106h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTB. 7. Thanh ghi PORTC: a ch 07h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTC 8. Thanh ghi PORTD: a ch 08h. Thanh ghi cha gia tr nhan vao hay xuat ra PORTD. 9. Thanh ghi PORTE: a ch 09h. 105
Gio trnh Vi iu Khin Thanh ghi cha gia tr nhan vao hay xuat ra PORTE. 10. Thanh ghi PCLATCH: a ch 0Ah, 8Ah, 10Ah, 18Ah. Thanh ghi ong vai tro la buffer em trong qua trnh ghi gia tr len 5 bit cao cua bo em chng trnh PC. 11. Thanh ghi INTCON: a ch 0Bh, 8Bh, 10Bh, 18Bh.
Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php c v ghi, cha cc bit iu khin v cc bit c hiu khi timer0 b trn, ngt ngoi vi RB0/INT v ngt interrputon-change ti cc chn ca PORTB. GIE Bit 7 PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF Bit 0
Bit 7: GIE Global Interrupt Enable bit GIE = 1 cho php tt c cc ngt. GIE = 0 khng cho php tt c cc ngt. Bit 6: PEIE Pheripheral Interrupt Enable bit PEIE = 1 cho php tt c cc ngt ngoi vi PEIE = 0 khng cho php tt c cc ngt ngoi vi Bit 5: TMR0IE Timer0 Overflow Interrupt Enable bit TMR0IE = 1 cho php ngt Timer0 TMR0IE = 0 khng cho php ngt Timer0 Bit 4: INTE RB0/INT External Interrupt Enable bit INTIE = 1 cho php ngt ngoi vi RB0/INT INTIE = 0 khng cho php ngt ngoi vi RB0/INT Bit3: RBIE RB Port change Interrupt Enable bit RBIE = 1 cho php ngt RB Port change RBIE = 0 khng cho php ngt RB Port change Bit 2: TMR0IF Timer0 Interrupt Flag bit TMR0IF = 1 thanh ghi TMR0 b trn (phi xa bng chng trnh) . TMR0IF = 0 thanh ghi TMR0 cha b trn. Bit 1: INTF BR0/INT External Interrupt Flag bit INTF = 1 ngt RB0/INT xy ra (phi xa c hiu bng chng trnh). INTF = 0 ngt RB0/INT cha xy ra. Bit 0: RBIF RB Port Change Interrupt Flag bit RBIF = 1 t nht c mt chn RB7:RB4 c s thay i trng thi.Bit ny phi c xa bng chng trnh sau khi kim tra licc gi tr ca cc chn ti PORTB.
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Gio trnh Vi iu Khin
RBIF = 0 khng c s thay i trng thi cc chn RB7:RB4

12. Thanh ghi PIR1: a ch 0Ch Thanh ghi cha c ngat cua cac khoi ngoai vi.
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Bit 7 Bit 0 Bit 7: PSPIF Parallel Slave Port Read/Write Interrupt Flag bit PSPIF = 1 va hon tt thao tc c hoc ghi PSP (phi xa bngchng trnh). PSPIF = 0 khng c thao tc c ghi PSP no din ra. Bit 6: ADIF ADC Interrupt Flag bit ADIF = 1 hon tt chuyn i ADC. ADIF = 0 cha hon tt chuyn i ADC. Bit 5: RCIF USART Receive Interrupt Flag bit RCIF = 1 buffer nhn qua chun giao tip USART y. RCIF = 0 buffer nhn qua chun giao tip USART rng. Bit 4: TXIF USART Transmit Interrupt Flag bit TXIF = 1 buffer truyn qua chun giao tip USART rng. TXIF = 0 buffer truyn qua chun giao tip USART y. Bit 3: SSPIF Synchronous Serial Port (SSP) Interrupt Flag bit SSPIF = 1 ngt truyn nhn SSP xy ra. SSPIF = 0 ngt truyn nhn SSP cha xy ra. Bit 2: CCP1IF CCP1 Interrupt Flag bit Khi CCP1 ch Capture CCP1IF=1 cp nht gi tr trong thanh ghi TMR1. CCP1IF=0 cha cp nht gi tr trong thanh ghi TMR1. Khi CCP1 ch Compare CCP1IF=1 gi tr cn so snh bng vi gi tr cha trong TMR1 CCP1IF=0 gi tr cn so snh khng bng vi gi tr trong TMR1. Bit 1: TMR2IF TMR2 to PR2 Match Interrupt Flag bit TRM2IF = 1 gi tr cha trong thanh ghi TMR2 bng vi gi tr cha trong thanh ghi PR2. TRM2IF = 0 gi tr cha trong thanh ghi TMR2 cha bng vi gi tr cha trong thanh ghi PR2. Bit 0: TMR1IF TMR1 Overflow Interrupt Flag bit TMR1IF = 1 thanh ghi TMR1 b trn (phi xa bng chng trnh). TMR1IF = 0 thanh ghi TMR1 cha b trn
13. Thanh ghi PIR2: a ch 0Dh
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Gio trnh Vi iu Khin
Bit 7
CMIF
EEIF
BCLIF
CCP2IF Bit 0
Bit 7, 5, 2, 1: khng quan tm v mc nh mang gi tr 0. Bit 6: CMIF Comparator Interrupt Flag bit CMIF = 1 tn hiu ng vo b so snh thay i. CMIF = 0 tn hiu ng vo b so snh khng thay i. Bit 4: EEIF EEPROM Write Operation Interrupt Flag bit EEIF = 1 qu trnh ghi d liu ln EEPROM hon tt. EEIF = 0 qu trnh ghi d liu ln EEPROM cha hon tt hoc cha bt u. Bit 3: BCLIF Bus Collision Interrupt Flag bit BCLIF = 1 Bus truyn nhn ang bn khi (ang c d liu truyn i trong bus) khi SSP ht ng ch I2C Master mode. BCLIF = 0 Bus truyn nhn cha b trn (khng c d liu truyn itrong bus). Bit 0: CCP2IF CCP2 Interrupt Flag bit ch Capture CCP2IF = 1 cp nht gi tr trong thanh ghi TMR1. CCP2IF = 0 cha cp nht gi tr trong thanh ghi TMR1. ch Compare CCP2IF = 1 gi tr cn so snh bng vi gi tr cha trong TMR1. CCP2IF = 0 gi tr cn so snh cha bng vi gi tr cha trong TMR1
14. Thanh ghi TMR1L: a ch 0Eh Thanh ghi cha 8 bit thap cua bo nh thi TMR1. 15. Thanh ghi TMR1H: a ch 0Fh Thanh ghi cha 8 bit cao cua bo nh thi TMR2. 16. Thanh ghi T1CON: a ch 10h Thanh ghi ieu khien Timer1.
Bit7
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Bit 0
Bit 7,6 Khng s dng, c l 0. Bit 5,4 T1CKPS1 : T1CKPS0 : Cc bit chn t l xung ng vo cho Timer1. 11 1 : 8 gi tr t l 10 1 : 4 gi tr t l 01 1 : 2 gi tr t l 00 1 : 1 gi tr t l Bit 3 T10SCEN : Bit cho php b dao ng Timer 1 Oscillator 1 : Cho php dao ng
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0 : Khng cho php dao ng Bit 2 T1SYNC : Bit la chn ng b ha xung clock ngoi ca Timer 1 (Ch : Bit ny ch c tc dng khi bit TMR1CS = 1) 1: Khng ng b ha xung clock ngoi 0: ng b ha xung clock ngoi. Bit 1 TMR1CS : Bit chn ngun xung clock cho Timer 1 1: Chn xung clock ngoi qua chn T1OSC/T1CKI ( tc ng cnh ln) 0: Chn xung clock ni (Fosc/4) Bit 0 TMR1ON: Bit cho php ngoc ngng Timer 1 1: Cho php 0: Khng cho php
17. Thanh ghi TMR2: a ch 11h Thanh ghi cha gia tr bo em Timer2. 18. Thanh ghi T2CON: a ch 12h Thanh ghi ieu khien Timer2.
Bit 7
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
T2CKPS1
T2CKPS0
Bit0
Bit 7: khng s dng Bit 6:3 TOUTPS3:TOUTPS0: Bit chn t l ng ra ca Timer 2 0000: 1:1 T l ng ra 0001: 1:2 T l ng ra . 1111: 1:16 T l ng ra Bit 2 TMR2ON: Bit cho php hot ng ca Timer 2 1: Cho php 0: Khng cho php. Bit 1:0 T2CKPS1:T2CKPS0: Bit chn t l ng vo ca Timer 2 00 : Prescaler 1 01 : Prescaler 4 1x : Prescaler 16
19. Thanh ghi SSPBUF: a ch 13h Thanh ghi em d lieu 8 bit cho chuan giao tiep MSSP. 20. Thanh ghi SSPCON: a ch 14h Thanh ghi iu khin chun giao tip MSSP.
WCOL Bit 7
SSPOV
SSPEN
CKP
109
SSPM3
SSPM2
SSPM1
SSPM0 Bit 0
Gio trnh Vi iu Khin
Khi MSSP ch SPI: Bit 7 WCOL Write Collition Detect bit WCOL = 1 d liu mi c a vo thanh ghi SSPBUF trong khi cha truyn xong d liu trc . WCOL = 0 khng c hin tng trn xy ra. Bit 6 SSPOV Receive Overflow Indicalor bit (bit ny ch c tc dng ch SPI Slave mode). SSPOV = 1 d liu trong bufer m (thanh ghi SSPBUF) b trn (d liu c cha c c th c d liu mi gi ln). SSPOV = 0 khng c hin tng trn xy ra. Bit 5 SSPEN Synchronous Serial Port Enable bit SSPEN = 1 cho php cng giao tip MSSP (cc pin SCK, SDO, SDI v ). SSPEN = 0 khng cho php cng giao tip MSSP. Bit 4 CKP Clock Polarity Select bit CKP = 1 trng thi ch ca xung clock l mc logic cao. CKP = 0 trng thi ch ca xung clock l mc logic thp. Bit 3-0 SSPM3:SSPM0 Synchronous Serial Mode Select bit Cc bit ny ng vai tr la chn cc ch hot ng ca MSSP. 0101 Slave mode, xung clock ly t pin SCK, khng cho php pin iu khin ( l pin I/O bnh thng). 0100 SPI Slave mode, xung clock ly t pin SCK, cho php pin iu khin . 0011 SPI Master mode, xung clock bng (ng ra TMR2)/2. 0010 SPI Master mode, xung clock bng (FOSC/64). 0001 SPI Master mode, xung clock bng (FOSC/16). 0000 SPI Master mode, xung clock bng (FOSC/4). Cc trng thi khng c lit k hoc khng c tc dng iu khin hoc ch c tc dng i vi ch I2C mode. Khi MSSP ch I2C Bit 7 WCOL Write Collition Detect bit Khi truyn d liu ch I2C Master mode: WCOL = 1 a d liu truyn i vo thanh ghi SSPBUF trong khi ch truyn d liu ca I2C cha sn sng. WCOL = 0 khng xy ra hin tng trn. khi truyn d liu ch I2C Slave mode: WCOL = 1 d liu mi c a vo thanh ghi SSPBUF trong khi d liu c cha c truyn i. WCOL = 0 khng c hin tng trn xy ra.
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Gio trnh Vi iu Khin
ch nhn d liu (Master hoc Slave): Bit ny khng c tc dng ch thi cc trng thi. Bit 6 SSPOV Receive Overflow Indicator Flag bit. Khi nhn d liu: SSPOV = 1 d liu mi c nhn vo thanh ghi SSPBUF trong khi d liu c cha c c. SSPOV = 0 khng c hin tng trn xy ra. Khi truyn d liu: Bit ny khng c tc dng ch th cc trng thi. Bit 5 SSPEN Synchronous Serial Port Enable bit SSPEN = 1 cho php cng giao tip MSSP (cc pin SDA v SCL). SSPEN = 0 khng cho php cng giao tip MSSP. Cn ch l cc pin SDA v SCL phi c iu khin trng thi bng cc bit tng ng trong thanh ghi TRISC trc ). Bit 4 CKP SCK Release Control bit ch Slave mode: CKP = 1 cho xung clock tc ng. CKP = 0 gi xung clock mc logic thp ( bo m thi gian thit lp d liu). Bit 3,0 SSPM3:SSPM0 Cc bit ny ng vai tr la chn cc ch hot ng ca MSSP. 1111 I2C Slave mode 10 bit a ch v cho php ngt khi pht hin bit Start v bit Stop. 1110 I2C Slave mode 7 bit a ch v cho php ngt khi pht hin bit Start v bit Stop. 1011 I2C Firmwave Controlled Master mode (khng cho php ch Slave). 1000 I2C Master mode, xung clock = FOSC/(4*(SSPADD+1)). 0111 I2C Slave mode 10 bit a ch. Cc trng thi khng c lit k hoc khng c tc dng iu khin hoc ch c tc dng i vi ch SPI mode.
21. Thanh ghi CCPR1L: a ch 15h Thanh ghi cha 8 bit thap cua khoi CCP1. 22. Thanh ghi CCPR1H: a ch 16h Thanh ghi cha 8 bit cao cua khoi CCP1. 23. Thanh ghi CCP1CON va thanh ghi CCP2CON: a ch 17h (CCP1CON) va 1Dh (CCP2CON) Thanh ghi ieu khien khoi CCP1.
CCPXX
CCPXY CCPXMP3 CCPXMP2 CCPXMP1 CCPXMP0

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Bit 7,6 Khng c tc dng v mc nh mang gi tr 0. Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (cc bit ny khng c tc dng ch Capture v Compare). ch PWM, y l 2 bit MSB cha gi tr tnh rng xung (duty cycle) ca khi PWM (8 bit cn li c cha trong thanh ghi CCPRxL). Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit Cc bit dng xc lp cc ch hot ng ca khi CCPx 0000 khng cho php CCPx (hoc dng reset CCPx) 0100 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh xung ti pin dng cho khi CCPx. 0101 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln ti pin dng cho khi CCPx. 0110 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln th 4 ti pin dng cho khi CCPx. 0111 CCPx hot ng ch Capture, "hin tng" c thit lp l mi cnh ln th 16 ti pin dng cho khi CCPx. 1000 CCPx hot ng ch Compare, ng ra c a ln mc cao v bit CCPxIF c set khi cc gi tr cn so snh bng nhau. 1001 CCPx hot ng ch Compare, ng ra c xung mc thp v bit CCPxIF c set khi cc gi tr cn so snh bng nhau. 1010 CCPx hot ng ch Compare, khi cc gi tr cn so snh bng nhau, ngt xy ra, bit CCPxIF c set v trng thi pin output khng b nh hng. 1011 CCPx hot ng ch Compare, khi cc gi tr cn so snh bng nhau, xung trigger c bit (Trigger Special Event) s c to ra, khi c ngt CCPxIF c set, cc pin output khng thay i trng thi, CCp1 reset Timer1, CCP2 reset Timer1 v khi ng khi ADC. 11xx CCPx hot ng ch PWM. 24. Thanh ghi RCSTA: a ch 18h Thanh ghi cha cc bit trng thi v cc bit iu khin qu trnh nhn d liu qua chun giao tip USART. SPEN Bit 7 RX9 SREN CREN ADDEN FERR OERR RX9D Bit 0
Bit 7 SPEN Serial Port Enable bit

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SPEN = 1 Cho php cng giao tip USART (pin RC7/RX/DT v RC6/TX/CK). SPEN = 0 khng cho php cng giao tip USART. Bit 6 RX9 9-bit Receive Enable bit RX9 = 1 nhn 9 bit d liu. RX9 = 0 nhn 8 bit d liu. Bit 5 SREN Single Receive Enable bit ch USART bt ng b: bit ny khng cn quan tm. ch USART Master ng b: SREN = 1 cho php chc nng nhn 1 byte d liu (8 bit hoc 9 bit). SREN = 0 khng cho php chc nng nhn 1 byte d liu. Bit 4 CREN Continous Receive Enable bit ch bt ng b: CREN = 1 cho php nhn 1 chui d liu lin tc. CREN = 0 khng cho php nhn 1 chui d liu lin tc. ch bt ng b: CREN = 1 cho php nhn d liu cho ti khi xa bit CREN. CREN = 0 khng cho php nhn chui d liu. Bit 3 ADDEN Address Detect Enable bit ch USART bt ng b 9 bit ADDEN = 1 cho php xc nhn a ch, khi bit RSR<8> c set th ngt c cho php thc thi v gi tr trong buffer c nhn vo. ADDEN = 0 khng cho php xc nhn iz5 ch, cc byte d liu c nhn vo v bit th 9 c th c s dng nh l bit parity. Bit 2 FERR Framing Eror bit FERR = 1 xut hin li "Framing" trong qu trnh truyn nhn d liu. FERR = 0 khng xut hin li "Framing" trong qu trnh truyn nhn d liu. Bit 1 OERR Overrun Error bit, OERR = 1 xut hin li "Overrun" OERR = 0 khng xut hin li "Overrun" Bit 0 RX9D Bit ny cha bit d liu th 9 ca d liu truyn nhn. 25. Thanh ghi TXREG: a ch 19h Thanh ghi ng vai tr l buffer m 8 bit trong qu trnh truyn d liu thng qua chun giao tip USART. 26. Thanh ghi RCREG: a ch 1Ah Thanh ghi ng vai tr l buffer m trong qu trnh nhn d liu qua chun giao tip USART.
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27. Thanh ghi CCPR2L: a ch 1Bh Thanh ghi cha 8 bit thp ca khi CCP2. 28. Thanh ghi CCPR2H: a ch 1Ch Thanh ghi cha 8 bit cao ca khi CCP2. 29. Thanh ghi ADRESH: a ch 1Eh Thanh ghi cha byte cao ca kt qu qu trnh chuyn i ADC. 30. Thanh ghi ADCON0: a ch 1Fh y l mt trong hai thanh ghi iu khin khi chuyn i ADC. Thanh ghi cn li l thanh ghi ADCON1 (a ch 9Fh)
Bit 7:6 ADCS1:ADCS0: Cc bit la chn tn s chuyn i A/D 00 =FOSC/2 01 =FOSC/4 10 =FOSC/32 11 =FRC (xung clock c ly t dao ng ni RC) Bit 5:3 CHS2:CHS0: Cc bit la chn knh Analog 000: Knh 0, (AN0) 001: Knh 1, (AN1) 010: Knh 2, (AN2) 011: Knh 3, (AN3) 100: Knh 4, (AN4) 101: Knh 5, (AN5) 110: Knh 6, (AN6) 111: Knh 7, (AN7) Bit 2 GO/ DONE: Bit bo trng thi chuyn i A/D Khi bit ADON = 1 1: Qu trnh A/D ang thc hin (Khi chng ta set bit ny ln th qu trnh chuyn i s xy ra, khi qu trnh kt thc n s t ng c xa bng phn mm). 0: Qu trnh A/D khng xy ra hoc hon tt. Bit 1 Khng s dng, gi tr l 0 Bit 0 ADON : Bit cho php module A/D hot ng. 1: Ngun c cung cp cho A/D 0: Ngng cung cp ngun cho A/D
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31. Thanh ghi ADCON1: a ch 9Fh Thanh ghi cha cc bit iu khin b chuyn i ADC (ADC c hai thanh ghi iu khin l ADCON1 v ADCON0).
Bit 7 ADFM: Bit la chn nh dng kt qu A/D 1: Canh phi, 6 bit cao nht ca thanh ghi ADRESH c gi tr 0 0: Canh tri, 6 bit thp nht ca thanh ghi ADRESL c gi tr 0 Bit 6 ADCS2: Bit la chn clock chuyn i A/D
Bit 5,4 khng s dng Bit 3:0 PCFG3:PCFG0: Cc bit iu khin cu hnh cc chn ADC
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32. Thanh ghi OPTION_REG: a ch 81h, 181h

Thanh ghi nay cho phep oc va ghi, cho phepieu khien chc nang pull-up cua cac chan trong PORTB, xac lap cac tham so ve xung tacong, canh tac ong cua ngat ngoai vi va bo em Timer0.
Thanh ghi ty chn cha cc bit iu khin cu hnh cho cc cha nng nh: ngt ngoi, Timer 0 chc nng ko ln Vdd ca cc chn Port B, v thi gian ch ca WDT.
Bit 7RBPU : Bit cho php PORTB c ko ln ngun. 1: Khng cho php PORTB ko ln ngun. 0: Cho php PORTB ko ln ngun. Bit 6 INTEDG: Bt la chn cnh tc ng ngt (INTERRUPT EDGE) 1: Ngt s c tc ng bi cnh ln ca chn RB0/INT 0: Ngt s c tc ng bi cnh xung ca chn RB0/INT Bit 5 T0CS: Bit la chn ngun xung Clock cho Timer 0 1: Xung Clock cung cp bi ngun ngoi qua chn RA4/T0CKI 0: Xung Clock cung cp bi ngun dao ng ni. Bit 4 T0SE: Bit la chn cnh no ca xung clock tc ng ln timer 0 1: Cnh xung 0: Cnh ln Bit 3 PSA: Bit quyt nh tc m PS2:PS0 s tc ng ln Timer 0 hay WDT 1: Tc m PS2:PS0 s tc ng ln WDT 0: Tc m PS2:PS0 s tc ng ln Timer 0 Bit 2-0 PS2:PS0: Dng la chn tc m ca timer hay WDT
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33. Thanh ghi TRISA: a ch 85h Thanh ghi iu khin xut nhp ca cc pin trong PORTA. 34. Thanh ghi TRISB: a ch 86h, 186h Thanh ghi iu khin xut nhp ca cc pin trong PORTB. 35. Thanh ghi TRISC: a ch 87h Thanh ghi iu khin xut nhp ca cc pin trong PORTC. 36. Thanh ghi TRISD: a ch 88h Thanh ghi iu khin xut nhp ca cc pin trong PORTD. 37. Thanh ghi TRISE: a ch 89h Thanh ghi iu khin xut nhp ca cc pin trong PORTE, iu khin cng giao tip song song PSP (Parallel Slave Port). IBF OBF IBOV SPPMODE 2 1 0 Bit 7 Bit 0 Bit 7 BIF Input Buffer Full Status bit BIF = 1 mt Word d liu va c nhn v ang ch CPU c vo. BIF = 0 cha c Word d liu no c nhn. Bit 6 OBF Output Buffer Full Status bit OBF = 1 Buffer truyn d liu vn cn cha d liu c v vn cha c c. OBF = 0 Buffer truyn d liu c c. Bit 5 IBOV Input Buffer Overflow Detect bit IBOV = 1 d liu c ghi ln buffer trong khi d liu c vn cha c c. IBOV = 0 buffer cha b trn. Bit 4 PSPMODE Parallel Slave Port Mode Select bit PSPMODE = 1 Cho php PSP, PORTD ng vai tr l cng giao tip song song PSP. PSPMODE = 0 Khng cho php PSP.
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Bit 3 Khng cn quan tm v mc nh mang gi tr 0. Bit 2 Bit2 Direction Control for pin . Bit2 = 1 Input Bit2 = 0 Output Bit 1 Bit1 Direction Control for pin Bit1 = 1 Input Bit1 = 0 Output Bit 0 Bit0 Direction Control for pin Bit0 = 1 Input Bit0 = 0 Output 38. Thanh ghi PIE1: a ch 8Ch Thanh ghi cha cc bit cho php cc ngt ngoi vi. PSPIE Bit 7 ADIE RCIE TXIE SSPIE CCPIE1 TMR2IE TMR1IE Bit 0
Bit 7 PSPIE Parallel Slave Port Read/Write Interrupt Enable bit PSPIE = 1 cho php ngt PSP read/write. PSPIE = 0 khng cho php ng PSP read/write. Bit 6 ADIE ADC (A/D converter) Interrupt Enable bit ADIE = 1 cho php ngt ADC. ADIE = 0 khng cho php ngt ADC. Bit 5 RCIE USART Receive Interrupt Enable bit RCIE = 1 cho php ngt nhn USART RCIE = 0 khng cho phpn gt nhn USART Bit 4 TXIE USART Transmit Interrupt Enable bit TXIE = 1 cho php ngt truyn USART TXIE = 0 khng cho php ngt truyn USART Bit 3 SSPIE Synchronous Serial Port Interrupt Enable bit SSPIE = 1 cho php ngt SSP SSPIE = 0 khng cho php ngt SSP Bit 2 CCP1IE CCP1 Interrupt Enable bit CCP1IE = 1 cho php ngt CCP1 CCP1IE = 0 khng cho php ngt CCP1 Bt 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit TMR2IE = 1 cho php ngt. TMR2IE = 0 khng cho php ngt. Bit 0 TMR1IE TMR1 Overflow Interrupt Enable bit
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TMR1IE = 1 cho php ngt. TMR1IE = 0 khng cho php ngt. 39. Thanh ghi PIE2: a ch 8Dh Thanh ghi cha cc bit cho php cc ngt ngai vi. Bit 7 CMIE EEIE BCLIE CCP2IE Bit 0
Bit 7, 5, 2, 1 Khng cn quan tm v mc nh mang gi tr 0. Bit 6: CMIE Comparator Interrupt Enable bit CMIE = 1 Cho php ngt ca b so snh. CMIE = 0 Khng cho php ngt. Bit 4: EEIE EEPROM Write Operation Interrupt Enable bit EEIE = 1 Cho php ngt khi ghi d liu ln b nh EEPROM. EEIE = 0 Khng cho php ngt khi ghi d liu ln b nh EEPROM. Bit 3: BCLIE Bus Collision Interrupt Enable bit BCLIE = 1 Cho php ngt. BCLIE = 0 Khng cho php ngt. Bit 0: CCP2IE CCP2 Interrupt Enable bit CCP2IE = 1 Cho php ngt. CCP2IE = 0 Khng cho php ngt 40. Thanh ghi PCON: a ch 8Eh Thanh ghi iu khin cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin.
Bit 7, 6, 5, 4, 3, 2 Khong can quan tam va mac nh mang gia tr 0.
Bit 1 Power-on Reset Status bit = 1 khng c s tc ng ca Power-on Reset. = 0 c s tc ng ca Power-on reset. Bit 0 Brown-out Reset Status bit = 1 khng c s tc ng ca Brown-out reset. = 0 c s tc ng ca Brown-out reset. 41. Thanh ghi SSPCON2: a ch 91h Thanh ghi iu khin cc ch hot ng ca chun giao tip I2C. GCEN Bit 7 ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Bit 0
Bit 7 GCEN General Call Enable bit

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GCEN = 1 Cho php ngt khi a ch 0000h c nhn vo thanh ghi SSPSR (a ch ca ch General Call Address). GCEN = 0 Khng cho php ch a ch trn. Bit 6 ACKSTAT Acknowledge Status bit (bit ny ch c tc dng khi truyn d liu ch I2C Master mode). ACKSTAT = 1 nhn c xung t I2C Slave. ACKSTAT = 0 chaq nhn c xung . Bit 5 ACKDT Acknowledge Data bit (bit ny ch c tc dng khi nhn d liu ch I2C Master mode). ACKDT = 1 cha nhn c xung . ACKDT = 0 nhn c xung . Bit 4 ACKEN Acknowledge Sequence Enable bit (bit ny ch c tc dng khi nhn d liu ch I2C Master mode) ACKEN = 1 cho php xung xut hin 2 pin SDA v SCL khi kt thc qu trnh nhn d liu. ACKEN = 0 khng cho php tc ng trn. Bit 3 RCEN Receive Enable bit (bit ny ch c tc dng ch I2C Master mode). RCEN = 1 Cho php nhn d liu ch I2C Master mode. RCEN = 0 Khng cho php nhn d liu. Bit 2 PEN Stop Condition Enable bit PEN = 1 cho php thit lp iu kin Stop 2 pin SDA v SCL. PEN = 0 khng cho php tc ng trn. Bit 1 RSEN Repeated Start Condition Enable bit RSEN = 1 cho php thit lp iu kin Start lp li lin tc 2 pin SDA v SCL. RSEN = 0 khng cho php tc ng trn. Bit 0 SEN Start Condition Enable/Stretch Enable bit ch Master mode: SEN = 1 cho php thit lp iu kin Start 2 pin SDA v SCL. SEN = 0 khng cho php tc ng trn. ch Slave mode: SEN = 1 cho php kha xung clock t pin SCL ca I2C Master. Khng cho php tc ng trn. 42. Thanh ghi PR2: a ch 92h Thanh ghi dng n nh trc gi tr m cho Timer2. Khi vi iu khin c reset, PR2 mang gi tr FFh. Khi ta a mt gi tr vo thanh ghi PR2, Timer2 s m t 00h cho n khi gi tr b m ca Timer2 bng vi gi tr ca b m trong thanh ghi PR2. Nh vy mc nh Timer2 s m t 00h n FFh.
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43. Thanh ghi SSPADD: a ch 93h Thanh ghi cha a ch ca vi iu khin khi hot ng chun giao tip I2C Slave mode. Khi khng dng cha a ch (I2C Master mode) SSPADD c dng cha gi tr to ra xung clock ng b ti pin SCL. 44. Thanh ghi SSPSTAT: a ch 94h Thanh ghi cha cc bit trng thi ca chun giao tip MSSP. SMP Bit 7 CKE D/A P S R/W UA BF Bit 0
Khi MSSP hot ng ch SPI: Bit 7 SMP Sample bit SPI Master mode: SMP = 1 d liu c ly mu (xc nh trang thi logic) ti thi im cui xung clock. SMP = 0 d liu c ly mu ti thi im gia xung clock. SPI Slave mode: bit ny phi c xa v 0. Bit 6 CKE SPI Clock Select bit CKE = 1 SPI Master truyn d liu khi xung clock chuyn t trng thi tch cc n trng thi ch. CKE = 0 SPI Master truyn d liu khi xung clock chuyn t trng thi ch n trng thi tch cc.(trng thi ch c xc nh bi bit CKP (SSPCON<4>). Bit 5 bit. Bit ny ch c tc dng ch I2C mode. Bit 4 P Stop bit Bit ny ch s dng khi MSSP ch I2C. Bit 3 S Start bit Bit ny ch c tc dng khi MSSP ch I2C. Bit 2 bit information Bit ny ch c tc dng khi MSSP ch I2C. Bit 1 UA Update Address bit Bit ny ch c tc dng khi MSSP ch I2C. Bit 0 BF Buffer Status bit BF = 1 thanh ghi m SSPBUF c d liu. BF = 0 thanh ghi m SSPBUF cha c d liu. Khi hot ng ch I2C Bit 7 SPM Slew Rate Control bit SPM = 1 dng tc chun (100 KHz v 1 MHz).
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SPM = 0 dng tc cao ( 400 KHz). Bit 6 CKE MSBus Select bit CKE = 1 cho php MSBus. CKE = 0 khng cho php MSBus. Bit 5 bit I2C Master mode: khng quan tm. = 1 byte va truyn i hoc nhn c l d liu. = 0 byte va truyn i hoc nhn c l a ch. Bit 4 P Stop bit P = 1 va nhn c bit Stop. P = 0 cha nhn c bit Stop. Bit 3 S Start bit S = 1 va nhn c bit Start. S = 0 cha nhn c bit Start. Bit 2 bit information I2C Slave mode: = 1 c d liu. = 0 ghi d liu. I2C Master mode: = 1 ang truyn d liu. = 0 khng truyn d liu. Bit 1 UA Update Address Bit ny ch c tc dng i vi ch I2C Slave mode10 bit a ch. UA = 1 vi iu khin cn cp nht thm a ch t thanh ghi SSPADD. UA = 0 khng cn cp nht thm a ch. Bit 0 BF Buffer Full Status bit BF = 1 Thanh ghi SSPBUF ang cha d liu truyn i hoc nhn c. BF = 0 thanh ghi SSPBUF khng c d liu. 45. Thanh ghi TXSTA: a ch 98h Thanh ghi cha cc bit trng thi v iu khin vic truyn d liu thng qua chun giao tip USART. CSRC Bit 7 TX-9 TXEN SYNC BRGH TRMT TX9D Bit 0
Bit 7 CSRC Clock Source Select bit ch bt ng b: khng cn quan tm. ch ng b: CSRC = 1 Master mode (xung clock c ly t b to xung BRG).
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CSRC = 0 Slave mode (xung clock c nhn t bn ngoi). Bit 6 TX-9 9-bit Transmit Enable bit TX-9 = 1 truyn d liu 9 bit. TX-9 = 0 truyn d liu 8 bit. Bit 5 TXEN Transmit Enable bit TXEN = 1 cho php truyn. TXEN = 0 khng cho php truyn. Bit 4 SYNC USART Mode Select bit SYNC = 1 dng ng b SYNC = 0 dng bt ng b. Bit 3 Khng cn quan tm v mc nh mang gi tr 0. Bit 2 BRGH High Baud Rate Select bit, Bit ny ch c tc dng ch bt ng b. BRGH = 1 tc cao. BRGL = 0 tc thp. Bit 1 TRMT Transmit Shift Register Status bit TRMT = 1 thanh ghi TSR khng c d liu. TRMT = 0 thanh ghi TSR c cha d liu. Bit 0 TX9D Bit ny cha bit d liu th 9 khi d liu truyn nhn l 9 bit. 45. Thanh ghi SPBRG: a ch 99h Thanh ghi cha gi tr to xung clock cho b to xung BRG (Baud Rate Generator). Tn s xung clock do BRG to ra c tnh theo cc cng thc trong bng sau:
46.Thanh ghi CMCON: a ch 9Ch Thanh ghi iu khin v ch th cc trng thi cng nh kt qu ca b so snh. C2OUT C1OUT Bit 7 C2INV C1INV CIS CM2 CM1 CM0 Bit 0
Bit 7 C2OUT Comparator 2 (C2) Output bit Khi C2INV = 0 C2OUT = 1 khi (pin VIN+ ca C2)> (pin VIN- ca C2). C2OUT = 0 khi (pin VIN+ ca C2) < (pin VIN- ca C2). Khi C2INV = 1 C2OUT = 1 khi (pin VIN+ ca C2)< (pin VIN- ca C2).
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C2OUT = 0 khi (pin VIN+ ca C2) > (pin VIN- ca C2). Bit 6 C1OUT Comparator 1 (C1) Output bit Khi C1INV = 0 C1OUT = 1 khi (pin VIN+ ca C1)> (pin VIN- ca C1). C1OUT = 0 khi (pin VIN+ ca C1) < (pin VIN- ca C1). Khi C1INV = 1 C1OUT = 1 khi (pin VIN+ ca C1)< (pin VIN- ca C1). C1OUT = 0 khi (pin VIN+ ca C1) > (pin VIN- ca C1). Bit 5 C2INV Comparator 2 Output Conversion bit C2INV = 1 ng ra C2 c o trng thi. C2INV = 0 ng ra C2 khng o trng thi. Bit 4 C1INV Comparator 1 Output Conversion bit C1INV = 1 ng ra C1 c o trng thi. C1INV = 0 ng ra C1 khng o trng thi. Bit 3 CIS Comparator Input Switch bit Bit ny ch c tc dng khi CM2:CM0 = 110 CIS = 1 khi pin VIN- ca C1 ni vi RA3/AN3 v pin VIN- ca C2 ni vi RA2/AN2 CIS = 0 khi pin VIN- ca C1 ni vi RA0/AN0 v pin VIN- ca C2 ni vi RA1/AN1 Bit 2-0 CM2:CM0 Comparator Mode bit Cc bit ny ng vai tr trong vic thit lp cc cu hnh hot ng ca b Comparator. 47. Thanh ghi CVRCON: a ch 9Dh Thanh ghi iu khin b to in p so snh khi b Comparator CVREN CVROE Bit 7 CVRR CVR3 CVR2 CVR1 CVR0 Bit 0
Bit 7 CVREN Comparator Voltage Reference Enable bit. CVREN = 1 b to in p so snh c cp in p hot ng. CVREN = 0 b to in p so snh khng c cp in p hot ng. Bit 6 CVROE Comparator VREF Output Enable bit CVROE = 1 in p do b to in p so snh to ra c a ra pin RA2. CVROA = 0 in p do b to in p so snh to ra khng c a ra ngoi. Bit 5 CVRR Comparator VREF Range Selection bit CVRR = 1 mt mc in p c gi tr VDD/24 (in p do b to in p so snh to ra c gi tr t 0 n 0.75VDD).
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CVRR = 0 mt mc in p c gi tr VDD/32 (in p do b to in p so snh to ra c gi tr t 0.25 n 0.75VDD). Bit 4 Khng cn quan tm v mc nh mang gi tr 0. Bit 3-0 CVR3:CVR0 Cc bit chn in p ng ra ca b to in p so snh. Khi CVRR = 1: in p ti pin RA2 c gi tr CVREF = (CVR<3:0>/24)*VDD. Khi CVRR = 0 in p ti pin RA2 c gi tr CVREF = (CVR<3:0>/32)*VDD + VDD. 48. Thanh ghi ADRESL: a ch 9Eh Thanh ghi cha cc bit thp ca kt qu b chuyn i A/D (8 bit cao cha trong thanh ghi ADRESH a ch 1Eh). 50. Thanh ghi EEDATA: a ch 10Ch Thanh ghi cha byte thp ca d liu trong qu trnh ghi c trn b nh d liu EEPROM. 51. Thanh ghi EEADR: a ch 10Dh Thanh ghi cha byte thp ca a ch trong qu trnh ghi c trn b nh d liu EEPROM. 52. Thanh ghi EEDATH: a ch 10Eh Thanh ghi cha byte cao ca d liu trong qu trnh ghi c trn b nh d liu EEPROM (thanh ghi ny ch s dng 6 bit thp). 53. Thanh ghi EEADRH: a ch 10Fh Thanh ghi cha byte cao ca a ch trong qu trnh ghi c trn b nh d liu EEPROM (thanh ghi ny ch s dng 4 bit thp). 54. Thanh ghi EECON1: a ch 18Ch Thanh ghi iu khin b nh EEPROM.
EEPGD
WRERR
WREN
WR
Bit 7
Bit 7 EEPGD Program/Data EEPROM Select bit
RD Bit 0
EEPGD = 1 truy xut b nh chng trnh. EEPGD = 0 truy xut b nh d liu. Bit 6-4 Khng cn quan tm v mc nh mang gi tr 0. Bit 3 WRERR EEPROM Error Flag bit WRERR = 1 qu trnh ghi ln b nh b gin on v khng th tip tc (do cc ch Reset WDT hoc ). WRERR = 0 qu trnh ghi ln b nh hon tt. Bit 2 WREN EEPROM Write Enable bit
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WREN = 1 cho php ghi. WREN = 0 khng cho php ghi. Bit 1 WR Write Control bit WR = 1 ghi d liu. Bit ny ch c set bng chng trnh v t ng xa v 0 khi qu trnh ghi d liu hon tt. WR = 0 hon tt qu trnh ghi d liu. Bit 0 RD Read Control bit RD = 1 c d liu. Bit ny ch c set bng chng trnh v t ng xa v 0 khi qu trnh c d liu hon tt. RD = 0 qu trnh c d liu khng xy ra. 55.Thanh ghi EECON2: a ch 18Dh. y l mt trong 2 thanh ghi iu khin b nh EEPROM. Tuy nhin y khng phi l thanh ghi vt l thng thng v khng cho php ngi1 s dng truy xut d liu trn thanh ghi.
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CHNG 2: T CHC B NH - CC THANH GHI CHC NNG......6

CHNG 3: TP LNH - CU TRC CHNG TRNH..........................17

CHNG 4: CC KHI CHC NNG........................................................46

CHNG 5: CNG NI TIP.......................................................................67

CHNG 6: NGT INTERRUPT..............................................................80

* PH LC: CC THANH GHI CHC NNG..............................105

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TNG QUAN V VI IU KHIN PIC

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T CHC B NH - CC THANH GHI CHC NNG

Hnh 2.1: S chn v hnh dng ca Pc 16F877A

Gio trnh Vi iu Khin Chc nng cc chn :

Tn /VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/TOCKI/C1OUT RA5/AN4/ /C2OUT

RE0/ RE1/ RE2/

/AN5 /AN6 /AN7

VDD VSS OSC1/CLKI

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RC0/T1 OCO/T1CKI RC1/T1OSI/CCP2

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RB0/INT RB1 RB2 RB3 RB4 RB5 RB6/PGC RB7/PGD

2.2 MT VI THNG S V VI IU KHIN PIC16F877A

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2.3 S KHI VI IU KHIN PIC16F877A

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Hnh 2.2: Cu trc bn trong ca Pic 16F877A

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Hnh 2.3: B nh chng trnh ca Pic

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Hnh 2.4: B nh b nh ca Pic

2.5 CC THANH GHI C BIT - THANH GHI FSR V INDF

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TP LNH - CU TRC CHNG TRNH

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3.2. TO TR BNG VNG LP

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Gio trnh Vi iu Khin

Gio trnh Vi iu Khin

3.4. CC KHI GIAO TIP 3.4.1. GIAO TIP VI LED 7 OAN

Gio trnh Vi iu Khin

Hnh 3.4:K hiu Led 7 on

Hnh 3.5: Dng s hin th ln Led 7 on

Hnh 3.6: Hnh dng Led 7 on Bi tp 1: Vit chng trnh hin th s 3

Gio trnh Vi iu Khin

STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 STATUS,5

Gio trnh Vi iu Khin

Hnh 3.8 PROCESSOR 16F877A #INCLUDE <P16F877A.INC>

STATUS,6 STATUS,5 PORTB PORTC STATUS,5 TRISB TRISC,4 TRISC,5 STATUS,5