B CNG THNG TRNG I HC CNG NGHIP H NI KHOA IN T

ti: Nghin cu v vi iu khin PIC 16F877A

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GV hng dn : SV thc hin : Lp Khoa Trng : in T 1 K2 : in T : i hc Cng Nghip H Ni

ec tro ni

v mt s ng dng. 16F877A

C th: Nghin cu v thit k b KIT PIC

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LUN VN TT NGHIP

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LUN VN TT NGHIP

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LUN VN TT NGHIP

B CNG THNG CNG HO X HI CH NGHA VIT NAM TRNG H CNG NGHIP H NI c lp - T do - Hnh phc

THC TP TT NGHIP I HC H v tn hc sinh : TRN XUN CHIN Lp : IN T 1 K2 Kho : 2 Khoa, Trung tm : IN T

C th: Nghin cu v thit k b KIT PIC 16F877A Gio vin hng dn : PHM TH QUNH TRANG

TT

2 3 4

Gii thiu v PIC 16F877A

ng dng PIC 16F877A xy dng b kit thc hnh vi iu khin

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Ngy giao ti : . Ngy hon thnh : .

TRNG KHOA

GIO VIN HNG DN

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Tng quan v vi iu khin

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Ni dung

NI DUNG YU CU

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Tn ti: Nghin cu v vi iu khin PIC 16F877A v mt s ng dng.

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LUN VN TT NGHIP

nh gi v nhn xt ca GV hng dn
........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................ ........................................................................................................................................
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MC LC
LI M U
Ngy nay k thut vi iu khin tr nn quen thuc trong cc ngnh k thut v trong dn dng. Cc b vi iu khin c kh nng x l nhiu hot ng phc tp m ch cn mt chip vi mch nh, n thay th cc t iu khin ln v phc tp bng nhng mch in gn nh, d dng thao tc s dng. to ln vo vic pht trin thng tin. Chnh v cc l do trn, vic tm hiu, kho st thut in-in t phi ht sc quan tm. chnh l mt nhu cu cn thit v cp bch i vi mi sinh vin, ti ny c thc hin chnh l p ng nhu cu . Cc b iu khin s dng vi iu khin tuy n gin nhng vn hnh v s vo con ngi, chnh l chng trnh hay phn mm. Nu khng c s tham gia n vi iu khin cng ging nh my tnh bao gm 2 phn l phn cng v phn mm. Mc d vi iu khin i c nhng bc di nh vy nhng tip cn c vi k thut ny khng th l mt vic c c trong mt sm mt chiu. tm hiu b vi iu khin mt cch khoa hc v mang li hiu qu cao lm nn tn cho vic xm nhp vo nhng h thng ti tn hn. Vic trang b nhng kin thc v vi iu khin cho sinh vin l ht sc cn thit. Xut pht t thc tin ny em i n quyt nh Thit k b Kit Vi iu Khin PIC 16F877A nhm p ng nhu cu ham mun hc hi ca bn than v gip cho cc bn sinh vin d tip cn v hiu su hn v VK PIC. Trong qu trnh thc hin ti vn cn nhiu sai st, mong nhn c nhiu kin ng gp t c v cc bn. Em chn thnh cm n! H ni, ngy 19 thng 4 nm 2011 Sinh vin
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ca con ngi th h thng vi iu khin cng ch l mt vt v tri. Do vy khi ni

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dng c li l mt iu rt phc tp. Phn cng vic x l chnh vn ph thuc

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vi iu khin l iu m cc sinh vin ngnh in m c bit l chuyn ngnh k

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Vi iu khin khng nhng gp phn vo k thut iu khin m cn gp phn

LUN VN TT NGHIP Trn Xun Chin

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CHNG 1: TNG QUAN V VI IU KHIN

1.1 GII THIU KHI QUT V VI IU KHIN

1.1.1 GII THIU CHUNG B Vi x l c kh nng vt bc so vi cc h thng khc v kh nng tnh ton, x l, v thay i chng trnh linh hot theo mc ch ngi dng, c bit hiu qu i vi cc bi ton v h thng ln.Tuy nhin i vi cc ng dng nh, cn nhc. Bi v h thng d ln hay nh, nu dng vi x l th cng i hi cc d liu v chng trnh thc hin, cc mch in giao tip ngoi vi xut nhp v iu khin tr li, cc khi ny cng lin kt vi vi x l th mi thc hin c cng vic. kt ni cc khi ny i hi ngi thit k phi hiu bit tinh tng phc tp, chim nhiu khng gian, mch in phc tp v vn chnh l trnh p dng cho cc h thng nh. v cc thnh phn vi x l, b nh, cc thit b ngoi vi. H thng c to ra kh ngi thit k. Kt qu l gi thnh sn phm cui cng rt cao, khng ph hp V mt s nhc im trn nn cc nh ch to tch hp mt t b nh v mt s mch giao tip ngoi vi cng vi vi x l vo mt IC duy nht c gi l Microcontroller- Vi iu khin.
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Mt s c im khc nhau gia vi x l v VK: V phn cng: VXL cn c ghp thm cc thit b ngoi vi bn ngoi nh b nh, v cc thit b ngoi vi khc, c th to thnh mt bn mch hon chnh. i vi VK th bn thn n l mt h my tnh hon chnh vi CPU, b nh, cc mch giao tip, cc b nh thi v mch iu khin ngt c tch hp bn trong mch.
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V cc c trng ca tp lnh: Do ng dng khc nhau nn cc b VXL v VK cng c nhng yu cu khc nhau i vi tp lnh ca chng. Tp lnh ca cc VXL thng mnh v cc kiu nh a ch vi cc lnh cung cp cc hot ng trn cc lng d liu ln nh 1byte, byte, word, double word,... cc b VK, cc tp lnh rt mnh trong vic x l cc kiu d liu nh nh bit

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khi mch in giao tip phc tp nh nhau. Cc khi ny bao gm b nh cha

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tm tnh ton khng i hi kh nng tnh ton ln th vic ng dng vi x l cn

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LUN VN TT NGHIP hoc mt vi bit.

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Do VK cu to v phn cng v kh nng x l thp hn nhiu soi vi VXL nn gi thnh ca VK cng r hn nhiu. Tuy nhin n vn kh nng p ng c tt c cc yu cu ca ngi dng.

Vi iu khin c ng dng trong cc dy chuyn t ng loi nh, cc robot c chc nng n gin, trong my git, t v.v... 1.1.2 PHN LOI di thanh ghi Da vo di ca cc thanh ghi v cc lnh ca VK m ngi ta chia ra cc loi VK 8bit, 16bit, hay 32bit.... Cc loi VK 16bit do c di lnh ln hn nn cc tp lnh cng nhiu hn, phong ph hn. Tuy nhin bt c chng trnh no vit bng VK 16bit chng ta u c th vit trn VDK 8bit vi chng trnh thch hp. Kin trc CISC v RISC

VXL hoc VK CISC l VK c tp lnh phc tp. Cc VK ny c mt s lng ln cc lnh nn gip cho ngi lp trnh c th linh hot v d dng hn khi vit chng trnh. VK RISC l VK c tp lnh n gin. Chng c mt s lng nh cc lnh n gin. DO , chng i hi phn cng t hn, gi thnh thp hn, v nhanh hn so vi CISC. Tuy nhin n i hi ngi lp trnh phi vit cc chng trnh phc tp hn, nhiu lnh hn. Kin trc Harvard v kin trc Vonneumann

Kin trc Harvard s dng b nh ring bit cho chng trnh v d liu. Bus a

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ch v bus d liu c lp vi nhau nn qu trnh truyn nhn d liu n gin hn Kin trc Vonneumann s dng chung b nh cho chng trnh v d liu. iu ny lm cho VK gn nh hn, gi thnh nh hn. Mt s loi VK c trn th trng:
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VK AVR AT90Sxxxx VK PIC 16C5x, 17C43...

VK MCS-51: 8031, 8032, 8051, 8052, ... VK ATMEL: 89Cxx, AT89Cxx51..

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1.1.3 CU TRC TNG QUAN CA VDK CPU: L tri tim ca h thng. L ni qun l tt c cc hot ng ca VK. Bn trong CPU gm: ALU l b phn thao tc trn cc d liu B gii m lnh v iu khin, xc nh cc thao tc m CPU cn thc hin Thanh ghi lnh IR, lu gi opcode ca lnh c thc thi Mt tp cc thanh ghi dng lu thng tin tm thi

Thanh ghi PC, lu gi a ch ca lnh k tip cn thc thi

2. ROM:

cc bng, cc tham s h thng, cc s liu c nh ca h thng. Trong qu trnh hot ng ni dung ROM l c nh, khng th thay i, ni dung ROM ch thay i khi ROM ch xa hoc np chng trnh. RAM: RAM l b nh d liu. B nh RAM dng lm mi trng x l thng tin, lu tr cc kt qu trung gian v kt qu cui cng ca cc php ton, x l thng tin. N cng dng t chc cc vng m d liu, trong cc thao tc thu pht, chuyn i d liu. BUS:

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BUS l cc ng dn dng di chuyn d liu. Bao gm: bus a ch, bus

B NH THI: c s dng cho cc mc ch chung v thi gian. WATCHDOG: B phn dng reset li h thng khi h thng gp bt

d liu , v bus iu khin

thng.
ADC: B phn chuyn tn hiu analog sang tn hiu digital. Cc tn hiu bn

ngoi i vo VDK thng dng analog. ADC s chuyn tn hiu ny v dng tn hiu digital m VDK c th hiu c.
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ROM l b nh dng lu gi chng trnh. ROM cn dng cha s liu

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1.2

KHI QUT V VI IU KHIN PIC

PIC l vit tt ca Programable Intelligent Computer, c th tm dch l my

1.2.1 PIC L G ? tnh thng minh kh trnh do hng Genenral Instrument t tn cho vi iu khin u tin ca h: PIC1650 c thit k dng lm cc thit b ngoi vi cho vi iu khin CP1600. Vi iu khin ny sau c nghin cu pht trin thm v t hnh thnh nn dng vi iu khin PIC ngy nay. 1.2.2 KIN TRC PIC kin trc Von Neuman v kin trc Havard.

Cu trc phn cng ca mt vi iu khin c thit k theo hai dng kin trc:

T chc phn cng ca PIC c thit k theo kin trc Havard. im khc bit

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gia kin trc Havard v kin trc Von-Neuman l cu trc b nh d liu v b nh chng trnh. i vi kin trc Von-Neuman, b nh d liu v b nh chng trnh nm chung trong mt b nh, do ta c th t chc, cn i mt cch linh hot b nh chng trnh v b nh d liu. Tuy nhin iu ny ch c ngha khi tc x l ca CPU phi rt cao, v vi cu trc , trong cng mt thi im CPU ch c th tng tc vi b nh d liu hoc b nh chng trnh. Nh vy c th ni kin trc Von-Neuman khng thch hp vi cu trc ca mt vi iu khin. i vi kin trc Havard, b nh d liu v b nh chng trnh tch ra thnh
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Hnh 1.1: Kin trc Havard v kin trc Von-Neuman

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LUN VN TT NGHIP hai b nh ring bit. Do trong cng mt thi im CPU c th tng tc vi c hai b nh, nh vy tc x l ca vi iu khin c ci thin ng k. Mt im cn ch na l tp lnh trong kin trc Havard c th c ti u ty theo yu cu kin trc ca vi iu khin m khng ph thuc vo cu trc d liu. V d, i vi vi iu khin dng 16F, di lnh lun l 14 bit (trong khi d liu c t chc thnh tng byte), cn i vi kin trc Von-Neuman, di lnh lun l bi s ca 1 byte (do d liu c t chc thnh tng byte). c im ny c minh ha c th trong hnh 1.1. 1.2.3 RISC V CISC Nh trnh by trn, kin trc Havard l khi nim mi hn so vi kin trc Von-Neuman. Khi nim ny c hnh thnh nhm ci tin tc thc thi ca mt vi iu khin. Qua vic tch ri b nh chng trnh v b nh d liu, bus chng trnh v bus d liu, CPU c th cng mt lc truy xut c b nh chng trnh v b nh d liu, gip tng tc x l ca vi iu khin ln gp i. ng thi cu trc lnh khng cn ph thuc vo cu trc d liu na m c th linh ng iu chnh ty theo kh nng v tc ca tng vi iu khin. V tip tc ci tin tc thc thi lnh, tp lnh ca h vi iu khin PIC c thit k sao cho chiu di m lnh lun c nh (v d i vi h 16Fxxxx chiu di m lnh lun l 14 bit) v cho php thc thi lnh trong mt chu k ca xung clock ( ngoi tr mt s trng hp c bit nh lnh nhy, lnh gi chng trnh con cn hai chu k xung ng h). iu ny c ngha tp lnh ca vi iu khin thuc cu trc Havard s t lnh hn, ngn hn, n gin hn p ng yu cu m ha lnh bng mt s lng bit

El

nht nh.

RISC (Reduced Instruction Set Computer) hay vi iu khin c tp lnh rt gn. Vi iu khin c thit k theo kin trc Von-Neuman cn c gi l vi iu khin CISC (Complex Instruction Set Computer) hay vi iu khin c tp lnh phc tp v m lnh ca n khng phi l mt s c nh m lun l bi s ca 8 bit (1 byte). 1.2.4 PIPELINING y chnh l c ch x l lnh ca cc vi iu khin PIC. Mt chu k lnh ca vi iu khin s bao gm 4 xung clock. V d ta s dng oscillator c tn s 4 MHZ,
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Vi iu khin c t chc theo kin trc Havard cn c gi l vi iu khin

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LUN VN TT NGHIP th xung lnh s c tn s 1 MHz (chu k lnh s l 1 us). Gi s ta c mt on chng trnh nh sau: 1. MOVLW 2. MOVWF PORTB 3. CALL 4. BSF SUB_1 PORTA,BIT3 55h

5. instruction @ address SUB_1 y ta ch bn n qui trnh vi iu khin x l on chng trnh trn thng qua tng chu k lnh. Qu trnh trn s c thc thi nh sau:

El

Qu trnh ny c thc hin tng t cho cc lnh tip theo ca chng trnh. Thng thng, thc thi mt lnh, ta cn mt chu k lnh gi lnh , v mt chu k xung clock na gii m v thc thi lnh. Vi c ch pipelining c trnh
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TCY0: c lnh 1 TCY1: thc thi lnh 1, c lnh 2 TCY2: thc thi lnh 2, c lnh 3 TCY3: thc thi lnh 3, c lnh 4.

Hnh 1.2: C ch pipelining

TCY4: v lnh 4 khng phi l lnh s c thc thi theo qui trnh thc thi ca chng trnh (lnh tip theo c thc thi phi l lnh u tin ti label SUB_1) nn chu k thc thi lnh ny ch c dng c lnh u tin ti label SUB_1. Nh vy c th xem lnh 3 cn 2 chu k xung clock thc thi. TCY5: thc thi lnh u tin ca SUB_1 v c lnh tip theo ca SUB_1.

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LUN VN TT NGHIP by trn, mi lnh xem nh ch c thc thi trong mt chu k lnh. i vi cc lnh m qu trnh thc thi n lm thay i gi tr thanh ghi PC (Program Counter) cn hai chu k lnh thc thi v phi thc hin vic gi lnh a ch thanh ghi PC ch ti. Sau khi xc nh ng v tr lnh trong thanh ghi PC, mi lnh ch cn mt chu k lnh thc thi xong.

1.2.5 CC DNG PIC V CCH LA CHN VI IU KHIN PIC Cc k hiu ca vi iu khin PIC: F: PIC12xxxx: di lnh 12 bit PIC16xxxx: di lnh 14 bit PIC18xxxx: di lnh 16 bit

C: PIC c b nh EPROM (ch c 16C84 l EEPROM) PIC c b nh flash LF: PIC c b nh flash hot ng in p thp LV: tng t nh LF, y l k hiu c

Bn cnh mt s vi iu khin c k hiu xxFxxx l EEPROM, nu c thm ch A cui l flash (v d PIC16F877 l EEPROM, cn PIC16F877A l flash). Ngoi ra cn c thm mt dng vi iu khin PIC mi l dsPIC. Vit Nam ph bin nht l cc h vi iu khin PIC do hng Microchip sn xut.
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Cch la chn mt vi iu khin PIC ph hp:

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chn.

Trc ht cn ch n s chn ca vi iu khin cn thit cho ng dng. C nhiu vi iu khin PIC vi s lng chn khc nhau, thm ch c vi iu khin ch c 8 chn, ngoi ra cn c cc vi iu khin 28, 40, 44, Cn chn vi iu khin PIC c b nh flash c th np xa chng trnh c nhiu ln hn. Tip theo cn ch n cc khi chc nng c tch hp sn trong vi iu khin, cc chun giao tip bn trong. Sau cng cn ch n b nh chng trnh m vi iu khin cho php. Ngoi ra mi thng tin v cch la chn vi iu khin PIC c th c tm
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LUN VN TT NGHIP thy trong cun sch Select PIC guide do nh sn xut Microchip cung cp. 1.2.6 NGN NG LP TRNH CHO PIC Ngn ng lp trnh cho PIC rt a dng. Ngn ng lp trnh cp thp c MPLAB (c cung cp min ph bi nh sn xut Microchip), cc ngn ng lp trnh cp cao hn bao gm C, Basic, Pascal, Ngoi ra cn c mt s ngn ng lp trnh c pht trin dnh ring cho PIC nh PICBasic, MikroBasic, 1.2.7 MCH NP PIC y cng l mt dng sn phm rt a dng dnh cho vi iu khin PIC. C th s dng cc mch np c cung cp bi nh sn xut l hng Microchip nh: PICSTART plus, MPLAB ICD 2, MPLAB PM 3, PRO MATE II. C th dng cc sn phm ny np cho vi iu khin khc thng qua chng trnh MPLAB. Dng sn phm chnh thng ny c u th l np c cho tt c cc vi iu khin PIC, tuy nhin gi thnh rt cao v thng gp rt nhiu kh khn trong qu trnh mua sn phm. Ngoi ra do tnh nng cho php nhiu ch np khc nhau, cn c rt nhiu mch np c thit k dnh cho vi iu khin PIC. C th s lc mt s mch np cho PIC nh sau:
-

JDM programmer: mch np ny dng chng trnh np Icprog cho php np cc vi iu khin PIC c h tr tnh nng np chng trnh in p thp ICSP (In Circuit Serial Programming). Hu ht cc mch np u h tr tnh nng np chng trnh ny.

WARP-13A v MCP-USB: hai mch np ny ging vi mch np PICSTART PLUS do nh sn xut Microchip cung cp, tng thch vi trnh bin dch MPLAB, ngha l ta c th trc tip dng chng trnh MPLAB np cho vi iu khin PIC m khng cn s dng mt chng trnh np khc, chng hn nh ICprog.

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P16PRO40: mch np ny do Nigel thit k v cng kh ni ting. ng cn thit k c chng trnh np, tuy nhin ta cng c th s dng chng trnh np Icprog.

Mch np Universal ca Williem: y khng phi l mch np chuyn dng dnh cho PIC nh P16PRO40.

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LUN VN TT NGHIP Cc mch np k trn c u im rt ln l n gin, r tin, hon ton c th t lp rp mt cch d dng, v mi thng tin v s mch np, cch thit k, thi cng, kim tra v chng trnh np u d dng tm c v download min ph thng qua mng Internet. Tuy nhin cc mch np trn c nhc im l hn ch v s vi iu khin c h tr, bn cnh mi mch np cn c s dng vi mt chng trnh np thch hp.

CHNG 2: VI IU KHIN PIC16F877A

2.1 GII THIU CHUNG

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2.1.1 CC DNG S CHN

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2.1.2 S KHI VI IU KHIN PIC16F877A

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Hnh 2.1 Vi iu khin PIC16F877A/PIC16F874A v cc dng s chn
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Hnh 2.2 l s khi ca PIC 16F877A, gm cc khi:

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Hnh 2.2 S o khoi vi ieu khien PIC16F877A.

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LUN VN TT NGHIP -

Khi ALU Arithmetic Logic Unit. Khi b nh cha chng trnh Flash Program Memory. Khi b nh cha d liu EPROM Data EPROM. Khi b nh file thanh ghi RAM RAM file Register. Khi gii m lnh v iu khin Instruction Decode Control. Khi thanh ghi c bit. Khi ngoi vi timer.

Khi chuyn i tn hiu tng t sang s - ADC. Khi cc port xut nhp.

2.1.3 CHC NNG CC CHN CA PIC16F877A

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Chn OSC1/CLK1(13): ng vo kt ni vi dao ng thch anh hoc ng vo nhn xung clock t bn ngoi. Chn OSC2/CLK2(14): ng ra dao ng thch anh hoc ng ra cp xung clock. Chn
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(1) c 2 chc nng : ng vo reset tch cc mc thp.

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Khi giao tip ni tip.

LUN VN TT NGHIP Vpp: ng vo nhn in p lp trnh khi lp trnh cho PIC. RA0,1,2: xut/ nhp s. AN 0,1,2: ng vo tng t ca knh th 0,1,2.

Chn RA0/AN0(2), RA1/AN1(3), RA2/AN2(3): c 2 chc nng

Chn RA2/AN2/VREF-/CVREF+(4): xut nhp s/ ng vo tng t ca knh th 2/ nh vo in p chun thp ca b AD/ ng vo in p chn cao ca b AD.

Chn RA3/AN3/VREF+(5): xut nhp s/ ng vo tng t knh 3/ ng vo in p chun (cao) ca b AD. cho Timer 0/ ng ra b so snh 1. Chn RA4/TOCK1/C1OUT(6): xut nhp s/ ng vo xung clock bn ngoi

Chn RA5/AN4/

/ C2OUT(7): xut nhp s/ ng vo tng t knh 4/

ng vo chn la SPI ph/ ng ra b so snh 2.

Chn RB1(34), RB2(35): xut nhp s.

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ICSP. ra PWM1. I2C. I2C.

Chn RB3/PGM(36): xut nhp s/ cho php lp trnh in p thp ICSP. Chn RB4(37), RB5(38): xut nhp s. Chn RB6/PGC(39): xut nhp s/ mch g ri v xung clock lp trnh Chn RB7/PGD(40): xut nhp s/ mch g ri v d liu lp trnh ICSP. Chn RC0/T1OCO/T1CKI(15): xut nhp s/ ng vo b giao ng Timer1/ ng vo xung clock bn ngoi Timer 1. Chn RC1/T1OSI/CCP2(16) : xut nhp s/ ng vo b dao ng Timer 1/ ng vo Capture2, ng ra compare2, ng ra PWM2. Chn RC2/CCP1(17): xut nhp s/ ng vo Capture1 ,ng ra compare1, ng Chn RC3/SCK/SCL(18): xut nhp s/ ng vo xung clock ni tip ng b, ng ra ch SPI./ ng vo xung clock ni tip ng b, ng ra ca ch Chn RC4/SDI/SDA(23): xut nhp s/ d liu vo SPI/ xut nhp d liu

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Chn RB0/INT (33): xut nhp s/ ng vo tn hiu ngt ngoi.

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LUN VN TT NGHIP

Chn RC5/SDO(24): xut nhp s/ d liu ra SPI. Chn RC6/TX/CK(25): xut nhp s/ truyn bt ng b USART/ xung ng b USART. Chn RC7/RX/DT(26): xut nhp s/ nhn bt ng b USART. Chn RD0-7/PSP0-7(19-30): xut nhp s/ d liu port song song. Chn RE0/ tng t 5. /AN5(8): xut nhp s/ iu khin port song song/ ng vo

vo tng t knh th 6.

song/ ng vo tng t knh th 7.

Chn VDD(11, 32) v VSS(12, 31): l cc chn ngun ca PIC. y l vi iu khin thuc h PIC16Fxxx vi tp lnh gm 35 lnh c di 14

2.1.4 C IM VI IU KHIN PIC16F877A

bit. Mi lnh u c thc thi trong mt chu k xung clock. Tc hot ng ti bit, b nh d liu 368x8 byte RAM v b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O l 5 vi 33 pin I/O. C 8 knh chuyn i A/D Cc c tnh ngoi vi bao gmcc khi chc nng sau: Timer0: b m 8 bit vi b chia tn s 8 bit. Timer1: b m 16 bit vi b chia tn s, c th thc hin chc nng m da vo xung clock ngoi vi ngay khi vi iu khin hot ng ch sleep. Timer2: b m 8 bit vi b chia tn s, b postcaler. Hai b Capture/so snh/iu ch rng xung. Cc chun giao tip ni tip SSP (Synchronous Serial Port), SPI v I2C. Chun giao tip ni tip USART vi 9 bit a ch. Cng giao tip song song PSP (Parallel Slave Port) vi cc chn iu khin RD, WR, Bn cnh l mt vi c tnh khc ca vi iu khin nh: B nh flash vi kh nng ghi xa c 100.000 ln.
LP: IN T 1 K2 20

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-

a cho php l 20 MHz vi mt chu k lnh l 200ns. B nh chng trnh 8Kx14

cc

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Chn RE2/

/AN7(10): xut nhp s/ Chn chn la iu khin port song

et

Chn RE1/

/AN6(9): xut nhp s/ iu khin ghi port song song/ ng

LUN VN TT NGHIP -

B nh EEPROM vi kh nng ghi xa c 1.000.000 ln. D liu b nh EEPROM c th lu tr trn 40 nm. Kh nng t np chng trnh vi s iu khin ca phn mm. Np c chng trnh ngay trn mch in ICSP (In Circuit Serial Programming) thng qua 2 chn. Watchdog Timer vi b dao ng trong. Chc nng bo mt m chng trnh. Ch Sleep. C th hot ng vi nhiu dng Oscillator khc nhau.

El

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Bng 2.3: Tm tt c im ca VDK PIC 16F877A
LP: IN T 1 K2 21

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LUN VN TT NGHIP

2.2 T CHC B NH
Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh chng trn (Program memory) v b nh d liu (Data Memory). 2.2.1 B NH CHNG TRNH B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b thnh nhiu trang (t page0 n page 3) . Nh vy b nh chng trnh c kh nng cha c 8*1024 = 8192 lnh (v mt lnh bit). m ha c a ch ca 8K word dung lng 13 bit (PC<12:0>). nh 8K word (1 word = 14 bit) v c phn

sau khi m ha s c dung lng 1 word (14

b nh chng trnh, b m chng trnh c Khi vi iu khin c reset, b m

chng trnh s ch n a ch 0000h (Reset vector). Khi c ngt xy ra, b m chng trnh s ch n a ch 0004h (Interrupt vector). B nh chng trnh khng bao

ec tro ni
2.2.2 B NH D LIU

cc
Hnh 2.4 B nh chng trnh
LP: IN T 1 K2 22

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PIC16F877A

gm b nh stack v khng c a ch ha bi b m chng trnh. B nh stack s c cp c th trong phn sau. B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i vi PIC16F877A b nh d liu c chia ra lm 4 bank. Mi bank c dung lng 128 byte, bao gm cc thanh ghi c chc nng c bit SFG (Special Function Register) nm cc vng a ch thp v cc thanh ghi mc ch chung GPR (General Purpose Register) nm vng a ch cn li trong bank. Cc thanh ghi
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LUN VN TT NGHIP SFR thng xuyn c s dng (v d nh thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu PIC16F877A nh sau:

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LP: IN T 1 K2 23

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LUN VN TT NGHIP Hnh 2.5 S b nh d liu PIC16F877A

1. THANH GHI CHC NNG C BIT SFR

y l cc thanh ghi c s dng bi CPU hoc c dng thit lp v iu khin cc khi chc nng c tch hp bn trong vi iu khin. C th phn thanh ghi SFR lm hai lai: thanh ghi SFR lin quan n cc chc nng bn trong (CPU) v thanh ghi SRF dng thit lp v iu khin cc khi chc nng bn ngoi (v d nh ADC, PWM, ). Phn ny s cp n cc thanh ghi lin quan n cc chc nng bn trong. Cc thanh ghi dng thit lp v iu khin cc khi chc Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha kt qu thc hin b nh d liu. nng s c nhc n khi ta cp n cc khi chc nng .

Thanh ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi, tham s v xung tc ng, cnh tc ng ca ngt ngoi vi v b m Timer0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php c v ghi, cha cc bit iu khin v cc bit c hiu khi timer0 b trn, ngt ngoi vi RB0/INT v ngt interrput- on-change ti cc chn ca PORTB.

El

Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng ngoi vi.

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cho php iu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc

cc

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php ton ca khi ALU, trng thi reset v cc bit chn bank cn truy xut trong

et

LP: IN T 1 K2 24

LUN VN TT NGHIP Thanh ghi PIR1 (0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM.

Thanh ghi PIR2 (0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin.

El

Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh

ghi

FSG (File Select Register). y l cc thanh ghi d liu thng thng, ngi s dng c th ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc bin s, hng s, kt qu hoc cc tham s phc v cho chng trnh. 2.2.3 STACK Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh c bit khng cho php c hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC
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2. THANH GHI MC CH CHUNG GPR

cc

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LUN VN TT NGHIP t ng c vi iu khin ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh theo ng qui trnh nh trc. B nh Stack trong vi iu khin PIC h 16F87xA c kh nng cha c 8 a ch v hot ng theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tr 6 ct vo Stack ln th 2. Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit c khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin bi CPU.

2.3 CC CNG XUT NHP CA PIC16F877A

tc

Cng xut nhp (I/O port) chnh l phng tin m vi iu khin dng tng vi th gii bn ngoi. S tng tc ny rt a dng v thng qua qu trnh tng tc , chc nng ca vi iu khin c th hin mt cch r rng. cch b tr v chc nng ca vi iu khin m s lng cng xut nhp v s lng chn trong mi cng c th khc nhau. Bn cnh , do vi iu khin c tch hp sn bn trong cc c tnh giao tip ngoi vi nn bn cnh chc nng l cng xut nhp thng thng, mt s chn xut nhp cn c thm cc chc nng khc th hin s tc ng ca cc c tnh ngoi vi nu trn i vi th gii bn ngoi. Chc nng ca tng chn xut nhp trong mi cng hon ton c th c xc lp v iu

El

khin c thng qua cc thanh ghi SFR lin quan n chn xut nhp . Vi iu khin PIC16F877A c 5 cng xut nhp, bao gm PORTA, PORTB, PORTC, PORTD v PORTE. Cu trc v chc nng ca tng cng xut nhp s c cp c th trong phn sau. 2.3.1 PORTA PORTA (RPA) bao gm 6 I/O pin. y l cc chn hai chiu (bidirectional pin), ngha l c th xut v nhp c. Chc nng I/O ny c iu khin bi thanh ghi TRISA (a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l
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Mt cng xut nhp ca vi iu khin bao gm nhiu chn (I/O pin), ty theo

cc

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LUN VN TT NGHIP input, ta set bit iu khin tng ng vi chn trong thanh ghi TRISA v ngc li, mun xc lp chc nng ca mt chn trong PORTA l output, ta clear bit iu khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu khin tng ng TRIS (i vi PORTA l TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l TRISD vi vi PORTE l TRISE). Bn cnh PORTA cn l ng ra ca b ADC, b so snh, ng vo analog ng vo xung clock ca Timer0 v ng vo ca b giao tip MSSP (Master Synchronous Serial Port). c tnh ny s c trnh by c th trong phn sau. Cc thanh ghi SFR lin quan n PORTA bao gm:
PORTA (a ch 05h) TRISA (a ch 85h) : cha gi tr cc pin trong PORTA.

: cha gi tr cc pin trong PORTA.

CMCON (a ch 9Ch) : thanh ghi iu khin b so snh.

CVRCON (a ch 9Dh) : thanh ghi iu khin b so snh in p.

2.3.2 PORTB

TRISB. Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np chng trnh cho vi iu khin vi cc ch np khc nhau. PORTB cn lin quan n ngt ngoi vi v b Timer0. PORTB cn c tch hp chc nng in tr ko ln c iu khin bi chng trnh.
-

Cc thanh ghi SFR lin quan n PORTB bao gm: PORTB (a ch 06h,106h) TRISB (a ch 86h,186h) Timer0. : cha gi tr cc pin trong PORTB : iu khin xut nhp

El

2.3.3 PORTC PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISC. Bn cnh PORTC cn cha cc chn chc nng ca b so snh, b Timer1, b PWM v cc chun giao tip ni tip I2C, SPI, SSP, USART. Cc thanh ghi iu khin lin quan n PORTC:
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PORTC (a ch 07h)

PORTB (RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l

OPTION_REG (a ch 81h,181h) : iu khin ngt ngoi vi v b

cc

ADCON1 (a ch 9Fh) : thanh ghi ieu khien bo ADC.

: cha gia tr cac pin trong

LP: IN T 1 K2 27

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LUN VN TT NGHIP PORTC TRISC (a ch 87h) : ieu khien xuat nhap. 2.3.4 PORTD PORTD (RPD) gm 8 chn I/O, thanh ghi iu khin xut nhp tng ng l TRISD. PORTD cn l cng xut d liu ca chun giao tip PSP (Parallel Slave Port). Cc thanh ghi lin quan n PORTD bao gm: -

Thanh ghi PORTD : cha gi tr cc pin trong PORTD. Thanh ghi TRISD : iu khin xut nhp.

2.3.5 PORTE

PORTE (RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng l TRISE. Cc chn ca PORTE c ng vo analog. Bn cnh PORTE cn l cc chn iu khin ca chun giao tip PSP. -

Cc thanh ghi lin quan n PORTE bao gm: PORTE TRISE

: cha gi tr cc chn trong PORTE. : iu khin xut nhp v xc lp cc thng s cho chun

2.4 TIMER 0

y l mt trong ba b m hoc b nh thi ca vi iu khin PIC16F877A. Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer0 cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer0 s xut hin khi Timer0 b trn. Bit TMR0IE

El

(INTCON<5>) l bit iu khin ca Timer0. TMR0IE=1 cho php ngt Timer0 tc ng, TMR0IF= 0 khng cho php ngt Timer0 tc ng. S khi ca Timer0 nh sau:

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giao tip PSP. -

ADCON1 : thanh ghi iu khin khi ADC.

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LP: IN T 1 K2 28

LUN VN TT NGHIP

Hnh 2.6 S khi ca Timer0. (OPTION_REG<5>), khi gi tr thanh ghi TMR0 s tng theo tng chu k xung ng h (tn s vo Timer0 bng tn s oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ngt Timer0 s xut hin. Thanh ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt

Timer0 xut hin mt cch linh ng. Mun Timer0 hot ng ch counter ta set bit TOSC (OPTION_REG<5>). Khi xung tc ng ln b m c ly t

El

chn RA4/TOCK1. Bit TOSE (OPTION_REG<4>) cho php la chn cnh tc ng vo bt m. Cnh tc ng s l cnh ln nu TOSE=0 v cnh tc ng s l cnh xung nu TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON<2>) s c set. y chnh l c ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc hin li qu trnh m. Ngt Timer0 khng th nh thc vi iu khin t ch sleep. B chia tn s (prescaler) c chia s gia Timer0 v WDT (Watchdog Timer). iu c ngha l nu prescaler c s dng cho Timer0 th WDT s khng c
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Mun Timer0 hot ng ch Timer ta clear bit TOSC

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LUN VN TT NGHIP c h tr ca prescaler v ngc li. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3>) xc nh i tng tc ng ca prescaler. Cc bit PS2:PS0 (OPTION_REG<2:0>) xc nh t s chia tn s ca prescaler. Xem li thanh ghi OPTION_REG xc nh li mt cch chi tit v cc bit iu khin trn. Cc lnh tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler. Khi i tng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay i i tng tc ng ca prescaler. Khi i tng tc ng l WDT, lnh CLRWDT s xa prescaler, ng thi prescaler s ngng tc v h tr cho WDT. Cc thanh ghi iu khin lin quan n Timer0 bao gm: -

TMR0 (a ch 01h, 101h) : cha gi tr m ca Timer0. INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE). OPTION_REG (a ch 81h, 181h): iu khin prescaler.

2.5 TIMER1

Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh ghi (TMR1H:TMR1L). C ngt ca Timer1 l bit TMR1IF (PIR1<0>). Bit iu khin ca Timer1 s l TMR1IE (PIE<0>).

Tng t nh Timer0, Timer1 cng c hai ch hot ng: ch nh thi (timer) vi xung kch l xung clock ca oscillator (tn s ca timer bng tn s

El

ca oscillator) v ch m (counter) vi xung kch l xung phn nh cc s kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI (cnh tc ng l cnh ln). Vic la chn xung tc ng (tng ng vi vic la chn ch hot ng l timer hay counter) c iu khin bi bit TMR1CS (T1CON<1>). Sau y l s khi ca Timer1:

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LP: IN T 1 K2 30

LUN VN TT NGHIP

Hnh 2.7 S khi ca Timer1.

Ngoi ra Timer1 cn c chc nng reset input bn trong c iu khin bi mt trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set, Timer1 s ly xung clock t hai chn RC1/T1OSI/CCP2 v tin ca xung ng vo. Khi PORTC s b qua s tc ng ca hai bit TRISC<1:0> v PORTC<2:1> c gn gi tr 0. Khi clear bit T1OSCEN Timer1 s ly xung m t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 c hai ch m l ng b (Synchronous) v bt ng b (T1CON<2>). (Asynchronous). Ch m c quyt nh bi bit iu khin Khi RC0/T1OSO/T1CKI lm xung m. Timer1 s bt u m sau cnh xung u

xung clock bn trong, Timer1 s tip tc qu trnh m khi vi iu khin ang ch sleep v ngt do Timer1 to ra khi b trn c kh nng nh thc vi iu khin. ch m bt ng b,

El

Timer1 khng th c s dng lm ngun xung clock cho khi CCP =0 xung m vo

(Capture/Compare/Pulse width modulation). Khi khng hot ng khi vi iu khin ang ch sleep. Cc thanh ghi lin quan n Timer1 bao gm: -

Timer1 s c ng b ha vi xung clock bn trong. ch ny Timer1 s

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v PEIE).

=1 xung m ly t bn ngoi s khng c ng b ha vi

INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF).
LP: IN T 1 K2 31

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LUN VN TT NGHIP PIE1( a ch 8Ch): cho php ngt Timer1 (TMR1IE). TMR1L (a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1. TMR1H (a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1. T1CON (a ch 10h): xc lp cc thng s cho Timer1.

2.6 TIMER2
Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler v postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc ng l TMR2ON (T2CON<2>). C ngt ca Timer2 l bit TMR2IF (PIR1<1>). Xung ng vo (tn s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit (vi cc t s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0 (T2CON<1:0>)).

s tng t 00h n gi tr cha trong thanh ghi PR2, sau c reset v 00h. Kh I

El

reset thanh ghi PR2 c nhn gi tr mc nh FFh. Ng ra ca Timer2 c a qua b chia tn s postscaler vi cc mc chia t 1:1 n 1:16. Postscaler c iu khin bi 4 bit T2OUTPS3:T2OUTPS0. Ng ra ca postscaler ng vai tr quyt nh trong vic iu khin c ngt. Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn ng vai tr to ra xung clock ng b cho khi giao tip SSP. Cc thanh ghi lin quan n Timer2 bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ngt
LP: IN T 1 K2 32

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Hnh 2.8 S khi Timer2.

Timer2 cn c h tr bi thanh ghi PR2. Gi tr m trong thanh ghi TMR2

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LUN VN TT NGHIP (GIE v PEIE). PIR1 (a ch 0Ch): cha c ngt Timer2 (TMR2IF). PIE1 (a ch 8Ch): cha bit iu khin Timer2 (TMR2IE). TMR2 (a ch 11h): cha gi tr m ca Timer2. T2CON (a ch 12h): xc lp cc thng s cho Timer2. PR2 (a ch 92h): thanh ghi h tr cho Timer2.

Nhn xt v Timer0, Timer1 v Timer2 nh sau: Timer0 v Timer2 l b m 8 bit (gi tr m ti a l FFh), trong khi Timer1 l b m 16 bit (gi tr m ti a l FFFFh).

Timer0, Timer1 v Timer2 u c hai ch hot ng l timer v counter. Xung clock c tn s bng tn s ca oscillator. Xung tc ng ln Timer0 c h tr bi prescaler v c th c thit lp nhiu ch khc nhau (tn s tc nh. Timer2 c h tr bi hai b chia tn s prescaler v postcaler c lp, tuy nhin cnh tc ng vn c c nh l cnh ln. Timer1 c quan h vi khi CCP, trong khi Timer2 c kt ni vi khi SSP. Mt vi so snh s gip ta d dng la chn c Timer thch hp cho ng dng. ng, cnh tc ng) trong khi cc thng s ca xung tc ng ln Timer1 l c

2.7 ADC

ADC (Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t v s. PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hiu in th chun VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn RA2 v RA3. Kt qu chuyn i t tn tiu tng t sang tn hiu s l 10 bit s tng ng v c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dng b chuyn i ADC, cc thanh ghi ny c th c s dng nh cc thanh ghi thng thng khc. Khi qu trnh chuyn i hon tt, kt qu s c lu vo hai thanh ghi ADRESH:ADRESL, bit v c ngt ADIF c set. Quy trnh chuyn i t tng t sang s bao gm cc bc sau: 1. Thit lp cc thng s cho b chuyn i ADC:
-

El

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cc

Chn ng vo analog, chn in p mu (da trn cc thng s ca

LP: IN T 1 K2 33

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(ADCON0<2>) c xa v 0

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LUN VN TT NGHIP thanh ghi ADCON1) 3. 4. 5. Chnh knh chuyn i AD (thanh ghi ADCON0). Chnh xung clock cho knh chuyn i AD (thanh ghi ADCON0). Cho php b chuyn i AD hot ng (thanh ghi ADCON0). Clear bit ADIF. Set bit ADIE. Set bit PEIE. Set bit GIE.

2. Thit lp cc c ngt cho b AD

i cho ti khi qu trnh ly mu hon tt. Bt u qu trnh chuyn i (set bit Kim tra bit Nu Kim tra c ngt. )

i cho ti khi qu trnh chuyn i hn tt bng cch:

-

=0, qu trnh chuyn i hon tt.

6. c kt qu chuyn i v xa c ngt, set bit

cc

tu .n

chuyn i).
7.

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Tip tc thc hin cc bc 1 v 2 cho qu trnh chuyn i tip theo.

et
(nu cn tip tc
LP: IN T 1 K2 34

LUN VN TT NGHIP

Hnh 2.9 S khi b chuyn i ADC. Cn ch l c hai cch lu kt qu chuyn i AD, vic la chn cch lu c iu khin bi bit ADFM v c minh ha c th trong hnh sau:

El

Cc thanh ghi lin quan n b chuyn i ADC bao gm: INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt (cc bit GIE,
LP: IN T 1 K2 35

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Hnh 2.10 Cc cch lu kt qu chuyn i AD.

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LUN VN TT NGHIP PEIE). -

PIR1 (a ch 0Ch): cha c ngt AD (bit ADIF). PIE1 (a ch 8Ch): cha bit iu khin AD (ADIE). ADRESH (a ch 1Eh) v ADRESL (a ch 9Eh): cc thanh ghi cha kt qu chuyn i AD. ADCON0 (a ch 1Fh) v ADCON1 (a ch 9Fh): xc lp cc thng s cho b chuyn i AD. PORTA (a ch 05h) v TRISA (a ch 85h): lin quan n cc ng vo analog PORTA. PORTE (a ch 09h) v TRISE (a ch 89h): lin quan n cc ng vo analog PORTE.

2.8 COMPARATOR

B so snh bao gm hai b so so snh tn hiu analog v c t PORTA. ghi iu khin b so snh l CMCON. Cc bit CM2:CM0 trong thanh ghi CMCON ng vai tr chn la cc ch hot ng cho b Comparator (hnh 2.10). C ch hot ng ca b Comparator nh sau:

El

Tn hiu analog chn VIN + s c s snh vi in p chun chn V IN- v tn hiu ng ra b so snh s thay i tng ng nh hnh v. Khi in p chn VIN+ ln hn in p chn VIN+ ng ra s mc 1 v ngc li.
SV: TRN XUN CHIN LP: IN T 1 K2 36

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Hnh 2.11 Nguyn l hot ng ca mt b so snh n gin.

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Ng vo b so snh l cc chn RA3:RA0, ng ra l hai chn RA4 v RA5. Thanh

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LUN VN TT NGHIP Da vo hnh v ta thy p ng ti ng ra khng phi l tc thi so vi thay i ti ng vo m cn c mt khong thi gian nht nh ng ra thay i trng thi (ti a l 10 us). Cn ch n khong thi gian p ng ny khi s dng b so snh. Cc tnh ca cc b so snh c th thay i da vo cc gi tr t vo cc bit C2INV v C1INV (CMCON<4:5>).

El

SV: TRN XUN CHIN

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Hnh 2.12 Cc ch hot ng ca b comparator.
LP: IN T 1 K2 37

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LUN VN TT NGHIP Cc bit C2OUT v C1OUT (CMCON<7:6>) ng vai tr ghi nhn s thay i tn hiu analog so vi in p t trc. Cc bit ny cn c x l thch hp bng chng trnh ghi nhn s thay i ca tn hiu ng vo. C ngt ca b so snh l bit CMIF (thanh ghi PIR1). C ngt ny phi c reset v 0. Bit iu khin b so snh l bit CMIE (Tranh ghi PIE). Cc thanh ghi lin quan n b so snh bao gm:
-

CMCON (a ch 9Ch) v CVRCON (a ch 9Dh): xc lp cc thng s cho b so snh. Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cc bit cho php cc ngt (GIE v PEIE). Thanh ghi PIR2 (a ch 0Dh): cha c ngt ca b so snh (CMIF). Thanh ghi PIE2 (a ch 8Dh): cha bit cho php b so snh (CNIE). Thanh ghi PORTA (a ch 05h) v TRISA (a ch 85h): cc thanh ghi iu khin PORTA.

B TO IN P SO SNH

B so snh ny ch hot ng khi b Comparator c nh dng hot ng ch 110.Khi cc pin RA0/AN0 v RA1/AN1 (khi CIS = 0) hoc pin RA3/AN3 v RA2/AN2 (khi CIS = 1) s l ng vo analog ca in p cn so snh a vo ng VIN- ca 2 b so snh C1 v C2 (xem chi tit hnh 2.10). Trong khi in p a vo ng VIN+ s c ly t mt b to in p so snh. S khi ca b to in p so snh c trnh by trong hnh v sau:

El

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LUN VN TT NGHIP

Hnh 2.13 S khi b to in p so snh.

B to in p so snh ny bao gm mt thang in tr 16 mc ng vai tr l cu phn p chia nh in p VDD thnh nhiu mc khc nhau (16 mc). Mi mc Nu CVRR mc logic 1, in tr 8R s khng c tc dng nh mt thnh phn ca cu phn p (BJT dn mnh v dng in khong i qua ien tr 8R), khi o 1 mc ien ap co gia tr VDD/24. Ngc lai khi CVRR mc logic 0, dong ien se qua ien tr 8R va1 mc ien ap co gia tr VDD/32. Cac mc ien ap nay c a qua bo MUX cho phep ta chon c ien ap a ra pin

El

RA2/AN2/VREF-/CVREF e a vao ngo VIN+ cua bo so sanh bang cach a cac gia tr thch hp vao cac bit CVR3:CVR0. Bo tao ien ap so sanh nay co the xem nh mot bo chuyen oi D/A n gian. Gia tr ien ap can so sanh ngo vao Analog se c so sanh vi cac mc ien ap do bo tao ien ap tao ra cho ti khi hai ien ap nay at c gia tr xap x bang nhau. Khi o ket qua chuyen oi xem nh c cha trong cac bit CVR3:CVR0.
SV: TRN XUN CHIN LP: IN T 1 K2 39

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c gi tr in p khc nhau ty thuc vo bit iu khin CVRR (CVRCON<5>).

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LUN VN TT NGHIP Cc thanh ghi lin quan n b to in p so snh ny bao gm:

-

Thanh ghi CVRCON (a ch 9Dh): thanh ghi trc tip iu khin b so snh in p. Thanh ghi CMCON (a ch 9Ch): thanh ghi iu khin b Comparator.

2.9

CCP (CAPTURE/COMPARE/PWM)
CCP (Capture/Compare/PWM) bao gm cc thao tc trn cc xung m cung

cp bi cc b m Timer1 v Timer2. PIC16F877A c tch hp sn hai khi CCP : CCP1 v CCP2.Mi CCP c mt thanh ghi 16 bit (CCPR1H:CCPR1L v CCPR2H:CCPR2L), pin iu khin dung cho khi CCPx l RC2/CCP1 v RC1/T1OSI/CCP2. Cc chc nng ca CCP bao gm: Capture. So snh (Compare).

iu ch rng xung PWM (Pulse Width Modulation).

tng khi l kh c lp. Tuy nhin trong mt s trng hp ngoi l CCP1 v CCP2 c kh nng phi hp vi nhau to ra cc hin tng c bit (Special event trigger) hoc cc tc ng ln Timer1 v Timer2. Cc trng hp ny c lit k trong bng sau:

El

Khi hot ng ch Capture th khi c mt hin tng xy ra ti pin RC2/CCP1 (hoc RC1/T1OSI/CCP2), gi tr ca thanh ghi TMR1 s c a vo thanh ghi CCPR1 (CCPR2). Cc hin tng c nh ngha bi cc bit CCPxM3:CCPxM0

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C CCP1 v CCP2 v nguyn tc hot ng u ging nhau v chc nng ca

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LUN VN TT NGHIP (CCPxCON<3:0>) v c th l mt

mode). Hnh 2.14 S khi CCP (Capture

trong cc hin tng sau: - Mi khi c cnh xung ti cc pin CCP. Mi khi c cnh ln. Mi cnh ln th 4. Mi cnh ln th 16.

Sau khi gi tr ca thanh ghi TMR1 c a vo thanh ghi CCPRx, c ngt ra m gi tr trong thanh ghi CCPRx cha c x l, gi tr tip theo nhn c s Mt s im cn ch khi s dng CCP nh sau: -

Cc pin dng cho khi CCP phi c n nh l input (set cc bit tng ng trong thanh ghi TRISC). Khi n nh cc pin dng cho khi CCP l output, vic a gi tr vo PORTC cng c th gy ra cc hin tng tc ng ln khi CCP do trng thi ca pin thay i.

El

CCPRx se thng xuyen c so sanh vi gia tr trong thanh ghi TMR1. Khi hai thanh ghi cha gia tr bang nhau, cac pin cua CCP c thay oi trang thai (c a len mc cao, a xuong mc thap hoac gi nguyen trang thai), ong thi c ngat CCPIF cung se c set. S thay
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-

Timer1 phi c hot ng ch Timer hoc ch m ng b. Trnh s dng ngt CCP bng cch clear bit CCPxIE (thanh ghi PIE1), c ngt CCPIF nn c xa bng phn mm mi khi c set tip tc nhn nh c trng thi hot ng ca CCP. CCP cn c tch hp b chia tn s prescaler c iu khin bi cc bit CCPxM3:CCPxM0. Vic thay i i tng tc ng ca prescaler c th to ra hot ng ngt. Prescaler c xa khi CCP khng hot ng hoc khi reset.

Khi hoat ong che o Compare, gia tr trong thanh ghi

cc

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t ng c ghi ln gi tr c.

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CCPIF c set v phi c xa bng chng trnh. Nu hin tng tip theo xy

LUN VN TT NGHIP oi trang thai cua pin co the c ieu khien bi cac bit CCPxM3:CCPxM0 (CCPxCON <3:0>).

Hnh 2.15 S khi CCP (Compare mode). timer

tng c bit (Special Event trigger) lm reset gi tr thanh ghi TMR1 v khi ng b chuyn i ADC. iu ny cho php ta iu khin gi tr thanh ghi TMR1 mt cch linh ng hn. Khi hot ng ch PWM (Pulse Width Modulation _ khi iu ch rng xung), tn hiu sau khi iu ch s c

El

a ra cc pin ca khi CCP (cn n nh cc pin ny l output). s dng chc nng iu ch ny trc tin ta cn tin hnh cc bc ci t sau: 1. Thit lp thi gian ca 1 chu k ca xung iu ch cho PWM (period) bng cch a gi tr thch hp vo thanh ghi PR2. 2. Thit lp rng xung cn iu
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hoc m ng b. Ngoi ra, khi ch Compare, CCP c kh nng to ra hin

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Tng t nh ch Capture, Timer1 phi c n nh ch hot ng l

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LUN VN TT NGHIP ch (duty cycle) bng cch a mode). gi tr vo thanh ghi CCPRxL v cc bit CCP1CON<5:4>. 3. iu khin cc pin ca CCP l output bng cch clear cc bit tng ng trong thanh ghi TRISC. 4. Thit lp gi tr b chia tn s prescaler ca Timer2 v cho php Timer2 hot ng bng cch a gi tr thch hp vo thanh ghi T2CON. 5. Cho php CCP hot ng ch PWM. Hnh 2.16 S khi CCP (PWM

Trong gi tr 1 chu k (period) ca xung iu ch c tnh bng cng thc:

B chia tn s prescaler ca Timer2 ch c th nhn cc gi tr 1,4 hoc 16 (xem li Timer2 bit thm chi tit). Khi gi tr thanh ghi PR2 bng vi gi tr thanh ghi TMR2 th qu trnh sau xy ra: Thanh ghi TMR2 t ng c xa. Pin ca khi CCP c set. cycle) c a vo thanh ghi CCPRxH. Gi tr thanh ghi CCPR1L (cha gi tr n nh rng xung iu ch duty

El

rng ca xung iu ch (duty cycle) c tnh theo cng thc:

Nh vy 2 bit CCPxCON<5:4> s cha 2 bit LSB. Thanh ghi CCPRxL cha byte cao ca gi tr quyt nh rng xung. Thanh ghi CCPRxH ng vai tr l buffer cho khi PWM. Khi gi tr trong thanh ghi CCPRxH bng vi gi tr trong thanh ghi TMR2 v hai bit CCPxCON<5:4> bng vi gi tr 2 bit ca b chia tn s
SV: TRN XUN CHIN LP: IN T 1 K2 43

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Hnh 2.17 Cc tham s ca PWM

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LUN VN TT NGHIP prescaler, pin ca khi CCP li c a v mc thp, nh vy ta c c hnh nh ca xung iu ch ti ng ra ca khi PWM nh hnh 2.15. Mt s im cn ch khi s dng khi PWM: Timer2 c hai b chia tn s prescaler v postscaler. Tuy nhin b postscaler khng c s dng trong qu trnh iu ch rng xung ca khi PWM. Nu thi gian duty cycle di hn thi gian chu k xung period th xung ng ra tip tc c gi mc cao sau khi gi tr PR2 bng vi gi tr TMR2.

2.10 GIAO TIP NI TIP

1.10.1 USART trong USART (Universal Synchronous Asynchronous Receiver Transmitter) l mt hai chun giao tip ni tip.USART cn c gi l giao din giao tip ni tip ni tip SCI (Serial Communication Interface). C th s dng giao din ny cho cc dng ca giao din USART ngai vi bao gm: Bt ng b (Asynchronous). ng b_ Master mode. ng b_ Slave mode. giao tip vi cc thit b ngai vi, vi cc vi iu khin khc hay vi my tnh. Cc

Hai pin

RC6/TX/CK dng truyn xung clock (baud rate) v RC7/RX/DT dng truyn data. Trong trng hp ny ta phi set bit TRISC<7:6> v SPEN (RCSTA<7>) cho php giao din USART. PIC16F877A c tch hp sn b to tc baud BRG (Baud Rate Genetator)

El

8 bit dng cho giao din USART. BRG thc cht l mt b m c th c s dng cho c hai dng ng b v bt ng b v c iu khin bi thanh ghi PSBRG. dng bt ng b, BRG cn c iu khin bi bit BRGH ( TXSTA<2>). dng ng b tc ng ca bit BRGH c b qua. Tc baud do BRG to ra c tnh theo cng thc sau:

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dng cho giao din ny l RC6/TX/CK v RC7/RX/DT, trong

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LUN VN TT NGHIP Trong X l gi tr ca thanh ghi RSBRG ( X l s nguyn v 0<X<255). Cc thanh ghi lin quan n BRG bao gm:
-

TXSTA (a ch 98h): chn ch ng b hay bt ng b ( bit SYNC) v chn mc tc baud (bit BRGH). RCSTA (a ch 18h): cho php hot ng cng ni tip (bit SPEN). RSBRG (a ch 99h): quyt nh tc baud.

2.10.2 MSSP MSSP ( Master Synchronous Serial Port) l giao din ng b ni tip dng giao tip vi cc thit b ngoi vi (EEPROM, ghi dch, chuyn i ADC,) hay cc vi iu khin khc. MSSP c th hot ng di hai dng giao tip: SPI (Serial Pheripheral Interface). I2C (Inter-Intergrated Circuit).

Cc thanh ghi iu khin giao chun thi SSPSTAT v hai thanh ghi iu

Giao tip ny bao gm thanh ghi trng

khin SSPSON v SSPSON2. Ty theo

chun giao tip c s dng (SPI hay I2C) m chc nng cc thanh ghi ny c th hin khc nhau.
SPI)

ec tro ni

El

2.11

CNG GIAO TIP SONG SONG PSP (PARALLEL SLAVE

PORT)
iu

Ngoi cc cng ni tip v cc giao in ni tip c trnh by phn trn, vi khin PIC16F877A cn c h tr mt cng giao tip song song v chun giao tip song song thng qua PORTD v PORTE. Do cng song song ch hot ng ch Slave mode nn vi iu khin khi giao tip qua giao din ny s chu s iu khin ca thit b bn ngoi thng qua cc pin ca PORTE, trong khi d liu s c c hoc ghi theo dng bt ng b thng qua 8 pin ca PORTD.
SV: TRN XUN CHIN LP: IN T 1 K2 45

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Hnh 2.19 S khi MSSP (giao din

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LUN VN TT NGHIP Bit iu khin PSP l PSPMODE (TRISE<4>). PSPMODE c set s thit lp chc nng cc pin ca PORTE l cc pin cho php c d liu cho phep ghi d liu v pin chn vi iu khin ,

phc v cho vic truyn nhn d liu song song thng qua bus d liu 8 bit ca PORTD. PORTD lc ny ng vai tr l thanh ghi cht d liu 8 bit, ng thi tc ng ca thanh ghi TRISD cng s c b qua do PORTD lc ny chu s iu khin ca cc thit b bn ngoi. PORTE vn chu s tc ng ca thanh ghi TRISE, TRISE<2:0>. Ngoi ra cn a gi tr thch hp cc bit PCFG3:PCFG0 (thanh ghi cn l cc pin chc nng ca khi ADC). do cn xc lp trng thi cc pin PORTE l input bng cc set cc bit ADCON1<3:0>) n nh cc pin ca PORTE l cc pin I/O dng digital (PORTE

2.12 TNG QUAN V MT S C TNH CA CPU

PIC16F877A c kh nng s dng mt trong 4 loi oscillator, l:

i vi cc loi oscillator LP, HS, XT, oscillator c gn vo vi iu khin thng qua cc pin OSC1/CLKI v OSC2/CLKO.

El

i vi cc ng dng khng cn cc loi oscillator tc cao, ta c th s dng mch dao ng RC lm ngun cung cp xung hot ng cho vi vi iu khin. Tn s to ra ph thuc vo cc gi tr in p, gi tr in tr v t in, bn cnh l s nh hng ca cc yu t nh nhit , cht lng ca cc linh kin. Cc linh kin s dng cho mch RC oscillator phi bo m cc gi tr sau: 3 K < REXT < 100 K CEXT >20 pF
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XT: Thch anh bnh thng. HS: (High-Speed Crystal).

LP: (Low Power Crystal).

RC: (Resistor/Capacitor) dao ng do mch RC to ra.

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2.12.1 B DAO NG (OSCILLATOR)

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Hnh 2.39 RC oscillator.

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LUN VN TT NGHIP 2.12.2 CC CH RESET C nhiu ch reset vi iu khin, bao gm: -

Power-on Reset POR (Reset khi cp ngun hot ng cho vi iu khin). reset trong qu trnh hot ng. reset t ch sleep. WDT reset (reset do khi WDT to ra trong qu trnh hot ng). WDT wake up t ch sleep. Brown-out reset (BOR).

Ngoi tr reset POR trng thi cc thanh ghi l khng xc nh vWDT wake up khng nh hng n trng thi cc thanh ghi, cc ch reset cn li u a gi tr cc thanh ghi v gi tr ban u c n nh sn. Cc bit reset: Khi pin mc logic thp,

tu .n

thi hot ng, trng thi reset ca vi iu khin v c iu khin bi CPU. vi iu khin s c reset. Tn hiu reset c cung cp bi mt mch ngoi vi vi
-

Khng ni pin ngun VDD.

R1 phi nh hn 40 K m bo

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trc tip ln cc c tnh in ca vi iu khin. vo vi iu khin. cc tn hiu nh tc ng ln pin

cc yu cu c th sau:

R2 phi ln hn 1 K hn dng i pin

El

reset cn c chng nhiu bi mt b lc trnh

Power-on reset (POR): y l xung reset do vi iu khin to ra khi pht hin ngun cung cp VDD. Khi hot ng ch bnh thng, vi iu khin cn c m bo cc thng s v dng in, in p hot ng bnh thng. Nhng nu cc tham s ny khng c m bo, xung reset do POR to ra s a vi iu khin v trng thi reset v ch tip tc hot ng khi no cc tham s trn c m bo. Power-up Timer (PWRT): y l b nh thi hot ng da vo mch RC bn
SV: TRN XUN CHIN LP: IN T 1 K2 47

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Hnh 2.40 Mach reset qua

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v

ch th trng

LUN VN TT NGHIP trong vi iu khin. Khi PWRT c kch hot, vi iu khin s c a v trng thi reset. PWRT s to ra mt khong thi gian delay (khong 72 ms) VDD tng n gi tr thch hp. Oscillator Start-up Timer (OST): OST cung cp mt khong thi gian delay bng 1024 chu k xung ca oscillator sau khi PWRT ngng tc ng (vi iu khin iu kin hot ng) m bo s n nh ca xung do oscillator pht ra. Tc ng ca OST cn xy ra i vi POR reset v khi vi iu khin c nh thc t ch sleep. OST ch tc ng i vi cc lai oscillator l XT, HS v LP. Brown-out reset (BOR): Nu VDD h xung thp hn gi tr VBOR (khong 4V) v ko di trong khong thi gian ln hn TBOR (khong 100 us), BOR c kch hot v vi iu khin c a v trng thi BOR reset. Nu in p cung cp cho vi iu khin h xung thp hn VBOR trong khong thi gian ngn hn TBOR, vi iu khin s khng c reset. Khi in p cung cp cho vi iu khin hot ng, PWRT c kch hot to ra mt khong thi gian delay (khong 72ms). Nu trong khong thi gian ny in p cung cp cho vi ieu khien lai tiep tuc ha xuong di mc ien ap VBOR, BOR reset se lai c kch hoat khi vi ieu khien u ien ap hoat ong. Mot iem can chu y la khi BOR reset c cho phep, PWRT cung se hoat ong bat chap trang thai cua bit PWRT. Tm li vi iu khin hot ng c t khi cp ngun cn tri qua cc bc sau: -

POR tc ng.

El

PWRT (nu c cho php hot ng) to ra khong thi gian delay TPWRT n nh ngun cung cp. OST (nu c cho php) to ra khong thi gian delay bng 1024 chu k xung ca oscillator n nh tn s ca oscillator. n thi im ny vi iu khin mi bt u hot ng bnh thng. Thanh ghi iu khin v ch th trng thi ngun cung cp cho vi iu khin l thanh ghi PCON.

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LUN VN TT NGHIP

2.12.3 NGT (INTERRUPT) ghi

INTCON (bit GIE). Bn cnh mi ngt cn c mt bit iu khin v c ngt ring. Cc c ngt vn c set bnh thng khi tha mn iu kin ngt xy ra bt chp trng thi ca bit GIE, tuy nhin hot ng ngt vn ph thuc vo bit GIE v cc bit iu khin khc. Bit iu khin ngt RB0/INT v TMR0 nm trong thanh ghi INTCON, thanh ghi ny cn cha bit cho php cc ngt ngoi vi PEIE. Bit iu

El

khin cc ngt nm trong thanh ghi PIE1 v PIE2. C ngt ca cc ngt nm trong thanh ghi PIR1 v PIR2. Trong mt thi im ch c mt chng trnh ngt c thc thi, chng trnh ngt c kt thc bng lnh RETFIE. Khi chng trnh ngt c thc thi, bit GIE t ng c xa, a ch lnh tip theo ca chng trnh chnh c ct vo trong b nh Stack v b m chng trnh s ch n a ch 0004h. Lnh RETFIE c dng thot khi chng trnh ngt v quay tr v chng trnh chnh, ng thi bit GIE cng s c set cho php cc ngt hot ng tr li. Cc c hiu c
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PIC16F877A c n 15 ngun to ra hot ng ngt c iu khin bi thanh

cc

Hnh 2.41 S cc ch reset ca PIC16F877A.

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LUN VN TT NGHIP dng kim tra ngt no ang xy ra v phi c xa bng chng trnh trc khi cho php ngt tip tc hot ng tr li ta c th pht hin c thi im tip theo m ngt xy ra. i vi cc ngt ngoi vi nh ngt t chn INT hay ngt t s thay i trng thi cc pin ca PORTB (PORTB Interrupt on change), vic xc nh ngt no xy ra cn 3 hoc 4 chu k lnh ty thuc vo thi im xy ra ngt. Cn ch l trong qu trnh thc thi ngt, ch c gi tr ca b m chng trnh c ct vo trong Stack, trong khi mt s thanh ghi quan trng s khng c ct v c th b thay i gi tr trong qu trnh thc thi chng trnh ngt. iu ny nn c x l bng chng trnh trnh hin tng trn xy ra.

El

NGT INT Ngt ny da trn s thay i trng thi ca pin RB0/INT. Cnh tc ng gy ra ngt c th l cnh ln hay cnh xung v c iu khin bi bit INTEDG (thanh ghi OPTION_REG <6>). Khi c cnh tc ng thch hp xut hin ti pin RB0/INT, c ngt INTF c set bt chp trng thi cc bit iu khin GIE v PEIE. Ngt ny c kh nng nh thc vi iu khin t ch sleep nu bit cho
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Hnh 2.42 S logic ca tt c cc ngt trong vi iu khin PIC16F877A.

cc

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LUN VN TT NGHIP php ngt c set trc khi lnh SLEEP c thc thi. NGT DO S THAY I TRNG THI CC PIN TRONG PORTB Cc pin PORTB<7:4> c dng cho ngt ny v c iu khin bi bit RBIE (thanh ghi INTCON<4>). C ngt ca ngt ny l bit RBIF (INTCON<0>).
2.12.4

WATCHDOG TIMER (WDT)

Watchdog timer (WDT) l b m c lp dng ngun xung m t b to xung c tch hp sn trong vi iu khin v khng ph thuc vo bt k ngun xung clock ngoi vi no. iu c ngha l WDT vn hot ng ngay c khi xung clock c ly t pin OSC1/CLKI v pin OSC2/CLKO ca vi iu khin ngng hot ng (chng hn nh do tc ng ca lnh sleep). Bit iu khin ca WDT l bit WDTE nm trong b nh chng trnh a ch 2007h (Configuration bit). WDT s t ng reset vi iu khin (Watchdog Timer Reset) khi b m ca

xa. Nu vi iu khin ang ch sleep th WDT s nh thc vi iu khin iu khin thi im cn thit m khng cn n s tc ng t bn ngoi, chng hn nh trong qu trnh thc thi lnh, vi iu khin b kt mt ch no m khng thot ra c, khi vi iu khin s t ng c reset khi WDT b trn chng trnh hot ng ng tr li. Tuy nhin khi s dng WDT cng c s phin toi v vi iu khin s thng xuyn c reset sau mt thi gian nht nh, do i cn tnh ton thi gian thch hp xa WDT (dng lnh CLRWDT). V vic n nh thi gian reset c linh ng, WDT cn c h tr mt b chia tn s prescaler c iu khin bi thanh ghi OPTION_REG (prescaler ny c chia x vi Timer0). ra lnh xa CLRWDT ch xa b m ch khng lm thay i i tng tc ng ca prescaler (WDT hay Timer0). 2.12.5 CH SLEEP y l ch hot ng ca vi iu khin khi lnh SLEEP c thc thi. Khi
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(Watchdog Timer Wake-up) khi b m b trn. Nh vy WDT c tc dng reset vi

Mt im cn ch na l lnh sleep s xa b m WDT v prescaler. Ngoi

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WDT b trn (nu WDT c cho php hot ng), ng thi bit

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LUN VN TT NGHIP nu c cho php hot ng, b m ca WDT s b xa nhng WDT vn tip tc hot ng, bit thc thi. Do khi ch SLEEP, dng cung cp cho vi iu khin l rt nh nn ta cn thc hin cc bc sau trc khi vi iu khin thc thi lnh SLEEP: -

(STATUS<3>) c reset v 0, bit

c set, oscillator

ngng tc ng v cc PORT gi nguyn trng thi nh trc khi lnh SLEEP c

a tt c cc pin v trng thi VDD hoc VSS Cn bo m rng khng c mch ngoi vi no c iu khin bi dng in ca vi iu khin v dng in nh khng kh nng cung cp cho cc mch ngoi vi hot ng.

Tm ngng hot ng ca khi A/D v khng cho php cc xung clock t bn ngoi tc ng vo vi iu khin. n chc nng ko ln in tr PORTB.
NH THC VI IU KHIN

Vi iu khin c th c nh thc di tc ng ca mt trong s cc hin tng sau: -

Cc bit

El

hin ngun tc ng lm reset vi iu khin. Bit c set khi vi iu khin c cp ngun v c reset v 0 khi vi iu khin ch sleep. Bit 0 khi WDT tc ng do b m b trn. Ngoi ra cn c mt s ngun tc ng khc t cc chc nng ngoi vi bao gm: 1) c hay ghi d liu thng qua PSP (Parallel Slave Port). 2) Ngt Timer1 khi hot ng ch m bt ng b. 3) Ngt CCP khi hot ng ch Capture. 4) Cc hin tng c bit lm reset Timer1 khi hot ng ch m bt ng
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Tc ng ca WDT khi b trn. hoc pin INT). v

Tc ng ca reset ngoi vi thng qua pin Tc ng t cc ngt ngoi vi t PORTB (PORTB Interrupt on change

c dng th hin trng thi ca vi iu khin v pht c reset v

cc

Pin

phi mc logic cao.

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LUN VN TT NGHIP 5) b dng ngun xung clock bn ngoi). 6) Ngt SSP khi bit Start/Stop c pht hin. 7) SSP hot ng ch Slave mode khi truyn hoc nhn d liu.
8) Tc ng ca USART t cc pin RX hay TX khi hot ng ch Slave

mode ng b. 9) Khi chuyn i A/D khi ngun xung clock hot ng dng RC. 10)Hon tt qu trnh ghi vo EEPROM. 11)Ng ra b so snh thay i trng thi. Cc tc ng ngoi vi khc khng c tc dng nh thc vi iu khin v khi ch sleep cc xung clock cung cp cho vi iu khin ngng hot ng. Bn cnh cn cho php cc ngt hot ng trc khi lnh SLEEP c thc thi bo m tc ng ca cc ngt. Vic nh thc vi iu khin t cc ngt vn c thc thi bt chp trng thi ca bit GIE. Nu bit GIE mang gi tr 0, vi iu khin s thc thi lnh tip theo sau lnh SLEEP ca chng trnh (v chng trnh ngt khng c cho php thc thi). Nu bit GIE c set trc khi lnh SLEEP c thc thi, vi iu khin s thc thi lnh tip theo ca chng trnh v sau nhy ti a ch cha chng trnh ngt (0004h). Trong trng hp lnh tip theo khng ng vai tr quan trng trong chng trnh, ta cn t thm lnh NOP sau lnh SLEEP b qua tc ng ca lnh ny, ng thi gip ta d dng hn trong vic kim sot hot ng ca chng trnh ngt. Tuy nhin cng c mt s im cn lu nh sau:
-

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kim tra xem lnh SLEEP c thc thi hay cha, ta kim tra bit Nu bit vn mang gi tr 1 tc l lnh SLEEP khng c thc thi v thay

vo l lnh NOP. Bn cnh ta cn xa WDT chc chn rng WDT c xa trc khi
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SLEEP cng s c b qua. sau khi vi iu khin c nh thc.

Nu ngt xy ra trc khi lnh SLEEP c thc thi, lnh SLEEP s khng c thc thi v thay vo l lnh NOP, ng thi cc tc ng ca lnh Nu ngt xy ra trong khi hay sau khi lnh SLEEP c thc thi, vi iu khin lp tc c nh thc t ch sleep, v lnh SLEEP s c thc thi ngay

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LUN VN TT NGHIP thc thi lnh SLEEP, qua cho php ta xc nh c thi im vi iu khin c nh thc do tc ng ca WDT.

2.13

TP LNH CA VI IU KHIN PIC

2.13.1 Lnh ADDLW C php: ADDLW k (0 k255) Tc dng: cng gi tr k vo thanh ghi W, kt qu c cha trong thanh ghi W. Bit trng thi: C, DC, Z 2.13.2 Lnh ADDWF C php: ADDWF f,d (0f255, d nu d=1. Bit trng thi: C, DC, Z 2.13.3 Lnh ANDLW

[0,1]). Tc dng: cng gi tr hai thanh ghi

W v thanh ghi f. Kt qu c cha trong thanh ghi W nu d = 0 hoc thanh ghi f

C php: ANDLW k (0k255) Tc dng: thc hin php ton AND gia thanh ghi v gi tr k, kt qu c cha trong thanh ghi W. Bit trng thi: Z 2.13.4 Lnh ANDWF

C php: ANDWF f,d (0f127, d [0,1]). Tc dng: thc hin php ton AND gia cc gi tr cha trong hai thanh ghi W v f. Kt qu c a vo thanh ghi W nu d=0 hoc thanh ghi f nu d = 1. Bit trng thi: Z 2.13.5 Lnh BCF C php: BCF f,b (0f127, 0b7). Tc dng: xa bit b trong thanh ghi f v gi tr 0. Bit trng thi: khng c. 2.13.6 Lnh BSF C php: BSF f,b (0f127, 0b7). Tc dng: set bit b trong trnh ghi f. Bit trng thi: khng c 2.13.7 Lnh BTFSS C php: BTFSS f,b (0f127, 0b7).Tc dng: kim tra bit b trong thanh ghi
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LUN VN TT NGHIP f. Nu bit b bng 0, lnh tip theo c thc thi. Nu bit b bng 1, lnh tip theo c b qua v thay vo l lnh NOP. Bit trng thi: khng c 2.13.8 Lnh BTFSC C php: BTFSC f,b(0f127, 0b7). Tc dng: kim tra bit b trong thanh ghi f. Nu bit b bng 1, lnh tip theo c thc thi. Nu bit b bng 0, lnh tip theo c b qua v thay vo l lnh NOP. Bit trng thi: khng c. 2.13.9 Lnh CALL

C php: CALL k (0k2047). Tc dng: gi mt chng trnh con. Trc ht a ch quay tr v t chng trnh con (PC+1) c ct vo trong Stack, gi tr a ch mi c a vo b m gm 11 bit ca bin k v 2 bit PCLATH<4:3>. Bit trng thi: khng c 2.13.10 Lnh CLRF Bit trng thi: Z

C php CLRF f (0f127) Tc dng: xa thanh ghi f v bit Z c set. 2.13.11 Lnh CLRW Bit trng thi: Z

C php CLRW Tc dng: xa thanh ghi W v bit Z c set. 2.13.12 Lnh CLRWDT

C php: CLRWDT Tc dng: reset Watchdog Timer, ng thi prescaler cng

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c reset, cc bit Bit trng thi:

2.13.13 Lnh COMF C php: COMF f,d (0f127, d Bit trng thi: Z 2.13.14 Lnh DECF C php: DECF f,d (0f127, d [0,1]). Tc dng: gi tr thanh ghi f c gim i 1 n v. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d =
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Kt qu c a vo thanh ghi W nu d=0 hoc thanh ghi f nu d=1.

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v

c set ln 1.

cc

[0,1]). Tc dng: o cc bit trong thanh ghi f.

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LUN VN TT NGHIP 1. Bit trng thi: Z 2.13.15 Lnh DECFSZ C php: DECFSZ f,d(0f127, d 1 n v. Nu kt qu sau khi gim khc 0, lnh tip theo c thc thi, nu kt qu bng 0, lnh tip theo khng c thc thi v thay vo l lnh NOP. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: khng c 2.13.16 Lnh GOTO [0,1]).Tc dng: ga tr thanh ghi f c gim

C php: GOTO k (0k2047). Tc dng: nhy ti mt label c nh ngha bi tham s k v 2 bit PCLATH<4:3>. Bit trng thi: khng c. 2.13.17 Lnh INCF n

C php: INCF f,d (0f127, d

v. Kt qu c a vo thanh ghi W nu d = 0 hoc thanh ghi f nu d = 1. Bit trng thi: Z 2.13.18 Lnh INCFSZ

C php: INCFSZ f,d (0f127, d

1 n v. Nu kt qu khc 0, lnh tip theo c thc thi, nu kt qu bng 0, lnh

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tip theo c thay bng lnh NOP. Kt qu s c a vo thanh ghi f nu d=1 hoc thanh ghi W nu d = 0. Bit trng thi: khng c. 2.13.19 Lnh IORLW C php: IORLW k (0k255) Tc dng: thc hin php ton OR gia thanh ghi W v gi tr k. Kt qu c cha trong thanh ghi W. Bit trng thi: Z 2.13.20 Lnh IORWF C php: IORWF f,d (0f127, d gia
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cc

[0,1]). Tc dng: tng gi tr thanh ghi f ln 1

[0,1]). Tc dng: tng gi tr thanh ghi f ln

[0,1]). Tc dng: thc hin php ton OR

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LUN VN TT NGHIP hai thanh ghi W v f. Kt qu c a vo thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: Z 2.13.21 Lnh RLF C php: RLF f,d (0f127, d f qua c carry. Kt qu c lu trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. [0,1]). Tc dng: dch tri cc bit trong thanh ghi

2.13.22 Lnh RETURN C php: RETURN. Bit trng thi:khng c 2.13.23 Lnh RRF ghi

Tc dng: quay tr v chng trnh chnh t mt chng trnh con

C php: RRF f,d (0f127, d

f qua c carry. Kt qu c lu trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1.

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Bit trng thi: C

2.13.24 Lnh SLEEP C php: SLEEP Tc dng: a vi iu khin v ch sleep. Khi WDT b xa v 0, bit xa v 0, bit Bit trng thi: 2.13.25 Lnh SUBLW C php: SUBLW k Tc dng: ly gi tr k tr gi tr trong thanh ghi W. Kt qu c cha trong thanh
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cc
[0,1]). Tc dng: dch phi cc bit trong thanh c

c set ln 1 v oscillator khng c cho php hot ng.

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LUN VN TT NGHIP ghi W. Bit trng thi: C, DC, Z 2.13.26 Lnh SUBWF C php: SUBWF f,d (0f127, d [0,1]) Tc dng: ly gi tr trong thanh ghi f em tr cho thanh ghi W. Kt qu c lu trong thanh ghiaW nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: C, DC, Z 2.13.27 Lnh SWAP C php: SWAP f,d (0f127, d [0,1]) Tc dng: o 4 bit thp vi 4 bit cao trong thanh ghi f. Kt qu c cha trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: khng c 2.13.28 Lnh XORLW C php: XORLW k (0k255) qu c lu trong thanh ghi W. Bit trng thi: Z 2.13.29 Lnh XORWF C php: XORWF f,d thanh

Tc dng: thc hin php ton XOR gia gi tr k v gi tr trong thanh ghi W. Kt

Tc dng: thc hin php ton XOR gia hai gi tr cha trong thanh ghi W v ghi f. Kt qu c lu vo trong thanh ghi W nu d=0 hoc thanh ghi f nu d=1. Bit trng thi: Z

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2.13.30 Lnh #DIFINE C php: #DEFINE <text1> <text2> Tc dng: thay th mt chui k t ny bng mt chui k t khc, c ngha l mi khi chui k t text1 xut hin trong chng trnh, trnh bin dch s t ng thay th chui k t bng chui k t <text2>. 2.13.31 Lnh INCLUDE C php: #INCLUDE <filename> hoc #INCLUDE filename Tc dng: nh km mt file khc vo chng trnh, tng t nh vic ta copy file
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Ngoi cc lnh trn cn c mt s lnh dng trong chng trnh nh:

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LUN VN TT NGHIP vo v tr xut hin lnh INCLUDE. Nu dng c php <filename> th file nh km l file h thng (system file), nu dng c php filename th file nh km l file ca ngi s dng. Thng thng chng trnh c nh km theo mt header file cha cc thng tin nh ngha cc bin (thanh ghi W, thanh ghi F,..) v cc a ch cc thanh ghi chc nng c bit trong b nh d liu. Nu khng c header file, chng trnh s khs c v kh hiu hn. 2.13.32 Lnh CONSTANT C php: CONSTANT <name>=<value> Tc dng: khai bo mt hng s, c ngha l khi pht hin chui k t name trong chng trnh, trnh bin dch s t ng thay bng chui k t bng gi tr value c nh ngha trc . 2.13.33 Lnh VARIABLE C php: VARIABLE <name>=<value>

Tc dng: tng t nh lnh CONSTANT, ch c im khc bit duy nht l gi tr value khi dng lnh VARIABLE c th thay i c trong qu trnh thc thi chng trnh cn lnh CONSTANT th khng. 2.13.34 Lnh SET C php: <name variable> SET <value> trnh thc thi chng trnh. 2.13.35 Lnh EQU

Tc dng: gn gi tr cho mt tn bin. Tn ca bin c th thay i c trong qu

C php: <name constant> EQU <value>

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Tc dng: gn gi tr cho tn ca tn ca hng s. Tn ca hng s khng thay i trong qu trnh thc thi chng trnh. 2.13.36 Lnh ORG C php: ORG <value> Tc dng: nh ngha mt a ch cha chng trnh trong b nh chng trnh ca vi iu khin. 2.13.37 Lnh END C php: END Tc dng: nh du kt thc chng trnh.
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LUN VN TT NGHIP 2.13.38 Lnh __CONFIG C php: __CONFIG(Configuration bit) Tc dng: thit lp cc bit iu khin cc khi chc nng ca vi iu khin c cha trong b nh chng trnh (Configuration bit) 2.13.39 Lnh PROCESSOR C php: PROCESSOR <processor type> Tc dng: nh ngha vi iu khin no s dng chng trnh.

CHNG 3: NG DNG PIC 16F877A XY DNG B

3.1 GII THIU

ti: Thit k b KIT thc hnh PIC 16F877A bao gm cc phn chnh:
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Qut Led trn( LED MATRIX). Qut Led 7 thanh( 7SEG). Qut Led n( LED). LCD). -

KIT THC HNH VI IU KHIN

iu khin ng c mt chiu( PWM).

o nhit qua LM35 hin th LCD( LM35 & LCD). Bn phm tnh ton cng tr nhn chia hin th LCD( KEY BOARD & Giao tip vi cng ni tip USART(USART). Khi ngun 12V, 5V( POWER). Khi iu khin ngun( CONTROL POWER).

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LUN VN TT NGHIP
3.2 TRNH T THIT K

Tm hiu v vi iu khin PIC 16F877A. Tm hiu v IC LM35. Tm hiu v LCD, Led matrix, led 7 thanh, ng c 1 chiu V mch nguyn l bng phn mm Proteus. Vit code chng trnh bng phn mm CCS( lp trnh v bin dch chng trnh cho vi iu khin PIC) M phng v test chy th trn board. V mch in bng phn mm proteus. Hn linh kin v hon chnh mch.

3.3 MCH NGUYN L CA B KIT V NGUYN TC VN HNH

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3.3.1 Mch nguyn l
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LUN VN TT NGHIP

ng vi mi ng dng c th trong b kit th ta s np chng trnh cho PIC 16F877A v iu chnh khi control power cho ph hp vi ng dng .

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3.4 NGUYN L HOT NG CA TNG KHI.

3.4.1 Khi qut Led 7 thanh

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3.3.2 Nguyn tc vn hnh b kit

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LUN VN TT NGHIP

Nhim v:

Qut LED

Hin th thi gian thc

Hin th nhit cn o.

Hot ng: Hot ng hin th thi gian thc: Cpu x l tn hiu thi gian

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3.4.2 Khi qut LED ma trn.

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on.

thc sau s xut d liu qua IC7447(Gii m). Sau s hin th LED 7

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LUN VN TT NGHIP

Nhim v: Dng hin th ch chy v c th hin th hnh nh. Hot ng: Cpu xut d liu ng thi ra IC 595 (chuyn d liu t ni tip sang song song) v ng thi n s xut d liu ra IC 74ls138 (Dng qut m cc tn hiu).

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3.4.3 Khi o nhit hin th LCD

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LUN VN TT NGHIP

Nhim v : Dng o nhit v hin th ln mn hnh LCD. Hot ng : Cm bin (LM35) s xut d liu v VK (PIC), Vi iu khin s nhn tn hiu cm bin v xut ra LCD (Hin th).

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LUN VN TT NGHIP 3.4.4 Khi bn phm.

Nhim v : Tnh ton cc php tnh c bn v hin th ra LCD.

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Hot ng : Cpu nhn tin hiu vo t bn phm sau khi x l d liu (Cpu) s xut d liu ra mn hnh.

3.4.5 iu khin ng c (PWM)

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LUN VN TT NGHIP

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Nhim v : iu khin tc ng c mt chiu. Hot ng : Mch ng lc mc theo kiu mch cu H. D liu PWM c CPU truyn qua mch cu H iu khin ng c.

3.4.6 Hin th vo ra bng LED n.

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LUN VN TT NGHIP

Nhim v: Kim tra vo ra bng led n. Hot ng : Cpu s xut d liu vo ra kim tra.

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3.4.7 Khi truyn thng ni tip (USART).

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LUN VN TT NGHIP

Nhim v: Dng kt ni gia CPU v my tnh qua cng COM bng IC

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Hot ng : Cpu s xut v nhn d liu t cng ni tip thng qua b m Max232.

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( Max232).

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LUN VN TT NGHIP 3.4.8 Khi ngun.

Nhim v: Cung cp ngun cho ton b mch iu khin v mch lc.

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