Lab MSP430 2012

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Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012
Mc tiu:
Sau khi c xong ti liu ny, sinh vin c th: S dng KIT MSP-EXP430FG4618 thc hin cc bi lab c bn. S dng b Debug MSP-FET430UIF np chng trnh cho chip MSP430 trn KIT MSPS dng phn mm IAR lp trnh mt chng trnh n gin. Thc hin cc bi lin quan n xut/nhp, ngt, timer.
EXP430FG4618 .
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Kit MSP-EXP430FG4618
1.1. Gii thiu chung:

KIT MSP-EXP430FG4618 ca hng TI l bo mch tch hp 2 chip MSP430FG4618 v MSP430F2013 nn cung cp cc ngoi vi ph bin trong h MSP430. c bit, 2 chip 4618 v 2013 c th giao tip vi nhau (xem hnh 2) hoc giao tip vi cc thit b bn ngoi. C th s dng mt trong 2 gi cng c sau lp trnh v debug: IAR Embeeded Workbench, TI Code Composer Essential (CCE) v TI code Composer Studio (CCS). Thit b lp trnh v debug cho chip TI l TI USB Flash Emulation Tool (FET)
Hnh 1. KIT MSP-EXP430FG4618 do TI ti tr cho b mn K thut My tnh

Binson:PhmXunTrung,BmnKthutMy nh,KhoaintVinthng,TrngHBchkhoa,HNng
1.2. S khi phn b linh kin trn KIT MSP-EXP430FG4618
Hnh 2. S khi phn b linh kin trn KIT MSP-EXP430FG4618
1.2.1. JTAG
Hai header JTAG1 v JTAG2 lp trnh v debug mi MSP430 ring bit: JTAG1 cho MSP430FG4618 v JTAG2 cho MSP430F2013. JTAG1 cho MSP430FG4618 dng kiu kt ni JTAG chun 4 dy, cn JTAG cho MSP430F2013 dng kiu giao tip JTAG Spy-Bi-Wire (2 dy). iu ny cho php cc chn cc port c s dng trong qu trnh debug.
1.2.2. Microphone:
Microphone (MIC) c kt ni vi MSP430FG4618 qua cc chn trong hnh 3. Microphone c kch hot hay khng qua chn ca MSP430FG4618.
Hnh 3. S nguyn l Microphone trn KIT MSP430FG4618

1.2.3. Buzzer
Buzzer c kt ni vi port I/O P3.5 ca MSP430FG4618. Buzzer c th hon ton b cch ly vi jumper JP1. Lu : trong qu trnh th nghim, sau khi th nghim thnh cng, sinh vin nn tho JP1 ny trnh lm nh hng ngi xung quanh.
1.2.4. LCD
LCD trong kit ny l loi SoftBaugh SBLCDA4, n c 4 ch : tnh, 2-mux, 3-mux v 4-mux. LCD ny c h tr khi giao tip vi MSP430FG4618 qua LCD driver c sn.
1.2.5. Nt nhn S1 v S2:

Hai nt nhn S1 v S2 c ni vi cng xut/nhp s P1 c chc nng ngt ca MSP430FG4618.
Hnh 4. S nguyn l kt ni nt nhn S1 & S2 vi MSP430FG4618
1.2.6. Cc LED n
KIT MSP430FG4618 c 4 LED: LED1, LED2, v LED4 c kt ni vi chip MSP430FG4618, LED3 c kt ni vi chip MSP430F2013. LED3 v LED4 c th c ngt khi kt ni bng Jumper tit kim nng lng cho kit (LED3 dng jumper JP2, LED4 dng JP3). LED LED1 LED2 LED3 LED4

Kt ni vi chip MSP430FG4618 MSP430FG4618 MSP430F2013 MSP430FG4618
Port P2.2 P2.1 P1.0 P5.1
Ghi ch Jumper JP2 JP3
Bng 1: Kt ni LED
Hnh 5.S nguyn l kt ni LED1, LED2 & LED4 vi MSP430FG4618
Hnh 6. S nguyn l kt ni LED3 vi MSP430F2013
1.2.7. Giao tip RS232

Chip MSP430FG4618 h tr chun giao tip RS-232 9 chn thng qua ngoi vi USC ca chip (c cu hnh trong ch UART).
Hnh 7. S nguyn l giao tip cng RS232 vi MSP430FG4618
1.2.8. Jumper
Hnh 8.S b tr jumper trn KIT MSP430FG4618

Header JTAG1 JTAG2 PWR1 PWR2 BATT JP1 JP2 JP3 JP4 H1(1-2, 3-4) H1(1-2, 3-4, 56,7-8)
Chc nng khi dung Jumper kt ni B FET lp trnh-debug FG4618 B FET lp trnh-debug F2013
Khi khng dng jumper kt ni FG4618 khng c s dng F2013 khng c s dng
Yu cu X X Yu cu cn gn jumper ny s dng FG4618 Yu cu cn gn jumper ny s dng F2013 Yu cu khi cn dng pin Ty chn Ty chn/ yu cu khi dng LED3 Ty chn/ yu cu khi dng LED4 Yu cu cho giao tip bn trong processor Yu cu cho giao tip bn trong processor
Cung cp ngun cho FG4618. Ngoi ra, FG4618 khng c cung cp ngun dng o dng Cung cp ngun cho F2013. Ngoi ra, F2013 khng c cung cp ngun dng o dng Cung cp ngun cho kit bng 2 pin AAA. Ngoi ra, dung o dng tng cng ca kit s dng buzzer (ni vi chn FG4618-P3.5) Cho php LED3 hot ng (LED3 ni vi chn F2013-P1.0) Cho php LED4 hot ng (LED4 ni vi chn FG4618-P5.1) Cu hnh cho I2C 1-2: SDA-UCBOSDA 3-4: SCL-UCBOSCL Cu hnh cho SPI 1-2: SDI UCB0SIMO 3-4: SDO UCB0SOMI 5-6: P1.4 P3.0 (CS) 7-8: SCLK UCB0CLK VCC_1: 3 chn pha di. Dng cho FG4618/JTAG1. VCC_2: 3 chn pha trn. Dng cho F2013/JTAG2. LCL: cung cp Vcc n FET. FET: ngun t FET (jumper BATT khng c thit lp) Pin khng cung cp ngun cho c 2 chip MSP430 Khng dng buzzer Khng dng LED3 Khng dng LED4
Suy hao mc in p ra ca audio (69%) 98% suy hao ca ng ra audio DAC12 Ty chn Khng giao tip qua I2C Khng giao tip qua SPI
Vcc
Ngun t JTAG
Yu cu khi s dng khng cn pin
Bng 2.Lit k chc nng ca jumper trn KIT MSP430FG4618 khi c kt ni
1.3. S nguyn l ca KIT MSP-EXP430FG4618
Hnh 9.S nguyn l ton KIT MSP430FG4618

2.c tnh v cch ci t b Debug MSP-FET430UIF

2.1. Gii thiu cng c FET
FET (Flash Emulation Tool) cho php lp trnh - debug h vi x l MSP430 qua chun kt ni JTAG y (4 dy) v JTAG tit kim chn (2 dy, Spy Bi-Wire). Do , FET c dng pht trin cc ng dng trn h MCU ny qua 2 c ch giao tip ca FET l qua USB cng song song, tng ng vi cc loi MSP-FET430UIF (Hnh 10) v MSP- FET430PIF. Hin ti, Cng ty TI ch ti tr loi MSP FET430UIF cho b mn K thut My tnh nn tt c cc bi th nghim trn KIT MSP430FG4618 s s dng loi ny.
Hnh 10. B Debug MSP-FET430UIF

c tnh H tr tt c h MSP430 da trn Flash (F1xx, F2xx, F4xx, F5xx) Cho php cu hnh bo mt JTAG bo v code Cho php to ra ngun cp chnh c 1.8V-3.6V 100mA C nh to ra ngun cp 2.8V Debug dng JTAG chun 4 dy Debug dng JTAG chun 2 dy (Spy-Bi-Wire) H tr bi CCE H tr bi IAR MSP-FET430UIF x x x KHNG x x x x MSP-FET430PIF x KHNG KHNG x x KHNG x x
Bng 3. So snh mt vi tnh nng gia 2 loi MSP-FET430UIF v MSP- FET430PIF
2.2.Ci t driver ca b Debug MSP-FET430UIF ln PC

Hin ti, phng th nghim M phng v Vi x l c trang b PC ci t windows 7 nn vic thit lp driver cho b Debug MSP-FET430UIF u tun theo cc bc sau Bc 1: Download driver cho FET430UIF v lu vo PC i vi Windows 7-64 bit: processors.wiki.ti.com/images/d/dc/TUSBWINVCP_Win7-64.zip i vi Windows 7-32 bit: processors.wiki.ti.com/images/6/6a/TUSBWINVCP_Win7-32.zip i vi WindowsXP-32 bit: processors.wiki.ti.com/images/7/73/TUSBWINVCP_XP32.zip i vi WindowsXP-64 bit: processors.wiki.ti.com/images/3/3b/TUSBWINVCP_XP64.zip i vi cc h iu hnh khc, la chn drive ph hp ti a ch:

http://processors.wiki.ti.com/index.php/MSP430_JTAG_Interface_USB_Driver Bc 2: Gn FET430UIF vo my vi tnh qua cng USB Bc 3: Click phi chut vo Computer/ chn Properties s cho ca s sau.
Tip theo click vo Device Manager. Bc 4: Click phi trn phn thit b m cha c ci t, ri chn Properties. Tip n chn tab Driver / Update Driver v chn ng dn n file driver c download bc 1.
3. Cng c son tho, m phng, bin dch v np chng trnh:

lp trnh v debug, ngi pht trin ng dng c th s dng mt trong 3 gi cng c sau y: IAR Embeeded Workbench, TI Code Composer Essential (CCE) v TI Code Composer Studio (CCS). IAR c chn s dng v tnh n gin, gn nh ca n. Tham kho website http://www.iar.com/ bit thm thng tin v IAR. Download IAR Embedded Workbench Code size limited Kickstart version ti: http://www.ti.com/lit/zip/slac050 C bn v s dng IAR to 1 project v lp trnh trn MSP430 u tun theo cc bc sau y

Bc 1: chy chng trnh IAR Embedded Workbench IDE theo ng dn
Start/All Programs/IAR Systems/ IAR Embeeded Workbench Kickstart for MSP430 4.21/ IAR Embeeded Workbench.
Hoc click chut vo Icon trn desktop nh hnh di y.
. Sau ca s giao din chng trnh s hin th
Bc 2: T ca s giao din chnh, chn Project/ Create New Project
Bc 3: chn ngn ng s dng. Trong th nghim ny, chng ta chn Empty project hoc C/main hoc Asm/asm v click OK. y, la chn Empty project c s dng, sau click vo nt
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OK tin hnh bc tip theo.
Bc 4: Chn ng dn mun lu project v tn Project. Trong v d ny, tn project l lab1 v

c lu trong th mc my lab.
Nu bc 3 chn Empty project th ca s c giao din nh sau:
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Nu bc 3 chn C/main th ca s c giao din nh sau:
Bc 5: thit lp cc ty chn: vi iu khin, debug, file np,.

Chn Project/Option (hoc Alt+F7)
Trong mc General Options -> chn tab Target -> chn MSP430FG4618
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Tip tc, chn cc tab khc thit lp nh sau (cc la chn cn li, xem help r hn) Trong tab Output: chn Output file: Executable Trong tab Library Configuration: chn Library: CLIB Trong mc C/C++ Compiler: (nu la chn ngn ng lp trnh l ngn ng C)
Trong tab Optimizations: chn level: None ( h tr ti a qu trnh debug) Trong tab List: chn Output list file: Assembler mnemonics Trong mc Debugger: Trong tab Setup: chn Driver: FET Debugger
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Trong FET Debugger: Trong tab Setup: chn Connection: Texas Instrument USB-IF. Xong cc chn la trn trong bc 5, click OK lu li ty chn tip tc bc 6 Bc 6: Thit lp file lp trnh
(Nu bc 3 chn ngn ng C hoc Asm th c sn mt s file mc nh trn ca s lm vic, ta c th s dng lp trnh, hoc remove chng to cc file khc, hoc add thm file vo.)
File/ New/File, ca s c giao din nh hnh sau:
Vi mn hnh son tho pha bn phi ca s lm vic, ngi lp trnh c th bin son chng trnh.
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Sau , file c lu bng: File/Save vi tn v nh dng: lab1.c.
( Hoc nu bc 3 chn ngn ng C th ca s son tho s ging nh hnh di y.
)
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File lab1.c ny cha c a vo project lab1. a file lab1.c vo project dng, ta cn: Project/Add file, mt ca s hin ra v chn lab1.c nh giao din sau:
Lc ny, trong ca s lm vic project s nh sau:
Bc 7: Bin dch file lp trnh

Thc hin: Project/Compile (hoc Ctrl + F7), lc ny IAR s yu cu lu li Workspace lm vic vi giao din sau. Nhp tn Workspace, trong hng dn ny, l lab.eww
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Sau khi lu Workspace, qu trnh bin dch s c thc hin. Nu khng c li th s hin ra thng bo nh sau (nu c li, tra cu t help)
Bc 8: Lp trnh-debug cho chip

Thc hin Project/Download and Debug (hoc Ctrl+D). thy kt qu thc hin trn kit: Debug/Go (hoc F5)
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Khi bin dch v np thnh cng, ta c th tin hnh debugger trc tip trn mch bng cc Step
4. Thit lp c bn cho th nghim

Sau y l cc bc c bn nht m ngi lm th nghim phi nm k trc khi bt tay vo s dng mi cng c thc hin cc bi th nghim. Trong tng bi th nghim, s trnh by cc bc thit lp thm ty thuc tng bi. Bc 1: Thit lp MSP-EXP430FG4618 - Kim tra/s dng jumper PWR1 cung cp ngun cho FG4618. (jumper PWR1 nm khong gia kit, pha bn phi chip M430G4618, nu t kit nh v tr hnh 1) - Kim tra/ khng s dng jumper BATT (jumper BATT pha di, bn phi kit). Khi th nghim, thit lp nh vy khng s dng pin cung cp ngun cho 2 chip vi mc ch tit kim pin. - Kim tra/ s dng jumper Vcc (jumper Vcc pha di, bn phi kit). thit lp s dng ngun t FET (khi khng dng pin), thit lp jumper v tr FET cho c 2 hng 1 v 2 (ngha l 2 jumper kt ni, mi jumper kt ni 2 header tn cng bn phi: 2 header pha di: dng cho FG4618/JTAG1, 2 chn pha trn: dng cho F2013/JTAG2). Bc 2: Kt ni FET430UIF - Kt ni dy USB gia my tnh v FET. - Kt ni dy 14 pin JTAG gia FET v kit MSP-EXP430FG4618.
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Thay i cc Jump trn mch:
Trn mch np, led xanh (Power) bo hiu ngun, led (Mode) bo hiu khi mch c np. Bc 3: S dng IAR lp trnh-debug Bc 4: Thc hin cc bi th nghim.
5.Cu trc mt chng trnh C thng thng cho MSP430
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Ch : o Trong hm main ta thng thy dng lnh: WDTCTL = WDTPW + WDTHOLD; Stop watchdog timer n khi reset chip. Nu khng c lnh ny (v khng c ty chn khc con WDTCTL) th mch s khng hot ng. o Trong C cho MSP430, th c cc hng s c nh ngha trc ( file header), ta rt hay dng cc hng s ny: BIT0 = 0000 0001 BIT1 = 0000 0010 BIT2 = 0000 0100 BIT7 = 1000 0000 o Mt chn ca MSP430 thng c nhiu chc nng, ta mun s dng chc nng g th nh ngha cho n. V d: P1DIR = 0xFF; // ton b port1 l Output P1DIR = 0x00; //ton b port1 l Input Nh vy nu mun mt s chn ca port1 l Output v mt s chn ca port1 l Input th lm th no? Khng ging mt s VK khc, MSP430 khng cho php ta tc ng trc tip n 1 chn no ring l, ch c th tc ng ln port (8 chn). Nh vy mun tc ng ln chn ring l no th ta dng php ton OR, AND v XOR. V d: P1DIR |= BIT1; //chn P1.1 s l chn Output, cc chn khc ko b nh hng bi lnh ny P1DIR &= ~BIT1; // chn P1.1 s l chn Input (nu ta ko nh ngha th n mc nh l Input) P2DIR |= BIT0 + BIT1 + BIT3; //chn P2.0, P2.1, P2.3 s l Output Lnh trn cng c th vit li: P2DIR |= 0x0B; // BIT0 + BIT1 + BIT3 = 11d=0Bh P2DIR &= ~(BIT4+BIT5); //P2DIR &=~0x30; //chn P2.4, P2.5 l Input o Xut ra port theo tng bit ring l. Nh vic nh ngha cc chn, MSP430 cng khng cho ta tc ng trc tip n tng chn no, mun xut ra mt bit hay nhiu bit bt k ta s dng cch nh dng vi nh ngha chn. V d mun cho P1.1=1, P1.3=1, P2.1=0 P1OUT |= BIT1+BIT3 ; //P1.1=1, P1.3=1 P2OUT &=~ BIT1 ; //P2.1=0 Hoc c th o mt bit chn bt k bng ln XOR ^ P1OUT ^= BIT4 ; //chn P1.4 o trng thi o Kim tra trng thi mt chn. Ngoi ngt ra ta c th kim tra trng thi mt chn no ang mc thp (0V) hay mc cao (1.8V n 3.6V). V d kim tra chn P1.2 if( (P1IN&BIT2)==0 ) //nu chn P1.2 bng 0 //do anything else //do anything // nu vit if( P1IN&BIT2==0 ), thiu 1 ngoc l sai
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6. Cc bi th nghim Bi 1: GPIO
6.1. Cc thanh ghi lin quan n GPIO: 6.1.1. Direction Register PxDIR (P1DIR, P2DIR):
y l cc thanh ghi 8 bit iu khin chiu ca 8 chn port. P1DIR iu khin PORT1, P2DIR iu khin PORT2. Bit = 1: Chn PORT tng ng c cu hnh thnh output Bit = 0: Chn PORT tng ng c cu hnh thnh input
6.1.2. Input Register (PxIN):
y l cc thanh ghi 8 bit cha gi tr c c t cc chn PORT. Bit = 1: Chn PORT tng ng mc cao Bit = 0: Chn PORT tng ng mc thp. y l thanh ghi iu khin ng ra ca cc PORT. Bit = 1: Xut mc cao ra chn PORT tng ng. Bit = 0: Xut mc thp ra chn PORT tng ng.
6.1.3. Output Register (PxOUT):
6.1.4. Function Select Register:

y l thanh ghi chn chc nng cho chn PORT. Mi chn PORT c th cu hnh chn chc nng Input/Output hay l chc nng c bit khc. Bit = 1: Chn chc nng c bit. Bit = 0: Chn chc nng GPIO. Trong lab ny, chng ta khng cn s dng Watchdog timer. tt Watchdog timer, ghi gi tr 5A vo 8 bit cao ca thanh ghi WDTCTL v set th 7 ca thanh ghi WDTCTL. WDTCTL = 0x5A00 | 0x0080 Hoc: (WDTCTL = WDTPW | WDTHOLD )
Cc lu khi vit chng trnh cho lab ny: - Watchdog Timer
Delay:
Bi v trong chng trnh cha nh ngha clock nn CPU s s dng thch anh 32.768 kHz. c thi gian delay khong 1s, vng delay s m xung t 30.000SV c th dng cu lnh di y to delay: for(int i=30000;i>0;i++);
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Bi 1.1
Yu cu: Sinh vin vit chng trnh cho LED1 v LED2 sng tt lun phin. Thi gian gia 2 ln sng tt l khong 1s.
Cu hi 1: Cc LED c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + LED1 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + LED2 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + iu khin LED, cc chn port phi l input hay output? Tr li: + LED sng, phi xut gi tr g ra chn port? Tr li: Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> void main (void) { volatile unsigned int i; WDTCTL = | ; P2DIR |= .; P2OUT &= .; P2OUT |= ; while(1) { i= .; do (i--); while (i !=0);
//Stop Watchdog Timer //Configure P2.1 and P2.2 as Output // Turn off LED1, LED2 // Turn on LED 1, turn off LED 2 //Infinite loop //Delay
//Toggle Port P2.1 and P2.2 using an exclusive-OR P2OUT ^= ; } }
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Bi 1.2
Yu cu: Sinh vin vit chng trnh o trng thi LED1 mi khi SW1 c nhn.
Cu hi 1: Cc SW(switch) c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + SW1 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + SW2 ni vo chn no ca MCU? (Cng (Port) no?) Tr li: + c trng thi switch, cc chn port phi l input hay output? Tr li: Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> void main (void) { volatile unsigned int i; WDTCTL = .; P2DIR |= ..; P1DIR &= ........; while (1) { while ((P1IN & 0x01)); P2OUT ^= .; for(.........); while (....); for(.........); } }
//Stop Watchdog Timer //Configure P2.2 as Output (LED1) //Configure P1.0 as Input (S1) //Wait for the press of the button //Toggle Port P2.2 //Delay, button debounce //Wait for the release of the button //Delay, button debounce
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Bi 2. GPIO & INTERRUPT

MSP430 c thit k lm vic vi cc ng dng cng sut thp. V vy CPU thng trng thi off trong phn ln thi gian. a CPU vo trng thi off, cc bit SCG1, SCG0 v CPUOFF trong thanh ghi SR c set. Mt ngt xy ra s nh thc CPU. Khi thanh ghi SR c lu vo stack v CPU thc thi ISR. Khi thot khi ISR, thanh ghi SR c ly ra t stack v lm cho CPU tt tr li. a CPU vo trng thi cng sut thp v cho php ngt: Bit GIE trong thanh ghi SR khi c set s cho php ngt. Ta a CPU vo trng thi cng sut thp, cho php ngt bng lnh: _BIS_SR (LPM3_bits + GIE); Trong : LPM3_bits = (SCG1+SCG0+CPUOFF) nh ngha chng trnh phc v ngt (ISR): Ta nh ngha 1 ISR ti vector ngt ISR_VECTOR bng cu trc sau: #pragma vector=ISR_VECTOR interrupt void myISR (void) { } Mi chn PORT ca MSP430 u c th dng to ngt. Cc ngt ny c cu hnh thng qua cc thanh ghi PxIFG, PxIE, PxIES.
6.1.5. Cc thanh ghi cu hnh ngt cho cc chn PORT:
6.1.5.1.
Interrupt enable Register (PxIE) :
Mi bit trong thanh ghi ny dng cho php/khng cho php ngt trn chn PORT tng ng. Bit = 1: Cho php ngt. Bit = 0: Cm ngt.
6.1.5.2.
Interrupt Edge Select Registers (PxIES):
Dng chn cnh ca tn hiu ngt Bit = 1: Ngt ti cnh xung ca tn hiu. Bit = 0: Ngt ti cnh ln ca tn hiu. Thanh ghi ny cha cc c ngt. Cc c ny c t ng bt bi phn cng, phi c xa bng phn mm. Cc c ny c th c bt bng phn mm cho php ngt. Bit = 1: Mt ngt ang ch x l. Bit = 0: Khng c ngt no ang ch.
6.1.5.3.
Interrupt Flag Registers (PxIFG):
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Bi 2.1
Yu cu: Sinh vin vit chng trnh o trng thi LED1 khi Switch 1 c nhn. Trong chng trnh s dng ngt trn chn port giao tip Switch.
Cu hi 1: Cc SW(switch) c kt ni vi MCU nh hnh trn. in vo ch trng tr li cc cu hi di y. + SW1 ni vo chn Port g ca CPU? Tr li: + Khi Switch c nhn, s c chuyn trng thi nh th no trn chn PORT? + cho php ngt trn chn P1.0, ta phi ghi vo bit.ca thanh ghi .? + chn cnh xung cho ngt trn chn P1.0, ta phi ghi vo bit.ca thanh ghi ? Cu hi 2: Hon chnh chng trnh bng cch in vo cc ch trng: #include <msp430xG46x.h> #pragma vector= __interrupt void Port_1 (void) { //define an interrupt service routine at 0xFFE8 volatile unsigned int i; P2OUT ^= ; //Toggle Port P2.2 for(); //Delay, button debounce while (...); //Wait for the release of the button for(.); //Delay, button debounce P1IFG &= ~0x01; //Clean P1.0 Interrupt Flag (bit 0 of P1IFG register) } void main (void) { WDTCTL = ; //Stop Watchdog Timer P2DIR |= ; //Configure P2.2 as Output (LED1) P1DIR &= ..; //Configure P1.0 as Input (S1) P1IE |= ...; //Interrupt Enable in P1.0 P1IES |= .; //P1.0 Interrupt flag high-to-low transition _BIS_SR (..); //Low Power Mode with interrupts enabled }
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Bi 3: TIMER
cu hnh cho timer, u tin b FLL+ to xung nhp phi c cu hnh trc chn xung nhp a vo timer. Sau cc gi tr thch hp s c a vo cc thanh ghi cu hnh cho timer lm timer hot ng theo ch mong mun. Timer ca MSP430x4xxx: - Basic Timer 1 - Timer_A - Timer_B
6.2. Basic Timer 1 Module:
Hnh 6.2.1: S khi ca Basic Timer 1
6.2.1.
-
Basic Timer1 Counter 1 (BTCNT1):
Dng to tn s frame (frame frequency) cho b iu khin LCD (LCD Controller) L thanh ghi 8 bit, c th ghi/c Ngun clock: ACLK H s chia cho clock ng ra (fLCD) c chn bi cc bit BTFRFQx trong thanh ghi BTCTL. fLCD = ACLK / x
6.2.2.
Basic Timer1 Counter 2 (BTCNT2):
L b chia tn s c kh nng to ngt, dng ta nhng ngt theo chu k cho CPU hoc to thnh h thng ng h thi gian thc. L thanh ghi 8 bit, c th ghi/c Ngun clock: ACLK, SMCLK, hoc SMCLK/256 khi mc ni tip vi BTCNT1 H s chia cho clock ng ra (fLCD) c chn bi cc bit BTFRFQx trong thanh ghi BTCTL. Dng to ngt Basic Timer 1 Interrupt BTIFG, thi gian ngt c chn bi cc bit BTIPx trong thanh ghi BTCTL.
6.2.3. Cc thanh ghi cho Basic Timer 1 Module: 6.2.3.1. BTCTL, Basic Timer 1 Control Register:
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6.2.3.2. IE2, Interrupt Enable Register 2:
6.2.3.3. IFG2, Interrupt Flag Register 2:
6.3. Cc ngun xung nhp:

Xung nhp h thng ca MSP430x4xx c nh ngha bi b kha tn s FLL+ (Frequency Locked Loop). FLL+ c th lm vic vi thch anh gn ngoi hay b dao ng ni. FLL+ gm c 3 ngun : - LFXT1CLK: B dao ng c kh nng to xung nhp tc thp vi thch anh ng h 32.768 Hz, hoc xung nhp tc cao vi thch anh, resonance hay ngun xung nhp ngoi vi tn s t 450Khz-8Mhz. - XT2CLK: B dao ng c kh nng to xung nhp tc cao vi thch anh, resonance hay ngun xung nhp ngoi vi tn s t 450Khz-8Mhz.
28
DCOCLK: B dao ng R-C ni, c n nh tn s bi FLL. C 4 tn hiu xung nhp c to ra: - Master Clock (MCLK): c chn bi phn mm t cc ngun LFXT1CLK, XT2CLK hoc DCO. MCLK c th c chia bi cc h s 1, 2, 4, 8 trc khi s dng. MCLK c s dng bi CPU v h thng. - Sub-System Main Clock (SMCLK): c chn bi phn mm gia XT2CLK v DCOCLK. SMCLK c th c chn bng phn mm cho cc ngoi vi. - Auxiliary Clock (ACLK): ACLK c ta ra t LFXT1CLK, c th c chn bng phn mm cho ngoi vi. - Buffered Auxiliary Clock (ACLK/n): L ng ra c m ca ACLK. ACLK/n chnh l ACLK chia cho h s chia 1, 2, 4, 8 v c s dng cho cc ngoi vi bn ngoi. Sau khi reset, MCLK v SMCLK c ly t DCOCLK tn s gp 32 ln ACLK. Nu b dao ng LFXT1CLK s dng thch anh 32.768 Hz, tn s ca MCLK v SMCLK s l 1.048576 Mhz.
6.3.1.
Hnh 6.2.2: S khi b to xung nhp Cc b to dao ng:
6.3.1.1. Low/High Frequency Oscillator (LFXT1):

B dao ng ny c th c dng to xung nhp tc thp (low speed) t thch anh ng h (tn s 32.768 Mhz) hoc xung nhp tc cao (high speed) t thch anh ngoi hoc b dao ng ngoi vi tm t 450 Khz n 8 Mhz. Bit XTS_FLL trong thanh ghi FLL_CTL0 dng chn la ch hot ng ca LFXT1. - XTS_FLL = 0 : Low speed
29
XTS_FLL = 1: High Speed Gi tr t in bn trong ca b dao ng (1, 6, 8, 10pF) c chn bi cc bit XCAPxPF. B dao ng LFXT1 c th c tt bng cch set bit OSCOFF ln 1 nu LFXT1 khng c chn to ngun cho MCLK (SELM # 3 hoc CPUOFF = 1).
6.3.1.2. B giao ng tn s cao (High Frequency Oscillator) (XT2):

B dao ng XT2 dng thch anh ngoi to dao ng tn s cao XT2CLK. B dao ng XT2 khng c t bn trong, v vy t ngoi s cn c s dng khi giao tip thch anh. B dao ng XT2 c th c tt bng cch set bit XT2OFF ln 1 nu XT2CLK khng c chn to ngun cho MCLK (SELM # 2 hoc CPUOFF = 1) v SMCLK (SELS = 0 hoc SMCLKOFF = 1).
6.3.1.3. B dao ng ni DCO:

B dao ng DCO dng FLL nhn tn hiu ACLK ln (N+1) ln, vi N l 7 bit thp ca thanh ghi SCFQCTL. Bit DCOPLUS chn tn s fDCOCLK bng fDCO hoc fDCO/D. S chia D bng 1, 2, 4, 8 v c chn bi cc bit FLLDx. Sau khi reset, DCOPLUS bng 0 v D bng 2. - DCOPLUS = 0: fDCOCLK = (N+1) x fACLK. - DCOPLUS = 1: fDCOCLK = D x (N+1) x fACLK. Gii hn tn s ca DCO: Gii hn tn s dao ng ca DCO c chn bi cc bit FNx. Ngi lp trnh phi m bo tn s ca MCLK khng vt qu tn s hot ng cao nht ca DCO.
6.3.2. Cc thanh ghi iu khin clock: 6.3.2.1. SCFQCTL, System Clock Control Register :
6.3.2.2. SCFI0, System Clock Frequency Integrator Register 0 :
30
6.3.2.3. SCFI1, System Clock Frequency Integrator Register 1:
6.3.2.4. FLL_CTLO, FLL+ Control Register 0:
31
6.3.2.5. FLL_CTL1, FLL+ Control Register 1:
6.4. Cc ch hot ng:

MSP430 c thit k hot ng ch cng sut thp. Cc ch hot ng c cu hnh bi cc bit CPUOFF, OSCOFF, SCG0, v SCG1 trong thanh ghi trng thi SR.
32
33
Bi 3.1
Yu cu: Sinh vin vit chng trnh o trng thi LED1 v LED2 sau thi gian 1s, s dng ngt Basic Timer 1 Interrupt. Cu hi 1: v hiu ha Watchdog Timer, ta phi ghi vo thanh ghi WDTCTL mt gi tr bng bao nhiu? WDTCTL = ..; Cu hi 2: Cu hnh FLL+ Mt thch anh tn s 32768 Hz uc ni vo b dao ng LFXT1. Ta phi ghi vo thanh ghi FLL_CTL0 gi tr g chn t bn trong c gi tr 8PF? FLL_CTL0 |= ...; Vi cc thanh ghi khc gi tr mc nh, tn s ca cc tn hiu xung nhp s bang bao nhiu? ACLK = ; MCLK = ; SMCLK = ..; Cu hi 3: Cu hnh GPIO LED1 v LED2 c ni vo chn P2.2 v P2.1. Ta phi ghi vo thanh ghi no vi gi tr g cu hnh cho 2 chn PORT ny thnh output, cn li l input? . = .; Ta phi ghi vo thanh ghi no vi gi tr g lm cho LED1 sng, LED2 tt? . = .; Cu hi 4: Cu hnh cho Basic Timer 1: Ta dng Basic Timer 1 to ngt. Basic timer gm 2 b m mc ni tip, trong ng vo ca BTCNT2 l ng ra ca BTCNT1 chia cho 256. (Tham kho hnh 2.1). Ng vo ca BTCNT1 l tn hiu ACLK c tn s 32768 Hz. Ng ra ca BTCNT2 phi c chia cho bao nhiu c ngt Basic Timer 1 c chu k l 1s? .. Gi tr phi ghi vo cc thanh ghi sau l bao nhiu c s chia cho BTCNT2 nh trn v cho php ngt? BTCTL = ; IE2 = ...; Cu hi 5: Ch cng sut thp: Chng trnh n gin o trng thi LED1 v LED2 trong ngt. Ch cng sut thp no nn c s dng? . Khi , ngun xung nhp no s c tch cc trong sut qu trnh hot ng? ..................................... Cu hi 6: Hon tt chng trnh: #include <msp430xG46x.h> //***************************************************************** // Basic Timer interrupt service routine: refresh LCD with 0.5 sec //***************************************************************** #pragma vector=BASICTIMER_VECTOR __interrupt void basic_timer_ISR(void) { P2OUT ^=0x06; // LED2 toogle } //*****************************************************************
34

// Main routine //***************************************************************** void main(void) { WDTCTL = ..................................; // Stop WDT FLL_CTL0 |= ...............................; // Set load cap for 32k xtal // Basic Timer 1 Configuration BTCTL = ......................................; // (ACLK/256)/64 IE2 |= ............................................; // Enable BT interrupt with 0.5 period // LED1 & LED2 configuration P2DIR = ........................................; // P2.2 and P2.1 as digital output P2OUT = ......................................; // LED1 on and LED2 off __bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupt }
Bi 3.2
Yu cu: Sinh vin vit chng trnh hin th gi tr ln lt t 0 -> 9 ln led 7 on P1 ca LCD. Gi tr hin th tng ln 1 sau 1 s. Nu n SW2, chng trnh ngng m (gi tr ngng tng ln). Nu n SW1, chng trnh hot ng bnh thng. Chng trnh s dng ngt timer hin th LCD, ngt ngoi trn chn P2.1 v P2.2 cho php chng trnh dng m hay tip tc hot ng. LCD s dng trn board c cc phn t hin th nh sau:
P1 S dng file lcd.h km theo
35
36
Bi 3.3
Yu cu: Thit k mt ng h s n gin (cho php la chn gia real time hoc s dng b nh thi)
37

Lab MSP430 2012

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Lab MSP430 2012

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1

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

1.1. Gii thiu chung:

Hnh 1. KIT MSP-EXP430FG4618 do TI ti tr cho b mn K thut My tnh

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

1.2. S khi phn b linh kin trn KIT MSP-EXP430FG4618

Hnh 2. S khi phn b linh kin trn KIT MSP-EXP430FG4618

Hnh 3. S nguyn l Microphone trn KIT MSP430FG4618

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

1.2.5. Nt nhn S1 v S2:

Hnh 4. S nguyn l kt ni nt nhn S1 & S2 vi MSP430FG4618

Kt ni vi chip MSP430FG4618 MSP430FG4618 MSP430F2013 MSP430FG4618

Port P2.2 P2.1 P1.0 P5.1

Ghi ch Jumper JP2 JP3

Hnh 5.S nguyn l kt ni LED1, LED2 & LED4 vi MSP430FG4618

Hnh 6. S nguyn l kt ni LED3 vi MSP430F2013

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

1.2.7. Giao tip RS232

Hnh 7. S nguyn l giao tip cng RS232 vi MSP430FG4618

Hnh 8.S b tr jumper trn KIT MSP430FG4618

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Yu cu khi s dng khng cn pin

Bng 2.Lit k chc nng ca jumper trn KIT MSP430FG4618 khi c kt ni

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

1.3. S nguyn l ca KIT MSP-EXP430FG4618

Hnh 9.S nguyn l ton KIT MSP430FG4618

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

2.c tnh v cch ci t b Debug MSP-FET430UIF

Hnh 10. B Debug MSP-FET430UIF

Bng 3. So snh mt vi tnh nng gia 2 loi MSP-FET430UIF v MSP- FET430PIF

2.2.Ci t driver ca b Debug MSP-FET430UIF ln PC

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

3. Cng c son tho, m phng, bin dch v np chng trnh:

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Hoc click chut vo Icon trn desktop nh hnh di y.

. Sau ca s giao din chng trnh s hin th

Bc 2: T ca s giao din chnh, chn Project/ Create New Project

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

OK tin hnh bc tip theo.

Bc 4: Chn ng dn mun lu project v tn Project. Trong v d ny, tn project l lab1 v

Nu bc 3 chn Empty project th ca s c giao din nh sau:

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Bc 5: thit lp cc ty chn: vi iu khin, debug, file np,.

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Sau , file c lu bng: File/Save vi tn v nh dng: lab1.c.

( Hoc nu bc 3 chn ngn ng C th ca s son tho s ging nh hnh di y.

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Lc ny, trong ca s lm vic project s nh sau:

Bc 7: Bin dch file lp trnh

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Bc 8: Lp trnh-debug cho chip

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

4. Thit lp c bn cho th nghim

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

5.Cu trc mt chng trnh C thng thng cho MSP430

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012

6.1.2. Input Register (PxIN):

6.1.3. Output Register (PxOUT):

6.1.4. Function Select Register:

Cc lu khi vit chng trnh cho lab ny: - Watchdog Timer

Ta i lie u hng dan th nghie m Vi x ly va Vi ieu khien, 2012