Hng dn s dng phn mm Xilinx ISE Xilinx ISE v Xilinx EDK l hai b phn mm chuyn dng cu hnh cho

o FPGA ca hng Xilinx. Xilinx ISE dng cho vic bin dch v tng hp cc file HDL (VHDL hoc Verilog HDL) thnh file bitstream (*.bit) cu hnh cho FPGA. Xilinx EDK chuyn dng h tr pht trin cc ng dng nhng c cha CPU trn FPGA ca Xilinx. Ngoi ra, Xilinx ISE cn h tr m phng cc file HDL kim tra xem h thng c hot ng ng nh yu cu cn thit k hay khng. Hn na, Xilinx ISE cn c th kt hp vi phn mm ModelSim ca hng Mentor Graphic thc thi nhng tc v m phng ln vit bng ngn ng HDL. 1. Xilinx ISE 1.1. Tng quan v Xilinx ISE Xilinx ISE (Integrated Software Environment) l mt b phn mm thit k ca Xilinx , cho php ta thc hin cc h thng nhng ca Xilinx t khu thit k ban u (thng qua VHDL, Verilog HDL, ABEL hoc l v Schematic) cho n khu cui cng l np thit k ca mnh ln FPGA. bt u mt thit k, ta phi to mt project mi trong ISE thng qua cng c qun l ISE Project Navigator. Sau ISE Project Navigator s qun l tt c cc qu trnh thit k trong trong project .

Ch thch 1: Toolbar : Hp cng c ca ISE 2: Ca s qun l cc file trong project. 3: Ca s qun l tin trnh trong ISE . 4: Ca s lm vic (Work Space) : cho php xem,chnh sa cc file ngun, dng sng. 5: Ca s console : hin th thng bo v cc tin trnh ang chy, thng bo li Quy trnh thit kt trong ISE bao gm cc qu trnh sau : Design Entry -> Synthesis -> Implementation -> Verification -> Device Configuration. * Design Entry : y l bc u tin trong qu trnh thit k ca ISE. Trong sut qu trnh design entry, ta s thit k nhng file ngun (Source File) theo nhng yu cu ban u (nhng m t chc nng ca h thng m ta cn phi thit k). bc ny, ta s dng nhng ngn ng m t phn cng nh : VHDL, Verilog HDL, Abel hoc dng Schematic thit k . Chng ta c th dng nhiu ngn ng khc nhau trong cng mt

thit k. V d nh : thit k cc module chc nng bng Verilog HDL, sau dng dng schematic (s khi) thit k h thng chnh. * Synthesis : Sau khi thit k h thng v thc hin nhng m phng kim tra chc nng logic ca h thng, chng ta phi chy synthesis chuyn i nhng file ngun c vit bng VHDL,Verilog HDL, thnh file netlist. Nhng file netlist ny cn thit a vo qu trnh Implementation. * Implementation : Qu trnh ny s chuyn i thit k mc logic thnh cc file nh dng vt l c th download xung FPGA. Sau khi chy Synthesis, chng ta s c nhng file netlist, qu trnh Implementation s chuyn i nhng file netlist thnh nhng file cu hnh vt l c th da vo linh kin FPGA c th m ta ang s dng, do qu trnh ny i hi chng ta phi ch r linh kin FPGA no ang c s dng. * Verification: Sau khi chy bc Implementation, chng ta s c th m phng thit k ca mnh mt cch chnh xc hn. V qu trnh m phng bc Design Entry ch c th m phng chc nng ca mch ch n cha th m phng thi gian (timing), timing ty thuc vo linh kin vt l c th . * Device Configuration: y l bc cui cng trong sut qu trnh thit k . bc ny cc file nh dng cu hnh s c dng to ra nhng file bitstream np xung chip FPGA .

1.2. Qu trnh thit k trn ISE : d hnh dung, ta s to mt mch m nh phn n gin trn kit XUP (do Digilent ch to vi FPGA Virtex II Pro ca Xilinx) vi Xilinx ISE bng ngn ng Verilog HDL.

* M t h thng: Mch m nh phn nhn xung clock t h thng xung clock trn XUP v tn hiu RESET c to ra t nt n trn kit, gi tr m (8 bit) s c xut ra 8 led trn kit. Mch m nh phn s reset li nu c tn hiu reset t nt n. * To project trong Xilinx ISE bt u thit k ,vic u tin ta phi lm l to mt project mi. File -> New Project, sau in tn ca project mi counter vo project name v ch ng dn cha project counter trong project location. Do chng ta s dng Verilog HDL thit k nn chng s chn phn Top-level Module type l HDL, sau n next.

Chn FPGA ang s dng trn kit, i vi kit XUP, chn Device family l Virtex2p, Device : XC2VP30, Package : ff896, Speed Grade : -7, n next.

Chn "New Source" v chn "Verilog Module" (bi v ta ang dng verilog), in tn ca module cn thit k : counter. n next.

Khai bo cc input, output ca module counter (input l : clk, reset; output l : data_out).

n next cho n khi hon thnh bc to mt file source mi, sau double click chn counter.v trn ca s qun l file trong project m file counter.v, sau thm cc dng lnh vit cho module counter nh hnh v.

Vic tip theo l phi map chn cho module counter vi chn clock ca kit, cc led, v nt n vi tn hiu reset, vic gn chn ny phi tham kho User Guide ca kit bit cc chn c th. C th mch counter ny ta s gn tn hiu clk vi chn AJ15, ngun clock ca kit, reset vi chn AG5, v cc chn data_out vi cc chn led : V7, Y2, V5, U7, W1, V3, T9, V2. Chn Assign Package Pin trong phn User Constraint trong ca s qun l cc tin trnh, v gn chn nh trong hnh v, sau khi gn chn xong, save li file cha thng tin vic gn chn ca h thng (*.ucf).

Sau khi gn chn xong, ta s chuyn sang qu trnh Synthesis. Chn Synthesis-XST trong ca s tin trnh. Nu file source b sai c php th qu trnh Synthesis s bo li, khi ta phi sa li cho ng. Nu file source ng th qu trnh Synthesis s to ra cc file netlist , khi s c du check mu xanh hin ln bo cho ta bit l qu trnh

Synthesis thnh cng. Sau khi Synthesis xong, chng ta s chn Implement Design trong ca s tin trnh to ra cc file cu hnh cho module counter. Sau qu trnh Implement chng ta c cc file cu hnh ca h thng, tuy nhin c rt nhiu loi file cu hnh ty theo chng ta s khi ng h thng t thit b no : nu mun khi ng t PROM ta s cn phi to ra file cu hnh theo nh dng hex hoc bin, nu mun khi ng t Compact Flash th cn phi to ra file *.ace. Vic to ra file cu hnh c thc hin khi chn Generate PROM, ACE or JTAG file trong ca s qun l tin trnh. Sau chng ta c np trc tip file cu hnh t JTAG hoc chp file cu hnh vo CF card, hoc np vo PROM. np trc tip qua JTAG, ta chn Confige Device (iMPACT) trong ca s tin trnh. Sau ISE Project Navigator s khi ng gi iMPACT bt u dectect xem kit c sn sng np cha, nu c th iMPACT s yu cu ta chn file cu hnh np v FPGA hoc PROM .

Sau khi gn xong file cu hnh ta s np file cu hnh vo FPGA .

Cc led trn kit s thc hin m nh phn. P/S: ti liu copy ti din n in t.com. nu bn mun vit chng trnh test bench cho sn phm FPGA ca mnh th vo project chn new source --->vhdl tesx becnh ---> g tn vo ri next.