Giao Trinh Thi Nghiem VDK

Gio trnh th nghim vi iu khin ng dng
MC LC
CHNG I : PHN CNG PIC16F.......................................................................................... 4
I.KIN TRC .......................................................................................................................... 4
1.Kin trc Von neumann .................................................................................................... 4
2.Kin trc harvard ............................................................................................................. 4
II.INSTRUCTION PIPELINING ........................................................................................... 5
III.KCH THC T LNH ................................................................................................. 9
IV.THIT K PHN CNG CHO PIC .............................................................................. 10
1.Mch nguyn l.................................................................................................................. 10
2.Chun ICSP(In-Circurt Serial Programming) .................................................................... 11
3.Cc tnh nng c bit, cc bit cu hnh ca PIC16F887................................................... 11
CHNG II : XUT NHP I/O PORT .................................................................................. 21
I.MC CH TH NGHIM ................................................................................................ 21
II.DNG C TH NGHIM ............................................................................................... 21
III.C S L THUYT ....................................................................................................... 21
1.Thanh ghi qui nh tn hiu x l ...................................................................................... 21
2.Chc nng ca thanh ghi TRIS ......................................................................................... 22
3. Chc nng ca thanh ghi PORT ...................................................................................... 22
4.Nhng thanh ghi c bit ch c ring PORTB .............................................................. 23
IV.BI TP THC HNH .................................................................................................. 26
V.BI TP T GII ........................................................................................................... 32
CHNG III : ADC MODULE................................................................................................ 33
I.MC CH TH NGHIM ................................................................................................ 33
II.DNG C TH NGHIM ................................................................................................. 33
III.C S L THUYT ...................................................................................................... 33
1.Tn hiu tng t v tn hiu s ........................................................................................ 33
2.ADC ca vi iu khin PIC16F887 ................................................................................... 34
3.Lm vic vi LCD 16x2 ................................................................................................... 38
IV.BI TP THC HNH .................................................................................................. 40
V.BI TP T GII ............................................................................................................. 44
1

CHNG IV :TIMER ............................................................................................................... 46
I.MC CH TH NGHIM ................................................................................................ 46
II.DNG C TH NGHIM ................................................................................................. 46
III.C S L THUYT ....................................................................................................... 46
1.Nguyn tc hot ng ca timer : ...................................................................................... 47
2.Timer 0 .............................................................................................................................. 47
3.Timer 1 .............................................................................................................................. 50
4.Timer 2 .............................................................................................................................. 53
IV.BI TP THC HNH .................................................................................................. 55
V.BI TP T GII ............................................................................................................. 60
CHNG V: KHI CCP .......................................................................................................... 61
(CAPTURE-COMPARE-PWM) ............................................................................................... 61
I.MC CH TH NGHIM ................................................................................................ 61
II.DNG C TH NGHIM ................................................................................................. 61
III.C S L THUYT ....................................................................................................... 61
1.Thanh ghi khi to khi CCP1
. .................................................................................. 62
2.Thanh ghi khi to khi CCP2 .......................................................................................... 63

3.Capture .............................................................................................................................. 64
4.Compare ............................................................................................................................ 64
5.PWM(Pulse-Width Modulated) ........................................................................................ 65
6.Cc bc khi to chc nng PWM ................................................................................. 66
IV.BI TP THC HNH ................................................................................................... 67
V.BI TP T GII ............................................................................................................. 70
CHNG VI :GIAO TIP NI TIP BT NG B........................................................ 72
I.MC CH TH NGHIM ................................................................................................ 72
II.DNG C TH NGHIM ................................................................................................. 72
III.C S L THUYT ....................................................................................................... 72
1.Khi nim v giao tip ni tip bt ng b ..................................................................... 72
2.Cc thanh ghi iu khin truyn UART ............................................................................ 74
3.Cc thanh ghi iu khin nhn UART .............................................................................. 76
5.Cng thc tnh tc baund rate ...................................................................................... 78
2

IV:BI TP THC HNH .................................................................................................. 78
V.BI TP T GII ............................................................................................................. 81
TI LIU THAM KHO ......................................................................................................... 83
PH LC ..................................................................................................................................... 84
I.CA S CHNG TRNH .............................................................................................. 84
II.CC BC KHI TO MT PROJECT MI ............................................................ 84
II.HI TECH C C BN ......................................................................................................... 88
1.Khai bo bin .................................................................................................................... 88
2.Kiu con tr ....................................................................................................................... 89
3.Kiu enum .......................................................................................................................... 89
4.Php ton hc ..................................................................................................................... 90
5.Php ton gn ..................................................................................................................... 90
6.Php ton tng , gim ......................................................................................................... 90
7.Php ton quan h .............................................................................................................. 90
8.Tan t logic ..................................................................................................................... 91
9.Ton t theo bit ................................................................................................................. 91
10.Chn mt on code Assembly ....................................................................................... 91
11.Cc ton t u tin .......................................................................................................... 92
12.Cu iu kin .................................................................................................................. 92
13.Ton t la chn ............................................................................................................. 94
14.Vng lp ........................................................................................................................... 95
15.Mng 1 chiu ................................................................................................................... 96
16.Mng hai chiu ................................................................................................................ 97
17.Cu trc ca mt chng trnh c c bn ......................................................................... 97
IV.S NGUYN L KIT TH NGHIM ..................................................................... 98
V.FILE LCD ......................................................................................................................... 101
1.lcd.c ...................................................................................................................................... 101
2.lcd.h...................................................................................................................................... 106
CHNG I : PHN CNG PIC16F

I.KIN TRC :
Microchip Pic c thit k da trn kin trc Harvard, mt kin trc RISC (Reduced
Instruction Set Conputer My tnh vi tp lnh n gin ha). y l mt kin trc mi vi
nhiu ci tin nng cao hiu nng x l v gim thiu gi thnh sn xut. Vy th nhng c tnh
no ca kin trc Havard mang li hiu qu cho PIC, chng ta th so snh hai kiu RISC kh
ph bin l Von Neumann v Harvard.
1.Kin trc Von neumann:
Cn gi l kin trc Princeton, cch t chc b nh ca kiu kin trc ny l c b nh
chng trnh v b nh d liu c xem nh mt vng nh, dng chung mt Bus d liu. Thi
k u ca k nguyn my tnh, b nh khng c tin cy nh hin nay v hay to ra nhng li
h thng. Chnh v vy m kiu kin trc ny c a chung, bi v n c d dng thit k,
nng cao tin cy ca h thng v d dng thay th nhng vng nh b li k thut. Nh nhng
li th m trong mt thi gian kiu kin trc ny c thng mi v sn xut. Tuy nhin
n cng c mt s nhc im: hn ch bng thng, thc hin nhiu ln ly d liu ch cho mt
lnh, khng th thc hin song song thao tc ny. Chnh v s ph bin u tin ca kin trc
Von Neumann m hu ht cc loi Vi iu Khin u c xy dng quanh cu trc ny, mc
d gi thnh b nh hin nay r hn rt nhiu v tin cy cng tng ln rt nhiu.
Von Neumann
Architecture
8-bit
Bus
CPU
Program
& Data
Memory
Hnh 1: Kin trc b nh kiu Von Neuman

2.Kin trc harvard :
Havard c khng gian nh dnh cho b nh d liu v b nh chng trnh ring bit. Li
th v hiu nng chnh ca kiu d liu ny l n c 2 Bus d liu ring bit hot ng ng thi
phc v cho b nh d liu v b nh chng trnh: Trong khi CPU ly d liu t b nh
chng trnh, th n vn c th c ghi d liu vng nh d liu.
4

Mt li th khc ca kin trc Harvard l rng Bus b nh chng trnh v Bus d liu
c th khc nhau. Khng phi tt tt c cc loi Vi iu Khin c kin trc Harvard iu c li
th ny, nhng PIC th c. Do bus c rng khc nhau nn rng Bus b nh chng trnh c
th rng hn b nh d liu. Vi PIC-8bit th Bus d liu lun l 8-bit, tuy nhin Bus b nh
chng trnh c th rng hn, bao nhiu ty thuc v mc ch ca loi PIC . Vi PIC 8-bit
th c 3 loi c phn chia thnh loi c rng Bus b nh chng trnh l 12-bit, 14-bit, v
16-bit. Bus b nh chng trnh rng hn s a d liu t b nh chng trnh nhiu hn cng
trong mt chu k my.
Harvard
Architecture
8-bit
Bus
14-bit
Bus
CPU
Data
Memory
Program
Memory
Hnh 2: Kin trc b nh kiu Von Neuman

II.INSTRUCTION PIPELINING:
Vic ly lnh/d liu t b nh chng trnh cng c thit k nng cao hiu sut.
Instruction pipelining l cch thc ly v thc thi lnh t b nh chng trnh mt cch ng
thi. C th xem hnh:
Hnh 3: Quy trnh thc thi cc lnh

PIC c bus truy xut b nh chng trnh v bus truy xut b nh d liu ring bit c th
hot ng ng thi. Nhng trong qu trnh ta ly mt lnh, lm th no bit c d liu cn
5

thit cho lnh u thc thi ng thi hai thao tc ny trong mt chu k lnh, bi v thng
tin a ch ca d liu cn thit trong vng nh d liu nm trong lnh kia.Vn c gii
quyt bng Instruction Pipelining.
Trong chu k lnh u tin khi CPU hot ng, lnh c ly vo Pipeline. Bus b nh
chng trnh c truy xut, Bus d liu khng hot ng.
Hnh 4: Thc hin lnh trong chu k u tin

Trong chu k lnh th 2, lnh ly trc c thc thi, c ngha l Bus d liu hot ng
trao i d liu vi CPU khi CPU thc thi lnh. ng thi trong lc ny, c 2 Bus u hot ng
ng thi.
Hnh 5: Thc hin lnh trong chu k th hai

Trong chu k lnh th 3, lnh th 2 ly trc c thc thi, ng thi lnh tip theo
c ly. Ti lc ny th mi th kh r rng, ngoi tr chu k lnh u tin ra, mi chu k
lnh s thc thi xong mt lnh, bao gm 2 bc ly lnh v thc thi. Bi v lc thc thi 1 lnh th
lnh c sn, v thng tin v a ch b nh d liu cng c ly vo t lc lnh trc
thc thi.
6
Hnh 6:Thc hin lnh trong chu k th ba

Chu k th 4,5:Vi quy trnh nh vy th lnh nm sau lun lun thc thi khi lnh trc n
thc thi xong. Tuy nhin khi b m chng trnh b thay i bng mt lnh, th c th lnh sau
khng c thc hin. y, lnh Call c thc thi khin chng trnh nhy n vng nh
khc v lnh ng sau lnh Call tt nhin ch c thc thi sau khi chng trnh tr v t hm
SUB1. Nhng, khi lnh Call c thc thi th lnh k tip n vn c ly vo Pipeline.
Hnh 7: Thc hin lnh trong chu k th 4

Nh vy cn thit phi loi b lnh sau Call ra khi Pipeline, ng thi ly mt lnh khc
vo Pipeline. C th thy, vi bt k mt lnh no lm thay i b m chng trnh th phi mt
2 chu k my.
7

III.KCH THC T LNH
Bi v c kin trc Harvard nn vi iu khin PIC c rng ca Bus b nh chng trnh
khng nht thit bng vi rng ca Bus b nh d liu (vi iu khin 8 bit th bus c rng
8 bit). i vi mt s vi iu khin dng kin trc Von neumann th s c cng rng bus. Do
rt nhiu lnh i hi 2 byte mi c th cung cp y thng tin thc thi. n gin, mt
lnh LDAA(Load Data to Accumulator A) chuyn mt hng s 8 bit vo thanh ghi A i hi t
nht 2 byte d liu hng 8 bit, v byte cn li cho lnh. iu ny c ngha l, khi thc hin lnh
ny, b nh b truy xut 2 ln. Ngoi vic km hiu qu v tc truy xut ra, cc t chc t
lnh 1, 2 hay 3 ca kiu kin trc ny lm cho vic thit k mt vi iu khin vi b nh va
phi hp yu cu kh khn hn.
Hnh 8: Quy trnh thc thi lnh LDAA

i vi PIC16F m chng ta ang dng, kin trc b nh c thit k l 14 bit c rng
bus b nh chng trnh, ph hp vi cc ng dng va phi. T lnh di nh vy s cha c
nhiu thng tin hn, thc thi mt cng vic ch vi mt t lnh, c ngha l ch cn truy
xut b nh 1 ln cho 1 lnh. Vi thit k ny th kch thc b nh s ti u hn so vi cc kch
thc b nh kiu khc.
Hnh 9: Thc thi mt cng vic ch vi mt t lnh

IV.THIT K PHN CNG CHO PIC
1.Mch nguyn l:
Cc chn ngun Vdd phi c cp ngun y , khng c b trng: Chip cng nhiu
tnh nng th lng Transistor cng ln, khi s lng Transistor trong chip tng ln, th di
ng cp ngun trong diesilicon cng tng ln, lm in tr tng gy ra mt cn i in p
cung cp trn cc vng ca chip. Hn na khi ng ni di th cm khng k sinh cng tng
theo lm p cung cp cho cc vng trn cng b st tc thi khi chip hot ng tn s cao.
Nhng hiu ng ny lm chip hot ng km n nh. Do chip a ra nhiu u cp ngun
lm gim cc hiu ng trn.
Phi c cc t decouling 0.1uF t gn cc chn cp ngun (khi v PCB phi t cng gn
cng tt): Mt d dng tiu th trung bnh c th nh nhng khi hot ng tn s cao, dng
in tc thi m chip cn ( np cc cng ca cc MOSFET) l rt ln. Do di/dt ln nn nh
hng ca in cm trn ng mch cng rt ln.
Ngoi ra cc n p tuyn tnh iu khng th cung cp c dng in ny cho chip. V
vy bn phi cn cc t in tch in tm thi trong chu k chip khng hot ng v x dng
cung cp cho chip trong chu k hot ng. Cc t in ny phi: ESR thp c kh nng x
dng ln. T gm (t bi) 0.1uF l ph hp. i khi c th mc song song thm 1 t 0.01uF tht
gn 2 chn ngun ca chip gim in cm, in tr ca ng mch. Khi lp cc t
decouling, trn cc ng cp ngun s c nhiu tn s cao do np v x cc t ny cng thm
nhiu t cc ngun khc v cn phi trit tiu. Nhng y l vn rt phc tp: S dng LDO
tt , dng tnh thp, nu phi xi 7805, vi mt loi ch cn c 1 con 0.1uF st ngay chn output
trnh b dao ng.
Tng kch thng ng ngun gim in cm.
t ri rc cc t 10uF(low ESR) trn cc ng cp ngun.
Nu phi dng cc ti cm nh relay, motor, v dng chung ngun, nn i 2 ng mch
Vss Vdd ring.
Dng diode schottky(1N5817, 1N5822) thay v cc loi nn dng (1N4001, 1N4007)
dp dng cm ng trong cc ti cm. C mt s linh kin gi l tranzorbs, sidactor dp cc
dng cm ng.
t thch anh st gn vi PIC: Khi thit k PCB, nn t thch anh gn vi PIC, nht l
khong cch t chn OSCI n chn thch anh phi cng ngn cng tt, dao ng i vo chn
ny, cng xa cng nhiu gy mt n nh cho PIC.
10

2.Chun ICSP(In-Circurt Serial Programming)
y l chun np trc tip cho vi iu khin PIC k c khi PIC c hn trn Board, gm
c 6 chn nh theo th t :
Hnh 10: V tr cc chn trong chun ICSP

Ch cn 5 chn t 1 n 5 l c th np c PIC, tuy nhin c thm chn s 6 phng
trng hp nu nh cm ngc, lc chn MCLR/Vpp s a vo chn NC, khi thit b np
chn Chip, n s nng in p chn MCLR/Vpp ln t 8-13V, nu chn MCLR/Vpp ni vo mt
I/O bt k, c th gy hng.
Bus np cho chun ICSP ny ta c th chn loi Bus c quy nh chiu cm th cng tt.
3.Cc tnh nng c bit, cc bit cu hnh ca PIC16F887:
PIC16F887 c mt loi cc tnh nng nhm ti a ha tin cy ca h thng, gim thiu
chi ph qua vic loi b cc linh kin bn ngoi, cc tnh nng bo v m, tit kim nng lng.
Nhng tnh nng l:
Reset
Power-on Reset (POR)
Power-up timer (PWRT)
Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Interrupts
Watchdog timer (WDT)
Oscillator selection
Sleep
Code protection
ID Locations
In-Circurt Serial Programming
Low-voltage In-Circurt Serial Progrmamming
11

Mt vi tnh nng trn s lun lun sn c, nhng mt vi tnh nng khc th cn phi cu
hnh trong lc np chng trnh cho PIC. Cu hnh l vic bt/tt cc bit trong thanh ghi cu
hnh CONFIG1 v CONFIG2 ca PIC, thanh ghi ny nm trong b nh chng trnh nn c
rng bng rng ca t lnh (14-bits) v c ghi bng b np (hay self-write). Cc tnh nng
cng l tnh nng cn thit PIC c th chy c , do trc khi lp trnh cn xc nh
PIC cn nhng tnh nng g tin hnh cu hnh cho n trc khi chy. C 2 cch thc hin
cng vic cu hnh ny, s dng t kha ch dn ca Hi-tech C a cc bit ny vo trong
code (file*.hex) v dng MPLAB cu hnh. Phn tip theo s trnh by v cc tnh nng ca
PIC v cch thc cu hnh bng Hi-Tech C, phn dng MPLAB s trnh by sau cng.
Trc khi thc hin cu hnh cc bit cu hnh cho PIC, cn tham kho datasheetsPIC
16F887, mc 14.0 special features of the CPU v file pic16f887.h trong th mc include ca
trnh bin dch Hi-Tech C (v d phin bn 9.65 Pro, th mc mc nh ny nm c:\program
Files\Hi-Tech\Software\PICC\PRO\9.65\include\pic16f887.h).
Khi mun t trc cc bit cu hnh vo trong chng trnh vit bng Hi-Tech C, t kha
trnh dch bit c t nhng ty chn vo m l __CONFIG (nh l c hai du gch
di).
__CONFIG (OPTION & OPTION2 & OPTION3 &);
__CONFIG (OPTION & OPTION2 & OPTION3 &);
.
Trong cc OPTION1,OPTION2 l nhng nh ngha nm trong file pic16f887.h ca
Hi-tech C, c cch nhau bng du &. T __CONFIG u tin cu hnh cho thanh ghi
CONFIG1,__CONFIG th 2 cu hnh cho thanh ghi CONFIG2
Mt chng trnh mu khi s dng cc bit cu hnh t trong chng trnh:
/////////////////////Cu hnh thanh ghi CONFIG1
XT: Dao ng thch anh bn ngoi, 4Mhz
WDTDIS: Tt chc nng watch-dog
PWRTEN: M tnh nng Power-up Timer
MCLREN: M tnh nng master clear t chn MCLR
UNPROTECH : khng bo v m
DUNPROTECH: Khng bo v d liu trong EEPROM
BORDIS: Khng s dng Brown-out reset
IESODIS: Khng s dng tnh nng Internal External Switchoer
FCMDIS: Khng s dng tnh nng Fail-Safe Clock Monitor
LVPDIS:Khng s dng tnh nng LVP.
/////////////////////Cu hnh thanh ghi CONFIG2
BORV40: Nu Brown-out Reset c cho php, th in p Vbor = 4V
Cho php PIC c ghi ln Flash ( khng xut hin WP0,WP1, WP2 ngha l cho
php tt c ).
12

Thanh ghi cu hnh CONFIG1:
DEBUG: tch cc mc thp, khi bit ny b xa(0), chip s hot ng ch g ri, chy
tng bc, truyn thng tin b nh v thit b g ri. Chn RB6/CLK v RB7/DAT hot ng
vi chc nng g ri. Ngc li, khi bit ny bt ln bng (1), chip khng thc hin tnh nng
Debug, thay vo RB6/CLK v RB7/DAT hot ng nh mt I/O thng thng. Ch l bit
ny c th xa hay bt bi MPLAB khi chn ch np hay g ri trn MPLAB, do vy trong
qu trnh lm vic khng nht thit quan tm n bit ny.
Trong Hi-tech C nh ngha Debug:
// In-Circuit Debugger Mode
#define DEBUGEN 0x1FFF
// Enable ICD2 debugging
#define DEBUGDIS 0x3FFF
// Disable ICD2 debugging
LVP (Low Voltage Programming): tnh nng lp trnh in p thp, ngha l np chip vi
in p lm vic ca n(5V), khi tnh nng ny c cho php (bit c bt(1)) , c th np chip
thng qua ICSP vi in p ngun ca n.Khi thc hin tnh nng ny, chn RB3/PGM phi
c ni ln Vdd, iu ny c ngha l khng th s dng RB3 nh mt I/O, n phc v cho tnh
nng LVP v chn MCPR/Vpp phi cp in p VDD. Ch : tnh nng lp trnh in p cao
lun c, vi tnh nng ny , PIC lun c c th np thng qua cng ICSP khi in p chn
MCLR/Vpp nng ln khong 13V (ty loi PIC, c loi ch c 8V).Thng thng tnh nng ny
t s dng v c tt tn dng chn RB3 nh I/O.
Trong Hi-Tech C nh ngha nh sau:
// Low Voltage Programming
#define LVPDIS
0x2FFF
// Disabled
#define LVPEN
0x3FFF
// Enabled
FCMEN (Fali safe Clock Monitor Enable ): Tnh nng ny cho php PIC tip tc hot
ng nu ngun dao ng bn ngoi b hng. FSCM c th dng vi cc ngun dao ng ngoi
nh: LP , XT, HS, EC, RC v RCIO (tham kho phn dao ng). Nguyn tc hot ng, xem
mch m t.
Hnh 11: S khi FSCM trong PIC16F887

13

FSCM pht hin s sai khc dao ng bng cch so snh dao ng bn ngoi vi dao ng
mu t ngun dao ng ni tn s thp (LFINTOSC) c chia 64. Nh hnh trn, bn trong
FSCM l mt SR Latch, c mi xung clock bn ngoi a vo s bc ng ra Q=1 v c khong
2ms, dao ng mu s xa ng ra Q=0; Dao ng bn ngoi hng s c pht hin ngay nu
trong hn mt na chu k ca dao ng mu, Q lun bng 0.
Hnh 12: Quy trnh hot ng khi FSCM

Khi dao ng bn ngoi b hng, FSCM s chuyn dao ng dng cho PIC t ngun dao
ng bn ngoi sang ngun dao ng ni, ng thi bt c OSFIF trong thanh ghi PIR2, s gy
ngt nu OSFIF trong thanh ghi PIE2 c cho php. Dao ng ni c dng cho ti khi no
ngun dao ng bn ngoi c phc hi v phn mm trong PIC chuyn sang dao ng ngoi.
Dao ng ni c FSCM chn phc thuc vo 3 bit IRCF<2:0> trong thanh ghi OSCCON,
ngha l FSCM cho php cu hnh dao ng ni trc khi FSCM nhn bit s hng hc ca dao
ng bn ngoi.
Khi phn mm PIC thay i ngun dao ng (dao ng ni v dao ng ngoi), tc l bt,
tt bit SCS, th coi nh FSCM khi ng li t u, lc ny bit OSFIF mi c php xa.Ngoi
ra, sau khi PIC khi ng t RESET hay SLEEP, FSCM cng khi ng.
nh ngha trong Hi-Tech C:
// Monitor Clock Fail-safe
#define FCMEN
0x3FFF
// Enabled
#define FCMDIS
0x37FF
// Disabled
IESO (Internal External Switch Over ): Bit ny dng cu hnh cho ch khi ng 2
tc (Two-speech Start up). y l tnh nng gip gim thiu nng lng tiu hao trn PIC do
qu trnh khi ng gy ra bng cch gim thiu tr dao ng bn ngoi v qu trnh thc thi
m.Vi nhng ng dng thng s sng nh SLEEP tit kin nng lng, TSS thc s hiu
qu khi m PIC i vo SLEEP v thc dy t SLEEP mt cch nhanh chng.TSS s s dng dao
ng ni trong qu trnh khi ng, ngay sau khi dao ng bn ngoi n nh, PIC s t chuyn
s dng dao ng bn ngoi.
14

Cc bc thc hin khi s dng TSS:
Cu hnh IESO=1, trong thanh ghi CONFIG1, cu hnh ny thc hin trong qu trnh np.
SCS=0 (trong thanh ghi OSCCON), chn ngun dao ng s dng l dao ng ni.
FOSC<2:0> phi chn dao ng chnh l dao ng bn ngoi (LP,XT hat HS).
nh ngha IESO trong Hi-Tech C:
// Internal External Switch Over Mode
#define IESOEN
0x3FFF
// Enabled
#define IESODIS
0x3BFF
// Disabled
BOREN<1:0> (Brown Out Reset Enable): y l tnh nng Reset ca PIC khi ip p nh hn
mt mc no c nh ngha (VBOR). Brown Out Reset hot ng nh sau:
Hnh 13: S tn hiu in p Brown out

Khi in p trn chn cp ngun (Vdd) nh hn in p VBOR, PIC s b Reset, qu trnh
ny gi khong 64ms k t ln cui cng b Brown Out. Cu hnh Brown out trong thanh ghi
CONFIG1 chia ra lm 4 ch :
BOREN<1:0> = 11:Brown out Reset c cho php, hot ng c khi PIC Sleep, in
p VBOR ph thuc vo BOR4V thanh ghi CONFIG2.
BOREN<1:0> = 10:Brown out Reset Ch hot ng khi PIC hot ng, v tt khi PIC
sleep .
BOREN<1:0> = 01:Brown out Reset ph thuc vo bit SBOREN trong thanh ghi
PCON, bit ny c th bt/tt bng phn mm trong PIC .
BOREN<1:0> = 0:Brown out Reset khng hot ng.
15

nh ngha Brown Out Reset trong Hi tech C:
// Brown Out Detect
#define BORDIS
0x3CFF
#define SWBOREN
0x3DFF
(Software control)
#define BORXSLP
0x3EFF
sleep, SBOREN disabled
#define BOREN
0x3FFF
// BOD and SBOREN disabled

// SBOREN controls BOR function
// BOD enabled in run, disabled in
// BOD Enabled, SBOREN Disabled
CPD (Code Protect Data): Bit ny tch cc mc thp, khi cu hnh bng 0, cho php bo v
d liu trong EEPROM, s khng th c li d liu EEPROM t PIC bng bt c chng trnh
vi s h tr ca thit b np no.
nh ngha tring Hi tech C:
// Data EE Read Protect
#define DUNPROTECT
0x3FFF
// Do not read protect EEPROM data
#define CPD
0x3F7F
// Read protect EEPROM data
CP(Code Protect): Bo v ton b b nh chng trnh, tch cc mc thp, khi c xa
bng 0, khng th c li ni dung t b nh chng trnh ca PIC.Ch : trong qu trnh g ri
(Debug), CP khng cho php, MPLAB s cnh bo v yu cu nu c tnh cho php CP (CP=0)
trong qu trnh g ri.
// Code Protect
#define UNPROTECT
0x3FFF
// Code is not protected
#define CP
0x3FBF
// Code is protected
#define PROTECT
CP
//alternate
MCLRE(Master Clear Enable): y l tnh nng cho php PIC c th b reset bng chn
MCLR. Khi bit MCLRE(tch cc mc thp) c cho php (b xa bng 0), th chn Master
Clear c th reset PIC khi c cp mc 0, v khi PIC hot ng, phi cp mc logic1. Mch
in trn chn MCLR nn dng nh hnh :
Hnh 14: Kt ni phn cng khi s dng ch Master clear

16

Khi bit MCLRE khng c cho php (bng 1), th chn MCLR khng c tnh nng reset
PIC, lc ny chn MCLR/RA3 ch hot ng nh mt ng vo.
nh ngha trong Hi-Tech C:
// Master Clear Enable
#define MCLREN
0x3FFF
// MCLR function is enabled
#define MCLRDIS
0x3FDF
// MCLR functions as IO
PWRTEN(Power up Timer Enable): Tnh nng ny cho php gi PIC reset trong khong
64ms t khi cp ngun, hay b reset bi Brown out. Bit ny tch cc mc thp.
// Power Up Timer
#define PWRTDIS
0x3FFF
// Off
#define PWRTEN
0x3FEF
// On
WDTE (Watchdog Timer Enable): Tch cc mc cao khi c cho php, Timer Watchdog
s chy, v s gy reset chip mi khi trn. Nu khng c cho php th WDT s b tt, ng
thi c iu khin bng phn mm trong PIC thng qua thanh ghi WDTCON
Hnh 15: Khi Watch dog timer trong Vi iu khin

S lc v tnh nng Watchdog: Watchdog timer l mt timer c ngun dao ng RC
31Khz c lp vi dao ng ca PIC, c th coi y l m timer c th cu hnh c gi tr n
m, (m 32xung trn (5 bit) hay m 65536 xung trn(16 bit) ), khi WDT Timer trn s
Reset PIC. Nu s dng WDT, trong mt khong thi gian nht nh, nh hn thi gian trn ca
WDT Timer th phi xa b m ca WDT v 0, u ny hu ch khi PIC b treo v khng th
xa b m ca WDT Timer.
17

Ch : Khi dng Watchdog Timer, th cn cu hnh thi gian cn thit WDT trn, vic
cu hnh bng phn mm trong PIC, tc ng ln cc bit WDTPS<3:0> trong thanh ghi
WDTCON.
nh ngha trong Hi Tech C:
// Watchdog Timer
#define WDTEN
0x3FFF
// On
#define WDTDIS
0x3FF7
// Disabled / SWDTEN control
FOSC<2:0> (Oscliiator Selection): Chn ch dao ng chnh ca PIC, 3 bit FOSC<2:0>
c th la chn c 8 ch . Khi la chn ch dao ng, cn phi tm hiu cc ch dao
ng ca: PIC hot ng nh th no.
Hnh 16: S khi dao ng bn trong vi iu khin

FOSC<2:0>=000:ch dao ng dng thch anh LP(Low power), 2 chn OSC1 v
OSC2 c ni vi thch anh tn s thp (32Khz).
FOSC<2:0>=001:ch dao ng dng thch anh vi li trung bnh XT, s dng hai
chn OSC1 v OSC2 ni vi thch anh c tn s nh hn 10Mhz.
FOSC<2:0>=010:ch dao ng dng thch anh vi li cao HS, s dng 2 chn
OSC1 v OSC2 ni vi thch anh c tn s ln hn 10 Mhz.
18
Hnh 17: S s dng thch anh ngoi, tn s cao

FOSC<2:0>=011:ch dao ng t ngun xung clock bn ngoi EC(External
Clock).Chn RA6/OSC2/CLKOUT hot ng nh mt I/O thng thng, clock a vo chn
RA7/OSC1.CLKIN.
Hnh 18: Ch s dng clock ngoi vi mt chn clock

FOSC<2:0>=100: Ch dao ng ni INTOSCIO, lc ny dao ng c ly t ngun
dao ng bn trong PIC, tn s dao ng ph thuc vo cc bit IRCF<2:0> trong thanh ghi
OSCCON, mc nh cc bit IRCF<2:0> cu hnh dao ng ni l 4Mhz khi Reset.Chn
RA6/OSC2/CLKOUT v RA7/OSCI/CLKIN hot ng nh I/O thng thng.
FOSC<2:0>=101:Ch dao ng ni INTOSC, tng t nh INTOSCIO, nhng chn
RA6/OSC2/CLKOUT xut xung clock ta ngoi vi tn s bng tn s chn chia 4.
FOSC<2:0>=110:Ch dao ng dng t in tr bn ngoi RCIO, dao ng s c
a vo chn RA7/OAC1/CLKI, v chn RA6/OSC2/CLKOUT hot ng nh mt I/O thng
thng.
Hnh 18: Dao ng dng t v in tr

19

FOSC<2:0>=111:Ch RC, ging nh RCIO, tuy nhin RA6/OSC2/CLKOUT xut
xung clock bng xung a vo chia 4.
i vi phn dao ng, ch n bit SCS trong thanh ghi OSCCON, bit ny c th thay
i bng phn mm trong PIC, mc nh SCS = 0. Khi SCS bng 0, PIC s chy bng dao ng
nh ngha bi FOSC<2:0> trong thanh ghi CONFIG1 nh bn trn, khi SCS bng 1, dao
ng c s dng l dao ng ni, v tn s c quyt nh bi IRCF<2:0> trong thanh ghi
OSCCON. Ngoi ra vic cn chnh cho dao ng ni chnh xc th s dng thanh ghi
OSCTUNE.
nh ngha trong Hi TechC:
// Oscillator
#define EXTCLK
0x3FFF
// External RC Clockout
#define EXTIO
0x3FFE
// External RC No Clock
#define INTCLK
0x3FFD
// Internal RC Clockout
#define INTIO
0x3FFC
// Internal RC No Clock
#define EC
0x3FFB
// EC
#define HS
0x3FFA
// HS
#define XT
0x3FF9
// XT
#define LP
0x3FF8
// LP
20
CHNG II: XUT NHP I/O PORT

I.MC CH TH NGHIM :
Kin thc sinh vin cn t c sau khi thc tp:
Lit k cc thanh ghi lin quan n vic x l tn hiu s cc chn vi iu khin .
Khi to cc chn ca vi iu khin l ng ra , vo s .
Gii thch c cng dng ca hm _delay(n) , cch dng hm delay chng di cho
nt nhn.
Lp trnh iu khin led theo yu cu .
Gii thch u khuyt im ca ngt .
II.DNG C TH NGHIM :
Kt th nghim + cp USB.
My tnh .
Ngun 12V/1A.
III.C S L THUYT :
1.Thanh ghi qui nh tn hiu x l chn vi iu khin l tn hiu s hay tn hiu tng
t:
Hnh 19: Cc chn c th x l tn hiu s
Hnh 20: Cc chn c th x l tn hiu tng t
Nhng chn c k hiu ANX l nhng chn va c th x l tn hiu s va c th x l tn

hiu tng t . Do khi lm vic vi nhng chn ny ta cn ch n hai thanh ghi :
21
Hai thanh ghi ny c tng cng 14bit t ANS0 n ANS13 , s quy nh tn hiu lm vic
ca cc chn t AN0 n AN13 l tn hiu s hay tn hiu analog .
ANSX=0 : Cho php chn ANX x l tn hiu s .
ANSX=1 : Cho php chn ANX x l tn hiu tng t .
Trong : X= 0 13
2.Chc nng ca thanh ghi TRIS :
Trong cc chn x l tn hiu s , hot ng ca chn c th l ng ra (lm cho led chp tt,
kch transistor , iu khin hot ng IC....) , hay c th l ng vo (c trng thi nt nhn , c
encoder , c tn hiu t cm bin s....). Nh vy , khi to cho cc chn l ng ra hay ng
vo tn hiu s , chng ta cn ch n thanh ghi TRISX (X=A,B,C,D,E):
TRISXY=0:Quy nh bit th Y ca PORTX l ng ra (0 = Output)

TRISXY=1:Quy nh bit th Y ca PORTX l ng vo (1=Input)
(Trong :X=A,B,C,D,E ; Y=0-7)
Ch : PORTE ch c 4 bit thp : TRISE0, TRISE1, TRISE2 ,TRISE3.
3. Chc nng ca thanh ghi PORT :
Trong trng hp x l tn hiu s v l ng ra , th c th l ng ra mc cao (in p chn
l VH) , hay ng ra l mc thp (in p l VL) s do bit RXY ca thanh ghi PORTX quy
nh .
RXY=0 : Quy nh chn th Y ca PORTX l mc thp(VL).

22

RXY=1: Quy nh chn th Y ca PORTX l mc cao(VH).
(Trong : X=A,B,C,D,E ; Y=0-7)
Tm li ta c bng tm tt sau :
ANSX
0
0
0
0
1
TRISXY
0
0
1
1
1
RXY
0
1
0
1
x
Kt qu
Ng ra mc thp(0V)
Ng ra mc cao(+5V)
Tng tr cao (R=)
Ng vo , tc ng mc thp
X l tn hiu tng t .
Hnh 21: ng dng x l tn hiu s

4.Nhng thanh ghi c bit ch c ring PORTB:
4.1.Thanh ghi h tr in tr treo bn trong:
trnh trng thi th ni (tn hiu in p chn khng r rng) khi khi to PORTB l
ng vo s , PIC16f887 tch hp thm vo cho PORTB cc in tr ko ln (pull-up), s dng
cc in tr ny ta ch n thanh ghi :
WPUBy=0: Khng cho php in tr ko ln chn th y ca PORTB.

WPUBy=1: Cho php in tr ko ln chn th y ca PORTB.
Khi s dng in tr ko ln ngoi vic s dng thanh ghi WPUB cn phi khi to bit:
RBPU
23

in tr ko ln nn khi to khi PORTB l ng vo s , cc PORT khc khng c h
tr in tr treo trong , do nu c nhu cu s dng ta c th mc thm in tr bn
ngoi.
4.2.Ngt ngoi chn RB0:
x l c cc tn hiu tc ng tc thi (cnh ln hay cnh xung), chn RB0 c h tr
x l ngt (interrupt ) k hiu chn l INT, khi to ngt ngoi chn RB0 ta cn ch n
cc bit sau :
INTE(Interrupt enable ) : bit cho php ngt PORTB
INTF(Interrupt flag): c ngt , bit ny t ng bng 1 khi c s kin ngt (cnh ln hay
cnh xung) xy ra chn RB0, ta phi xa bt ny trong khi lp trnh .
GIE(Global interrupt ) : bit cho php ngt ton cc.
INTEDG (interrupt edge select bit ) : Bit chn cnh tc ng sinh ra s kin ngt
RB0.
INTEDG=1: Xy ra ngt khi c tn hiu cnh ln RB0
INTEDG=0: Xy ra ngt khi c tn hiu cnh xung RB0
Hnh 22: S ngt INT chn RB0

Cc bc khi to ngt INT:
Bc 1 : Khi to chn RB0 l ng vo s , in tr treo.
Bc 2 : Khi to ngt INT
INTE=1;
//Cho php ngt hot ng
INTF=0;
//Xa c ngt th ngt ln tip theo mi c th xy ra.
INTEDG=....;
//Chn cnh tc ng ngt.
GIE=1;
//Cho php ngt ton cc .
4.3.Ngt on-change PORTB:
Ngoi ngt INT ch c duy nht chn RB0 , th c PORTB (t RB0 n RB7) cn h tr
ngt on-change , ngt on-change xy ra khi tn hiu logic chn ca PORTB thay i trng thi
logic.
24

S ngt on-change:
Hnh 23: S ngt on-change PORTB

Cc thanh ghi v cc bit iu khin ngt on-change :
IOCBX=0 : Khng cho php ngt on-change chn th X ca PORTB.

IOCBX=1 : Cho php ngt on-change chn th X ca PORTB.
Cc bit khi to khc :
RBIF : C ngt on-change PORTB, cn phi xa bt ny trong lp trnh.
RBIE : Bit cho php ngt on-change ca PORTB.
GIE : Bit cho php ngt ton cc.
Cc bc khi to ngt on-change :
Bc 1 : Khi to PORTB l ng vo s , c in tr treo.
Bc 2 : Khi to ngt on-change PORTB
IOCB=0xFF;
//khi to ton b PORTB ngt on-change(c th khi to
mt hay c PORTB).
RBIE=1;
//Cho php ngt xy ra .
RBIF=0;
//Xa c ngt
GIE=1;
//Cho php ngt ton cc
Ch : i vi ngt on-change , vic xa c ngt (RBIF=0) khng cho ln ngt
tip theo c thc hin , m cn phi thm iu kin c hoc vit vo thanh ghi PORTB.
25

V d :
unsigned char bien ;
bien = PORTB ;
hoc PORTB = 5 ;
//c thanh ghi PORTB.

//vit vo thanh ghi PORTB
4.4.Bng so snh gia ngt INT v ngt on-change :

Ngt chn INT(RB0)
Ch c duy nht chn RB0
xy ra ngt th tn hiu logic l cnh ln
hoc cnh xung.
Cc bit khi to :
INTE , INTF , INTEDG , GIE
cho ln ngt tip theo c thc hin th
cn phi xa c ngt INTF.
Ngt on-change
Xy ra trn c PORTB
Ch cn tn hiu logic thay i l xy ra ngt,
khng phn bit cnh ln hay cnh xung.
Cc bit khi to :
IOCBx , RBIE , RBIF , GIE
cho ln ngt tip theo c thc hin th
cn phi xa c ngt INTF v c ( hoc ghi)
vo thanh ghi PORTB.
IV.BI TP THC HNH :

Bi 1: Vit chng trnh iu khin led theo yu cu sau :
Nhn (khng gi) nt nhn ni vi chn RB0 : led RE1 v led RE2 chp tt xen k trong
thi gian T=0.2(s).
Nhn (khng gi) nt nhn ni vi chn RB1 : led RE1 v led RE2 cng chp tt trong
thi gian T=0.5(s).
Nhn (khng gi) nt nhn ni vi chn RB2 : led RE1 sng v led RE2 tt trong thi
gian T=0.1(s) , led RE1 tat v LED2 sng T=0.7(s).
S dng nh thi bng hm _delay(n) ; thch anh Fosc = 4 Mhz.
S phn cng :
26

*Bc 1: To mt project mi vi tn 01_01_MSSV .
*Bc 2: Nhp chng trnh sau vo my tnh v hon thnh cc du .
#include<htc.h>
__CONFIG(INTIO&WDTDIS&PWRTEN&MCLREN&UNPROTECT&DUNPROTECT&BO
RDIS&IESODIS&LVPDIS&FCMDIS);
void delay(unsigned char counter);
//Khai bo chng trnh con hm delay
void RB_0( );void RB_1( );void RB_2( );
char so_lan_nhan;
void main( )
//Chng trnh chnh
{
//Disable analog cc chn RE1,RE2,RB0,RB1,RB2
ANS6=ANS7=ANS12=ANS10=ANS8= .;
//Khi to cc chn RE1,RE2 l ng ra , ban u led tt
TRISE1=TRISE2= .; RE1=RE2= . ;
//Khi to chn RB0,RB1,RB2 l ng vo, tc ng mc thp
TRISB0=TRISB1=TRISB2= .; RB0=RB1=RB2= .;
//Khi to in tr ko ln cc chn RB0,RB1,RB2
WPUB0=WPUB1=WPUB2= .; RBPU= . ;
//(-------------1------------)
while(1)
{
//Xc nh trng thi cc nt nhn
if(!RB0)so_lan_nhan=0;
//(------------2-----------)
else if(!RB1)so_lan_nhan=1;
//(------------3-----------)
else if(!RB2)so_lan_nhan=2;
//(------------4-----------)
//Hin th led
if (so_lan_nhan==0)
else if(so_lan_nhan==1)
else if(so_lan_nhan==2)
RB_0( );//Chy chng trnh con RB_0

RB_1( ); //Chy chng trnh con RB_1
RB_2( ); //Chy chng trnh con RB_2
}
}
//(-------------5-----------)
void delay(unsigned char counter) //Chng trnh con lm tng thi gian delay
{
unsigned char value=0;
while(counter>value)
{
value++;
_delay(100000);
//tr 1ms vi Fosc = 4MHz
}
}
void RB_0( )
{
RE1^=1;RE2= .RE1;
// led RE1 v led RE2 chp tt xen k
27

delay(2);
//delay 0.2s
}
void RB_1( )
{
RE1^=1;RE2 .RE1;
// led RE1 v led RE2 cng chp tt
delay(5);
//delay 0.5s
}
void RB_2( )
{
RE1= .;RE2= .;
// led RE1 sng v led RE2 tt
delay(1);
//delay 0.1s
RE1= .;RE2= .;
// led RE1 tat v LED2 sng
delay(7);
//delay 0.7s
}
*Bc 3: Bin dch chng trnh, np xung kt th nghim , tin hnh nhn cc nt nhn v
quan st 2 led.
*Bc 4: Thay i chng trnh nh sau:
Thm vo dng : (-------------1------------) on code sau:
IOCB0=IOCB1=IOCB2=1;
//Cho php ngt onchange chn B0,B1,B2
RBIE=1;
//Cho php ngt onchange ton PORTB
RBIF=0;
//Reset c ngt
PEIE=1;
//Cho php ngt ngoi vi
GIE=1;
Xa cc dng 2,3,4.
Thm vo dng: (-------------5-----------) on code sau:
void interrupt isr( )
//Chng trnh con x l tt c ngt
{
if(RBIE&&RBIF)
//Chng trnh con cho ngt on-change
{
if(!RB0)
so_lan_nhan=0;
//nhn RB0
else if(!RB1) so_lan_nhan=1;
//nhn RB1
else if(!RB2) so_lan_nhan=2;
//nhn RB2
RBIF=0;
//Reset c ngt
}
}
*Bc 5: Bin dch chng trnh, np xung kt th nghim , tin hnh nhn cc nt nhn v
quan st 2 led.
*Bc 6: Nhn xt s khc nhau v tc p ng khi nhn nt nhn trc v sau khi sa code,
gii thch, rt ra kt lun:
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------28

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 2 : Vit chng trnh iu khin led theo yu cu sau :
Nhn (khng gi) nt nhn ni vi chn RB0 ln (2n+1) : 8 led dch t tri qua phi.
Nhn (khng gi) nt nhn ni vi chn RB0 ln (2n) : 8 led dch t phi qua tri.
n = 0,1,3,4,5k
S dng nh thi bng hm _delay(n) ; thch anh Fosc = 4 Mhz.
S phn cng :
*Bc 1: To mt project mi vi tn 01_02_MSSV.

*Bc 2 : Nhp chng trnh sau vo my tnh v hon thnh vo du .
#include<htc.h>
char count=0;
void display(char number);
void main( )
{
29

char i=0;
//Disable analog cc chn RE1,RE2,RB0,RB3,RB4,RB5
ANS6=ANS7=ANS9=ANS11=ANS12=ANS13=.;
//Khi to RE1 , RE2 l ng ra , trng thi ban u led tt
TRISE1=TRISE2=.; RE1=RE2=.;
//Khi to RB0 l ng vo , tc ng mc thp
TRISB0=.; RB0=.;
//Cho php in tr ko ln chn RB0;
IOCB0=.; RBPU=.;
//Khi to ngt ngoi chn RB0 .
INTEDG=..........; //cnh ln
INTE =.;
INTF =.;
GIE =.;
while(1)
{
while(count==1)
//Chng trnh dch t tri qua phi.
{
i++;
if(i>=9)
i=1;
display(i);
_delay(100000);
}
while(count==2)
//Chng trnh dch t phi qua tri.
{
i--;
if(i<=0)
i=9;
display(i);
_delay(100000);
}
}
}
{
if(INTE&&INTF)
{
count++;
if(count.3)count=1;
INTF=.;
}
}
void display(char number) //Chng trnh con hin th led khi nhn vo mt s tng ng
30

{
RE1=RE2=.;
//Tt led RE1, RE2
TRISB |= 0b00111000;
RB3=RB4=RB5=.;
//Khi to chn RB3 , RB4 , RB5 l tng tr cao
switch(number)
{
case 1:
RE2=.; //RE2 sng
break;
case 2:
RE1=.; //RE1 sng
break;
case 3:
//led D6 sng
TRISB3=0;RB3=.;TRISB4=.;RB4=0;
break;
case 4:
//led D7 sng
TRISB3=.;RB3=0;TRISB4=.;RB4=1;
break;
case 5:
//led D8 sng
break;
case 6:
//led D9 sng
break;
case 7:
//led D10 sng
TRISB5=0;RB5=.;TRISB3=0;RB3=.;
break;
case 8:
//led D11 sng
TRISB5=0;RB5=.;TRISB3=0;RB3=.;
break;
}
}
*Bc 3: Bin dch chng trnh , np xung kt th nghim , tin hnh nhn nt nhn v quan
st cc led.
*Bc 4:Tr li cu hi :
ra cc phng php x l khi ng vo tc ng mc cao :
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
31

V.BI TP T GII :
Bi 3.Vit chng trnh c gi tr phm v hin th gi tr ln led 7 on theo s phn
cng sau : (To mt project mi vi tn 01_03_MSSV)
(Phm t 0-9 , led hin th s tng ng , phm * th hin ch S, phm # th hin ch
H, lc khng nhn th hin ch U ).
Bi 4.Vit chng trnh theo yu cu sau , 16 led kt ni vi PORTD, PORTC (tc ng

mc cao) , 8 nt nhn kt ni vi PORTB : (To mt project mi vi tn 01_04_MSSV)
Nhn nt RB0 :16 led dch t phi qua tri.
Nhn nt RB1:16 led dch t tri qua phi.
Nhn nt RB2:16 led chp tt xen k.
Nhn nt RB3:16 led sng dn t tri qua phi .
Nhn nt RB4 :16 led sng dn t phi qua tri.
Nhn nt RB5:16 led sng dn t trong ra ngoi.
Nhn nt RB6:16 led sng dn t ngoi vo trong .
Nhn nt RB7:16 led cng chp tt.
Bi 5.Vit chng trnh m s ln nhn nt (RB0) v hin th t 000 n 255 ln 3 led by
on theo s phn cng sau : (To mt project mi vi tn 01_05_MSSV)
32
CHNG III: ADC MODULE

I.MC CH TH NGHIM :
Kin thc sinh vin cn t c sau khi thc tp :
Gii thch c khi nim v chc nng ca in p tham chiu.
Thit lp c in p tham chiu trong v ngoi cho khi ADC ca vi iu khin.
Lit k c cc bc thit lp o ADC cho mt hoc nhiu knh.
Thit lp c cng thc tnh ADC 8-bit , v ADC 10-bit ch nh dng canh tri v
canh phi .
Tn ton c gi tr tn hiu tng t thu c thng qua gi tr ca thanh ghi ADRESL,
ADRESH.
Thit lp v khi to c mt project c lin quan LCD , thay i file LCD.h ph hp
vi cu hnh phn cng bn ngoi .
II.DNG C TH NGHIM:
Vt (vn bin tr).
My tnh .
Ngun 12V/1A.
III.C S L THUYT :
1.Tn hiu tng t v tn hiu s :
Tn hiu tng t
Tn hiu s
Hnh 24: th tn hiu tng t v tn hiu s

Trong thc t , tn hiu cn x l xung quanh ta l tn hiu tng t , v d : vn tc , nhit
, m , cng nh sng , p sut v.v...Tuy nhin vi x l ch c th lm vic vi tn hiu
s (ch c hai trng thi 0 v 1) do x l c cc tn hiu tng t , th vi iu khin cn
phi c b chuyn i tn hiu tng t sang s ADC (Analog to Digital Converter).
33
Hnh 25: B ADC c tch hp bn trong vi iu khin

Tn hiu s
255
VREF-
VREF+
Tn hiu tng t
Hnh 26: th ca b chuyn i ADC 8-bit:

phn gii (Resolution) : T s trn ta thy b chuyn i ADC c phn gii 8bit th s c 256 gi tr dng cha cc gi tr in p t VREF- n VREF+ , nh vy nu b
chuyn i ADC c phn gii n bit th s c 2n gi tr . phn gii c lin quan mt thit
n cht lng chuyn i ADC , phn gii cng cao th kt qu chuyn i cng chnh xc .
in p tham chiu (Reference voltage) : in p tham chiu l in p dng so snh
vi tn hiu in p analog cn o , VREF+ nn chn bng vi mc in p ln nht cn o ,
khng nn chn nh hn hay ln hn .
2.ADC ca vi iu khin PIC16F887:
2.1Cc chn vi iu khin c kh nng x l tn hiu analog :
34
Hnh 27: Cc chn c th lm vic vi tn hiu analog
Hnh 28: S khi b ADC trong vi iu khin PIC16F887.

2.2Cc thanh ghi iu khin hot ng chuyn i ca b ADC :
ADON : Bit cho php b ADC hot ng

ADON=1 : Cho php b ADC hot ng
ADON=0 : Khng cho php hot ng
GO/: Bit ch trng thi chuyn i , bit ny t ng bng 0 khi b ADC chuyn i xong,
mun cho ln chuyn i tip theo c thc hin , cn phi t bit ny ln bng 1 trong lp
trnh .
35

CHS<3:0>: Dng chn knh cn chuyn i .
ADCS<1:0> : Bit la chn tn s chuyn i .
VCFG1 : Dng chn in p tham chiu VREF- .

VCFG1=1: khi VREF-= in p chn s 4 (VREF-)
VCFG1=0: khi VREF- = Vss
VCFG0 : Dng chn in p tham chiu VREF+.
VCFG0=1: khi VREF+= in p chn s 5 (VREF+)
VCFG0=0: khi VREF+= VDD
ADFM : bit dng la chn kiu nh dng kt qu chuyn i :
Sau khi chuyn i hon tt , kt qu s c lu theo mt trong hai kiu

36
Hai thanh ghi ADRESH v ADRESL l hai thanh ghi dng cha kt qu khi b ADC
chuyn i hon tt , b ADC ca vi iu khin PIC16F887 c phn gii 10-bit do cn hai
byte cha kt qu, tuy nhin kt qu c th lu theo hai kiu : canh tri (ADFM=0) v canh
phi (ADFM=1).
i vi nh dng kt qu bn tri : ADFM=0 th ta c th c kt qu nh sau :
phn gii 10-bit :
Kt qu = ADRESH*4+ADRESL >> 6
(1)
phn gii 8-bit :
Kt qu = ADRESH
(2)
i vi nh dng kt qu bn phi : ADFM=1 th ta c th c kt qu nh sau :
phn gii 10-bit :
Kt qu = ADRESH*256+ADRESL
(3)
phn gii 8-bit :
Kt qu = ADRESH*64+ADRESL>>2
(4)
R rng ta thy biu thc (1) v (4) gy kh khn trong vic lp trnh v thi gian cn tn
ton lu hn , do ta rt ra kt lun:
Khi cn c ADC 8-bit th cn nh dng kt qu bn tri(ADFM=0)
Khi cn c ADC 10-bit th cn nh dng kt qu bn phi(ADFM=1)
2.3 Ngt ADC :
Khi ADC cng c th to ra s kin ngt (ngt trong) , s kin ngt xy ra khi b ADC
chuyn i hon tt .
Hnh 29: S khi to ngt ADC

ADIE : Bit cho php b chuyn i ADC.
ADIF : C ngt ADC , bit ny t ng bng 1 khi b ADC chuyn i hon tt , cho
ln chuyn i tip theo c thc hin , chng ta cn phi xa bt ny bng phm mm lp
trnh.
PEIE : Bit cho php ngt ngoi vi .
GIE : Bit cho php ngt ton cc.
2.4 Cc bc khi to b chuyn i ADC:
Bc 1:Chn tn hiu x l
Khi to chn l ng vo:
TRISxy=1;
//x:A,B,E , y:0-7
Khi to chn x l tn hiu tng t : ANSx=1;
//Trong : x=0-13
Bc 2:Khi to khi ADC
Chn tn s chuyn i
ADCS1=.........;ADCS0=........;
37
Chn in p tham chiu

VCFG1=......; VCFG0=.........;
Chn knh cn o .
CHS3=....;CHS2=.....;CHS1=.....;CHS0=.....;
Chn nh dng kt qu
ADFM=......;
Cho php module ADC
ADON=1;
Bc 3: Khi to ngt ADC(c th b qua bc ny nu khng s dng ngt):
Xa c ngt:
ADIF=0;
Cho php ngt ADC:
ADIE=1;
Cho php ngt ngoi vi:
PEIE=1;
Cho php ngt ton cc :
GIE=1;
Bc 4:Ch thi gian khi to.
Bc 5:Bt u cho php chuyn i .
GODONE=1;
Bc 6:Ch cho b ADC chuyn i hon tt bng cc du hiu sau :
Bit GODONE t ng xung 0 , ta c th s dng code sau thc hin vic ch:
while(GODONE) ;
Ngt ADC xy ra.(Nu bc 3 c thc hin)
Bc 7 : c kt qu
ADC 8-bit :
kt qu = ADRESH
//canh tri
ADC 10-bit :
kt qu = ADRESH*64+ADRESL //canh phi
Bc 8:Xa c ngt cho ln chuyn i tip theo (Nu bc 3 c thc hin)
ADIF=0;
3.Lm vic vi LCD 16x2 :

vi iu khin PIC16F887 giao tip c vi LCD i hi trong code chng trnh cn
phi c nhng dng lnh ph hp lcd , thng nhng yu cu lnh ny c quy nh bi chip
x l bn trong lcd , do chng trnh ngn gn v n gin , ta thng xy dng file lcd.c
v lcd.h l nhng file cha sn nhng chng trnh con c nhng cu lnh giao tip vi lcd , ta
ch cn khai bo hai file lcd.c v lcd.h th c th d dng giao tip vi lcd bng nhng cu lnh
bn trong file . Cc bc khi to v lm vic vi LCD :
Bc 1 : Kim tra phn cng , phi ph hp vi nhng khai bo trong file LCD.h
Bc 2 : Copy 2 file LCD.c v LCD.h vo th mc ca project ang lp trnh .
Bc 3 : Add hai file trn vo Header file v Source file .
Bc 4 : Ti thiu cn phi khai bo 2 dng lnh sau (t en) trong chng trnh khi c
lin quan ti file LCD:
38

#include<htc.h>
__CONFIG(.);
#include lcd.h
void main( )
{
lcd_init( );
//khai bo th vin hm lcd.h
//lnh khi to lcd
//Cc lnh c s dng cho lcd c th tham kho trong file LCD.c v d :
lcd_gotoxy(x,y); //Lnh ny dng di chuyn con tr i n cc v tr trn mn hnh lcd,
trong x l gi tr ca hng ngang (x=[0,1]) , y l gi tr ca hng dc(y=[0,15]).
lcd_putc(k t cn in); //Lnh ny dng in k t ln mn hnh lcd ti v tr con tr .
lcd_puts(chui cn in); //Lnh ny dng in chui ln mn hnh lcd ti v tr con tr ,
ch chui cn in nm gia hai du v k t cn in nm gia hai du .
lcd_putc(\f) ; //xa mn hnh lcd , sau con tr tr v v tr (0,0).
while(1)
{
}
}
*Ngoi ra cn c th s dng hm printf nhng cn khai bo nh sau :
#include<htc.h>
#include<stdio.h> //khai bo th vin cho hm printf
__CONFIG(.);
#include lcd.h
//khai bo th vin hm lcd.h
void main( )
{
lcd_init( );
//lnh khi to lcd
printf(In gia tri :%3d , bien2);
printf(In gia tri :%5.3d , bien2);
//Hin th chui In gia tri : 6

//Hin th chui In gia tri :006
printf(In gia tri :%f , bien1);

printf(In gia tri :%3.2f , bien1);
//Hin th chui In gia tri :19.6666

//Hin th chui In gia tri : 19.67
printf(In gia tri :%d , bien3);

printf(In gia tri :%ld , bien3);
//Hin th chui In gia tri :-5536

39
char bien2=6;
float bien1=19.66667 ;
unsigned int bien3=60000;
printf(In ra man hinh );
printf(In ra \n man hinh );
while(1); printf(In gia tri :%03d , bien2);
printf(In gia tri :%5.3d , bien2);
//Hin th chui In ra man hinh

//Hin th chui In ra
man hinh
}
//Hin th chui In gia tri :19.6666
void putch(charprintf(In
ki_tu) gia tri :%f , bien1);
printf(In gia tri :%3.2f , bien1);
//Hin th chui In gia tri : 19.67
{
lcd_putc(ki_tu);
//Hin th chui In gia tri :-5536
}
printf(In
gia
tri
:%ld
,
bien3);
th cng
chuithc
In gia
tri :60000
Ch : Khi vit chng trnh c lin quan lcd//Hin
m phn
t khng
c lcd hay
lcd kt ni khng ng vi th vin lcd.h th con tr chng trnh s dng ngay lnh lcd_init();
IV.BI TP THC HNH :
Bi 1: Vit chng trnh c ADC 8 bit chn AN3 v thc hin theo yu cu sau :
Hin th gi tr thanh ghi ANSEL hng (0,0) ca LCD.
Hin th gi tr in p chn AN3 hng (0,1) ca LCD.
nh thi bng hm delay , in p tham chiu trong , Fosc = 4Mhz , giao tip LCD
bng th vin LCD.h
S phn cng :
*Bc 1 : To mt project mi vi tn 02_01_ MSSV

*Bc 2: Nhp chng trnh sau vo my tnh v hon thnh vo du .
#include<htc.h>
#include<stdio.h> //th vin cho hm printf( );
40

#include"lcd.h";
void main( )
{
lcd_init( );
//Khi to LCD
ANS3=.;
//Enable analog chn RA3
TRISA3=.;RA3=.;
//Khi to RA3 l ng vo
VCFG0=VCFG1=.;
//Chn in p tham chiu trong
CHS3=CHS2=.;CHS1=CHS0=.; //Chn knh o l AN3
ADFM=.;
//nh dng d liu canh tri , bi v ch s dng ADC 8 bit
ADCS0=ADCS1=.;
//Tn s chuyn i
ADON=.;
//Enable module ADC hot ng
while(1)
{
GODONE=.;
//Cho php ADC bt u chuyn i
while(GODONE) .
//Ch b ADC chuyn i xong
lcd_gotoxy(0,0);
printf("\fADRESH :%d",ADRESH);
lcd_gotoxy(0,1);
printf("Dien ap :%3.2f",ADRESH*5.0/255.0);
_delay(100000);
}
}
void putch(char c)
//H tr cho hm printf in ra LCD
{
lcd_putc(c);
}
*Bc 3: Bin dch chng trnh , np xung kt th nghim , jum header 3 v tr POT , dng
vt vn bin tr v quan st kt qu trn LCD.
*Bc 4:Thit lp cng thc quan h gia in p v gi tr thanh ghi ADRESH .
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 2: Vit chng trnh c ADC 10 bit hai knh AN3 , AN12 v thc hin theo yu cu
sau :
Hin th gi tr in p ti chn AN3 hng (0,0) ca LCD.
Hin th gi tr in p ti chn AN12 hng (0,1) ca LCD.
nh thi bng hm delay , in p tham chiu trong , Fosc = 4Mhz, giao tip LCD
bng th vin LCD.h
41

S phn cng :

#include<htc.h>
#include<stdio.h>
#include "lcd.h"
void main( )
{
unsigned char old_ADRESH;
lcd_init( );
ANS3= .;ANS12= .;
//Enable analog chn RA3 v chn RB0
TRISA3= .;RA3= .;TRISB0=1;RB0=1; //Khi to RA3,RB0 l ng vo
VCFG0=VCFG1= .;
//Chn in p tham chiu trong
ADFM= .;
//nh dng kt qu bn phi (ADC 10 bit)
ADCS0=ADCS1=0;
//Tn s chuyn i
ADON= .;
//Enable module ADC
while(1)
{
CHS3=CHS2= .;CHS1=CHS0= .; //Chn knh AN3
GODONE= .;
while(GODONE);
lcd_gotoxy(0,0);
printf("\fAN3 la:%d",ADRESH*256+ADRESL);
_delay(100000);
CHS3=CHS2= .;CHS1=CHS0= .; //chon kenh AN12
GODONE= .;
42

while(GODONE);
lcd_gotoxy(0,1);
printf("AN12 la:%d",ADRESH*256+ADRESL);
_delay(100000);
}
}
void putch(char c)
{
lcd_putc(c);
}
*Bc 3 : Jum header 3 v tr BUTTON
Nhn gi nt nhn SW2 v quan st kt qu trn LCD v tr (0,0) tc l kt qu o knh
AN3.
Nhn gi nt nhn SW3v quan st kt qu trn LCD v tr (0,0) tc l kt qu o knh
AN3.
Nhn gi c hai nt SW2,SW3 v quan st kt qu trn LCD v tr (0,0) tc l kt qu
o knh AN3.
Da vo mch in nguyn l, chng minh c 3 kt qu quan st c .
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*Bc 4 : Quan st kt qu hng (0,1) ca lcd , tc l kt qu o c knh AN12 khi c
nhn nt RB0 v khi khng c nhn nt v nhn xt :
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------43

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------V.BI TP T GII :
Bi 3 : Vit chng trnh s dng khi ADC ca vi iu khin PIC16F887 o nhit ca
5 phng v hin th ln LCD, s dng LM35 theo yu cu sau :
(To mt project mi vi tn 02_03_ MSSV)
Khi nhn (khng gi )RB0 th LCD hin th gi tr gi tr nhit ca phng 1.
Khi nhn (khng gi )RB1th LCD hin th gi tr gi tr nhit ca phng 2.
Tn s hot ng Fosc = 4MHz , phn cng LCD c kt ni vi PORTD ca Vi iu khin

theo s chn ca th vin lcd.h , in p tham chiu bn trong , s dng ADC 8 bit .
Bi 4:Vit chng trnh c gi tr in p chn AN0 v hin th ln LCD 16x2 theo yu
cu sau : (To mt project mi vi tn 02_04_ MSSV)
Hin th gi tr hai thanh ghi ADRESH v ADRESL v tr (0,0) ca LCD.
Hin th gi tr in p o c v tr (0,1) ca LCD .
44
Tn s hot ng Fosc = 4MHz , phn cng LCD c kt ni vi PORTD ca Vi iu

khin theo s chn ca th vin lcd.h , in p tham chiu bn ngoi , s dng ADC 10 bit .
Bi 5 : Vit chng trnh dng vi iu khin PIC16F887 thc hin chc nng nh mt
my tnh theo s phn cng sau : (To mt project mi vi tn 02_05_ MSSV)
45
CHNG IV: TIMER

I.MC CH TH NGHIM :
Kin thc sinh vin cn t c sau khi thc tp :
Gii thch c nguyn tc hot ng ca timer0 , timer1 , timer 2.
Thit lp cng thc tnh nh thi ca tng timer .
Lit k cc bit iu khin tng hot ng ca timer .
Phn bit s khc nhau v ging nhau gia hai ch timer v counter trong timer 0 ,
timer1.
Gii thch chc nng ca b chia trong timer .
Khi to ngt cho timer0 , timer 1 , timer 2 .
II.DNG C TH NGHIM:
My tnh .
Ngun 12V/1A.
Oscilloscope
III.C S L THUYT :
Timer l khi hot ng c lp vi CPU , do nu trong lp trnh chng ta s dng timer
th s lm gim i thi gian x l , gip vi iu khin hot ng nhanh hn . ng dng ch yu
ca timer l nh thi trong khong thi gian ngn , m s lng xung clock bn ngoi cho cc
ng dng nh : m sn phm , c s xung encoder v.v... PIC16f887 c tch hp 3 timer : timer
0(8-bit), timer 1(16-bit), timer 2(8-bit).
Hnh 30: S khi cc timer trong PIC16F887
46

1.Nguyn tc hot ng ca timer :
Nguyn tc hot ng chung ca timer l tng gi tr ca thanh ghi m ln khi nhn c
mt xung clock ( qua b chia ) . Khi thanh ghi m n gi tr ln nht , nu c xung clock
tip tc tc ng th timer s xy ra s kin trn timer (overflow) , s kin ny c th xy ra
ngt.
V d : Thanh ghi TMR0 l thanh ghi 8-bit cha gi tr m ca timer 0 :
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 0 1 1
Trn timer
TMR0=0
+
TMR0=1
+
TMR0=2
+
TMR0=3
+
:
1 1 1 1 1 1 1 1
TMR0=255
+
Hnh 31: Qu trnh hot ng ca mt timer

2.Timer 0 :
Timer 0 c nhng c tnh sau :
Thanh ghi 8-bit timer/counter (TMR0).
B chia prescaler 8-bit (dng chung vi Watchdog timer )
Hot ng vi xung clock bn trong hoc bn ngoi .
Hot ng vi vic la chn cnh ca xung clock bn ngoi .
Ngt trn timer .
Hnh 32: s khi timer 0 v watchdog timer trong PIC16F887

47

2.1 Cc thanh ghi khi to timer 0 :
T0CS : bit la chn ch hot ng ca timer 0

T0CS=1: Timer 0 hot ng vi ch m counter .(clock c cp t chn T0CKI)
T0CS=0:Timer 1 hot ng vi ch nh thi timer.(clock c cp t thch anh hot
ng ca vi iu khin ).
T0SE : Bit chn cnh tc ng khi timer hot ng vi ch m counter.
T0SE=1: Thanh ghi TMR0 tng khi c s kin cnh xung chn T0CKI.
T0SE=0: Thanh ghi TMR0 tng khi c s kin cnh ln chn T0CKI.
PSA : Dng la chn b chia Prescaler thuc v ca timer 0 hay ca Watchdog.
PSA=1:B chia prescaler thuc v Watchdog .
PSA=0: B chia prescaler thuc v Timer 0.
PS<2:0> : Chn t l cho b chia prescaler
2.2 Cng thc nh thi timer 0:
TMR0
255
Over flow
Hnh 33: Thi gian hot ng ca timer0 (8-bit)
48

T s trn ta thy thi gian nh thi ca timer 0 :
T=(255-TMR0)* =
(2550) 4
Do thay i thi gian nh thi T ta c th thay i mt trong cc thng s sau :

TMR0 : Gi tr ban u ca thanh ghi TMR0 cho timer 0 bt u m. Khi trong
lp trnh khng gn gi tr u cho thanh ghi TMR0 th timer bt u m l 0.
(TMR0=0).
Prescaler : T l b chia ca timer 0.
Fosc : Tn s hot ng ca vi iu khin.(t khi thay i thng s ny)
Ch : Trong qu trnh tnh ton tm ra thi gian nh thi T hp l , thng c sai s
xy ra , do chng ta chn Prescaler v TMR0 sao cho sai s t nht .
2.3 Ngt trong timer0 :
Timer 0 cng c th xy ra ngt , ngt timer 0 xy ra khi timer 0 trn (tc l thanh ghi
TMR0=255 ri sau tr v gi tr ban u).
S ngt timer 0 :
Hnh 34: S ngt timer 0

T0IE : Bit cho php xy ra ngt timer 0 , ngt timer 0 xy ra th bit ny phi bng 1.
T0IF : C ngt timer 0 , khi ngt xy ra bt ny t ng bng 1 , chng ta cn phi xa (=0) bt
ny trong lp trnh .
GIE : GIE bit cho php ngt ton cc , ngt timer 0 xy ra th bit ny phi bng 1.
2.4 : Cc bc khi to timer 0:
2.4.1 : Khi to timer 0 hot ng vi ch nh thi timer:
T0CS=0;
//Clock cp cho timer 0 l Fosc (tn s hot ng ca vi iu khin)
PSA=0 ;
//B chia prescaler c s dng cho timer 0 .
PS<2:0>=....; //Chn t l b chia . Nu PSA=1 th c th b qua dng ny .
//Khi to ngt nu c s dng
INTE=1;
INTF=0;
GIE=1;
49

2.4.2:Khi to timer 0 hot ng vi ch m counter :
//Khi to chn T0CKI l ng vo .
TRISA4=1;
RA4=1;
T0CS=1; // Clock cp cho timer 0 t chn T0CKI
PSA=0 ;
//B chia prescaler c s dng cho timer 0 .
PS<2:0>=....; //Chn t l b chia .Nu PSA=1th c th b qua dng ny .
//Khi to ngt nu c s dng
INTE=1;
INTF=0;
GIE=1;
3.Timer 1 :
Timer 1 c hai thanh ghi cha gi tr m , do c th m ln n 65535(2^16-1) mi xy
s kin trn timer , timer 1 thch hp nht cho vic m xung encoder tc cao , cng ging
nh timer 0 , timer 1 cng hot ng vi hai ch : ch nh thi v ch m counter.
Hnh 35: S khi timer 1
50

3.1 Cng thc nh thi timer 1 :
T=
[65535 (TMR 1H256+TMR 1L)]Prescaler 4

Fosc
Trong :
T thi gian nh thi timer 1
TMR1L , TMR1H : thanh ghi cha gi tr m ca timer 1
FOSC : tn s hot ng ca vi iu khin
Prescaler : t l b chia .
3.2Thanh ghi iu khin timer1 :
TMR1ON : Bit cho php timer1 hot ng

1: Cho php timer 1 (iu kin cn cho timer 1 hot ng , cha )
0: Timer 1 ngng hot ng .
TMR1CS :Bit la chn clock cho timer 1
1:Clock t bn ngoi (t chn T1CKI)
0:Clock bn trong (FOSC/4)
: Bit iu khin la chn ng b clock vo t bn ngoi ca timer 1
Nu TMR1CS =1:
1:Clock vo t bn ngoi khng c ng b
0:Clock vo t bn ngoi c ng b
Nu TMR1CS = 0:
Khng cn quan tm bit ny , timer 1 s dng clock bn trong .
T1OSCEN : Bit iu khin cho php dao ng LP
1: Dao ng LP c cho php cho clock timer 1 .
0: Tt dao ng LP .
T1CKPS<1:0> : Bit la chn t l b chia Prescale
11 = 1:8
10 = 1:4
01 = 1:2
00 = 1:1
TMR1GE : Bit cho php cng timer 1
Nu TMR1ON=0 : bit ny khng cn quan tm
Nu TMR1ON=1 :
1 : S m ln ca timer1 s c iu khin bi cng Timer 1
0 : Timer 1 c th m ln m khng cn quan tm n trng thi ca cng timer 1 .
T1GINV : Bit o cng timer1
51

1 : Cng timer1 tc ng mc cao (Timer1 hot ng khi cng mc cao ).
0 : Cng timer 1 tc ng mc thp (Timer 1 hot ng khi cng mc thp).
3.3 Timer1 on :
Khng ging vi timer 0 , chng ta cn khi to mt s bit th timer 1 mi c th hot ng
c . T s trn ta c th thy vic bt/tt timer 1c hai dng :
Cho php timer 1 hot ng m khng cn tc ng t bn ngoi :
TMR1ON=1;
TMR1GE=0;
Cho php timer 1 hot ng khi c tn hiu logic chn T1G :
//Cho php in tr treo .
//Khi to chn T1G l ng vo .
ANS13=0;
TRISB5=1;
RB5=1;
TMR1ON=1;
TMR1GE=1;
T1GINV=.....;
//Ty theo mc logic chn T1G l mc cao hay thp.
T1GSS=1;
3.4 Ngt trong timer 1 :
Timer 1 cng c th to ra s kin ngt khi xy ra trn timer , cc bit khi to ngt ca
timer 1 :
TMR1IF : C ngt , bit ny t ng bng 1 khi c s kin trn timer .
TMR1IE :Bit cho php ngt trn timer .
PEIE
:Bit cho php ngt ngoi vi .
GIE
:Bit cho php ngt ton cc .
Hnh 36: S ngt timer 1

3.5 Khi to timer 1 hot ng vi ch m counter :
//Khi to chn T1CKI l ng vo s
T1OSCEN=1;
TMR1CS=1;
T1CKPS1=..;
T1CKPS0=..;
T1SYNC=0;
//Cho php timer 1 on
//Khi to ngt nu c
52

Ngoi ra , timer 1 cn c th hot ng vi ch timer s dng thch anh ngoi , c
lp vi tn s hat ng ca vi iu khin , thch anh ngoi ta c th kt ni vi hai chn :
OSC1 v OSC2 v khi to tng t nh trn .
3.6 Khi to timer 1 hot ng vi ch nh thi timer :
TMR1CS=0;
T1CKPS1=..;
T1CKPS0=..;
T1SYNC=1;
//Cho php timer 1 on
//Khi to ngt nu c
4.Timer 2 :
Khc vi timer 0 v timer 1 , timer 2 ch c th hot ng ch nh thi timer , tuy nhin
timer 2 c hai b chia v mt gi tr t do thi gian nh thi c th linh hot hn , v t sai
s trong tn ton .
Hnh 37: S khi timer 2

Nguyn tc hot ng timer 2 :
Khi c xung clock tn s Fosc/4 qua b chia Prescaler i vo thanh ghi TMR2 , lm thanh
ghi TMR2 tng ln , khi thanh ghi TMR2 bng gi tr thanh ghi t PR2 th s c mt xung clock
i qua b chia Postscaler , ng thi thanh ghi TMR2 tr v v tr ban u , nu t l b chia
Postscaler c chn 1:1 th s xy ra s kin ngt timer 2 .
4.1 Cng thc tnh nh thi timer 2 :
T=
Trong
T
PR2
TMR2
Prescaler
Postscaler
Fosc
PR 2TMR 2 Postscaler Prescaler 4

Fosc
:Thi gian nh thi timer 2

:gi tr thanh ghi t
: gi tr bt u m ca thanh ghi TMR0
: T l b chia prescaler
: T l b chia Postscaler
:Tn s hot ng ca vi iu khin .
53

4.2. Thanh ghi iu khin timer 2 :
T2CKPS<1:0>: Bit la chn t l b chia Prescaler

00 : 1:1
01 : 1:4
1x : 1:16
TMR2ON : Bit cho php timer 2 hot ng
0:Khng cho php timer2 hot ng
1:Cho php timer 2 hot ng
TOUTPS<3:0>: Bit la chn t l b chia Postscaler
4.2.Khi to timer 2 hot ng vi ch nh thi timer :

//Tn ton la chn t l b chia Prescaler , Postscaler
//Chn t l b chia Prescaler
T2CKPS1=..; T2CKPS0=;
//Chn t l b chia Postscaler
TOUTPS3=.; TOUTPS2=.;
TOUTPS1=.; TOUTPS0=.;
//t gi tr ln nht cho gi tr thanh ghi m TMR2
PR2=;
//Cho php timer 2 hat ng
TMR2ON=1;
//Khi to ngt timer 2 nu c s dng :
TMR2IE=1;
TMR2IF=0;
PEIE=1;
GIE=1;
54

IV.BI TP THC HNH :
Bi 1: Vit chng trnh c s ln nhn nt ti chn T0CKI(RA4) v hin th kt qu ln
LCD:
S phn cng :
*Bc 1: To mt project mi vi tn 03_01_ MSSV

#include<htc.h>
#include<stdio.h>
#include "lcd.h";
void main( )
{
lcd_init( );
TRISA4=.; RA4=.; //Khi to chn T0CKI l ng vo
T0CS =.;
//Chn clock cp cho Timer0 l t chn T0CKI
T0SE =.;
//Chn cnh tc ng l cnh xung
PSA =.;
//Xung clock khng qua b chia (-------------1------------)
//(-------------2------------)
while(1)
{
lcd_gotoxy(0,0);
printf("\fSo lan nhan nut la:\r\n %d",TMR0);
_delay(100000);
}
}
void putch(char c)
{
lcd_putc(c);
}
*Bc 3:Nhn nt nhn kt ni vi chn T0CKI v quan st kt qu trn LCD.
*Bc 4:Xa dng (-------------1------------)
55

*Bc 5:Thm vo dng (-------------2------------) on code sau :
PSA=0;
//Chn b chia thuc v timer
PS2=0;
//Chn t l chia
PS1=1;
PS0=1;
*Bc 6: Quan st kt qu khi nhn nt nhn.
*Bc 7: So snh hai kt qu trc v sau khi sa code , gii thch ? Nu chc nng ca b chia
trong timer 0:
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 2: Vit chng trnh chp tt led RE1 , nh thi bng timer 0,tn s Fosc/4:
*Bc 1: To mt project mi vi tn 03_02_ MSSV
#include<htc.h>
void main( )
{
ANS6=.;TRISE1=.;
//Khi to chn RE1 l digital output
T0CS=.;
//Chn xung clock cp cho timer 0 l t Fosc/4
PSA=.;
//Xung clock s i qua b chia
PS2=.; PS1=.; PS0=.; //T l b chia l 128
//Khi to ngt cho timer 0
T0IE=.;
//Cho php ngt timer 0
T0IF=.;
//Reset c ngt
GIE=.;
while(1);
//Lp v tn
}
void interrupt isr()
{
if(T0IE&T0IF)
//Chng trnh con ngt cho timer0
{
RE1^=1;
//Chp tt led
TMR0=0;
//Khi to gi tr m ban u cho timer0(-------1--------)
T0IF=0;
//Reset c ngt.
}
56

}
*Bc 3 : Bin dch chng trnh , np xung kt th nghim , quan st trng thi ca led .
*Bc 4:Tng gi tr TMR0 dng (-------1--------) t thp n cao(0-255) , bin dch chng
trnh v np xung kit th nghim , n lc mt khng cn nhn thy led RE1 chp tt , tnh
tn s ng vi gi tr thanh ghi TMR0 va tm c .
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*Bc 5 : S dng oscillocope o tn s va tm c v so snh vi kt qu tnh ton , nhn
xt.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 3:Vit chng trnh hin th ng h ln LCD , s dng timer 1 nh thi , thch anh
ngoi 32.768KHz.
#include<htc.h>
#include<stdio.h>
RDIS&IESODIS&LVPDIS&FCMDIS);void insothuc(unsigned char old_ADRESH);
#include "lcd.h"
unsigned char hh,mm,ss;
//Khai bo bin cha gi , pht , giy
void main()
{
lcd_init();
//Khi to cc chn ng vo thch anh 32.768KHz
TRISC0=TRISC1=1;RC0=RC1=0;
T1OSCEN= .;
//Cho php timer 1 hot ng clock ngoi
TMR1CS=
.;
//Clock cp cho timer 1 l clock ngoi
T1CKPS1=T1CKPS0=.;
//T l b chia 1:8(-------1--------)
T1SYNC=
.;
//Qua khi ng b
//Cho php timer hot ng khng cn tc ng bn ngoi
TMR1ON= .;
TMR1GE= .;
57

TMR1IE=
TMR1IF=
PEIE=
GIE=
while(1);
.;
.;
.;
.;
//Khi to ngt timer1

//Reset c ngt timer 1
//Lp v tn
}
void putch(char c)
//Chng trnh con cho hm printf( )
{
lcd_putc(c);
}
{
if(TMR1IE&&TMR1IF)
//Ngt trn timer 1
{
ss++;
if(ss==60)
{
ss=0;
mm++;
if(mm==60)
{
mm=0;
hh++;
}
}
lcd_gotoxy(0,0);
printf("\fBay Gio La :\r\n %02d:%02d:%02d",hh,mm,ss);
TMR1H=239;
//Khi to gi tr m ban u cho timer1 (-------2--------)
TMR1L=255;
//
(-------3--------)
TMR1IF=0;
}
}
*Bc 3 : Np chng trnh xung kit th nghim , jumper J1(XTAL).Quan st lcd , v so snh
kt qu vi ng h thc, nhn xt :
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Da vo cng thc nh thi ca timer 1, chng minh nhng thng s cc dng (1),(2),(3):
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------58

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 4: Vit chng trnh s dng timer 2 iu khin led RE1 chp tt vi chu k T=0.1s ,
s dng thch anh ngoi 20MHz.
*Bc 2: Nhp chng trnh sau vo my tnh :
#include<htc.h>
#include<stdio.h>
__CONFIG(HS&WDTDIS&PWRTEN&MCLREN&UNPROTECT&DUNPROTECT&BORDI
S&IESODIS&LVPDIS&FCMDIS);
void main()
{
ANS6=.;TRISE1=.;RE1=.;
//Khi to chn RE1 l ng ra s
T2CKPS1=.;T2CKPS0=.;
//chn t l b chia prescaler 1:1
//Chn t l b chia postscaler 1:2
(-------1--------)
TOUTPS3=0;TOUTPS2=0;TOUTPS1=.;TOUTPS0=.;
PR2=.;
//Gi tr thanh ghi PR2
(-------2--------)
TMR2=.;
//Gi tr bt u m ca timer 2 (-------3--------)
//Cho php timer 2 hot ng
TMR2ON=.;
//Khi to ngt timer 2
TMR2IE=.;
TMR2IF=.;
PEIE=.;
GIE=.;
while(1)
{
}
}
{
if(TMR2IE&&TMR2IF)
{
RE1^=1;
TMR2IF=.;
TMR2=. ;
}
}
//Cho php ngt trn timer 2

//Reset c ngt
//Xa c ngt Timer2

//Khi to gi tr bt u m timer2(-------4------)
59

*Bc 3 : Tnh ton cc thng s dng (1),(2),(3),(4)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*Bc 4 : Hon thnh vo du .............v bin dch chng trnh , np xung kt th nghim ,
quan st led .
V.BI TP T GII :
Bi 5 : Vit chng trnh hin th tc ng c ln lcd theo s phn cng sau :
(To mt project mi vi tn 03_05_ MSSV)
60
CHNG V: KHI CCP

(CAPTURE-COMPARE-PWM)
I.MC CH TH NGHIM :
Gii thch nguyn tc hot ng v khi to ch Capture.
Gii thch nguyn tc hot ng v khi to ch Compare .
Gii thch nguyn tc hot ng v khi to ch PWM.
Phn bit s khc nhau v ging nhau gia hai khi CCP1 v CCP2.
Thit lp c tn s PWM v iu chnh rng xung PWM theo yu cu.
II.DNG C TH NGHIM:
ng c DC12V.
Oscillocope.
My tnh .
Ngun 12V/1A.
III.C S L THUYT :
Cc chn c s dng cho khi CCP:
Hnh 38: Cc chn c s dng trong khi CCP

s dng khi CCP chng ta cn phi bit khi to v s dng thnh tho timer 0,1,2 bi
v mt mnh khi CCP khng th hot ng c mt ng dng m phi s dng kt hp vi
mt trong 3 timer , c th l :
61

1.Thanh ghi khi to khi CCP1:
Khi CCP1 cn tch hp thm 4 chn mang k hiu : P1A, P1B, P1C, P1D h tr cho vic
iu khin cu H.
Hnh 39: Cc chn CCP1 h tr iu khin cu H
P1M<1:0> : Bit khi to ng ra PWM

Nu khi CCP1 c khi to ch capture hoc compare th chn c k hiu P1A l
chn hot ng ch capture hoc compare , cn cc chn c k hiu P1B, P1C, P1D l cc
chn khng lin quan n khi CCP1 , chng ta c th gn cho chng chc nng I/O thng
thng .
Nu khi CCP1 c khi to ch PWM th 2 bit P1M<1:0> c 4 trng thi iu khin
cu H nh sau :
00:Ng ra n , P1A to xung , P1B , P1C, P1D hot ng vi chc nng I/O.
01:Ch Full Bridge thun , P1D to xung , P1A tc ng , P1B , P1C khng tc ng
10:Ch hafl Bridge , P1A ,P1B to xung , P1C, P1D hot ng vi chc nng I/O.
11: Ch Full Bridge nghch , P1B to xung , P1C tc ng , P1A , P1D khng tc
ng .
DC1B<1:0> : Hai bit mang trng s nh nht trong ch hot ng PWM10bit . ch
Capture v Compare th khng cn quan tm n hai bit ny.
CCP1M<3:0> : Bit la chn ch hat ng khi CCP1
0000: Capture/Compare/PWM off(reset khi CCP1)
0001: Khng s dng
0010: Ch Compare , o ng ra khi c s kin Compare (bit CCP1IF = 1).
0011: Khng s dng
0100: Ch Capture , s kin Capture xy ra khi chn CCP1 c 1 xung cnh xung .
0101: Ch Capture , s kin Capture xy ra khi chn CCP1 c 1 xung cnh ln .
62

1000: Ch Compare , ng ra bng 1 khi c s kin Compare (bit CCP1IF = 1).
1010: Ch Compare , to ra s kin ngt ni (bit CCP1IF = 1 , chn CCP1 khng s
dng ).
1011: Ch Compare, to ra s kin trigger (CCP1IF =1; CCP1 resets TMR1 or
TMR2)
1100: Ch PWM , P1A , P1C tc ng mc cao , P1B , P1D tc ng mc cao
1101: Ch PWM , P1A , P1C tc ng mc cao , P1B , P1D tc ng mc thp
1110: Ch PWM , P1A , P1C tc ng mc thp , P1B , P1D tc ng mc cao
1111: Ch PWM , P1A , P1C tc ng mc thp , P1B , P1D tc ng mc thp
2.Thanh ghi khi to khi CCP2:
Khc vi khi CCP1 , khi CCP2 khng c chc nng h tr iu khin cu H , trong ch
PWM , khi CCP2 ch c chc nng to ra xung PWM 10 bt chn CCP2.
DC2B<1:0> : Hai bit mang trng s nh nht trong ch hot ng PWM-10bit , ch

Capture v Compare th khng cn quan tm n hai bit ny.
CCP2M<3:0> : Bit lc chn ch ha ng khi CCP1
0000: Capture/Compare/PWM off(reset khi CCP1)
0001:Khng s dng
0010: Khng s dng
0011:Khng s dng
0100:Ch Capture , s kin Capture xy ra khi chn CCP1 c 1 xung cnh xung .
0101:Ch Capture , s kin Capture xy ra khi chn CCP1 c 1 xung cnh ln .
1010: Ch Compare , to ra s kin ngt ni (bit CCP1IF = 1 , chn CCP1 khng s
dng ).
1011: Ch Compare, to ra s kin trigger (CCP1IF =1; CCP1 resets TMR1 or
TMR2).
11XX:Ch PWM.
63

3.Capture :
Hnh 40: S khi ch capture

3.1 Nguyn tc hot ng ca ch capture :
Khi c s kin (cnh ln , cnh xung , 4 cnh ln hoc 16 cnh ln ) chn CCPx (c th l
CCP1 hay CCP2 ty vo ta s dng khi CCP1 hay CCP2) th gi tr thanh ghi m ca timer 1
l TMR1H v TMR1L s c cp nht qua hai thanh ghi CCPRxH v CCPRxL ca khi CCPx.
ng thi c th xy ra ngt ni bng vic cho php c ngt CCPRxIF = 1 .(x=0,1)
3.2 Cc bc khi to ch capture :
Khi to chn CCPx l ng vo : TRISCx=1;RCx=1;
Khi to timer 1 hot ng .
Khi to khi CCPx hot ng vi ch capture :
CCPxCON = ......;
//Chn ch capture .
CCPRxH=CCPRxL=0;
//reset hai thanh ghi ca khi CCPx.
Khi to ngt (nu c s dng):
CCPxIE=1;
//Cho php ngt CCP
CCPxIF=0;
//Reset c ngt
PEIE=1;
GIE=1;
4.Compare :
Hnh 41: S khi ch compare

64

4.1Nguyn tt hot ng ca ch compare :
Khi hai thanh ghi m TMR1H v TMR1L ca timer 1 m n gi tr ca hai thanh ghi
CCPRxH v CCPRxL th s xy ra mt trong cc s kin sau :
o trng thi ng ra ca chn CCPx.
To tn hiu chn CCPx ln bng 1 .
Xa tn hiu chn CCPx xung bng 0 .
To ra ngt .(CCPxIF =1 , chn CCPx khng s dng )
To ra s kin trigger .(CCP1IF=1,CCP1 reset timer 1 hoc timer 2,CCP2IF=1,CCP2
reset timer 1 v ADC bt u chuyn i nu khi ADC c cho php chuyn i , chn
CCP2 khng s dng ).
4.2Cc bc khi to ch compare:
Khi to chn CCPx l ng ra : TRISCx=0;
Khi to timer 1 hot ng .
Khi to khi CCPx hot ng vi ch compare :
CCPxCON = ......;
//Chn ch compare .
CCPRxH=....;CCPRxL=.....; //Chn gi tr t .
Khi to ngt (nu c s dng) :
CCPxIE=1;
//Cho php ngt CCP
CCPxIF=0;
//Reset c ngt
PEIE=1;
GIE=1;
5.PWM(Pulse-Width Modulated) :
Ni n PWM th ta phi ni n hai c tnh c bn l : tn s (do timer 2 to ra ) v
rng xung (do thanh ghi CCPRxL:CCPxCON<5:4> to ra ).
S to xung PWM l s kt hp ca khi CCPx vi timer 2 :
Hnh 42: S iu ch PWM

5.1Nguyn tt hot ng ca ch PWM :
Thanh ghi m ca timer 2 l TMR2 m n gi tr thanh ghi CCPRxL:CCPxCON<5:4>
ca khi CCPx th trng thi logic chn CCPx b o , khi gi tr ca thanh ghi TMR2 n gi tr
PR2 th hon tt mt chu k to xung PWM .
Ch : T s trn ta thy to xung PWM th gi tr

CCPRxL::CCPxCON<5:4> phi nh hn hoc bng gi tr thanh ghi PR2 , v mun thay
65

i rng xung ta ch cn thay i gi tr thanh ghi CCPRxL::CCPxCON<5:4> trong lp
trnh .
Cng thc tnh chu k PWM :
Cng thc tnh rng xung PWM :
6.Cc bc khi to chc nng PWM:

Bc 1 : Cho php chn PWM l ng vo:
TRISCx=1;
//x= 1 , 2
Bc 2 : Khi to tn s PWM bng vic nh gi tr thanh ghi PR2 ca timer 2:
PR2=....;
//Tnh ton c t cng thc chu k PWM
Bc 3: t khi CCP hot ng ch PWM
CCPxCON=0bxxxx11xx;
//x=0;1
Bc 4 : t rng xung ca khi PWM bng vic t gi tr cho thanh ghi CCPRxL
v 2 bit DCxB<1:0> ca thanh ghi CCPxCON
CCPRxL=.....; //C th iu chnh gi tr ny trong khi vi iu khin hot ng
thay i rng xung khi cn thit .
DCxB1=.....; //Nu s dng PWM 8 bit th c th b qua dng ny
DCxB0=.....; //Nu s dng PWM 8 bit th c th b qua dng ny
Bc 5 : Khi to v cho php timer 2 hot ng :
TMR2IF=0;
//Xa c ngt TMR2IF ca thanh ghi PIR1
//Chn t l b chia ca timer 2 :
T2CKPS1=.....;
//Chn t l b chia Prescaler
T2CKPS0=.....;
TOUTPS3=....;
//Chon t l b chia Postscaler
TOUTPS2=....;
TOUTPS1=....;
TOUTPS0=....;
TMR2ON=1;
Bc 6 : Cho php ng ta PWM sau khi chu k PWM mi c bt u :
while(TMR2IF);
// Ch cho n khi timer 2 trn (bit TMR2IF ca thanh ghi
PIR1 c bc ln 1)
TRISCx = 0 ;
//x = 1 , 2 .
66

IV.BI TP THC HNH :
Bi 1:Vit chng trnh to xung PWM c tn s 20KHz hai chn : CCP1(RC2) v
CCP2(RC1) vi rng xung CCP1 l 50% xung , CCP2 l 80% xung .
S phn cng :
*Bc 1 :To mt project mi vi tn 04_01_ MSSV

#include <htc.h>
void main( )
{
//Khi to tn s 20Khz PWM (timer 2)
PR2=.;
//Chn tn s 20KHz
T2CKPS1=T2CKPS0=.;
//B chia Prescales 1:1
TOUTPS3=TOUTPS2=TOUTPS1=TOUTPS0=.;//B chia Postcales1:1
//Khi to khi CCP1
TRISC2=.;
//Disable ng ra ca chn CCP1
CCP1CON=0b00001100;
//(-------1--------)
CCPR1L=.;
//To PWM 50% xung chn CCP1(-------2--------)
TMR1IF=.;
//Xa c ngt ca khi CCP1
// Khi to khi CCP2
TRISC1=.;
// Disable ng ra ca chn CCP1
CCP2CON=0b00001100;
// Khi to module CCP2 hot ng ch PWM
CCPR2L=.;
//To xung PWM 80% chn CCP2(-------3--------)
TMR2IF=.;
// Xa c ngt ca khi CCP2
//Cho php timer 2 hot ng bt u to xung PWM
TMR2ON
=.;
TRISC2
=.;
//Cho php chn CCP1 l ng ra
TRISC1
=.;
//Cho php chn CCP2 l ng ra .
while(1);
}
*Bc 3 : Np chng trnh vo kit th nghim , dng oscillocope o tn hiu hai xung chn
CCP1 v CCP2 .
*Bc 4 : Thay i dng (-------1--------) thnh on code sau :
CCP1CON=0b00001111;
67

Bin dch chng trnh np vo kt , dng oscillocope o ng ra PWM chn CCP1 , quan
st xung c to ra , nhn xt s khc nhau gia xung trc v sau khi thay i code , v gii
thch s khc nhau .
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*Bc 5 : Tnh ton gi tr thanh ghi CCPR1L cho CCP1 to ra PWM 90% .
Tnh ton gi tr thanh ghi CCPR2L cho CCP2 to ra PWM 10% .
Thay vo (-------2--------) v (-------3--------) , bin dch chng trnh , np xung kt
th nghim , s dng oscillocope o ng ra xung v hon thnh vo bng sau :
PWM 90%
PWM 10%
CCPR1L
CCPR2L
Bi 2 : Vit chng trnh iu khin tc ng c s dng IC chuyn dng L298 theo
yu cu sau : (To mt project mi vi tn 04_02_ MSSV)
Nhn RB0 tc ng c tng dn (mi ln nhn tng 10% rng xung).
Nhn RB1 tc ng c gim dn(mi ln nhn gim 10% rng xung).
Nhn RB2 ng c o chiu quay .
Vi PWM tn s 10Khz , phn gii 8 bit , thch anh ni 4MHz.
Phn cng :
68

*Bc 1 :To mt project mi vi tn 04_02_ MSSV
*Bc 2 :Nhp chng trnh sau vo my tnh v hon thnh vo du .
#include <htc.h>
void main( )
{
ANSEL=ANSELH=.; //Tt chc nng x l analog tt c cc chn
TRISB=.; //Khi to PORTB l ng vo
PORTB=.;
WPUB=.; //Cho php in tr treo tt c PORTB
RBPU=.;
IOCB =.; //Cho php ngt on-change c PORTB
RBIE =.; //Enable ngt on-change PORTB
RBIF =.; //Xa c ngt on-change
GIE =.; //Cho php ngt ton cc
TRISE0=.;
RE0 =.;
//Khi to chn RE0 l ng ra , mc cao
T2CON = 0x04; //Timer 2 , prescaler 1:1 , postcaler 1:1 , TMR2ON=1

PR2
=.;
//tn s 10KHz
CCP1CON=0x0C; //Khi to ch PWM cho module CCP1
CCP2CON=0x0C; //Khi to ch PWM cho module CCCP2
CCPR1L=0;
CCPR2L=0;
TRISC2=1;
TRISC1=1;
while(1)
{
}
}
{
if(RBIE&&RBIF)
{
if(!RB0)
{
CCPR1L+=10;
CCPR2L+=10;
TMR2ON=1;
}
if(!RB1)
{
CCPR1L-=10;
69

CCPR2L-=10;
TMR2ON=1;
}
if(!RB2)
{
TRISC2^=1;
TRISC1=~TRISC2;
TMR2ON=1;
}
RBIF=0;
}
}
*Bc 3 : Jum header CCP2 (J2) , bin dch chng trnh np xung kt th nghim , kt ni
ng c v cp ngun cho L298 , tin hnh nhn nt v quan st kt qu .
V.BI TP T GII :
*Bi 3 : Vit chng trnh s dng chc nng capture o tn s chn CCP1(RC2) v hin th
gi tr ln LCD theo s phn cng sau (To mt project mi vi tn 04_03_ MSSV):
*Bi 4 : Vit chng trnh to xung PWM 8 bit chn CCP2(RC1) vi tn s 15 KHz theo
yu cu sau (To mt project mi vi tn 04_04_ MSSV)::
Nhn nt nhn (khng gi ) chn RB0 ln 1 : rng xung 15% .
70

Nhn nt nhn (khng gi ) chn RB0 ln 7 : Tr li trng thi nhn ln 1 .
*Bi 5 :Vit chng trnh theo yu cu sau (To mt project mi vi tn 04_05_ MSSV):
Nhn RB0 ng c quay cng chiu kim ng h , PWM 10Khz , rng xung 90%.
Nhn RB1 ng c quay ngc chiu kim ng h , PWM 15Khz , rng xung 70%.
71
CHNG VI: GIAO TIP NI TIP BT NG B

I.MC CH TH NGHIM :
Gii thch nguyn l truyn nhn tn hiu UART.
Trnh by c khi nim : baud , start bit , stop bit , frame truyn , parity .
Lit k c cc thanh ghi lin quan truyn nhn UART.
Thit lp cc bit cho vi iu khin truyn nhn d liu qua chun UART.
II.DNG C TH NGHIM:
ng c DC12V.
Oscillocope.
My tnh .
Ngun 12V/1A.
III.C S L THUYT :
Cc chn lin quan n chc nng giao tip ni tip :
Hnh 43: Cc chn truyn nhn UART

1.Khi nim v giao tip ni tip bt ng b :
Cc thut ng trong truyn nhn ni tip bt ng b :
Thut ng USART trong ting anh gi l :Universal Synchronous v Asynchronous serial
Receiver and Transmitter , ngha l b truyn ni tip ng b v bt ng b . USART hay
UART cn phi kt hp vi mt thit b chuyn i in p to nn mt chun giao tip no
.V d chun Rs232(COM Port ) trn my tnh l s kt hp ca chip UART v chip chuyn
i mc in p .Tn hiu t chip UART thng theo mc in p : mc high l +5V , mc slow
l 0V. Trong khi tn hiu theo chun RS232 trn my tnh thng l -12v cho mc high , v
+12v cho mc slow .
Hnh 44: Cu trc mt frame truyn

72

Truyn thng ni tip :
Gi s mun truyn mt d liu 8-bit gia hai vi iu khin vi nhau , chng ta c th ngh
n cch n gin nht l kt ni mt PORT (8 bit) ca mi vi iu khin vi nhau , mi ng
trn PORT s m nhim vic truyn/nhn mt bit d liu . y gi l cch giao tip song song ,
cch ny n gin v truyn nhn d liu cng khng qua bt c mt gii thut truyn nhn no ,
v tc truyn nhn cng rt nhanh .Tuy nhin , nhc im ca cch truyn ny l s ng
truyn nhiu , d liu truyn cng ln th s ng truyn cng nhiu , do h thng truyn
nhn song song thng rt cng knh v km hiu qu . Ngc li trong truyn thng ni tip ,
d liu c truyn theo tng bit trn mt ng truyn , chnh v vy d liu cho d c ln th
chng ta cng ch cn c mt ng truyn duy nht .
Hnh 45: S truyn nhn 8 bit theo giao thc song song v ni tip .
Cc thng s c bn trong truyn nhn ni tip :
Baud rate (tc baud ): truyn nhn ni tip xy ra thnh cng th cc thit b phi
thng nht vi nhau v khong thi gian ginh cho mt bit truyn , hay ni cch khc l tc
truyn phi c ci t ging nhau , tc ny gi l tc baud .Tc baud l s bit truyn
trong 1 giy . V d nu tc baud l 9600 th thi gian ginh cho mt bit truyn l 1/9600(s).
Frame (khung truyn ) : Khung truyn quy nh v s bit trong mi ln truyn , cc bit
bo nh start , stop , cc bit kim tra nh parity , ngoi ra s lng cc bit trong mt d liu cng
c quy nh bi khung truyn . Hnh trn m t v d v mt khung truyn theo UART , khung
truyn ny c bt u bng mt start bit , tip theo l 8 bit , sau l 1bit parity dng
kim tra d liu v cui cng l 2 bits stop .
Start bit : start bit l bit u tin c truyn trong mt frame , bit ny c nhim v bo
cho thit b nhn bit rng c mt gi d liu sp c truyn ti .Start bit l bit bt buc phi c
trong mt khung truyn .
Data : l s d liu m chng ta cn phi truyn nhn , data c th l gi 8 bit hay 9 bit
ty theo yu cu truyn nhn m ta quy nh .Trong truyn thng ni tip UART , bit c trng s
nh nht LSB(Least significant bit ) s c truyn trc , sau bit c trng s ln nht s
c truyn sau cng MSB(Most signnificant bit ).
Parity bit : parity dng kim tra d liu truyn c ng khng , c hai loi parity l
parity chn (event parity )v parity l (odd parity ) .
Stop bit : stop bit l mt hoc cc bit bo cho thit b rng cc bit c gi xong. Sau
khi nhn c stop bit , thit b nhn s tin hnh kin ra khung truyn m bo tnh chnh
xc ca d liu .Stop bit l bit bt buc xut hin trong khung truyn .
73

2.Cc thanh ghi iu khin truyn UART:
Hnh 46: S khi b truyn UART

Nguyn tc hot ng :
D liu cn truyn c t vo thanh ghi TXREG , baud rate c to ra , khi bit TXEN
c gn bng mt , d liu t thanh ghi TXREG i vo thanh ghi TSR ng thi baud rate tc
ng n thanh ghi TSR , y d liu cn truyn ra b im , sau xut ra chn TX v i ra
ngoi .
Bit TXIF dng bo trng thi trong thanh ghi TXREG , nu c d liu trong thanh ghi
TXREG th bt ny s c tn hiu l 1 , ngc li sau khi d liu c truyn xung thanh ghi
TSR th bt TXIF c xa v khng .Tng t nh bit TXIF , bit TRMT dng bo trng thi
ca thanh ghi TSR .Qu trnh truyn cng c th to ra ngt truyn , mi khi d liu truyn
kt thc bng vic t bit TXIF=1.
Ngoi ra b truyn cn c th truyn vi ch 9 bit bng vic cho bit TX9 =1 , v d liu
ca bit th 9 do bit TX9D quy nh .
Thanh ghi quy nh ch truyn :
Cc bit lin quan n ch truyn nhn bt ng b.

TX9 :bit cho php truyn nhn ch 9-bit
1:Cho php hot ng vi ch 9 bit
0:Hot ng vi ch 8bit
TXEN:bit cho php truyn UART
1:Cho php truyn .
0:Khng cho php truyn .
74

SYNC :bit la chn ch truyn .
1:Truyn nhn ch ng b.
0:Truyn nhn ch bt ng b.
BRGH: bit la chn ch baud rate
1: tc cao (bt ng b )
0:tc thp (bt ng b)
TRMT : bit hin th trng thi thanh ghi truyn
1:Thanh ghi TSR trng .
0:Thanh ghi TSR c d liu .
TX9D : D liu bit th 9 trong ch truyn 9 bit
Hnh 47: Ngt truyn UART

Cc bit khi to ngt truyn UART :
TXIF : c ngt , sau khi thanh ghi TXREG truyn d liu xung thanh ghi TSR th bit ny t
ng bng 1 .
TXIE : bit cho php ngt truyn , to ra ngt truyn ta cn phi cho php bit ny bng 1 .
PEIE : bit cho php ngt ngoi vi .
GIE : bit cho php ngt ton cc .
Cc bc khi to ch truyn UART :
*Bc 1 : Khi to thanh ghi SPBRGH , SPBRG v cc bit BRGH v BRG16 to ra baud
rate cn thit .
*Bc 2 : Cho php giao tip bt ng b :
SYNC=0;
SPEN=1;
*Bc 3 : Cho php ch 9 bit (nu s dng truyn nhn 9 bit ) :
TX9=1;
*Bc 4 : Cho php truyn :
TXEN=1;
*Bc 5 : Nu s dng ngt th cn phi khi to :
TXIE=1;
PEIE=1;
GIE=1;
*Bc 6: Gi d liu cn truyn ca bit th 9 (nu s dng truyn nhn 9 bit ):
75

TX9D=..;
*Bc 7 : Gi d liu cn truyn vo thanh ghi 8 bit:
TXREG=..;
3.Cc thanh ghi iu khin nhn UART:
Hnh 48: S khi b truyn UART

Nguyn tc hot ng :
Khi c d liu c truyn ti chn RX , nu bit SPEN c cho php , th d liu s c
ng b vi khi to xung , v baund rate gia hai khi truyn nhn bng nhau, nn xung baud
mang d liu tng bit vo thanh ghi RSR , khi mt frame truyn hon tt (du hiu t bit stop) ,
th d liu c truyn xung thanh ghi RCREG , bit th 9 c truyn xung RX9D(nu s
dng ch 9 bit) , nu trn ng truyn c li th cc bit OERR, FERR s c hin th
bo .
Qu trnh nhn cng c th to ra ngt sau khi kt thc mt frame truyn nhn, bng vic lm
cho bit RCIF =1 .
Thanh ghi quy nh ch nhn :
Cc bit lin quan n ch truyn nhn bt ng b.

SPEN : Bit cho php khi to cng ni tip :
1:Cho php cng ni tip
0: Khng cho php cng ni tip
RX9: Bit cho php nhn 9 bit
1: Ch nhn 9 bit
0: Ch nhn 8 bit
76

CREN : bit cho php nhn lin tc
1: Cho php .
0: Khng cho php .
ADDEN : bit cho php pht hin a ch (s dng ch truyn nhn bt ng b 9 bit )
1:Cho php pht hin a ch , cho php ngt v ti b m nhn khi RSR<8> c set.
0:Khng cho php pht hin a ch , tt c byte c nhn v bit th 9 dng lm bit
parity
FERR : bit bo li frame
1: C li
0:Khng c li .
OERR : li OVERRUN
1:C li (c th xa bng vic xa bt CREN)
0:Khng li .
RX9D : Bit cha d liu nhn ca bit th 9
Hnh 49: Ngt nhn UART

Cc bit khi to ngt nhn UART :
RCIF : c ngt , sau khi thanh ghi RCREG nhn c d liu th bit ny t ng bng 1.
RCIE : bit cho php ngt nhn , to ra ngt nhn ta cn phi cho php bit ny bng 1 .
PEIE : bit cho php ngt ngoi vi .
GIE : bit cho php ngt ton cc .
Cc bc khi to ch nhn UART :
*Bc 1 : Khi to thanh ghi SPBRGH , SPBRG v cc bit BRGH v BRG16 to ra baund
rate cn thit .
*Bc 2 : Cho php giao tip bt ng b :
SYNC=0;
SPEN=1;
*Bc 3 : Nu s dng ngt nhn :
RCIE=1;
PEIE=1;
GIE=1;
*Bc 4 : Cho php ch 9 bit bng (nu s dng truyn nhn 9 bit ) :
RX9=1;
77

*Bc 5 : Cho php nhn d liu :
CREN=1;
*Bc 6 : C ngt RCIF = 1 khi d liu chuyn i t RSR ti b im nhn . Ngt s c to
ra nu RCIE=1.
*Bc 7 : c thanh ghi RCSTA pht hin cc li trong qu trnh truyn nhn.
*Bc 8 : Nhn 8 bit d liu t b im nhn bng cch c thanh ghi RCREG.
*Bc 9 : Nu c li overrun xy ra , xa c OERR bng cch xa bit CREN.
5.Cng thc tnh tc baud rate :
Trong :
FOSC l tn s hot ng ca vi iu khin .
n=SPBRGH:SPBRG
V d : Tnh tc baud 9600 ,vi iu kin cc bit khi to nh sau :
SYNC=0 ; BRG16=1; BRGH=1; Fosc= 4Mhz
Khi theo bng ta c :
9600= 4(+1)
n=103
Do : SPBRG=103 , SPBRGH=0;
IV:BI TP THC HNH :
Bi 1 :Vit chng trnh truyn nhn UART ca vi iu khin vi my tnh , iu khin
hot ng ca led theo yu cu sau :
Vi iu khin nhn mt s t my tnh v iu khin hai led RE1 va RE2 vi 4 trng thi
Nhn s 1: Hai led tt , gi ln my tnh chui "Number 1".
Nhn s 2: Hai led sng, gi ln my tnh chui "Number 2".
Nhn s 3:Led RE1 sng,RE2 tt ,gi li my tnh chui "Number 3".
Nhn s 4:Led RE1 tt ,RE2 sng ,gi li my chui "Number 4".
S khc :Hai led cng chp tt vi chu k _delay(100000);gi li my tnh chui "Other
numbers".
78

Vi iu khin s dng thch anh ni 4MHz , tc baund : 9600 , truyn nhn 8 bit .
Cu hnh phn cng :

*Bc 2 : Nhp chng trnh sau vo my tnh v hon thnh vo du .
#include <htc.h>
#include <stdio.h>
__CONFIG(INTIO&WDTDIS&PWRTEN&MCLREN&UNPROTECT&DUNPROTECT&FC
MDIS&IESODIS&LVPDIS&BORDIS);
void send_string(char *s);
void send_char(char c);
char data ;
void main()
{
ANS6=ANS7=.;TRISE1=TRISE2=.; //Khi to RE1,RE2 l ng ra s
//Cu hnh truyn UART
TXEN=.;
//Cho php truyn
SYNC=.;
//Cu hnh nhn UART
SPEN =.;
//Cu hnh chn RX,TX ch truyn nhn UART
CREN=.;
//Khi to tc baund 9600=Fosc/(4*(n+1)) vi n=SPBRGH:SPBRG
BRG16=1;
//(--------1----------)
BRGH=1;
//(--------2----------)
SPBRG=103;SPBRGH=0;
//(--------3----------)
//Khi to ngt nhn
RCIE =.;
PEIE =.;
GIE =.;
while(1)
{
79

switch(data)
{
case 1:
RE1=RE2=.;send_string("Number 1\r");
break;
//Hai led tt
RE1=RE2=.;send_string("Number 2\r");
break;
//Hai led sng
case 2:
case 3:
RE1=0;RE2=.;
send_string("Number 3\r");
break;
//RE1 tt , RE2 sng
case 4:
RE1=.;RE2=.;
send_string("Numer 4\r");
//RE2 tt , RE1 sng
break;
default:
RE1^=.;RE2=RE1;
//Hai led cng chp tt.
send_string("Other numbers\r");
break;
}
_delay(100000);
}
}
{
if(RCIF)
{
data=RCREG;
}
}
void send_char(char c)
{
while(!TXIF);
TXREG=c;
}
void send_string(char *s)
{
while(*s)
send_char(*s++);
}
*Bc 3 : Np chng trnh vo kt th nghim , kt ni my tnh vi kt th nghim bng cng
COM(Nu s dng Laptop khng c cng COM th cn c cp USBCOM ).
80

*Bc 4 : S dng chng trnh Terminal (chng trnh dng test cng COM) truyn nhn k t
xung kit th nghim , ng thi quan st 2 led trn kit th nghim .
*Bc 5 : Chng minh thng s ca dng (1) , (2), (3).
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Bi 2 : Lm li bi 1 vi tc baud 14400 (To mt project mi vi tn 05_02_ MSSV).
V.BI TP T GII :
Bi 3 : Vit chng trnh truyn nhn UART ca vi iu khin vi my tnh , hin th kt
qu ln lcd theo s phn cng sau (To mt project mi vi tn 05_02_ MSSV):
Yu cu : Truyn mt chui s (ti a 5 ch s xxxxx) t my tnh xung vi iu khin , vi iu
khin hin th s va nhn c t my tnh ln lcd , ng thi gi li my tnh s va nhn
cng thm 10.Thch anh 4Mhz , baud 9600 , truyn nhn 8-bit , phn cng kt ni lcd theo th
vin lcd.h .
81

Bi 4 : Vit chng trnh truyn nhn gia vi iu khin v my tinh vi cc yu cu sau :
My tnh truyn xung vi iu khin k t S , ng c start.
My tnh truyn xung vi iu khin k t P , ng c stop.
My tnh truyn xung vi iu khin k t B-xxx , ng c quay thun ,vi xxx l
rng xung PWM 8 bit .
My tnh truyn xung vi iu khin k t F-xxx , ng c quay nghch , vi xxx l
rng xung PWM 8 bit .
Bi 5 : Vit chng trnh truyn nhn gia my tnh v vi iu khin vi yu cu sau : my tnh
hin th vn tc ng c trn Terminal , baud 9600, Fosc = 4Mhz .
82
TI LIU THAM KHO :

[1] PIC16F882/883/884/886/887 Data Sheet
[2]Dogan lbrahim , Advanced PIC Microcontroller Projects in C
[3] 101 ASP Getting Started with PICmicro Mid-Range, Microchip
[4] Ti liu ging dy R&P
83
PH LC
I.CA S CHNG TRNH :
Thanh Menu
Thanh Cng C
Ca s vit
chng trnh
II.CC BC KHI TO MT PROJECT MI:

1.To mt folder (A) cha tt c cc file chng trnh
2.Khi ng MPLAB : Chn Project , Project Wizard
84
3.Chn Next :
4.Chn dng PIC mun lp trnh , Next :

4
5.La chn cng c lp trnh ( y chn H-TECH) , Next:

Ch : Ch duy nht c dng H-TECH sau khi ci t thnh cng Hi-tech C.
85
6.Browse ti folder (A) , t tn cho bi lm (main), Next :
7.Nhn Next , chn Finish:
10
86

8.Chn NewFile thanh cng c , vit on chng trnh #include<htc.h> trong MPLAB
IDE Editor , chn Save :
11
13
12
9.t tn main.c (Ch : phi c .c v Save in th mc A) ,chn save :

14
15
16
87

10.Right click vo Source file ca s main.mcw chn Add files , Browse ti main.c
chn open :
17
18
11.Hon tt to mt project , tip tc vit chng trnh .
II.HI TECH C C BN:

1.Khai bo bin :
<Kiu bin > <Tn bin > ;
Kiu bin :
Kiu bin
bit
char
signed char
int
unsigned int
short int
signed short int
Kch thc (bit)

1
8
8
16
16
8
8
Tm gi tr
0,1(false, true)
0 = >255
-128=>127
-32768 => 32767
0=>65535
0=>255
-128=>127
88

long int
signed long int
float
double
32
32
32
32
0=>4294967295
-2147483648=>2147483647
1.755 .10-38 =>6.8056.1038
1.755 .10-38 =>6.8056.1038
Tn bin :
Tn bin bao gm cc k t t A ti Z ,cc s t 0 ti 9 v du _ , tn bin khng bt
u vi mt s v khng trng vi t kha .
V d :
char bien_1, bien_2;

signed char bien3=5;
int bien4=bien5=3;
2.Kiu con tr :
Khai bo con tr :
<Kiu con tr >
*<Tn con tr> ;
Kiu con tr : Ging kiu bin.

Tn con tr : Ging tn bin .
V d :
unsigned int *con_tro;
con_tro = &bien1;
//Con tr tr ti bin mang tn 1
*con_tro = 6 ;
//Gn s 6 cho bin 1 , tng ng bien1=6;
bien2 = *con_tro ;
//gn gi tr m bien1 ang cha cho bien2 ;
//Tng ng vi : bien2=bien1;
3.Kiu enum:
V d
enum motor{up,down,left,right};
Kh : gi tr cc bin s l
motor(up) = 0
motor(down)= 1
motor(left) = 2
motor(right)=3
89

4.Php ton hc :
Php ton
Cng
Tr
Nhn
Chia
Chia ly d
K hiu
+
*
/
%
5.Php ton gn :
Ton t
+=
-=
*=
/=
%=
V d
Biu thc
a+=8
a-=8
a*=8
a/=8
a%=8
Bng
a=a+8
a=a-8
a=a*8
a=a/8
a=a%8
V d
++a
a++
--a
a--
Bng
Tng bin a ln 1 n v.
6.Php ton tng , gim :

Ton t
++
--
Gim bin a xung 1

n v.
7.Php ton quan h :

Php ton
>
>=
<
<=
==
!=
V d
b>a
b>=a
b<a
b<=a
b==a
b!=a
ngha
Ln hn
Ln hn hoc bng
B hn
B hn hoc bng
Bng
Khng bng
90

8.Tan t logic :
Ton t
AND
Tham s 2
0
1
0
1
OR
0
1
0
1
NOT
Tham s 1
0
0
1
1
&&
0
0
1
1
||
Kt qu
0
0
0
1
0
1
1
1
0
1
1
0
9.Ton t theo bit :

Ton t
~
<<
>>
ngha
o bit
Dch tri
Dch phi
V d
a=~b
a=b<<2
a=b>>2
&
AND bit
c=a&b
OR bit
c=a|b
XOR bit
c=a^b
Kt qu
b=5
b=0b01011001
b=0b11101011
a=0b01101110
b=0b01101011
a=0b01101110
b=0b01101011
a=0b01101110
b=0b01101011
a=-5
a=0b01100100
b=0b00010110
c=0b01101010
c=0b01101111
c=0b00000101
10.Chn mt on code Assembly :

Trong C ta cng c th chn mt on code Assembly bt k vo bng cu lnh sau :
V d :
unsigned int b=0;
asm
{
MOVE maximun,W
..............................
}
b =10;
91

11.Cc ton t u tin :
12.Cu iu kin :
Cu iu kin c hai dng sau : if hoc if-else
Dng if :
if(<iu kin>)cu lnh ;
Nu <iu kin> ng th cu lnh c thc hin .
Nu <iu kin> sai th cu lnh khng c thc hin .
V d :
char a,b;
a=1, b=5;
if(a==1)
a=5;
b=6;
Kt qu : a=5 , b=6
Dng if-else :
if(<iu kin>)cu lnh 1 ; else cu lnh 2;
92
Nu <iu kin> ng th cu lnh 1 c thc hin , cu lnh 2 khng c thc hin.

Nu <iu kin> sai th cu lnh 1 khng c thc hin , cu lnh 2 c thc hin .
Quy c s 0 = false , v s khc khng = true .
V d :
char a,b;
a=1;b=5;
if(a==1)
a=5
else
b=6;
Kt qu : a=5 , b=5 .
Nu trong cu lnh 1 c t 2 cu lnh tr ln ta phi t chng trong du ngoc {}
if(<iu kin>)
{cu lnh 1; cu lnh 2 ; cu lnh 3 ;}
else
{cu lnh 4 ; cu lnh 5;}
V d :
char a,b
c=1 ; b=5;
if(a==1)
{
a=5;
b=6;
}
else
b=3;
Kt qu : a=5 , b=6.
Ch :
char a,b;
a=1;b=5;
if(a==1)
a=5;
b=6;
else
93

b=3;
Kt qu : bin dch bo li .
Ton t if-else c th thay th bng ton t ?
(iu kin)?cu lnh 1: cu lnh 2;
Nu iu kin = true th cu lnh 1 c thc hin.
Nu iu kin = false th cu lnh 2 c thc hin .
13.Ton t la chn :
Khc vi cu lnh if-else ch cho la chn mt trong hai thuc tnh , th switch case cho
la chn mt vo thuc tnh .
switch(<la chn>)
{
case hng 1:
cu lnh 1:
..................
break;
case hng 2 :
cu lnh 5 ;
..................
break ;
default :
cu lnh n ;
..................
}
Nu biu thc <la

chn> = hng
1 th cu lnh 1 c
thc hin .
Nu biu thc <la chn> = hng 2 th cu lnh 2 c thc hin .
Nu biu thc <la chn> != hng 1 , hng 2 th cu lnh n c thc hin.
94

14.Vng lp:
14.1 while:
while(<biu thc iu kin>)

{
lnh 1;
lnh 2;
............
lnh n ;
}
Nu biu thc iu kin ng th : lnh 1 , lnh 2 ............lnh n c thc hin , sau
quay li kim tra biu thc iu kin.
Nu biu thc iu kin sai th lnh 1, 2 .......lnh n khng c thc hin , v thot ra
ngoi thc hin dng lnh tip theo lnh while .
V d :
char a=3;
while(a<=19)
{
a+=5;
}
Kt qu : a=18
14.2 do_while:
do
lnh 1;
lnh 2;
...........
lnh n;
while(<iu kin>);
Vng lp do_while() thc hin lnh 1 , lnh 2,.....,lnh n , sau xt <iu kin>
Nu iu kin ng th tip tc lp li thc hin lnh 1 , lnh 2 ....lnh n.
Nu iu kin sai th thot ra ngoi v thc hin lnh tip theo lnh while .
Khc vi vng lp while , vng lp do_while thc hin lnh bn trong t nht 1 ln , nu
iu kin sai .
95

14.3 :Vng lp for :
for(<khi to biu thc >;<biu thc iu kin>;<thay i biu thc>)

{
lnh 1 ;
lnh 2;
............
lnh n ;
}
1. <Khi to biu thc>
2. Xt <biu thc iu kin> :
Nu <biu thc iu kin> ng th thc hin lnh 1 , lnh 2 ,....,lnh n , <thay i
biu thc >,tip tc xt<biu thc iu kin>
Nu<biu thc iu kin> sai th thot ra khi vng for.
V d :
unsigned int b=0;
for(int a=10;a<=15;a++)
{
b+=5;
}
Kt qu a=15 , b = 30 ;
15.Mng 1 chiu :
Khai bo :
<Kiu mng > <Tn mng >[<s phn t mng >] ;
Kiu mng = kiu bin
Tn mng = tn bin 2
S phn t mng = s nguyn.
V d :
char mang[4]={2,4,7,5};
Khi :
mang[0]=2, mang[1]=4, mang[2]=7,mang[3]=5
96

16.Mng hai chiu :
<Kiu mng > <Tn mng>[<s hng>][<s ct>];

V d :
int table[3][4];
Khi :
table[0][0]
table[1][0]
table[2][0]
table[0][1]
table[1][1]
table[2][1]
table[0][2]
table[1][2]
table[2][2]
table[0][3]
table[1][3]
table[2][3]
17.Cu trc ca mt chng trnh c c bn :

#include<htc.h>
__CONFIG(INTIO&WDTDIS&PWRTEN&MCLREN&UNPROTECT&DUNPROTEC
T&BORDIS&IESODIS&FCMDIS&LVPDIS)//
//Khai bo bin ton cc
//Khi bo tn chng trnh con
void main()
{
//khai bo bin cc b cho chng trnh void main
//khi to chc nng cho vi iu khin
while(1); //Lp v tn .
}
//Nm trong chng trnh con khai bo trn .
97

IV.S NGUYN L KIT TH NGHIM:
98
99
100

V.FILE LCD :
1.lcd.c:
#include <stdlib.h>
#include <ctype.h>
#include "lcd.h"
unsigned char i ;
void lcd_init()
{
unsigned char i;
LCD_EN_TRIS = 0;
LCD_RS_TRIS = 0;
LCD_RW_TRIS = 0;
LCD_DATA4_TRIS = 0;
LCD_DATA5_TRIS = 0;
LCD_DATA6_TRIS = 0;
LCD_DATA7_TRIS = 0;
LCD_EN = 0;
LCD_RS = 0;
LCD_RW = 0;
for(i=0;i<10;i++){Nop();}
// delay for power on
// reset LCD
lcd_put_byte(0,0x30);
for(i=0;i<5;i++){Nop();}
for(i=0;i<5;i++){Nop();}
for(i=0;i<10;i++){Nop();}
for(i=0;i<10;i++){Nop();}
for(i=0;i<10;i++){Nop();}
//
//
//
__delay_ms(100);
__delay_ms(100);
__delay_ms(100);
// delay for LCD reset

while(lcd_busy());
lcd_put_byte(0,FOUR_BIT & LINES_5X7);
// Set LCD
type
101

while(lcd_busy());
lcd_put_byte(0,DOFF&CURSOR_OFF&BLINK_OFF);
while(lcd_busy());
lcd_put_byte(0,DON&CURSOR_OFF&BLINK_OFF);
while(lcd_busy());
and move cursor to home
while(lcd_busy());
lcd_put_byte(0,SHIFT_CUR_LEFT);
mode
while(lcd_busy());
and move cursor to home
while(lcd_busy());
}
unsigned char lcd_busy()
{
unsigned char busy;
// display off
// display on
// clear display
// cursor shift
// clear display
LCD_DATA4_TRIS = 1;
LCD_DATA5_TRIS = 1;
LCD_DATA6_TRIS = 1;
LCD_DATA7_TRIS = 1;
LCD_RW = 1;
LCD_RS = 0;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
busy = LCD_DATA7;
LCD_EN = 0;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
102

//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 0;
return busy;
}
unsigned char lcd_get_byte(unsigned char rs)
{
BYTE_VAL b;
LCD_DATA4_TRIS = 1;
LCD_DATA5_TRIS = 1;
LCD_DATA6_TRIS = 1;
LCD_DATA7_TRIS = 1;
LCD_RW = 1;
LCD_RS = 0;
if(rs) LCD_RS = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
b.bits.b7 = LCD_DATA7;
LCD_EN = 0;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
103

LCD_EN = 0;
return b.Val;
}
void lcd_put_byte(unsigned char rs, unsigned char b)
{
BYTE_VAL temp;
LCD_DATA4_TRIS = 0;
LCD_DATA5_TRIS = 0;
LCD_DATA6_TRIS = 0;
LCD_DATA7_TRIS = 0;
LCD_RS = 0;
if(rs) LCD_RS = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_RW = 0;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 0;
temp.Val = b;
// send the high nibble
LCD_DATA4 = temp.bits.b4;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 0;
// send the low nibble
104

//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 1;
//
__delay_us(20);
for(i=0;i<2;i++){Nop();}
LCD_EN = 0;
}
void lcd_putc(char c){
switch(c){
case '\f':
lcd_put_byte(0, 1);
while(lcd_busy());
break;
case '\n':
lcd_gotoxy(0, 1);
break;
default:
if(isprint(c)){
lcd_put_byte(1, c);
while(lcd_busy());
}
break;
}
}
void lcd_gotoxy(unsigned char col, unsigned char row)
{
unsigned char address;
if(row!=0)
address=0x40;
else
address=0;
address += col;
lcd_put_byte(0,0x80|address);
while(lcd_busy());
}
void lcd_puts(const char* s)
105

{
while(*s)
{l
cd_putc(*s++);
}
}
2.lcd.h:
#ifndef _LCD_H_
#define _LCD_H_
#include <p24fxxxx.h>
//#ifndef _XTAL_FREQ
//#define _XTAL_FREQ
20000000
#endif
/* Display ON/OFF Control defines */
#define DON
0b00001111 /* Display on
*/
#define DOFF
0b00001011 /* Display off */
#define CURSOR_ON 0b00001111 /* Cursor on
*/
#define CURSOR_OFF 0b00001101 /* Cursor off
*/
#define BLINK_ON 0b00001111 /* Cursor Blink */
#define BLINK_OFF 0b00001110 /* Cursor No Blink */
/* Cursor or Display Shift defines */
#define SHIFT_CUR_LEFT 0b00000100 /* Cursor shifts to the left */
#define SHIFT_CUR_RIGHT 0b00000101 /* Cursor shifts to the right */
#define SHIFT_DISP_LEFT 0b00000110 /* Display shifts to the left */
#define SHIFT_DISP_RIGHT 0b00000111 /* Display shifts to the right */
/* Function Set defines */
#define FOUR_BIT 0b00101100 /* 4-bit Interface
*/
#define EIGHT_BIT 0b00111100 /* 8-bit Interface
*/
#define LINE_5X7 0b00110000 /* 5x7 characters, single line */
#define LINE_5X10 0b00110100 /* 5x10 characters
*/
#define LINES_5X7 0b00111000 /* 5x7 characters, multiple line */
/* Pins mapping */
#ifndef
LCD_RS
#defineLCD_RS
PORTDbits.RD1
#defineLCD_EN
PORTDbits.RD3
#defineLCD_RW
PORTDbits.RD2
#defineLCD_DATA4 PORTDbits.RD4
106

#defineLCD_RS_TRIS
#defineLCD_EN_TRIS
#defineLCD_RW_TRIS
#defineLCD_DATA4_TRIS
#endif
//typedef unsigned char
typedef union _BYTE_VAL
{
unsigned char Val;
struct
{
unsigned char b0:1;
unsigned char b1:1;
unsigned char b2:1;
unsigned char b3:1;
unsigned char b4:1;
unsigned char b5:1;
unsigned char b6:1;
unsigned char b7:1;
} bits;
} BYTE_VAL;
TRISDbits.TRISD1
TRISDbits.TRISD3
TRISDbits.TRISD2
TRISDbits.TRISD4
TRISDbits.TRISD5
TRISDbits.TRISD6
TRISDbits.TRISD7
unsigned char;
// 8-bit unsigned
void lcd_init();
unsigned char lcd_busy();
unsigned char lcd_get_byte(unsigned char rs);
void lcd_put_byte(unsigned char a,unsigned char b);
void lcd_gotoxy(unsigned char col, unsigned char row);
void lcd_putc(char c);
void lcd_puts(const char* s);
//#endif
107

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Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

2.Thanh ghi khi to khi CCP2 .......................................................................................... 63

Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

CHNG I : PHN CNG PIC16F

Hnh 1: Kin trc b nh kiu Von Neuman

Gio trnh th nghim vi iu khin ng dng

Hnh 2: Kin trc b nh kiu Von Neuman

Hnh 3: Quy trnh thc thi cc lnh

Gio trnh th nghim vi iu khin ng dng

Hnh 4: Thc hin lnh trong chu k u tin

Hnh 5: Thc hin lnh trong chu k th hai

Gio trnh th nghim vi iu khin ng dng

Hnh 6:Thc hin lnh trong chu k th ba

Hnh 7: Thc hin lnh trong chu k th 4

Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

Hnh 8: Quy trnh thc thi lnh LDAA

Hnh 9: Thc thi mt cng vic ch vi mt t lnh

Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

Hnh 10: V tr cc chn trong chun ICSP

Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

Hnh 11: S khi FSCM trong PIC16F887

Gio trnh th nghim vi iu khin ng dng

Hnh 12: Quy trnh hot ng khi FSCM

Gio trnh th nghim vi iu khin ng dng

Hnh 13: S tn hiu in p Brown out

Gio trnh th nghim vi iu khin ng dng

// BOD and SBOREN disabled

Hnh 14: Kt ni phn cng khi s dng ch Master clear

Gio trnh th nghim vi iu khin ng dng

Hnh 15: Khi Watch dog timer trong Vi iu khin

Gio trnh th nghim vi iu khin ng dng

Hnh 16: S khi dao ng bn trong vi iu khin

Gio trnh th nghim vi iu khin ng dng

Hnh 17: S s dng thch anh ngoi, tn s cao

Hnh 18: Ch s dng clock ngoi vi mt chn clock

Hnh 18: Dao ng dng t v in tr

Gio trnh th nghim vi iu khin ng dng

Gio trnh th nghim vi iu khin ng dng

CHNG II: XUT NHP I/O PORT

Hnh 19: Cc chn c th x l tn hiu s

Hnh 20: Cc chn c th x l tn hiu tng t

Nhng chn c k hiu ANX l nhng chn va c th x l tn hiu s va c th x l tn

Gio trnh th nghim vi iu khin ng dng

TRISXY=0:Quy nh bit th Y ca PORTX l ng ra (0 = Output)

RXY=0 : Quy nh chn th Y ca PORTX l mc thp(VL).

Gio trnh th nghim vi iu khin ng dng

Hnh 21: ng dng x l tn hiu s

WPUBy=0: Khng cho php in tr ko ln chn th y ca PORTB.

Gio trnh th nghim vi iu khin ng dng

Hnh 22: S ngt INT chn RB0

Gio trnh th nghim vi iu khin ng dng

Hnh 23: S ngt on-change PORTB

IOCBX=0 : Khng cho php ngt on-change chn th X ca PORTB.

Gio trnh th nghim vi iu khin ng dng

//c thanh ghi PORTB.

4.4.Bng so snh gia ngt INT v ngt on-change :

IV.BI TP THC HNH :

Gio trnh th nghim vi iu khin ng dng

RB_0( );//Chy chng trnh con RB_0