Thit k v tng hp h thng s 2012 (C) nguyenducminh@edabk.org (www.edabk.org) ddas.edabk.

org

1 Chng 1: Gii thiu thit k mch s

1.1 1.1 Cc khi nim c bn trong thit k mch s
1.1.1 1.1.1 nh ngha: mch in t l mt h thng gm cc linh kin in t bin i tn hiu (dng in, in p) u vo thnh tn hiu u ra 1.1.1.1 m t mch in t: cn m t tn hiu u vo, tn hiu u ra, v hm truyn t ca mch 1.1.2 1.1.2 Phn loi 1.1.2.1 Mch tng t 1.1.2.2 Mch s Tn hiu vo/ra ch c 2 mc thp v mc cao Mc 0,1 Mch s t hp Hm truyn t ch ph thuc vo u vo Mch s tun t (Mch dy) Hm truyn t ph thuc vo u vo v trng thi hin ti ca mch Mch ng b Trng thi ca mch c lu vo Flip Flop theo mt tn hiu nhp (tn hiu ng h)

Mch khng ng b Trng thi v hot ng ca mch khng theo ng h

1.1.3 1.1.3. i s Bool v logic t hp 1.1.3.1 Bin Bool Bin n a,b,x,y nhn cc gi tr 0,1 Bin vector a[3:0] nhn cc gi tr {0,1}^4 1.1.3.2 Hm Bool

Nhiu u vo, mt u ra: MISO Nhiu u vo, nhiu u ra: MIMO Biu din hm Bool Biu thc Bool gm Cc bin Bool Cc php ton Bool
AND, OR, NOT, XOR

Bng chn l Lit k tt c cc t hp gi tr ca cc bin u vo Lit k cc gi tr hm tng ng L cch biu din duy nht Kch thc rt ln ~ hm m ca s bin Bng chn l rt gn
Kch thc nh hn Khng l duy nht

Ch c th dng cho cc mch n gin, t u vo

Ti u hm Bool Dng cch ti gin ba Karnaugh http://en.wikipedia.org/wiki/Karnaugh_map See document(s): Karnaugh_map

Dng phng php Quine-McCluskey http://en.wikipedia.org/wiki/Quine%E2%80%93McCluskey_algorithm See document(s): Quine%E2%80%93McCluskey_algorithm

Trin khai hm Bool bng mch logic t hp Gm cc cng logic cn bn kt ni vi nhau to thnh hm truyn t Kch thc ~ tuyn tnh vi s php ton dng trong hm truyn t

1.1.3.3 V d: B gii m 7 thanh B cng 1.1.4 1.1.4. My trng thi hu hn FSM 1.1.4.1 Hm truyn t Hm trng thi k tip Delta s' = delta(x,s) s' trng thi tip theo ca mch s trng thi hin ti ca mch x l u vo ca mch

Hm u ra Lambda Mealy: y = lambda(x,s) More: y = lambda(s) 1.1.4.2 Biu din FSM

th chuyn trng thi Node: cc trng thi c dn nhn l m trng thi tng ng

Cnh: chuyn trng thi c dn nhn l gi tr u vo tng ng Kch thc ~ s trng thi ~ hm m ca s bin trng thi Bng chuyn trng thi v bng u ra 1.1.4.3 Ti u FSM

Gim s lng trng thi Tm cc trng thi tng ng M ha trng thi M one-hot, zero-hot, binary, gray 1.1.4.4 Trin khai FSM-Mch dy

M ha cc trng thi, cc k hiu vo v cc k hiu ra bng cc bin Bool trng thi, tn hiu vo v tn hiu ra, tng ng Xc nh hm Bool cho trng thi k tip v cho u ra Mch t hp trng thi k tip Cc Flip Flop Mch t hp ra

1.1.4.5 V d B m B iu khin n giao thng

B iu khin thang my B iu khin giao thc RS232, Bluetooth 1.1.5 1.1.5. Cc phn t phn cng c bn 1.1.5.1 Transitor FET

1.1.5.2 Cng logic c bn

1.1.5.3 Gate Netlist: mng cng

1.1.5.4 Standard Cell

Cell: Phn t logic c bn, cc khi chc nng c bn RAM, ROM... Cu trc m t quy trnh sn xut Chc nng logic M hnh tnh thi gian IC c chia lm cc hng v ct Mi phn t t mt phn t logic c bn: Cng logic, RAM, ... Cc cell c kt ni thng qua dy kim loi 1.1.5.5 FPGA

Phn cng c th ti cu hnh: reconfigurable Khi c bn LUT, LE: gm b chn MUX v SRAM B nh lu bng chn l ca hm Trin khai hm logic Gi tr b nh dng iu khin b MUX Cc khi c ni bng ng dy c th lp trnh

1.2 1.2. Gii thiu v HDL

1.2.1 1.2.1. Ngn ng m t phn cng (Hardware Description Language) 1.2.1.1 Mc ch M hnh v m phng (c thi gian) thit k s C th tng hp thnh mch bng cc cng c tng hp Synopsys Design Compiler Altera Quatus Xilinx ISE Cadence 1.2.1.2 Phn loi Verilog Mm do S dng nhiu trong cng nghip VHDL S dng trong quc phng v thit k t Hng kiu mnh 1.2.1.3 u im ca HDL Cho php thit k mch rt ln Tru tng hn s mch M t mc RTL-dch chuyn thanh ghi

S dng bit vector thay v cc bit n

Qu trnh tng hp t ng s dng phn mm EDA Thit k c th chuyn i

Thit k Verilog m t hnh vi hoc dng d liu c th tng hp thnh mch dng cng ngh ch to mi vi t cng sc (VD. T 0.13um sang 45nm) Verilog dng text, d dng chuyn i gia cc chng trnh khc nhau khng nh nh dng nh phn dng ring cho cc chng trnh v mch Cho php th nghim, la chn nhiu gii php thit k hn

Cc ty chn tng hp cho php ti u v cn bng cc tham s v nng lng, thi gian, kch thc Cho php kim nghim thit k tt hn Dng Verilog m hnh ha mi trng hot ng ca mch (testbench) Phn mm tng hp hot ng tt m bo tnh ng n ca hm Bool c trin khai 1.2.1.4 Ch Trng ging ngn ng lp trnh Khng phi ngn ng lp trnh Lun phi nh rng ang m t phn cng M c dng tng hp ra phn cng M c th c m phng trn my tnh, ch l mc ch th 2 1.2.2 1.2.2. V d v cc khi nim ngn ng c bn 1.2.2.1 module decoder_2_to_4 (A, D) ; input [1:0] A ; output [3:0] D ; assign D = (A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 ; assign D[0] = (~A[1])*(~A[2]); endmodule

1.2.2.2 Mt mch in l 1 module, c m t gm cc thnh phn Khai bo module Tn decoder_2_to_4

u vo, u ra Ports A, D

Khai bo tn hiu kt ni vi u vo u ra Kiu port Input Output Inout

Kch thc port v hng (n) vector

[MSB:LSB]

Khai bo tn hiu bn trong M t hot ng ca module (A ==

assign D = (A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 ;

1.2.3 1.2.3. Gii thiu v phn mm Quartus 1.2.3.1 http://www.youtube.com/watch?v=PDOTLuuKgqE See document(s): watch 1.2.3.2 http://www.youtube.com/watch?v=PDOTLuuKgqE See document(s): watch

1.2.4 1.2.4. Khi nim m phng v tng hp 1.2.4.1 M phng a tc ng u vo (input stimuli) v quan st so snh u ra vi u ra chun (output reference) Hnh v

Kim tra mch chim 90% cng sc, gi thnh lm ra mch 1.2.4.2 Tng hp

T m t hot ng mch to ra phn cng thc hin hot ng Hnh v

cng

Ch Khc vi chy chng trnh phn mm tt c cc cu lnh u c tng hp thnh phn Hc bit cc cu lnh Verilog HDL c chuyn thnh phn cng th no Hnh v

1.3 1.3. Lu thit k h thng s dng ngn ng m t phn cng

1.3.1 Hnh v

1.3.1.1

1.3.2 Chia lm 2 cng on chnh 1.3.2.1 Front-end Thit k mc hot ng, mc logic B1. Xc nh cc tham s k thut ca mch Hiu nng Tn s hot ng Thng lng d liu (Data throughput)

Chc nng logic ca mch V d: Thc hin php cng, thc hin php bin i FFT

B2. Phn tch chc nng v chia thnh cc khi chc nng nh (thit k s khi)

B3. M t hot ng cc khi chc nng bng ngn ng HDL Kim tra m phng tng khi chc nng Kim chng ton hc cc khi chc nng B4. Ghp ni cc khi chc nng thnh ton b h thng Kim tra m phng ton b h thng B5. Tng hp mch t mc HDL thnh mc cng Kim tra cc yu cu thi gian ca mch Kim chng s tng ng ca mch mc cng v mc HDL 1.3.2.2 Back-end

Thit k mc vt l

1.4 1.4. ng dng v v d v thit k s

1.4.1 Thit k b x l MIPS pipelined 1.4.1.1 Chc nng Thc hin cc chng trnh assembly theo kin trc tp lnh MIPS add, sub, addi beq, bne j lw, sw Pipeline 5 trng thi Chng trnh c lu trong b nh chng trnh (b nh lnh) D liu lu trong b nh d liu 1.4.2 Thit k b truyn nhn s QAM16 1.4.2.1 Chc nng iu ch u vo: Dng s 1 bit

u ra: Dng tn hiu I/Q iu ch theo phng php QAM Gii iu ch u vo: Dng tn hiu I/Q iu ch theo phng php QAM u ra: Dng s 1 bit Ty chn Dng tn hiu I/Q cn c nhn vi tn hiu sng mang Tn hiu sng mang c th c bin i thnh tng t bng b DAC Tn hiu thu c tng t c bin i thnh s dng ADC Tin hiu s thu c cn c ng b v nhn vi sng mang sau gii iu ch

2 Chng 2. Cc khi nim c bn trong thit k s (n li). Tham kho: Digital Design and Computer Architecture
2.1 2.1 Mch logic t hp
2.1.1 2.1.1 i s Bool 2.1.1.1 Biu thc v hm Bool Biu thc tng cc tch sum of product DNF

sum of minterm canonical form

Biu thc tch cc tng product of sum CNF

product of maxterm canonical form

Tham kho

Mc 2.2 2.1.1.2 Php ton v php bin i Bool

And, or, not, xor Tin trong i s Bool

Cc quy tc/nh l trong i s bool Quy tc AND/OR vi 1/0 Lut giao hon, kt hp, phn phi Bin i Demorgan nh l vi 1 bin

nh l nhiu bin

S dng php bin i Bool ti gin biu thc Bool 2.1.2 2.1.2 Trin khai hm Bool 2.1.2.1 Cc cng logic c bn

Tham kho Mc 1.5 sch nu Not

Buffer

And

Or

XOR, NAND, NOR, XNOR

2.1.2.2 T biu thc Bool n mch logic Tham kho Mc 2.4 Schematic, Gate-Net list Gm cc cng logic v cc dy dn ni cc cng logic V d Cng logic: cc node trong th Dy dn: cc cnh c hng trong th Input: cc node khng c node pha trc Output: cc node khng c node pha sau Fanout: Cc node ni vo cnh i ra khi mt node Fanin: Cc node ni vo cc cnh i vo node

Mch logic nhiu mc Tham kho Mc 2.5

2.1.3 2.1.3 Ti u hm Bool bng ba Karnaugh 2.1.3.1 Tham kho Mc 2.6 Mc 2.7 2.1.3.2 V d

2.1.4 2.1.4 Mt s hm Bool v mch n gin 2.1.4.1 Hm la chn v b MUX Trin khai b MUX 4-1

Hnh v b MUX 2-1

S dng b MUX thc hin cc hm logic

2.1.4.2 Hm gii m v b gii m B Decoder 2:4

2.1.4.3 Tham kho Mc 2.8 2.1.5 2.1.5 Hot ng ca mch logic 2.1.5.1 Biu thi gian Sn ln: tn hiu thay i t mc logic thp ln mc logic cao Sn xung: tn hiu thay i t mc logic cao xung mc logic thp

im 50%: thi im tn hiu thay i gi tr c 50% Hnh v

2.1.5.2 Thi gian Thi gian p ng ca 1 cng logic: Khong thi gian t lc u vo thay i n khi u ra thay i tng ng o t im 50% ca tn hiu vo ti im 50% ca tn hiu ra tr lan truyn (propagation delay) tpd Thi gian t lc 1 u vo thay i n khi u ra/cc u ra t ti gi tr cui cng trod = count t pdf of logic i train koreroing door what tr nh hng (contamination delay) tcd Thi gian t khi 1 u vo thay i n khi u ra bt u thay i tainted ong logic i train origin gain. what Hnh v

Thi gian chuyn i (transition time)

Thi gian tn hiu chuyn t trng thi 1->0 (falling time), v 0->1 (rising time): o bng khong cch gia 2 im 10%-90% ca tn hiu 2.1.5.3 ng ti hn (ng di nht) - critical path v ng ngn nht ng di nht v chm nht trong mch t hp Tr lan truyn tpd l tng tr lan truyn ca cc cng logic trn ng di nht Tr nh hng tcd l tng cc tr nh hng ca cc cng logic trn ng ngn nht V d

Hnh v

2.1.5.4 Glitches/Hazards 1 s thay i ca u vo dn ti nhiu s thay i u ra m khng ph hp/tng ng vi hm logic Hnh v

Loi tr nh hng ca hazards i n khi u ra n nh Thm cng logic kt ni cc prime implicants cch nhau

2.1.5.5 Tham kho Mc 2.9

2.2 2.2 Mch dy

2.2.1 2.2.1 Cc phn t nh c bn 2.2.1.1 Cu trc Phn t cht SR

Phn t cht D

Thay i trng thi khi CLK = 1 (level sensitive latch) Phn t D-Flip Flop Thay i trng thi khi c sn ln ca CLK

2.2.1.2 M t hot ng Lu tr trng thi Chuyn i trng thi 2.2.1.3 Mch hot ng theo ng h h Tham kho 3.3 Cc phn t nh trong mch thay i trng thi ti cc sn ln (xung) ca tn hiu ng Hnh v

2.2.1.4 Tham kho

Mc 3.2 2.2.1.5 Thc hnh

Lab 3

ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Logic/DE2/ verilog/lab3_Verilog.pdf See document(s): lab3_Verilog.pdf

2.2.2 2.2.2 My trng thi hu hn - FSM 2.2.2.1 Hm Bool biu din FSM Hm chuyn trng thi Hm trng thi k tip Delta s' = delta(x,s)
s' trng thi tip theo ca mch s trng thi hin ti ca mch x l u vo ca mch

Hm u ra Hm u ra Lambda Mealy: y = lambda(x,s) Moore: y = lambda(s)

2.2.2.2 Biu din FSM bng th chuyn trng thi STG Node: cc trng thi c dn nhn l m trng thi tng ng Cnh: chuyn trng thi c dn nhn l gi tr u vo tng ng Kch thc ~ s trng thi ~ hm m ca s bin trng thi 2.2.2.3 M ha trng thi bng bin Bool 2.2.2.4 Biu din hm chuyn trng thi bng bng chuyn trng thi 2.2.2.5 Tham kho Mc 3.4 2.2.2.6 Thc hnh Lab 4. Phn 1

ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Logic/DE2/ verilog/lab4_Verilog.pdf See document(s): lab4_Verilog.pdf

2.2.2.7 My Moore/Mealy

2.2.3 2.2.3 Thi gian trong mch dy 2.2.3.1 Thi gian trong Flip-Flop Setup time v hold time Khong thi gian u vo D cn n nh Tr lan truyn t ng h n Q: Tpdq Tr nh hng t ng h n Q: Tcdq Hnh v

2.2.3.2 Thi gian h thng Chu k ng h Khong thi gian gia 2 sn ln (xung) ca tn hiu ng h Tc 2.2.3.3 iu kin thi gian setup ng tr gia 2 thanh ghi

iu kin v thi gian setup Hnh v

Trong thc t

Chu k ng h quyt nh bi khch hng, th trng, v gim c k thut m bo tnh cnh tranh ca sn phm tsetup quyt nh bi nh sn xut cn thit k phn mch logic t hp tha mn iu kin thi gian setup 2.2.3.4 iu kin thi gian hold u vo D ca FF khng c thay i n thold sau sn ln (xung) ca clock Hnh v

3 Chng 3. C php c bn ca ngn ng Verilog Tham kho v d: http://www.asic-world.com

3.1 3.1. Ch thch
3.1.1 Gip c code d dng hn cho ngi khc v v sau 3.1.2 Gip g li d hn 3.1.3 Khng cn ch thch chc nng ca on code 3.1.3.1 Bn thn code chnh l lm vic nh th no nn khng cn ch thch na 3.1.3.2 V d

 always @(posedge clk) begin Sig_FF1 <= Sig // Capture value of Sig Line in FF Sig_FF2 <= Sig_FF1; // Flop Sig_FF1 to form Sig_FF2 Sig_FF3 <= Sig_FF2; // Flow Sig_FF2 to form Sig_FF3 end // start_bit is ~Sig_FF2 & Sig_FF3 assign start_bit = (~Sig_FF2 && Sig_FF3) ? 1b1 : 1b0; signet-atop-Frito-Pa.-start. bit 3.1.4 Ch thch ti sao lm mt vic 3.1.4.1 V d always @(posedge clk) /******************************************** * Sig is ansynchronous and has to be double flopped * * for meta-stability reasons prior to use *********************************************/ begin Sig_FF1 <= Sig; Sig_FF2 <= Sig_FF1; // double flopped meta-stability free Sig_FF3 <= Sig_FF2; // flop again for use in edge detection end /********************************************** * Start bit in protocol initiated by falling edge of Sig line * **********************************************/ assign start_bit = (~Sig_FF2 && Sig_FF3) ? 1b1 : 1b0; 3.1.5 Ch thch tng t ngn ng C 3.1.5.1 Nm gia /* */ 3.1.5.2 Bt u t // n cui dng

3.2 3.2. Khai bo module

3.2.1 Trong Verilog, 1 mch l 1 module 3.2.2 Hnh v 3.2.2.1

3.2.2.2

3.2.3 3.2.1. Khai bo module 3.2.3.1 C php module module_name (list_of_port) port_declare; internal_signal_declare; module_behavior_description endmodule 3.2.3.2 Tn module Khng c trng vi t kha Nn chn tn gi nh chc nng module 3.2.3.3 Cc cng vo ra 3.2.3.4 Cc tn hiu bn trong module 3.2.3.5 M t chc nng (hot ng) ca mch 3.2.4 3.2.2.Khai bo cng vo ra ca module 3.2.4.1 Mi cng vo ra tng ng vi 1 tn hiu trong mch 3.2.4.2 Khai bo kiu ca cng port_type: input output inout bidirectional

3.2.4.3 Kch thc ca cng v hng: mt bit: input cin; Vector: gm nhiu bit - ch ra kch thc c th trong 1 khong ch s [MSB:LSB] T bit gi tr ln nht n bit gi tr nh nht: t tri sang phi Ch : khng cn bt u t ch s khng output [7:0] out; input [0:4] in; 3.2.4.4 Tm li, khai bo 1 cng: port_type [range] port_name; 3.2.4.5 Bi tp v d: Khai bo module decoder 2:4 c tn hiu enable

3.3 3.3. Khai bo cc tn hiu/bin/hng bn trong mch

3.3.1 3.3.1 Cc gi tr d liu trong Verilog 3.3.1.1 Kiu logic C 4 gi tr 0: logic 0, iu kin sai 1: logic 1, iu kin ng x: khng xc nh: do cha c khi to hoc xung t Hnh v

z: tr khng cao: do khng c ni vi cng logic, hoc ni vi cng 3 trng thi Hnh v

Php ton trn logic 4 gi tr or Hnh v

and

not

3 trng thi

3.3.1.2 Kiu s nguyn C php chung <size>'<base><number> base nhn cc gi tr> b, d, h, o number c th l cc ch s (gi tr ph thuc c s) x z

size: ch ra kch thc (s bit) ca s. Nu khng c ch r th s l gi tr mc nh ca phn mm m phng V d 4'b1101 10'h2e7 12'h13x s m: -16'h3A

3.3.2 3.3.2 Khai bo bin/dy dn trong Verilog 3.3.2.1 Ch : Cc bin trong Verilog thng c dng i din cho 1 phn t vt l trong mch. V d: dy dn, cng logic, Flip-Flop 3.3.2.2 C php chung type range identifier array_range Tn bin: Identifier Chn tn c tnh miu t, gi nh Ch : Dng quy tc nht nh ch ra mt tn hiu l active-low type wire biu din dy dn trong mch
Khng lu tr gi tr Cn c ni vi cng Nhn gi tr ca cng iu khin n Kt ni u ra v u vo khi thc th ha cc module C th khai bo tn hiu input, output ca module l wire Khng th nm bn tri php gn = v <= trong khi always@ L kiu duy nht c th nm bn tri php gn dng assign Ch c th dng m t logic t hp

V d: rst_n

reg biu din cng logic/flip flop trong mch

lu tr gi tr cho n khi c gn gi tr mi ch khng nht thit l flip flop C th kt ni vi 1 cng vo ca 1 module con Khng th kt ni vi 1 cng ra ca 1 module con C th khai bo tn hiu output l reg

Khng th khai bo tn hiu input l reg L kiu duy nht nm bn tri php gn trong khi always v khi initial Khng th nm bn tri php gn assign m t thanh ghi nu nm bn tri php gn trong khi always@(posedge clk) Dng m t logic t hp v logic tun t

wor, trior wand, triand tri trireg range nh ngha kch thc ca bin vector tp hp cc bit

[msb:lsb] array_range dng nh ngha mt mng (miu t b nh, tp thanh ghi) [index_1:index_2] V d wire [15:0] opA, opB, res; reg [2:0] state, nxt_state; reg [31:0] reg_files[0:15] reg [31:0] mem[0:255] 3.3.3 3.3.3. Khai bo hng s trong Verilog 3.3.3.1 Tng tnh biu din, d hiu 3.3.3.2 Tng tnh mm do, d thay i 3.3.3.3 define

nh ngha hng s ton cc v d

`define idle = 2b00; // idle state of state machine `define conv = 2b01; // in this state while A2D converting `define avg = 2b10; // in this state while averaging samples 3.3.3.4 localparam nh ngha hng s a phng v d

localparam idle = 2b00; // idle state of state machine localparam conv = 2b01; // in this state while A2D converting localparam accum = 2b10; // in this state while averaging samples 3.3.3.5 parameter c th thay i khi tng hp mach cp sau

3.4 3.4. Cc m hnh m t mch

3.4.1 3.4.1. M hnh cu trc 3.4.1.1 Kt ni cc phn t c bn v cc module con 3.4.1.2 M t dng text ca mng module gm ng kt ni cc phn t trong mch Cc phn t trong mch Phn t logic c bn Flip-flop Cc module con 3.4.1.3 Cc bc to m hnh cu trc B1: Khai bo giao din module Tn module Tn cng, kiu v kch thc cng B2: Khai bo cc dy dn bn trong mch

dng kiu bin wire

B3: To module con hoc primitive. Kt ni - a tn dy dn vo v tr u vo, ra tng ng ca cng C php module_name instance_name [#(parameter values)] (port_connection_list)

port_connection_list Phng php kt ni n: da vo th t khai bo cng. Th t tn hiu khi to module con quyt nh cng ca module m tn hiu c ni vo.
Ch ph hp vi module t cng Cc cng vo ca module l ging nhau v vai tr (v d primitive) Khi s cng ln, d nhm ln V d

3.4.1.3..1.1.1.1 module dec_2_4_en (A, E_n, D); input [1:0] A; input E_n; output [3:0] D; . . . 3.4.1.3..1.1.1.2 wire [1:0] X; wire W_n; wire [3:0] word; // instantiate decoder dec_2_4_en DX (X, W_n, word);

Phng php kt ni r rng: ch r tn cng m tn hiu s c kt ni.

C php: .<port name>(<signal name>) V d

3.4.1.3..1.1.1.3 wire [1:0] X; wire W_n; wire [3:0] word; // instantiate decoder dec_2_4_en DX (.A(X), .E_n(W_n), .D(word));

3.4.1.4 Cc cng logic c bn (primitive) Gate level and, nand or, nor xor, xnor buf , not bufif0, bufif1, notif0, notif1 (three-state) Switch level

 *mos where * is n, p, c, rn, rp, rc; pullup, pulldown; *tran+ where * is (null), r and + (null), if0, if1 with both * and + not (null) Khng cn khai bo, ch s dng (instantiate) Khi s dng: u ra ng u tin, trc cc u vo

Example: and N25 (Z, A, B, C); //instance name Example: and #10 (Z, A, B, X); // delay (X, C, D, E); //delay /*Usually better to provide instance name for debugging.*/ Example: or N30 (SET, Q1, AB, N5), N41 (N25, ABC, R1); Example: and #10 N33(Z, A, B, X); // name + delay 3.4.1.5 V d V d 3.4.1

module majority (major, V1, V2, V3) ; output major ; input V1, V2, V3 ; wire N1, N2, N3; and A0 (N1, V1, V2), A1 (N2, V2, V3), A2 (N3, V3, V1); or Or0 (major, N1, N2, N3); endmodule

V d 3.4.2

module half_add (X, Y, S, C); input X, Y ; output S, C ; xor SUM (S, X, Y); and CARRY (C, X, Y); endmodule module full_add (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; wire S1, C1, C2; // build full adder from 2 half-adders half_add PARTSUM (A, B, S1, C1), SUM (S1, CI, S, C2); // add an OR gate for the carry or CARRY (CO, C2, C1); endmodule V d 3.4.3

 * module_keyword module_identifier (list of ports) */ module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declaration input E_n ; // input_declaration output [3:0] D ; // output_declaration assign D = {4{~E_n}} & ((A == 2'b00) ? 4'b0001 : (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 : 4'bxxxx) ; // continuous_assign endmodule module C_4_16_decoder_with_enable (A, E_n, D) ; input [3:0] A ; input E_n ; output [15:0] D ; wire [3:0] S; wire [3:0] S_n; C_2_4_decoder_with_enable DE (A[3:2], E_n, S); not N0 (S_n, S); C_2_4_decoder_with_enable D0 (A[1:0], S_n[0], D[3:0]); C_2_4_decoder_with_enable D1 (A[1:0], S_n[1], D[7:4]); C_2_4_decoder_with_enable D2 (A[1:0], S_n[2], D[11:8]); C_2_4_decoder_with_enable D3 (A[1:0], S_n[3], D[15:12]); endmodule 3.4.1.6 Bi tp Vit m hnh cu trc ca mch cng 16bit CRA v CLA s dng b cng full-adder To ra 20 gi tr u vo cho a, b M phng timing cho 2 mch o tr tpd cho tng gi tri u vo Tnh tr trung bnh cho 2 mch CRA v CLA, so snh 3.4.2 3.4.2. M hnh dng d liu - RTL 3.4.2.1 M t dng x l d liu Dng cu lnh gn lin tc assign gn biu thc bool cho bin wire cc php gn assign hot ng song song vi nhau php gn s c thc hin khi gi tr biu thc bn phi thay i M hnh chnh xc, nhng vn d c hiu Dng m t cc hm Bool v ng d liu Nhc im: phi da vo phn mm tng hp to ra mch Vi cch mch yu cu tc rt cao (GHz), vn cn m hnh cu trc 3.4.2.2 V d 3.4.3 V2 module majority (major, V1, V2, V3) ; output major ; input V1, V2, V3 ; assign major = V1 & | V2 & V3 | V1 & V3; endmodule

3.4.2.3 V d 3.4.4 module fa_rtl (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; // use continuous assignments assign S = A ^ B ^ CI; assign C0 = (A & B) | (A & CI) | (B & CI); endmodule 3.4.3 3.4.3. M hnh hnh vi 3.4.3.1 M t cc hnh vi ca mch khi c cc s kin (tn hiu thay i gi tr) xy ra Dng cc khi always v initial 3.4.3.2 V d 3.4.5 module majority (major, V1, V2, V3) ; output reg major ; input V1, V2, V3 ; always @(V1, V2, V3) begin if (V1 && V2 || V2 && V3 || V1 && V3) major = 1; else major = 0; end endmodule Trong m phng: khi c s thay i ca V1, V2, hay V3 th major s c tnh li

Trong phn cng: khng c ch i s xut hin s thay i=> cc cng logic tnh ton ngay lp tc 3.4.3.3 V d 3.4.6 module fa_bhv (A, B, CI, S, CO) ; input A, B, CI; output S, CO; reg S, CO; // assignment made in an always block // must be made to registers // use procedural assignments always@(A or B or CI) begin S = A ^ B ^ CI; CO = (A & B) | (A & CI) | (B & CI); end endmodule 3.4.3.4 Ch Khi m phng khi tn hiu u vo (bn phi php gn) thay i, u ra (bn tri php gn) c tnh ton li 3.4.4 3.4.4. Phn cp 3.4.4.1 Trong Verilog, mi khi (mch) l mt module. 3.4.4.2 Cc module c th c ti s dng bn trong mt module khc (instantiate)

3.4.4.3 Thit k phn cp xy dng h thng t cc phn t nh hn. y l phng php thit k top-down Primitives (cng logic c bn) Cc module khc 3.4.4.4 V d Thit k phn cp ca full-adder

Half-Adder

module Add_half(c_out, sum, a, b); output sum, c_out; input a, b; xor sum_bit(sum, a, b); and carry_bit(c_out, a, b); endmodule Full-Adder

module Add_full(c_out, sum, a, b, c_in) ; output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b)); Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1)); or carry_bit(c_out, w2, w3); endmodule 3.4.4.5 Ch : Trong mt module c th s dng nhiu loi m hnh m t Khi tng hp thnh mch, vic tnh ton khng cn ch i c kch hot. Tnh ton ng thi, c 3 loi m hnh u c tng hp thnh phn cng nh nhau

3.4.4.6 Ch : Phm vi ca tn hiu Module cha khng th truy cp vo cc tn hiu trong module con => cn phi a ra thnh cc cng ca module con V d module add8bit(cout, sum, a, b); output [7:0] sum; output cout; input [7:0] a, b; wire cout0, cout1, cout6; FA A0(cout0, sum[0], a[0], b[0], 1b0); FA A1(cout1, sum[1], a[1], b[1], cout0); FA A7(cout, sum[7], a[7], b[7], cout6); endmodule pht hin trn overflow = cout XOR cout6 Cn a ra tn hiu cout6 hoc overflow

3.4.4.7 Ch : Mi module nn a vo 1 file ring bit D t chc D tm kim D ti s dng trong project khc Tng tc tng hp khi ti s dng Hnh v Cc module cng trong 1 file

Mi module trong 1 file

3.5 3.5. Cc cu trc m t dng d liu

3.5.1 3.5.1. Php gn lin tc (continuous assignment) 3.5.1.1 C php assign [drive_strength] [delay] list_of_net_assignments; Where: list_of_net_assignment ::= net_assignment [{,net_assignment}] & Where: Net_assignment ::= net_lvalue = expression assign <LHS> = <RHS expression>;

Khi cc bin trong v phi thay i gi tr, kt qu biu thc RHS thay i, bin LHS c cp nht gi tr mi Php gn ny hot ng lin tc (hardware) v c tng hp thnh mch logic t hp Ch c mt trng hp ngoi l

Biu thc RHS s dng cc bin (dy dn, thanh ghi) v cc php ton: +,-,&,|,^,~,>>, LHS lun l cc bin kiu dy dn (wire) hoc php ton ni vector 3.5.1.2 V d 3.5.1: n gin

// out is a net, a & b are also nets assign out = a & b; // and gate functionality 3.5.1.3 V d 3.5.2: Gn vector

wire [15:0] result, src1, src2; // 3 16-bit wide vectors assign result = src1 ^ src2; // 16-bit wide XOR 3.5.1.4 V d 3.5.3: B cng 32 bit wire [31:0] sum, src1, src2; // 3 32-bit wide vectors assign {c_out,sum} = src1 + src2 + c_in; // wow!

3.5.2 3.5.2. Cc php ton 3.5.2.1 Ni cc vector To ra cc vector t cc vector nh hn hoc t bin n Operator {v1, v2} C php: {list_of_subvector} Cc vector pha tri ca danh sch cc vector con s c ngha cao hn cc vector pha phi V d 3.5.4 input [2:0] a; input [1:0] b, c; input d; output // assign out10 ={a[1:0],b,c,d,a[2]}[1:0]; endmodule

module concatenate(out, a, b, c, d); [9:0] out; assign out = {a[1:0],b,c,d,a[2]};

V d 3.5.5: S dng khi kt ni cng module

module add_concatenate(out, a, b, c, d); input [7:0] a; input [4:0] b; input [1:0] c; input d; output [7:0] out; add8bit(.sum(out), .cout(), .a(a), .b({b,c,d}), .cin()); // u vo 8 bit b ca b cng l 1 vector ghp t 3 vector b, c, d endmodule Thm hng s vo trc php ton {} Dng nhn bn bit V d 3.5.6: M rng du input [7:0] offset; // 8-bit offset term from EEPROM wire [15:0] src1,src2; // 16-bit source busses to ALU assign src1 = {8{offset[7]},offset}; // sign extend offset term // src1 = offset[7], offset[7], ..., offset[7], offset[7], offset[6], ..., offset[0] Ch php ton tch vector l [msb_index:lst_index] V d a[1:0] ly 2 bit thp ca vector a 3.5.2.2 Php ton s hc

* multiply ** exponent / divide % modulus + add - subtract D m t hn dng m hnh cu trc Khng phi tt c cc php ton u c th tng hp

V d: cc php ton *, **, /, % kh tng hp thnh mch logic, cho mch kch thc ln, tc chm Phn mm tng hp thng s dng th vin module c sn cho cc php ton Cn ch n kch thc kt qu nh hng n du ca php ton Kch thc (bitsize) quyt nh bi c 2 pha ca php ton V d 3.5.7: Cc php ton s hc

1 module arithmetic_operators(); 2 3 initial begin 4 $display (" 5 + 10 = %d", 5 + 10); 5 $display (" 5 - 10 = %d", 5 - 10); 6 $display (" 10 - 5 = %d", 10 - 5); 7 $display (" 10 * 5 = %d", 10 * 5); 8 $display (" 10 / 5 = %d", 10 / 5); 9 $display (" 10 / -5 = %d", 10 / -5); 10 $display (" 10 %s 3 = %d","%", 10 % 3); 11 $display (" +5 = %d", +5); 12 $display (" -5 = %d", -5); 13 #10 $finish; 14 end 15 16 endmodule 3.5.2.3 Php ton logic Php dch Dch tri S hc: <<< Logic: <<

Dch phi S hc: >>> Logic: >>

V d 3.5.8: Php dch 1 module shift_operators(); 2 3 initial begin 4 // Left Shift 5 $display (" 4'b1001 << 1 = %b", (4'b1001 << 1)); 6 $display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1)); 7 $display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1)); 8 // Right Shift 9 $display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1)); 10 $display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1)); 11 $display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1)); 12 #10 $finish; 13 end 14 15 endmodule

Php so snh Ln hn, nh hn: <, >, <=, >= Bng: ==, != C xt n gi tr x v z ===, !== ch dng khi m phng

V d 3.5.9: Php so snh 1 module relational_operators(); 2 3 initial begin 4 $display (" 5 <= 10 = %b", (5 <= 10)); 5 $display (" 5 >= 10 = %b", (5 >= 10)); 6 $display (" 1'bx <= 10 = %b", (1'bx <= 10)); 7 $display (" 1'bz <= 10 = %b", (1'bz <= 10)); 8 #10 $finish; 9 end 10 11 endmodule

V d 3.5.10: Php so snh bng 1 module equality_operators(); 2 3 initial begin 4 // Case Equality 5 $display (" 4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001)); 6 $display (" 4'bx0x1 === 4'bx001 = %b", (4'bx0x1 === 4'bx001)); 7 $display (" 4'bz0x1 === 4'bz0x1 = %b", (4'bz0x1 === 4'bz0x1)); 8 $display (" 4'bz0x1 === 4'bz001 = %b", (4'bz0x1 === 4'bz001)); 9 // Case Inequality 10 $display (" 4'bx0x1 !== 4'bx001 = %b", (4'bx0x1 ! == 4'bx001)); 11 $display (" 4'bz0x1 !== 4'bz001 = %b", (4'bz0x1 ! == 4'bz001)); 12 // Logical Equality 13 $display (" 5 == 10 = %b", (5 == 10)); 14 $display (" 5 == 5 = %b", (5 == 5)); 15 // Logical Inequality 16 $display (" 5 != 5 = %b", (5 ! = 5)); 17 $display (" 5 != 6 = %b", (5 ! = 6)); 18 #10 $finish; 19 end 20 21 endmodule

Php logic iu kin and: && or: || not: ! Dng trong biu thc iu kin. Tr v kt qu l 1 bit V d 3.5.11: Logic iu kin

 1 module logical_operators(); 2 3 initial begin 4 // Logical AND 5 $display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1)); 6 $display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0)); 7 $display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx)); 8 // Logical OR 9 $display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0)); 10 $display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0)); 11 $display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx)); 12 // Logical Negation 13 $display ("! 1'b1 = %b", ( ! 1'b1)); 14 $display ("! 1'b0 = %b", ( ! 1'b0)); 15 #10 $finish; 16 end 17 18 endmodule Php ton Bool and: & or: | xor: ^ not: ~ Tnh ton tng bit ca vector. Kt qu l vector V d 3.5.12: Php ton Bool 1 module bitwise_operators(); 2 3 initial begin 4 // Bit Wise Negation 5 $display (" ~4'b0001 = %b", (~4'b0001)); 6 $display (" ~4'bx001 = %b", (~4'bx001)); 7 $display (" ~4'bz001 = %b", (~4'bz001)); 8 // Bit Wise AND 9 $display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001)); 10 $display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001)); 11 $display (" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001)); 12 // Bit Wise OR 13 $display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001)); 14 $display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001)); 15 $display (" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001)); 16 // Bit Wise XOR 17 $display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001)); 18 $display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001)); 19 $display (" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001)); 20 // Bit Wise XNOR 21 $display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001)); 22 $display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001)); 23 $display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001)); 24 #10 $finish; 25 end 26 27 endmodule Php rt gn bit

Php ton 1 s hng. Thc hin php ton Bool vi cc ton hng l cc bit ca vector, tr v kt qu l 1 bit and: & nand: ~& or: | nor: ~|

xor: ^ V d 3.5.13: Php ton rt gn bit 1 module reduction_operators(); 2 3 initial begin 4 // Bit Wise AND reduction 5 $display (" & 4'b1001 = %b", (& 4'b1001)); 6 $display (" & 4'bx111 = %b", (& 4'bx111)); 7 $display (" & 4'bz111 = %b", (& 4'bz111)); 8 // Bit Wise NAND reduction 9 $display (" ~& 4'b1001 = %b", (~& 4'b1001)); 10 $display (" ~& 4'bx001 = %b", (~& 4'bx001)); 11 $display (" ~& 4'bz001 = %b", (~& 4'bz001)); 12 // Bit Wise OR reduction 13 $display (" | 4'b1001 = %b", (| 4'b1001)); 14 $display (" | 4'bx000 = %b", (| 4'bx000)); 15 $display (" | 4'bz000 = %b", (| 4'bz000)); 16 // Bit Wise NOR reduction 17 $display (" ~| 4'b1001 = %b", (~| 4'b1001)); 18 $display (" ~| 4'bx001 = %b", (~| 4'bx001)); 19 $display (" ~| 4'bz001 = %b", (~| 4'bz001)); 20 // Bit Wise XOR reduction 21 $display (" ^ 4'b1001 = %b", (^ 4'b1001)); 22 $display (" ^ 4'bx001 = %b", (^ 4'bx001)); 23 $display (" ^ 4'bz001 = %b", (^ 4'bz001)); 24 // Bit Wise XNOR 25 $display (" ~^ 4'b1001 = %b", (~^ 4'b1001)); 26 $display (" ~^ 4'bx001 = %b", (~^ 4'bx001)); 27 $display (" ~^ 4'bz001 = %b", (~^ 4'bz001)); 28 #10 $finish; 29 end 30 31 endmodule 3.5.2.4 Php ton iu kin

C php cond_expr ? true_expr : false_expr V d 3.5.14: Php ton c iu kin

1 module conditional_operator(); 2 3 wire out; 4 reg enable,data; 5 // Tri state buffer 6 assign out = (enable) ? data : 1'bz; 7 8 initial begin 9 $display ("time\t enable data out"); 10 $monitor ("%g\t %b %b %b",$time,enable,data,out); 11 enable = 0; 12 data = 0; 13 #1 data = 1; 14 #1 data = 0; 15 #1 enable = 1; 16 #1 data = 1; 17 #1 data = 0; 18 #1 enable = 0; 19 #10 $finish; 20 end 21 22 endmodule Ch khi m t latch? assign q_out = enable ? data_in : q_out; Kt qu tng hp

Ch : Lun lun cn bit m Verilog c tng hp thnh mch cng nh th no? 3.5.2.5 Th t u tin ca cc php ton

Unary, Multiply, Divide, Modulus !, ~, *, /, % Add, Subtract, Shift +, - , <<, >> Relation, Equality <,>,<=,>=,==,!=,===,!== Reduction &, !&,^,^~,|,~| Logic &&, || Conditional ? : 3.5.2.6 Bi tp 3.5.1.Tng hp cc php ton bng quartus Xc nh cc php ton h tr bi quartus So snh kch thc (LE) khi tng hp cc php ton So snh kch thc vi b cng CRA, CLA m t bng m hnh cu trc vi php cng So snh tr CRA, CLA vi php cng 3.5.2. Xy dng khi ALU 32 bit

u vo opA: 32 bit opB: 32 bit shamt: 5 bit func

= 0: cng =1: tr =2: nhn =3: so snh bng =4: dch tri s hc opA s bit m ha trong shamt =5: dch phi s hc opA s bit m ha trong s shamt =others: u ra = 0000

u ra res: 32 bit overflow zero=1: nu so snh bng nhau

a) Khi cha c php nhn xc nh s LE v tc b) Thm php nhn xc nh s LE v tc c) M phng kim tra kt qu vi t nht 5 cp s opA, opB cho mi php ton

3.6 3.6. Cc cu trc m t hnh vi

3.6.1 3.6.1. Mt s khi nim chung 3.6.1.1 Cu trc always/initial dng m hnh hot ng dng hnh vi ca mch 3.6.1.2 Tt c cc cu trc hnh vi khc u nm trong 2 khi always/initial 3.6.1.3 Nhiu cu trc hnh vi c th nm trong always/initial bng cch t gia begin v end 3.6.1.4 Tt c cc bin bn tri php gn trong 2 khi always/initial u phi l kiu reg 3.6.2 3.6.2. Cu trc initial

3.6.2.1 Bt u thc hin thi im m phng 0 3.6.2.2 C th c nhiu cu trc initial trong m, chng c thc hin c lp v u bt u thc hin thi im 0 3.6.2.3 Khng c tng hp thnh mch 3.6.2.4 Cc cu lnh trong khi initial c thc hin ln lt v c thc hin 1 ln 3.6.2.5 Ch yu c dng trong testbench 3.6.2.6 Ch : Khng dng initial trong m t mch 3.6.2.7 V d 3.6.1: Dng cu trc initial trong testbench `timescale 1 ns / 100 fs module full_adder_tb; reg [3:0] stim; wire s, c; full_adder(sum, carry, stim[2], stim[1], stim[0]); // instantiate DUT // monitor statement is special - only needs to be made once, initial $monitor(%t: s=%b c=%b stim=%b, $time, s, c, stim[2:0]); // tell our simulation when to stop initial #50 $stop; initial begin // stimulus generation for (stim = 4h0; stim < 4h8; stim = stim + 1) begin #5; end end endmodule 3.6.2.8 C php initial [begin] behavior_statements; [end] 3.6.3 3.6.3. Cu trc always 3.6.3.1 Bt u thc hin thi im 0 3.6.3.2 c thc hin lp i lp li lin tc khi c s kin xy ra trong danh sch kch hot (trigger_list, danh sch nhy - sensitive list) 3.6.3.3 V d 3.6.2: always 1 module clock_gen (output reg clock); initial clock = 1b0; // must initialize in initial block always // no trigger list for this always #10 clock = ~clock; // always will re-evaluate when // last <LHS> assignment completes endmodule 3.6.3.4 Ch m t hot ng ca mch T hp Khng dng kch hot bng sn (edge-triggered) Tt c cc "u vo" (bin v phi php gn) cn c a vo trigger-list Khng ph thuc ng h Tun t (dy)

S kin ng h v m t Flip-Flop S kin ng h

posedge

3.6.3.4..1.1.1.1 Xy ra khi tn hiu chuyn t 0 ln x,z, 1 3.6.3.4..1.1.1.2 Xy ra khi tn hiu chuyn t x, z ln 1 negedge

3.6.3.4..1.1.1.3 Xy ra khi tn hiu chuyn t 1 xung x,z, 0 3.6.3.4..1.1.1.4 Xy ra khi tn hiu chuyn t x, z xung 0

S dng s kin ng h m t Flip-Flop

always @ (posedge clk) register <= register_input;

V d 3.6.3: M t D-FF khng c tn hiu reset

reg q; always @(posedge clk) q <= d; Kt qu tng hp

3.6.3.4..1.1.1.5

Ch : Khng nn dng FF khng c reset

V d 3.6.4: M t D-FF c reset ng b

reg q; always @(posedge clk) if (!rst_n) Kt qu tng hp q <= 1b0; //synch reset else q <= d;

3.6.3.4..1.1.1.6

Tn hiu reset khng nm trong danh sch kch hot ca khi always

V d 3.6.5: M t flip-flop vi reset khng ng b

Kt qu tng hp

3.6.3.4..1.1.1.7 Th vin cc cng thng c flip-flop vi u vo reset khng ng b 3.6.3.4..1.1.1.8 Kch thc ln hn flipflop thng khng ng k 3.6.3.4..1.1.1.9

reg q; always @(posedge clk or negedge rst_n) if (!rst_n) else q <= d; Tn hiu reset nm trong trigger list ca khi always

q <= 1b0; //synch reset

V d 3.6.6: M t flip-flop vi reset ng b/khng ng b v tn hiu enable

M reset ng b

3.6.3.4..1.1.1.10 1 module always_example(); 2 reg clk,reset,enable,q_in,data; 3 4 always @ (posedge clk) 5 if (reset) begin 6 data <= 0; 7 end else if (enable) begin 8 data <= q_in; 9 end 10 11 endmodule 3.6.3.4..1.1.1.11 Kt qu tng hp 3.6.3.4..1.1.1.12

M reset khng ng b

Ch : Cn bit r cc cng c trong th vin

FF iu khin bi sn dng hay sn m? u vo reset l active low hay active high, ng b hay khng ng b? FF c h tr test? Khi vit code, vit code cho nhng cng c trong th vin

3.6.3.4..1.1.1.13 Phn mm tng hp s to ra mch kch thc nh nht (cn t cng logic nht) 3.6.3.4..1.1.1.14 Nu th vin khng c FF vi reset active high=>vit code th no?

FF.

Kch hot bng sn ca tn hiu ng h Ch ng h v reset nm trong trigger-list C th bao gm phn m t mch t hp ni vo FF. Tc l m t hm trng thi k tip ca V d 3.6.7: Kt hp logic t hp trong khi always mch dy
module counter(up,down, cnt, rst_n, clk); output [7:0] cnt; input up,down; // = 10 count up, 01 count down, otherwise stop input clk, rst_n; reg [7:0] cnt; always @ (posedge clk or negedge rst_n) if (!rst_n) cnt <= 0; else if (up) cnt <= cnt+1; else if (down) cnt <= cnt-1; else cnt <= cnt; endmodule

3.6.3.5 C php always @(trigger list) begin behavior_statements; end Trigger list (sensitive list)

always @(a, b, c) begin end C php Before Verilog 2001

always @(signal_1 or signal_2 or signal 3 or...)

Verilog 2001
always @(signal_1, signal_2, signal_3, ...) always @(*)

3.6.3.5..1.1.1.1 Dng m t mch logic t hp 3.6.3.5..1.1.1.2 Khng khuyn dng

Kch hot vic thc hin cc lnh trong khi always khi c s thay i gi tr ca cc tn hiu trong list thc Nu khng c danh sch kch hot, c thc hin lp li ngay sau khi php gn cui cng kt Ch : ch dng trong testbench v m phng

Cc tn hiu xut hin trong trigger list l u vo ca khi mch t hp c m t bng cu trc always Cc tn hiu cn xut hin trong trigger list l cc bin/tn hiu biu thc bn phi php gn trong khi always 3.6.4 3.6.4. Php gn blocking v non-blocking 3.6.4.1 Lnh gn tun t (Blocking Assignment) C php LHS = RHS LHS: cc bin kiu reg hoc biu thc ni vector ca cc bin kiu reg RHS: biu thc

Trong m phng c thc hin tun t tng php gn B1: Tnh ton RHS B2: Gn RHS vo LHS

 Trong tng hp: m t cng logic trong mch logic t hp. Th hin s kt ni tun t ca cc cng logic (u ra ti u vo) Ch : Ch khi kt qu ca php gn pha trc c s dng trong php gn pha sau V d 3.6.8: Lnh gn tun t

module addtree(output reg [9:0] out, input [7:0] in1, in2, in3, in4); reg [8:0] part1, part2; always @(in1, in2, in3, in4) begin part1 = in1 + in2; part2 = in3 + in4; out = part1 + part2; end endmodule Kt qu tng hp

3.6.4.2 Lnh gn song song (Nonblocking assignment) C php LHS <= RHS LHS: cc bin kiu reg hoc biu thc ni vector RHS: biu thc

Trong m phng c thc hin ng thi nu khng c thm gi tr tr B1: Tnh ton RHS cho tt c cc php gn B2: Gn RHS ca tng biu thc cho LHS tng ng theo th t khng xc nh

Trong tng hp: m t thanh ghi trong mch tun t (dy). Th hin cc FF c lp (gi tr hin ti ca cc FF khng ph thuc vo nhau) V d 3.6.9: Lnh gn song song

 module swap(output reg out0, out1, input rst, clk); always @(posedge clk) begin if (rst) begin out0 <= 1b0; out1 <= 1b1; end else begin out0 <= out1; out1 <= out0; end end endmodule Kt qu tng hp

3.6.4.3 So snh gn tun t v gn song song V d 3.6.10:Swap dng lnh gn tun t

module swap(output reg [15:0] out0, out1, input [15:0] in0, in1, input swap); reg [15:0] temp; always @(*) begin out0 = in0; out1 = in1; if (swap) begin temp = out0; out0 = out1; out1 = temp; end end endmodule Kt qu tng hp

V d 3.6.11: Khng dng lnh gn tun t m t mch tun t (trong always)

Ch : Vic tnh ton biu thc v phi ca cc cu lnh pha sau lnh gn tun t s b dng cho n khi vic gn kt thc Mc tiu m t mch

module pipe(input clk, d, output q1, q2, q3);

M m t dng lnh gn tun t module blocking_pipe(clk, d, q1, q2, q3); input clk,d; output q1, q2, q3; reg q1, q2, q3; always @(posedge clk) begin q1 = d; q2 = q1; q3 = q2; end endmodule Kt qu tng hp

M m t dng lnh gn song song module blocking_pipe(clk, d, q1, q2, q3); input clk,d; output q1, q2, q3; reg q1, q2, q3; always @(posedge clk) begin q1 <= d; q2 <= q1; q3 <= q2; end endmodule Kt qu tng hp

V d 3.6.12: Khng dng lnh gn song song m t mch logic t hp M 1 module nonblocking_comb(z,a,b,c,d); input a,b,c,d; output z; reg z,tmp1,tmp2; always @(a,b,c,d) begin tmp1 <= a & b; tmp2 <= c & d; z <= tmp1 | tmp2; end endmodule Testbench
module test_nonblocking_comb; reg a, b, c, d; wire z; nonblocking_comb nonblocking_comb_dut(z, a, b, c, d); initial $monitor ("%g z=%b, a=%b, b=%b, c=%b, d=%b", $time, z, a, b, c, d); initial begin #0 a = 0; #0 b = 1; #0 c = 0; #0 d = 1; #5 a = 1; #5 c = 1; #5 b = 0; #5 d = 0; end endmodule;

Kt qu m phng
# 0 z=x, a=0, b=1, c=0, d=1 # 5 z=0, a=1, b=1, c=0, d=1 (kt qu m phng sai v z c tnh bng gi tr c ca tmp1, tmp2) # 10 z=1, a=1, b=1, c=1, d=1 # 15 z=1, a=1, b=0, c=1, d=1 # 20 z=1, a=1, b=0, c=1, d=0 Timing diagram

3.6.4.3..1.1.1.1

Phn tch:
1) a, b, c, d thay i => khi always c tnh li. Tc l tnh li cc biu thc bn phi php gn vi cc gi tr mi ca a, b, c, d v gi tr c ca tmp1, tmp2

2) php gn cho tmp1, tmp2 c v php gn cho z c nh thi gian thc hin 3) Thc hin php gn cho tmp1, tmp2, z lm cc bin ny thay i gi tr 4) Kt thc thc hin khi always i s thay i itp theo ca a, b, c, d Ch : tmp1, tmp2 thay i khng lm always c thc hin

M 2 module nonblocking_comb(z,a,b,c,d); input a,b,c,d; output z; reg z,tmp1,tmp2; always @(a,b,c,d, tmp1, tmp2) begin tmp1 <= a & b; tmp2 <= c & d; z <= tmp1 | tmp2; end endmodule Kt qu m phng
run # 0 z=0, a=0, b=1, c=0, d=1 # 5 z=1, a=1, b=1, c=0, d=1 # 10 z=1, a=1, b=1, c=1, d=1 # 15 z=1, a=1, b=0, c=1, d=1 # 20 z=0, a=1, b=0, c=1, d=0

Phn tch:
1) a, b, c, d thay i => khi always c tnh li. Tc l tnh li cc biu thc bn phi php gn vi cc gi tr mi ca a, b, c, d v gi tr c ca tmp1, tmp2 2) php gn cho tmp1, tmp2 c v php gn cho z c nh thi gian thc hin 3) Thc hin php gn cho tmp1, tmp2, z lm cc bin ny thay i gi tr 4) Khi always c tnh ton ln th 2 do s thay i ca tmp1, tmp2

Kt qu tng hp

M 2 ng nhng s mt thi gian m phng hn khi dng lnh gn tun t

Bi tp: Vit li on m trn dng php gn blocking. Cc tn hiu no cn nm trong trigger_list kt qu m phng ng? Kt qu tng hp mch nh th no?

 Tham kho thm: Clifford E. Cummings, "Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!" 3.6.5 3.6.5. Cu trc if-else 3.6.5.1 C php if n if (condition) begin <statement1>; <statement2>; end if v else

if (condition) begin <statement1>; <statement2>; end else begin <statement3>; <statement4>; end nested if

if (condition) begin <statement1>; <statement2>; end else if (condition2) begin <statement3>; <statement4>; end else begin <statement5>; <statement6>; end 3.6.5.2 Tng hp Phn cng cho tt c cc nhnhthc hin qua khi if/else u c to ra Khng to ra phn cng ph thuc vo kt qu iu kin Cc nhnh c tnh ton ng thi To ra cc khi mux la chn kt qu Kt qu c la chn ph thuc iu kin 3.6.5.3 V d 3.6.13. Lnh if/else M if (func_add) alu = a + b; else if (func_and) alu = a & b; else alu = 8h00; Kt qu tng hp

ng vi mi nhnh if, mt khi tnh ton tng ng c to ra (+, &, 8'h00) B mux th nht la chn nhnh if v else di cng B mux th 2 la chn nhnh if v else pha trn 3.6.5.4 Ch phn t latches n

Khi if khng i km else tng ng V d 3.6.14. Lnh if thiu nhnh else M

module if_no_else(input [1:0] alu_func, input [4:0] src1, src2, output reg [4:0] res); parameter alu_add = 2'b00; parameter alu_and = 2'b01; always @(alu_func, src1, src2) begin // trnh latch khi khng c nhnh else, // nhng khng khuyn khch. res = 0; if (alu_func == alu_add) begin res = src1 + src2; end else if (alu_func == alu_and) begin res = src1 & src2; end end endmodule

Kt qu tng hp

L do
res l kiu reg, n s gi nguyn gi tr khi khng c gn gi tr mi (i.e. khi alu_func != alu_add, alu_and) => latch

Ch : Lun c vit if c else

3.6.5.5 Ch mc u tin khi tng hp cc nhnh if V d 3.6.15: if lng nhau M module nested_if(input clk, rst_n, up_en, down_en, output reg [3:0] counter); always @ (posedge clk or negedge rst_n) // If reset is asserted if (!rst_n) begin counter <= 4'b0000; // If counter is enable and up count is asserted end else if (up_en) begin counter <= counter + 1'b1; // If counter is enable and down count is asserted end else if (down_en) begin counter <= counter - 1'b1; // If counting is disabled end else begin counter <= counter; // Redundant code end endmodule Kt qu tng hp

Khi cc nhnh if c lng vi nhau, nhnh if u tin s c mc u tin cao nht

Khi iu kin ca cc nhnh if lng nhau khng loi tr nhau (overlapped conditions - c th cng ng) th kt qu mch c th khc vi specification V d Mch m tng/gim c u vo: up,down = 10 => m tng up,down = 01 => m gim others => dng Cn vit cc iu kin ca nhnh if loi tr nhau Nu iu kin cc nhnh if khng loi tr
M

3.6.5.5..1.1.1.1 module counter(input clk, input rst_n, input up, down, output reg [7:0] cnt); always @(posedge clk or negedge rst_n) begin if (!rst_n) cnt <= 0; else if (up) cnt <= cnt+1; else if (down) cnt <= cnt-1; else cnt <= cnt; end endmodule Hot ng

3.6.5.5..1.1.1.2 updown=11 vn m tng

3.6.6 3.6.6. Cu trc case 3.6.6.1 C php case (expression) alternative1 : statement1; // any of these statements could alternative2 : statement2; // be a compound statement using alternative3 : statement3; // begin/end default : statement4 // always use default for synth stuff endcase so snh tng bit ca expression vi case item (alternative1, 2, 3, ...) Nu expression bng nhnh case no, th s thc hin cu lnh trong nhnh case tng ng 3.6.6.2 Cc loi case case Phn bit cc gi tr x, z, 0, 1 Cc chui bt 01, 0x, z1 l khc nhau

V d 3.6.16: Normal case M

module alu(input [1:0] alu_op, input [31:0] src1, src2, output reg [31:0] res); parameter AND = 2'b00; parameter OR = 2'b01; parameter XOR = 2'b10; parameter ADD = 2'b11; always @(alu_op, src1, src2) begin case (alu_op) AND : res = src1 & src2; OR : res = src1 | src2; XOR : res = src1 ^ src2; default : res = src1 + src2; endcase end endmodule

casez

Kt qu tng hp

Cc bit c gi tr z, ? c coi nh nhau l don't care: c th match vi 0/1 Cc chui 01, 00, 0z, 0? c coi l ging nhau

V d 3.6.18: casez casex Cc bit c gi tr x, z, ? c coi nh nhau l don't care c th match 0/1

 Khi c nhiu la chn case (alternative) cng ph hp vi expression th s dng la chn u tin => alternative pha trn c mc u tin cao hn V d 3.6.17: casex M
module test_casex(); reg [1:0] code; reg [7:0] control; always @ (code) begin casex (code) // case expression 2'b0?: control = 1; // case item1 2'b10: control = 2; // case item 2 2'b11: control = 3; // case item 3 endcase end initial $monitor("%t: code = %b, control = %d", $time, code, control); initial begin #0 code = 2'b00; #5 code = 2'b01; #5 code = 2'b10; #5 code = 2'b11; #5 code = 2'b1x; #5 code = 2'b0x; end endmodule

Kt qu m phng

3.6.6.3 Ch : trnh latch th lun phi c nhanh default

Lun vit case cho trng hp cc iu kin alternative l loi tr nhau v c mc u tin nh nhau Nu mun vit iu kin c u tin v khng loi tr th nn dng if lng Hn ch dng casez v casex Tham kho:Clifford Cummings: "full_case parallel_case, the Evil Twins of Verilog Synthesis"

3.7 3.7 Thc hnh

3.7.1 Lm quen vi phn mm Altera Quartus 3.7.1.1 M phng mch s ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Verilog/Quartus_II_Simulatio n.pdf See document(s): Quartus_II_Simulation.pdf

3.7.1.2 Gii thiu Quartus ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Verilog/Quartus_II_Introducti on.pdf 3.7.2 Lm quen vi kit DE1 3.7.2.1 ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Getting_Started_with_ DE-series_boards.pdf 3.7.3 Bi Lab 1 3.7.3.1 ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Lo gic/DE2/verilog/lab1_Verilog.pdf 3.7.3.2 Ch trong bi lab ny ta cn lm cc bc B1. Xc nh bng s tht cho cc u ra B2. Ti gin cc hm Bool cho u ra

B3. Trin khai m ta cc hm Bool u ra bng cu lnh gn assign trong Verilog. Hoc m t mch bng Verilog 3.7.4 Bi Lab 2 3.7.4.1 ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Laboratory_Exercises/Digital_Lo gic/DE2/verilog/lab2_Verilog.pdf 3.7.4.2 Lm ht phn 2 3.7.5 tr 3.7.5.1 Cch m t tr 1 cng trong Verilog 3.7.5.2 M phng tr ca mch trong lab1 v lab2 3.7.6 Tham kho 3.7.6.1 altera.com, university program

3.8 Bi tp chng:
3.8.1 Thit k b m m gray 4 bit, b dch logic tri phi 1 bit, b quay tri phi 1 bit gm n bit

4 Chng 4. M phng v testbench

4.1 4.1. Nguyn tc hot ng ca chng trnh m phng

4.1.1 4.1.1. nh ngha: L qu trnh phn tch m hnh m t mch tnh ton gi tr u ra t u vo 4.1.1.1 L mt qu trnh thc hin tru tng bng b no con ngi hoc my tnh 4.1.2 4.1.2. Nguyn tc m phng mch s 4.1.2.1 Khi u vo thay i tnh ton li ton b cc tn hiu trong mch Hnh v

4.1.2.2 Khi du vo thay i tnh li cc ng t u vo Hnh v

4.1.3 4.1.3. M phng da trn s kin 4.1.3.1 B1: a cc tn hiu u vo thay i vo hng i s kin ti thi gian m phng 0 4.1.3.2 B2: Lp li n khi no hng i rng hiu Ly mt tn hiu ra khi hng i Vi mi phn t (cng logic, cu lnh Verilog, module, lnh gn...) l fanout(sink) ca tn Tnh li gi tr u ra tng ng ca phn t

Nu u ra thay i gi tr, a tn hiu u ra vo hng i ti thi im m phng = thi im hin ti + tr ca phn t 4.1.3.3 B3: Khi hng i rng, gi nguyn kt qu m phng hoc i n thi gian m phng tip theo 4.1.3.4 Hnh v

4.1.3.5 V d m phng mch s

4.1.3.6 u im ca m phng s kin Tc nhanh M phng c thi gian M phng c mch m t bng cc m hnh cu trc/RTL/hot ng 4.1.4 4.1.4. Thi gian trong m phng 4.1.4.1 c dng m hnh ha thi gian hot ng ca mch ( tr tnh ton) Khng tr (zero-delay)

C php and A0(OUT, A, B); assign OUT = A&B; always @(A, B) OUT = A&B;

u ra c thay i cng vi u vo S kin ti OUT c a vo hng i ti thi im m phng hin tai

Khng thc t C th chp nhn kt qu m phng khi xt mch hot ng ng b

Tr n v (unit-delay) Cc phn t trong mch c gn mt thi gian tr tnh theo n v tr tng tng Khng chnh xc, nhng l xp x gn ng thc t Th hin c thc t l s mc logic nh hng ti tc ca mch D dng quan st s thay i ca tn hiu lan truyn trong mch C php and #1 A0(OUT, A, B); assign OUT = #1 A & B; assign #1 OUT = A & B; OUT c thay i 1 n v m phng sau khi A hoc/v B thay i

Quy nh n v thi gian trong Verilog `timescale 1ns /100 fs // time_unit/time_precision ' `

Tuy nhin: Khng nn vit tr ca cng logic trong phn m t mch Vn khng chnh xc Khng c kt qu tng hp tng ng Chm tc m phng C th m phng thi gian ngay sau khi tng hp Ch nn dng tr trong testbench

4.1.4.2 V d v m t tr trong Verilog

wire #5 net_1; // 5 unit tr dy dn and #4 (z_out, x_in, y_in); // 4 unit tr cng wire #2 z_out; // 2 unit tr dy dn and #3 (z_out, x_in, y_in); // 3 for gate, 2 for wire wire #3 c; // 3 unit transport delay assign #5 c = a & b; // 5 for assign, 3 for wire assign z_out = #3 a & b; // 3 unit tr cng Thc hin tnh ton, ch 3 n v tr v gn z_out = a & b assign #3 z_out = a & b; // 3 unit tr cng Thc hin tnh ton v gn z_out = a & b sau ch 3 n v tr Ch nn dng kiu tr ny 4.1.4.3 Tr trong cu lnh gn Verilog

Inter-Statement Delay Tr c vic tnh RHS v gn #4 c = d; #8 e = f; Intra-Statement Delay Tr vic gn nhng khng tr vic tnh RHS c = #4 d; e = #8 f; V d so snh

1, b=

# 2#

0: a= 3, b= x# 8: a= 1, b= 3#

3: a= 1, b= x# 10: a= 4, b= 3

6: a=

1, b=

# 6#

0: a= 3, b= x# 8: a= 1, b= 3#

3: a= 1, b= x# 10: a= 7, b= 3

6: a=

Ch : Khng gn gi tr cho mt bin trong nhiu khi lnh

4.2 4.2. Testbench

4.2.1 4.2.1. nh ngha 4.2.1.1 M hnh ha mi trng hot ng ca mch cn c kim tra (DUT, DUV) 4.2.1.2 L mt module Verilog khng c u vo v u ra

4.2.1.3 Hnh v

4.2.2 4.2.2. Chc nng 4.2.2.1 To ra tn hiu u vo (input vectors, input patterns, input stimuti) a ti mch cn kim tra 4.2.2.2 Theo di tn hiu u ra (v) so snh, kim tra vi tn hiu u ra chun (ng) 4.2.2.3 V d 4.2.1 Mch cng 4 bit

Testbench

`timescale 1ns /100 fs // time_unit/time_precision-nh ngha n v thi gian m phng module adder4bit_tb; // Khai bo cc tn hiu ni vo DUT reg[8:0] stim; // inputs to DUT are regs wire[3:0] S; // outputs of DUT are wires wire C4; // instantiate DUT adder4bit adder4bit_DUT (.sum(S), .c_out(C4), .a(stim[8:5]), .b(stim[4:1]), .c(stim[0])); // stimulus generation -- to tn hiu u vo initial begin stim = 9'b0000_0000_0; // at 0 ns #10 stim = 9'b1111_0000_1; // at 10 ns #10 stim = 9'b0000_1111_1; // at 20 ns #10 stim = 9'b1111_0001_0; // at 30 ns #10 stim = 9'b0001_1111_0; // at 40 ns #10 $stop; // at 50 ns stops simulation end // outputs observation initial $monitor("%t, a = %d, b=%d, ci=%b, s = %d, co=%b", $time, stim[8:5], stim[4:1],stim[0],s, c4) endmodule 4.2.2.4 Bi tp: Vit testbench cho b cng 16 bit, CLA v CRA 4.2.3 4.2.3. Thnh phn 4.2.3.1 1. To module con l DUT v kt ni u vo ca DUT vi tn hiu cha input patterns (mu u vo), kt ni u ra vi tn hiu c quan st v kim tra 4.2.3.2 2. To mu tn hiu u vo cho DUT Phng php 1: To tt c cc t hp tn hiu u vo S dng vng lp for (x = 0; x < 16; x = x + 1) #5;

V d 4.2.2 `timescale 1ns /100 fs // time_unit/time_precision module adder4bit_tb; reg [9:0] stim; // inputs to DUT are regs - ch vng lp for di kt thc, stim c nhiu hn 1 bit so vi s bit u vo wire[3:0] S; // outputs of DUT are wires wire C4; // instantiate DUT adder4bit(.sum(S), .c_out(C4), .a(stim[8:5]), .b(stim[4:1]), .c(stim[0])); // stimulus generation initial begin for (stim = 0;stim <512; stim = stim+1) #10; #10 $stop; end endmodule

exhaustive/complete simulation

Chm Khng kh thi S dng cho cc mch nh m bo chc chn pht hin c cc li ca mch

Phng php 2: To t hp tn hiu u vo ngu nhin S dng hm random Khng pht hin c tt c cc li C th b st cc li cc trng hp ti hn/trng hp gc (critical corner cases) Bi tp: xy dng li testbench v d trn dng hm random Phng php 3: To u vo t cc kch bn hot ng ca mch Xem xt cc trng hp hot ng ti hn ca mch u vo v u ra tng ng c th c c ra t file Vi mi mch khc nhau s cn lit k ra trng hp ti hn khc nhau c xc nh trong bc ln k hoch kim tra (Verification Plan) c tin hnh ng thi vi bc Architecture Design

Phn tch cc kch bn hot ng ca mch chnh l tng ng vi phn tch/phn r chc nng ca mch Tham s nh gi cht lng t hp u vo Coverage Metrics Bao ph m Bao ph cu lnh Bao ph iu kin Bao ph nhnh lnh

Bao ph chc nng Bao ph FSM Bao ph trng thi

Bao ph chuyn trng thi

4.2.3.3 3. Quan st v kim tra tn hiu u ra Phng php 1: Quan st v so snh th cng Tn hiu u vo/ u ra c hin th di dng biu thi gian In ra tn hiu u ra di dng text $display, $strobe $monitor

D c sai st do ngi thc hin Khng t ng ha c Thng c thay th bng testbench t kim tra (self-test) Phng php 2: Quan st v kim tra kt qu u ra t ng Cn c khi tnh ton kt qu u ra Cch 1: Tnh ton u ra "ng" bng m Verilog trong testbench
V d:

4.2.3.3..1.1.1.1 `timescale 1ns /100 fs // time_unit/time_precision-nh ngha n v thi gian m phng module adder4bit_tb; // Khai bo cc tn hiu ni vo DUT reg[8:0] stim; // inputs to DUT are regs wire[3:0] S; // outputs of DUT are wires wire C4; // instantiate DUT adder4bit adder4bit_DUT (.sum(S), .c_out(C4), .a(stim[8:5]), .b(stim[4:1]), .c(stim[0])); // stimulus generation -- to tn hiu u vo initial begin stim = 9'b0000_0000_0; // at 0 ns #10 stim = 9'b1111_0000_1; // at 10 ns #10 stim = 9'b0000_1111_1; // at 20 ns #10 stim = 9'b1111_0001_0; // at 30 ns #10 stim = 9'b0001_1111_0; // at 40 ns #10 $stop; // at 50 ns - stops simulation end // outputs observation initial $monitor("%t, a = %d, b=%d, ci=%b, s = %d, co=%b", $time, stim[8:5], stim[4:1],stim[0],s, c4) // outputs self-test always @(stim, s, c4) begin if ({c4, s} != stim[8:5]+stim[4:1]+stim[0]) $display ("FAIL: %t, a = %d, b=%d, ci=%b, s = %d, co=%b", $time, stim[8:5], stim[4:1],stim[0],s, c4); end endmodule Testbench thc hin vic m t chc nng mch mt ln na (nguyn l duplicate trong kim tra) 4.2.3.3..1.1.1.2 Ch : mch c m t trong testbench khng cn phi tng hp => c th m t bng cc cu trc ngn ng bc cao (tru tng hn) => n gin hn mch DUT

Cch 2: Tnh ton u ra "ng" bng chng trnh phn mm (C/C++, Matlab/Simulink)
Giao tip thng qua tp tin

4.2.3.3..1.1.1.3 Phn mm s ghi mu u vo v u ra "ng" tng ng vo file

4.2.3.3..1.1.1.4 Testbench s c file ly u vo v u ra "ng" Giao tip thng qua giao din PLI, giao din HIL,...

4.2.3.4 4. To tn hiu clk Dng always initial clk = 0; always @(clk) clk = #5 ~clk; Dng forever initial begin clk = 0; forever #5 clk = ~clk; end

4.3 4.3. Mt s cu lnh c th dng trong testbench

4.3.1 4.3.1. Cc lnh lp 4.3.1.1 for C php for (starting_statement; condition_expression; ending_statement) V d 4.3.1: for

reg [15:0] rf[0:15]; // memory structure for modeling register file reg [5:0] w_addr; // address to write to for (w_addr=0; w_addr<16; w_addr=w_addr+1) rf[w_addr[3:0]] = 16h0000; // initialize register file memory 4.3.1.2 while C php while (condition_expression) V d 4.3.2: while

reg [15:0] flag; reg [4:0] index; initial begin index=0; found=1b0; while ((index<16) && (!found)) begin if (flag[index]) found = 1b1; else index = index + 1; end if (!found) $display(non-zero flag bit not found!); else $display(non-zero flag bit found in position %d,index); end 4.3.1.3 repeat C php repeat (number_of_iteration) Trong : number_of_iteration l 1 hng s nguyn hoc 1 bin

Lp s ln c nh S ln lp c th l mt bin, nhng ch c tnh mt ln khi bt u vng lp Dng khi mun i mt s xc nh chu k ng h V d 4.3.3: repeat

initial begin inc_DAC = 1b1; repeat(4095) @(posedge clk); // bring DAC right up to point of rollover inc_DAC = 1b0; inc_smpl = 1b1; repeat(7)@(posedge clk); // bring sample count up to 7 inc_smpl = 1b0; end 4.3.1.4 forever C php forever statements; V d 4.3.4: forever initial begin clk = 0; forever #10 clk = ~ clk; end 4.3.2 4.3.2. Khi lnh v iu khin khi lnh 4.3.2.1 Khi lnh tun t - begin/end bao khi lnh thc hin tun t 4.3.2.2 Khi lnh song song - fork/join bao khi lnh thc hin song song cc cu lnh trong khi c thc hin ng thi

Thi gian tr trong cc cu lnh nm gia fork/join c tnh tng i k t khi khi lnh c bt u thc hin Thch hp ch 2 s kin xut hin nhng khng bit s kin no xut hin trc begin fork @Aevent @Bevent join areg = breg; end

Ch : fork/join c th gy ra ua tn hiu (hazard) Khi nhiu khi fork/join cng gn gi tr cho mt bin 4.3.2.3 t tn khi lnh

C th nh ngha bin a phng bn trong khi lnh c t tn Cc bin a phng c th c truy cp bng cch truy cp phn cp

C th dng (disable) mt khi lnh c tn Hnh v

4.3.2.4 Tm dng thc hin mt khi lnh C php: disable block_name; Tm dng thc hin mt khi lnh V d 4.3.5: disable M `timescale 1ns/1ns module test_diable(); integer a, b; integer i; reg clk; initial begin : break for (i = 0; i < 20; i = i+1) begin : continue @(posedge clk) if (a == 0) // "continue" loop disable continue; // Dng khng thc hin lnh bn trong khi continue if (a == b) // "break" from loop disable break; // Dng khng thc hin lnh bn trong khi break $display("%t:Inside continue block a=%d,b=%d,i=%d",$time,a,b,i); end $display("%t:Inside break block a=%d,b=%d,i=%d",$time,a,b,i); end initial begin a = 2; b = 1; #20 a = 0; #20 a = 3; #20 a = 1; end initial begin clk = 0; forever #5 clk = ~clk; end // initial $monitor ("%t:a=%d,b=%d,i=%d",$time,a,b,i); endmodule; Kt qu m phng run 100ns # 15:Inside continue block a= 3,b= 1,i= 4# 5:Inside continue block a= 2,b= 1,i= 1# 55:Inside continue block a= 2,b= 1,i= 0# 45:Inside continue block a= 3,b= 1,i= 5

4.3.3 4.3.3 Vo ra file 4.3.3.1 Thc hin kim chng t ng 4.3.3.2 u vo, u ra c a vo file v c lp vi testbench u vo v u ra chun c th c to ra bi phn mm ngn ng bc cao nh C/C++, Matlab/Simulink Dng file kt ni 2 mc m t h thng Mc phn mm: m t thut ton Mc phn cng (DUT): m t trin khai RTL/behavior 4.3.3.3 Cc hm thao tc trn file ng m $fopen m file, tr v 1 handle s dng trong cc lnh khc integer fd = $fopen(filename); integer fd = $fopen(filename, r); Nu khng m c file tr v 0

$fclose ng file

 Ghi

$fclose(fd)

$fdisplay, $fwrite ghi d liu vo file khi c gi. $fdisplay thm 1 k t bt u dng mi vo d liu. $write khng thm. $fstrobe ghi vo file, nhng i n khi tt c cc lnh khc trong cng thi gian m phng kt thc trc khi ghi. initial #1 a=1; b=0; $fstrobe(hand1, a,b); b=1;
on m trn s ghi gi tr 1 1 vo file cho a v b

$fmonitor ghi vo file bt c khi no cc tham s truyn cho n thay i $fdisplay(fd, out=%b in=%b, out, in); c c mt k t $fgetc
V d 3.3.6: fgetc

4.3.3.3..1.1.1.1 module file_read() parameter EOF = -1; integer file_handle,error,indx; reg signed [15:0] wide_char; reg [7:0] mem[0:255]; reg [639:0] err_str; initial begin indx=0; file_handle = $fopen(text.txt,r); error = $ferror(file_handle,err_str); if (error==0) begin wide_char = 16h0000; while (wide_char!=EOF) begin wide_char = $fgetc(file_handle); mem[indx] = wide_char[7:0]; $write(%c,mem[indx]); indx = indx + 1; end end else $display(Cant open file); $fclose(file_handle); end endmodule

c mt dng $fgets
V d 3.3.7: fgets

4.3.3.3..1.1.1.2 module file_read2() integer file_handle,error,indx,num_bytes_in_line; reg [256*8:1] mem[0:255],line_buffer; reg [639:0] err_str; initial begin indx=0; file_handle = $fopen(text2.txt,r); error = $ferror(file_handle,err_str); if (error==0) begin num_bytes_in_line = $fgets(line_buffer,file_handle); while (num_bytes_in_line>0) begin mem[indx] = line_buffer; $write(%s,mem[indx]); indx = indx + 1; num_bytes_in_line = $fgets(line_buffer,file_handle); end end else $display(Could not open file text2.txt);

c theo bin $fscanf

V d 3.3.8: fscanf

4.3.3.3..1.1.1.3 module file_read3() integer file_handle,error,indx,num_matches; reg [15:0] mem[0:255][1:0]; reg [639:0] err_str; initial begin indx=0; file_handle = $fopen(text3.txt,r); error = $ferror(file_handle,err_str); if (error==0) begin num_matches = $fscanf(file_handle,%h %h,mem[indx][0],mem[indx][1]); while (num_matches>0) begin $display(data is: %h %h,mem[indx][0],mem[indx[1]); indx = indx + 1; num_matches = $fscanf(file_handle,%h %h,mem[indx][0],mem[indx][1]); end end else $display(Could not open file text3.txt);

c file theo khi b nh $readmemb(<file_name>,<memory>); $readmemb(<file_name>,<memory>,<start_addr>,<finish_addr>); $readmemh(<file_name>,<memory>); $readmemh(<file_name>,<memory>,<start_addr>,<finish_addr>); V d cu trc file

V d 3.3.9: c b nh
module rom(input clk; input [7:0] addr; output [15:0] dout); reg [15:0] mem[0:255]; // 16-bit wide 256 entry ROM reg [15:0] dout; initial $readmemh(constants,mem); always @(negedge clk) begin /////////////////////////////////////////////////////////// // ROM presents data on clock low // ///////////////////////////////////////////////////////// dout <= mem[addr]; end endmodule

V d 3.3.10: Testbench s dng file

module CLA16_selft_tb(); reg [32:0] stim; reg [55:0] inout_patterns [0:10]; wire [15:0] s; wire co; reg [4:0] addr; CLA16 cla16_dut(.a(stim[15:0]), .b(stim[31:16]), .ci(stim[32]), .s(s), .co(co)); initial $monitor("%t: a=%h, b=%h, ci=%b, s=%h, co=%b, correct_s=%h, correct_co=%b", $time, stim[15:0], stim[31:16], stim[32], s, co, inout_patterns[addr][51:36],inout_patterns[addr][52]); // read input-output patterns from file and // drive to input // in file correct-outputs.txt the data is arranged as follow: // each input patterns and corresponding correct output values are given as a hexa number where // first four digits is a value [15:0] // next four is b value [31:16] // next one digit is ci value [35:32] // next four digits is s value [51:36] // next one digit is co value [55:52] // total are 14 digits initial begin: input_gen $readmemh("correct-outputs.txt", inout_patterns); stim = 32'h0; for (addr = 0;addr < 11; addr=addr+1) begin stim = inout_patterns[addr][32:0]; #5; end end // output self-test always @(stim) begin: output_selftest if ((co!==inout_patterns[addr][52])|(s!==inout_patterns[addr][51:36])) $display ("WRONG!!!-%t: a=%h, b=%h, ci=%b, s=%h, co=%b, correct_s=%h, correct_co=%b", $time, stim[15:0], stim[31:16], stim[32], s, co,inout_patterns[addr][51:36],inout_patterns[addr][52]); end endmodule 4.3.4 4.3.4 t gi tr tn hiu trong mch 4.3.4.1 a mch n mt trng thi xc nh v bt u m phng t 4.3.4.2 Ch s dng trong testbench, khng c trong thc t 4.3.4.3 Gip i n gn trng thi c th xy ra li ca mch 4.3.4.4 Dng kim tra mch dy "su" (cn nhiu chu k n c mt trng thi bt k ca mch)

a mch n mt trng thi Kim tra cc bc chuyn trng thi t trng thi Kim tra u ra tng ng 4.3.4.5 force signal_name = value; release signal_name = value;

Ch : c th dng cch truy cp phn cp (du chm) ch ti tn hiu su bn trong cc module con 4.3.4.6 V d 4.3.6: force/release Testbench

module gray_counter_tsb(); reg clk, rst_n; wire [3:0] out; gray_counter GC(.cnt(out), .clk(clk), .rst_n(rst_n)); // DUT initial $monitor("%t out: %b rst_n: %b state: %b", $time, out, rst_n, GC.state); // no clock initial begin clk = 0; forever #5 clk = ~clk; // What is the clock period? end initial begin rst_n = 1; #10 rst_n = 0; #90 rst_n = 1; force GC.state = 4'b0001; #10 release GC.state; #10 force GC.state = 4'b0010; #10 release GC.state; #10 force GC.state = 4'b0011; #10 release GC.state; #10 force GC.state = 4'b0100; #10 release GC.state; #10 force GC.state = 4'b0101; #10 release GC.state; #10 force GC.state = 4'b0110; #10 release GC.state; #10 force GC.state = 4'b0111; #10 release GC.state; #10 force GC.state = 4'b1000; #10 release GC.state; #10 force GC.state = 4'b1001; #10 release GC.state; #10 force GC.state = 4'b1010; #10 release GC.state; #10 force GC.state = 4'b1011; #10 release GC.state; #10 force GC.state = 4'b1100; #10 release GC.state; #10 force GC.state = 4'b1101; #10 release GC.state; #10 force GC.state = 4'b1110; #10 release GC.state; #10 force GC.state = 4'b1111; #10 release GC.state; end // initial endmodule gray_counter

module gray_counter (input clk, rst_n, output [3:0] cnt); reg [3:0] state; always @(posedge clk) begin if (~rst_n) state <= 4'b0000; else state <= state+1; end assign cnt = state ^ {1'b0,state[3:1]}; endmodule

4.4 4.4. Mt s hm h thng trong Verilog

4.4.1 $stop 4.4.1.1 Dng m phng vo ch giao tip lnh vi ngi dng, cho php theo di cc tn hiu v g li 4.4.2 $finish 4.4.2.1 Kt thc chng trnh m phng quay v h iu hnh 4.4.3 $reset 4.4.3.1 t li thi gian m phng v 0

4.4.4 $time, $stime, $realtime 4.4.4.1 Tr v thi gian m phng hin ti dng 64 bit nguyn, 32 bit nguyn, s thc 4.4.5 $display, $strobe, $monitor 4.4.5.1 C php $display ("format_string", par_1, par_2, ... ); $strobe ("format_string", par_1, par_2, ... ); $monitor ("format_string", par_1, par_2, ... ); $displayb (as above but defaults to binary..); $strobeh (as above but defaults to hex..); $monitoro (as above but defaults to octal..); format string tng t printf ca C 4.4.5.2 $display v $strobe c thc hin 1 ln khi c gi 4.4.5.3 $monitor c thc hin bt c khi no cc tham s truyn vo thay i 4.4.5.4 c s dng trong testbench khi m phng mch 4.4.5.5 $display(At time %t count = %h,$time,cnt); 4.4.6 $random 4.4.6.1 To mt s nguyn ngu nhin khi c gi 4.4.6.2 ln gi u tin c th truyn cho hm mt s seed (cc ln gi vi cng mt s seed s to ra cng mt chui ngu nhin 4.4.6.3 Nu khng truyn s seed, s seed s c ly t ng h h thng 4.4.7 $dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall 4.4.7.1 $dumpfile("filename.vcd") t file cha cc gi tr bin c in ra 4.4.7.2 $dumpvar In ra gi tr tt c cc bin trong thit k 4.4.7.3 $dumpvar(n, top) In ra gi tr cc bin trong module top v n-1 module con pha di 4.4.7.4 Subtopic 4.4.7.5 $dumpon Bt u thc hin in

4.4.7.6 $dumpoff Kt thc vic in ra cc bin 4.4.8 Ch : Cc hm ny khng dng m t mch m ch yu dng g li mch khi m phng, trong testbench

5 Chng 5. Tng hp. Tham kho: http://asic-soc.blogspot.de

5.1 5.1. Gii thiu chung
5.1.1 Quy trnh thit k vi mch 5.1.1.1

5.1.1.2 Thit k vt l l qu trnh t cc layout cc cng ln phin (Place) v kt ni cc cng bng cc ng dy kim loi (Route) 5.1.2 nh ngha 5.1.2.1 Tng hp l qu trnh chuyn t m t RTL/behavior thnh mch lp cng RTL/Behavior ngn ng HDL (Verilog/VHDL) m t hot ng ca mch bng RTL: m t qu trnh x l d liu ca mch (Dataflow) Behavior: M t cc bc hot ng ca mch-FSMD Mch lp cng: Cc cng logic kt ni vi nhau

Mch lp cng generic khng ph thuc cng ngh ch to khi cc cng khng i km thng tin v layout, kch thc transitor, b tr transitor, im kt ni

Khng dng c ch to vi mch

Mch lp cng ph thuc cng ngh ch to, nu cc cng c thng tin v layout, kch thc transitor, im kt ni Cho php xc nh chnh xc thi gian hot ng/ tr/tc ca mch

5.1.2.2 Hai bc tng hp Dch Chuyn i m t Verilog thnh m t lp cng generic Ti u v nh x cng nh x cc cng generic thnh cc cng trong th vin cell chun ph thuc cng ngh. Ti u mch t c cc iu kin k thut t ra Hnh v

5.1.3 Nhim v ca tng hp 5.1.3.1 Mc u tin cao nht: m bo chc nng ca mch Mch netlist tng hp c tng ng mch m t Verilog Tng ng v hm logic Bool

Tng ng v s th t tun t trong mch dy Khng to ra cc latch khng mong mun 5.1.3.2 Mc u tiu 2: Tha mn cc gii hn v lut thit k

hn

c cho trong th vin cng ngh bi cc nh sn xut ASIC Ngi thit k khng th thay i cc gii hn lut thit k Ngi thit k c th p t gii hn kht khe hn, nhng khng th p t gii hn nh V d: Gii hn v tc chuyn gi tr tn hiu, s fanout ti a,... 5.1.3.3 Mc u tin 3: Tha mn cc gii hn ti u

c t ra bi ngi thit k, theo th t u tin nh sau 1. Thi gian (Speed/Timing) 2. Kch thc (Area) 3. Nng lng (Power) Gii hn ny phi thc t, nhng khng c qu nh Nu khng s c thit k ti 5.1.4 u vo/ra ca tng hp 5.1.4.1 u vo

M HDL (.v, vhd) Gii hn v lut thit k Gii hn ti u Tc Kch thc Nng lng 5.1.4.2 u ra

M t mch mc cng ph thuc cng ngh

5.2 5.2. Chun b tng hp

5.2.1 5.2.1 Th vin ch 5.2.1.1 Cho bit cng ngh c s dng sn xut mch Cn th vin cc cng logic ph thuc cng ngh Th vin target c dng to ra mch cng ph thuc cng ngh Th vin target c cung cp bi nh sn xut IC hoc nhm thit k standard cell .lib Cc th vin standard cell l c lu trong file .db trong cc th mc libs../../LM 5.2.1.2 Th vin standard cells mc logic. Cha cc thng tin v cc cng logic c bn

Tn cell Kch thc cell u vo/ra Hm logic Tham s thi gian

5.2.1.3 Lnh DC: set_app_var target_library dc_shell-topo> set_app_var target_library libs/mw_lib/sc/LM/sc_max.db libs/mw_lib/sc/LM/sc_max.db 5.2.1.4 Bt buc phi t target_library 5.2.2 5.2.2 Th vin lin kt 5.2.2.1 Khi tng hp cn bit m t cu trc tt c cc module s dng trong mch c cha trong th vin link V d: Module DDR-RAM, module CPU c mua ca hng th 3 5.2.2.2 Nu khng c s bo li Unable to resolve reference "..." 5.2.2.3 Lnh DC set_app_var link_library dc_shell-topo> set_app_var link_library * libs/mw_lib/sc/LM/sc_max.db 5.2.2.4 Thng link_library s gm * v target_library * ch n b nh, l phn dc lu tr tm thi cc th vin n tng hp hoc np V d: mt file .v cha module con Cc file ddc cha module con c tng hp

C th dng target_library lm th vin link nu file .v bn u l RTL/behavior khng ph thuc cng ngh Nu file .v ban u l file tng hp ph thuc cng ngh th link library phi l library cng ngh c

5.2.3 5.2.3 Th vin vt l 5.2.3.1 Th vin vt l cha cc thng s gip dc tnh ton chnh xc thi gian tr ca mch hn trong ch hot ng topological (ty chn -topo khi chy dc_shell) 5.2.3.2 Gm

Reference library Standard Cells Cc cng logic cn bn lp transistor/layout

IP hoc Macro cells V d: RAM module, Multiplier IP

I/O Pad cells Cha thng tin cc lp/mc khc nhau CEL
Thng tin y v layout cell - ch to

FRAM
Thng tin v kch thc cell v v tr cc chn trong cell DC cn dng

LM
Thng tin v hm logic v timing ca cell DC cn dng Chnh l th vin target

DC dng nh dng Milkyway cho reference library c cung cp bi nh ch to IC C th c to ra t file LEF, GDS bng cch dng tool Synopsys Milkyway Tham kho
Data preparation user guide

D liu cng ngh Technology File nh ngha v cc lp i dy, cc l ni gia cc lp, lut DRC

TLUPLUS file Cha cc tham s v t in v in tr k sinh

Layer Mapping file Cha cc tn khc nhau cho cng mt lp

5.2.3.3 to cn Tr ti reference library Np file technology Np file tluplus

5.2.3.4 Lnh set_app_var mw_referecen_library set_app_var mw_design_library create_mw_lib Ch cn to mt ln

open_mw_lib Sau ch cn m check_library set_tluplus_files check_tluplus_files

dc_shell-topo> set_app_var mw_reference_library libs/mw_lib/sc libs/mw_lib/sc dc_shelltopo> set_app_var mw_design_library mylib mylib dc_shell-topo> create_mw_lib -technology libs/tech/cb13_6m.tf -mw_reference_library $mw_reference_library $mw_design_library Start to load technology file libs/tech/cb13_6m.tf. Technology file libs/tech/cb13_6m.tf has been loaded successfully. 5.2.4 5.2.4 Qun l cc tp 5.2.4.1 To cu trc th mc

Th mc chnh cha ton b d liu v thit k: risc_design. L th mc m ti ta gi dc_shell -topo Th mc con v files mapped Cha cc file .ddc m t mch gm cc cng ph thuc cng ngh (sau khi nh x t cng khng ph thuc cng ngh) vo th vin cng theo cng ngh

libs Cha cc file .db cc th vin khi, IPs c s dng trong thit k

cons Cha cc file .cons l cc cu lnh tcl ca dc_shell thit lp gii hn thi gian, din tch nng lng ca mch

rtl Cha cc file thit k ngn ng HDL

unmapped Cha cc file .ddc m t mch cng khng ph thuc cng ngh

.synopsys_dc.setup File gm cc lnh tcl s c thc thi khi gi dc_shell

Lnh s dng: mkdir

minh@dolcetto-suse:/home/projects> mkdir dc-ex minh@dolcetto-suse:/home/projects> mkdir dc-ex/rtl minh@dolcetto-suse:/home/projects> mkdir dc-ex/work minh@dolcettosuse:/home/projects> mkdir dc-ex/libs minh@dolcetto-suse:/home/projects> mkdir dc-ex/cons minh@dolcetto-suse:/home/projects> mkdir dc-ex/mapped minh@dolcetto-suse:/home/projects> mkdir dc-ex/unmapped minh@dolcetto-suse:/home/projects> ll dc-ex total 24 drwx--x--x 2 minh users 4096 2012-04-18 08:20 cons drwx--x--x 2 minh users 4096 2012-04-18 08:20 libs drwx--x--x 2 minh users 4096 2012-04-18 08:20 mapped drwx--x--x 2 minh users 4096 2012-04-18 08:20 rtl drwx--x--x 2 minh users 4096 2012-04-18 08:20 unmapped drwx--x--x 2 minh users 4096 2012-04-18 08:20 work Chy dc_shell vi option -topo Ch : vo th mc lm vic dc-ex

minh@dolcetto-suse:/home/projects> cd dc-ex minh@dolcetto-suse:/home/projects/dc-ex> dc_shell -topo DC Professional (TM) DC Expert (TM) DC Ultra (TM) FloorPlan Manager (TM) HDL Compiler (TM) VHDL Compiler (TM) Library Compiler (TM) DesignWare Developer (TM) DFT Compiler (TM) BSD Compiler Power Compiler (TM) Version D2010.03-SP5-2 for linux -- Jan 21, 2011 Copyright (c) 1988-2010 by Synopsys, Inc. ALL RIGHTS RESERVED This software and the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software is subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. The above trademark notice does not imply that you are licensed to use all of the listed products. You are licensed to use only those products for which you have lawfully obtained a valid license key. Initializing... Starting shell in Topographical mode... dc_shell-topo> 5.2.4.2 set_app_var search_path "$search_path rtl unmapped mapped" Thm cc ng dn dc tm cc file .v, .db, .ddc 5.2.4.3 define_design_lib WORK -path ./work Cc file tm sinh ra trong qu trnh tng hp c lu trong work Gi th mc chnh dc-ex gn gng, trt t 5.2.5 5.2.5 Tng kt

5.2.5.1 cc thit lp ng dn cho th vin c th c vit vo file .tcl v c gi ra bng file .synopsys_dc.setup 5.2.5.2 ch cn sa cc bin ng dn trong file common_setup.tcl cho cc thit k khc nhau 5.2.5.3 common_setup.tcl t tn cho cc bin ng dn s dng lnh : set tn_bin ng dn V d
########################################################################################## # User-defined variables for logical library setup in dc_setup.tcl ##########################################################################################

set ADDITIONAL_SEARCH_PATH libraries,

"../ref/libs/mw_lib/sc/LM ./rtl ./scripts" ;# Directories containing logical

# logical design and script files.

set TARGET_LIBRARY_FILES

sc_max.db

;# Logical technology library file

set SYMBOL_LIBRARY_FILES

sc.sdb

;# Symbol library file

########################################################################################## # User-defined variables for physical library setup in dc_setup.tcl ##########################################################################################

set MW_DESIGN_LIB

TOP_LIB

;# User-defined Milkyway design library name

set MW_REFERENCE_LIB_DIRS

../ref/libs/mw_lib/sc

;# Milkyway reference libraries

set TECH_FILE

../ref/libs/tech/cb13_6m.tf

;# Milkyway technology file

set TLUPLUS_MAX_FILE

../ref/libs/tlup/cb13_6m_max.tluplus ;# Max TLUPlus file

set MAP_FILE

../ref/libs/tlup/cb13_6m.map

;# Mapping file for TLUplus

5.2.5.4 dc_setup.tcl s dng cc bin trong file common_setup/tcl ch ti cc th vin link,target ... v d
###################################################################### # Logical Library Settings ###################################################################### set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH" set_app_var target_library $TARGET_LIBRARY_FILES set_app_var link_library "* $target_library" set_app_var symbol_library $SYMBOL_LIBRARY_FILES

###################################################################### # Physical Library Settings ######################################################################

set_app_var mw_reference_library $MW_REFERENCE_LIB_DIRS set_app_var mw_design_library $MW_DESIGN_LIB

create_mw_lib -technology $TECH_FILE \ -mw_reference_library $mw_reference_library \ $mw_design_library open_mw_lib $mw_design_library set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE \ -tech2itf_map $MAP_FILE

5.2.5.5 .synopsys_dc.setup dng gi 2 file dc_setup v common_setup t ng chy khi gi dc_shell ti ng dn cha file ny v d:
source common_setup.tcl source dc_setup.tcl

ngoi ra c th vit thm cc lnh check lib kim tra th vin

5.3 5.3. Cc iu kin gii hn tng hp

5.3.1 5.3.1. Gii hn thi gian 5.3.1.1 nh ngha L thng tin thi im xut hin v tn hiu ng h, u vo, u ra ca mch. Thng tin ny cho php b tng hp kim tra iu kin setup v hold ca cc FF trong mch Thng tin ng h: xc nh thi im xut hin sn ng h iu khin FF Cho php xc nh/v ti u tr ca cc ng tn hiu t u ra Q ca FF n u vo D ca FF (ng tn hiu REG-REG) Thng tin u vo: xc nh thi im n ca tn hiu u vo so vi sn ng h Cho php xc nh/v ti u tr ca cc ng tn hiu t u vo PI n u vo D ca FF (ng tn hiu PI-REG) Thng tin u ra: xc nh thi im cn a tn hiu u ra so vi sn ng h Cho php xc nh/v ti u tr ca cc ng tn hiu t u ra Q ca FF n u ra PO (ng tn hiu REG-PO) Hnh v

5.3.1.2 Thng tin ng h

t gii hn thi gian tr ti a cho ng logic t hp gia 2 FF: FF_start v FF_stop Tmax(REG-REG)=min(t_clk_cap-t_clk_launch)-t_setup

Khong cch gia 2 sn xung ng h lin tip dng iu khin 2 FF_start, FF_stop trong ng tn hiu ang xt. Hai loi sn ng h iu khin 2 FF_start, FF_stop c dng nh mc tham chiu tnh ton thi gian (thi im) Sn bt d liu (capture edge)
L sn c dng pht hin v lu tr d liu vo FF_stop Xut hin ti thi im t_clk_cap

Sn xut d liu (launch edge)

L sn c dng a d liu ra khi FF_start Xut hin ti thi im t_clk_lauch

Hnh v

Ch : loi sn ng h c xc nh ng vi tng ng tn hiu trong mch

Thi im xut hin 2 sn ng h bt d liu v xut d liu c quyt nh bi cc khong thi gian Chu k v rng xung ng h

 5.3.1.2..1.1.1.1

Hnh v

Lnh to ng h

5.3.1.2..1.1.1.2 create_clock -period chu_k_clk [get_ports tn_clk] 5.3.1.2..1.1.1.3 create_clock -period 3.0 [get_ports clk] # A 333Mhz clock is a 3.0ns period:

Lnh t rng xung ng h

5.3.1.2..1.1.1.4 set_min_pulse_width -high 2.5 [all_clocks] 5.3.1.2..1.1.1.5 set_min_pulse_width -low 2.0 [all_clocks]

tr do ng tn hiu ng h (Clock latency)

Lnh t latency

5.3.1.2..1.1.1.6 set_clock_latency -source 5.3.1.2..1.1.1.7 tr ca cc ng clk ngoi module ang xt 5.3.1.2..1.1.1.8 C th coi l tr ca u vo clk 5.3.1.2..1.1.1.9 set_clock_latency -max 5.3.1.2..1.1.1.10 tr ng clk bn trong module 5.3.1.2..1.1.1.11 sau khi post-layout th dng lnh 5.3.1.2..1.1.1.12 set_propagated_clock 5.3.1.2..1.1.1.13 set_clock_latency -source -max 0.7 [get_clocks clk] [get_clocks clk] set_clock_latency -max 0.3

Thi gian chuyn gi tr (0->1, 1->0)/ dc sn xung ng h

Lnh t transition

5.3.1.2..1.1.1.14 set_clock_transition 5.3.1.2..1.1.1.15 set_clock_transition 0.12 [get_clocks clk] # The maximum clock transition is 120ps or 0.12ns

S thay i thi gian n ca cc sn ng h (clock uncertainty)

chnh thi gian lan truyn ng h ti FF_start, FF_stop (Clock skew)

5.3.1.2..1.1.1.16 chnh dng 5.3.1.2..1.1.1.17 Khi sn bt n sau sn xut 5.3.1.2..1.1.1.18 ng h v d liu i theo cng hng 5.3.1.2..1.1.1.19 chnh dng lm vi phm iu kin hold 5.3.1.2..1.1.1.20 chnh dng h tr iu kin setup 5.3.1.2..1.1.1.21 chnh m 5.3.1.2..1.1.1.22 Hnh v 5.3.1.2..1.1.1.23

chnh x dch sn xung ng h (clock jitter) do ngun to ng h Phn d tr (margin) Lnh t skew, jitter, margin

5.3.1.2..1.1.1.24 set_clock_uncertainty -setup 0.15 [get_clocks clk] # The +/-30ps internal clock delay variation to register clock pins results in a 60ps worst case skew or uncertainty, if you launch

# late (+30ps) and capture early (-30ps)r; Add 40ps due to jitter and 50ps for setup margin; # This equals 150ps or 0.15 ns of total uncertainty.

Hnh v

Lnh DC

Khong cch gia 2 sn bt v xut d liu c tn bng khong thi gian ngn nht gia thi im xut hin sn bt v xut d liu =min(t_clk_cap-t_clk_launch) Nu 2 FF u c iu khin bng sn ln (xung)
t_clk_launch_min = network_latency+source_latency-0.5*uncertainty t_clk_launch_max = network_latency+source_latency+0.5*uncertainty t_clk_capture_min = clk_period+network_latency+source_latency-0.5*uncertainty t_clk_launch_max = clk_period+network_latency+source_latency+0.5*uncertainty

i vi cc thit k khng dng clk th vn phi constraint nh trn vi 1 tn hiu virtual_clk 5.3.1.3 Thng tin u vo/ tr u vo(input delay)

L thi gian xut hin mun nht ca tn hiu ti u vo k t khi c sn xut tng ng vi n Hnh v

V d 5.3.1

Nu clock c chu k l 2ns v uncertainty l 0.3ns, thi gian tr ti a ca phn mch logic t hp N l? Tmax=Tclk-Tsetup-Tinput_delay-Tuncertainty=2-0.2-0.6-0.3=0.9ns

V d 5.3.2

Hnh v

Input delay cn t bng bao nhiu? Tinput_delay=2.5-1.5-0.1-0.3=0.6ns

Input delay c phn mm tng hp s dng tnh ton/ti u tr ca ng tn hiu (PI-REG) Tmax(PI-REG)=min(t_clk_cap-t_clk_launch)-t_input_delay-t_setup 5.3.1.4 Thng tin u ra/ tr u ra(output delay) L thi gian xut hin mun nht ca tn hiu ti u ra trc khi c sn bt tng ng ca n Hnh v

V d 5.3.3

 Cho chu k ng h l 2ns, uncertainty l 0.3ns, thi gian tr ti a ca phn t hp S l bao nhiu? Tmax=Tclk-Toutput_delay-Tuncertainty=2-(0.7+0.1)-0.3=0.9ns

V d 5.3.4

Xc nh output delay cho u ra B? Toutput_delay=Tclk-Tmax=2-0.7=1.3

Output delay c phn mm tng hp s dng tnh ton/ti u tr ng tn hiu (REG-PO) Tmax(REG-PO)=min(Tclk_cap-Tclk_launch)-Toutput_delay 5.3.1.5 Ch 1: xc nh input, output delay cn xc nh r thi im ca sn xut v sn bt d liu 5.3.1.6 Ch 2: gim bt thng tin u vo/u ra dng output bng FF input delay = max FF delay output delay = clock period - min FF delay

5.3.1.7 Ch 3: Gii hn ng tn hiu t hp

Cho chu k ng h l 2ns, uncertainty l 0.3 Xc nh input delay, output delay cho B v D Tinput_delay(B)=Tmax(E)=0.4ns Toutput_delay(D)=Tsetup+Tmax(G) =0.1+0.2=0.3 Xc nh tr ti a ca F Tmax(F)=Tclk-Tinput_delay(B)-Toutput_delay(D)-Tuncertainty =2-0.4-0.3-0.3=1 5.3.1.8 Ch 4: Nu mch thit k l hon ton logic t hp

gii hn thi gian cn to ra mt ng h o

Khng gn vi tn mt tn hiu c th trong mch V d Hnh v

5.3.1.9 Lnh ca Design Compiler

5.3.2 5.3.2. Gii hn lut thit k 5.3.2.1 Cc tham s tnh ton thi gian(Environmental attributes) Cc thng s nh hng ti tr ca cell Thi gian chuyn gi tr ca u vo Tinput_r, Tinput_f

Tr khng knh dn transitor ca cng (R) Dung khng ti Cload (u ra) bin thin quy trnh ch to: P in p cung cp: V Nhit hot ng: T

Gii hn thi gian ch xc nh iu kin cho tr m khng xc nh cc iu kin tnh tr ra Ch : ch cn cung cp cc thng tin cho cng bin ca chip (cc cng ni vi u vo, u 5.3.2.2 Hnh v minh ha

5.3.2.3 a) Thi gian chuyn gi tr u vo/gi tr in tr cng u kch thch u vo Thi gian chuyn gi tr ti u vo s nh hng ti tr ca cng ti u vo

Thi gian chuyn gi tr u vo ln nht l gii hn lut thit k c quy nh trong th vin ch (th vin cell chun) cell (<cellname>) { cell_leakage_power : 3.748077e-03; threshold_voltage_group : "si38p" ; area : "8.775" ; . abc_cell () { pin (Z) { direction : "output"; } pin (CP) { direction : "input"; } pin (D) { direction : "input"; } . } pin (CP) { clock : true; direction : "input"; related_bias_pin : "VDDB VSSB"; rise_capacitance : 0.001733; rise_capacitance_range(0.001268,0.002017); capacitance : 0.001706; fall_capacitance : 0.001680; fall_capacitance_range(0.001293,0.001938); max_transition : 0.550; .. } pin (D) { direction : "input"; related_bias_pin : "VDDB VSSB"; rise_capacitance : 0.000752; rise_capacitance_range(0.000648,0.000960); capacitance : 0.000741; fall_capacitance : 0.000730; fall_capacitance_range(0.000638,0.000875); max_transition : 0.800; related_power_pin : "VDD"; related_ground_pin : "VSS"; .. } Hnh v

Nu l u vo ca vi mch Thng l 1 gi tr tuyt i, cho trong specification ca chip set_input_transition 0.12 [get_ports A]

Nu l u vo ca mt module trong chip C th xc nh thng qua in tr ra (knh) ca cng kch thch u vo ang xt Lnh DC set_driving_cell -lib_cell OR3B [get_ports A] set_driving_cell -lib_cell FD1 -pin Qn [get_ports A] set_driving_cell -lib_cell tn_cell -pin tn_pin -library tn_lib [get_ports tn_port]

5.3.2.4 b) in dung ti u ra in dung ti u ra s nh hng ti thi gian chuyn gi tr ca tn hiu ra=> nh hng ti tr ca mch Ti u ra cng ln th mch cng chm Hnh v

Nu l u ra ca chip c cho trong specification ca chip v l gi tr tuyt i Lnh DC set_load [expr 30.0/1000] [get_ports B]

Nu l u ra ca module c xc nh bng s lng cng ti a m u ra s kch thch Hnh v

Lnh DC set_load [expr [load_of my_lib/inv1a0/A]*3] [get_ports B] my_lib/inv1a0/A= tn th vin/tn_cell/tn_pin

5.3.2.5 Ch : Khi cc cng kch thch u vo v ti u ra cha bit Dng Load Budget,xc nh d phng cho thit k Gi s cc u vo c kch thch bng cell yu nht set_driving_cell -no_design_rule -lib_cell inv1a1 $all_in_ex_clk set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports clk]

mi th vin s qui nh 1 rule thit k ring -no_design_rule l tm thi dc s khng check rule t in dung u vo ln nht l 10 cell and2 set MAX_INPUT_LOAD [expr load_of my_lib/and2a1/A] * 10] set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk t in dung u ra ln nht l 3 khi 10 cell Hnh v set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]

Khi u vo c kch thch bng FF, v u ra s kch thch FF

Cng kch thch u vo s l pin Q/Qn ca FF Cng ti u ra s l pin D ca FF 5.3.2.6 c) iu kin nhit /in p/cng ngh ch to

Ch ra trong file target_library list_libs Xem cc file db c np Xc nh tn ca th vin.VD : cb13fs120_tsmc_max report_lib Xem cc thng s trong 1 th vin S dng lnh xut ra file report redirect -file lib.rpt { report_lib tn_thuvin} sh gedit lib.rpt

set_operating_conditions t thng s PVT trong th vin Xem phn operating conditions trong file lib.rpt set_operating_conditions -max cb13fs120_tsmc_max Hnh v

5.3.2.7 d) RC k sinh trn ng dy ni

ph thuc kch thc thit k(chiu di dy ni) 5.3.2.8 Tng kt lnh

5.3.3 5.3.3. V d cho Design Compiler 5.3.3.1 Spec

5.3.3.2 Schematic

5.3.3.3 MY_DESIGN.con
################################### # # UNITS # # # #

###################################

# The unit of time in this library is 1ns # The unit of capacitance in this library is 1pF #

################################### # #

# CLEAN-UP # #

###################################

# Remove any existing constraints and attributes # reset_design

################################### # # #

# CLOCK DEFINITION # #

###################################

# A 333Mhz clock is a 3.0ns period: # create_clock -period 3.0 [get_ports clk]

# External clock source latency is 700ps or 0.7ns # set_clock_latency -source -max 0.7 [get_clocks clk]

# The maximum internal clock network insertion delay or latency is 300ps or 0.3 ns: # set_clock_latency -max 0.3 [get_clocks clk]

# The +/-30ps internal clock delay variation to register clock pins results in a 60ps worst case skew or uncertainty, if you launch # late (+30ps) and capture early (-30ps)r; Add 40ps due to jitter and 50ps for setup margin; # This equals 150ps or 0.15 ns of total uncertainty. # set_clock_uncertainty -setup 0.15 [get_clocks clk] # uncertainty = 190ps

# The maximum clock transition is 120ps or 0.12ns # set_clock_transition 0.12 [get_clocks clk]

################################### # # INPUT TIMING # # # #

###################################

# The maximum "input delay" (external) on ports data1 and data2 is: # clock period - clock uncertainty - delay of S - register setup time = # Wrong: 3.0 # Right: 3.0 0.15 0.19 - 2.2 - 2.2 0.2 0.2 = 0.45ns = 0.41ns

set_input_delay -max 0.45 -clock clk [get_ports data*]

# The latest arrival time at port sel is ds1.4ns (absolute time). The total clock insertion delay or latency to the external # registers is 700ps + 300ps or 1.0ns. Therefore, the relative input delay on the port is 1.4 -1.0 = 0.4ns # set_input_delay -max 0.4 -clock clk [get_ports sel]

################################### # # OUTPUT TIMING # # # #

###################################

# The output delay at port out1 is 420ps + 80ps = 500ps or 0.5ns # set_output_delay -max 0.5 -clock clk [get_ports out1]

# The internal delay to out2 is 810ps. The external capturing clock edge happens 3ns after the launch edge, # minus the uncertainty of 0.15ns, or 2.85ns after launch. To constrain the internal delay to 0.81ns the # output delay must therefore be constrained to 2.85ns - 0.81ns = 2.04ns. # set_output_delay -max 2.04 -clock clk [get_ports out2]

# The setup time requirement on port out3 is 400ps or 0.4ns with respect to the capturing register's clock. # This is, by definition, the "set_output_delay" value # set_output_delay -max 0.4 -clock clk [get_ports out3]

################################### # #

# COMBINATIONAL LOGIC TIMING # # #

###################################

# The maximum delay through the combinational logic is 2.45ns. This can be constrained by pretending that there are # launching registers on the input ports Cin1 and Cin2 and capturing registers on the output port Cout, and applying

# corresponding input and output delays. The sum of the external input and output delay values must be equal to the # clock period minus the clock uncertainty minus the maximum combo delay = 3ns - 0.15ns - 2.45ns = 0.4ns. # This means that the input and output delay values can be 0.4 and 0.0, or 0.2 and 0.2, or 0.1 and 0.3, etc., respectively. # set_input_delay -max 0.3 -clock clk [get_ports Cin*] set_output_delay -max 0.1 -clock clk [get_ports Cout]

################################### # # #

# ENVIRONMENTAL ATTRIBUTES # #

###################################

# All input ports, except clk and Cin, are driven by bufbd1 buffers # set_driving_cell -lib_cell bufbd1 -library cb13fs120_tsmc_max \ [remove_from_collection [all_inputs] [get_ports "clk Cin*"]]

# Port Cin is a chip level input and has an input transition of 120ps or 0.12 ns #

set_input_transition 0.12 [get_ports Cin*]

# All outputs, except Cout, drive 2x bufbd7 loads # set_load [expr 2 * {[load_of cb13fs120_tsmc_max/bufbd7/I]}] [get_ports out*]

# Cout drives 25fF, or .025 pF # set_load 0.025 [get_ports Cout*]

# operating condition use to scale cell and net delays. # set_operating_conditions -max cb13fs120_tsmc_max

5.4 5.4. C s qu trnh tng hp

5.4.1 5.4.1 Qu trnh tng hp 5.4.1.1 Hnh v

5.4.1.2 B1: Tng hp mc kin trc (mc cao) 5.4.1.3 B2: Tng hp mc logic khng ph thuc cng ngh 5.4.1.4 B3: Tng hp mc cng v nh x cng ngh 5.4.1.5 Thut ton tng hp tm cch ti thiu ha din tch trong khi tha mn cc iu kin gii hn thi gian v cc iu kin khc Tm mch c hiu nng (tc ) va v c din tch nh nht 5.4.1.6 t c kt qu tng hp tt Code RTL c vit tt, ti u cho phn mm tng hp (Xem chng 6) Code RTL tun theo kiu vit code ca DC v ph thuc kinh nghim Thut ton c vit hiu qu vi phn cng Cc iu kin gii hn c t , v chnh xc Cc iu kin gii hn v tnh cht mi trng t thc t, khng qu cht Tt c cc ng tn hiu c xc nh

5.4.2 5.4.2. Mt s k thut tng hp 5.4.2.1 Ti u php ton s hc Ti gin hng s v ton hng A+2*B-2+B-A+7 = 3*B + 5 Chia s cc biu thc con Z1 = A+B+C; Z2=C+D+B=> T=B+C; Z1=A+T;Z2=T+D; Bin i SOP thnh POS A*C+B*C=(A+B)*C Chia s biu thc so snh Z1=A>B;Z2=A<B;Z3=A<=B; Dng mt b tr

Ti u cc php nhn vi hng s

Temp =In1+In2; Out1=Temp*105 (64+32+8+1) Out2=Temp*621 (105+512+4) Out1 = Temp<<6 + Temp<<5+Temp<<3+Temp Out2 = Out1+Temp<<9+Temp<<2 5.4.2.2 Chia s ti v nhn bn cng logic Trc ti u

Sau ti u

Nhn bn cc cng logic iu khin (kch thch) nhiu u ra v nm trn ng tn hiu chm nht s gip gim ti ca cng logic v tng tc ng tn hiu chm nht 5.4.2.3 Ti u qua ng bin Trc ti u

Sau ti u

Lan truyn hng s, cc cng khng kt ni, cc b o gim tr hoc/v din tch 5.4.2.4 nh thi thch nghi (Adaptive Retiming)

Trc

Sau

Retiming: thay i thi gian hot ng ca cc tn hiu bn trong mch bng cch di chuyn cc thanh ghi Ch : Retiming khng c lm thay i thi gian hot ng ca tn hiu u vo/u ra 5.4.2.5 nh thi thanh ghi (Register Retiming) always @(posedge clk) y <= a*b+c*d+e-f Tng hp

S dng thanh ghi pipeline p2_1 <=

always @(posedge clk) begin prodAB <= a*b; prodCD <= c*d; diffEF <= e-f; prodAB+prodCD; p2_2 <= diffEF; y <= p2_1+p2_2; Tng hp

tr l tr ca giai on pipeline chm nht (b nhn)

K thut Di chuyn thanh ghi

Chia tch

Ghp

Hnh v

5.5 5.5. Phn tch kt qu tng hp

5.5.1 Kim tra s vi phm iu kin thi gian 5.5.1.1 Xem xt cc ng tn hiu c slack <0 5.5.2 S dng cc k thut Timing Analysis 5.5.2.1 Tham kho thm ti liu ca Synopsys

5.6 Bi tp v d
5.6.1 Thit k v tng hp vi mch tun theo ch tiu k thut ca chip: Cd54hc192

6 Chng 6. Nng cao

6.1 6.1. Cc b m, dch, quay
6.1.1 6.1.1 B m 6.1.1.1 Hnh v

6.1.1.2 M module cnt(clk,rst_n,en,cnt); input clk,rst_n; output [7:0] cnt; reg [7:0] cnt; always @(posedge clk or negedge rst_n) if (!rst_n) cnt <= 8h00; else if (en) cnt <= cnt + 1; // combinational endmodule 6.1.1.3 Kt qu tng hp 6.1.2 6.1.2 B m vng 6.1.2.1 M module ring_counter (count, enable, clock, reset_n); output reg [7: 0] count; input enable, reset, clock; always @ (posedge clock or negedge reset_n) if (!reset_n) count <= 8'b0000_0001; else if (enable == 1'b1) count <= {count[6:0], count[7]}; endmodule 6.1.2.2 Kt qu tng hp 6.1.3 6.1.3 B quay 6.1.3.1 M module rotator (Data_out, Data_in, load, clk, rst_n); output reg [7: 0] Data_out; input [7: 0] Data_in; input load, clk, rst_n; always @ (posedge clk or negedge rst_n) if (!rst_n) Data_out <= 8'b0; else if (load) Data_out <= Data_in; else if (en) Data_out <= {Data_out[6: 0], Data_out[7]}; else Data_out <= Data_out endmodule 6.1.3.2 Kt qu tng hp 6.1.4 6.1.4 B dch 6.1.4.1 M

 always @ (posedge clk) begin if (rst) Data_Out <= 0; else case (select[1:0]) 2b00: Data_Out <= Data_Out; // Hold 2b01: Data_Out <= {Data_Out[3], Data_Out[3:1]}; // by 2 2b10: Data_Out <= {Data_Out[2:0], 1b0}; // X by 2 2b11: Data_Out <= Data_In; // Parallel Load endcase end endmodule 6.1.4.2 Kt qu tng hp 6.1.5 6.1.5 Tham s ha 6.1.5.1 parameter nh ngha hng s bn trong module C th truyn nh 1 tham s khi instantiate module 6.1.5.2 localparam nh ngha hng s trong module Khng truyn nh tham s khi instantiate module 6.1.5.3 V d 6.1.5 M

module adder(a,b,cin,sum,cout); parameter WIDTH = 8; // default is 8 input [WIDTH-1:0] a,b; input cin; output [WIDTH-1:0] sum; output cout; assign {cout,sum} = a + b + cin endmodule module alu(src1,src2,dst,cin,cout); input [15:0] src1,src2; ////////////////////////////////// // Instantiate 16-bit adder // //////////////////////////////// adder #(16) add1(.a(src1),.b(src2), .cin(cin),.cout(cout), .sum(dst)); endmodule 6.1.5.4 V d 6.1.6 M

module register2001 #(parameter SIZE=8) (output reg [SIZE-1:0] q, input [SIZE-1:0] d, input clk, rst_n); always @(posedge clk, negedge rst_n) if (!rst_n) q <= 0; else q <= d; endmodule

6.2 6.2. M t my trng thi hu hn FSM

6.2.1 6.2.1. Khi nim FSM 6.2.1.1 Hnh v

6.2.1.2 FSM c trin khai bng mch logic tun t gm 2 khi c bn Khi logic t hp m t hm trng thi k tip v hm u ra Khi FF lu tr trng thi hin ti ca mch 6.2.1.3 FSM c m t hot ng bng th chuyn trng thi hoc bng chuyn trng thi 6.2.2 6.2.2. M t FSM trong Verilog 6.2.2.1 M t logic t hp v FF ring r 6.2.2.2 Logic t hp c m t bng khi always v php gn blocking Thng s dng km lnh case, trong mi case item l 1 trng thi 6.2.2.3 FF c m t bng khi always c clock v php gn non-blocking 6.2.2.4 Ch : trnh latch Khi case lun cn nhnh default C th gn gi tr mc nh cho u ra v thanh ghi trng thi k tip trc khi case, if/else 6.2.3 V d 6.2.1 6.2.3.1 Hnh v

6.2.3.2 M 1 module fsm(clk,rst,a,b,Y,Z); input clk,rst,a,b; output Y,Z; reg Y, Z; localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10; reg [1:0] state,nxt_state; always @(posedge clk, posedge rst) if (rst) state <= S0; else state <= nxt_state; always @ (state,a,b) case (state) S0 : if (a) begin nxt_state = S1; Z = 1; end else nxt_state = S0; S1 : begin Y=1; if (b) begin nxt_state = S2; Z=1; end else nxt_state = S1; end S2 : nxt_state = S0; endcase endmodule

6.2.3.3 Kt qu tng hp

6.2.3.4 M 2

6.2.4 6.2.3. M t cc my trng thi tng tc vi nhau 6.2.4.1 V d khi cn i mt trng thi trong khong thi gian xc nh My trng thi tng tc vi b m 6.2.4.2 u ra ca mt FSM c dng iu khin mt FSM khc v ngc li. Thng s dng kiu lin lc bt tay 6.2.4.3 V d 6.2.2

th chuyn trng thi

Biu thi gian ton mch

Biu thi gian tng tc gia FSM v b m S khi mch

module eeprom(clk,rst_n,wrt_eep, wrt_data,eep_r_w_n,eep_cs_n, eep_bus,chrg_pmp_en); parameter IDLE=2'b00, BUS=2'b01, CHRG=2'b10; input clk,rst_n,wrt_eep; input [11:0] wrt_data; // data to write output eep_r_w_n,eep_cs_n; output chrg_pmp_en; // hold for 3ms inout [11:0] eep_bus; wire eep_r_w_n,eep_cs_n; reg chrg_pmp_en; // hold for 3ms reg [13:0] tm; // 3ms => 14-bit timer reg clr_tm,inc_tm,bus_wrt; reg [1:0] state,nxtState; //// implement 3ms timer below //// always @(posedge clk or posedge clr_tm) if (clr_tm) tm <= 14'h0000; else if (inc_tm) tm <= tm+1; //// @4MHZ cnt of 2EE0 => 3ms //// assign tm_eq_3ms = (tm==14'h2EE0)?1'b1 : 1'b0; //// implement state register below //// always @(posedge clk or negedge rst_n) if (!rst_n) state <= IDLE; else state <= nxtState; //// state transition logic & //// //// output logic //// always @(state,wrt_eep,tm_eq_3ms) begin nxtState = IDLE; // default all bus_wrt = 0; // to avoid clr_tm = 0; // unintended inc_tm = 0; // latches chrg_pmp_en = 0; case (state) IDLE : if (wrt_eep) nxtState = BUS; BUS : begin clr_tm = 1; bus_wrt = 1; nxtState = CHRG; end default : begin // is CHRG inc_tm = 1; chrg_pmp_en=1; if (tm_eq_3ms) begin nxtState = IDLE; end else nxtState = CHRG; end endcase end assign eep_r_w_n = ~bus_wrt; assign eep_cs_n = ~bus_wrt; assign eep_bus = (bus_wrt) ? wrt_data : 12'bzzz; endmodule Kt qu tng hp Mch

6.2.5 6.2.4. Thit k mch iu khin v ng d liu: FSMD/ASMD 6.2.5.1 Cc mch x l tn hiu (v d trong thng tin/vin thng) cn x l v dch chuyn mt lng ln d liu bng cc php ton lp i lp li 6.2.5.2 Cc mch tun t x l d liu thng c chia lm hai phn ng d liu

Bao gm cc ti nguyn tnh ton (nh b cng, nhn, dch...) cc thanh ghi lu tr d liu, cc khi logic dng dch chuyn d liu gia cc khi tnh ton, thanh ghi, v mi trng ng d liu thc hin cc thao tc tnh ton lp li trn cc b d liu khc nhau c m t bng th dng d liu th hin cc bc tnh ton tun t d liu Khi iu khin Lm mt FSM thc hin vic iu phi cc thao tc tnh ton trong ng d liu Thc hin vic iu phi, ng b hot ng ca ng d liu (hot ng ca cc khi chc nng trong ng d liu) To ra cc tn hiu np, c, dch chuyn ni dung cc thanh ghi c lnh/d liu t b nh Ghi d liu vo b nh iu hng d liu qua cc b mux iu khin cc cng 3 trng thi iu khin hot ng ca khi ALU hay cc khi x l d liu phc tp

c m t bng th chuyn trng thi, hoc Algorithmic-State Machine Hnh v

6.2.5.3 Phn chia mch thnh 2 phn gip lm r kin trc v n gin ha vic thit k 6.2.5.4 FSMD, ASMD c dng miu t hot ng ca thit k c chia thnh 2 phn ng d liu v khi iu khin thi FSMD l s kt hp ca th chuyn trng thi STG v th dng d liu Trong FSMD, cc hot ng ca ng d liu c th hin trn cc ng chuyn trng ASM l dng c bit ca lu thut ton Gm cc khi kt ni vi nhau. Mi khi gm 3 node Hnh v Trng thi: Th hin trng thi ca mch Quyt nh: Th hin iu kin chuyn trng thi ca mch ph thuc u vo iu kin: Th hin u ra ca mch

ASMD c to ra t ASM bng cch gn cc hot ng ca ng d liu vi cc ng ni gia cc trng thi. Cc hot ng ny xy ra khi phn iu khin chuyn t trng thi ny sang trng thi khc tng ng 6.2.5.5 Cc bc thit k mch iu khin v ng d liu u vo: Lu thut ton m t hot ng ca mch

u ra: Kin trc ng d liu v ASMD m t hot ng ca ng d liu v khi iu khin B1: Thit k ng d liu

B1a) Xc nh cc php ton (hot ng) ca ng d liu da trn cc php ton c trong lu thut ton B1b) Xc nh cc khi chc nng phn cng cn c thc hin cc php ton

B1c) Kt ni cc khi chc nng phn cng thnh ng d liu th hin dng dch chuyn ca d liu cn c x l nh lu thut ton B1d) Xc nh u vo iu khin v u ra trng thi ca ng d liu B2: Thit k khi iu khin B2a) Chuyn i lu thut ton thnh ASM B2b) Gn cc hot ng ca ng d liu vi ASM 6.2.5.6 V d 6.2.2 Thit k b m up/down dng FSMD 6.2.5.7 V d 6.2.3 Thit k b nhn ni tip

module serial_mult #(parameter n=8) (input clk, rst_n, input load, input [n-1:0] a, input [n1:0] b, output [2*n-1:0] c); wire b0, adder_control, load_control, compute_control; wire [n-1:0] i; data_unit #(.n(n)) datapath (.clk(clk), .rst_n(rst_n), .a(a), .b(b), .c(c), .load_control(load_control), .adder_control(adder_control), .compute_control(compute_control), .i(i), .b0(b0) ); control_unit #(.n(n)) control (.clk(clk), .rst_n(rst_n), .load(load), .b0(b0), .i(i), // status signal from datapath .load_control(load_control), // control signal to datapath .adder_control(adder_control), .compute_control(compute_control) ); endmodule module data_unit #(parameter n=8) (input clk, rst_n, input [n-1:0] a, b, output reg [2*n-1:0] c, input load_control, adder_control, compute_control, output b0, output reg [n-1:0] i ); reg [n-1:0] Rb; reg [n-1:0] Ra; reg [2*n:0] tmp; reg carry; assign b0 = Rb[0]; assign tmp = (adder_control==1)?(c[2*n1:n]+Ra):c; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin Ra <= 0; Rb <= 0; c <= 0; i <= 0; carry <= 0; end else begin if (load_control) begin Ra[n-1:0] <= a; Rb <= b; i <= 0; c <= 0; carry <= 0; end else begin if (compute_control) begin Rb <= {1'b0, Rb[n-1:1]}; // dich phai Rb c <= {tmp[2*n:1]}; // dich phai tmp i <= i+1; end end end end endmodule module control_unit # (parameter n=8) ( input clk, rst_n, input load, input [n-1:0] i, input b0, output reg load_control, adder_control, compute_control); localparam idle = 1'b0; localparam computing = 1'b1; reg current_state, next_state; always @(posedge clk or negedge rst_n) begin if (!rst_n) current_state <= idle; else current_state <= next_state; end always @(current_state, load, i, b0) begin next_state = idle; load_control = 0; adder_control = 0; compute_control = 0; case (current_state) idle: if (load) begin next_state = computing; load_control = 1; end computing: if (i==n) next_state = idle; else begin compute_control = 1; adder_control = b0; next_state = computing; end endcase end endmodule

6.3 6.3. Cc cu lnh nng cao 6.4 6.4. Hng dn code ca phn mm tng hp Synopsys
6.4.1 Cc kiu vit code khc nhau s cho kt qu tng hp khc nhau 6.4.2 Phn mm tng hp khng th t ti u m ngun RTL ti 6.4.3 Hiu cch phn mm tng hp bin dch m RTL s gip c c kt qu tng hp tt 6.4.4 6.5.1. Dng chung ti nguyn 6.4.4.1 Phn mm tng hp c th s dng 1 b ti nguyn s hc cho cc cu lnh trong if/case t c thit k nh nht m vn tha mn iu kin thi gian 6.4.4.2 Ti u ti nguyn dng chung c thc hin khi ti u mc kin trc. 6.4.4.3 Vic quyt nh c chia s hay khng ti nguyn ph thuc Cch vit code

Ch cc php ton trong cng if/case c th chia s ti nguyn Gii hn Chia s ti nguyn ch xy ra khi khng vi phm iu kin gii hn thi gian 6.4.4.4 V d:

M Kt qu tng hp 6.4.4.5 C th vit m khng cho php hoc lun yu cu chia s ti nguyn 6.4.5 6.5.2. Thay i th t ton hng 6.4.5.1 Phn mm tng hp c th thay i th t thc hin php ton tha mn gii hn thi gian

Th t s khng thay i nu s dng du ngoc n bt buc th t thc hin 6.4.5.2 V d

M Kt qu tng hp 6.4.6 6.5.3. For loop

7 Cc kin thc cn thit

7.1 Lp trnh Verilog
7.1.1 Mch logic t hp 7.1.1.1 always 7.1.1.2 If else 7.1.1.3 Assign blocking, non-blocking assignment 7.1.1.4 tr trong mch logic t hp 7.1.2 Mch tun t 7.1.2.1 always with clock

7.1.2.2 reset 7.1.2.3 case 7.1.2.4 Moore/Mealy 7.1.2.5 Setup/Hold time 7.1.2.6 Xc nh tn s ng h 7.1.2.7 Flip-Flop 7.1.3 Lp trnh FSMD/ASM

7.2 Tng hp mch (Synthesis)

7.2.1 Cu trc ASIC 7.2.1.1 Tng hp ra gate netlist dng Synopsys 7.2.1.2 Phn tch timing 7.2.2 Cu trc FPGA 7.2.2.1 Tng hp mch ln board Altera DE2 7.2.2.2 Kt ni mch Altera DE2 vi Simulink/Matlab 7.2.3 Cc thut ton tng hp mch c bn 7.2.4 Khi nim timing 7.2.5 Khi inm Datapath optimization khi dng HDL v khi synthesis

7.3 Layout mch

7.3.1 Cu trc CMOS 7.3.2 Clock tree 7.3.3 Standard cell 7.3.4 Power supply

8 Mc ch mn hc
8.1 Thit k mch s dng ngn ng m t phn cng Verilog HDL 8.2 Xy dng testbench t kim tra thit k phn cng

8.2.1 M phng HDL 8.2.2 Kim chng thit k s

8.3 Tng hp dng d liu v thit k hnh vi (behavior) 8.4 Khi nim c bn v phn tch thi gian (Timing analysis) 8.5 Ti u thit k phn cng (thi gian, din tch, nng lng) 8.6 Suy ngh kiu phn cng!!!

9 Yu cu kin thc
9.1 Biu din s
9.1.1 Nh phn, h 16 9.1.2 C du 9.1.2.1 M b 2 9.1.3 Khng du

9.2 i s Bool 9.3 Thit k mch mc cng logic

9.3.1 Ti u mch bng ba Karnaugh

9.4 My trng thi hu hn (FSM)

9.4.1 My More 9.4.2 My Mealy 9.4.3 Trin khai my trng thi hu hn bng logic t hp 9.4.3.1 Phng php ti u my bng cch tm trng thi tng ng 9.4.3.2 Phng php m ha trng thi

10 Ti liu tham kho

10.1 Advanced Digital Design Verilog HDL, Michael D. Ciletti. 10.2 IEEE Standard Verilog Hardware Description Language, IEEE, Inc., 2001

10.3 IEEE Standard for Verilog Register Transfer Level Synthesis, IEEE, Inc., 2002 10.4 Digital Design and Computer Architecture, David Money Harris 10.5 Bi ging ca Eric Hoffman

11 Cng c phn mm thc hnh

11.1 Modelsim HDL Simulation Tools (Mentor)
11.1.1 http://model.com/content/modelsim-pe-student-edition-hdl-simulation See document(s): modelsim-pe-student-edition-hdl-simulation

11.2 Cng c tng hp IC: Synopsys - Design Compiler 11.3 Cng c tng hp FPGA: Quartus II Web Edition Software
11.3.1 https://www.altera.com/download/software/quartus-ii-we See document(s): quartus-ii-we

12 im s
12.1 Gia k 30%
12.1.1 20%: Bi tp ln 12.1.1.1 Originality 12.1.1.2 Workload 12.1.1.3 Funny 12.1.2 10%: Cu hi & Tr li

12.2 Cui k: 70% 12.3 10%: im thng

13 Thi gian & a im

13.1 Th 3,14h15-17h20, TC305 13.2 Th 4, 7h35-11h50, D6-101