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Cc bc thc hin.............................................................................................................................3
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2
Code...................................................................................................................................................17
2.2.1
Code memoryDesign................................................................................................................17
2.2.2
Code C Nios...............................................................................................................................18
2.2.3
Code m phng.........................................................................................................................18
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1. bi
Thit k memory 4x32 bits, c cc tn hiu
clk (CLOCK_50)
cs (chip_select)
re (read_enable)
we (write_enable)
addr[1:0] (address)
data_in[31:0]
data_out[31:0]
Hnh 1. 1 S khi memory
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T
Hnh 2. 1 Cc th mc v tp tin chnh
2.1.1
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Hnh 2. 9 ng b cc tn hiu
ca component t to v Avalon Bus
9 Sau khi ht li, nhn Finish, ta c component mi trong SOPC
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2.1.3
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Hnh 2. 17 To code C
9 Sau khi bin dch xong, Nios s to ra 3 file
o onchip_mem.hex ( cp u mc 2)
o onchip_mem.dat
o onchip_mem.sym
Trong , 2 file cui cha trong th mc nios_sim phc v cho vic m
phng
2.1.5
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Hnh 2. 30
So snh ni dung memory gia Nios v Modelsim
9 Ngoi ra, ta cn c th quan st c ni dung onchip_mem trong Modelsim
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2.2 Code
2.2.1
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Code memoryDesign
module memoryDesign (
// input
addr,
re,
data_in,
we,
clk,
cs,
// output
data_out
);
input
input
input
[1:0]
[31:0]
we,
re,
clk,
cs;
addr;
data_in;
output
[31:0]
data_out;
reg
reg
[31:0]
[31:0]
memory [0:3];
data_out;
endmodule
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Trong :
DATA_WIDTH: s ng d liu
ADDR_WIDTH: s ng a ch
[0:15]
9 Memory nhn gi tr ghi vo khi cs (chn chip), we (cho php ghi vo) v ~re
(khng cho php c ra)
9 Memory c gi tr ra khi cs (chn chip), ~we (khng cho php ghi vo) v re
(cho php c ra)
2.2.2 Code C Nios
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#include <stdio.h>
#include <system.h>
int main()
{
// khai bao
volatile int * ptr = (int *) MEMORYDESIGN_INST_BASE;
*ptr
= 0x99;
*(ptr + 0x1) = 0x10;
*(ptr + 0x2) = 0x23;
*(ptr + 0x3) = 0x567;
return 0;
}
Phn cng
B nh
Phn mm
offset = 0x0
0x0
0x1
0x2
0x3
ptr
offset = 0x4
0x4
0x5
0x6
0x7
ptr+1
offset = 0x8
0x8
0x9
0xa
0xb
ptr+2
0xc
0xd
0xe
0xf
offset = 0xc
Hnh 3. 3 a ch vt l v a ch logic
ptr+3
2.2.3
Code m phng
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clk;
reset_n;
xxx XXX(
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// Inputs
clk,
reset_n
);
initial
clk = 1b0;
always
#10 clk <= ~clk;
initial
begin
reset_n <= 0;
#200 reset_n <= 1;
end
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