MC LC CHNG 1: CC KHI NIM C BN TRONG H THNG NHNG ................ 3 1.1. H nhng ........................................................................................................... 3 1.2. H thi gian thc ...............................................................................................

3 1.3. Biu din s v d liu ...................................................................................... 3 1.4. Cu trc phn cng ca h thng nhng ............................................................ 4 1.5. H iu hnh nhng v phn mm nhng .......................................................... 5 1.5.1. H iu hnh nhng .................................................................................... 5 1.5.2. H iu hnh thi gian thc RTOS: (Realtime Operationg System ) ......... 6 1.5.3. Phn mm nhng ........................................................................................ 7 1.6. Quy trnh thit k h thng nhng ..................................................................... 8 1.7. M hnh h thng nhng .................................................................................. 10 CHNG 2: H VI IU KHIN ARM ................................................................. 11 2.1. Tng quan ....................................................................................................... 11 2.2. C ch Pipeline ............................................................................................... 12 2.3. Cc thanh ghi .................................................................................................. 13 2.4. Thanh ghi trng thi chng trnh hin hnh ................................................... 14 2.5. Cc mode ngoi l ........................................................................................... 15 2.6. Tp lnh ARM 7.............................................................................................. 16 2.6.1. Cc lnh r nhnh ..................................................................................... 18 2.6.2. Cc lnh x l d liu ............................................................................... 18 2.6.3. Cc lnh truyn d liu ............................................................................. 19 2.6.4. Lnh SWAP ............................................................................................. 20 2.7. Ngt mm (SWI Software Interrupt Instruction) ........................................... 20 2.8. n v MAC (Multiply Accumulate Unit (MAC) ............................................ 21 2.9. Tp lnh THUMB ........................................................................................... 21 2.10. Phn mm pht trin v cng c phn cng ................................................... 23 2.10.1. Cu trc file start up ............................................................................... 23 2.10.2. Cng c phn cng ................................................................................. 25 2.10.3. Cch vit chng trnh C vi tp lnh ARM v tp lnh THUMB .......... 25 2.11. Cu trc bn trong ......................................................................................... 26 2.11.1. Bn b nh ........................................................................................ 26 2.11.2. Lp trnh thanh ghi ................................................................................. 27 Trang 1

2.11.3. Memory Acelerator Module (MAM) ...................................................... 27 2.11.4. PLL- Phase Locked Loop ....................................................................... 29 2.11.5. B chia bus (VLSI Peripheral Bus Divider) ............................................ 32 2.12. Cc cng vo ra ............................................................................................. 33 CHNG 3: LP TRNH VI IU KHIN ARM ................................................... 34 3.1. Hng dn s dng phn mm Keil C ............................................................. 34 3.2. Truy nhp cc chn vo ra chung..................................................................... 42 Th d 1: Vit chng trnh iu khin led n sng nhp nhy ......................... 43 Th d 2: Chng trnh hin th ch trn LCD .................................................... 44 3.3. Lp trnh ngt .................................................................................................. 50 3.3.1. Chn Connect Block ................................................................................. 50 3.3.2. Cc chn ngt ngoi .................................................................................. 51 3.3.3. Cu trc ngt ............................................................................................ 52 3.3.4. Ngt FIQ .................................................................................................. 54 3.3.5. Kt thc ngt ............................................................................................ 56 3.3.6. Vecto IRQ ................................................................................................ 56 3.3.7. Kt thc mt ngt IRQ .............................................................................. 57 3.3.8. Ngt khng c a ch ............................................................................... 58 3.3.9. Kt thc ngt khng a ch ...................................................................... 59 3.4. Lp trnh Timer ............................................................................................... 59 3.4.1. Cc Timer ................................................................................................. 59 3.4.2. ng h thi gian thc (Real Time Clock - RTC) .................................... 67 3.5. Lp trnh qua UART........................................................................................ 70 3.6. Giao din I2C .................................................................................................. 78 3.7. Giao din SPI .................................................................................................. 81 3.8. Chuyn i ADC v DAC ............................................................................... 83 3.8.1. Chuyn i ADC ...................................................................................... 83 3.8.2. Chuyn i D/A........................................................................................ 85 3.9. Truyn d liu qua CAN(Controller Area Network) ........................................ 85 TI LIU THAM KHO .......................................................................................... 92

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CHNG 1: CC KHI NIM C BN TRONG H THNG NHNG (tng s tit: 3T, s tit l thuyt: 3T, s tit thc hnh: 0) 1.1. H nhng H nhng l mt phn h thng x l thng tin nhng trong cc h thng ln, phc hp v c lp. Th d: t, t lnh, cc thit b o lng, iu khin, truyn thng. L nhng t hp ca phn cng v phn mm thc hin mt hoc mt nhm chc nng chuyn bit, c th (Tri ngc vi my tnh PC l a nng). Mt h thng nhng l mt my tnh vi cht lng cao, yu cu v tin cy cao hn cc loi my tnh khc. Cc thit b PDAs, Web pad khng phi l h thng nhng. 1.2. H thi gian thc Chia lm 2 loi: Thi gian thc cng l khi h thng hot ng vi yu cu tho mn s rng buc trong khung thi gian cng tc l nu vi phm th s dn n hot ng ca ton h thng b sai hoc b ph hu. Th d: L phn ng ht nhn, Thi gian thc mm l khi h thng hot ng vi yu cu tho mn rng buc trong khung thi gian mm, nu vi phm v sai lch nm trong khong cho php th h thng vn c th hot ng c v chp nhn c. Th d nh h thng pht thanh truyn hnh. Hu ht h nhng l cc h thi gian thc v hu ht cc h thi gian thc l h nhng-> Thuc tnh thi gian l thuc tnh tiu biu cho h thng nhng. 1.3. Biu din s v d liu n v c bn nht trong biu din thng tin ca h thng s c gi l bit, chnh l k hiu vit tt ca thut ng binary digit. 1964, IBM thit k v ch to my tnh s s dng mt nhm 8 bit nh a ch b nh v nh ngha ra thut ng 8 bit = 1 byte. Ngy nay s dng rng ri thut ng word l mt t d liu dng biu din kch thc d liu m c x l mt cch hiu qu nht i vi mi Trang 3

loi kin trc x l s c th. Chnh v vy mt t c th l 16 bits, 32 bits, hoc 64 bits Mi mt byte c th c chia ra thnh hai na 4 bit v c gi l cc nibble. Nibble cha cc bt trng s ln c gi l nibble bc cao, v nibble cha cc bit trng s nh c gi l nibble bc thp. Cc h thng c s: Mt cch tng qut mt h biu din s c s b v a l mt s nguyn nm trong khong gi tr c s b c biu din nh sau:
A ai xbi1
i 0 n

c s binary (nh phn), c s decimal (thp phn), c s hexadecimal, c s 8 Octal (bt phn). 1.4. Cu trc phn cng ca h thng nhng

Hnh 1.1. Kin trc c bn ca ca cc chip vi iu khin nhng CPU: ng vi tr l b no, gi m v thc thi lnh, gm khi ALU, b gi m, b tun t v cc thanh ghi.

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Xung nhp v trng thi tn hiu: Hot ng ca h thng c thc hin ng b hoc d b theo cc xung nhp chun. Cc nhp c ly trc tip hoc gin tip t mt ngun xung chun thng l cc mch to xung hoc dao ng thch anh. Bus: c 3 loi, bus d liu, a ch v iu khin (Bus iu khin phc v truyn ti cc thng tin d liu iu khin hot ng ca h thng). B nh: c 2 loi kin trc Kin trc von neumann: khng phn bit vng cha d liu v m chng trnh. C chng trnh v d liu u c truy nhp theo cng mt ng. Kin trc Havard: tch/phn bit vng lu m chng trnh v d liu. M chng trnh ch c th c lu v thc hin trong vng cha ROM v d liu cng ch c th lu v trao i trong vng RAM. Hu ht cc vi x l nhng ngy nay s dng kin trc b nh Havard hoc kin trc Havard m rng (tc l b nh chng trnh v d liu tch bit nhng vn cho php kh nng hn ch ly d liu ra t vng m chng trnh). B nh chng trnh: Eprom v Flash L cc chp kh trnh, cu to t cc transitor, eprom c th xa bng tia cc tm, trong khi Flash c th xa bng cc xung in, c th lp trnh trc tip v khng cn tho ra khi mch. B nh RAM: gm SRAM v DRAM B iu khin ngt: X l yu cu ngt B nh thi ch canh (Watchdog Timer): L mt b nh thi c bit nh ngha 1 khung thi gian hot ng bnh thng ca h thng. T ng reset li h thng khi pht hin cc s c mm nh h thng b treo hoc chy qun. Khung thi gian do ngi lp trnh t ra. 1.5. H iu hnh nhng v phn mm nhng 1.5.1. H iu hnh nhng - ng vai tr trung gian tng tc trc tip vi phn cng v cc chng trnh lp trn cng nh ngi s dng: Qun l cc tin trnh, qun l ti ngyn v bo v cc ti nguyn khi s xm phm. Trang 5

- c np v thc thi u tin khi h thng khi ng - np h iu hnh cn s dng b np boot-loader, c kch thc nh gn, m nhim chc nng tin h iu hnh. - B np khi to cng c nhim v khi to vng nh d liu v cc thanh ghi h thng trc khi nhy ti chng trnh ng dng chnh. - C rt nhiu dng khc nhau ca b np khi to, t dng n gin n phc tp. 1.5.2. H iu hnh thi gian thc RTOS: (Realtime Operationg System ) - Cc chc nng chnh nh nh thi, gii quyt xung t d liu, giao tip gia cc tc v process/task.->Ngn gn: RTOS l h iu hnh a nhim - multitasking dng cho cc ng dng thi gian thc. - RTOS: Cung cp cc giao tip gia phn cng v chng trnh ng dng, vi cc tnh nng ch yu sau: a nhim - Multitasking, ng b - Sync , x l s kin v ngt, I/O, truyn thng gia cc tch v process/task, qun l Timer, Clock v b nh (ta chung l qun l ti nguyn).

Hnh 1.2. Cu trc ca OSEK Phn loi: a. Cc h iu hnh mang tnh thng mi: thng nh v nhanh, nh QNX, PDOS, pSOS, VxWorks, Nulceus, ERCOS, EMERALDS, Windows CE, chng c cc c im sau: Trang 6

+ C thi gian chuyn ng cnh v thi gian p ng nhanh. + + + Kch thc rt nh. Khng c b nh o v c th c nh m, d liu trong b nh. H thng a tc v v chun giao tip lin qu trnh. Cc mailbox, cc

s kin, cc tn hiu v cc n bo c nh ngha tt. Nhng h iu hnh ny thng c cc c t tt v c cc cng c tt pht trin cc ng dng nhng thi gian thc. N h tr cc rng buc thi gian thc vi cc dch v nh: + Cc gii hn thi gian thc hin. + + + + + ng h thi gian thc. Lp lch th t u tin. Cnh bo c bit v thi gian qu hn (timeout). H tr cc hng i thi gian thc. Cung cp vic x l tr, treo hay kch hot vic thc hin.

b. H iu hnh thi gian thc m rng ti Unix v cc h iu hnh khc Cc h iu hnh ny nh: RT-UNIX, RT-LINUX, RT-MACH, RT-POSIX. Chng chm hn v c kh nng d on t hn so vi cc h iu hnh thi gian thc thng mi trn nhng chng li c nhiu chc nng v mi trng pht trin tt hn da trn tp cc giao tip chun v thn thin. c. Cc nhn cho mc ch nghin cu Th d nh: Spring, MARS, HARTOS, MARUTI, ARTS, CHAOS, DARK. Cc h iu hnh ny c cc c im sau: + + + + H tr cc thut ton lp lch thi gian thc v vic phn tch thi gian. H tr cc dch v c bn ng b thi gian thc. Nhn mnh kh nng d on hn l hiu nng trung bnh. H tr cho kh nng chu li.

- i vi LPC2000 th OS c xem l h iu hnh tt nht. 1.5.3. Phn mm nhng - Ngn ng c s dng pht trin cc ng dng nhng thng l C hoc Assembler. - Keil C l cng c h tr vit son tho, debug v bin dch code (c C v ASM). Trang 7

- Simulator l mt chng trnh phn mm cho php ngi pht trin m chng trnh chy m phng mt chng trnh vit cho mt nn VXL/VK (nn phn cng ch) trn mt mi trng phn cng khc (hay cn gi l mi trng pht trin); cho php chy tng bc, kim th, iu chnh vi cc gi tr khc nhau, s dng cc thut ton khc nhau. H tr cc chc nng ging nh trn phn cng ch, c th km theo emulator. - Emulator l mt thit b phn cng c kh nng thc hin nh mt nn phn cng ch ( Cn gi l cng c pht trin thi gian thc bi v n cho ta phn ng vi cc s kin nh VK ch thc thi) Cc b Emulator thng c km theo c phn chng trnh gim st (monitor program) cho php ngi pht trin chng trnh cho VK ch kim tra ni dung, trng thi cc thanh ghi v cc khu vc b nh v thit lp cc im dng khi thc hin chy chng trnh. 1.6. Quy trnh thit k h thng nhng Khi tip cp kin trc h thng nhng di gc nhn k thut c th s dng mt s m hnh miu t chu k thit k. Mt s m hnh in hnh nh sau: M hnh big-bang: M hnh ny v c bn l khng cn c k hoch v quy trnh trc v trong qu trnh thit k. M hnh code anh fix: a ra ra cc yu cu nhng khng c quy trnh trc khi bt u pht trin d n. M hnh waterfall(thc nc): Pht trin h thng theo tng bc, c c kt qu ca bc trc mi thc hin bc sau v lp li t u.

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Hnh 1.3. M hnh thc nc M hnh spiral (xoy c): L mt quy trnh pht trin h thng theo tng bc, ti mi bc c s thay i v quay li thit k bc trc sao cho ph hp.

Hnh 1.4. M hnh xon c Thc t ngi ta thng kt hp cc m hnh, nh m hnh chu k thi gian sng l s kt hp ca m hnh waterfall v m hnh spiral

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Hnh 1.5. M hnh pht trin h thng theo chu k thi gian sng 1.7. M hnh h thng nhng M hnh h thng nhng gm 3 lp

Hnh 1.5. M hnh tng th ca h thng nhng

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CHNG 2: H VI IU KHIN ARM 2.1. Tng quan - H vi iu khin LPC2000 l ARM7, ngi lp trnh khng cn thit phi thnh tho ARM 7 s dng LPC2000 m vn phc tp l trnh bin dch C. - Ngi lp trnh cn c kin thc c bn v cch CPU lm vic v cc c tnh ca n to ra cc thit k tin cy. - ARM 7 l mt my tnh nh vi tp lnh nh, kh nng tnh ton cao, tiu th nng lng thp. - Vi iu khin ARM c pht trin theo kin trc RISC (Reduced Instruction Set Computer): - Ch c cc lnh np hoc lu tr l c th tham chiu ti b nh, - Tn ti t lnh v kiu nh a ch, khun dng lnh c nh, - C nhiu tp thanh ghi, - Cc lnh thc hin trong mt chu ky my, - Lnh c thc hin trc tip trn phn cng(CISC c 1 chng trnh thng dch nh), - Chng trnh bin dch m ngun phc tp(CISC-chng trnh thng dch phc tp), - H tr c ch pipeline, - Kch thc chng trnh ln. Cu trc cc chn: Th d cc chn ca LPC2101:

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Hnh 2.1. Cu trc cc chn ca LPC2101 2.2. C ch Pipeline - Tri tim ca ARM7 l c ch pipeline, thc thi lnh theo ba bc: c lnh, gii m lnh v thc thi lnh.

Hnh 2.2. Ba bc thc hin ca pipepline - Pipeline c phn cng c lp thc hin cc bc, trong khi lnh th nht ang thc thi, lnh th 2 c gii m v lnh th 3 c c ln pipeline. - Hu ht cc lnh ca ARM 7 c thc thi trong 1 chu k my.

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- Pipeline lm vic rt tt trong trng hp chng trnh khng r nhnh. ARM ch cho php thc hin cc bc nhy ngn trong on chng trnh. - Pipeline l mt thnh phn ca CPU, thanh ghi PC chy 8 bytes u ca lnh hin hnh s c thc thi. Th d: 0x4000 LDR PC,[PC,#4]-> PC=0x400C 2.3. Cc thanh ghi - ARM7 c kin trc kiu load and store, bi vy, thc hin cc lnh x l d liu th tt c cc d liu phi c ti t b nh vo mt tp cc thanh ghi trung tm, lnh x l d liu c thc hin v lu tr d liu tr li b nh.

Hnh 2.3. Kin trc load and store ca ARM 7 - ARM7 c 17 thanh ghi 32 bt: - Cc thanh ghi R0 n R12 l cc thanh ghi chung, - Thanh ghi R13 l thanh ghi con tr ngn xp, - R14 l thanh ghi lin kt, - R15 l thanh ghi b m chng trnh (PC) v - Thanh ghi trng thi chng trnh CPSR. - Thanh ghi R14 dng trong chng trng hp gi n chng trnh con gn th n s ct gi a ch ca tr v ca chng trnh chnh, nu trong chng trnh con ny gi n mt chng trnh con khc th a ch ca chng trnh chnh phi c ct gia vo ngn xp.

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Hnh 2.4. Cc thanh ghi ca ARM7 2.4. Thanh ghi trng thi chng trnh hin hnh

Hnh 2.5. Thanh ghi trng thi chng trnh CPSR - CPU ARM7 thc thi 2 loi lnh: Tp lnh ARM 32 bt v tp lnh c nn 16 bt. Bt T s quyt nh loi lnh no s c thc thi, ngi lp trnh khng nn set hay xa gi tr ca bt ny. - ARM7 c 7 ch hot ng khc nhau, ngi lp trnh thng chy trong ch ngi dng truy cp n cc bank thanh ghi t R0-R15 v thanh ghi trng thi chng trnh(CPSR). Tuy nhin khi gp cc ngoi l nh ngt, li b nh, ngt mm CPU s chuyn sang ch khc. Mi ch cc thanh ghi R13 v R14 c gi tr Trang 14

ring. ch ngt nhanh FIQ cc thanh ghi R7-R12 c gi tr ging nhau (khng cn dng stack lu ch).

Hnh 2.6. 6 ch hot ng ca APU ARM7 2.5. Cc mode ngoi l - Khi c mt ngoi l xy ra, CPU s chuyn ch v thanh ghi PC s c y v a ch ca vecto ngoi l. Bng vecto bt u t a ch 0 trng a ch vecto ngt. - Mi vecto ngoi l l 4 bytes.

Hnh 2.6. Bng cc vecto ngt

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Hnh 2.7. Th t u tin ca cc ngt

Hnh 2.8. Th d v trt t x l khi c mt ngoi l ngt xy ra

Hnh 2.9. CPU tr li trng thi ban u khi kt thc ph v ngoi l 2.6. Tp lnh ARM 7 - ARM7 c 2 tp lnh: Tp lnh m rng 32 bt v tp lnh nn (THUMB) 16 bt. - CPU ARM7 c thit k h tr x l theo kiu big endian hay little endian:

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Hnh 2.10. Hai kiu x l ca CPU ARM7 - Mt c im th v ca ARM7 l tt c cc lnh u c th l cc lnh c iu kin, bng cch so snh 4 bt t bit 28 n bt 31 ca kt qu thc hin lnh vi cc bt iu kin trong thanh ghi CPSR, nu iu khin khng tha mn th lnh s khng c thc thi. - Cc lnh x l d liu s b nh hng bi cc bt iu kin trong thanh ghi CPSR. Hai lnh c bn MOV v ADD c th t cc tin t ng trc vi 16 iu kin nh sau:

Hnh 2.11. 16 iu kin c kim tra trc khi thc thi lnh Trang 17

Th d: EQMOV R1,#0x00800000; Gi tr 0x00800000 ch a vo R1 khi kt qu cui cng ca lnh c cc bt tng ng vi 4 bt trong thanh ghi CPSR v bt c Z c set =1. - Cc lnh ca ARM7 c th chia thnh 6 nhm: Cc lnh r nhnh, cc lnh x l d liu, truyn d liu, truyn khi d liu, lnh s hc v ngt mm. 2.6.1. Cc lnh r nhnh - Cho php nhy tin hoc li trong phm vi 32MB, a ch ca lnh tip theo s c lu vo thanh ghi lin kt R14. - Lnh r nhnh c 2 bin th: R nhnh trao i (branch exchange) v r nhnh lin kt trao i (branch link exchange). Hai lnh ny c ging nhau nhng lnh r nhnh lin kt a ch ca lnh tip theo c cng thm 4 bytes ri a vo R14. 2.6.2. Cc lnh x l d liu C php tng qut:

Hnh 2.12. C php tng qut ca mt lnh x l d liu c iu kin Mi lnh u c 2 ton hng, trong ton hng th nht phi l thanh ghi, ton hng cn li c th thanh ghi hoc gi tr c th. Bt S c s dng iu khin iu kin ca lnh: S=1 th iu kin ca lnh ph thuc vo kt qu ca lnh, S=0 th khng c iu g xy ra Nu S=1 v PC l thanh ghi cha kt qu th SPSR ca ch hin hnh c copy vo CPSR.

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Hnh 2.13. Bng cc lnh x l d liu 2.6.3. Cc lnh truyn d liu

Hnh 2.14. Cc lnh truyn d liu

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Hnh 2.15. Cc lnh truyn mt khi d liu 2.6.4. Lnh SWAP - ARM7 h tr cc tn hiu thi gian thc vi mt lnh swap cho php trao i ch ni dung ca hai thanh ghi. - Lnh ny c h tr trong th vin ARM ch khng trc tip t ngn ng C.

Hnh 2.16. M t lnh swap trong ARM7 2.7. Ngt mm (SWI Software Interrupt Instruction)

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Cc ngt mm sinh ra mt ngoi l khi thc thi, a vi x l vo ch hot ng gim st v PC nhy ti a ch 0x00000008. Cng nh cc lnh ARM khc, lnh ngt mm cha mt m iu kin thc thi trong 4 bt thp ca ton hng, cc bt cn li l trng rng.

Hnh 2.17. iu kin ca ngt mm CPU vo ch gim st C th gi lp chng trnh con phc v ngt ca ngt mm nh sau: switch( *(R14-4) & 0x00FFFFFF) // Kim tra gi tr //c lu tr trong thanh ghi lin kt { case ( SWI-1): } 2.8. n v MAC (Multiply Accumulate Unit (MAC) - MAC h tr php nhn s nguyn kiu integer v long integer, khi nhn kiu integer 2 thanh ghi 32 bt vi nhau th kt qu l 32 bt c t vo thanh ghi th 3. Khi nhn 32 bt kiu long integer th kt qu l 64 bt v c t vo 2 thanh ghi. - Cc lnh nhn dng ASM: Tn lnh MUL MULA UMULL UMLAL SMULL SMLAL Multiply Multiply accumulate Unsigned multiply Unsigned multiply accumulate Signed multiply Signed multiply accumulate Vit tt 32 bit 32 bit 64 bit 64 bit 64 bit 64 bit Kt qu

Bng 2.1. Cc lnh nhn trong vi iu khin ARM 2.9. Tp lnh THUMB - Tp lnh ARM l tp lnh 32 bt, ARM c tp lnh 16 bt gi l tp lnh THUMB. Tp lnh THUMB thc cht l tp lnh nn li t tp lnh ARM. Trang 21

Hnh 2.18. Tp lnh THUMB c nn li t tp lnh ARM - Tp lnh THUMB cho gi tr kt qu thp hn tp lnh ARM nhng m cc kt qu ny chim mt t l ln hn. Tp lnh THUMB tit kim c khng gian nh 30% v chy nhanh hn 40% so vi tp lnh ARM. - Tp lnh THUMB khng c iu kin thc thi tr cc lnh r nhnh. Cc lnh x l d liu th cn c mt thanh ghi ngun v mt thanh ghi ch. Th d: Vi lnh cng thanh ghi R0 v R1: Dng lnh ARM: ADD R0, R0,R1 //R0 = R0+R1 Dng lnh THUMB: ADD R0,R1 // R0 = R0+R1 - Tp lnh THUMB ch c th truy cp n cc thanh ghi thp t R0-R7, cc thanh ghi cao t R8-R12 b gii hn truy cp:

Hnh 2.19. M hnh lp trnh tp lnh THUMB Trang 22

Ngi lp trnh khng th truy cp trc tip vo thanh ghi CPSR v SPSR. Ngi lp trnh c th s dng 2 lnh BLX v BX chuyn ch hot ng vi cc lnh. Khi reset vi iu khin lm vic vi tp lnh THUMB, khi c 1 ngoi l xy ra th s chuyn sang lm vic vi tp lnh ARM, khi kt thc ngoi l th quay tr v lm vic vi lnh ARM.

Hnh 2.20. Trao i gia lnh ARM v lnh THUMB 2.10. Phn mm pht trin v cng c phn cng - Keil C ARM l cng c cho php lp trnh m phng vi iu khin ARM vi h thng th vin c h tr tng i y v vi iu khin core ARM 7 nh: h vi iu khin LPCxxxx v ARM966E-S, cortex-M0 n cortex-M3. - Phn mm isp ca atmel v H-jtag bin dch v np code ln board. 2.10.1. Cu trc file start up - Phn u cung cp bng vecto ngt:

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Hnh 2.21. Cc nh ngha cc vecto ngt trong file startup.s Bng vecto ngt c nh ngha ti a ch 0x00000000 v cho php b m chng trnh nhy n chng trnh con ph v ngt ( ISR-interupt service routine). Ri a ch ca vio iu khin l lin tip, khng b ngt qung trong bng vecto ngt. Lnh LDR (Load Register) c s dng ti hng tng ng vi vecto ngt trong bng vecto ngt. - Bng vecto ngt v bng cc hng nm 64 bytes u tin ca b nh. - Lnh NOP c s dng nhy n v tr vecto ngt ti a ch 0x00000014, v tr li. - Phn tip trong file startup.s cu hnh con tr nh ngn xp cho tng ch hot ng: - Kch thc Stack tnh theo byte, th d trong file startup ca LPCxxxx nh sau:

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Hnh 2.22. Cu hnh stack cho tng ch hot ng - Vng nh dnh cho stack c nh ngha phn a ch cao nht ca b nh v ln dn v phn a ch thp. 2.10.2. Cng c phn cng - H LPC2000 ca hng Philips c nhiu cng cho php kt ni vi iu khin vi my tnh, thng c s dng nht l cng JTAG. Khi kt ni trc tip vi my tnh cho php ngi lp trnh debug trc tip trn mch phn cng:

Hnh 2.23. Kt ni LPC2000 vi my tnh qua cng JTAG - ng thi km theo module ETM cho php debug chng trnh: nh theo di thi gian thc, theo di s kin v phn tch qu trnh thc thi. 2.10.3. Cch vit chng trnh C vi tp lnh ARM v tp lnh THUMB - s dng cc nh ngha a ch cc ARM7, trong chng trnh cn khai bo th vin hp l, th d vi h LPC c cc khai bo: #include LPC2xxx.h hoc LPC21xx.h hoc LPC210x.h - Ngi lp trnh c th a ra cc hm c bin dch theo lnh tp ARM hoc tp THUMB. ch nh mt hm s c bin dch theo tp lnh no dng directive #pragma, th d: Trang 25

#pragma ARM // khai bo cc lnh ARM int main(void) { while(1){ THUMB_function(); //gi n hm THUMB }} #pragma THUMB //Switch to THUMB instructions void THUMB_function(void) { unsigned long i,delay; for (i = 0x00010000;i < 0x01000000 ;i = i<<1){ for (delay = 0;delay<0x000100000;delay++){} //to vng lp IOSET1 = i; //chuyn n led tip theo }} - C th ch ra trc tip trn lnh: int ARM_FUNCTION ( int my_var) __ARM {} int THUMB_FUNCTION ( int my_var) __THUMB {} 2.11. Cu trc bn trong 2.11.1. Bn b nh

Hnh 2.24. Trang 26

2.11.2. Lp trnh thanh ghi - Mt thanh ghi chc nng c iu khin bi 3 thanh ghi ngi dng, mt thanh ghi c trng thi, mt thanh ghi xa v mt thanh ghi ghi d liu ln.

Hnh 2.25.Cu trc tng qut khi truy cp thanh ghi chc nng trong ARM7 2.11.3. Memory Acelerator Module (MAM) - L b nh nm gia b nh Flash v CPU ARM, c tc thc thi cao.

Hnh 2.26: M hnh b nh MAM - CPU ARM c th chy tc 80MHz, mi ln chp Flash truy cp ht 50ns. - Flash chy tc 20MHz Trang 27

- MAM c to ra nh l mt cache y cho php CPU d dng truy cp trc tip vo FLASH.

Hnh 2.27. Truy cp b nh FLASH qua MAM - Khi c cc lnh t bank th nht th bank th hai c cht. - MAM l trong sut vi ngi dng v c cu hnh bi 2 thanh ghi: iu khin (MAMCR) v nh thi (MAMTIM). Thanh ghi nh thi c s dng iu khin mi quan h gia CPU v FLASH bng cch thit lp 3 bt u tin ca n ch nh chu k xung nhp ca CPU c yu cu bi MAM truy cp vo FLASH. - Khi FLASH c tc 20MHz v CPU c c th c tc cc i l 60MHz, s chu k yu cu truy cp FLASH l 3. Th d: Cu hnh MAM #include "LPC21xx.h" void ChangeGPIOPinState(unsigned int state); int main(void){ unsigned int delay,val; unsigned int FLASHer = 0x00010000; // Khai bo cc b IODIR0 = 0x00FF0000; VPBDIV = 0x02; ADCR = 0x00270601; ADCR |= 0x01000000; while(1) { do { val = ADDR; // c thanh ghi d liu b chuyn i A/D Trang 28 // Thit lp A/D: 10-bit AIN0 @ 3MHz // Khi to b chuyn i A/D // Thit lp cc chn ra

}while ((val & 0x80000000) == 0); val = ((val >> 6) & 0x03FF); if (val <0x80) { MAMCR = 0; MAMTIM = 0x03; MAMCR = 0x02; }else { MAMCR = 0x0; } for(delay = 0;delay<0x100000;delay++) //to vng lp {;} ChangeGPIOPinState(FLASHer); //i trng thi cc chn ra cng FLASHer = FLASHer <<1; if(FLASHer&0x01000000) { FLASHer = 0x00010000; //Lp li n u tin // overflow }}} void ChangeGPIOPinState(unsigned int state) { IOSET0 = state; //set output pins IOCLR0 = ~state; //clear output pins } 2.11.4. PLL- Phase Locked Loop - To ra mt tn s dao ng ngoi t 10-25MHz t mch dao ng c bn v c th tng ln 60 MHz cung cp cho CPU ARM v thit b ngoi vi. - Tn s u ra ca PLL c th thay i t ng, cho php thit b iu chnh theo tc thc thi duy tr ngun nng lng khi trng thi rnh ri. //Dch n n led tip

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Hnh 2.28 - Hai hng M v P phi c lp trnh quyt nh xung clock (Cclk) cho CPU v AHB. - Hng th nht c nhn mt cch tuyn tnh vi tn s dao ng bn ngoi a vo. Tn s ra ca PLL l: Cclk=M x Osc - Ngc li PLL li c iu khin bi mt dao ng hot ng hin hnh (CCO) di tn 156MHz-320MHz. Hng s th 2 phi c lp trnh m bo sao cho CCO c gi mt gi tr c th: Fcco = Cclk x 2 x P - Trn board pht trin th dao ng thch anh l 12MHz, bi vy CPU t c tc ti a 60MHz th: M = Cclk/Osc = 60/12 =5 v 156< Fcco <320 = 60 x 2 x P Thc nghim th P=2. - Giao din lp trnh PLL:

Hnh 2.29. - Gi tr trong cc thanh ghi PLLCON, PLLCFG v PLLSTAT s c ghi sau khi gi tr trong PLL FEED c ghi. Trang 30

- Khi cp nht gi tr thanh ghi PLLCON v PLLCFG th phi ghi lin tip hai gi tr 0x000000AA v 0x00000055 cho thanh ghi PLLFEED, cc gi tr ny phi ghi trong cc chu k lin tip. - Nu lp trnh cho php cc ngt th ngt s sinh ran gay sau khi t u tin c ghi v cc thit lp mi cho PLL s khng c nh hng. - ci t PLL phi ghi cc gi tr cho P v M ti thanh ghi PLLCFG, sau set D0 ca thanh ghi PLLCON cho php PLL khi ng. - Gi tr ca M chim 5 bt thp (D4-D0), P chim 2 bt D6D5:

Hnh 2.30. Gi tr ca P v M trong thanh ghi PLLCFG - PLL mt mt khong thi gian xc nh s dng ngun xung clock. S khi ng PLL c th c kim tra bng cch c bt LOCK (D10) trong thanh ghi trng thi PLLSTAT. - Khi LOCK bt =1, PLL c th c s dng nh ngun xung clock chnh. Mt ngt c th c sinh ra khi PLL kha, bi vy ngi lp trnh c th thc hin cc nhim v khc khi PLL khi ng. Khi PLL b kha th c th thay th ngun xung cho Cclk bng cch iu khin bt PLLC trong thanh ghi PLLCON.

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Hnh 2.31. Trnh t khi ng PLL 2.11.5. B chia bus (VLSI Peripheral Bus Divider) Mch dao ng ngoi hoc u ra ca PLL c s dng to ra ngun xung Cclk cho CPU ARM hoc h thng bus c tn s cao. Cc thit b ngoi vi c th s dng bus VPB ring bit.

Hnh 2.32. To xung Pclk t Cclk - B chia c th chia tc Cclk xung 2 n 24 ln. Thanh ghi trong b chia VPBDIV c th lp trnh c v cha s ln gim tc . Ti thi im khi ng, gi tr cc i c np v bng gi tr Cclk lc khi ng. - Hin nay tt c cc thit b ngoi vi ca h vi iu khin LPC c th chy tn s 60MHz. V vy, b chia tn VPB thng c s dng tit kim ngun bng cch to xung clock chp nhn c cho cc ng dng. Th du cu hnh PLL v VPB:

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Cu hnh PLL to ra tn s Cclk l 60MHz v Pclk l 30MHz vi xung u vo l 12MHz: void init_PLL(void) { PLLCFG = 0x00000024; // give 60.00 MHz PLLCON = 0x00000001; PLLFEED = 0x000000AA; PLLFEED = 0x00000055; while (!(PLLSTAT & 0x00000400)); // kim tra bt Lock PLLCON = 0x00000003; PLLFEED = 0x000000AA; PLLFEED = 0x00000055; VPBDIV = 0x00000002; } 2.12. Cc cng vo ra - Cc cng vo ra ca ARM l 32 bt, vi iu khin c th ch c 1 cng hoc c nhiu hn, nhng cc chn dng cho cng vo/ra cng l cc chn dng chung cho cc mc ch khc nh bin i AD, ngt, giao din SPI, I2C, - Cc chn c s dng vo mc ch no ty vo vic cu hnh chng cho mc ch . Trong chng 3 s trnh by c th v cch lp trnh cho cc chn cng vo ra. //Thit lp bus VLSI vi tn s 30.000MHz // Kt ni ti PLL //Cp nht cc thanh ghi PLL // Kch hot PLL // Cp nht thanh ghi PLLFEED // Thit lp h s nhn v b chia cho PLL

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CHNG 3: LP TRNH VI IU KHIN ARM 3.1. Hng dn s dng phn mm Keil C B1: To mt project mi:

B2: To th mc mi cha project mi to:

B3: t tn cho th mc l TD1 v click p ln th mc ny m ra v t tn cho project l TD1: Trang 34

B4: Chn vi iu khin vi core ARM7, th d LPC2101:

B5: Chn Yes t ng thm code start up vo project:

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B6: Chn New thm file mi son tho m ngun ca vi iu khin:

B7: Son tho m ngun v ghi vi tn MAM.C

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B8: Ghi li vi tn MAM.C

B9: Add file MAM.c vo project:

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B10: Chn file MAM.c:

B11: Cu hnh cho project:

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B12: Trong tab Target chn tn s l 12:

B13: Trong tab Output chn create hex File:

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B14: Bin dch project:

B15: Trn proteus v mch m phng:

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B16: Np file .hex cho vi iu khin:

B17: Chn file TD1.hex trong th mc ca project to t keil C:

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3.2. Truy nhp cc chn vo ra chung Cc chn vo (General purpose I/O input pins) ra c iu khin bi 4 thanh ghi:

Hnh 3.1. Cc chn vo ra c dng cho mc ch chung - Mi chn GPIO c iu khin bi 4 bt iu khin hng d liu, set, xa v trng thi ca chn. - Mi bt trong thanh ghi IODIR: 0 cho php cu hnh cc chn l u vo 1 cho php cu hnh cc chn l u ra

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- Khi cc chn l u ra th cc bt tng ng trn cc thanh ghi IOSET v IOCLR cho php ngi lp trnh iu khin trng thi ca cc bt. - xa chn no th a set bt =1 tng ng trong thanh ghi IOCLR - c ni dung ca chn s dng thanh ghi IOPIN Th d 1: Vit chng trnh iu khin led n sng nhp nhy Ghp ni mt led n vi chn P0.0 ca LPC2101, S ni chn Proteus:

Chng trnh iu khin: //Thi du chuong trinh dieu khien led nhap nhay tai chan p0.1 //LPC 2101 #include"LPC21xx.h" void delay(unsigned int a); int main(void){ IODIR0=0x00000001 ; while(1){

IOSET0=0x00000001 delay(0x100000);

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IOCLR0=0x00000001 ; delay(0x100000); } } void delay(unsigned int a){ unsigned int i; for (i=0;i<a;i++){;} } Th d 2: Chng trnh hin th ch trn LCD S trn proteus:

Chng trnh iu khin: T chc cc tp trong chng trnh nh sau:

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Tp lcd.h nh ngha a ch dnh cho lcd: /***************************************/ /* LCD routines for OLIMEX LPC-MT-2106 */ /* 16x2 Character LCD 1602K /* 4-bit mode operation */ */

/***************************************/ /* DEFINE IOMASK */ #define LCD_D4 0x10 //P0.04 #define LCD_D5 0x20 //P0.05 Trang 45

#define LCD_D6 0x40 //P0.06 #define LCD_D7 0x80 //P0.07 #define LCD_EN 0x400000 //P0.22 #define LCD_RS 0x800000 //P0.23 #define LCD_RW 0x1000000 //P0.24 #define LCD_DATA #define (LCD_D4|LCD_D5|LCD_D6|LCD_D7) LCD_IOALL

(LCD_D4|LCD_D5|LCD_D6|LCD_D7|LCD_EN|LCD_RS|LCD_RW) #define LCD_GPIO_SEL0 #define LCD_GPIO_SEL1 /* Functions Header */ /* internal I/O functions */ #define lcd_rs_set() IOSET |= LCD_RS #define lcd_rs_clr() IOCLR |= LCD_RS #define lcd_en_set() IOSET |= LCD_EN #define lcd_en_clr() IOCLR |= LCD_EN #define lcd_rw_set() IOSET |= LCD_RW #define lcd_rw_clr() IOCLR |= LCD_RW /* wait until lcd controller is free */ void lcd_wait(); void lcd_out_data4(unsigned char); void lcd_write_nibbles(unsigned char); void lcd_write_control(unsigned char); /* initialize both the GPIO of lpc and LCD */ void lcd_init(); #define lcd_clear() lcd_write_control(0x01) 0x0000FF00 //MASK for P0.04-P0.07 0x0003F000 //MASK for P0.22-P0.24

#define lcd_cursor_home() lcd_write_control(0x02) #define lcd_display_on() lcd_write_control(0x0E)

#define lcd_display_off() lcd_write_control(0x08) #define lcd_cursor_blink() lcd_write_control(0x0F) #define lcd_cursor_on() lcd_write_control(0x0E) Trang 46

#define lcd_cursor_off()

lcd_write_control(0x0C)

#define lcd_cursor_left() lcd_write_control(0x10) #define lcd_cursor_right() lcd_write_control(0x14) #define lcd_display_sleft() lcd_write_control(0x18) #define lcd_display_sright() lcd_write_control(0x1C) /* put a character out to lcd */ void lcd_putchar(unsigned char); /* print a string */ void lcd_print(unsigned char*); Tp lcd.c nh ngha cc phng thc lin quan n cc thao tc trn LCD: #include "lcd.h" #include "lpc210x.h" void lcd_wait(){ int loop=2800; //more than enough //busy loop while(loop--); } void lcd_out_data4(unsigned char val){ IOCLR |= (LCD_DATA); IOSET |= (val<<4); } void lcd_write_nibbles(unsigned char val){ //higher-order byte lcd_en_set(); lcd_out_data4((val>>4)&0x0F); lcd_en_clr(); lcd_wait(); //lower-order byte lcd_en_set(); lcd_out_data4((val)&0x0F); lcd_en_clr(); Trang 47

lcd_wait(); } void lcd_write_control(unsigned char val){ lcd_rs_clr(); lcd_write_nibbles(val); } void lcd_init(){ PINSEL0 &= (~LCD_GPIO_SEL0); PINSEL1 &= (~LCD_GPIO_SEL1); /* we only work on OUTPUT so far */ IODIR |= LCD_IOALL; /* IO init complete, init LCD */ /* init 4-bit ops*/ lcd_rs_clr(); lcd_rw_clr(); lcd_en_clr(); //wait VDD raise > 4.5V lcd_wait(); //dummy inst lcd_write_nibbles(0x30); lcd_write_nibbles(0x30); lcd_write_nibbles(0x30); //FUNCTION SET //001DL N F XX //DL=1: 8bit //DL=0: 4bit //N=0: 1 line display //N=1: 2 line display //F=0: 5x7 dots //F=1: 5x10 dots //our case: Trang 48

//0010 1000 lcd_en_set(); lcd_out_data4(0x2); lcd_en_clr(); lcd_wait(); lcd_write_nibbles(0x28); //LCD ON lcd_write_nibbles(0x0E); //Clear Display lcd_write_nibbles(0x01); //Entry mode lcd_write_nibbles(0x06); } void lcd_putchar(unsigned char c){ lcd_rs_set(); lcd_write_nibbles(c); } void lcd_print(unsigned char* str){ int i; //limit 1 line display for prints for (i=0;i<16 && str[i]!=0;i++){ lcd_putchar(str[i]); }} Tp test.c cha chng trnh chnh: #include "lpc210x.h" #include "lcd.h" int main(void) { lcd_init(); lcd_print("Trieu Dai Gia"); return 1; Trang 49

} 3.3. Lp trnh ngt Trong phn ny s trnh by 2 loi ngt ngoi: ngt sinh ra qua cc chn vo ra (IRQ) v ngt nhanh (FIQ). - Cu trc tng qut ca mt chng trnh con phc v ngt: void tn_ctcpvn (void) __Kiu_chng_trnh_phc_v_ngt { // cc lnh thn chng trnh con phc v ngt } - C 3 kiu chng trnh con phc v ngt: _IRQ, _SWI, _ABORT, - Chn EINT1 c kt ni ti mt cng tc trn board cho php by li nhanh mt ngt v quan st trn trnh debug. 3.3.1. Chn Connect Block - Tt c cc chn trn LPC2000 c kt ni ti mt s chc nng bn trong qua mt b a khi a thnh phn c gi l chn select block. Chn select block cho php mt user cu hnh mt chn qua GPIO hoc chn 3 chn khc.

Hnh 3.2. Chn I/O qua khi a thnh phn - Khi khi ng th tt c cc chn qua khi a thnh phn l chn GPIO, chc nng th 2 s c chn nh thanh ghi PINSEL. Chn ngt EINT1 va l chn I/O, va l chn GPIO 0.14 v l ng iu khin UART1. Do vy, s dng EINT1 phi cu hnh chn chn thanh ghi chuyn t GPIO sang EINT1.

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Cc thanh ghi PINSEL khi c khi ng ln c gi tr mc nh l 0 v cu hnh cc chn dnh cho mc ch v ra. Cc chn ca thanh ghi PINSEL cu hnh cho mc ch ngt: PINSEL0: (Th d cho LPC213x) STT 1 2 3 4 5 6 Chn 3:2 7:6 15:14 19:18 29:28 31:30 K hiu P0.1 P0.3 P0.7 P0.9 P0.14 P0.15 K hiu P0.16 P0.20 P0.30 Gi tr 11 11 11 11 10 10 Gi tr 11 11 11 Loi ngt EINT0 EINT1 EINT2 EINT3 EINT1 EINT2 Loi ngt EINT0 EINT3 EINT3

PINSEL1: (Th d cho LPC213x) STT 1 2 3 Chn 1:0 9:8 29:28

3.3.2. Cc chn ngt ngoi Cc ngt ngoi c iu khin bi 4 thanh ghi nh hnh di. Thanh ghi EXMODE chn ngt kch theo mc hoc theo sn. Nu mt ngt ngoi c cu hnh l kch theo sn th thanh ghi EXPOL c s dng theo di ngt hot ng tng ln hay gim xung. Trong trng hp kch theo mc, ngt ngoi c th ch mc logic 0. Nu ch tit kim ngun th thanh ghi EXWAKE c th cho php mt ngt nh thc CPU. ci t mt ngun ngt n gin chng trnh cn cu hnh chn EINT1 kch theo mc v kt ni ti CPU qua thanh ghi PINSEL0.

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Hnh 3.3. Chn ngt ngoi d dng c cu hnh to ngun ngt. 3.3.3. Cu trc ngt - ARM7 c 2 chn ngt ngoi cho yu cu ngt nhanh (FIQ) v yu cu ch ngt a mc ch. Tt c cc ngt u phi kt ni ti ngt IRQ. Trong mt h thng n gin c th kt ni qua cng OR. - VIC cho php iu khin ngt mt cch hiu qu:

Hnh 3.4 B iu khin ngt VIC cho php iu khin ngt hiu qu - Cc ngt pht sinh trong ng dng c a n VIC v c iu khin nh ngt FIQ hoc mt vecto ngt hoc khng c vecto ngt. Trang 52

Hnh 3.5. Cc thanh ghi iu khin ngt: VICIRQStatus: Trng thi cc ngt IRQ VICFIQStatus: Trng thi cc ngt FIQ VICIntSelect: Thanh ghi chn ngt FIQ hay IRQ vi cc chn t 14 n 17: Nu cc chn c gi tr 0 tng ng vi ngt IRQ c chn, bng 1 tng ng vi ngt FIQ c chn: STT 1 2 3 4 Bt 14 5 16 17 Loi ngt EINT0 EINT1 EINT2 EINT3 =0 loi ngt IRQ =1 loi ngt FIQ Gi tr

VICIntEnable: Thanh ghi cho php ngt. S dng cc bt t bt 14 n bt 17 cho php cc ngt t EINT0 n EINT3: STT 1 2 3 4 Bt 14 5 16 17 Loi ngt EINT0 EINT1 EINT2 EINT3 =0 khng cho php ngt =1 cho php ngt Gi tr

VICIntEnClr: Xa cc ngt s dng cc bt t 14 n 17 tng ng vi cc ngt t EINT0 n EINT3: STT 1 2 Bt 14 5 Loi ngt EINT0 EINT1 Trang 53 =1 cho php xa ngt Gi tr

3 4

16 17

EINT2 EINT3

VICProtection: Thanh ghi bo v ngt, s dng bt 0: Bt ngha =0: VIC cho php truy cp cc thanh ghi ch phn quyn hoc ngi 0 dng. =1: VIC ch cho php truy cp cc thanh ghi ch phn quyn. VICVectAddr : Cha c ch chng trnh con phc v ngt khi xy ra ngt. VICDefVectAddr: Cha a ch chng trnh con phc v ngt i vi loi ngt khng vecto. VICVectAddr0 n VICVectAddr16: Cha a ch chng trnh con phc v ngt tng ng vi cc slot t 0 n 15. VICVectCntl0 n VICVectCntl15: Cho php ngt: Bt 5 4:0 Ngun ngt Ngun ngt v quy nh knh ngt trn LPC213x: Ngun ngt C ngt Knh phc v qua VIC WDT ARM Core ARM Core TIMER0 Watchdog Interrupt (WDINT) Ch dng cho ngt mm Embedded ICE, DbgCommRx Embedded ICE, DbgCommRx Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) TIMER1 Match 0 - 3 (MR0, MR1, MR2, MR3) 5 0 1 2 3 4 ngha = 1 cho php ngt ti slot tng ng Cha s lng ngt ti slot

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Capture 0 - 3 (CR0, CR1, CR2, CR3) UART0 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) UART1 PWM0 Rx Line Status (RLS) Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) I2C0 SPI0 SI (state change SPI Interrupt Flag (SPIF) Mode Fault (MODF) SPI1(SSP) TX FIFO at le ast half empty (TXRIS) Rx FIFO at least half full (RXRIS) Receive Timeout condition (RTRIS) Receive overrun (RORRIS) PLL RTC PLL Lock (PLOCK) Counter Increment (RTCCIF) Alarm (RTCALF) System Control External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2) External Interrupt 3 (EINT3) ADC0 A/D I2C1 BOD ADC1 A/D Converter 0 end of conversion SI (state change) Brown Out detect Converter 1 end of conversion 14 15 16 17 18 19 20 21 12 13 11 9 10 8 7 6

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3.3.4. Ngt FIQ - Nu c nhiu ngt FIQ th tng ng vi cc bt trong trong thanh ghi ISR th thanh ghi trnh thi VIC FIQ s chn chng trnh cn phc v ngt ph hp thc thi. - Khi mt ngt FIQ sinh ra, CPU s chuyn sang ch FIQ v PC nhy ti a ch 0x0000001C v nhy ti a ch chng trnh con pvn. 3.3.5. Kt thc ngt - Trc khi kt thc chng trnh con phc vu ngt phi m xa c ngt pha thit b khng ngt li tip tc sinh ra. Th d ngt FIQ: void main (void) { IODIR1 = 0x00FF0000; //Thiet lap chan LED la chan ra PINSEL0 = 0x20000000; //Chon chuc nang EINT1 tai chan connect block VICIntSelect = 0x00008000; //Cho phep mot kenh qua VIC la FIQ VICIntEnable = 0x00008000; //Cho php ngat tu EINT1 vo VIC IOCLR1 = 0x00FF0000; while(1); //Lap mai mai } void fiqint (void) __fiq //chuong trinh pvn { IOSET1 = 0x00FF0000; //thiet lap chan led EXTINT = 0x00000002; //xoa co ngat tu phia thiet bi ngoai } 3.3.6. Vecto IRQ - Nu c mt ngun ngt l FIQ th tt c cc ngun con li phi c kt ni ti ng IRQ. qu trnh x l ngt hiu qu, VIC cung cp mt bng tm kim phn pht a ch ca cc hm C cho tng ngun ngt. - VIC cha ng 16 khe cho a ch. Mi khe cha ng mt a ch vecto v mt thanh ghi iu khin vecto. // Xoa LED

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Hnh 3.6 - Thanh ghi iu khin ngt cha ng 2 trng: mt trng knh v mt bt cho php. Bng cch lp trnh trng knh, bt k mt knh ngt no cng c th c kt ni n mt khe (slot) c a ra v kch hot bt cho php ngt. Th t u tin ca mt vecto ngt c a ra bi s slot,slot cng thp th ngt cng c u tin.

Hnh 3.7 - Mt thanh ghi khc trong VIC slot l thanh ghi a ch vecto (Vector Address Register). Thanh ghi ny cha a ch ca mt chng trnh con phc v ngt. 3.3.7. Kt thc mt ngt IRQ - Khi kt thc mt ngt th gi mt tn hiu n thanh ghi a ch vecto: void main (void) Trang 57

{ IODIR1 = 0x000FF000; //thiet lap chan ra PINSEL0 = 0x20000000; //cho phep ngat ngoai EXTINT1 VICVectCntl0 = 0x0000002F; //chon 1 khe uu tien cho ngat VICVectAddr0 = (unsigned)EXTINTVectoredIRQ; //lay dia chi chuong //trinh phuc vu ngat VICIntEnable = 0x00008000; //cho phep ngat while(1); } void EXTINTVectoredIRQ (void) __irq { IOSET1 = 0x000FF000; //bat led EXTINT = 0x00000002; //xoa co ngat ngoai VICVectAddr = 0x00000000; //gui 1 tin hieu ket thuc ngat } 3.3.8. Ngt khng c a ch VIC c th iu khin c 16 ngt, nu c nhiu hn 16 ngt th phi m rng ngt. Cc ngt ny c ph bi mt ISR. a ch ca ISR c lu trong trong mt thanh ghi a ch ngt mc nh. Nu mt ngt c cho php bi VIC m khng c cu hnh l FIQ hoc IRQ th s c xp vo ngt khng c a ch. Khi ngt ny xy ra th mt a ch s c ti vo trong thanh ghi a ch ngt. V CPU phi c thanh ghi trng thi IRQ xem nguyn nhn ngt.

Hnh 3.8. Mt a ch mc nh c ti vo thanh ghi a ch ngt Trang 58

3.3.9. Kt thc ngt khng a ch - Khi kt thc ngt phi xa c trng thi v vit thanh ghi a ch ngt. Th d ngt khng a ch: void main (void) { IODIR1 = 0x000FF000; PINSEL0 = 0x20000000; //cau hinh cac chan ra //cho phap ngat ngoai EXTINT0

VICDefVectAddr = (unsigned)NonVectoredIRQ; //dua dia chi ngat IRQ //vao VIC slot VICIntEnable = 0x8000; while(1); } void NonVectoredIRQ (void) __irq { if(VICIRQStatus&0x00008000) //kiem tra nguon sinh ngat { IOSET1 = 0x00FF0000; //bat led EXTINT = 0x00000002; update++; } VICVectAddr = 0x00000000; //gui tin hieu ket thuc ngat } 3.4. Lp trnh Timer 3.4.1. Cc Timer - H vi iu khin ARM c s lng cc Timer dng cho mc ch chung l khc nhau, ty vo tng loi, nhng t nht l c 2 Timer. - Mi Timer 32 bt v mt mch m 32 bt. - Ngun xung clock cho tt c cc Timer l mt mch to xung c ln VLSI. //xoa co ngat //cho phep ngat ngoai EXTINT0 trong VIC

Trang 59

Hnh 3.9. Cu trc Timer 32 bt ca ARM Thangh ghi PINSEL0 cu hnh cho cc chn ca TIMER: STT 1 2 3 4 5 6 7 8 9 Chn 5:4 9:8 13:12 21:20 23:22 7:6 11:10 25:24 27:26 K hiu P0.2 P0.4 P0.6 P0.10 P0.11 P0.3 P0.5 P0.12 P0.13 Gi tr 10 10 10 10 10 10 10 10 10 Chn chn Capture 0.0 (Timer 0) Capture 0.1 (Timer 0) Capture 0.2 (Timer 0) Capture 1.0 (Timer 1) Capture 1.1 (Timer 1) Match 0.0 (Timer 0) Match 0.1 (Timer 0) Match 1.0 (Timer 1) Match 1.1 (Timer 1)

Thanh ghi VICIntEnable cho php ngt ca TIMER: - Bt D5: cho php ngt ca Timer 1 - Bt D4: cho php ngt ca Timer 0 Gi tr cc bt ny c th c hoc ghi c. Thanh ghi VICIntSelect cho php chn loi ngt ca TIMER: - Bt D5: cho php chn loi ngt ca Timer 1 - Bt D4: cho php chn loi ngt ca Timer 0

Trang 60

Gi tr cc bt ny c th c hoc ghi c, nu bng 0-l loi ngt IRQ, 1-loi ngt FIQ. Cc thanh ghi ca Timer: Thanh ghi ngt: TxIR (T0IR, T1IR) Bt K hiu ngha C ngt cho knh so khp 0 C ngt cho knh so khp 1 C ngt cho knh so khp 2 C ngt cho knh so khp 3 C ngt cho s khin chp trn knh so khp 0 C ngt cho s khin chp trn knh so khp 1 C ngt cho s khin chp trn knh so khp 2 C ngt cho s khin chp trn knh so khp 3 Gi tr khi khi ng 0 1 2 3 4 5 6 7 MR0 MR1 MR2 MR3 CR0 CR1 CR2 CR3 0 0 0 0 0 0 0 0

Thanh ghi iu khin Timer TCR: TIMER0: T0TCR, TIMER1: T1TCR: Bt 0 1 7:2 ngha =1: Cho php m =1: Reset b m Khng dng

Thanh ghi iu khin m - CTCR: TIMER0: T0CTCR v TIMER1:T1CTCR: Thanh ghi ny cho php chn gia ch nh thi v ch m: Bt 1:0 Mc ch Cho php chn ch m hoc nh thi ngha cc bt 00: Chn ch nh thi 01-Ch m: TC tng trn chn chp c chn bi bt 3:2 c tng theo sn 10-Ch m: TC tng trn chn chp c chn bi bt 3:2 c gim theo sn 11-Ch m: TC tng trn chn chp c chn bi bt 3:2 theo c sn tng v sn gim Trang 61

3:2

Cho php chn u vo m

00-Chn knh CAPn.0 (CAP0.0 cho TIMER0 v CAP1.0 cho TIMER1) 00-Chn knh CAPn.1 (CAP0.1 cho TIMER0 v CAP1.1 cho TIMER1) 00-Chn knh CAPn.2 (CAP0.2 cho TIMER0 v CAP1.2 cho TIMER1) 00-Chn knh CAPn.3 (CAP0.3 cho TIMER0 v CAP1.3 cho TIMER1)

7:4

Khng dng Thanh ghi m TC: T0TC v T1TC: Cha gi tr m, gi tr trong TC s tng ln khi b m Prescale Counter t ti gi tr ti hn. Khi t n gi tr 0xFFFFFFFF th TC li quay v 0. Thanh ghi Prescale Register PR: TIME R0: T0PR v TIMER1: T1PR: L thanh ghi 32 bt, cha gi tr cc i cho Prescale Counter. Thanh ghi Prescale Counter Register PC: TIMER0: T0PC v TIMER1: T1PC: L thanh ghi 32 bt, gi tr ca PC s tng ln theo mi xung nhp, khi PC t ti gi tr lu trong thanh ghi PR v tr v 0 th TC s tng ln 1. Thanh ghi so khp MR0 n MR3: Gi tr lin tip c so snh vi gi tr ca TC trn cc knh tng ng. Thanh ghi iu khin so khp - MCR, TIMER0: T0MCR v TIMER1: T1MCR:

iu khin hnh ng xy ra khi c s kin chp trn cc knh tng ng: Bt 0 1 2 3 4 5 K hiu MR0I MR0R MR0S MR1I MR1R MR1S ngha Cho php sinh ra ngt khi TC=MR0 Reset TC khi TC=MR0 Dng TC v PC khi TC=MR0 Cho php sinh ra ngt khi TC=MR1 Reset TC khi TC=MR1 Dng TC v PC khi TC=MR1 Trang 62

6 7 8 9 10 11

MR2I MR2R MR2S MR3I MR3R MR3S

Cho php sinh ra ngt khi TC=MR2 Reset TC khi TC=MR2 Dng TC v PC khi TC=MR2 Cho php sinh ra ngt khi TC=MR3 Reset TC khi TC=MR3 Dng TC v PC khi TC=MR3 Khng dng

15:12 ng.

Cc thanh ghi chp - CR0-CR3: Cha gi tr chp c trn cc knh tng Thanh ghi iu khin chp CCR: TIMER0: T0CCR v TIMER1: T1CCR: Bt 0 1 2 3 4 5 6 7 8 9 10 11 K hiu CAP0RE CAP0FE CAP0I CAP1RE CAP1FE CAP1I CAP2RE CAP2FE CAP2I CAP3RE CAP3FE CAP3I ngha Chp khi c tn hiu tng t 0 ln 1 ti knh CAPn.0 Chp khi c tn hiu gim t 1 ln 0 ti knh CAPn.0 Cho php sinh ra ngt xy ra ti knh CAPn.0 Chp khi c tn hiu tng t 0 ln 1 ti knh CAPn.1 Chp khi c tn hiu gim t 1 ln 0 ti knh CAPn.1 Cho php sinh ra ngt xy ra ti knh CAPn.1 Chp khi c tn hiu tng t 0 ln 1 ti knh CAPn.2 Chp khi c tn hiu gim t 1 ln 0 ti knh CAPn.2 Cho php sinh ra ngt xy ra ti knh CAPn.2 Chp khi c tn hiu tng t 0 ln 1 ti knh CAPn.3 Chp khi c tn hiu gim t 1 ln 0 ti knh CAPn.3 Cho php sinh ra ngt ngt xy ra ti knh CAPn.3 Khng dng

15:12 -

Thanh ghi so khp ngoi External Match Register EMR: TIMER0: T0EMR v TIMER1: T1EMR: Cung cp c tn hiu iu khin v trng thi ca cc chn so khp ngoi, o trng thi ca cc chn MAT. Hot ng ca timer: -Tc ca Timer c iu khin bi gi tr lu tr trong thanh ghi prescaler Reg (TxPR). Trang 63

- B m s tng ln cho n khi t ti gi tr lu tr trong thanh ghi thanh ghi m. - Khi t ti gi tr ti a, b m s c reset li v tr li gi tr 0. - Thanh ghi iu khin m TxTCR ch c 2 bt (D1D0), mt bt iu khin cho php m(D0), mt bt reset b m(D1). - Mi b m c 4 knh cho php chp li gi tr ca b m ti thi im khi c tn hiu u vo tc ng to ra s dch chuyn gi tr.

Hnh 3.10. - Thanh ghi iu khin chp (TxCCR) c th c cu hnh iu khin chp, khi gi tr b m tng ln hoc gim. - Khi xy ra s kin chp, gi tr ca b m c chuyn vo thanh ghi chp (TxCRx )v c th sinh ra mt ngt nu cn thit. Th d sau cu hnh Timer 0 cho php chp ti 2, khi c s kin chp th s sinh ra mt ngt. int main(void) { VPBDIV = 0x00000002; //thiet lap pclk co tan so 30 MHz PINSEL0 T0PR T0TCR T0CCR T0TCR = 0x00000020; //cho phep chn P0.2 de chup tai kenh 0

= 0x00007530; //Toc do cua timer l 1 Msec = 0x00000002; //reset bo dem va prescaler = 0x00000005; //Chup theo suon tng 0->1 v sinh ra ngt. = 0x00000001; //cho phep timer

VICVectAddr4 = (unsigned)T0isr; //Thiet lap dia chi vecto ngat cho ISR cua time VICVectCntl4 = 0x00000024; //Thiet lap kenh Trang 64

VICIntEnable = 0x00000010; while(1); } void T0isr (void) __irq { static int value; value T0IR = T0CR0;

//Cho phep ngat

// c gi tr chp c ti kenh 0

|= 0x00000001; // xoa ngat = 0x00000000; //Gia ghi mot tin hieu ket thuc ngat

VICVectAddr }

- Mi knh ca Timer co mt thanh ghi so khp 32 bt, gi tr chp c s c so snh vi gi tr trong thanh ghi so khp, khi hai gi tr trng nhau th Timer s thc hin mt trong cc hnh ng nh: khi ng li, dng hoc sinh ra ngt v tc ng n chn ngt ngoi c th set =1 hoc xa bng 0 hoc l lng.

Hnh 3.11. - cu hnh Timer c s kin so khp v np gi tr ca thanh ghi so khp mong mun. S kin so khp c th c th c iu khin bi thanh ghi iu khin so khp. Trong thanh ghi nay mi knh c iu khin bi mt nhm bt cho php cc s kin so khp xy ra: sinh ra ngt, khi ng timer v dng timer. - Mi knh so khp c kt hp vi mt chn so khp c th thay i c khi c mt s kin xy ra. Cc chn so khp c th c iu khin bi 4 bt u trong thanh ghi so khp ngoi.

Trang 65

Hnh 3.12. Thanh ghi so khp ngoi - Thanh ghi so khp ngoi cha ng cc trng cu hnh cho mi knh. Lp trnh cc trng ny quyt nh hnh ng s xy ra khi c s kin so khp. Mi chn so khp ng vi mt bt c th lp trnh trc tip thay i mc logic. - Th d sau m phng cch to mt xung n gin s dng 2 knh so khp. Knh 0 c s dng sinh ra chu k tn hiu PWM. Khi s kin so khp xy ra, timer khi ng li v sinh ra mt ngt. Ngt c s dng thit lp chn Match 1 ln mc cao. Knh 1 c s dng iu khin hon thnh chu k. Khi s kin match 1 xy ra, chn Match 1 c xoa v 0. Bi vy, s thay i gi tr trong thanh ghi Match 1 to ra tn hiu PWM. Th d: int main(void) { VPBDIV = 0x00000002; // Cu hnh b chia tn VPB PINSEL0 |= 0x00000800; // Match1 l u ra T0PR = 0x0000001E; //Ti presaler T0TCR = 0x00000002; //Reset counter v presale T0MCR = 0x00000003; //Khi so khp th khi ng li v sinh ra ngt T0MR0 = 0x00000010; //Thit lp chu k timer T0MR1 = 0x00000008; // Thit lp 50% chu k T0EMR = 0x00000042; //Thit lp chp MAT1 ln 1 trong chu k u Trang 66

T0TCR = 0x00000001; //cho php timer VICVectAddr4 = (unsigned)T0isr; //Thit lp a ch ISR ca timer VICVectCntl4 = 0x00000024; //Thit lp knh VICIntEnable |= 0x00000010; //Cho php ngt while(1); } void T0isr (void) __irq { T0EMR |= 0x00000002;// Thit lp MAT1 ln mc cao bt u chu k T0IR |= 0x00000001; // Xa ngt ti match 0 VICVectAddr = 0x00000000; // Gi tin hiu kt thc ngt } 3.4.2. ng h thi gian thc (Real Time Clock - RTC) - ng h thi gian thc LPCxxx l mt lch biu chnh xc n nm 2099 v khng hot ng vi tn s Pclk. RTC tiu th mt nng lng thp. RTC c mt tp cc thanh ghi cnh bo c s dng lu tr ngy thng hoc gi tr c th trong thanh ghi m thi gian (time-count register).

Hinh 3.13. - RTC hot ng xung nhp chun vi tn s 32.7 KHz. c c s ny th Pclk cn c kt ni ti b chia tn tham chiu. Trang 67

Hnh 3.14. To xung clock cho RTC - m bo xung clock c to ra chnh xc t Pclk, prescaler c lp trnh bi 2 thanh ghi PREINT v PREFRAC. Tnh ton gi tr cho mi thanh ghi nh sau: PREINT = (int)(pclk/32768)-1 PREFRAC = pclk ((PREINT+1) x 32768 Vi mt xung Pclk 30MHz th: PREINT = (int)( 30,000,000/32768)-1 = 914 PREFRAC = 30,000,000 ((914+1) x 32768) = 17280 Cc gi tr c th c lp trnh trc tip vo thanh ghi prescaler ca RTC, sau cho php xung clock trong thanh ghi iu khin clock v cc b m timer s bt u, PREINT = 0x00000392; //Thit lp prescaler RTC vi tn s Pclk //l 30.000 MHz PREFRAC = 0x00004380; CCR = 0x00000001; //Bt u RTC C 8 thanh ghi m thi gian (time-counter), mi thanh ghi cha mt con s thi gian n c th c c bt k lc no. Ngoi ra, c mt tp cc thanh ghi tng hp biu din cng gi tr thi gian trong 3 t cho php tt c cc thng tin c c trong 3 thao tc.

Trang 68

Hnh 3.15. Cc thanh ghi tng hp ca RTC - RTC c th sinh ra mt s kin ngt. C 2 b to ngt, Ngi lp trnh c th to ra ngt khi gi tr ca thanh ghi time-counter c tng ln, hoc khi b giy c cp nht hoc khi nm c tng ln. Thanh ghi ngt cho chp 8 ngt c th. - Cch th 2 c th sinh ra ngt RTC cc thanh ghi cnh bo. Mi thanh ghi timecounter c mt thanh ghi cnh bo (Alarm register), v c th cnh bo trong khong thi gian hin ti n nm 2099 mt cch chnh xc. - Thanh ghi Alarm Mask iu khin s so snh. Thanh ghi ngt location c 2 bt c s dng cho bit nguyn nhn sinh ra ngt. Th d minh ha: int main(void) { VPBDIV = 0x00000002; IODIR1 = 0x00FF0000; // Thit lp cc chn u ra ni vi led IOSET1 = 0x00020000; PREINT = 0x00000392; //Thit lp RTC prescaler vi Pclk 30MHz PREFRAC = 0x00004380; CIIR = 0x00000001; //Cho php ngt khi n s giy //Cho php cnh bo theo s giy Alarm //Khi ng RTC //Thit lp knh ALSEC = 0x00000003; //Thit lp thanh ghi cnh bo 3 AMR = 0x000000FE; CCR = 0x00000001;

VICVectAddr13 = (unsigned)RTC_isr; //Ly a ch chng trnh phc v ngt VICVectCntl13 = 0x0000002D; VICIntEnable = 0x00002000; //Cho php ngt Trang 69

while(1); } void RTC_isr(void){ unsigned led; if(ILR&0x00000001) { led = IOPIN1; //c trng thi ca cc chn vo ra IO IOCLR1 = led&0x00030000; //tt LED IOSET1 = ~led&0x00030000; // bt LED ILR = 0x00000001; } if(ILR & 0x00000002) { IOSET1 = 0x00100000; //set led 0.7 ILR = 0x00000002; } VICVectAddr = 0x00000000; /*Gi lp kt thc ngt */ } 3.5. Lp trnh qua UART - LPCxxx c 2 chp UARTs. UART1 c nhng tnh nng hin i. Cc thit b kt ni ph hp vi chun cng nghip 550. 16 bytes truyn v nhn theo kiu FIFOs. //xa thanh ghi ngt //xa ngt //Kim tra ngt RTC

Hnh 3.16. S chn UART Trang 70

Thanh ghi PINSEL0 cu hnh cho UART: STT 1 2 3 4 5 6 7 8 9 Chn 1:0 3:2 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 Cc thanh ghi ca UART: - Thanh ghi Receiver Buffer Register UxRBR: l thanh ghi m nhn d liu 8 bt. Khi bt DLAB (Divisor Latch Access Bit) trong thanh ghi UxLCR th cho php c gi tr thanh ghi ny. Thanh ghi ny ch cho php c, khng c php ghi. - Thanh ghi Transmit Holding Register UxTHR: L thanh ghi m truyn 8 bt d liu. Khi bt DLAB = 0 cho php ghi k t ln thanh ghi ny m khng cho php c d liu t thanh ghi. - Thanh ghi cht phn chia Divisor Latch Registers UxDLL: Cha tc truyn d liu, gm 2 thanh ghi 8 bt l DLL v DLM. Cc thanh ghi ny c truy cp khi bt DLAB=1. - Thanh ghi Fractional Divider Register UxFDR: L thanh ghi 31 bt dng iu khin tc truyn d liu theo xung nhp h thng v c th c ghi theo ca ngi dng. Cc bt 3:0 cha gi tr DIVADDVAL, cc bt 7:4 cha gi tr MULVAL, vi 0 <= DIVADDVAL<=15 v 0< MULVAL <=15. Khi tc truyn c tnh theo cng thc sau: K hiu P0.0 P0.1 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 Gi tr 01 01 01 01 01 01 01 01 01 01 Chn chn TxD ca UART0 RxD ca UART0 TxD ca UART1 RxD ca UART1 C th RTS ca UART1 C th CTS ca UART1 C th DST ca UART1 C th DTR ca UART1 C th DCDca UART1 C th RI ca UART1

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Thanh ghi ny chir c s dng trong mt s phin bn ca LPC t 213x tr ln. Tnh ton tc ca UART: Th d 1: Tnh ton tc ca UART0 theo PCLK ca h thng. Khi PCLK = 20 MHz, U0DL = 130 (U0DLM = 0x00 and U0DLL = 0x82), DIVADDVAL = 0 v MULVAL = 1 s cho php UART0 t ti tc 9615 bauds. Example 2: Tnh ton tc ca UART0 theo PCLK ca h thng. Khi PCLK = 20 MHz, U0DL = 93 (U0DLM = 0x00 and U0DLL = 0x5D), DIVADDVAL = 2 v MULVAL = 5 s cho tc UART0 l 9600 bauds. - Thanh ghi cho php ngt Interrupt Enable Regi ster UxIER: Hot ng khi DLAB=0. Bt 0 1 2 ngha =1 cho php sinh ra ngt khi nhn d liu =1 cho php sinh ra ngt khi truyn d liu =1 Cho php ngt khi thay i trng thi chn Rx

- Thanh ghi iu khin hng i FIFO Control Register - UxFCR: - Thanh ghi iu khin ng truyn: Line Control Register - U0LCR: L thanh ghi 8 bt vi chc nng c th ca cc bt nh sau: Bt 1:0 Gi tr v ngha Cha s bt d liu 00- 5 bt 01-6 bt 10-7 bt 11-8 bt 2 Bt stop 0- 1 bt 1-2 bt (1.5 bt nu bt 1:0=00) 3 0-Khng kim tra chn/l 1-Cho php kim tra chn/l 5:4 00-Kim tra l 01-Kim tra chn

Trang 72

10-bt buc kt qu bng 0 11-bt buc kt qu bng 1 6 Cho php ngt khi truyn 0-khng cho php 1- chn TxD=0 khi UxLCR[6]=1 7 DLAB-bt cht 0-Khng cho php truy cp thanh ghi tc c DLL v DLM 1-Cho php truy cp thanh ghi DLL v DLM Thanh ghi trng thi ng truyn Line Status Register UxLSR: L thanh ghi ch coj cung cp trng thi ca qu trnh nhn v gi d liu. Bt 0 K hiu RBR Gi tr, ngha 0-UxRBR rng 1- UxRBR c d liu 1 OE 0-Khng kch hot li trn FIFO nhn 1-Kch hot li trn FIFO nhn 2 PE 0-Khng kch hot li kim tra chn l 1-Kch hot li kim tra chn l 3 FE 0-khng kch hot li bt stop=0 1- kch hot li bt stop=0 4 BI 0-khng kch hot ngt break 1-kch hot ngt break 5 THRE 0-m truyn UxTHR c d liu 1-m truyn UxTHR rng 6 TEMT 0-m truyn UxTHR hoc UxTSR c d liu 1-m truyn UxTHR hoc UxTSR rng 7 RxFE 0-UxRBR khng c li 1- UxRBR c t nht mt li Ci t UART0 nh sau: void init_serial (void) /* khi to giao dien cong uart Trang 73 */

{ PINSEL0 = 0x00050000; U1LCR = 0x00000083; U1DLL = 0x000000C2; U1LCR = 0x00000003; } - Chn chn khi phi c lp trnh vi x l chuyn t chc nng GPIO sang UART. Thanh ghi iu khin ng truyn ( line control register ) UART c s dng nh dng khung truyn d liu. /* cho phep RxD1 va TxD1*/ /* 8 bt d liu, khng bt Parity, 1 Stop bit */ /* tc 9600, xung nhp clock 30MHz VPB */ /* DLAB = 0*/

Hnh 3.17. Thanh ghi iu khin ng truyn LCR ca UART - Tn s hot ng ca UART c chia t Pclk, gp 16 ln tc truyn d liu v tnh theo cng thc: Divisor = Pclk/16 x BAUD - Gi s Pclk=30MHz: Divisor = 30,000,000/16 x 9600 = (approx) 194 or 0xC2 Khng th ly tc chnh xc ca UART, tuy nhin cc cng ny c th hot ng vi sai s tc 5%. Nu mun iu chnh Pclk nhn c tc chnh xc th phi s dng n CAN. - Gi tr Divisor c t chc thnh 2 thanh ghi Divisor latch MSB (DLM) v Divisor latch LSB (DLL). 8 bt u tin ca c 2 thanh ghi cha na gi tr chia nh hnh di, cui cng, bt DLAB c set =0 bo v ni dung ca thanh ghi chia tc :

Trang 74

Hnh 3.18. Thit lp tc ca UART - Khi UART c khi to, cc k t c th c truyn bng cch ghi ti thanh ghi Transmit Holding Register. Cc k t nhn c c th c c t thanh ghi m nhn (receive buffer register). Thc cht c hai thanh ghi ny l 1, v vic c ghi theo c ch FIFO. Hai chng trnh con di y m t vic gi v nh k t.\ int putchar (int ch) { if (ch == '\n') { while (!(U1LSR & 0x20)); U1THR = CR; } while (!(U1LSR & 0x20)); return (U1THR = ch); } int getchar (void) { while (!(U1LSR & 0x01)); return (U1RBR); Trang 75 /* c t cng Serial */ /* output CR */ /* Ghi mt k t ti cng Serial */

} Trong th vin STDIO ca Keil C c th s dng hm printf() v scanf(). C hai hm putchar() v getchar() u c thanh ghi lin kt trng thi (LSR) kim tra li v trng thi truyn v nhn.

Hnh 3.19. Thanh ghi lin kt trng thi cho php kim tra li UART c 1 ngt ti VIC, nhng c 3 ngun ngt. Cc ngt c sinh ra khi thay i trng thi ng nhn (receive line status). Nu c mt li pht sinh th mt ngt s c sinh ra v thanh ghi lin kt trng thi s c c tm nguyn nhn li, Hai loi ngt cn li sinh ra do nhn v truyn d liu. Ngt sinh ra s c theo di bi cc k t nhn c trong chn RX FIFO. Cc ngt c theo di trong thanh ghi iu khin UART FIFO.

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Hnh 3.20. Bng theo di cc ngt Khi truyn sinh ra ngt khi thanh ghi m truyn v thanh ghi dch truyn l rng:

Hnh 3.21. Ngt to ra khi truyn UART1 c cu trc ging UART0 nhng c h tr thm modem iu khin. C thm cc chn m rng h tr giao din modem: CTS, DCD, DSR, DTR, RI, RTS, c thm 2 thanh ghi: iu khin modem v trng thi modem; v mt ngun ngt cung cp thm trng thi ngt ca modem.

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Hnh 3.22. Cu trc chn m rng ca UART1 3.6. Giao din I2C - I2C c th hot ng ch ch hoc khch vi tc 400K bit/s v ch ch s t ng c phn x trong h thng c nhiu thit b ch.

Hnh 3.23. Bus I2C Hai ng Serial Clock (SCL) v Data line (SDA) phi c chuyn i t chn GPIO sang I2C qua b kt ni.

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Hnh 3.24. Cc thanh ghi ca I2C Giao din I2C c iu khin bi 7 thanh ghi. Thanh ghi iu khin c 2 thanh ghi ring bit c s dng set v clear thanh ghi iu khin (I2CONSET v I2CONCLR). Tc bt c quyt nh bi hai thanh ghi (I2SCLH v I2CLL); thanh ghi trng thi tr li m iu khin c lin quan ti cc s kin trn bus. Thanh ghi ghi m pht v m truyn, khi LPC c cu hnh l thit b slave th a ch mng c lu trong thanh ghi I2ADR. Cc lnh khi to giao din I2C: VICVectCntl1 = 0x00000029; //Chn u tin cho ngt VICVectAddr1 = (unsigned)I2CISR //a a ch ngt v vecto ngt VIC VICIntEnable = 0x00000200; //cho php ngt PINSEL0 = 0x50; I2SCLH I2SCLL //chuyn chn GPIO sang chn I2C = 0x08; //Tc bt to 57.6KHz = 0x08

- Tc bt c lu trong 2 thanh ghi I2SCLH v I2CSLL: Bit Rate = Pclk/(I2SCLH+I2CSLL - Gi s trong v d trn PLL khng c s dng v xung nhp bn ngoi l 14.1456MHz th tc bt l: Bit Rate = 14.7456/B ( 8 + 8) = 937500 - Cu hnh thanh ghi iu khin bus I2C c hoc ghi d liu nh l bus ch hoc nhn hoc tr li t bus ch nh sau:

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Hnh 3.25. Cu hnh thanh ghi iu khin I2C Chng trnh truyn d liu I2C ch master nh sau: void I2CTransferByte(unsigned Addr,unsigned Data) { I2CAddress = Addr; //Place address and data in Globals to be used by //the interrupt I2CData = Data; I2CONCLR = 0x000000FF; //Clear all I2C settings I2CONSET = 0x00000040; //Enable the I2C interface I2CONSET = 0x00000020; //Start condition }

Hnh 3.26. Thanh ghi trng thi ca I2C: Chng trnh gi mt k t qua I2C: void I2CISR (void) { switch (I2STAT) //Read result code and switch to next action{ case ( 0x08): //Start bit Trang 80 //I2C interrupt routine

I2CONCLR = 0x20; //Clear start bit I2DAT = I2CAddress; //Send address and //write bit break; case (0x18): //Slave address+W, ACK //Write data to tx register

I2DAT = I2Cdata; break; case (0x20):

//Slave address +W, Not ACK

I2DAT = I2CAddress; //Resend address and write bit break; case (0x28): //Data sent, Ack

I2CONSET = 0x10; //Stop condition break; default : break; } I2CONCLR = 0x08; //Clear I2C interrupt flag VICVectAddr = 0x00000000; //Clear interrupt in } 3.7. Giao din SPI Cng ging nh I2C, SPI cng l mt giao din bus cho php truyn v nhn d liu vi thit b bn ngoi nhng cha thng minh qun l bus:

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Hnh 3.27. Giao din SPI Giao din SPI c 4 chn: mt chn clock, mt chn chn slave v hai chn d liu master in/slave out v master out/slave in. Chn clock cung cp mt xung 400kbits/s khi ch master, hoc nhn ngun xung t bn ngoi khi ch slave. Bus SPI hon ton ch truyn d liu ni tip vi tc cao v khng ging nh giao din I2C, n khng c s a ch c xy dng khi truyn ni tip. Mt thit b ngoi vi ngoi c chn qua chn slave. Thng thng LPC2000 c kch hot ch ch v s dng cc chn vo ra chung chn thit b SPI mong mun. Khi SPI ch slave, chn slave ca n c y v mc 0 cho php SPI ch truyn thng vi n. Hai chn d liu c kt ni vi thit b SPI t xa v chiu truyn ph thuc vo thit b hot ng ch ch hay khch (master hay slave). Lp trnh qua giao din SPI c 5 thanh ghi: - Thanh ghi n xung (clock counter register) quyt nh tc , Pclk c chia gi tr trong b n xung to tc cho SPI. Thanh ghi ny gi gi tr nh nht trong 8 bt. - Thanh ghi iu khin c s dng cu hnh hot ng ca bus SPI. Do cc thit b SPI ch truyn d liu v c gii rng cc thit b c th kt ni, xung SPI v

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ng d liu c th c cu hnh hot ng trong ch cu hnh ring. Trc ht cn to cc (mc thp hay cao hoc gia) phn on v xung nh hnh sau:

Hnh 3.28. To cc v phn on xung clock Cui cng cu hnh hng d liu cho bit MSB hay LSB c truyn trc.

Hnh 3.29. Cu hnh hng d liu qua SPI - Tng bt trong thanh ghi cu hnh c cu hnh kt ni truyn thng vi tng thit b qua SPI v c set bi ngi lp trnh. - D liu c gi i s c a vo thanh ghi d liu v truyn theo tng byte. 3.8. Chuyn i ADC v DAC 3.8.1. Chuyn i ADC - Chuyn i A/D trong mt s bin th ca LPC2000 l mt b chuyn i 10 bt vi tc chuyn i 2.44 uSec hoc 410KSps. B chuyn i A/D c 4 hoc 8 bt u ra ty tng phin bn. Trang 83

Hnh 3.30 Chuyn i A/D c 4 hoc 8 knh u ra vi phn gii 10 bt -Thanh ghi iu khin A/D thit lp cu hnh chuyn i v khi ng b chuyn i. - Trc ht phi ci t xung clock cho thit b, xung clock A/D s phn phi xung clock ti tt c cc thit b t ngun xung PCLK. Xung PCLK phi c chia xung 4.5MHz. y l gi tr xung cc i, nu PCLK khng th c chia xung 4.5MHz th gi tr gn nht vi 4.5MHz s c chn.

Hnh3.31. Cc bt ca thanh ghi iu khin AD PCLK c chia theo gi tr lu trong CLKDIV v theo cng thc sau: CLKDIV = ( PCLK/Adclk) - 1 Th d: M phng chuyn i A/D trong ch phn cng int main(void) { VPBDIV = 0x00000002; IODIR1 = 0x00FF0000; ADCR = 0x00270607; //thiet lap Pclk la 30 MHz // P1.16..23 dinh nghia cac chan ra // khoi dong A/D: 10-bit AIN0 @ 3MHz //ket noi toi A/D qua slot 0

VICVectCntl0 = 0x00000032;

VICVectAddr0 = (unsigned)AD_ISR; //lay dia chi cua ngat IRQ dua vao Trang 84

//VIC slot VICIntEnable = 0x00040000; //cho phep ngat while(1) {;} } void AD_ISR (void) { unsigned val,chan; static unsigned result[4]; val = ADDR; val = ((val >> 6) & 0x03FF); //Trich ket qua A/D

chan = ((ADCR >>0x18) & 0x07); result[chan] = val; } 3.8.2. Chuyn i D/A - Bin th LPC2132/2138 b chuyn i DA 10 bt. - B chuyn i ny n gin ch c 1 thanh ghi. - DAC c cho php bng cch ghi ti bt 18 v 19 ca PINSEL1 chuyn chn 0.25 t GPIO thnh chc nng AOUT. Ch rng mt knh ca b chuyn A/D cng s dng chn ny.

Hnh 3.32. Thanh ghi iu khin D/A B iu khin D/A c khi ng bng cch ghi gi tr ti bt VALUE trong thanh ghi iu khin. Thi gian chuyn i ph thuc vo bt BIAS. Nu =1 th thi gian chuyn i l 2.5uSec nhng c th t ti 700uA. Nu =0 th thi gian chuyn i l 1uSec nhng c th t n 350uA. Tuy nhin, tng thi gian thit lp ph thuc vo tr khng bn ngoi. 3.9. Truyn d liu qua CAN(Controller Area Network) Trang 85

- Cc bin th ca LPC c th c 4 b iu khin can c lp trn board. Giao thc CAN (Controller Area Network) c pht trin bi Robert Bosch cho mng t ng (Automotive Networking) vo nm 1982. Tri qua 22 nm sau, CAN tr thnh mt chun cho mng t ng v tr ln hp dn i vi cc h thng khng t ng m mun yu cu mt s nt c nhng vo. CAN c nhng c tnh hp dn i vi nhng ngi pht trin h nhng. N c chi ph thp, d hin thc ha, cc mng ngang hng vi c tnh kim tra li mnh v tc truyn cao, hng Mbit/s. Mi gi CAN kh nh v c th gi mt khi lng cc i l 8 byte d liu. Do , CAN rt ph hp vi cc mng nhng nh truyn mt lng d liu nh gia cc nt mt cch tin cy. Thit k node CAN: Mt nt CAN in hnh c thit k nh sau:

Hnh 3.33. Cu trc CAN - Mt c tnh quan trng khi thit k CAN l b iu kin CAN c ng truyn v nhn d liu ring bit v t thit b vt l. Bi vy mt nt ang ghi d liu ln bus, ng thi cng lng nghe phn hi trn bus. Do vy cn c c ch phn x v pht hin li trn bus. Hai mc logic c ghi ln 2 cp cp nh hnh di, hai mc logic 0 th hin trng thi ri ca bus.

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Hnh 3.34. Cu trc mt thng ip CAN:

Hnh 3.35. Cu trc thng ip CAN Cc bt nh danh dng dnh danh gi tin: theo chun 20A c 11 bt nh danh, 20B th ng th c bt nh danh v 20B ch ng c 29 bt nh danh. RTR lun bng 0. Bt DLC cha di d liu Bt CRC cha m li khi truyn Bt ACK: cho php chp nhn gi tin truyn mt thng ip CAN, B iu khin CAN c mt tp cc thanh ghi iu khin v thanh ghi trng thi nh sau:

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Hnh 3.36 Cc thanh ghi b iu khin CAN Tc truyn tnh theo cng thc: Tc baund=PCLK/(RBRx(1+Tseg1+Tseg2)) Vi RBR l tc prescaler. Cu trc thanh ghi nh thi prescaler:

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on chng trnh sau m t khi to CAN v truyn thng ip: C2MOD = 0x00000001; C2BTR = 0x001C001D; C2MOD = 0x00000000; //Khoi dong bo dieu khien CAN //thiet lap bi Timing la 125k //dung bo dieu khie CAN

if(C2SR & 0x00000004) //neu bo dem Tx Buffer 1 rong { C2TFI1 = 0x00040000; //thiet lap DLC la 4 byte C2TID1 = 0x00000022; //dia chi Standard Frame la 0x22 C2TDA1 = NetworkData; //copy du lieu vao 4 byte dau tien C2CMR = 0x00000001; //truyen thong diep } Nhn d liu qua CAN:

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Cu trc vng m nhn d liu

Hnh 3.37. Cc thanh ghi dng khi nhn d liu t CAN

int main(void) { VPBDIV = 0x00000001; //thiet lap PClk la 60MHz

IODIR1 = 0x00FF0000; // thiet lap cac chan ra PINSEL1|= 0x00040000; //cho phep chan 0.25 la CAN1 RX

C1MOD = 0x00000001; //reset CAN C1BTR = 0x001C001D; //thiet lap bit Timing la 125k C1IER =0x00000001; //cho phep nhan ngat Trang 90

VICVectCntl0 = 0x0000003A; //chon thu tu uu tien ngat VICVectAddr0 = (unsigned)CAN1IRQ; //lay dia chi ngat IRQ //into the VIC slot VICIntEnable = 0x04000000; //cho phep ngat AFMR = 0x00000001; C1MOD = 0x00000000; while(1){;} } //Cam bo loc //ket thuc CAM

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TI LIU THAM KHO

[1]. Philips (2005), The insiders guide to the Philips ARM7 based microcontroller. [2]. Jean J. Labrosse (2000), Embbeded System Building Block Second Edition: Commplete and ready to use in module C, R&D Books [3]. Michael Barr, Anthony Massa (2006), Programming Embedded Systems, O'Reilly

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