VLSI Lab5 2012

GII THIU V TOOL IC COMPILER

I/ MC CH
Gii thiu v lm quen vi tool ICC ca Synopsys

II/ L THUYT
1/ Gii thiu quy trnh layout Qu trnh layout gm cc bc sau: Phn vng (Partitioning) thit k Dng nn (Floorplanning) Sp xp (Placement) Tng hp cy clock (Clock tree synthesis) i dy (Routing) Xc nh RC (RC extraction) 1.1/ Phn vng thit k

Hnh 1: V d v mt m hnh c phn vng thit k Hai kiu thit k ASIC ph bin: thit k san bng (flat) v thit k phn cp (hierarchical). Thit k san bng th khng cn phn vng thit k, m ta s san bng v sp xp cc cng sao cho ph hp vi cc rng buc hay ti u thit k. Cch ny c p dng vi cc thit k loi nh

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VLSI Lab5 2012

Nu chn thit k phn cp, ta tin hnh phn vng thit k trong ASIC. Vic phn vng thit k ny c th c thc hin bc logic gi l phn vng logic hoc bc vt l gi l phn vng vt l. Vi kiu thit k ny, ta c th gp nhiu vn v thi gian tr v tn nhiu din tch hn thit k san bng. Nhng vi cch ny vic qun l thit k d dng hn, nh th trnh c cc li c th pht sinh do vic tp trung mt cc dy mt khu vc no 1.2/ Dng nn (Floorplanning) Bc dng nn (Floorplanning) nhm thc hin to cc mng power v ground trong chip, to cc pad power v ground cho li (core) v I/O, to cc vng (Ring) power, ground bao quanh core, ni cc im power v ground cho cc cell chun. Ngoi ra, floorplanning cn xc nh v tr cc pad I/O, xc inh v tr v s lng pad power, xc nh v tr v kiu phn phi clock. 1.3/ Sp xp (Placement) Sp xp (Placement) nhm tng hp vt l ca thit k t tp tin mc cng (Netlist). Bc ny trong qu trnh thit k vt l ng vai tr rt quan trng v n s quyt nh nhiu yu t ca thit k nh l ti u v thi gian, din tch, hay cng sut v kh nng i dy Placement s xc nh kch thc cell, phn chia cc li, chn cc buffer m hay nhn i cng nhm tng thm tr cc ng. Mc nh l khc phc cc vn v thi gian thit lp (Setup time), thi gian gi (Hold time) hay trnh s tc nghn (congestion driven placement) trong qu trnh i dy (Routing) 1.4/ Tng hp cy clock (Clock Tree Synthesis) Clock Tree Synthesis (CTS) nhm ti thiu ha lch clock gia clock ngun v cc nhnh bng cch chn buffer vo nhm ng b cc clock. ng thi li dng s lch clock gia cc tn hiu cng gip cho vic sa cc li v thi gian n gin hn. Qu trnh ny ph thuc nhiu vo cng c m ta s dng ti u

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

Hnh 2: Minh ha v chn cc buffer vo tn hiu clock trong CTS 1.5/ Di dy (Routing) Di dy (Routing) thc hin ni cc cng sau khi ta sp xp trong Placement. Routing l qu trnh to s lin kt vt l da trn tnh kt ni logic. Nhng chn tn hiu th c kt ni bng cc lin kt kim loi. Cc ng kt ni ny s c thc hin sao cho m bo cc yu cu v thi gian, lch clock, tr gia cc cng, in dung Do tnh phc tp ca cc thit k ASIC v s lng lin kt rt ln nn khi routing ta chia thnh ba giai on: Routing ring bit (special routing), routing ton b (global routing) v routing chi tit (detail routing).

Hnh 3: Mt thit k c routing 1.6/ Xc nh RC (RC Extraction) RC Extraction nhm xc nh cc gi tr k sinh RC c sinh ra trong thit k sau khi c layout. Vi cc cng ngh ngy cng cao, cc gi tr ny s nh hng kh ln n tr ca cc ng d liu (path delay). Chnh v th nhng ng m trong qu trnh ta kim tra

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

Pre-layout c th l ng nhng sau khi qua layout s sai. Do , trong bc Pre-layout c mt bc kim tra chc nng ca thit k vi rng buc v thi gian a ra nhng thng c b qua, do kt qu ca n khng c tn thuyt phc cao. Cc gi tr vt l ca layout s quyt nh rt ln n kh nng sng ca thit k. Do bc ny cn tin hnh k 2/ Gii thiu v cng c IC Compiler

Hnh 4: Tng qut v mt quy trnh IC Compiler

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

Tp tin mc cng (Netlist): ui .v hoc .ddc Tp tin rng buc (Constraints): ui .sdc Th vin cng ngh (Library synopsys): ui .db, .tf TLUPlus l tp tin c nh dng bng nh phn lu tr cc h s RC. Cc m hnh TLUPlus c tng hp bi nh sn xut, nh n ta c th kim tra c cc gi tr RC chnh xc bao gm cc h s chiu rng, khong cch, mt v nhit theo cc h s in tr. Cc tp tin cn thit lp m hnh TLUPlus l :
Tp tin tham chiu (.map) c th ch nh tng ng n cc lp (Layer) v Via

trong tp tin cng ngh Milkyway (.tf)

File m hnh TLUPlus cc i (maximum). File m hnh TLUPlus cc tiu (minimum).

3/ Cc lnh c bn trong IC Compiler

#Tao ra thu vien mw cua thiet ke create_mw_lib -technology $Techfile \ -mw_reference_library $Ref_lib \ $my_mw_lib

-technology file_name: Xc nh tp tin cng ngh (.tf) -mw_reference_library file_names: Xc nh th vin tham chiu Milkyway. Dng to ra th vin ca thit k mnh library_name: Tn ca th vin thit k m mnh mun to ra.
#Import cac tap tin thu vien TLUPlus trong layout set_tlu_plus_files \ -max_tluplus $Tlupmax \ -min_tluplus $Tlupmin \ -tech2itf_map $Tech2itf

-max_tluplus file_name: Tp tin m hnh TLUPlus cc i (maximum) -min_tluplus file_name: Tp tin m hnh TLUPlus cc tiu (minimum). -tech2itf_map file_name: Tp tin cng ngh Milkyway (.tf)
#Import tap tin netlist import_designs \ -format verilog \ -top $cell_name \

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

-cel $cell_name ${LinkNetlist}/${cell_name}_NL.v #Neu import tap tin .v thi khong can tap tin .ddc #import_designs -format ddc ${LinkNetlist}/${cell_name}_NL.ddc #Import tap tin rang buoc cua thiet ke read_sdc "${LinkNetlist}/${cell_name}.sdc"

Tp tin Netlist y c th l tp tin verilog (.v) hay tp tin nh dng c s d liu ca Synopsys (.ddc) v tp tin quy nh cc rng buc (.sdc) c m t trong bc tng hp thit k
initialize_floorplan \ -core_utilization $Core_util \ -left_io2core $Core_space \ -bottom_io2core $Core_space \ -right_io2core $Core_space \ -top_io2core $Core_space

Lnh initialize_floorplan tin hnh khi to Floorplan nhm to nn khung ca thit k. Cc thit lp trong lnh ny l : -core_utilization: Xc nh h s s dng li ca thit k. Gi tr ny s cho bit phm vi m ta tin hnh sp xp cc cell chun l bao nhiu ca tng din tch thit k. Gi tr nm trong 0 n 1. Thng thng ta nn s dng l 0.6 hay 0.7 v nu li chim qu cao th s khng c ch cho ta tin hnh i dy (routing). Cn nu qu nh s lng ph khng gian ca thit k Utilization = (Tng din tch cc cell hay Macro) x 100% / ( Kch thc ca thit k) -left_io2core: Xc nh khong cch t l bn tri ca li vi bn phi ca cc hoc pad gn nht -bottom_io2core: Xc nh khong cch t l bn di ca li vi bn phi ca cc hoc pad gn nht -right_io2core: Xc nh khong cch t l bn phi ca li vi bn phi ca cc hoc pad gn nht -top_io2core: Xc nh khong cch t l bn trn ca li vi bn phi ca cc hoc pad gn nht

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

derive_pg_connection \ -create_ports all\ -power_net VDD \ -power_pin VDD \ -ground_net VSS \ -ground_pin VSS \ -tie

Lnh derive_pg_connection dng to cc port kt ni ngun (VDD) v t (VSS) cho thit k. Cc thit lp trong lnh l: -create_ports: To port trn mc top ca thit k. -power_net: Xc nh tn ca li ngun (Power net) -power_pin: Xc nh tn ca chn ngun (Power pin) -ground_net: Xc nh tn ca li t (Ground net) -ground_pin: Xc nh tn ca chn t (Ground pin) -tie: kt ni cc chn lin kt cao (tie-high) v lin kt thp (tie-low). Cc mng power v ground phi tn ti trc khi kt ni cc chn tie-high v tie-low
#Tao vong VDD create_rectangular_rings \ -nets {VDD} \ -right_offset 2.0 \ -right_segment_layer M4 \ -right_segment_width 2.0 \ -left_offset 2.0 \ -left_segment_layer M4 \ -left_segment_width 2.0 \ -bottom_offset 2.0 \ -bottom_segment_layer M5 \ -bottom_segment_width 2.0 \ -top_offset 2.0 \ -top_segment_layer M5 \ -top_segment_width 2.0 #Tao vong VSS create_rectangular_rings \ -net {VSS} \

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

-left_offset 0.5 \ -left_segment_layer M5 \ -left_segment_width 2.0 \ -right_offset 0.5 \ -right_segment_layer M5 \ -right_segment_width 2.0 \ -bottom_offset 0.5 \ -bottom_segment_layer M5 \ -bottom_segment_width 2.0 \ -top_offset 0.5 \ -top_segment_layer M5 \ -top_segment_width 2.0

Lnh create_rectangular_rings thc hin to cc vng. Vi cc thit lp nh sau: -net: Loi ng ta to -left_offset: khong lch so vi bn tri -left_segment_layer: lp m ta tin hnh to -left_segment_width: rng ca ng c to
#Tao cac strap VDD,VSS create_power_straps \ -direction vertical \ -start_at 30 \ -num_placement_strap 8 \ -increment_x_or_y 20 \ -nets {VDD} \ -layer M6 \ -width 1.0 \ -do_not_route_over_macros create_power_straps \ -direction vertical \ -start_at 40 \ -num_placement_strap 8 \ -increment_x_or_y 20 \ -nets {VSS} \ -layer M7 \ -width 1.0 \ -do_not_route_over_macros

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

Lnh create_power_straps thc hin to cc li. y ta dng lnh ny tin hnh to li ngun v t. Cc thit lp ca lnh ny l :
-direction: Hng m ta tin hnh xy dng, c hai hng: vertical(Theo chiu ngang)

hoc horizontal (Theo chiu dc). -start_at: V tr bt u tin hnh xy dng -num_placement_strap: s ng m ta mun xy dng -increment_x_or_y: Khong cch gia hai ng -nets: Loi ng (net) -layer: Lp thc hin -width: rng ca cc ng
#Tien hanh Placement place_opt

Tin hnh ti u Placement theo ch mc nh

#Tien hanh CTS clock_opt -fix_hold_all_clocks -inter_clock_balance

Tng t nh qu trnh Placement, Synopsys h tr ta cc lnh thit lp tng hp cy clock (CTS) bng lnh clock_opt.
#Tien hanh Routing set_fix_hold [all_clocks] route_opt -incremental -only_hold_time

y l bc k cui trong quy trnh thit k vt l. y cc cell chun s c ni li vi nhau. Bc ny s pht sinh thm cc c tnh vt l ca thit k. Trong IC Compiler, lnh dng thc hin chc nng ny l route_opt
#Them cac Core Filler Cells insert_stdcell_filler \ -connect_to_power "VDD" -connect_to_ground "VSS"

Lnh insert_stdcell_filler: Thm cc filler cells nhm m bo cc ng powe v ground lin tuc, cng nh m bo tnh lin tc ca cc n-well v p-well ti mi hng ca cc cell chun. Cc filler cells cha trong th vin cell chun.
#Tien hanh phu kim loai o 9 lop insert_metal_filler \

Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

-purge \ -out self \ -from_metal 1 -to_metal 9 \ -timing_driven -routing_space 2 insert_metal_filler -out self -tie_to_net ground \ -from_metal 1 -to_metal 9 -routing_space 2

Lnh insert_metal_filler: Tin hnh ph kim loi cc lp. -purge: Lm sng t tt c v tr kim loi ph trong cc cell c thy -out self: Xc nh v tr to ng ra.-from_metal 1 -to_metal 9: to ng ra t lp 1 n lp 9 -timing_driven: Ph kim loi c nh hng theo thi gian -routing_space: Khong cch gia cc dy v kim loi ph -tie_to_net: Xc nh kim loi ph c kt ni vi net hay khng.-tie_to_net ground: Kim loi ph kt ni vi t (Ground) 4/ Tin hnh chy cng c IC Compiler Ta c 3 cch tin hnh chy cng c Design Compiler Cch 1: Tin hnh chy trn giao din GUI. G lnh icc_shell gui Cch 2: Tin hnh chy trn terminal v tin hnh g cc lnh.
-

G lnh icc_shell

Tin hnh g cc lnh trn terminal tin hnh chy.

Cch 3: Tin hnh chy t u n cui ca mt tp tin rng buc bng cch s dng mt file script.tcl.
-

G lnh icc_shell f <filescript>.tcl

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

Tin hnh chy v cc thng bo v warning, error s xut ra trn terminal icc_shell f <filescript>.tcl | tee <ErrorICC>.log Sau khi chy, cc thng bo trn terminal s lu vo mt file .log gip ta quan st d hn

III/ THC HNH

Bc 1: Sa folder [Lab5]ICC thnh Lab5_ICC To folder ThucHanh trong Lab5_ICC To folder netlist, sdc, icc trong folder ThucHanh To folder icc_report trong folder icc To file icc_script.tcl trong folder icc Copy file counter_NL.v trong Lab4_PT/ThucHanh/netlist vo folder netlist mi to Copy file counter_SDC.sdc trong Lab4_PT/ThucHanh/sdc vo folder sdc mi to Bc 2: Vit file icc_script.tcl vi ni dung nh sau: 1. Thit lp cc bin ng dn cho file script:
#Thiet lap ten thiet ke set cell_name "Counter" set my_mw_lib "Counter_Lib" #Thiet lap cac duong dan set mw_path < ng dn n folder icc> set LinkProject < ng dn n folder Lab5_ICC/ThucHanh> set LinkLibrary_mk <ng dn n folder /Lib/process > set LinkLibrary_db <ng dn n folder /Lib/syn_lib/syn_lib > set LinkReport < ng dn n folder icc_report> set LinkNetlist < ng dn n folder netlist> #Thiet lap mot so bien trong thiet ke set Core_util "0.60" set Core_space "4" set mw_logic0_net VSS set mw_logic1_net VDD set power "VDD" set ground "VSS" set powerPort "VDD" set groundPort "VSS"

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

2. Thit lp ng dn cc th vin
#Thiet lap cac duong dan den cac thu vien cong nghe set Techfile "${LinkLibrary_mk}/astro/tech/astroTechFile.tf" set Ref_lib "${LinkLibrary_mk}/astro/fram/saed90nm_fr" set Tlupmax "${LinkLibrary_mk}/star_rcxt/tluplus/saed90nm_1p9m_1t_Cmax.tluplus" set Tlupmin "${LinkLibrary_mk}/star_rcxt/tluplus/saed90nm_1p9m_1t_Cmin.tluplus" set Tech2itf "${LinkLibrary_mk}/astro/tech/tech2itf.map" set target_library [list ${LinkLibrary_db}/saed90nm_min.db / ${LinkLibrary_db}/saed90nm_typ.db / ${LinkLibrary_db}/saed90nm_max.db] set link_library [list * ${LinkLibrary_db}/saed90nm_max.db] set mw_logic0_net VSS set mw_logic1_net VDD

3.

Khi to th vin Milkyway

#Tao ra thu vien mw cua thiet ke create_mw_lib -technology $Techfile \ -mw_reference_library $Ref_lib \ $my_mw_lib

4. Thit lp cc tp tin TLUPlus

#Import cac tap tin thu vien TLUPlus trong layout set_tlu_plus_files \ -max_tluplus $Tlupmax \ -min_tluplus $Tlupmin \ -tech2itf_map $Tech2itf

5. c tp tin Netlist v tp tin rng buc (Constraints)

#Import tap tin netlist import_designs \ -format verilog \ -top $cell_name \ -cel $cell_name ${LinkNetlist}/${cell_name}_NL.v #Import tap tin rang buoc cua thiet ke read_sdc "${LinkNetlist}/${cell_name}.sdc" #Luu thit k save_mw_cel -as "mw_Counter"

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

6. Khi to floorplaning
initialize_floorplan \ -core_utilization $Core_util \ -left_io2core $Core_space \ -bottom_io2core $Core_space \ -right_io2core $Core_space \ -top_io2core $Core_space

7. Kt ni Power v Ground
derive_pg_connection \ -create_ports all\ -power_net VDD \ -power_pin VDD \ -ground_net VSS \ -ground_pin VSS \ -tie

8. To vng power v ground

#Tao vong VDD create_rectangular_rings \ -nets {VDD} \ -right_offset 2.0 \ -right_segment_layer M4 \ -right_segment_width 0.5 \ -left_offset 2.0 \ -left_segment_layer M4 \ -left_segment_width 0.5 \ -bottom_offset 2.0 \ -bottom_segment_layer M5 \ -bottom_segment_width 0.5 \ -top_offset 2.0 \ -top_segment_layer M5 \ -top_segment_width 0.5 \ -extend_tl \ -extend_th #Tao vong VSS create_rectangular_rings \ -net {VSS} \ -left_offset 0.5 \

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VLSI Lab5 2012

-left_segment_layer M5 \ -left_segment_width 0.5 \ -right_offset 0.5 \ -right_segment_layer M5 \ -right_segment_width 0.5 \ -bottom_offset 0.5 \ -bottom_segment_layer M5 \ -bottom_segment_width 0.5 \ -top_offset 0.5 \ -top_segment_layer M5 \ -top_segment_width 0.5 \ -extend_tl \ -extend_th

preroute_standard_cells -mode rail -nets "VSS VDD" 9. To cc di power v ground

#Tao cac strap VDD,VSS create_power_straps \ -direction vertical \ -start_at 6 \ -num_placement_strap 10 \ -increment_x_or_y 2 \ -nets {VDD} \ -layer M6 \ -width 0.5 \ -do_not_route_over_macros create_power_straps \ -direction horizontal \ -start_at 6 \ -num_placement_strap 10 \ -increment_x_or_y 2 \ -nets {VSS} \ -layer M7 \ -width 0.5 \ -do_not_route_over_macros #Luu thit k save_mw_cel -as "mw_Counter_floorplan"

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012

10. Tin hnh Placement
#Tien hanh Placement place_opt -congestion

11. Clock Tree Synthesis

#Tien hanh CTS clock_opt -no_clock_route -only_psyn -fix_hold_all_clocks -only_hold_time #Report timing

report_placement_utilization > ng dn report to ra file cts_${cell_name}_util.rpt report_qor_snapshot > ng dn report to ra file cts_${cell_name}_qor_snapshot.rpt report_qor > ng dn report to ra file cts_${cell_name}_qor.rpt report_timing max_paths 20 delay max > ng dn report to ra file cts_${cell_name}_setup.rpt report_timing max_paths 20 delay min > ng dn report to ra file cts_${cell_name}_hold.rpt
#Luu thit k save_mw_cel -as "mw_Counter_cts"

12. Routing
#Tien hanh Routing route_opt #Report timing

report_placement_utilization > ng dn report to ra file route_${cell_name}_util.rpt report_qor_snapshot > ng dn report to ra file route_${cell_name}_qor_snapshot.rpt report_qor > ng dn report to ra file route_${cell_name}_qor.rpt report_timing max_paths 20 delay max > ng dn report to ra file route_${cell_name}_setup.rpt report_timing max_paths 20 delay min > ng dn report to ra file route_${cell_name}_hold.rpt
#Luu thit k save_mw_cel -as "mw_Counter_route"

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM

VLSI Lab5 2012 IV/ BI TP

Bi 1: Tin hnh chy layout thit k Counter v chp hnh kt qu trn giao din GUI tng bc. Tng hp cc kt qu trn vo mt file report (pdf hay word) Bi 2: Tin hnh chy layout thit k ChipLevel. Chp hnh kt qu trn giao din GUI tng bc. Gi bo co v timing (setup time v hold time) cc bc CTS, route v kt qu kim tra DRC, LVS ca thit k (S dng 2 lnh verify_drc v verify_lvs)

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Khoa in T - Vin Thng, Trng H KHTN, Tp HCM