Thiết kế BDK PID số trên nền VDK PIC

Trng i hc bch khoa h ni Khoa in
B mn iu khin t ng
N TT NGHIP
ti:Thit k b iu khin PID s trn nn vi iu khin PIC
Gio vin hng dn : PGS.TS Phan Xun Minh Sinh vin thc hin : Phm Vn Cng Hong Vn Qun Lp : KT1 Kho : 49
H Ni 5 - 2009
Mc lc
Li m u .......................................................................................... 5 Li cm n........................................................................................... 6
Chng 1 : H vi iu khin PIC v vi iu khin PIC18F4520 ..........................7 1.1 Gii thiu chung .......................................................................................... 7 1.2 . Vi iu khin Pic18F4520 ......................................................................... 8 1.2.1. T chc b nh (Memory Organization) ........................................... 13 1.2.2. 8 x 8 HARDWARE MULTIPLIER ................................................... 22 1.2.3. Ngt (Interrupts) ................................................................................. 23 1.2.4. Cng vo ra (I/O Port)........................................................................ 32 1.2.5. B nh thi (Timer) .......................................................................... 33 1.2.6. B truyn nhn d liu ng b (EUSART-Enhanced Universal Synchronous Asynchronous Receiver Transmitter)..................................... 37 1.2.7. Module chuyn i tong t sang s 10 bit (A/D) ............................ 50 Chng 2 : Thit k b iu khin PID s...........................................................57 2.1 Thit k m hnh phn cng mch iu khin........................................... 57 2.1.1. Yu cu thit k .................................................................................. 57 2.1.2. Cc khi chc nng trn kit iu khin.............................................. 58
a) Khi vi iu khin trung tm....................................................................................58 b) Khi giao tip my tnh qua cng ni tip ...............................................................59 c) Khi bn phm ..........................................................................................................60 d) Khi hin th LCD 2x16(2 dng, 16ct) ..................................................................61 e) Khi mch ng lc iu khin................................................................................62 f) Khi ngun 12V/5V..................................................................................................62 g) Cc khi khc ...........................................................................................................63
2.2 Thit k phn mm trn nn vi iu khin PIC ......................................... 64 2.2.1. Yu cu phn mm ............................................................................. 64 2.2.2. Gii thut chng trnh ...................................................................... 65
a) Loop iu khin........................................................................................................65 b) Thut ton PID s.....................................................................................................66
2.2.3. Thit k phn mm iu khin v gim st trn my tnh ................. 69 2.3 Kit iu khin............................................................................................. 71 Chng 3 : ng dng b iu khin PID s iu khin ng c mt chiu .......72 3.1 i tng iu khin ................................................................................. 72 3.1.1. Thng s k thut ................................................................................ 72 Phm Vn Cng - Hong Vn Qun. Lp KT1-K49
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3.1.2. Nhn dng m hnh ng hc ca ng c in mt chiu ............... 72 3.1.3. Thu thp d liu vo/ra ca ng c in mt chiu t thcnghim. 72 3.1.4. Nhn dng ng c in mt chiu bng Toolbox Identification cu Matlab........................................................................................................... 74 3.1.5. nh gi cht lng m hnh ............................................................. 76 3.2 Thit k lut iu khin PID...................................................................... 77 3.2.1. Phng php Ziegler-Nichols1 .......................................................... 77 3.2.2. Phng php IMC .............................................................................. 77 3.2.3. M phng v nh gi cht lng b iu khin ............................... 78 3.3 Thit b chp hnh(IC L298) ..................................................................... 78 3.4 Cm bin (Encoder) ................................................................................... 81 3.5 H thng iu khin................................................................................... 84 3.6 Mt s hnh nh v Kit iu khin ng c s dng vi iu khin PIC .. 86 3.7 :Kt qu thc nghim................................................................................. 87 3.8 So snh kt qu m phng v thc t ........................................................ 88
Kt lun ............................................................................................. 89 Ti liu tham kho ............................................................................. 91 Ph lc Code phn mm.................................................................... 92
Phm Vn Cng - Hong Vn Qun. Lp KT1-K49
MC LC HNH V
Hnh 1.1 S khi kin trc vi iu khin PIC18F4520 ............................................. 9 Hnh 1.2 S chn vi iu khin Pic18F4520 ........................................................... 10 Hnh 1.3: T chc b nh chng trnh ....................................................................... 13 Hnh 1.5: Clock/Instruction Cycle................................................................................ 15 Hnh 1.6 Instruction Pipeline Flow .............................................................................. 15 Hnh 1.7 Instruction In Program Memory.................................................................... 16 Hnh 1.8 S cu trc b nh d liu Pic18F4520 ................................................... 16 Hnh 1.9 S cu trc thanh ghi ca Pic18F4520 ..................................................... 17 Hnh 1.10 Pic 18 Interrup logic .................................................................................... 23 Hnh 2.1 M hnh khi mch iu khin...................................................................... 57 Hinh 2.2.S khi vi iu khin trung tm ............................................................... 58 Hinh 2.3 Mch np cho vi iu khin trung tm .......................................................... 58 Hinh 2.4 Khi giao tip my tnh Max232................................................................... 59 Hnh 2.5 : Cu to cng COM...................................................................................... 59 Hinh 2.6 Modul bn phm ............................................................................................ 60 Bng s lc chc nng LCD 2x16 ............................................................................. 61 Hnh 2.7 Khi hin th LCD ......................................................................................... 62 Hinh 2.8 Khi thit b chp hnh.................................................................................. 62 Hnh 2.9 S khi ngun........................................................................................... 62 S nguyn l kit iu khin..................................................................................... 63 S mch in hai lp ................................................................................................... 64 Hnh 2.10 Lu loop iu khin................................................................................ 65 Hnh 2.11 Lu hm ngt dng to chu l trch mu................................................. 66 Hnh 2.12 S b iu khin PID s ......................................................................... 67 Hnh 2.13 Chng bo ho tch phn ............................................................................. 68 Hnh 2.14. Giao din giao tip PC................................................................................ 69 Hnh 3.1 ng c s dng trong n......................................................................... 72 Hinh 3.2 S thu thp d liu nhn dng .................................................................. 72 Hnh 3.2 c tnh thu thp d liu nhn dng............................................................. 73 Hnh 3.3Chn u vo v m hnh nhn dng ca i tng ...................................... 75 Hnh 3.4Phng thc nhn dng v nh gi m hnh thu c ................................. 75 Hnh 3.5 c tnh qu i tng sau khi nhn dang ............................................... 76 Hnh 3.6 Sai lch m hnh nhn dng........................................................................... 76
Hnh 3.7 M phng trn Simulink cc phng php iu khin ................................ 78 Hnh 3.9 c tnh m phng ........................................................................................ 78 Hnh 3.10 S chn L298.......................................................................................... 79 Hnh 3.11: Cc ch ca L298 .................................................................................. 80 Hnh 3.12 : S gii php .......................................................................................... 81 Hnh 3.13 : M hnh1 - En coder quang tng i ...................................................... 81 Hnh 3.14 : Phng thc hot ng Encoder quang tng i.................................... 82 Hnh 3.15 : M hnh 2 -En coder quang tng i ...................................................... 82 Hnh 3.16 : S xung ca En coder quang tng i(m hnh 2) ............................ 83 Hnh 3.17 S h thngiu khin ng c .............................................................. 84 Hnh 3.18 Cu trc h thng iu khin....................................................................... 84 Hnh 3.19 Cu trc khi iu khin ng c................................................................ 85 Mt s hnh nh mch iu khin ng c mt chiu.................................................. 86 Hnh 3.20 c tnh vi b iu khin PI...................................................................... 87 Hnh 3.21 c tnh vi b iu khin PID ................................................................... 87 Hnh 3.22 H thng khi c nhiu................................................................................. 88 Hnh 3.23 c tnh khi h thng c thay i gi tr t ............................................... 88
Li m u
Khoa hc cng ngh hin i c nhng bc tin nhanh v xa i theo l nhng thnh tu ng dng trong mi lnh vc di sng, cng nghip. K thut iu khin trong tin trnh hon thin l thuyt cng to cho mnh nhiu pht trin c ngha. By gi khi nhc ti iu khin con ngi dng nh hnh dung n s chnh xc, tc x l v thut ton thng minh ng ngha l lng cht xm cao hn. C th ni trong lnh vc iu khin v trong cng nghip th b iu khin PID c ng dng kha rng ri, mt gi php a nng chocc ng dng c Analog cng nh Digital. Thng k cho thy c ti hn 90% cc b iu khin s dng trong thc t l PID. R rng nu c thit k v chn la cc thng s hp l cho b iu khin PID th vic t c cc ch tiu cht lng mong mun l kh thi B iu khin PID cng gip ngi s dng d dng tch hp cng nh chn cc lut iu khin nh : t l(P), tch phn(I), t l tch phn(PI), t l vi phn(PD) sao cho ph hp i vi cc i tng iu khin. Nhiu qu trnh trong cng nghip vic s dng b iu khin PID l khng th thay th nh khng ch nhit , mc, tc ? Ngay c nhng l thuyt iu khin hin i cng khng cho ta nhng hiu qu cao nh b iu khin PID mang li.Ngoi ra b iu khin PID cn ng dng nhiu trong iu khin thch nghi,bn vng vn mang li hiu qu cao trong cc c cu chnh nh. Bi ton thit k v iu khin ng c mt chiu l bi ton c bn v quen thuc trong ngnh iu khin t ng. C th thit k iu khin cho i tng ngc in mt chiu theo nhiu phng php nh :dng PLC & bin tn, in t cng sut, vi iu khin Mi phng php c u v nhc im khc nhau nhng u c mc ch n nh v iu khin c tc ng c. Ngy nay vi iu khin pht trin su rng v ngy cng ng dng nhiu trong ci t thit k b iu khin cho cc i tng cng nghip. Trn c s mun tm hiu v lnh vc vi iu khin chng em chn ti: Thit k b iu khin PID s trn nn vi iu khinPIC. V kh nng v thi gian c hn nn khng th trnh khi nhng thiu st trong n. Do vy chng em rt mong c thy c v bn b ng gp xy dng n ca chng em c hon thin hn. H Ni, ngy thng nm 2009 Sinh vin Phm Vn Cng Hong Vn Qun Lp KT1 - K49
Li cm n
u tin chng em xin chn thnh gi li cm n ti nh trung, khoa in, b mn KT, cc thy c dy d v du dt chng em trong sut 5 nm hc va qua c c nhng kin thc chuyn mn c s sau ny chng em c th vo i lm vic, s dng c ch cho x hi. thc hin thnh cng n l s hng dn, ch bo tn tnh ca PGS.TS Phan Xun Minh, Ngi hng dn tn tnh , gip chng em nh hng, gp v cung cp tng cng nh ch dn ti liu v cc tin trnh thc hin n .S hng dn ca c l mt yu t quan trng chng em c th hon thnh n ny . Cui cng chng em xin chn thnh gi nhng li cm n su sc n cha m v gia nh, nhng ngi lun st cnh cng chng em, nui dng chm sc chng em to iu kin tt nht cho chng em hc tp c kt qu nh ngy hm nay. Chng em xin chn thnh cm n
Vi iu khin Pic
Chng 1: H vi iu khin PIC v vi iu khin PIC18F4520

1.1 Gii thiu chung
Ngy nay, nhng ng dng ca vi iu khin i su vo i sng sinh hot v sn xut ca con ngi. Thc t hin nay l hu ht cc thit b in hin nay u c s gp mt ca vi iu khin v vi x l. ng dng vi iu khin trong thit k h thng lm gim chi ph thit k v h gi thnh sn phm ng thi nng cao tnh n nh ca thit b v h thng. Trn th trng hin nay c nhiu h vi iu khin la chn nh: 8051, Motola68HC, AVR, ARM, Picv c l 8051 l dng m chng ta c lm quen nhiu nht trong mi trng i hc nhng ti sao chng ta chn dng vi iu khin Pic thc hin ng dng v pht trin khng ngoi nhng nguyn nhn sau: H vi iu khin Pic pht trin v s dng ph bin nc ta => vic tm mua v trao i kinh nghim l ht sc thun li. Gi thnh cc dng Pic l khng qu mc. Cc dng Pic c y tnh nng hot ng c lp. L s b sung hp l v kin thc cng nh ng dng cho h vi iu khin 8051 C s h tr cao ca nh sn xut v cc cng c lp trnh, trnh bin dch, mch np Pic t n gin ti phc tp. Khng nhng vy cc tnh nng a dng ca cc ng Pic khng ngng c pht trin. C nhiu b phn ngoi vi ngay trn chip, bao gm: Cng v/ra s, b bin i ADC, b nh EEFROM, b nh thi, b iu ch rng xung (PWM) B nh chng trnh v b nh d liu c tch hp ngay trn chip.
y l h VK c ch to theo kin trc RISC (Reduced Intruction Set Computer) c cu trc kh phc tp. Ngoi cc tnh nng nh cc h VK khc, n cn tch hp nhiu tnh nng mi rt tin li cho ngi thit k v lp trnh. Pic18F4520 nm trong dng sn phm PIC18F2420/2520/4420/4520 ca nh sn xut Microchip vi c im 28/40/44 -Pin Enhanced Flash Microcontrollers with 10Bit A/D and nanoWatt Technology. Dng sn phm ny c nhiu ci tin ng k v tnh nng so cc dng Pic trc nh : - B nh chng trnh c tng cng (16Kbytes for PIC18F2420/4420 devices and 32Kbytes for PIC18F2520/4520 devices).
Vi iu khin Pic
I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). Tng cng modul CCP. S dng cng ngh nanoWatl
Dng sn phm ny ni chung c nhiu s tng ng v tnh nng nhng c th chia lm hai nhm Pic18F2420/2520 vi 28 chn v Pic 18F4420/4520 vi 40 hoc 44 chn ghp ni. Phn ny ch yu chng ta tm hiu Pic18F4520 nhng nhng c im cc Pic khc thuc dng ny s hon ton tng t vi cc k hiu tng ng. Trong n chng ta quan tm ch yu Pic18F4520 loi PDIP s dng trong mch thit k.
1.2 . Vi iu khin Pic18F4520

Vi iu khin Pic18F4520 c cc c im c bn: S dng cng ngh nanoWatl: Hiu nng cao, tiu th nng lng t Kin trc RISC
75 lnh mnh, hu ht cc lnh thc hin trong bn chu k xung. Tc thc hin ln ti 10 triu lnh trong 1s vi tn s 40Mhz C b nhn cng . - Cc b nh chng trnh v d liu c nh 32 Kbytes b nh flash c kh nng t lp trnh trong h thng c th thc hin c 100.000 ln ghi/xa 256 bytes EEPROM c th thc hin c 1.000.000 ln ghi/xa256 bytes SRAM - Nhng ngoi vi tiu biu 4 b nh thi/b m 8 bit vi cc ch t l t trc v ch so snh. B m thi gian thc vi b to dao ng ring bit 2 knh PWM 13 knh ADC 10 bit B truyn tin ni tip USART kh trnh Watchdog Timer kh trnh vi b to dao ng bn trong ring bit B so snh tng t - Cc c im c bit khc Power on Reset v d Brown out kh trnh
Vi iu khin Pic
B to dao ng RC c nh c bn trong Cc ngun ngt bn trong v bn ngoi - I/O v cc kiu ng gi 32 ng I/O kh trnh ng gi 40-pin PDIP, 44-lead TQFP, v 44-pad MLF
Hnh 1.1 S khi kin trc vi iu khin PIC18F4520
Vi iu khin Pic
S chn ca cc vi iu khin Pic18F4420/4520
Hnh 1.2 S chn vi iu khin Pic18F4520 Sau y l gii thiu cu to chn loi 40 chn (40 Pin PDIP):
Chn 1( MCLR /VPP/RE3) :

- MCLR l u vo Master Clear (reset) hot ng mc thp d reset ton b thit b. - VPP dng thay i in p u vo. - RE3 u vo s. Cc chn thuc cng vo ra Port A Chn 2(RA0/AN0):vi RA0 l cng vo ra s, AN0 l u vo tng t Input0. Chn 3(RA1/AN1): RA1 l cng vo ra s, AN1 l u vo tng t Input1. Chn 4(RA2/AN2/VREF+): RA2 l cng vo ra s, AN2 l u vo tng t Input2. VREF+ u vo tng t chuyn i A/D in p tham chiu(mc thp), cn CVREF l u ra tng t so snh in p chun. Chn 5(RA3/AN3/VREF-/CVREF ): RA3 l cng vo ra s, AN3 l u vo tng t Input3. VREF- u vo tng t chuyn i A/D in p tham chiu(mc cao). Chn 6(RA4/T0CKI/C1OUT): RA4 l u vo ra s,T0CKI du vo xung bn ngoi ca Timer0, C1OUT l u ra b so snh 1. Chn 7(RA5/AN4/ SS /HLVDIN/C2OUT): trong RA5 l cng vo ra s, AN4 l u vo tng t Input 4, SS chn u vo ph thuc SPI, HLVDINu vo tng t d in p, C2OUT u ra b so snh 2.
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Vi iu khin Pic
Chn 13(OSC1/CLKI/RA7): vi OSC1l u vo b dao ng thch anh hoc l u vo ngun xung t bn ngoi, khi ta ni dy vi cc thit b tng t th u vo ny dng ST( Schmitt Trigger input ith CMOS levels).CLKI l u vo CMOS cho ngun xung bn ngoi v lun c ghp ni vi chn OSC1. Cn RA7 l chn vo ra s dng chung . Chn 14(OSC2/CLKO/RA6): OSC2 l u ra b dao ng thch anh c ni vi thch anh hoc b cng hng d la chn dng b dao ng thch anh. CLK0 c tn s bng tn s ca OSC1 rng chu k lnh, RA6 l u vo ra chung. Cc chn cng vo ra hai chiu Port B. Port B c th lp trnh bng phn mm khi cho ko u vo bn trong yu ln trn ton b u vo. Chn 33(RB0/INT0/FLT0/AN12): Vi RB0 l cng vo ra s, INT0 l u vo ngt ngoi Interrup 0, FLT0 l u vo bo li PWM c tng cng CCP1, AN12 u vo tng t Input 12. Chn 34(RB1/INT1/AN10): RB1 l u vo ra s, INT1 u vo ngt ngoi Interrup1, AN10 u tng t Input 10. Chn 35(RB2/INT2/AN8): RB2 l u vo ra s, INT2 u vo ngt ngoi Interrup2, AN8 u tng t Input 8. Chn 36 (RB3/AN9/ccp2): RB3 l u vo ra s, AN9 u tng t Input 9, CCP2 ( Capture 2 input/Compare 2 output/PWM2 output.) Chn 37(RB4/KBI0/AN11):): RB4 l u vo ra s, KBI0 thay i m ngt, AN11 u tng t Input 9. Chn 38(RB5/KBI1/PGM): RB5 u vo ra s, KBI1 thay i m ngt, PGM cho php c th lp trnh ISCPTM in p thp. Chn 39(RB6/KBI2/PGC): RB6 l u vo ra s, KBI2 thay i m ngt, PGC chn dng trong mch chy v xung lp trnh ICSP. Chn 40(RB7/KBI3/PGD): RB7 u vo ra s, KBI3 thay i m ngt, PGD chn dng trong mch chy v xung lp trnh ICSP. Cc chn cng Port C Chn 15(RC0/T1OSO/T13CKI):RC0 u vo ra s, T1OSO u ra b dao ng Timer1, T13CKI u vo xung bn ngoi Timer1/Timer3. Chn 16(RC1/T1OSI/CCP2): RC1 u vo ra s, T1OSI u vo b dao ng Timer1, CCP2(Capture 2 input/Compare 2 output/PWM2 output.). Chn 17(RC2/CCP1/P1A): RC2 l u vo ra s, CCP1(Capture1 input/Compare 1 output/PWM1 output.), P1A u ra tng cng CCP1. Chn 18(RC3/SCK/SCL): RC3 l u vo ra s, SCK u vo ra chui xung vo ra cho SPI la chn, SCL u vo ra a chui xung vo ra cho I2CTM la chn.
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Vi iu khin Pic
Chn 23(RC4/SDI/SDA): RC4 l u vo ra s, SDI u vo d liu API, SDA u vo ra d liu cho I2C. Chn 24(RC5/SDO): RC5 u vo ra s, SDO u ra d liu SPI. Chn 25(RC6/TX/CK): RC6 u vo ra s, TX u ra chuyn i d b EUSARRT, CK du vo ra xung ng b EUSART. Chn 26(RC7/RX/DT): RC7 u vo ra s, RX u vo nhn d b EUSART, DT u vo ra d liu ng b EUSART. Cc chn cng Port D( Port D c th vo ra hai hng hoc cng song song ph thuc(PSP) cho giao din vi x l v khi cc u vo phi l TTL.. Chn 19(RD0/PSP0): RD0 u vo ra s, PSP0 cng d liu song song ph thuc. Chn 20(RD1/PSP1): RD1 u vo ra s, PSP1cng d liu song song ph thuc Chn 21(RD2/PSP2): RD2u vo ra s, PSP2 cng d liu song song ph thuc Chn 22(RD3/PSP3): RD3 u vo ra s, PSP3 cng d liu song song ph thuc Chn 27(RD4/PSP4): RD4 u vo ra s, PSP4 cng d liu song song ph thuc Chn 28(RD5/PSP5/P1B): RD5 u vo ra s, PSP5 cng d liu song song ph thuc, P1B u ra c tng cng CCP1. Chn 29(RD6/PSP6/P1C): RD6 u vo ra s, PSP6 cng d liu song song ph thuc, P1C u ra c tng cng CCP1. Chn 30(RD7/PSP7/P1D): RD7 u vo ra s, PSP7 cng d liu song song ph thuc, P1D u ra c tng cng CCP1. Cc chn cng Port E Chn 8(RE0/ RD /AN5): RE0 u vo ra s, RD u vo iu khin c cho cng PSP, AN5 u vo tng t Input5. Chn 9(RE1/ WR /AN6): RE1 u vo ra s, WR u vo iu khin vit d liu cng PSP, AN6 u vo tng t Input6. Chn 10(RE2/ CS /AN7): RE2 u vo ra s, CS iu khin chn Chip cho cng PSP, AN7 u vo tng t Input7. - u RE3 nm chn 1 Cc chn khc Chn 12,31(VSS): ni t chun cho I/O v logic. Chn 11,32(VDD): cungcp ngun dng cho I/O v logic. Loi 44 chn c thm mt s chn ph khc khi cn thit ta c th d dng tra trong DataSheet. Chi tit hn chng ta c th thy qua s khi ca Pic18F4420/4520 trong ti liu do microchip cung cp s c hon ton y thng tin. c im cu to.
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Vi iu khin Pic 1.2.1. T chc b nh (Memory Organization)

Dng Pic18Fxxxx c t chc b nh thnh ba loi: B nh chng trnh (Program Memory). B n d liu RAM (Data RAM). B nh d liu EEPROM (Data EEPROM ). T chc cc b nh chng trnh theo kin trc Harvard c sp xp theo s :
Hnh 1.3: T chc b nh chng trnh T chc b nh chng trnh(Program Memory Organization) Dng vi iu khin Pic18xxxx l thit b vi 21bit b m chng trinh PC (Program counter) c th qun l 2Mbyte b nh chng trnh. Vi Pic18F4520 c 32Kbytes b nh Flash c th lu tr ln ti 16,384 cu lnh n, dng Pic ny c hai vector ngt: Reset vector c a ch 0000h v Interrupt vector a ch 0008h v 0018h. B m chng trnh PC (Program Counter) PC c rng 21 bits phn chia trn 3 thanh ghi 8 bits: thanh ghi PCL, thanh ghi PCH, thanh ghi PCU. D liu bytes a ch ca PC c lu trong b nh chng trnh. Khi s dung cn lu ti cu trc lnh c lm thay i gi tr PC hay khng.
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Vi iu khin Pic
Khi phc da ch ngn xp (RETURN ADDRESS STACK) y ta c th cho php lu tr gi 31 chng trnh v cc ngt xy ra. Trong thc thi ngn xp cu trc lnh CALL v RCALL l c quan tm. S ngn xp dng:
Hnh 1.4: S a ch ngn xp

Trong vng ngn xp ny cn quan tm ti:: - Top-of-Stack Access - Return Stack Pointer (STKPTR) - Stack Full and Underflow Resets Khi chng ta lp trnh cn thit chnh xc khi gi chng trnh qua lnh Call v Rcall nn khi tc ng cn quan tm s thay i cc ngn xp cng nh qun l con tr (Pointer). Ta c th dng cc lnh Push v Pop iu khin con tr. Mt quan tm khc na l Stack Pointer Register (STKPTR) - thanh ghi con tr ngn xp:
Bit 7 (STKFUL): bit c bo ngn xp y Gi tri 1 c ngha l ngn xp y hoc trn Gi tr 0 th ngn xp vn cha b y hoc trn Bit 6 (STKUNF): bit c bo trn di Gi tr 1: xy ra trn di Gi tr 0: khng c trn di Bit 5 (Unimplementad): mang gi tr 0 Bit 4-0 (SP<4:0>:Cc bit xc nh con tr ngn xp Chng ta c th xa bit 6 v bit 7 nh phn mm hoc bi mt POR FAST REGISTER STACK Nhm thanh ghi ny gm c cc thanh ghi: Status, WREG, BSR gip vic khi phc nhanh lu chn cho cc ngt. V d mt chng trnh:
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Vi iu khin Pic
Vic qun l tt b nh chng trnh s gip ta thc hin chng trnh tt hn cng nh ti u cu lnh. Chu k lnh Pic 18Fxxx Bt k mt vi iu khin Pic no khi nhn mt xung t bn trong hay bn ngoi u x l theo mt chu k gm 4 bc. H 18Fxxxx cng vy chu k lnh c x l song song (Pipelining) qua 4 bc Q1,Q2,Q3,Q4.
Hnh 1.5: Clock/Instruction Cycle
Hnh 1.6 Instruction Pipeline Flow
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Vi iu khin Pic
Hnh 1.7 Instruction In Program Memory T chc d liu b nh(Data Memory Organization) Pic18Fxxxx l h Statis Ram mi thanh ghi b nh d liu c 12 bit a ch, cho php truy nhp ti 4096 bytes d liu b nh. Khng gian b nh chia lm 16 bank gm 256 byte mi bank Pic18F4520 nh s pha sau. B nh d liu bao gm : thanh ghi chc nng c bit (SFRs), thanh ghi mc ch chung (GPRs). Thanh ghi SFR dng iu khin trng thi v chc nng thit b ngoi vi, trong khi thanh ghi GPR dng lu tr hoc lm vng nh tm thi ang hot ng ca cc ng dng.
Hnh 1.8 S cu trc b nh d liu Pic18F4520 Theo cu trc lnh v kin trc dng Pic18Fxxxx cho php cc bank hot ng ng thi. Ton b b nh d liu c th cho php truy nhp c hng, v hng hay a ch c ch s, c im chung ca cc thanh ghi l cho php x l trong mt chu k
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Vi iu khin Pic
n. Pic 18Fxxxx cung cp mt AccesBank gm 256 byte b nh cho php truy cp nhanh ti SFRs v phn Bank0 ca GPR nu khng s dng BSR. Chi tit cc bank thanh ghi v chc nng ta c th theo di k hn trong dataSheet Sau y l mt s cu trc cc thanh ghi in hnh:
Hnh 1.9 S cu trc thanh ghi ca Pic18F4520 Thanh ghi Status (Status Register)
Bit 7-5 (Unimplemented): mang gi tr 0 Bit 4 (N): bit xc nh du(Negative bit) dc s dng cho s c du(s b 2), n c xc dnh khi kt qu mang du m(ALU MSB=1) Gi tr 1: kt qu l m Gi tr 0: kt qu l dng Bit 3 (OV): bt bo trn(overflow bit) c s dng cho s c du (s b 2), n xc nh bo trn cho di 7 bit ci l nguyn nhn thayi trng thi v du bit 7. Gi tr 1: xy ra trn Gi tr 0 : khng xy ra trn Bit 2 (Z): bt khng (Zero bit) Gi tr 1: kt qu cc php ton s hc v logic l bng 0 Gi tr 0 : kt qu cc php ton khc 0 Bit 1 (DC): Digit Carry/ borrow bit. S dng cho cc lnh ADDWF, ADDLW, Gi tr 1: xy ra vic thao tc 4 bit thp.
SUBLW v SUBWF
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Vi iu khin Pic
Gi tr 0 : khng xy ra vic thao tc 4 bit thp. Bit 1 (DC): Carry/ borrow bit. S dng cho cc lnh ADDWF, ADDLW, Gi tr 1: xy ra vic thao tc bit quan trng. Gi tr 0 : khng xy ra vic thao tc vi bit quan trng. Cc kiu a ch d liu(Data Addressing Modes) C bn kiu ch nh sau: a ch c sn (Inherent addressing) a ch bng ch (Literal addressing) a ch c hng (Direct addressing) a ch v hng (Indirect addressing) Cc ch ny c ch a ch theo hng khi s dng c lin h thanh ghi FSR
SUBLW v SUBWF
B nh d liu v cu trc lnh c m rng(Data Memory and the Extended Instruction Set) Pic 18 c kh nng cho ta m rng cu trc lnh nh Access Bank v cho ta gp di lnh khi la chon a ch khng gian b nh. N c th mang li nhiu ngha v kch thc b nh. Vi ch ny ch yu thay i cu trc kiu a ch c hng v v hng cn hai ch a ch bng ch v c sn l khng thay i, c th ta c th theo i nh hnh v
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Vi iu khin Pic B nh chng trnh Flash (Flash Program Memory)

c im b nh Flash l c kh nng c vit v xo trong thi gian hot ng da vo khong in p VDD mt cch d dng. Ti mt thi im chng ta c th thc hin c mt byte, Vit mt khi 32 byte, xo mt khi 64 byte. Hot ng xo mt khi ln khng c kh nng t m ngi s dng. Khi ta xo hoc vit vo b nh chng trnh s ngng ch dn cho khi hon thnh hot ng.V khng c s truy nhp trong sut qu trnh vit hoc xo d liu. S c mt b m thi gian khi c hot ng xo hoc vit. Sau y chng ta s tm hiu mt s thuc tnh c bn khi thao tc b nh Flash. Table Reads and Table Writes Theo th t c v vit d liu cho php vi x l di chuyn cc byte gia khng gian b nh chng trnh v d liu trong RAM thng qua: Table Reads and Table Writes. Nhng do b nh chng trnh c rng 16bit cn b nh Ram ch l 8 bit nn di chuyn d liu gia chng cn thanh ghi 8bit (TABLAT): Bng c hot ng ly ra d liu t b nh chng trnh a chng ti khong nh ca RAM.:
Bng vit hot ng lu tr d liu t b nh d liu htng qua gi trong b nh chng trnh:
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Vi iu khin Pic
Control Registers C bn thanh ghi iu khin: EECON1 register EECON2 register TABLAT (TABLE LATCH ) register TBLPTR(TABLE POINTER) registers Ta a ra thanh ghi EECON1 v d:
Bit 7 (EEPGD): bit la chn b nh Flash v b nh d liu EEPROM Gi tr 1:Cng vo cho b nh Flash. Gi tr 0: Cng vo cho b nh EEPROM. Bit 6 (CFGS): bit la chn b nh Flash , b nh d liu EEPROM hoc thanh ghi cu hnh (Configuration register): Gi tr 1:Cng vo cho thanh ghi cu hnh. Gi tr 0: Cng vo cho b nh EEPROM hoc b nh Flash . Bit 5 (Unimplemented): mang gi tr 0 Bit 4 (FREE): bit cho php xa b nh Flash theo hng: Gi tr 1: Xo b nh chng trnh theo a ch hng bi TBLPTR trn c s lnh WR k tip. Gi tr 0: Ch thc hin hot ng vit. Bit 3 (WRERR): bit c bo li trren b nh Flash v b nh d liu EEPROM. Gi tr 1: Mt hot ng vit kt thc sm. Gi tr 0: Hot ng vit c hon tt. Bit 2 (WREN): bt cho php hot ng vit trn b nh Flash v b nh d liu EEPROM. Gi tr 1: Cho php vit theo chu k trn b nh Flash v b nh d liu EEPROM. Gi tr 1: Ngn cn vit theo chu k trn b nh Flash v b nh d liu EEPROM. Bit 1 (WR): bit iu khin hot ng vit. Gi tr 1: Bt u chu k xa/vit d liu trn b nh d liu EEPROM hoc b nh chng trnh. Gi tr 0: Chu k vit trn b nh EEPROM hon tt. Bit 0 (RD): Bit iu khin hot ng c. Gi tr 1: Bt u hot ng c d liu EEPROM. Gi tr 0: Cha bt u hot ng c d liu. Ta c th xc nh hoc iu khin cc bit 0 v bit 1 nh phn mm.
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Vi iu khin Pic
Reading the Flash Program Memory Khi c d liu chng ta s dng cu trc lnh TBLRD ly d liu t b nh ti b nh RAM. Hot ng theo hnh sau:
Erasing Flash Program Memory Vic thc hin xo d liu c th thng qua ngi lp trnh hoc thng qua iu khin ISCP. Chng ta c th xo khi nh nht 32 t ti 64 byte, c kh nng cho ta xo khi ln nhng thng qua cng iu khin. Hot ng ny c h tr t thanh ghi EECON1. Writing to Flash Program Memory Ta c th thc hin vit d liu t bn trong ti d liu cn thit ti b nh. kh nng vit c th t 16 t ti 32 byte v thng qua bng vit vi h tr khong 32 thanh ghi cho lp trnh.
Flash Program Operation During Code Protection
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Vi iu khin Pic B nh d liu EEPROM (Data EEPROM Memory)

D liu EEPROM l mt mng b nh bt bin c phn chia t b nh RAM v b nh chng trnh, dc dng lu tr lu di d liu chng trnh. N coi l nh x c hng ti khng gian b nh chng trnh nhng li l a ch v hng thong qua thanh ghi SFRs. B nh EEPROM c kh nng c v vit trong qu trnh hot ng thng qua khong in p VDD. Nm thanh ghi SFRs c s dng c v vit d liu b nh EEPROM gm: EECON1, EECON2, EEDATA, EEADR. Khi c giao din ti khi d liu b nh th EEDATA nhim v gi d liu 8bit c vit cn thanh ghi EEADR l cht a ch EEPROM cho php truy nhp.. Mt byte c vit ngay lp tc xo tai v tr v vit d liu mi, qu trnh ny c iu khin bi b m thi gian on-Chip. Thanh ghi EEADR (EEADR Register) Chc nng thanh ghi ny dng d a a ch d liu trong hot ng c/vit. Thanh ghi ny rng 8 bit c kh nng qun l bnh rng 256byte(00h-FFh). EECON1 and EECON2 Registers C hai thanh ghi ny dng iu khin truy nhp d liu EEPROM, hot ng thanh ghi ny hon ton tng t nh cc thanh gi iu khin truy nhp b nh chng trnh nhng y l iu khin truy nhp d liu EEPROM. Chng c cu trc tng t nhau, cu trc thanh ghi EECON1 chng ta c phn b nh Flash. Reading the Data EEPROM Memory Qu trnh c d liu nh thanh ghi EEDATA, thanh ghi ny s gi gi tr cn c ti khi n c vit bi ngi s dng. Nhng c dc d liu ngi s dng phi vit d liu ln thanh ghi EEADR, xo bit iu khin EEPGD Thuc thanh gi EECON1<7>, sau d set bit iu khin EECON<0>. Writing to the Data EEPROM Memory Qu trnh vit d liu vo b nh EEPROM trc tin l np a ch vo thanh ghi EEADR, sau vit d liu ln thanh ghi EEDATA. Kim tra li qu trnh vit d liu (Write Verify) Hot ng ny ph thuc vo tng ng dng v n m bo ta c bi lp trnh tt. Operation During Code-Protect Protection Against Spurious Write Using the Data EEPROM
1.2.2. 8 x 8 HARDWARE MULTIPLIER

Tt c cc thit b Pic 18Fxxxx u c b nhn phn cng ging nh mt phn ALU. B nhn c hnh thc nhn khng u v cho kt qu 16 bit lu tr trong thanh ghi kt qu PRODH:PRODL. Hot ng b nhn khng nh hng g ti cc c ca thanh ghi trng thi STATUS. Hot ng b nhn cho php trong mt chu k lnh gp phn nng cao tc tnh ton v gim bt kch thc thut ton gip Pic18 s dng nhiu ng dng hn trong phn cng v phn mm.
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Vi iu khin Pic 1.2.3. Ngt (Interrupts)

Dng Pic18Fxxxx ny cung cp cho ngi s dng nhiu ngun ngt v mt c trng u tin ngt l hu ht cc ngt u c c mc u tin cao v thp. Ngt u tin cao a ch 0008h, ngt u tin thp a ch 0018h. Nhng ngt u tin cao thc hin ngt cn cc ngt u tin thp phi c gi trong chng trnh. C tt c mi thanh ghi s dng d iu khin hot dng ngt gm: RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 Ni chung cc ngun ngt c 3 bit d iu khin hot ng ngt; Flag bit : xc nh s kin ngt xy ra. Enable bit : Cho php thc hin ngt ti a ch Flag bit tr ti. Priority bit : chn mc u tin cho ngt Ngoi ra cc thanh ghi chc nng c th phc v cho cc ngt th c cc bit ring vi cc chc nng gip ngi lp trnh c th qun l v s dng cc ngt hiu qu. S trng thi Logic cc ngt c th m t :
Hnh 1.10 Pic 18 Interrup logic
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By gi chng ta s tm hiu cu trc mt s thanh ghi in hnh s dng phc v hot ng ngt: INTCON Registers Thanh ghi ny cho php dc ghi cc ngt v cho php u tin ngt c c Flag bit. INTCON 1 Registers
bit 7 (GIE/GIEH): bit cho php ngt ton cc. Khi IPEN = 0: Gi tr 1: Cho php ton b hot ng ngt. Gi tr 0: Khng thc hin ton b hot ng ngt. Khi IPEN = 1: Gi tr 1: Cho php ton b hot ng ngt vi mc u tin cao. Gi tr 0: Khng thc hin ton b hot ng ngt t ngoi vi. bit 6 (PEIE/GIEL): bit cho php cc ngt t ngoi vi thc hin. Khi IPEN = 0: Gi tr 1: Cho php ton b hot ng ngt t ngoi vi. Gi tr 0: Khng thc hin ton b hot ng ngt t ngoi vi. Khi IPEN = 1: Gi tr 1: Cho php ton b hot ng ngt t ngoi vi vi mc u tin thp. Gi tr 0: Khng thc hin ton b hot ng ngt t ngoi vi vi mc u tin thp. bit 5 (TMR0IE): bit cho php ngt bo trn TMR0 Gi tr 1: Cho php ngt bo trn TMR0. Gi tr 0: Khng cho php ngt bo trn TMR0. bit 4 (INT0IE): bit cho php ngt ngoi INT0 Gi tr 1: Cho php ngt ngoi INT0 . Gi tr 0: Khng cho php ngt ngoi INT0 bit 3 (RBIE): bit cho php thay i RB Port Gi tr 1: Cho php ngt thay i RB Port . Gi tr 0: Khng cho php ngt thay i RB Port . bit 2 (TMR0IF): bit c ngt bo trnTMR0 Gi tr 1: thanh ghi TMR0 xy ra trn (c th xo bng phn mm). Gi tr 0: Khng xy ra trn thanh ghi TMR0. bit 1 (INT0IF): bit c bo ngt ngoi INT0
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Gi tr 1: xy ra ngt ngoi INT0 (c th xo bng phn mm). Gi tr 0: Khng xy ra ngt ngoi INT0. bit 0 (RBIF): bit c bo thay i RB Port Gi tr 1: c thay i trng thi ca chn mang gi tr nh nht ca RB<7:4>(c th xo bng phn mm). Gi tr 0: Khng c thay trng thi cc chn RB<7:4>. INTCON 2 Registers
bit 7 ( RBPU ): bit cho php ko ln cng PORT B. Gi tr 1: ton b PORT B khng c ko ln. Gi tr 0: Cho php ton b PORT B c ko ln bi mt gi tr cng cht ring l.. bit 6 (INTEDG0): bit la chn bin ngt ngoi s 0. Gi tr 1: tng bin ngt. Gi tr 0: gim bin ngt bit 5 (INTEDG1): bit la chn bin ngt ngoi s 1. Gi tr 1: tng bin ngt. Gi tr 0: gim bin ngt bit 4 (INTEDG2): bit la chn bin ngt ngoi s 2. Gi tr 1: tng bin ngt. Gi tr 0: gim bin ngt bit 3 (Unimplemented): mang gi tr 0 bit 2 (TMR0IP): bit u tin ngt bo trn TMR0 Gi tr 1: mc u tin cao Gi tr 0: mc u tin thp. bit 1 (Unimplemented): mang gi tr 0 bit 0 (RBIP): bit u tin ngt thay i RB Port Gi tr 1: mc u tin cao Gi tr 0: mc u tin thp. INTCON 3 Registers
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bit 7 (INT2IP): bit u tin ngt ngoi INT2. Gi tr 1: mc u tin cao Gi tr 0: mc u tin thp. bit 6 (INT1IP): bit u tin ngt ngoi INT1. Gi tr 1: mc u tin cao Gi tr 0: mc u tin thp. bit 5 (Unimplemented): mang gi tr 0 bit 4 (INT2IE): bit cho php ngt ngoi INT 2. Gi tr 1: Cho php ngt ngoi INT2 thc hin. Gi tr 0: Khng cho php ngt ngoi INT2 thc hin. bit 3 (INT1IE): bit cho php ngt ngoi INT 1. Gi tr 1: Cho php ngt ngoi INT1 thc hin. Gi tr 0: Khng cho php ngt ngoi INT1 thc hin. bit 2 (Unimplemented): mang gi tr 0 bit 1 (INT2IF): bit c bo ngt ngoi INT2 Gi tr 1: xy ra ngt ngoi INT2 (c th xo bng phn mm). Gi tr 0: Khng xy ra ngt ngoi INT2. bit 0 (INT1IF): bit c bo ngt ngoi INT1 Gi tr 1: xy ra ngt ngoi INT1 (c th xo bng phn mm). Gi tr 0: Khng xy ra ngt ngoi INT1. PIR Registers Cc thanh ghi ny xc nh c ngt cho thit b ngoi vi. Cng lc c hai thanh ghi phc v cho hai thit b ngoi vi l PIR1 v PIR2. PIR1 Registers
bit 7 (PSPIF): bit c thc hin ngt khi c/vit cng song song ph thuc (Parallel Slave Port) Gi tr 1: hot ng c hoc vit c th da ti(c th xo bng phn mm) Gi tr 0: Khng c hot dng c vit. bit 6 (ADIF): A/D Converter Interrupt Flag bit Gi tr 1: Mt hot ng chuyn i A/D hon tt (c th xo bi phn mm). Gi tr 0 : Hot ng chuyn i A/D cha hon tt. bit 5 (RCIF): bit c bo ngt nhn EUSART .
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Gi tr 1:EUSART nhn t b m v RCREG l y(c xo khi RCREG c c) Gi tr 0: EUSART nhn t b m l rng. bit 4 (TXIF): bit c bo ngt vic truyn t EUSART Gi tr 1:EUSART truyn ti b m v TXREG l y(c xo khi TXREG c vit) Gi tr 0: EUSART nhn t b m l rng. bit 3 ( SSPIF): bit c bo ngt cng Master Synchronous Serial Port Gi tr 1:Hot ng truyn/nhn hon tt (c th xa bi phn mm) Gi tr 0:ang i truyn nhn. bit 2 (CCP1IF): bit c bo ngt CCP1 La chn kiu Capture : Gi tr 1: thanh ghi TMR1 theo kiu capture xy ra (phi xo bi phn mm) Gi tr 0: Khng xy ra kiu capture trn vi thanh ghi TMR1 . La chn kiu Compare : Gi tr 1: thanh ghi TMR1 theo kiu compare xy ra (phi xo bi phn mm) Gi tr 0: Khng xy ra kiu compare trn vi thanh ghi TMR1 . La chn kiu PWM: khng s dng kiu la chon ny. bit 1 (TMR2IF):bit c bo ngt lin ktTMR2 ti PR2 Gi tr 1:Xy ra lin kt TMR2 ti PR2 (phi c xo bi phn mm) Gi tr 0:Khng xy ra lin kt TMR2 ti PR2. bit 0 (TMR1IF): bit c bo ngt trnTMR1 Gi tr 1: thanh ghi TMR1 trn (phi c xo bi phn mm) Gi tr 0: Khng c trn trn thanh ghiTMR1. PIR 2 Register
bit 7 (OSCFIF): bit c bo ngt khi c li b dao ng Oscillator Gi tr 1:thit b b dao ng li, xung u vo tc ng thay i ti INTOSC (phi c xa bi phn mm). Gi tr 0:Xung thit b hot ng. bit 6 (CMIF): Bit c bo ngt b so snh. Gi tr 1: u vo b so snh l thay i (phi xo bi phn mm). Gi tr 0: Khng c thay i u vo b so snh. bit 5 (Unimplemented): mang gi tr 0
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bit 4 (EEIF):bit c bo ngt hot ng vit d liu b nh EEPROM/Flash Gi tr 1: Hot ng vit hon tt (phi xo bi phn mm). Gi tr 0: Hot ng vit cha hon tt hoc cha bt u. bit 3 (BCLIF): bit c bo ngt c xung t Bus Gi tr 1: xy ra xung t trn Bus (phi xo bi phn mm) Gi tr 0: Khng xy ra xung t Bus. bit 2 (HLVDIF): Bit c bo ngt c d in p (High/Low-Voltage) Gi tr 1: iu kin xy ra in p mc cao/thp (hng xavs ng bi VDIRMAG bit, HLVDCON<7>) Gi tr 0: Khng xy ra vi mc in p cao/thp. bit 1 (TMR3IF): bit c bo trn TMR3 Gi tr 1: C trn trn thanh ghi TMR3 (phi xa bi phn mm) Gi tr 0: Khng c trn thanh ghi TMR3. bit 0 (CCP2IF): bit c bo ngt trn CCP2 La chn kiu Capture : Gi tr 1: thanh ghi TMR1 theo kiu capture xy ra (phi xo bi phn mm) Gi tr 0: Khng xy ra kiu capture trn vi thanh ghi TMR1 . La chn kiu Compare : Gi tr 1: thanh ghi TMR1 theo kiu compare xy ra (phi xo bi phn mm) Gi tr 0: Khng xy ra kiu compare trn vi thanh ghi TMR1 . La chn kiu PWM: khng s dng kiu la chon ny. PIE Registers Ging nh cc thanh ghi PIR nhng thanh ghi PIE dng cho php ngt thit b ngoi vi v cng gm hai thanh ghi PIE1 v PIE2. PIE1 Registers
bit 7 (PSPIE): bit cho php ngt khi c/vit qua cng song song ph thuc Gi tr 1:cho php ngt khi c/vit qua cng sng song ph thuc Gi tr 0:khng cho php ngt khi c/vit qua cng sng song ph thuc bit 6 (ADIE): Bit cho php ngt khi c chuyn i A/D Gi tr 1: cho php ngt khi c chuyn i A/D Gi tr 0: Khng cho php ngt khi c chuyn i A/D bit 5 (RCIE): Bit cho php ngt khi USART nhn Gi tr 1: cho php ngt khi EUSART nhn Gi tr 0: Khng cho php ngt khi EUSART nhn bit 4 (TXIE):Bit cho php ngt khi EUSART truyn
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Gi tr 1: cho php ngt khi EUSART truyn Gi tr 0: Khng cho php ngt khi EUSART truyn bit 3 (SSPIE): bit cho php ngt khi giao tip cng Master Synchronous Gi tr 1: cho php ngt khi giao tip cng Master Synchronous Gi tr 0: Khng cho php ngt khi giao tip cng Master Synchronous. bit 2 (CCP1IE): Bit cho php ngt CCP1 Gi tr 1: cho php ngt CCP1 Gi tr 0: Khng cho php ngt CCP1 . bit 1 (TMR2IE): bit cho php ngt khi c lin kt TMR2 ti PR2. Gi tr 1: cho php ngt khi c lin kt TMR2 ti PR2. Gi tr 0: Khng cho php ngt khi c lin kt TMR2 ti PR2. bit 0 (TMR1IE): bit cho php ngt khi c trn TMR1 Gi tr 1: cho php ngt khi c trn TMR1 Gi tr 0: Khng cho php ngt khi c trn TMR1 PIE2 Registers
bit 7 (OSCFIE): bit cho php ngt khi c li b dao ng Oscillator Gi tr 1:cho php Gi tr 0:Khng cho php bit 6 (CMIE): Bit cho php bo ngt b so snh. Gi tr 1: cho php . Gi tr 0: Khng cho php . bit 5 (Unimplemented): mang gi tr 0 bit 4 (EEIE):bit cho php bo ngt hot ng vit d liu b nh EEPROM/Flash Gi tr 1: cho php Gi tr 0: Khng cho php bit 3 (BCLIE): bit cho php bo ngt c xung t Bus Gi tr 1: cho php Gi tr 0: Khng cho php. bit 2 (HLVDIE): Bit cho php bo ngt c d in p (High/Low-Voltage) Gi tr 1: cho php. Gi tr 0: Khng cho php. bit 1 (TMR3IE): bit cho php bo trn TMR3 Gi tr 1: cho php. Gi tr 0: Khng cho php. bit 0 (CCP2IE): bit cho php bo ngt trn CCP2 Gi tr 1: cho php. Gi tr 0: Khng cho php.
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IPR Registers Ging nh cc thanh ghi PIR,PIE phuc v hot ng ngt, thanh ghi IPR dng xc nh gi tr u tin cho php ngt thit b ngoi vi v cng gm hai thanh ghi IPR1 v IPR2. IPR1 Registers
bit 7 (PSPIP): bit u tin ngt khi c/vit qua cng sng song ph thuc Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 6 (ADIP): Bit u tin ngt khi c chuyn i A/D Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 5 (RCIE): Bit cho php ngt khi USART nhn Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 4 (TXIP):Bit u tin ngt khi EUSART truyn Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 3 (SSPIP): bit u tin ngt khi giao tip cng Master Synchronous Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 2 (CCP1IP): Bit u tin ngt CCP1 Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 1 (TMR2IP): bit u tin ngt khi c lin kt TMR2 ti PR2. Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 0 (TMR1IP): bit u tin ngt khi c trn TMR1 Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. IPR2 Registers
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bit 7 (OSCFIP): bit u tin ngt khi c li b dao ng Oscillator Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 6 (CMIP): Bit u tin bo ngt b so snh. Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 5 (Unimplemented): mang gi tr 0 bit 4 (EEIP):bit u tin bo ngt hot ng vit d liu b nh EEPROM/Flash Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 3 (BCLIP): bit u tin bo ngt c xung t Bus Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 2 (HLVDIP): Bit u tin bo ngt c d in p (High/Low-Voltage) Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 1 (TMR3IP): bit u tin bo trn TMR3 Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. bit 0 (CCP2IP): bit u tin bo ngt trn CCP2 Gi tr 1:mc u tin cao. Gi tr 0:mc u tin thp. RCON Register Thanh ghi ny c bit c (Flag bit) s dng xc nh ngyn nhn Reset v khi dng cc trng thi Idle v Sleep. Thanh ghi ny cha bit IPEN cho php mc u tin ngt.
bit 7 (IPEN): bit cho php u tin ngt Gi tr 1:cho php mc u tin ngt Gi tr 0: khng cho php mc u tin ngt bit 6 (SBOREN): Bit cho php lp trnh phn mm BOR Vi BOREN1:BOREN0 = 01: Gi tr 1 : Cho php BOR Gi tr 0 : Khng cho php BOR Vi BOREN1:BOREN0 = 00,10or11 khng cho php v mang gi tr 0 bit 5 (Unimplemented): mang gi tr 0 bit 4 (RI): bit c ca cu trc lnh RESET Gi tr 1:Khng thc hin cu trc lnh RESET Gi tr 0: khng thc hin cu trc lnh RESET RESET thit b.
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bit 3 ( TO ):Bit c bo b nh thi Watchdog Time-out Gi tr 1:Cp ngun in bi cu trc lnh CLRWDT hoc SLEEP. Gi tr 0: Xy ra trn b nh thi WDT time-out . bit 2 (PD): Bit c bo d mt ngun Gi tr 1:Cp ngun in bi cu trc lnh CLRWDT . Gi tr 0: Thc hin thit lp bi cu trc lnh SLEEP. bit 1 (POR): bit d RESET trng thi ngun khi chy Gi tr 1:Khng xy ra RESET ngun (c thit lp bi vi chng trnh) . Gi tr 0:Xy ra RESET ngun(cn phi thit lp bi phn mm sau khi RESET xy ra) bit 0 (BOR): Bit cho bit trng thi RESETyu ngun Gi tr 1:Khng xy ra RESET yu ngun (c thit lp bi vi chng trnh) . Gi tr 0:Xy ra RESET yu ngun(cn phi thit lp bi phn mm sau khi RESET xy ra) Ngoi ra Pic18 cng cung cp cho ta cc cng c phc v ngt khc nh : INTx Pin Interrupts TMR0 Interrupt PORTB Interrupt-on-Change Context Saving During Interrupts
1.2.4. Cng vo ra (I/O Port)

Nh tm hiu cu trc chn Pic18F4520 loi PDIP chng ta bit c tt c 5 cng vo ra PortA, PortB, Port C, PortD, PortE. Vic s dng la chn cc cng vo ra ny ph thuc nhiu vo cc ng dng v thit b ngoi vi. Mi cng ny u gm ba thanh ghi hot ng chnh l: Thanh ghi TRIS (thanh ghi d liu c hng) Thanhghi ca chnh cc cng (PORT register) Thanh ghi LAT(thanh ghi cht d liu) PORTA, TRISA and LATA Registers Port A l cng vo ra hai hng 8 bit. Thanh ghi TRISA dng iu khin d liu c hng. Khi bit TRISA(=1) th tng ng cc chn Port A l u vo, ngc li (=0) tng ng cc chn Port A l u ra.. Thanh ghi LATA kim sot hot ng c vit hiu chnh ca Port A. C th chc nng cc chn ca cng ny ni chi tit cu trc chn ca vi iu khin. PORTB, TRISB and LATB Registers PORTC, TRISC and LATC Registers PORTD, TRISD and LATD Registers V c bn Port B, PortC, PortD c nguyn tc hot ng ging PortA. Cn cc chc nng c bn khc trong s chn phn cng gii thch c th. Ring PortD c thm s c bit do n c th chuyn tip thnh cng song song ph thuc(PSP). PORTE, TRISE and LATE Registers Port E c rng 4 bit cc chn chng ta tm hiu trn. Hot ng thanh ghi TRISE cng tngt nh cc thanh ghi c cng chc nng cc cng khc.
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bit 7 (IBF): bit bo trng thi u vo b m y. Gi tr 1:Mt t c nhn v ang ch CPU c. Gi tr 0: Khng nhn mt t no. bit 6 (OBF): bit bo trng thi u ra b m y Gi tr 1:u ra b m vn gi d vit mt t trc .. Gi tr 0: u ra b im c. bit 5 (IBOV): bit la chn kim tra d trn u vo b m Gi tr 1:xy ra hot ng vit khi m mt t trc b m cha c c(cn xo biphn mm) Gi tr 0: Khng xy ra trn. bit 4 (PSPMODE): bit la chon kiu cho cng PSP Gi tr 1:hot ng cng PSP Gi tr 0: hot ng nh cng vo ra thng thng. bit 3 (Unimplemented): mang gi tr 0 bit 2 (TRISE2): bt iu khin hng cho RE2 Gi tr 1:u vo Gi tr 0: u ra bit 1 (TRISE1): bt iu khin hng cho RE1 Gi tr 1:u vo Gi tr 0: u ra bit 0 (TRISE0): bt iu khin hng cho RE0 Gi tr 1:u vo Gi tr 0: u ra Parallel Slave Port(PSP) y c th coi l s thm chc nng ca cc cng vo ra ni chung. PSP c chuyn i t cc chn PortD. PSP c iu khin bi 4 bit cao ca thanh ghi TRISE. Trong TRISE<4>-PSPMODE coi l bt diu khin cng. PSP cng c tng cng modul CCP n c th l giao din c hng ti mt vi iu khin 8 bit.
1.2.5. B nh thi (Timer)

Timer0 Module Modle ny c coi c nhng c im sau: C th la chon phn mm nh mt b nh thi hoc b m c th l 8 bit hoc 16 bit. C kh nng nh thanh ghi c vit Ring loi 8 bit c th coi l b m lp trnh bng phn mm Kh nng la chon xung ngun(c bn trong v bn ngoi)
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L chon gii hn cho xung t bn ngoi Ngt - m - trn c trng cho Timer0 l thanh ghi T0CON
bit 7(TMR0ON): bit iu khin ng m Timer0 Gi tr 1:cho php hot ng Gi tr 0: dng hot ng bit 6 (T08BIT): bit iu khin Timer0 8-Bit/16-Bit Gi tr 1:Timer0 cu hnh nh 8-bit timer/counter Gi tr 0: Timer0 cu hnh nh 16-bit timer/counter bit 5 (T0CS): bit la chn ngun xung cho Timer0 Gi tr 1:truyn trn chn T0CKI Gi tr 0: chu k xung lnh bn trong (CLKO) bit 4 (T0SE): bit la chon gii hn ngun choTimer0 Gi tr 1: truyn trn chn T0CKI thay i t cao-thp. Gi tr 0: truyn trn chn T0CKI thay i t thp-cao. bit 3 (PSA): bit thit lp b m gp trc choTimer0 Gi tr 1: khng thit lp b m gp trc Timer0. Xung du vo Timer0 c chuyn hng bi b m gp trc.. Gi tr 0: thit lp b m gp trc Timer0. Xung du vo Timer0 tr thnh du ra b m gp trc.. bit 2-0 (T0PS<2:0>): bit la chon b m gp trc cho Timer0 111 = 1:256 gi tr b m gp trc 110 = 1:128 gi tr b m gp trc 101 = 1:64 gi tr b m gp trc 100 = 1:32 gi tr b m gp trc 011 = 1:16 gi tr b m gp trc 010 = 1:8 gi tr b m gp trc 001 = 1:4 gi tr b m gp trc 000 = 1:2 gi tr b m gp trc Timer1 module c trng c bn ca b nh thi ny gm: Kh nng la chon bng phn mm ging nh b nh thi 16bit hoc b dm. Kh nng nh thanh ghi c vit c 8bit(TMR1H, TMR1L). Kh nng la chon ngun xung bn trong qua b dao ng Oscillator. Ngt-Trn Reset nh b to s kin dc bit CCP
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C bo trng thi xung thit b Thanh ghi T1CON s dng iu khin Timer1
bit 7 (RD16): bit cho php la chn cc ch c/vit 16-Bit Gi tri 1: cho php thanh ghi c/vit ca Timer1 trong hot ng nh mt s 16 bit. Gi tri 0: cho php thanh ghi c/vit ca Timer1 trong hot ng nh mt s 8 bit. bit 6 (T1RUN): Bit trng thi h thng xung Timer1 Gi tri 1: xung thit b l dn xut t b dao ng Timer1. Gi tri 0: xung thit b l dn xut t mootj ngun khc. bit 5-4 (T1CKPS<1:0>): bit la chn xung u vo b m gp trc cho Timer1 11 = 1:8 Gi tr b m gp trc 10 = 1:4 Gi tr b m gp trc 01 = 1:2 Gi tr b m gp trc 00 = 1:1 Gi tr b m gp trc bit 3 (T1OSCEN): bit cho php b dao ng Timer1 Gi tri 1: Cho php Gi tri 0: Dng b dao ng Timer1 . bit 2 ( T1SYNC ): bit la chn xung ng b u vo bn ngoi cho Timer1 Khi TMR1CS = 1: Gi tri 1: khng phi xung ng b u vo bn ngoi Gi tri 0: xung ng b u vo bn ngoi Khi TMR1CS = 0: bit ny khng s dng v lc ny Timer1 s dng ngun xung t bn trong bit 1 (TMR1CS): bit la chn ngun xung cho Timer1 Gi tri 1: ngun xung t bn ngoi qua chn RC0/T1OSO/T13CKI Gi tri 0: ngun xung t bn trong (Fosc/4) bit 0 (TMR1ON): bit hot ng Timer1 Gi tri 1: Cho php Gi tri 0: Dng Timer1 . Timer1 c th hot ng mt trong 3 ch B nh thi (Timer) B m ng b (Synchronous Counter) B m khng ng b(Asynchronous Counter) Vic s dng Timer1 ph thuc vo vic s dng thanh tho thanh ghi T1CON.
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Timer2 Module c im ni bt Timer2 gm: B nh thi 8bit(TMR2) v thanh ghi ghi Period(PR2) Kh nng c v vit c. Lp trnh phn mm Ngt trn TMR2 nh PR2 Ci t khi xung cho modul MSSP Timer 2 iu khin hot ng da thanh ghi T2CON
bit 7 (Unimplemented): mang gi tr 0 bit 6-3 (T2OUTPS<3:0>): bit la chn u ra Timer2 sau khi dng. 0000 = 1:1 sau khi dng 0001 = 1:2 sau khi dng 1111 = 1:16 sau khi dng bit 2 (TMR2ON): Bit hot dng Timer2 Gi tri 1: Cho php Gi tri 0: Dng Timer1 . bit 1-0 (T2CKPS<1:0>): bit chn xung b m gp trc cho Timer2 00 = b m gp trc 1 01 = b m gp trc 4 1x = b m gp trc 16 Timer 3 Module c im Timer3 bao gm: La chon c hot ng bng phn mm ging nh b m thi gian 16 bit. Kh nng c v vit c ging thanh ghi 8 bit(TMR3H-TMR3L). La chn cc ngun xung c bn trong v ngoi nh b dao ng Ngt- Trn Modul Reset trn CCP (c bit vi kt qu Trigger) Timer 3 iu chnh nh thanh ghi T3CON
bit 7(RD16): (RD16): bit cho php la chn cc ch c/vit 16-Bit Gi tri 1: cho php thanh ghi c/vit ca Timer1 trong hot ng nh mt s 16 bit.
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Gi tri 0: cho php thanh ghi c/vit ca Timer1 trong hot ng nh mt s 8 bit. bit 6,3 (T3CCP<2:1>): bit cho php Timer3 v Timer1 lin kt CCPx modules Gi tri 1x : Timer3 l cu hnh ngun xung capture/compare cho CCP modules Gi tri 01: Timer3 l cu hnh ngun xung capture/compare cho CCP2 modules, Timer1 l cu hnh ngun xung capture/compare cho CCP1 modules Gi tri 00 : Timer1 l cu hnh ngun xung capture/compare cho CCP modules bit 5-4 ((T3CKPS<1:0>): bit la chn xung u vo b m gp trc cho Timer3 11 = 1:8 Gi tr b m gp trc 10 = 1:4 Gi tr b m gp trc 01 = 1:2 Gi tr b m gp trc 00 = 1:1 Gi tr b m gp trc bit 2 ( T3SYNC ): bit iu khin xung ng b u vo bn ngoi cho Timer3 Khi TMR3CS = 1: Gi tri 1: khng phi xung ng b u vo bn ngoi Gi tri 0: xung ng b u vo bn ngoi Khi TMR3CS = 0: bit ny khng s dng v lc ny Timer3 s dng ngun xung t bn trong bit 1 (TMR3CS): bit la chn ngun xung cho Timer3 Gi tri 1: ngun xung t bn ngoi t bb dao ng Timer1 hoc T13CKI Gi tri 0: ngun xung t bn trong (Fosc/4) bit 0 (TMR1ON): bit hot ng Timer1 Gi tri 1: Cho php Gi tri 0: Dng Timer1 .
1.2.6. B truyn nhn d liu ng b (EUSART-Enhanced Universal Synchronous Asynchronous Receiver Transmitter)
Module thu pht ng b v khng ng b (EUSART) l mt trong hai module vo ra ni tip .(Ni chung EUSART cng c bit n nh giao din truyn thng ni tip hoc SCL).EUSART c th cu hnh nh h thng khng ng b song cng m n c th giao tip vi thit b ngoi vi, nh l cc thit b u cui v cc my tnh c nhn. N cng c th c cu hnh nh l ch bn song cng, h thng ng b c th giao tip vi thit b ngoi vi, nh l b A/D hoc D/A, v cc EEPROMs Module thu pht ng b v khng ng b m rng USART c tch hp , bao gm s d tc baud t ng v hiu chnh, t ng nhn bit qu trnh nhn d liu v 12 bit k t ngt truyn. Ph hp vi vic s dng h thng Bus kt ni cc b. Module thu pht ng b v khng ng b EUSART c th c cu hnh theo nhng phng thc sau : Ch d b (song cng) vi: T ng nhn k t
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T ng hiu chnh baud Truyn gin on 12 bit Ch ng b chnh (song cng ton phn) vi xung nhp chn. Ch ng b ph (bn song cng ) vi xung nhp chn Cc chn ca EUSART c t Port C cu hnh cho RC6/TX/CK v RC7/RX/DT nh l mt EUSART. bit SPEN (RCSTA<7>) c t bng ( = 1) bit TRISC<7> c t (= 1) bit TRISC<6> c t (= 1) S hot ng ca module EUSART m rng c iu khin thng qua ba thanh ghi sau: Thanh ghi iu khin v trng thi truyn (TXSTA) Thanh ghi iu khin v trng thi nhn (RCSTA) iu khin tc truyn (BAUDCON).
Thanh ghi iu khin v trng thi truyn
Bit 7 CSRC : bit chn ngun clock Ch khng ng b: Khng dng. Ch ng b: 1= Ch Master (clock c pht bn trong t BRG) 0=Ch Slave (clock t ngun bn ngoi) Bit 6 TX :Bit cho php ch truyn 9 bit 1= Chn truyn 9 bit 0= Chn truyn 8 bit. bit 5 TXEN: Bit cho php truyn 1= Cho php truyn . 0 = Khng cho php truyn. bit 4 SYNC: Bit chn ch EUSART 1 = Ch ng b 0 = Ch khng ng b. bit 3 SENDB: Bit gi k t gin on Ch khng ng b: 1 = Gi k t ngt ng b ln truyn tip theo (c xa bi phn cng khi hon thnh) 0 = K t ngt truyn xong. Ch ng b : Khng dng. bit 2 BRGH: Bit chn tc cao
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Ch khng ng b: 1= Tc cao 0 = Tc thp. Ch ng b: Khng s dng trong ch ny. bit 1 TRMT: Bit trng thi thanh ghi dch TSR. 1 = TSR rng. 0 = TSR y. bit 0 TX9D: D liu ca bit th 9 c th l a ch / d liu hoc a ch. THANH GHI IU KHIN V TRNG THI NHN.
bit 7 SPEN: Bit cho php cng truyn ni tip. 1 = Cho php hot ng (cu hnh RX/DT v TX/CK cc chn ny ging cc chn cng vo ni tip) 0 = Khng cho php (c t khi Reset) bit 6 RX9: Bit cho php nhn 9 bit 1 = Chn ch nhn 9 bit 0 = Chn ch nhn 8 bit bit 5 SREN: Bit cho php nhn ring r. Ch khng ng b: Khng s dng Ch ng b Master: 1 = Cho php nhn ring r. 0 = Khng cho php ring r. Bit ny c xa sau khi qu trnh nhn hon thnh. Ch ng b Slave: Khng dng ch ny. bit 4 CREN: Bit cho php tip tc nhn. Ch khng ng b: 1 = Cho php nhn. 0 = Khng cho php nhn. Ch ng b: 1 = Cho php nhn n khi bit , CREN, c xa (CREN overrides SREN) 0 = Khng cho php tip tc nhn. bit 3 ADDEN: Cho php nh a ch. Ch khng ng b nhn 9 bit (RX9 = 1): 1 = Cho php nh a ch , cho php ngt np d liu vo m khi RSR<8> c t. 0 = Khng cho php nh a ch, tt c cc byte c nhn v bit th 9 c c s dng nh bit chn l. Ch khng ng b nhn 8 bit (RX9 = 0):Khng dng. bit 2 FERR: Bit bo li khung truyn.
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1 = C li(C th c xa khi c thanh ghi RCREG v nhn gi tri byte tip theo) 0 = Khng c li. bit 1 OERR: Bit bo trn. 1 = Li trn (C th c xa khi xa bit CREN) 0 = Khng c li trn. bit 0 RX9D: D liu ca bit th 9. y c th l bit a ch / d liu hoc bit chn l v phi c tnh ton bng phn cng. THANH GHI IU KHIN TC TRUYN
bit 7 ABDOVF: Bit trng thi t ng nhn tc truyn. 1 = xy ra tc ng thanh ghi iu khin tc truyn trng cc ch la chn pht hin trng thi t ng boud (phi xo bi phn mm) 0 = khng xy ra bit 6 RCIDL: Bit bo trng thi nhn 1 = Khng nhn 0 = Xy ra qu trnh nhn bit 5 RXDTP: Bit xc nh mc tch cc d liu nhn Ch khng ng b: 1 = D liu nhn (RX) c o (mc tch cc thp) 0 = D liu nhn (RX) khng c o (mc tch cc cao) Ch ng b: 1 = D liu (DT) c o (mc tch cc thp) 0 = D liu (DT) khng o (mc tch cc cao) bit 4 TXCKP: Bit chn trng thi tch cc d liu v xung nhp. Ch khng ng b: 1 = Trng thi khng truyn (TX) l mc thp. 0 = Trng thi khng truyn (TX) l mc cao. Ch ng b: 1 = Trng thi khng hot ng ca clock (CK) l mc cao. 0 = Trng thi khng hot ng ca clock (CK) l mc thp. bit 3 BRG16: Bit cho php thanh ghi pht tc baud 16 bit. 1 = Cho php thanh ghi pht tc baud 16 bit SPBRGH v SPBRG 0 = Cho php thanh ghi pht tc baud 8 bit ch thanh SPBRG hot ng, SPBRGH khng hot ng. bit 2 Khng xc nh : xem nh bng 0 bit 1 WUE: Bit kch hot. Ch khng ng b: 1 = EUSART s tip tc ly mu trn chn RX ngt c to ra khi gim; bit ny c xa khi phn cng tng ln.
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0 = Chn RX khng c theo di hoc tng ln. Ch ng b: Khng dng cho ch ny. bit 0 ABDEN: Bit cho php t ng d baud. Ch khng ng b: 1 = Cho php o tc baud khi truyn k t tip theo. Cn nhn trng ng b (55h);c xa bi phn cng khi hon thnh. 0 = Khng tc baud hoc hon thnh. Ch ng b: Khng s dng cho ch ny.
B pht tc baud (BRG)

BRG l thanh ghi pht chuyn dng 8 bit hoc 16 bit c cung cp trong ch ng b v khng ng b ca EUSART. BRG c mc nh hot ng ch 8 bit ; t BRG lm vic 16 bit dng thanh ghi (BAUDCON <3>) chn ch 16 bit. The SPBRGH:SPBRG l hai thanh ghi iu khin chu k ca b m thi gian chy t do. Trong ch khng ng b cc bit BRGH (TXSTA<2>) v BRG16 (BAUDCON<3>) cng iu khin tc baud.Trong ch ng b, BRGH khng c dng. Bng 18-1 ch ra cch tnh ton tc baud cho cc ch EUSART khc nhau m n ch p dng cho ch chnh (to xung nhp bn trong). T tc baud yu cu v tn s thch anh Fosc , gi tr nguyn gn nht c tnh cho thanh ghi SPBRGH:SPBRG c th tnh ton da vo kt qu ca bng 18-1. T cc li v tc baud c th xc nh. Mt v d v tnh tc baud trong v d 18-1. Tc mc nh v li gi tr trong cc ch khng ng b khc nhau c ch ra trong bng 18-2. c th l thun li cho vic s dng tc baud cao (BRGH = 1) hoc 16-bit BRG lm gim li tc baud, hoc c th t c tc baud thp khi s dng b dao ng c tn s cao. Ghi li gi tr mi vo thanh ghi SPBRGH:SPBRG bng cch reset BRG (hoc xa). B BRG a ra tc baud mi trc thi gian trn. Hot ng ch qun l ngun. B to xung c s dng pht ra tc baud mong mun. Khi hot ng ch qun l ngun, ngun xung nhp mi c th hot ng cc tn s khc nhau . Bng cch thay i gi tr trong cp thanh ghi SPBRG. V D: D liu trn chn RX c ly mu 3 ln bng cch d trn mch nu mc tch cc trn chn RX l mc cao hay thp.
T NG D TC BAUD Module USART m rng h tr ch d v hiu chnh tc baud t ng. y l c trng hot ng ch c trong ch khng ng b v trong khi bit c xa.
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Tc baud c o lin tc bt u khi bit start c nhn v bit ABDEN c set.Kt qu tnh ton c t ly trung bnh. Trong ch t d tc baud (ABD) , xung nhp ca BRG c o hn na b m BRG thu thp tn hiu RX, tn hiu RX l thi gian BRG. Trong ch ABD, b pht tc baud t bn trong c s dng nh b m thi gian chu k bit ca thu thp chui byte ni tip. Khi m bit ABDEN c set, trng thi my s xa BRG v ch bit start. T ng d tc baud phi nhn byte vi gi tr 55h (ASCII U, n cng l k t ng b LIN bus) tnh ton tn s chnh xc. Php o c ly trn c hai mc cao v thp lm gim tnh i xng ca tn hiu thu thp. Sau khi start bit, SPBRG bt u m, n s m sn ln u tin u tin ca RX. Sau khi 8 bit trn chn RX hoc sn ln th 5 ca RX , mt gi tr tng chu k BRG c t trong cp thanh ghi SPBRGH :SPBRG. Mt khi c sn ln th 5 ,th bit ABDEN s t ng c xa. Nu thanh ghi BGR xy ra trn (trn t FFFFh n 0000h), s kin ny c bo hiu bi trng thi bit ABDOVF (BAUDCON<7>). Bit ny c set bng phn cng khi xy ra trn v c th set hoc xa bng phn mn . Ch ABD vn hot ng khi xy ra s kin trn v bit ABDEN vn c t (Figure 18-2). Trong khi hiu chnh chu k tc baud, gi tri thanh ghi BRG c t bng 1/8 tc xung nhp ban u . Xung nhp BRG c thit lp bi cc bit BRG16 v BRGH . Bit BRG16 c t c lp, c SPBRG v SPBRGH c s dng nh b m 16 bit. Cho php ngi lp trnh l khng c nh trong ch 8 bit bng cch kim tra thanh ghi SPBRGH c bng 00h khng . Trong qu trnh ABD din ra , trng thi b vi x l trong ch EUSRT l trng thi rnh ri(Idle). Bit bo ngt RCIF c t khi pht hin ra sn ln th 5 trn RX. Cn c gi tr trong thanh ghi RCREG xa c ngt RCIF. Gi tr cha trong RCREG c th b i. Ch truyn EUSART v ABD( Auto Baud Rate Detect) Khi xung nhp BRG c gi trong qu trnh ABD ,ch truyn EUSART khng c s dng trong qu trnh ABD hot ng . iu ny c ngha l bt c khi no bit ABDEN c set ,thi TXREG khng th c ghi . Ngi s dng phi m bo rng bit ABDEN khng c set trong qu trnh truyn lin tip. Khi hot ng ca EUSART s khng xc inh.
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Vi iu khin Pic Ch EUSART khng ng b.

Ch khng ng b c chon bng cch xa bit SYNC (TXSTA<4>). Trong ch ny , EUSART s dng khung d liu chun Non-Return-to-Zero (NRZ) (mt bit Start, tm hoc chn bit d liu v mt bit Stop). Thng thng khung d liu c dng ph bin nht l 8 bits. Trn mt chip, mt b pht tc 8-bit/16-bit Baud c s dng to tc chun t b dao ng. Trong EUSART th bit truyn hoc nhn u tin l bit c trng s thp nht. S truyn v nhn trong EUSART l chc nng c lp nhng s dng khung d liu v tc baud l ging nhau. B pht tc baud sinh ra tc xung nhp gp x16 hoc x64 tc thay i bit ph thuc vo bit BRGHv bit BRG16 (TXSTA<2> and BAUDCON<3>). Bit chn l khng c cung cp bi phn cng nhng c th ci t trong phn mm v c lu nh bit d liu th 9. Khi ch khng ng b hot ng, module EUSART bao gm nhng thnh phn quan trng sau: B pht tc baud. Mch to mu. Truyn khng ng b. Nhn khng ng b. T ng kch hot k t ngt ng b. Truyn 12 bit k t ngt. T ng d tc baud. CH TRUYN KHNG NG B EUSART. S khi truyn EUSART trong hnh 18-3. Trung tm ca khi truyn l thanh ghi dch truyn (ni tip) (TSR). Thanh ghi dch cha d liu t thanh ghi m truyn c /ghi TXREG. Thanh ghi TXREG np d liu t phn mm. Thanh ghi dch TSR s khng np d liu cho n khi bit Stop ca ln va np c truyn xong. Ngay khi bit Stop c truyn xong , thanh ghi dch TSR c np gi tr mi t thanh ghi m TXREG (nu c cho php). Khi thanh ghi m truyn TXREG truyn d liu cho thanh ghi dch TSR (xy ra trong TCY), th thanh khi TXREG s trng v c ngt truyn TXIF (PIR1<4>) c set. y l ngt c th cho php hoc khng cho php bng cch set hoc xa bit cho php ngt TXIE (PIE1<4>).bit TXIF will bes c set d cho trng thi ca bit TXIE nh th no; n khng th xa trong phn mm. bit TXIF cng khng th xa ngay lp tc khi d liu ang np trn thanh ghi TXREG, nhng n tr nn hp l trong chu k lnh th hai sau lnh va np. Kim tra bit TXIF ngay sau khi np li gi tri cho thanh ghi TXREG. Trong khi TXIF xc nh trng thi thanh ghi TXREG, mt bit khc l bit TRMT (TXSTA<1>), ch ra trng thi ca thanh ghi dch TSR . bit TRMT l bit ch c c v n c set khi thanh ghi TSR trng rng. Khng c ngt logic t bit ny v vy ngi s dng phi kim tra bit ny xc nh trng thi ca thanh ghi TSR nu n trng. t ch truyn khng ng b c cc bc sau: 1. Khi to cho thanh khi SPBRGH:SPBRG c tc baud tng ng . t hoc xa bit BRGH v bit BRG16, cn thit , t c tc baud mong mun.
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2. Cho php cng khng ng b ni tip bng cch xa bit SYNC, v t bit SPEN. 3. Nu mun c ngt ,set bit cho php TXIE. 4. Nu truyn khung d liu 9 bit, set bit truyn TX9. C th c s dng nh bit a ch hoc d liu. 5. Cho php truyn bng cch set bit TXEN, V bit TXIF cng s c set. 6. Nu chn truyn 9 bit trong khung d liu ,th bit th 9 s c np vo bit TX9D. 7. Np d liu t thanh ghi TXREG (bt u qu trnh truyn). 8. Nu s dng ngt, th phi m bo rng hai bit GIE v PEIE trong thanh ghi INTCON (INTCON<7:6>) c set.
CH NHN KHNG NG B EUSART. S khi nhn l khi trong hnh 18-6. D liu c nhn trn chn RX v c a ti khi khi phc d liu. Khi khi phc d liu thc t c tc dch cao gp 16 ln tc baud, v vy khi nhn hot ng tc bit hoc tn s dao ng . Ch ny thng c s dng trong h thng RS 232. Cc bc thit lp ch nhn khng ng b: 1. Khi to cho thanh ghi SPBRGH:SPBRG c tc baud thch hp. set hoc xa bit BRGH v BRG16 c c tc baud mong mun. 2. Cho php cng khng ng b ni tip bng cch xa bit SYNC, v set bit SPEN. 3. Nu mun c ngt , th set bit cho php ngt RCIE. 4. Nu mun nhn khung d liu 9 bit th set bit RX9. 5. Cho php qu trnh nhn bng cch set bit CREN. 6. C bo nhn RCIFs c set khi qu trnh nhn hon thnh v s xut hin mt ngt nu nh bit cho php ngt nhn RCIE c set. 7. c thanh ghi RCSTA ly bit th 9 (nu nhn l 9 bit) v xc nh li xy ra trong lc nhn. 8. Ly 8 bit d liu cn li bng cch c thanh ghi RCREG register. 9. Nu c li trong qu trnh nhn th xa li bng cch xa bit cho php nhn CREN. 10. Nu s dng ngt th phi m bo rng cc bit GIEv PEIE trong thanh ghi INTCON (INTCON<7:6>) phi c set.
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THIT LP CH 9 BIT D A CH. Ch ny thng c s dng trong h thng RS-485 . Thit lp cho ch nhn khng ng b c d a ch: 1. Khi to cho thanh ghi SPBRGH:SPBRG c tc baud thch hp. set hoc xa bit BRGH v BRG16 c c tc baud mong mun. 2. Cho php cng truyn khng ng b ni tip bng cch xa bit SYNC v set bit SPEN. 3. Nu cn s dng ngt th set bit RCENv chn mc u tin mong mun bng bit RCIP . 4. Set bit RX9 cho php nhn 9 bit. 5. Set bit ADDEN cho php d a ch . 6. Cho php nhn bng cch set bit CREN. 7. Bit RCIF s c set khi khi qu trnh nhn hon thnh. Ngt s c xc nhn nu bit RCIE v bit GIE bits are sec set. 8. c thanh ghi RCSTA xc nh li trong qu trnh nhn, hoc c bit d liu th 9 (nu c th dng). 9. c thanh ghi RCREG xc nu thit b l a ch. 10. Nu c li th xa bit CREN . 11. Nu thit b xc nh c a ch , xa bit ADDENv cho php nhn tt c d liu vo m v ngt CPU. T NG KCH HOT K T NGT NG B. Trong sut ch sleep , tt c cc xung ca ch EUSART b treo. Bi v vy , b pht tc baud khng hot ng v nhn mt byte khng th thc hin c. c im ca ch kch hot t ng cho php kch hot hot ng tr li trn ng RX/DT trong khi EUSART hot ng trong ch khng ng b. c im ca kch hot t ng c cho php hot ng bng vic set bit WUE (BAUDCON<1>). Mt khi set bit ny, thng thng nhn lin tip trn RX/DT l khng th v EUSART cn li trong trng thi Idle , s kin kch hot c lp vi ch ca CPU. S kin kch hot bao gm khi xut hin sn xung trn ng RX/DT . (N trng vi k t ngt ng b v k t kch hot giao thc LIN )
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Sau s kin kch hot , module s pht ra mt ngt RCIF. Ngt ny c pht ng b vi xung Q trong ch hot ng bnh thng. (hnh 18-8) v ch khng ng b, nu chp hot ng trong ch sleep (hnh 18-9). iu kin xy ra ngt l phi xa bng cch c thanh ghi RCREG . Bit WUE c t ng xa mt khi trn ng RX xut hin sn ln sau s kin kch hot ngt. Vo thi im , module EUSART trong ch Idle v tr li hot ng bnh thng. Tn hiu s dng trong s kin ngt ng b l s kin trn. Phi thn trng khi s dng Auto-Wake-up Khi m chc nng t ng kch hot c nhn bit bi sn ln trn chn RX/DT, thng tin v thay i trng thi trc khi bit Stop l tn hiu li End-of-Character (EOC) v nguyn nhn l li d liu hoc li khung truyn . lm vic ng th k t truyn ban u phi l 0s. y c th l 00h (8 bits) theio chun thit b RS-232 hoc 000h (12 bits) theo chun LIN. B dao ng bt u hot ng cng phi c xem xt, c bit l ng dng trong vic s dng b dao ng bt u ngng hot ng (i.e., XT or HS mode). K t ngt ng b (tn hiu kch hot ) phi di v sau phi cho php thi gian cho php b dao ng bt u v cung cp gi tr khi to cho EUSART. Cn phi c bit thn trng khi s dng bit WUE . Thi gian ca s kin bit WUE v bit RCIF c th b ri lon khi n xc nh gi tr ca d liu nhn when it comes to determining the validity of received data. Nh lu , set bit WUE khi s dng EUSART . Bit WUE c xa sau khi trn chn RX/DT xut hin sn ln. iu kin ca ngt l n phi c xa bng cch c thanh ghi RCREG. Thng thng , d liu trong RCREG s l d liu gi v nn c b. Thc t l bit WUE c xa (hoc vn c set) v c RCIF c set nn khng c s dng nh d liu ban u trong thanh ghi RCREG. Ngi s dng nn xem xt cc trin khai phng php song song trong firmware (l phn mm nh trong b nh ch c) nhn d liu nguyn vn. m bo rng khng b mt d liu, kim tra bit RCIDL xc nhn rng mt hot ng nhn d liu l khng xy ra trong qu trnh ny. Nu hot ng nhn khng xy ra th bit WUE c th sau c t trc khi vo ch Sleep K T NGT LIN TIP Module EUSART c th gi k t ngt lin tip c bit . K t ngt ny cn cho chun LIN. K t ngt truyn bao gm bit Start theo sau l 12 bit v mt bit Stop. Khung k t ngt c gi bt c khi no bit SENDB v bit TXEN (TXSTA<3> v TXSTA<5>) c set trong khi thanh ghi dch truyn c np d liu . Ch rng gi tr d liu ghi vo thanh TXREG s c b qua v tt c cc bit 0s(k hiu cho cc bit) s c truyn. Bit SENDB s c t ng reset bi phn cng bit Stop tng ng c gi. iu ny cho php ngi s dng np li gi tr truyn FIFO vi byte truyn tip theo sau k t ngt (thng thng k t ng b ch r trong LIN). Ch rng gi tr d liu ghi vo TXREG cho k t ngt c b qua. Cch vit n gin ch phc v cho cc mc ch khi ng n gin. Bit TRMT ch ra rng khi qu trnh truyn l khng hot ng hoc ch Idle,ging nh qu trnh truyn bnh thng . Xem hnh 18-10 cho thi gian ca chui k t ngt. Ngt v truyn ng b lin tip.
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Sau khi c ngt th chui lin tip s c gi bt u bng khung thng ip , sau l byte n Auto-Baud Sync . y mt s thnh phn chnh thng thng ca mt LIN bus. 1. Cu hnh EUSART c ch mong mun. 2. Set bit TXEN v bit SENDB t ch k t ngt. 3. Np vo TXREG mt k t gi bt u truyn (gi tr ny s c loi b ). 4. Ghi 55h vo TXREG np k t ng b vo m truyn FIFO. 5. Sau khi ngt c gi , bit SENDB c reset bi phn cng. K t ng b by gi c truyn trong ch cu hnh sn ri. Khi thanh ghi TXREG tr nn rng, c bit bi bit TXIF, byte d liu tip theo c th ghi vo TXREG.
NHN MT K T NGT. Module USART m rng c th nhn mt k t ngt bng hai cch. Phng php u tin l cu hnh tc baud bng 9/13 tn s bnh thng. iu ny cho php bit Stop truyn ng v tr ly mu (13 bits cho bit Start chng ngt v 8 bit d liu cho d liu bnh thng). Phng php th 2 s dng c im ca t ng kch hot ( auto-wake-up) m t trong mc 18.2.4 Auto-Wake-up on Sync Break Character. Bi vic cho php c im ny, EUSART s ly mu hai ln truyn tip theo trn RX/DT,bi v ngt RCIF v nhn d liu byte tip theo sau mt ngt khc.
Ch ng b chnh EUSART
Ch ng b chnh c nhp vo bng cch set bit CSRC (TXSTA<7>). Trong ch ny , d liu c truyn theo phng thc bn song cng (truyn v nhn ch c xy ra vo mt thi im). Khi truyn d liu , qu trnh nhn b cm v ngc li . Ch ng b c cho php bng cch set bit SYNC (TXSTA<4>). Ngoi ra, bit cho php SPEN (RCSTA<7>) c set cu hnh cho chn TX v chn RX tng ng vi ng xung nhp CK (clock) v ng d liu DT (data) . Ch chnh ch ra rng qu trnh truyn chnh to xung nhp trn ng CK. Chiu xung nhp c chn bng bit TXCKP (BAUDCON<4>); t bit TXCKP t trng thi Idle trn CK nh mc cao, trong khi xa trng thi Idle nh l mc thp. S chn ny c cung cp h tr thit b Microwire devices vi module ny. EUSART SYNCHRONOUS MASTER TRANSMISSION Khi biu truyn EUSART a ra trn hnh 18-3. Trung tm ca khi truyn l thanh ghi dch ( ni tip) TSR. Thanh ghi dch thu c d liu t thanh ghi m
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c/ghi TXREG. Thanh ghi TXREG c np d liu t phn mm . Thanh ghi TSR khng c np d liu cho n khi bit cui cng c truyn t ln np trc. Ngay khi bit cui cng c truyn, thanh ghi TSR c np gi tr mi t TXREG (nu cho php ). Mt khi thanh ghi TXREG truyn d liu cho thanh ghi TSR (xy ra trong mt TCY), thanh ghi TXREG b trng v bit c TXIF (PIR1<4>) c set . Ngt c th c cho php hoc khng cho php bng cch t hoc xa bit cho php ngt TXIE (PIE1<4>). TXIF c set cho d trng thi ca bit cho php ngt TXIE th no;n c th c xa trong phn mm. N ch s c reset khi d liu mi c np li thanh ghi TXREG . Trong khi bit c TXIF bo trng thi ca thanh ghi TXREG th bit khc l bit TRMT (TXSTA<1ch trng thi thanh ghi TSR . Thanh ghi TRMT ch c c khi bit bo trng thi thanh khi TSR l trng rng c set. Khng c ngt logic no c to ra t bit ny v vy ngi s dng phi gim st bit ny xc nh thanh ghi TSR c rng khng. Thanh ghi TSR khng c cho sn trong b nh v vy n khng c sn cho ngi s dng. Thit lp ch truyn ng b ch: 1. Khi to cho thanh ghi SPBRGH:SPBRG c tc baud thch hp. set hoc xa bit BRGH v BRG16 c c tc baud mong mun. 2. Cho php cng ni tip chnh ng b bng cch set bit SYNC, SPEN v CSRC. 3. Nu mun c ngt, set bit cho php TXIE. 4. Set bit RX9 cho php nhn 9 bit. 5. Cho php truyn bng cch set bit TXEN. 6. Nu chn truyn 9 bit trong khung d liu ,th bit th 9 s c np vo bit TX9D. 7. Bt u truyn bng cch np d liu vo thanh ghi TXREG . 8. Nu s dng ngt th phi m bo rng cc bit GIEv PEIE trong thanh ghi INTCON (INTCON<7:6>) phi c set. CH NHN NG B MASTER Mt khi ch ng b c chn, nhn d liu c cho php bng cch set bit Single Receive Enable SREN (RCSTA<5>), hoc bit cho php tip tc nhn CREN (RCSTA<4>). D liu l cc mu trn chn RX khi c sn xung ca xung nhp. Nu bit cho php SREN c set ,ch khi c t n c nhn. Nu bit cho php CREN c set, qu trnh nhn s tip tc cho n khi bit CREN c xa. Nu c hai bit c set , th CREN c u tin. Thit lp ch nhn ng b Master: 1. Khi to cho thanh ghi SPBRGH:SPBRG c tc baud thch hp. set hoc xa bit BRGH v BRG16 c c tc baud mong mun. 2. Cho php cng ni tip chnh ng b bng cch set bit SYNC, SPEN v CSRC. 3. Chc chn rng bit CREN v SREN c xa. 4. Nu cho php ngt, set bit RCIE. 5. Set bit RX9 cho php nhn 9 bit. 6. Nu nhn ring r , set bit SREN. tip tc nhn set bit CREN. 7. Bit c ngt RCIFs c set khi qu trnh nhn hon thnh v mt ngt s c pht ra nu bit cho php RCIE c set. 8. c thanh ghi RCSTA xc nh li trong qu trnh nhn, hoc c bit d liu th 9 (nu c th dng).
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9. c 8 bit d liu nhn bng cch c thanh ghi RCREG . 10. Nu c li th xa li bng cch xa bit CREN . 11. Nu s dng ngt th phi m bo rng cc bit GIEv PEIE trong thanh ghi INTCON (INTCON<7:6>) phi c set. Ch ng b Slave ca EUSART. Ch ng b Slave c a vo hot ng bng cch xa bit CSRC (TXSTA<7>). Ch ny khc vi ch ng b Master Synchronous Master mode trong xung nhp c cung cp t bn ngoi chn CK (thay v cung cp t bn trong trong ch Master ). iu ny cho php thit b truyn v nhn d liu trong ch tit kim nng lng. CH TRUYN NG B SLAVE CA EUSART. Hot ng ca ch Master v Slave l ging nhau , ngoi tr trong ch Sleep. Nu hai t c vit ln TXREG v sau ch SLEEP hng dn c thc hin nh sau: a) T u tin s ngay lp tc c chuyn vo thanh ghi TSR v truyn. b) T th hai cn li trong thanh ghi TXREG . c) Bit c TXIF s khng c set. d) Khi t th nht c truyn khi thanh ghi TSR,thanh ghi TXREG s truyn t th hai cho thanh ghi TSR v bit c TXIF by gi s c set. e) Nu bit cho php TXIE c set , ngt s kch hot chip t ch Sleep. Nu ngt ton cc c cho php , chng trnh s phn nhnh vector ngt . Thit lp ch truyn ng b Slave: 1. Cho php cng ni tip Slave bng cch set bit SYNC v bit SPEN v xa bit CSRC. 2. Xa bit CREN v bit SREN. 3. Nu cho php ngt, set bit TXIE. 4. Set bit RX9 cho php nhn 9 bit. 5. Cho php truyn bng cch set bit cho php TXEN . 6. Nu chn truyn 9 bit c chn ,bit th 9 c np t bit TX9D. 7. Bt u truyn bng cch np d liu cho thanh TXREG. 8. Nu s dng ngt th phi m bo rng cc bit GIEv PEIE trong thanh ghi INTCON (INTCON<7:6>) phi c set. CH NHN NG B SLAVE CA EUSART. Hot ng ca ch Master v Slave l ging nhau , ngoi tr trong ch Sleep hoc ch Idle v bit SREN l bit dont care trong ch Slave. Nu nhn c cho php bi vic set bit CREN bit u tin ch hoc ch Idle , sau khi mt t c th nhn trong ch tit kim nng lng. Mt khi mt t c nhn , thanh ghi RSR s truyn d liu cho thanh ghi RCREG ; nu bit cho php RCIE c set, ngt c pht s c kch hot chp trong ch tit kim nng lng. Nu ngt ton cc c cho php , chng trnh s phn nhnh vector ngt . Thit lp ch nhn ng b Slave : 1. Cho php cng ni tip Slave bng cch set bit SYNC v bit SPEN v xa bit CSRC. 2. Nu cho php ngt, set bit cho php RCIE. 3. Set bit RX9 cho php nhn 9 bit. 4. Cho php nhn bng cch set bit cho php CREN .
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5. Bit c RCIF s c set khi nhn hon thnh . Mt s c pht nu bit cho php RCIE c set . 6. c thanh ghi RCSTA nhn bit th 9 ( nu cho php ) v c xc nh nu c li xy ra trong qu trnh nhn. 7. c 8 bit d liu nhn bng cch c thanh ghi RCREG . 8. Nu c li xy ra ,xa li bng cch xa bit CREN. 9. Nu s dng ngt th phi m bo rng cc bit GIEv PEIE trong thanh ghi INTCON (INTCON<7:6>) phi c set.
1.2.7. Module chuyn i tong t sang s 10 bit (A/D)

Module chuyn i tng t sang s (A/D) c 10 u vo trong thit b 28 chn v c 13 u vo trong thit b 40/44 chn . Ch ny cho php trao i tn hiu tng t u vo tng ng vi 10 bit s. Module c nm thanh ghi: A/D Thanh ghi kt qu cao (ADRESH) A/D Thanh ghi kt qu thp (ADRESL) A/D Thanh ghi iu khin 0 (ADCON0) A/D Thanh ghi kt qu thp 1 (ADCON1) A/D Thanh ghi iu khin 2 (ADCON2) Thanh ghi ADCON0 trong thanh ghi 19-1, iu khin hot ng ca module A/D. Thanh ghi ADCON1 trong thanh ghi 19-2,cu hnh chc nng ca cc chn cng. Thanh ghi ADCON2 ch ra trong thanh ghi 19-3, cu hnh cho ngun xung A/D , phn mn s thu thp thi gian v hiu chnh. Thanh ghi ADCON0
bit 7-6 Unimplemented: mang gi tr 0 bit 5-2 CHS3:CHS0: bit la chn kenh tng t 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) (1,2) 0110 = Channel 6 (AN6) (1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Khng xc nh(2)
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1110 = Khng xc nh (2) 1111 = Khng xc nh (2) bit 1 GO/DONE: A/D trng thi bit chuyn i Khi bit ADON = 1: 1 = A/D ang trong qu trnh chuyn i. 0 = A/D Idle bit 0 ADON: bit hot ng A/D 1 = A/D Module chuyn i c cho php. 0 = A/D Module chuyn i khng cho php . Thanh ghi ADCON1
bit 7-6 Unimplemented: mang gi tr 0 bit 5 VCFG1: Bit cu hnh in p chun (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: bit cu hnh in p chun (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG3:PCFG0: A/D Nhng bt cu hnh iu khin cng:
Thanh ghi ADCON2
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bit 7 ADFM: bit chn nh dng cho A/D 1 = Cn chnh bn phi 0 = Cn chnh bn tri bit 6 Unimplementednmng gi tr 0 bit 5-3 ACQT2:ACQT0:bit la chn thi gian thu nhn A/D 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD bit 2-0 ADCS2:ADCS0: bt la chn xung chuyn i A/D 111 = FRC ( xung dn xut t b dao ng A/D RC ) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 in p chun tng t c chn bi phn mm l mt trong hai mc tch cc ca thit b cung cp in p l tch cc dng v tch cc m (VDD v VSS), hoc mc in p trn cc RA3/AN3/ VREF+ v cc chn RA2/AN2/VREF-/CVREF . B bin i tng t s A/D c c im l c th hot ng khi thit b ch Sleep . Hot ng trong ch Sleep, xung nhp chuyn i A/D c th c ly t b dao ng RC bn ngoi ca b chuyn i A/D. u ra ca mu v gi tr gi c ly t u vo ca b chuyn i, m n a ra thng qua vic ly xp x. Mt thit b c reset th buc phi reset tt c cc thanh ghi trng thi ca n .Khi module A/D module b tt v bt c qu trnh chuyn i no cng b b . Mi cng c ni vi b bin i A/D c th cu hnh nh mt u vo tng t hoc nh cng v ra s. Thanh ghi ADRESH v thanh ghi ADRESL cha kt qu ca chuyn i A/D.Khi chuyn i A/D hon thnh kt qu c np vo cp thanh ghi ADRESH:ADRESL ,bit GO/DONE ( thanh ghi ADCON0 ) c xa v bit c ngt A/D ( ADIF) c set. S khi ca module trong hnh 19-1. Yu cu khi s dng b thu nhn A/D i vi b A/D m bo chnh xc t np in phi c cho php np y mc in p u vo . Module vo tng t trong hnh 19-3. Tr khng ngun (RS) v tr khng bn trong cng tc ly mu (RSS) nh hng trc tip n thi gian np CHOLD. Tr khng trn cc cng tc ly mu (RSS) thay i khc nhau trn thit in p khc nhau (VDD). Tr khng ngun nh hng trc tip n in p offset ( in p lch) u vo tng t (r in trn chn ). Gi tr tr khng ln nht cho php ca ngun tng t l 2.5 k . Sau khi knh u vo tng t c chn ( thay
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i ), knh ny phi ly mu trong thi gian nh nht yu cu trc khi bt u chuyn i . Tnh ton thi gian nh nht yu cu To calculate the minimum acquisition time, Cng thc 19-1 c th c s dng . Trong cng thc ny cho rng 1/2 bit c trng s ln ( LSb error ) c s dng (1024 bc cho A/D). 1/2 bit c trng s ln li l li ln nht cho php ca A/D p ng phn gii nh . V d 19-3 ch ra cch tnh thi gian b nht cn thit TACQ. Tnh ton ny da trn cc gi thit thng s h thng sau: CHOLD = 25 pF Rs = 2.5 k Conversion Error 1/2 LSb VDD =5V Rss = 2 k Temperature = 85C (system max.) EQUATION:ACQUISITION TIME
EQUATION:A/D MINIMUM CHARGING TIME
EQUATION:CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Chn v cu hnh thi gian cn thit .

Thanh ghi ADCON2 cho php cho php ngi s dng chn c thi gian cn thit v thi gian ny xy ra mi ln bit GO/DONE c set . N cng cho ngi s dng la chn s dng t ng xc nh thi gian cn thit . Thi gian nhn c phi c t vi bit ACQT2:ACQT0 ( ADCON2 <5:3>), n cung cp mt di ca 2 n 20 TAD. Khi bit GO/DONE c set, module A/D tip tc ly mu u vo chn thi gian ,sau t ng bt u qu trnh chuyn i . Khi thi gian thu nhn c lp trnh , c th khng cn i mt thi gian thu nhn t lc chn knh n lc set bit GO/DONE . Ch chn thi gian thu nhn bng tay c chn khi ACQT2 :ACQT0 = 000. Khi bit GO/DONE c set, mu s ngng nhn v qu trnh nhn c bt u . Ngi s phi c trch nhim m bo thi gian thu nhn cn thit phi qua thi im chn knh v set bit GO/DONE . S la chn ny cng mc nh thit lp li trng
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thi ca bit ACQT2:ACQT0 v tng thch vi thit b m khng cung cp cho lp trnh thi gian thu nhn. Trong c hai trng hp ,khi chuyn i hon thnh th bit th bit GO/DONE c xa, c ADIF c set v A/D bt u ly mu c chn mt ln na . Nu thi gian thu nhn c lp trnh , khng c g xc nh nu thi gian thu nhn kt thc nu qu trnh truyn bt u .
Chn xung nhp chuyn i A/D .

Thi gian A/D chuyn i mt bit c xc nh nh l mt TAD. V thi gian A/D truyn 10-bit cn l 11 TAD. Ngun xung nhp A/D chuyn c phn mm chn . C by thi gian la chn cho TAD: 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC B to dao ng RC . Kim tra b chuyn i A/D , xung nhp b chuyn i A/D (TAD) phi ngn nht c th nhng ln hn thi gian nh nht TAD ( xem tham s 130 bit thm thng tin). Bng 19-1 ch ra rng tng thi gian TAD nhn c t tn s thit b hot ng v ngun xung nhp A/D c chn.
Hot ng trong cc ch qun l ngun.

Chn ch thi gian thu nhn t ng v xung nhp chuyn i A/D c xc nh mt phn t xung nhp ngun v tn s trong ch qun l ngun . Nu b A/D phi hot ng trong khi thit b trong ch qun l ngun th bit ACQT2:ACQT0 v bit ADCS2:ADCS0 bits trong thanh ghi ADCON2 phi c cp nhp ph hp vi ngun xung c s dng trong ch ny . Sau khi nhp ch ,b A/D thu nhn hoc chuyn i c th bt bt u hot ng . Khi n hot ng xung nhp ca thit b nn tip tc gi bng xung nhp ca ngun cho n khi qu trnh chuyn i c hon thnh . Nu mun ,thit b c th t vo ch Idle tng ng trong qu trnh chuyn i. Nu tn s xung nhp thit b l thp hn 1 MHz, v ngun xung nhp RC ca
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A/D c chn .Hot ng trong ch Sleep cn chn ngun xung nhp FRC ca A/D . Nu bit ACQT2:ACQT0 c set thnh 000 v qu trnh chuyn i c bt u , th qu trnh chuyn i s c tr trong mt chu k lnh cho php thc hin lnh SLEEP i vo ch Sleep . Bit IDLEN(OSCCON<7>) phi c xa trc khi qu trnh chuyn i.
Cu hnh cc chn ca cng tng t.

Cc thanh ghi ADCON1, TRISA, TRISB v TRISE dng cu hnh cho cc chn ca cng tng t s A/D . Cc chn khi m lm vic nh cng vo cn phi set cc bit TRIS tng ng (u vo). Nu bit TRIS b xa ,mc cng ra s ( VOH hoc VOL ) s c b bin i . Hot ng ca A/D c lp vi trng thi ca bit CHS3:CHS0 v bit TRIS .
S bin i A/D
Hnh 19-4 minh ha hot ng ca b bin i A/D sau khi bit GO/DONE c set v bit ACQT2:ACQT0 c xa. Mt s bin i c bt u sau khi lnh cho php i vo ch Sleep . Hnh 19-5 minh ha hot ng ca b bin i sau khi bit GO/DONE c set v bit ACQT2:ACQT0 c set thnh 010, v chn thi gian thu nhn bng 4TAD trc khi chuyn i bt u . Xa bit GO/DONE trong qu trnh chuyn i s b qua dng chuyn i . Cp thanh ghi kt qu ca chuyn i A/D s khng c cp nht khi mu chuyn i mi hon thnh mt phn . iu ny c ngha rng thanh ghi ADRESH:ADRESL s tip tc cha gi tr ca ln chuyn i trc (hoc gi tr ghi vo thanh ghi ADRESH:ADRESL ). Sau khi chuyn i A/D c hon thnh hoc hy b , thi gian ch 2TAD l cn thit trc ln thu nhn tip theo c th bt u . Sau thi gian ch ny , knh thu nhn c chn th t ng bt u hot ng .
Phng in
Giai on phng in c s dng khi to gi tr cho dy t in.Dy t in ny c phng in trc tt c cc mu . c im ny gip ti u ha b khuch i,nh l mch cn np mng t in ,ch khng phi np /phng in da trn s o lng gi tr .
S dng Trigger CCP2

Mt b chuyn i A/D c th c khi ng bng cch kch hot s kin c bit ca module CCP2 . S kin ny cn cc bit CCP2M3:CCP2M0 (CCP2CON<3:0>) c lp trnh bng 1011v module A/D c cho php (bit ADON c set ). Khi kch hot xy ra ,bit GO/DONE s c set , bt u qu trnh nhn v chuyn i , b m ca Timer1 (hoc Timer3) c reset v khng. Timer1
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(hoc Timer3) c reset t ng lp li chu k chuyn i vi mc ch ti u ha phn mm(chuyn ADRESH:ADRESL n v tr mong mun ). Knh u vo tng t tng ng phi c chn v chu k chuyn i nh nht cng c t bi ngi s dng, thi gianTACQ tng ng c chn trc khi s kin kch hot c bit set bit GO/DONE (bt u qu trnh chuyn i ). Nu module A/D khng c cho php hot ng (bit ADON c xa), s kin kch hot ngt c bit s b b qua bi module A/D, nhng vn reset b m ca Timer1 (hoc Timer3) .
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Thit k b iu khin PID s trn nn vi iu khin PIC
Chng 2: Thit k b iu khin PID s

2.1 Thit k m hnh phn cng mch iu khin
2.1.1. Yu cu thit k
Khi thit k mt kit iu khin thnh phn trung tm l vi iu khin cho php c th ci t nhiu thut ton iu khin th trc tin yu cu vi diu khin phi tnh ton nhanh, dung lung b nh ln hoc c th m rng c b nh vi dng chip Pic mi th c bn p ng yu cu ny. Bn cnh kit iu khin cng phi c kh nng giao tip vi nhiu i tng v thit b cm bin khc nhau, hin th cc tham s ch hot ng ng thi c kh nng c th giao tip my tnh thc hin chc nng iu khin gim st Trn c s vic thit k kit iu khin trong n thieets k m bo chc nng:
- Kit c cc u vo tng t theo cc chun cng nghip 0-20mA, 4 -20mA,

0-10V v u vo o in tr, bn cnh l cc u vo s cho php thu thp cc gi tr logic s, m xung, nhn tn hiu ngt t bn ngoi. - Kit c cc u ra tng t theo cc chun cng nghip 0-20mA, 4 -20mA, 0 10V, cc u ra s, bao gm u ra logic s, u ra xung cho php bm xung hoc pht tn s. - Kit giao tip vi my tnh qua cng ni tip RS 232, cho php gi v nhn d liu vi my tnh. - Kit c cc phn t cho php hin th l LCD hoc LED . - Kit c khi bn phm cho php nhp mt s tham s v ch hot ng. - Kit c cc chn vo ra cho php kt ni mt s modul chc nng khc Nh vy m hnh khi chc nng ca kit mch iu khin c dng:
Hnh 2.1 M hnh khi mch iu khin
57

Cu to ca kt iu khin : y cc u vo-ra tng t l cc tn hiu chun iu khin 0-20mA, 4 -20mA, 0-10V cn cc u vo ra s l cc tn hiu logic hoc xung s. Khi vi iu khin trung tm l thnh phn quan trng nht ca kit n gim st thu thp x l d liu t cm bin v c cu chp hnh iu khin truyn thng ni tip vi my tnh qua chun RS232. Bn phm v LCD l hai modul tc dng h tr qu trnh iu khin v gim st h thng hot ng.
2.1.2. Cc khi chc nng trn kit iu khin

a) Khi vi iu khin trung tm
Hinh 2.2.S khi vi iu khin trung tm Khi vi iu khin trung tm c nhim v iu khin qun l, gim st, iu khin hot ng ton b cc modul s dng trong mch c ngha l mi hot ng trong h thng trn c s diu khin Pic18F4520. Ngoi ra: - Vi iu khin Pic18F4520 s dng mch dao ng thch anh ngoi tn s 10MHz. - S dng mch np PicKit2 ring np chng trnh cho PIC18F4520
Hinh 2.3 Mch np cho vi iu khin trung tm
58

b) Khi giao tip my tnh qua cng ni tip
Hinh 2.4 Khi giao tip my tnh Max232 Cng ni tip ca my tnh l cng COM( Comunication Port) giao tip d liu hai chiu gia my tnh PC v ngoi vi vi nhiu u im . Ngy nay, mi my tnh c nhn u c mt hoc mt vi cng ni tip theo chun RS-232 (cng COM), c th s dng kt ni vi cc thit b ngoi vi hoc cc my tnh khc. Nhiu thit b cng nghip cng tch hp cng RS-232 phc v cho cng vic lp trnh hoc tham s ha. Cu to cng COM - TxD (Transmit Data): ng gi d liu - RxD (Receive Data): ng nhn d liu - RTS (Request To Send): Yu cu gi; b truyn t ng ny ln mc hot ng khi sn sng truyn d liu. - CTS (Clear To Send): Xo gi; b nhn t ng ny ln mc hot ng thng bo cho b truyn l n sn sng nhn d liu.
Hnh 2.5 : Cu to cng COM
59

DSR (Data Set Ready): D liu sn sng; tnh hot ng ging vi CTS nhng c kch hot bi b truyn khi n sn sng nhn d liu. - SG (Signal Ground): t ca tn hiu. - DCD (Data Carrier Detect): Pht hin tn hiu mang d liu. - DTR (Data Terminal Ready): u cui d liu sn sng; tnh hot ng ging vi RTS nhng c kch hot bi b nhn khi mun truyn d liu. - RI (Ring Indicate): Bo chung, cho bit l b nhn ang nhn tn hiu rung chung. Cng ni tip c nhiu u im v c im ni tri: - Tnh chng nhiu tng i tt, khong cch truyn xa hn cng song song. - S lng dy kt ni t ti thiu 3 dy: TxD, RxD , GND. - Ghp ni d dng vi iu khin hoc PLC. - C kh nng kt ni mng Trong s mch giao tip my tnh ny chng ta s dng 3 dy truyn nhn d liu TxD, RxD, GND khng dng ch bt tay phn cng, nu khi cn bt tay chng ta c th s dng phn mm. Ngy nay vi x l v my tnh tc hot ngcao khng n trc ln thun li khi chng ta truyn nhn . Trn vi iu khin chng ta s dng modul USART giao tip bt ng b my tnh ci t thng s: tc 9600 baud, 1bit start, 1 bit stop, 8 bit d liu khng s dng bit Parity. c) Khi bn phm -
Hinh 2.6 Modul bn phm
60

Nguyn tc s dng kh bn phm l :Dng ngt nhn bit c phm nhn. Ban u khi to cc COL1 : COL4 l 0000, v ngt ngoi INT0 c kch hot khi c sn xung (1 0). Khi nhn mt phm bt k th chn INT0 xut hin sn xung chng trnh chuyn sang phc v ngt. Trong th tc ngt ta xc nh phm no c nhn, xc nh c ta cn xc nh ra hng v ct ca phm c nhn. u tin ta kim tra cc hng ROW1 ROW4 nu hng no c gi tr bng 0 th hng c phm nhn. Tip theo ta xc nh ct, u tin ta cho COL1=1 v COL2=COL3=COL4=0 sau kim tra tch ROW1*ROW2* ROW3*ROW4, nu tch bng 1 th ct 1 c phm nhn, t xc nh c phm no nhn. Nu tch bng 0 th khng phi ct 1 c phm nhn, ta li chuyn sang kim tra ct 2 vi COL2=1 v COL1=COL3=COL4=0. C tip tc nh vy ta s xc nh c ct c phm nhn. d) Khi hin th LCD 2x16(2 dng, 16ct) LCD lm vic ch 8 bit ghp ni Port D ca vi iu khin trung tm
Bng s lc chc nng LCD 2x16
61
Hnh 2.7 Khi hin th LCD S dng mt bin tr 100K iu chnh tng phn ca LCD. Ch dng LCD hin th (Write) nn chn R/W c ni mass.
e) Khi mch ng lc iu khin
Hinh 2.8 Khi thit b chp hnh Khi mch lc ny lm vic ng theo nguyn l trnh c cu chp hnh (IC L298) trnh by chng 3 ng dng b iu khin PID s iu khin ng c mt chiu . f) Khi ngun 12V/5V
Hnh 2.9 S khi ngun
62

Trong mch s dng hai modul ngun 5V(cung cp mch iu khin) v 12V(cung cp cho ng c): - Mch cung cp u ra 5V cho mch iu khin: in p u vo xoay chiu khong 18-24V xoay chiu ly t bin p, qua chnh lu 2 na chu k bng cu diode, thu c in p 1 chiu 18 - 24V sau qua IC n p LM7805 mc song song thu c in p u ra 5V. Trc IC n p ta mc thm tr nhit v diode tn nhit 1 phn cho IC v bo v ngn dng nh ngc. u vo v u ra ca IC n p u mc thm t, gm c t ha (c phn cc) v t keo (khng phn cc) n nh in p. Ngoi ra cn thm n bo v cng tc bt, v cu ch bo v u vo khi ly ngun t bin p. - Mch ngun 12V cng tng t hot ng nh trn nhng thay v dng ICLM7805 chng ta dng LM7812 to ngun 12V iu khin ng c. g) Cc khi khc Trn Kit cn c mt s khi ph khc nh ci chip, led, ADC, ISP&ISCP kt ni mch np ngoi cho Chip, hai chn vo ra cho php kt ni u vo ra khc, Encoder, truyn thng cng Com.
S nguyn l kit iu khin
63
S mch in hai lp
2.2 Thit k phn mm trn nn vi iu khin PIC

2.2.1. Yu cu phn mm
Chng trnh phn mm cho vi iu khin Pic18F4520 c th vit theo nhiu cng c nh CCS, ngn ng Asembly hoc C18 . Trong n chng ta thc hin lp trnh vi iu khin Pic18F4520 s dng C18 trn mi trng MPLAB ca nh sn sut Mcochip. Phn mm nhng trn vi iu khin PIC thc hin cc nhim v sau: - Nhn d liu thng s t my tnh v bn phm. - X l v nhn cc tn hiu t cc u vo s hoc tng t trn modul phn cng. - Truyn d liu ln my tnh qua cng truen thng ni tip RS232. - Hin th d liu ln LCD v tn hiu n led. - Tnh ton u ra cho b iu khin thit k, trong ti l b iu khin PID s. Khi vit chng trnh cho vi iu khin chng ta c th s dngth vin khi chc nng h tr sn nh sn xut v cc modul PWM, Timer, ADC, Led, cc hm b iu khin PID
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Thit k b iu khin PID s trn nn vi iu khin PIC 2.2.2. Gii thut chng trnh
a) Loop iu khin BEGIN
Khi to cc khi chc nng:

PWM,LCD,TIMER
Khi to cc gi tr ban u
Start ? Yes Cp nht d liu t ADC CPU Tnh ton thut ton PID
No
Digital
Kiu cng ra ? Analog
PWM
CPU
ADC
X l truyn thng
END
Hnh 2.10 Lu loop iu khin
65

Khi thc hin chng trnh chng ta qun l theo ngt to chu k trch mu.
Start Interrupt
If (Bin m < Constant) then bin m++ Else bin m=Constant; thc hin thut ton Flag=1;
End Interrupt Hnh 2.11 Lu hm ngt dng to chu l trch mu Trong gi T l chu k trch mu chng trnh th ta s xy dng c quan h bin Constant v T theo khung thi gian hot ng ca timer. iu c ngha ln trong vic qun l chnh xc vic to thi gian trch mu. b) Thut ton PID s * ) Lut PID trn min thi gian ( lin tc ) c m t bi cng thc: (3.1) KR = H s t l TC = Hng s thi gian tch phn TV = Hng s thi gian vi phn * ) Xp x thnh phn I (3.2) Bn cht l php tnh xp x din tch ca hm e (t) - Xp x theo nguyn tc hnh ch nht : Trong :
- Xp x theo nguyn tc hnh thang :
Trong T l chu k trch mu . *) Xp x thnh phn D - Khai trin thnh chui
66
- Vi phn xp x bc 2 :
- Vi phn xp x bc 1 :
*) Xp x lut PID Thay cc cng thc xp x trn vo cng thc: uk = upk + uik + udk - Vi xp x thnh phn I theo phng php hnh ch nht v thnh phn D theo bc 1
(3.3)
- Vi xp x thnh phn I theo phng php hnh ch thang v thnh phn D theo bc2:
- Theo Takahashi c th lm gim bt bin ln iu khin khi i lng ch o ( gi tr t ) c t bin nhanh bng cch, thay v ek = wk xk ch s dng ek = - xk. T ta c :
(3.4)
M hnh b iu khin PID s:
Hnh 2.12 S b iu khin PID s
67

S nh trn gip chng ta c th la chn nhiu gii php s dng b iu khin PID theo nhiu lut khc nhau. Khi thit k thut ton PID s cho vi iu khin chng ta cng thc hin thut ton PID theo nguyn tc chung nh trn nhng s dng cc khi Timer qun l vic thc hin thut ton. Cc thng s u vo b iu khin l Ref_Input v Mea_Input lun c cp nhp t cc cng vo ra s v tng t trn kit iu khin vi iu khin thc hin thut ton PID p t ln c cu chp hnh iu khin i tng. Trong qu trnh iu khin da trn sai lch u vo gia Ref_Input v Mea_Input b iu khin PID s tc dng va a sai lch m hnh v khng va m bo cc ch tiu cht lng iu khin . Mi mt chu k thc hin thut ton PID trn vi iu khin th tn hiu u ra ca h thng iu khin lun c cp nhp qua cm bin chuyn i phn hi v to tn hiu Mea_Input . C nhiu cch xp x b iu khin PID nn vic thc thi cc thut ton PID trn vi iu khin cng khc nhau. Mt vn quan trng cn quan tm khi thit k b iu khin PID cn quan tm l vic hn ch cc hin tng bo ho tch phn (Winup). Vn d ny rt thng gp khi thc thi lut iu khin PID. Hin tng bo ho tch phn l hin tng u ra ca b iu khin vn tip tc tng qu mc gii hn do tch lu ca thnh phn tch phn vn cn khi sai lch iu khin tr v khng. Gii quyt vn ny c th s dng phng php: - Khi sai lch m hnh bng khng ta thc hin tch b thnh phn tch phn hoc xo trng thi ca n bng vng lp. - Gim h s khuch i u ra nm trong di cho php khng qu ln. - Thc hin thut ton b thnh phn tch phn bng phn hi gi tr thc o c. - t mt khu gii hn du ra ca b iu khin v s dng thut ton b. Hai phng php cui c u im hn c v thng c hu ht cc b iu khin cng nghip h tr. Gi php a nng v p dng nhiu trn thc t thc hin Anti_Winup l iu khin bm(tracking) thc cht ci thin thnh phn tch phn I:
Hnh 2.13 Chng bo ho tch phn
68
Thit k b iu khin PID s trn nn vi iu khin PIC 2.2.3. Thit k phn mm iu khin v gim st trn my tnh
Chng ta thc hin thit k giao din giao tip vi iu khin v my tnh bng ngon ng Visual Basic6.0(VB).Trong mi trng lp trnh VB, vic to ra mt giao din ha l tng i n gin. VB h tr cho ngi s dng nhng m un i tng ph bin gip cho cng vic ca ngi lp trnh tr nn nh nhng hn rt nhiu. Vic to giao din ch l la chn nhng i tng v vo mt giao din (form) c sn cng vi vic thit lp cc thng s cho i tng. y, giao din c to tng i n gin nhng p ng c nhng yu cu m cng vic t ra. Yu cu cng vic: Thu nhn d liu do ngi dng nhp vo (cc gi tr Kp, Ki, Kd , thng s cn t c ) Phn tch, x l d liu nhn, truyn xung cho vi iu khin PIC qua cng ni tip Nhn d liu truyn v t PIC v hin th ln mn hnh ha thy c kh nng p ng ca h thng
Hnh 2.14. Giao din giao tip PC
69

Trn giao in ho gm c cc button iu khin, cc textbox hin th s liu, combobox cho php la chn cc ch , v picturebox dng nhn d liu ca ngi s dng v vo, ng thi cng l ni hin th d liu thu nhn c cho thy p ng ca h thng. C th hot ng cc phm chc nng nh sau: - Khi chc nng iu khin ng c bao gm:comand button v textbox biu th v iu khin ch hot ng ng c DC. Button StartButton Start dng bt u gi gi tr v tr mong mun xung cho vi iu khin, lc chng trnh s nhn c gi tr tc c gi ln bi vi iu khin thng qua giao trip RS232, ri v trn th v hin th gi tr tc ca ng c trn th theo min thi gian, t ta c th quan st c hot ng ca h thng c p ng ng yu cu ra khng (nh sai lch, thi gian t c ).Button Inverser iu khin o chiu quay ng c. Button Stop dmg hot ng ca ng c Button update l cp nhp thng s khi iu khin. Hai Textbox tc t v Chu k to thng s cho iu khin ng c xung vi iu khin. - Khi Parameter Sattus Motor l cc texbox ch c chc nng hin th thng tin cp nhp trong qu trnh iu khin. - Khi b iu khin cho ngi s dng c th nhp d liu ban u iu khin. Trn c s xy dng thut ton pha di vi iu khin. - Khi th c button Export nhim v xut d liu ra mn hnh iu khin quan st cht lng h thng. - Cn li Button Exit thc hin thot khi chng trnh khi cn thit . - Mn hnh th cho ta hai c tnh l c tnh iu khin tc ng c v in p u vo.
70
2.3 Kit iu khin
Sn phm kit iu khin c c sau khi thit k c cc khi chc nng nh nu phn trn vi c im : - C cc cng vo tng t : 0 - 5V, 0 - 20mA. - C cc cng ra s ( xung s v logic) - Thi gian trch mu ti thiu l 2.55*10-5 s, tuy nhin vi thi gian trch mu nh ta phi lu ti thi gian tnh ton ca cc cu lnh. Vi thi gian trch mu ln ( v d trong ng dng iu khin nhit ) ta c th b qua thi gian tnh ton ca VXL. - C cc khi hin th LCD, Led . - C khi giao tip truyn thng ni tip my tnh RS232. - Khi ngun 5V v 12V - Ci cnh bo
71
Chng 3: ng dng b iu khin PID s iu khin ng c mt chiu

3.1 i tng iu khin
3.1.1. Thng s k thut
Hnh 3.1 ng c s dng trong n Chng ta s dng Servo Motor vi cc thng s c bn nh sau: in p ngunti a l 24V. Tc ti a l 3000 vng/pht. C gn lin Encoder quang tng i 100xung . Cng sut 30-50w.
3.1.2. Nhn dng m hnh ng hc ca ng c in mt chiu

Cu trc mhnh ng hc ca ng c in c sut ti liu tham kho [3], [4], [6] c m hnh dng:
WDT ( s ) = K 1 + 2 *Ts + (Ts ) 2
(3-1)
Cc tham s m hnh ng c in mt chiu s c nhn dng t thc nghim v gii thiu trong phn tip theo.
3.1.3. Thu thp d liu vo/ra ca ng c in mt chiu t thcnghim

Chng ta s dng kit iu khin thu thp d liu nhn dng ng c in mt chiu theo m hnh :
Hinh 3.2 S thu thp d liu nhn dng
72
Hnh 3.2 c tnh thu thp d liu nhn dng Trong giao in phn mm gim st h thng chng ta c th ly trc tip d liu vo/ra xut ra file nh dng Exel. Nh vy chng ta c tp d liu i tng lu trn file: C:\data.xls. Chng ta hon ton c th chuyn d liu dng khc s dng nhn dng nh file .mat, .dat Matlab vn h tr cc d liu nh dng ny. Khi thu thp d liu i tng ta cho in p du vo ng c l 9V, thi gian trch mu 5ms .
73
Thit k b iu khin PID s trn nn vi iu khin PIC 3.1.4. Nhn dng ng c in mt chiu bng Toolbox Identification cu Matlab
Sau khi thu thp d liu vo ra ca ng c ta tin hnh nhn dng i tng s dng toolbox ca Matlab (System Identification toolbox) . Khi nhn dng i tng s dng d liu trong min thi gian Time Domain Data. Cc bc tin hnh nhn dng trn Matlab tm lc nh sau :
Cc cu lnh tin hnh nhn dng d liu trong ca s Matlab: >> X=xlsread('D:\data.xls',1) >> u1=X(:,1) >> y1=X(:,2) >> save identdata u1 y1 >> ident // c d liu lu trong data1.xls // u vo in p bc nhy // u ra tc y1 // lu file d liu di dng identdata.mat // m ca s nhn dng
74
Hnh 3.3Chn u vo v m hnh nhn dng ca i tng
Hnh 3.4Phng thc nhn dng v nh gi m hnh thu c Sau khi tin hnh nhn dng chng ta thu c m hnh ca i tng vi hm truyn: WDT ( s ) =
K Vi =0.31528 ,T=0.0057876 , K=138.67 1 + 2 *Ts + (Ts ) 2
75
Hnh 3.5 c tnh qu i tng sau khi nhn dang
3.1.5. nh gi cht lng m hnh

Cng trong Toolbox ny Matlab cn cho ta thy sai lch tng i gia i tng nhn dng v tp d liu ban u thu thp c.
Hnh 3.6 Sai lch m hnh nhn dng C th nh gi sai lch m hnh thc i tng l khong 5.5% lc th chp nhn c. M hnh tng ng c in mt chiu chng ta nhn dng c l kh chnh xc.
76
3.2 Thit k lut iu khin PID

3.2.1. Phng php Ziegler-Nichols1
thit k b iu khin PID ta dng phng php Ziegler Nichols th nht da trn c s c tnh ca i tng .
T hnh v trn ta c L = 0,00375 ; T = 0,041v h s k = 71.2 Kp= 0.16 Ti = 0.0075 Td = 0.0019
3.2.2. Phng php IMC

Phng php ny c u im l thit k tnh ton cc tham s b iu khin PID cho tng loi m hnh i tng khc nahu qua mt s biu thc trung gian. Chng ta s dng phng php ny cho i tng ng c mt chiu l v n c sn lut thit k .i tng ng c in mt chiu c m hnh :
WDT ( s ) = K Vi =0.31528 ,T=0.0057876 , K=138.67 1 + 2 *Ts + (Ts ) 2
Ta c :
Chon tc=0.06 Kp=Ti/(tc*K)= 0.0004 Ti=2**T=0.00365=>Ki=0.12 Td=T/(2*)=0.092=>Kd=0.000037
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Thit k b iu khin PID s trn nn vi iu khin PIC 3.2.3. M phng v nh gi cht lng b iu khin
M hnh Simulink:
Hnh 3.7 M phng trn Simulink cc phng php iu khin
Hnh 3.9 c tnh m phng R dng hai phng php u cho c tnh h thng sai lch v o qu iu chnh bng khng nhng IMC cho ta thi gian qu Tqd=140ms, cn ZieglerNichols cho Tqd=230ms. Nh vy phng php IMC cho ta kt qu tt hn.
3.3 Thit b chp hnh(IC L298)

m nhim vai tr thit b chp hnh trong h thng iu khin thc thi thut ton iu khin l mch cng sut L298.L298 l mt Driver tch hp sn 2 mch cu H bn trong vi chun iu khin TTL, khng c Diode ni bo v Mosfet. Chu ti ti a trn mi cu l 2A, in p 40VDC. Logic 0 ng vo ln ti 1.5V ( kh nng kh nhiu cao). S dng dng ng gi Multiwatt15. Mt s c im ca mch cng sut L298: in p cp ln n 46V Tng dng DC chu ng ln n 4A Chc nng bo v qu nhit in p logic 0 t 0V n 1.5V nn tnh chng nhiu tt.
78
Hnh 3.10 S chn L298 Chc nng cc chn : MW.15 1.15 Power SO 2;19 Tn Sense A sense B 2;3 4;5 Out1 Out2 4 6 Vs Chc nng Ni chn ny qua in tr cm ng dng xung GND iu khin dng ti . Ng ra ca cu A . Dng ca ti mc gia 2 chn ny c qui nh bi chn 1. Chn cp ngun cho tng cng sut. Cn c mt t in khng cm khng 100nF ni gia chn ny v chn GND Chn ng vo ca cu A, tng thch chun TTL Chn ng vo enable (cho php) tng thch chun TTL. Mc thp chn ny s cm (disable) ng ra cu A (i vi chn EnableA) v/hoc cu B ( i vi chn EnableB) Chn t (Ground) Chn cp ngun cho khi logic. Cn c t in 100nF ni gia chn ny vi GND Cc chn logic ng vo ca cu B
5;7
7;9
Input1 Input2
6;11
8;14
EnableA EnableB
8 9 10;12
1;10;11;20 12 13;15
GND VSS Input3 Input4
13;14
16;17
Output3 Output4
Ng ra ca cu B. Dng ca ti mc gia hai chn ny c qui nh bi chn 15. Khng kt ni . 79
3;18
N.C
Hnh 3.11: Cc ch ca L298 Hai chn C,D ca L298 iu khin chiu ng c, phanh ng c. Chn Enable ca L298 dng lm u vo bm xung PWM cho ng c c th iu khin tc ng c. Bng ch ca trong qu trnh iu khin ng c : u vo M1A=1; M1B=0 M1E=1 M1E=0 M1A=0; M1B=1 M1A=M1B M1A=X; M1B=X Chc nng Tin ng c Li ng c Dng khn cp (phanh) Dng khng phanh
Trong thc t ng dng ny, ng c DC ch c dng ti 200mA khi hot ng bnh thng, v ln n ti a 2A khi qu ti. Tuy nhin cng cn thit k mt b iu khin m c th s dng cho cc ng c ln n 4A. Vic hn ch dng cho ng c l rt cn thit, c nhiu tnh hung khng mong i xy ra, v vy cn phi c ch hn dng bng phn mm. Trong cc trng hp nguy him nh ngn mch do va chm, hoc tut dy ni, cn c mch bo v chng ngn mch bng phn cng p ng kp thi. Cn iu khin PWM tn s cao trnh ting n do ng c to ra, nht l nhng ting ku nghe rt r khong tn s 1KHz n 3KHz. B iu khin PWM thng thng c iu khin 5KHz.Ni song song hai cu H iu khin ng c ln n 4A.
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Hnh 3.12 : S gii php L298 khng c Diode ni bo v, do cn c 4 Diode ngoi bo v. m bo iu khin PWM tn s cao, cn dng Diode nhanh c in tr thp. Diode chuyn dng iu khin ng c l cc Diode fast recovery Schottky. Nhng tn s khong 5KHz vn c th dng loi 1N4007. Lu rng, khi hot ng L298 rt nng, do vy cn cn phi lp ming tn nhit. Hai chn RC0 v RC1 iu khin chiu quay ca ng c: + ) RC0 = 1 v RC1 = 0 quay thun + ) RC0 = 0 v RC1 = 1 quay nghch + ) RC0 = RC1 = 0 hoc RC0 = RC1 = 1 ng c dng quay Chn PWM c a vo chn Enable ca L298, do vy ch cn iu chnh ln ca Dutycycle ca PWM ta c th iu chnh c in p u ra ca L298 a vo ng c ( 0V : 12V ).
3.4 Cm bin (Encoder)

Nguyen ly hoat ong cua cam bien encoder : co nhieu loai encoder khac nhau
nh : Encoder tiep xuc, Encoder t trng, Encoder quang (Encoder quang tng oi va Encoder quang tuyet oi). Moi loai lai co mot nguyen ly hoat ong khac nhau, trong khuon kho bao cao o an ch trnh bay phan nguyen ly loai encoder s dung la Encoder quang tng oi ( incremental encoder).
Mo hnh th 1
Hnh 3.13 : M hnh1 - En coder quang tng i
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Incremental encoder ve c ban la mot a tron quay quanh mot truc c uc lo nh hnh tren.
Hnh 3.14 : Phng thc hot ng Encoder quang tng i 2 ben mat cua cai a tron o, se co mot bo thu phat quang. Trong qua trnh encoder quay quanh truc, neu gap lo rong th anh sang chieu qua c, neu gap manh chan th tia sang khong chieu qua c. Do o tn hieu nhan c t sensor quang la mot chuoi xung. Moi encoder c che tao se biet san so xung tren mot vong. Do o ta co the dung vi ieu khien em so xung o trong mot n v thi gian va tnh ra toc o ong c. Cai encoder ma em s dung trong o an cua mnh, hoan toan giong vi mo hnh tren. Tuy nhien, mo hnh tren co nhc iem ln la : ta khong the xac nh c ong c quay trai hay quay phai, v co quay theo chieu nao i na th ch co mot dang xung a ra. Ngoai ra iem bat au cua ong c, ta cung khong the nao biet c. Cai tien mo hnh 1 bang mo hnh 2 nh sau:
Mo hnh th 2
Hnh 3.15 : M hnh 2 -En coder quang tng i
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Trong mo hnh nay, ngi ta uc tat ca la 2 vong lo. Vong ngoai cung giong nh mo hnh 1, vong gia pha so vi vong ngoai la 90 o. Khi o, dang xung ra t 2 vong tren nh sau :
Hnh 3.16 : S xung ca En coder quang tng i(m hnh 2) Hai xung a ra t 2 vong lech nhau 90 o, neu vong ngoai nhanh pha hn vong trong th chac chan ong c quay t trai sang phai va ngc lai. Mot lo vong trong cung dung e phat hien iem bat au cua ong c. Co the viet chng trnh cho vi ieu khien nhan biet : neu co mot xung phat ra t vong trong cung nay, tc la ong c a quay ung mot vong. Vi nhng ac tnh tren, encoder dung rat pho bien trong viec xac nh v tr goc cua ong c.. Van e quan trong trong viec tm mua nhng loai ong c co gan encoder nh the nay e lam o an oi vi sinh vien la : cap mat quang 2 ben encoder e tao xung thng b chet va khong co o thay the. Mot loai encoder th 2 cung pho bien hien nay, o la :absolute encoder. Mo hnh a quang cua loai nay nh sau:
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Cch tnh tc ng s s dng trong n n ng c c gn Encoder 100 xung/vng. Hai knh xung A v B c a vo hai chn ngt ca VK l INT1 , INT2. Ta thit lp khi c sn xung th to ngt. Do vy tng s xung trn 1 vng s c nhn i ln thnh 200 xung. Cch tnh tc : Tc = (Counter*60)/(200*T) y: T: l chu k trch mu Counter : l s xung m c trong khong thi gian T Trong n s dng T = 0.02 s nn : Tc = Counter * 15
3.5 H thng iu khin

Trn c s thit k b iu khin PID s chng 2 chng ta c th khi qut h thng iu khin ng c in mt chiu c dng:
Hnh 3.17 S h thngiu khin ng c
Hnh 3.18 Cu trc h thng iu khin
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C s nguyn l thc hin s iu khin tc ng c : - Thc hin iu khin ng c bng b iu khin thit k ci dt trn vi iu khin. - S dng encoder quang tng i dng d phn hi tc ng c. - Giao tip my tnh qua chun RS232 thng qua modul trn mch iu khin hin th c tnh h thng theo phng php iu ch rng xung PWM. - Trn mch c khi hin th LCD hin th cc ch hot ng ng c cng nh cc thng s: tc , in p iu khin
Hnh 3.19 Cu trc khi iu khin ng c
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3.6 Mt s hnh nh v Kit iu khin ng c s dng vi iu khin PIC
Mt s hnh nh mch iu khin ng c mt chiu
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3.7 :Kt qu thc nghim

B iu khin PI
Hnh 3.20 c tnh vi b iu khin PI B iu khin PID
Hnh 3.21 c tnh vi b iu khin PID
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Hnh 3.22 H thng khi c nhiu
Hnh 3.23 c tnh khi h thng c thay i gi tr t
3.8 So snh kt qu m phng v thc t

Da trn kt qu m phng trn Matlab v trn giao din chng trnh ta c th nh gi: - c tnh h thng sau thc hin b iu khin l tng i tt p ng ch tiu cht lng : qu iu chnh nh, thi gian qua nh khon 200-600ms - Trn giao din chng trnh vn thy r sai lch so m phng Matlab: c tnh cha tht mn, v vn tn ti sai s so vi tc t khong sai s dao ng t 2% ti 10%.
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Kt lun
Kt lun
Cc kt qu t c Trn c s thit k phn cng v phn mm khi thc hin n t c mt s kt qu sau: V phn cng: Tm hiu v vi iu khin Pic i su tm hiu mt s thut ton iu khin nh b iu khin PID, b iu khin m Nhn dng v m phng i tng iu khin (ng c mt chiu kch t c lp) trn Matlab. Thit k kit phn cng cho vi iu khin Pic 18F4520 c kh nng iu khin nhiu i tng (ng c mt chiu. l nhit). vi cc thut ton iu khin khc nhau To c giao din v giao tip c PC v vi iu khin trung tm
Mt s im hn ch Trong gian on lm n, chng em rt c gng nghin cu, thit k c c nhng kt qu nu trn. Tuy nhin do thi gian v kin thc ca chng em c hn, mt khc mt s iu kin v thit b khng cho php nn trong n cn nhng hn ch : S dng Encoder c phn gii cha cao nn vn gy ra nhiu sai s trong qu trnh tnh ton. Pic 18F4520 l dng vi iu khin 8 bits c tc tnh ton v b nh chng trnh khng ln nn kh p dng cho nhng b iu khin cn nhiu b nh nh : b iu khin m... Kt qu thu c vn c sai s so vi m hnh l tng thit k trn Matlab. Mt s modul trn Kit cha c khai thc.
Hng khc phc cc im hn ch Da trn c s hn ch chng ta c hng khc phc : C th s dng ng c c encoder 500 xung/vng hoc 1000 xung/vng khc phc sai s . S dng dng Pic 16 bits, 32 bits..........
Hng pht trin ti - Thit k b iu khin thch nghi PID, b iu khin m hc theo m hnh mu : FMRLC, hoc b iu khin ng dng mng Nron.
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Kt lun
M rng thm cc i tng thc m Kit c th lm vic c nh l nhit, bnh mc Do l do v thi gian nhng l do khch quan khc nn n c thc hin vn cn nhiu khim khuyt. Chng em rt mong nhn c nhng kin ng gp qu bu ca cc thy c. Mt ln na, chng em xin chn thnh cm n c gio PGS.TS Phan Xun Minh hng dn chng em tn tnh trong qu trnh thc hin n ny. ----------------------------o0o----------------------------
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Ph lc- Ti liu tham kho
Ti liu tham kho

1. Nguyn Phng Quang, Andreas Dittrich Truyn ng in thng minh NXB KHKT, 2002
2. Nguyn Tng Cng, Phan Quc Thng Cu trc v lp trnh h vi iu khin 8051 3. Nguyn Don Phc : L thuyt iu khin tuyn tnh. Nh xut bn khoa hc k thut, 2005 4. Nguyn Phng Quang : Matlab & Simulink dnh cho k s iu khin t ng. Nh xut bn khoa hc k thut, 2005 5. Nguyn Phng Quang : Bi ging iu kin s 6. Nguyn Vn Ho : T ng ho qu trnh cng ngh 7. Hong Minh Sn : iu khin qu trnh 8. Phm Cng Ng (ch bin) : T hc Visual C++ t c bn n nng cao. Nh xut bn thng k, 2002 9. Dng Thy V : Phng php tnh. Nh xut bn khoa hc k thut, 2002 10. Bi Quc Khnh, Nguyn Vn Lin & Nguyn Th Hin : Truyn ng in. Nh xut bn khoa hc k thut, 2006 11. Hng MicroSoft : MSDN Library for Visual Studio 2005 12. Hng Texas Instruments : datasheet MAX232 13. Hng microchip:datasheet 18F4520 14. Hng ST : datasheet L298 15. www.dientuvietnam.net 16. www.diendandientu.com
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Ph lc Code phn mm
Ph lc Code phn mm
//code bn phm// #ifndef __pvc_keypad_H #define __pvc_keypad_H #define row1 PORTAbits.RA2 #define row2 PORTAbits.RA3 #define row3 PORTAbits.RA4 #define row4 PORTAbits.RA5 #define col1 PORTBbits.RB4 #define col2 PORTBbits.RB5 #define col3 PORTBbits.RB6 #define col4 PORTBbits.RB7 /*******************************************************************/ unsigned char col(void) { col4 = 1; if (row1 & row2 & row3 & row4) { col4 = 0; return 4; } col4 = 0; col3 = 1; if (row1 & row2 & row3 & row4) { col3 = 0; return 3; } col3 = 0; col2 = 1; if (row1 & row2 & row3 & row4) { col2 = 0; return 2; } col2 = 0; col1 = 1; if (row1 & row2 & row3 & row4) { col1 = 0; return 1; } col1 = 0; }
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Ph lc Code phn mm
/*************************************************************/ unsigned char row(void) { if (!row4) return 4; else if (!row3) return 3; else if (!row2) return 2; else if (!row1) return 1; } /************************************************************/ unsigned char get_keypad(void) { if((col()==1) && (row()==1)) return 7; if((col()==1) && (row()==2)) return 4; if((col()==1) && (row()==3)) return 1; if((col()==1) && (row()==4)) return 0; if((col()==2) && (row()==1)) if((col()==2) && (row()==2)) if((col()==2) && (row()==3)) if((col()==2) && (row()==4)) if((col()==3) && (row()==1)) if((col()==3) && (row()==2)) if((col()==3) && (row()==3)) if((col()==3) && (row()==4)) if((col()==4) && (row()==1)) if((col()==4) && (row()==2)) if((col()==4) && (row()==3)) if((col()==4) && (row()==4)) } #endif /////// code LCD///// #ifndef __pvc_lcd_H #define __pvc_lcd_H #define #define #define #define LCD_RS PORTEbits.RE1 LCD_RW PORTCbits.RC3 LCD_E PORTEbits.RE2 LCD_DATA PORTD return return return return return return return return return return return return 8; 5; 2; 'Q'; 9; 6; 3; 'L'; 'P'; 'V'; 'C'; 'M';
/***************************************************************/ void busy_lcd (void)
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Ph lc Code phn mm
{ unsigned char data; TRISD=0xff; LCD_RS=0; LCD_RW=1; do { LCD_E=1; Delay10TCYx(2); LCD_E=0; data=PORTD; data=data&0x80; } while(data==0x80); } /*****************************************************************/ void write_cmd_lcd(char cmd) { busy_lcd(); TRISD=0x00; LCD_RW = 0; LCD_RS = 0; LCD_E = 1; LCD_DATA = cmd; LCD_E = 0; } /****************************************************************/ void init_lcd (void) { write_cmd_lcd(0b00111000); write_cmd_lcd(0b00001100); write_cmd_lcd(0b00000110); write_cmd_lcd(0b00000001); write_cmd_lcd(0x02); } /****************************************************************/ void write_data_lcd(char data) { if(data=='\n') { write_cmd_lcd(0xC0); // Dua con tro ve dau dong thu 2 return; } if(data=='\1') {
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Ph lc Code phn mm
write_cmd_lcd(0x01); return; } busy_lcd(); TRISD=0x00; LCD_RW = 0; LCD_RS = 1; LCD_E = 1; LCD_DATA = data; LCD_E = 0; } /*****************************************************************/ void write_str_lcd(char *str) { while(*str) { write_data_lcd(*str); str++; } } #endif /******************************************* CPU PIC18F4520 Frequency 40MHz *******************************************/ #include<stdio.h> #include<p18f4520.h> #include<delays.h> #include<adc.h> #include<timers.h> #include<pvc_lcd.h> #include<pvc_keypad.h> #include<pwm.h> #include<usart.h> //============================================ #pragma config OSC=HSPLL #pragma config BOREN=OFF #pragma config WDT=OFF // Xoa man hinh hien thi
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Ph lc Code phn mm
#pragma config #pragma config #pragma config #pragma config MCLRE=ON PBADEN=OFF LVP=OFF PWRT=ON
long vc=0; long w=0; long pc=0,ic=0,dc=0; char p_h=0,p_l=0,i_h=0,i_l=0,d_h=0,d_l=0; char mode=0; char w_h=0,w_l=0; //============================================= char flag=0; char co_tocdo=0; char timer0_flag=0; //============================================= float u_p=0,u_i=0,u_d=0,k_p=0,k_i=0; //long u=0,v=0; float u=0,v=0; float e=0; float pre_e=0; float sum_e=0; float tocdothuc=0; float pre_tocdothuc=0; float pre_ui=0; float pre_u=0; unsigned long counter=0,dienap=0; unsigned long tocdodat=0; unsigned int dutycycle=0; //============================================= unsigned char temp,msg[35]; unsigned int j=0; unsigned int jlcd=0; unsigned short long k=0; unsigned int k_usart=0; char pad=0;
96
Ph lc Code phn mm
char message[35]; char pvcm[32]={"\1 Pham Van Manh \n My Brother "}; void delay10ms (void) { Delay10KTCYx(10); } void delay500ms (void) { Delay10KTCYx(500); } void counter1_isr(void); void counter2_isr(void); void usart_isr(void); void keypad_isr(void); void timer0_isr(void); void pvc(void) { e= tocdodat - tocdothuc; u_p =pc*e; u_i=pre_ui + 0.0457*ic*pre_e ; u_d=dc*(e-pre_e)/0.0457; u= (u_p+u_i+u_d/10)/12800; pre_e=e; pre_ui=u_i; if(u>=11.8) { u=11.8; sum_e -= e; } if(u<=0) { u=0; sum_e -= e; } dutycycle = 256*u/12;
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Ph lc Code phn mm
SetDCPWM1(dutycycle); return; } //=============================================== #pragma code high_vector=0x08 void interrupt_at_high_vector(void) { _asm GOTO keypad_isr _endasm } #pragma code //=================================== #pragma interrupt keypad_isr void keypad_isr(void) { INTCONbits.INT0IF=0; delay10ms(); co_tocdo=1; if(!(row1 & row2 & row3 & row4)) { pad = get_keypad(); if (pad>=0 && pad<=9) sprintf(&message[0],"\1 KeyPad = %u ",pad); else sprintf(&message[0],"\1 KeyPad = %c ",pad); write_str_lcd(&message[0]); } } //************************************************* #pragma code low_vector = 0x18 void interurrupt_at_low_vector(void) { if(INTCON3bits.INT1IF) { _asm GOTO counter1_isr _endasm } if(INTCON3bits.INT2IF)
98
Ph lc Code phn mm
{ _asm GOTO counter2_isr _endasm } if(PIR1bits.RCIF) { _asm GOTO usart_isr _endasm } if(INTCONbits.TMR0IF) { _asm GOTO timer0_isr _endasm } } //******************************************************************** #pragma interruptlow usart_isr void usart_isr(void) { INTCONbits.GIE = 0; pad=0; if(k_usart==0) { mode=ReadUSART(); } if(k_usart==1) { w_h = ReadUSART(); } if(k_usart==2) { w_l = ReadUSART(); } if(k_usart==3) { p_h = ReadUSART(); } if(k_usart==4) {
99
Ph lc Code phn mm
p_l = ReadUSART(); } if(k_usart==5) { i_h = ReadUSART(); } if(k_usart==6) { i_l = ReadUSART(); } if(k_usart==7) { d_h = ReadUSART(); } if(k_usart==8) { d_l = ReadUSART(); k_usart=0; flag=1; } else k_usart++; INTCONbits.GIE = 1; } //======================================== #pragma interruptlow counter1_isr void counter1_isr(void) { counter++; INTCON3bits.INT1IF=0; } //ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc #pragma interruptlow counter2_isr void counter2_isr(void) { counter++; INTCON3bits.INT2IF=0;
100
Ph lc Code phn mm
} //ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc //tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt #pragma interruptlow timer0_isr void timer0_isr(void) { INTCONbits.GIE = 0; if(j<7)//0.026s { j++; } else { j=0; tocdothuc = counter*6.565; counter=0; timer0_flag=1; } INTCONbits.TMR0IF=0; INTCONbits.GIE = 1; } //tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt void main() { OpenUSART (USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_HIGH,64); OpenADC( ADC_FOSC_32 &ADC_RIGHT_JUST &ADC_6_TAD,ADC_CH0&ADC_INT_OFF, 0); RCONbits.IPEN=1; // cho phep uu tien ngat
101
Ph lc Code phn mm
INTCON=0xC0; // mo tat ca cac ngat INTCONbits.INT0IE =1; INTCON2=0x00; // ngat tai INT1,INT2 on falling edge INTCON2bits.TMR0IP=0; //Ngat timer0 thap INTCON3=0x18; // cho phep ngat INT1,INT2 PIE1bits.RCIE=1; IPR1bits.RCIP=0; PIE1bits.TXIE=0; // Khong cho ngat khi truyen du lieu ADCON1 = 0x0d; TRISC = 0x80; PORTCbits.RC5 =1; TRISD = 0x00; TRISE = 0x00; TRISA = 0xff; TRISB = 0b00001111; // Khoi tao cho Kepad PORTB = 0X00; // Khoi tao cho Kepad ADCON1 = 0x0E; // Lay nguon la 5V va 0v cua mach init_lcd(); write_str_lcd(&pvcm[0]); OpenTimer2( TIMER_INT_OFF & T2_PS_1_1 & T2_POST_1_16 ); delay500ms(); PORTCbits.RC5 = 1; //----------------------------------------------------------------------------------while(1) { //fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ff if(flag) { while(1) {
102
Ph lc Code phn mm
flag=0; sum_e=0; k=0; j=0; counter=0; if((pad=='P')||(pad=='V')||(pad=='M')||(pad=='Q')) break; if(mode) { tocdodat= w_h*256 + w_l; pc=p_h*256+p_l; ic=i_h*256+i_l; dc=d_h*256+d_l; OpenPWM1(63);//156.25kHz 256 PORTCbits.RC0 = 0; PORTCbits.RC1 = 1; } else { dutycycle=0; ClosePWM1(); tocdodat=0; PORTCbits.RC0 = 0; PORTCbits.RC1 = 0; pc=0; ic=0; dc=0; u=0; v=0; pre_u=0; pre_ui=0; pre_e=0; sum_e=0; }
103
Ph lc Code phn mm
OpenTimer0( TIMER_INT_ON & T0_8BIT & T0_SOURCE_INT & T0_PS_1_256 ); while(1) { if((pad=='P')||(pad=='V')||(pad=='M')||(pad=='Q')||(flag==1)) break;
if(timer0_flag) { timer0_flag=0; k++; jlcd++; pvc(); } if(k==2) { k=0; w=tocdothuc; while (BusyUSART()); WriteUSART(w/256); while (BusyUSART()); WriteUSART(w%256); while (BusyUSART()); vc=u*1000; WriteUSART(vc/256); while (BusyUSART()); WriteUSART(vc%256); } if(jlcd==10) { jlcd=0; w=tocdothuc;
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Ph lc Code phn mm
sprintf(&msg[0],"\1 Toc do la: \n %lu (rpm)",w); write_str_lcd(&msg[0]); } } } } //ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff //pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp if(pad=='P') { while(1) {
if((pad=='V')||(pad==0)||(pad=='M')||(pad=='C')) break; OpenPWM1(63);//156.25khz 256 SetDCPWM1(192);// 9V PORTCbits.RC0 = 0; PORTCbits.RC1 = 1; OpenTimer0( TIMER_INT_ON & T0_8BIT &
T0_SOURCE_INT & T0_PS_1_256 ); while(1) { if((pad=='V')||(pad==0)||(pad=='M')||(pad=='C')) break; if(timer0_flag)
105
Ph lc Code phn mm
{ timer0_flag=0; w=tocdothuc; while (BusyUSART()); WriteUSART(w/256); while (BusyUSART()); WriteUSART(w%256); while (BusyUSART()); WriteUSART(9000/256); while (BusyUSART()); WriteUSART(9000%256); sprintf(&msg[0],"\1 Toc do la: \n %lu (rpm)",w); write_str_lcd(&msg[0]); } } } } //pppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppppp //vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv if(pad=='V') { while(1) { if((pad==0)||(pad=='P')||(pad=='M')||(pad=='C')) break; dutycycle=0; ClosePWM1(); tocdodat=0; pc=0; ic=0; dc=0;
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Ph lc Code phn mm
pre_e=0; sum_e=0; u=0; v=0; pre_u=0; pre_ui=0; PORTCbits.RC0 = 0; PORTCbits.RC1 = 0; write_str_lcd(&pvcm[0]); } } //vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv //ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc if(pad=='C') { tocdodat=0; sprintf(&message[0],"\1Nhap toc do:\nNhan L de OK"); write_str_lcd(&message[0]); do{ if(co_tocdo) { co_tocdo=0; if((pad>=0)&&(pad<=9)) { tocdodat=tocdodat+pad; sprintf(&message[0],"\1V dat: %lu (rpm)\nNhan L de OK ",tocdodat); write_str_lcd(&message[0]); tocdodat=tocdodat*10; } } } while(pad !='L'); tocdodat = tocdodat/10;
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Ph lc Code phn mm
while(1) { sprintf(&message[0],"\1V dat: %lu (rpm)\nNhan Q(M) de chay ",tocdodat); write_str_lcd(&message[0]); if((pad==0)||(pad=='P')||(pad=='V')||(pad=='M')||(pad=='C')||(pad=='Q')) break; } } //ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc //mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm if(pad=='M') { OpenPWM1(63);//156.25kHz 256 PORTCbits.RC0 = 0; PORTCbits.RC1 = 1; OpenTimer0( TIMER_INT_ON & T0_8BIT &
T0_SOURCE_INT & T0_PS_1_256 ); pc=5; ic=300; sum_e=0; while(1) { if((pad=='P')||(pad=='V')||(pad=='C')||(pad=='Q')||(pad==0)) break; if(timer0_flag) { timer0_flag=0; jlcd++; pvc();
108
Ph lc Code phn mm
} if(jlcd==10) { jlcd=0; w=tocdothuc; sprintf(&msg[0],"\1W dat: %lu(rpm)\nW thuc: %lu(rpm)",tocdodat,w); write_str_lcd(&msg[0]); } } } //mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm //qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq if(pad=='Q') { OpenPWM1(63);//156.25kHz 256 PORTCbits.RC0 = 0; PORTCbits.RC1 = 1; OpenTimer0( TIMER_INT_ON & T0_8BIT &
T0_SOURCE_INT & T0_PS_1_256 );
pc=5; ic=400; sum_e=0; while(1) { if((pad=='P')||(pad=='V')||(pad=='C')||(pad=='M')||(pad==0)) break;
109
Ph lc Code phn mm
if(timer0_flag) { timer0_flag=0; jlcd++; pvc(); } if(jlcd==10) { jlcd=0; w=tocdothuc; sprintf(&msg[0],"\1W %lu(rpm)",tocdodat,w); write_str_lcd(&msg[0]); } } } //qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq //-------------------------------------------------------------------------------------------------} }
dat:
%lu(rpm)\nW
thuc:
110

Thiết kế BDK PID số trên nền VDK PIC

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Trng i hc bch khoa h ni Khoa in

Kt lun ............................................................................................. 89 Ti liu tham kho ............................................................................. 91 Ph lc Code phn mm.................................................................... 92

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Chng 1: H vi iu khin PIC v vi iu khin PIC18F4520

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1.2 . Vi iu khin Pic18F4520

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Hnh 1.1 S khi kin trc vi iu khin PIC18F4520

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Chn 1( MCLR /VPP/RE3) :

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Vi iu khin Pic 1.2.1. T chc b nh (Memory Organization)

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Hnh 1.4: S a ch ngn xp

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Hnh 1.5: Clock/Instruction Cycle

Hnh 1.6 Instruction Pipeline Flow

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Vi iu khin Pic B nh chng trnh Flash (Flash Program Memory)

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Flash Program Operation During Code Protection

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Vi iu khin Pic B nh d liu EEPROM (Data EEPROM Memory)

1.2.2. 8 x 8 HARDWARE MULTIPLIER

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Vi iu khin Pic 1.2.3. Ngt (Interrupts)

Hnh 1.10 Pic 18 Interrup logic

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1.2.4. Cng vo ra (I/O Port)

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1.2.5. B nh thi (Timer)

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Thanh ghi iu khin v trng thi truyn

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B pht tc baud (BRG)

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Vi iu khin Pic Ch EUSART khng ng b.

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