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Assignment - 1st

M.C.E.S
SUBMITTED TO: MS. Sandeep Kaur
SUBMITTED BY: Abhishek Sharma ROLL NO.- 935 E.C.E - 6TH SEM.

Ques 1. The 8051 Architecture Explained!

The first task faced when learning to use a new computer is to become familiar with the capability of the machine. The features of the computer are best learned by studying the internal hardware design, also called the architecture of the device, to determine the type, number, and size of the registers and other circuitry. The hardware is manipulated by an accompanying set of program instructions, or software, which is usually studied next. Once familiar with the hardware and software, the system designer can then apply the microcontroller to the problems at hand.

The 8051 microcontroller actually includes a whole family of microcontrollers that have numbers ranging from 8031 to 8751 and are available in N-Channel Metal Oxide Silicon (NMOS) and Complementary Metal Oxide Silicon (CMOS) construction in a variety of package types. An enhanced version of the 8051, the 8052, also exists with its own family of variations and even includes one member that can be programmed in BASIC. Internal ROM and RAM I/0 ports with programmable pins Timers and counters Serial data communication

8051 Microcontroller Hardware

The block diagram of the 8051 in Figure 2.la shows all of the features unique to Microcontrollers:

The 8051 architecture consists of these specific features:

Eight-bit CPU with registers A (the accumulator) and B Sixteen-bit program counter (PC) and data pointer (DPTR) Eight-bit program status word (PSW) Eight-bit stack pointer (SP) Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051) Internal RAM of 128 bytes Four register banks, each containing eight registers Sixteen bytes, which may be addressed at the bit level Eighty bytes of general-purpose data memory Thirty-two input/output pins arranged as four 8-bit ports: PO-P3 Two 16-bit timer/counters: TO and TI Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three internal interrupt sources Oscillator and clock circuits

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The heart of the 8051 is the circuitry that generates the clock pulses by which all internal operations are synchronized. Pins XTALI and XTAL2 are provided for connecting a resonant network to form an oscillator. Typically, a quartz crystal and capacitors are employed, as shown in Figure 2.3. The crystal frequency is the basic internal clock frequency of the microcontroller. The manufacturers make available 8051 designs that can run at specified maximum and minimum

The model is complicated by the number of special-purpose registers that must be present to make a microcomputer a microcontroller. A cursory inspection of the model is recommended for the firsttime viewer; return to the model as needed while progressing through the remainder of the text.

The 8051 Oscillator and Clock

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frequencies, typically I megahertz to 16 megahertz. Minimum frequencies imply that some internal memories are dynamic and must always operate above a minimum frequency, or data will be lost.

The 8051 contains two 16-bit registers: the program counter (PC) and the data pointer (DPTR). Each is used to hold the address of a byte in memory. Program instruction bytes are fetched from locations in memory that are addressed by the PC. Program ROM may be on the chip at addresses OOOOh to OFFFh, external to the chip for addresses that exceed OFFFh, or totally external for all addresses from OOOOh to FFFFh. The PC is automatically incremented after every instruction byte is fetched and may also be altered by certain instructions. The PC is the only register that does not have an internal address.

Program Counter and Data Pointer

A and B CPU Registers

Flags are 1-bit registers provided to store the results of certain program instructions. Other instructions can test the condition of the flags and make decisions based upon the flag states. In order that the flags may be conveniently addressed, they are grouped inside the program status word (PSW) and the power control (PCON) registers.

The 8051 contains 34 general-purpose, or working, registers. Two of these, registers A and B, comprise the mathematical core of the 8051 central processing unit (CPU). The other 32 are arranged as part of internal RAM in four banks, B0-83, of eight registers each, named RO to R7.

Flags and the Program Status Word (PSW)

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Internal Memory

The 8051 operations that do not use the internal 128-byte RAM addresses from OOh to 7Fh are done by a group of specific internal registers, each called a special-function register (SFR), which may be addressed much like internal RAM, using addresses from 80h to FFh.

The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. The 8-bit stack pointer (SP) register is used by the 8051 to hold an internal RAM address that is called the "top of the stack." The address held in the SP register is the location in internal RAM where the last byte of data was stored by a stack operation.

A functioning computer must have memory for program code bytes, commonly in ROM, and RAM memory for variable data that can be altered as the program runs. The 8051 has internal RAM and ROM memory for these functions. Additional memory can be added externally using suitable circuits.

The Stack and the Stack Pointer

Special Function Registers

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Some SFRs are also bit addressable, as is the case for the bit area of RAM. This feature allows the programmer to change only what needs to be altered, leaving the remaining bits in that SFR unchanged. Not all of the addresses from SOh to FFh are used for SFRs, and attempting to use an address that is not defined, or "empty," results in unpredictable results. In Figure 2. I b, the SFR addresses are shown in the upper right corner of each block. The SFR names and equivalent internal RAM addresses are given in the following table:

SFRs are named in certain opcodes by their functional names, such as A or THO, and are referenced by other opcodes by their addresses, such as OEOh or 8Ch. Note that any address used in the program must start with a number; thus address EOh for the A SFR begins with 0. Failure to use this number convention will result in an assembler error when the program is assembled.

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Input/output Pins, Ports, and Circuits

One major feature of a microcontroller is the versatility built into the input/output (110) circuits that connect the 8051 to the outside world. As noted in Chapter I, microprocessor designs must add additional chips to interface with external circuitry; this ability is built into the microcontroller. To be commercially viable, the 8051 had to incorporate as many functions as were technically and economically feasible. The main constraint that limits numerous functions is the number of pins available to the 8051 circuit designers. The DIP has 40 pins, and the success of the design in the marketplace was determined by the flexibility built into the use of these pins.

Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-directional low order address and data bus for external memory. For example, when a pin is to be used as an input, a I must be written to the corresponding port 0 latch by the program, thus turning both of the output transistors off, which in turn causes the pin to "float" in a high impedance state, and the pin is essentially connected to the input buffer.

Port 0

Port 2 may be used as an input/output port similar in operation to port I. The alternate use of port 2 is to supply a high-order address byte in conjunction with the port 0 low-order byte to address external memory. Port 2 pins are momentarily changed by the address control signals when supplying the high byte of a 16-bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around (set to I) for data input as is the case for port 0.

Port I pins have no dual functions. Therefore, the output latch is connected directly to the gate of the lower FET, which has an FET circuit labeled "Internal FET Pullup" as an active pullup load. Used as an input, a 1 is written to the latch, turning the lower FET off; the pin and the input to the pin buffer are pulled high by the FET load. An external circuit can overcome the high impedance pull up and drive the pin low to input a 0 or leave the input high for a 1.

Port 1

Port 2

Port 3 is an input/output port similar to port I. The input and output functions can be programmed under the control of the P3 latches or under the control of various other special function registers. The port 3 alternate uses are shown in the following table:

Port 3

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The system designer is not limited hy the amount of internal RAM and ROM available on chip. Two separate external memory spaces are made available by the 16-bit PC and DPTR and by different control pins for enabling external ROM and RAM chips. Internal control circuitry accesses the correct physical memory, depending upon the machine cycle state and the opcode being executed.

Unlike ports 0 and 2, which can have external addressing functions and change all eight port bits when in alternate use, each pin of port 3 may be individually programmed to be used either as 1!0 or as one of the alternate functions.

External Memory

A computer program has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump on the states of flags and port pins. The second responds to hardware signals. called interrupts, that force the program to call a sub-routine. Software techniques use up processor time that could be devoted to other tasks; interrupts take processor time only when action by the program is needed. Most applications of microcontrollers involve responding to events quickly enough to control the environment that generates the events (generically termed "real time programming"). Interrupts are often the only way in which real-time programming can be done successfully.

External RAM, which is accessed by the DPTR, may also be needed when 128 bytes of internal data storage is not sufficient. External RAM, up to 64K bytes, may also be added to any chip in the 8051 family.

Interrupts

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Pins INTO and INTI are used by external circuitry. Inputs on these pins can set the interrupt flags lEO and lEI in the TCON register to I by two different methods. The lEX flags may be set when the INTX pin signal reaches a low level, or the flags may be set when a high-to-low transition takes place on the INTX pin. Bits ITO and ITI in TCON program the INTX pins for low-level interrupt when set to 0 and program the INTX pins for transition interrupt when set to 1. A reset can be considered to be the ultimate interrupt because the program may not block the action of the voltage on the RST pin. This type of interrupt is often called "nonmaskable," since no combination of bits in any register can stop, or mask the reset action. Unlike other interrupts, the PC is not stored for later program resumption; a reset is an absolute command to jump to program address OOOOh and commence running from there.

External Interrupts

Reset

Internal RAM is not changed by a reset; however, the states of the internal RAM when power is first applied to the 8051 are random. Register bank 0 is selected upon reset as all hits in PSW are 0.

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Ques 2. Intel 8085 Microprocessor Family


Intel 8085 had single 5 Volt power supply. Clock oscillator and system controller were integrated on the chip. The CPU included serial I/O port.

Intel 8085 microprocessor is the next generation of Intel 8080 CPU family. In addition to being faster than the 8080, the 8085 had the following enhancements: Two new instructions were added to 8085 instruction set. The CPU also included a few undocumented instructions. These instructions were supposed to be a part of the CPU instruction set, but at the last moment they were left undocumented because they were not compatible with forthcoming Intel 8086.

There were multiple versions of 8085 microprocessors. The original version of the 8085 microprocessor without suffix "A" was manufactured by Intel only, and was very quickly replaced with 8085A containing bug fixes. A few years after that, around 1980, Intel introduced 8085AH HMOS version of 8085A. There was also 80C85A - CMOS version of the 8085A. It's not clear if 80C85 was ever manufactured by Intel or not, but it was produced by at least two second source manufacturers - OKI and Tundra Semiconductor. Tundra Semiconductor manufactured the fastest 8085 microprocessor running at 8 MHz. Intel 8086 microprocessor is a first member of x86 family of processors. Advertised as a "sourcecode compatible" with Intel 8080 and Intel 8085 processors, the 8086 was not object code compatible with them. The 8086 has complete 16-bit architecture - 16-bit internal registers, 16-bit data bus, and 20-bit address bus (1 MB of physical memory). Because the processor has 16-bit index registers and memory pointers, it can effectively address only 64 KB of memory. To address memory beyond 64 KB the CPU uses segment registers - these registers specify memory locations for code, stack, data and extra data 64 KB segments.

Intel 8086

The segments can be positioned anywhere in memory, and, if necessary, user programs can change their position. This addressing method has one big advantage - it is very easy to write memoryindependent code when the size of code, stack and data is smaller than 64 KB each. The complexity of the code and programming increases, sometimes significantly, when the size of stack, data and/code is larger than 64 KB. To support different variations of this awkward memory addressing scheme many 8086 compilers included 6 different memory models: tiny, small, compact, medium, large and huge. 64 KB direct addressing limitation was eliminated with the introduction of the 32bit protected mode in Intel 80386 processor.

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Intel 80186

Intel 80186 microprocessor, sometimes called i186, is an enhanced version of Intel 8086 16-bit processor. Being completely object code compatible with the 8086, the 80186 integrated many system components into one chip, added 7 new instructions, and added new operand types to three existing 8086 instructions. With the exception of integrated components, the Intel 80186 microprocessor is not very different from the 8086, and, because of this, the 80186 may be considered as an embedded version of 8086. The 80186 didn't even have its own version of co-processor and worked with Intel 8087. Although the Intel 80186 was not widely used in the computers as the 8086 and 80286 did, it was successful in embedded processor market. In fact, the processor was so successful, that many different versions of the processor were introduced over last 20 years - 80C186 (new features), 80186EA, 80186EB, etc. At this time (September 2006) some of these versions are still in production.

The second generation of x86 16-bit processors, Intel 80286, was released in 1982. The major new feature of the 80286 microprocessor was protected mode. When switched to this mode, the CPU could address up to 16 MB of operating memory (previous generation of 8086/8088 microprocessors was limited to 1 MB). In the protected mode it was possible to protect memory and other system resources from user programs - this feature was necessary for real program multitasking. There were many operating systems that utilized the 80286 protected mode: OS/2 1.x, Venix, SCO Xenix 286, and others. While this mode was useful for multitasking operating systems, it was of limited use for systems that required execution of existing x86 programs. The protected mode couldn't run multiple virtual 8086 programs, and had other limitations as well:

Intel 80286

Currently the 80286 protected mode is not used by x86 operating systems. All modern 32-bit x86based operating systems use 80386 protected mode that was introduced by next generation of Intel x86 processors. The Intel 80286 microprocessor included new protected mode and all real-mode instructions that were introduced by 80186/80188 processors. Execution time of many real-mode instructions was reduced.

80286 was a 16-bit microprocessor. Although in protected mode the CPU could address up to 16 MB of memory, this was implemented using memory segments. Maximum size of memory segment was still 64 KB. There was no fast and reliable way to switch back to real mode from protected mode.

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Intel 80386

The third x86 generation of x86 microprocessors, Intel 80386 (i386) was a 32-bit microprocessor backwards compatible with previous generations of 80x86 CPUs. Major new feature in the i386 CPU was 80386 protected mode - this mode fixed many shortcomings that existed in the 80286 processor and in the 80286 protected mode:

There were a few different versions of the 80386 CPUs:

Intel 80486

The Intel 80386 was produced at speeds up to 33 MHz, AMD produced even faster 40 MHz version. The successor to the 80386 processor, Intel 80486 (i486) included many changes to its microarchitecture that resulted in significant performance improvements:

80386DX - this CPU could work with 16-bit and 32-bit external buses. 80386SX - low cost version of the 80386. This processor had 16 bit external data bus and 24-bit external address bus. 80386SL - low-power microprocessor with power management features, with 16-bit external data bus and 24-bit external address bus. The processor included ISA bus controller, memory controller and cache controller. Embedded 80376 and 80386EX processors.

The 80386 mode included complete set of 32-bit registers and 32-bit instructions. Although in this mode the CPU still used memory segment architecture similar to the one present in earlier x86 microprocessors, the size of memory segments was increased to 4 GB. This simplified development of 32-bit software, and in most cases applications could run without worrying about switching memory segments. It became possible to switch from protected mode back to real-mode without simulating processor reset.

8 KB unified level 1 cache for code and data was added to the CPU. In later versions of the 80486 the size of level 1 cache was increased to 16 KB. Execution time of instructions was significantly reduced. Many load, store and arithmetic instructions executed in just one cycle (assuming that the data was already in the cache). Intel 486 featured much faster bus transfers - 1 CPU cycle as opposed to two or more CPU cycles for the 80386 bus. Floating-point unit was integrated into 80486DX CPUs. This eliminated delay in communications between the CPU and FPU. Furthermore, all floating-point instructions were optimized - they required fewer number of CPU cycles to execute. Power management features and System Management Mode (SMM) became a standard feature of the processor. Intel 80486 microprocessor was produced at speeds up to 100

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Intel Pentium

Fifth generation of x86 family, Intel Pentium microprocessor was the first x86 superscalar CPU. The processor included two pipelined integer units which could execute up to two integer instructions per CPU cycle. Redesigned Floating Point Unit considerably improved performance of floating-point operations and could execute up to 1 FP instruction per CPU cycle. Other enhancements to Pentium core included: To improve data transfer rates the size of data bus was increased to 64 bits. At first Pentium processors featured separate 8 KB code and 8 KB data caches. The size of both data and code L1 caches was doubled in Pentium processors with MMX technology. Intel Pentium CPU used branch prediction to improve effectiveness of pipeline architecture. Branch prediction was enhanced in Pentium MMX processors. Many desktop Pentiums could work in dual-processor systems. To reduce CPU power consumption the core voltage was reduced on all Pentium MMX, and many mobile and embedded Pentium processors.

MHz. AMD produced even faster 120 and 133 MHz versions of the 80486, and manufactured in small quantities 150 MHz and possibly 166 MHz versions.

Intel Itanium

Later versions of Pentium processors - Pentium MMX - included 57 new instructions. These instructions could be used to speed up processing of multimedia and communication applications. Like the Pentium processors, the Pentium MMX CPUs were also produced in three different versions - desktop, mobile and embedded processors.

Intel manufactured desktop, mobile and embedded versions of Pentium microprocessors. Distinguishing between different versions of Pentiums is not always easy because desktop, mobile and/or embedded Pentiums often used the same part numbers. In some cases Pentium processors with the same part and S-spec numbers were offered as desktop and embedded, or mobile and embedded microprocessors.

The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with other superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. The first Itanium processor, codenamed Merced, was released in 2001.Itanium-based systems have been produced by HP (the HP Integrity Servers line) and several other manufacturers.

Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel markets the processors for enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel.

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