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CNG NGH CH TO VI MCH IN T (MICROELECTRONICS & TECHNOLOGY PROCESSES)

Dr. DANG TRONG-TRINH Email: trinhqtu@yahoo.com Tel: 09 84 70 90 15

Microelectronic & Technology processes

Plan

Mn hc ny nhm cung cp cc kin thc v: + Cng ngh bn dn & cng ngh vi in t (Semiconductor & Microelectronic) + Cc qu trnh cng ngh (Technology processes) ch to linh kin in t + Qui trnh cng ngh sn xut vi mch (IC fabrication). + Xu th cng ngh v linh kin nano (nanotechnology & nanodevices)

Dang Trong-Trinh, trinhqtu@yahoo.com

Microelectronic & Technology processes

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Plan

Content
Chng 1. Tng quan v cng ngh ch to vi in t & nn cng nghip bn dn 1.1. Cng ngh vi in t (microelectronic technology) 1.2. Cng ngh bn dn (Semiconductor technology) 1.3. Cc cng on cng ngh chnh (Technology processes) 1.4. Tim nng v xu hng (Strategies & trends) Chng 2. Vt liu bn dn (Semiconductor materials) 2.1. Gin nng lng (energy diagram) 2.2. Tinh th hc v cu trc tinh th (crystal structure) 2.3. Khuyt tt tinh th & pha tp (dopage) 2.4. Cc loi cht bn dn Chng 3. Sn xut (wafer) 3.1. Cc loi wafer 3.2. Cc c tnh ca wafer 3.3. Cc phng php ch to wafer 3.4. Nui tinh th: Crystal growth (Czochralski, Float Zone, polishing, gettering, challenges) Chng 4. Layout v mt n (mask) trong sn xut vi in t 4.1. Layout & qu trnh lm layout 4.2. Mt n v vai tr trong sn xut vi in t 4.3. Qu trnh sn xut mask

Dang Trong-Trinh, trinhqtu@yahoo.com

Microelectronic & Technology processes

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Plan
Chng 5: Cc qui trnh n l trong sn xut chip 5.1 Khc v n mn (Lithography & Etching) Quang khc: cht cn quang Resist, thit b v qui trnh Li trong qu trnh photolithography Gii hn ca phng php photolithography Etching: n mn t & n mn t Etching: dry reactive ion-etching, anisotropic etches 5.2. Phng php pha tp K thut khuch tn (diffusion) Cy ion (Ion implantation) 5.3. Oxy ha nhit (Oxidation) Qu trnh oxy ha Si thnh SiO2 5.4. Phng php to mng mng (Deposition techniques) Phng php bay hi chn khng vt l (PVD) Phn x (sputtering) Phng php kt ta ha hc pha hi (CVD) Phng php CVD p sut kh quyn (APCVD) Phng php CVD p sut thp (LPCVD) Phng php CVD tng cng ca Plasma (PECVD) CVD mng kim loi K thut mc mn (Epitaxy)

Chng 6. Cng ngh MOSFET v CMOS Cc tnh cht c bn ca linh kin MOSFET Cc cng ngh MOS truyn thng & quy trnh ch to MOSFET Cng ngh CMOS v qui trnh ch to. Chng 7: Xu th cng ngh Xu th cng ngh: gim kch thc linh kin MOSFET Cng ngh Nanotechnology MEMS, NEMS

Dang Trong-Trinh, trinhqtu@yahoo.com

Microelectronic & Technology processes

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Plan

IC manufacturing process
Dang Trong-Trinh, trinhqtu@yahoo.com Microelectronic & Technology processes Page 5

Plan
Discussion:

Topic 01: Fab or Fabless in Vietnam Topic 02: Technology simulation vs. Device (IC) simulation Topic 03: MEMS fabrication vs. IC fabrication Topic 04: 3D integration technology Topic 05: Nanotechnology & Nanoelectronics Topic 06: Strained Silicon technology Topic 07: 22-nm Semiconductor technology Topic 08: Metrology: ellipsometry, profilometry, reflectrometry, TEM/SEM, parameter analyzer. Topic 09: Environment, Safety & Health in Semiconductor fabrication Topic 10: Introduce the other semiconductor materials: Ge, GaAs, SiC, GaN, GaP, AlGaAs Topic 11: Draw the layout of the the logic gates: NOT, NAND2, NOR2. Topic 12: Diffusion process: fick model, concentration dependent models, field effect, band-gap narrowing effect, anomalous effects. Present the simulator Suprem. Topic 13: Oxidation process: Deal-grove model, rate constant (linera & parabol), high pressure oxidation, dopant effects during oxidation, two & three-dimensional effects, defects during oxidation. Topic 14: Epitaxy process: surface process & reations, MOCVD, MBE, CBE, UHV-CVD.
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Dang Trong-Trinh, trinhqtu@yahoo.com

References

Textbooks:
1. Silicon Processing for the VLSI Era, Volume 1 Process Technology, 2nd, S. Wolf and R.N. Tauber, Lattice Press. 2. Introduction to VLSI Systems, Mead C. and Conway L.; Addison-Wesley. ISBN 0-201-04358-0. 3. CMOS VLSI Design A Circuits and Systems Perspective, (3rd Edition) Neil Weste and David Harris Addison Wesley ISBN: 0-321-14901-7.

Websites:
Background knowledge: http://hyperphysics.phy-astr.gsu.edu/hbase/hframe.html Microelectronic system news: http://www-ece.engr.utk.edu/~bouldin/MUGSTUFF/HTML/allnl.html Deep Submicron VLSI Design: http://www.ece.rutgers.edu/~bushnell/dsmdesign/dsmwebpage.html Cadence Design Tool tutorial : http://www.vlsi.wpi.edu/cds/flow.html International Technology Roadmap for Semiconductor: http://www.itrs.net IC knowledge: http://www.icknowledge.com/ http://ecee.colorado.edu/~bart/book/book/chapter3/ch3_1.htm Dang Trong-Trinh, trinhqtu@yahoo.com Microelectronic & Technology processes Page 7

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