Alteras User-Customizable ARM-Based SoC FPGAs

Design the Way You Want

What if you could select the intellectual property (IP) and peripherals you need to quickly create a custom system on a chip (SoC) tailored to fit your application? What if you could consolidate two discrete devices into one, reducing system power, cost, and board size while increasing performance? What if you could use this chip to differentiate your end product in both hardware and software? Now you can design that custom device with the Altera SoC FPGA devices, the newest members of our popular 28 nm Cyclone V and Arria V families. Our SoC FPGA devices help you keep up with changing market requirements and interface standards. We include a wide range of system peripherals, Altera IP, custom IP, and third-party IP that lets you quickly create a custom system using Altera design tools. Start software development today using the SoC FPGA Virtual Target prototyping tool.

What Is an SoC FPGA?

Our SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of a dual-core ARM processor, peripherals, and memory controllers with the FPGA fabric using a high-bandwidth interconnect backbone. The SoC FPGA is ideal for: Reducing system power, cost and board space by integrating two chips the processor and FPGA into one Differentiating your end product in both hardware and software Adding support for virtually any interface standard in the FPGA Extending product life and revenue through hardware and software updates in the field Improving system performance via high-throughput data paths between the HPS and the FPGA

SoC FPGAs

2012

www.altera.com/socfpga

SoC FPGA Hard Processor System

Single- or Dual-Core Processor Hard Processor System (HPS) ARM Cortex-A9 NEON/FPU L1 Cache

HPS I/O

FPGA

HPS

ARM Cortex-A9 NEON/FPU L1 Cache

USB OTG (x2) (1) GPIO

Ethernet (x2) (1) I2 C (x2) CAN (x2) UART (x2) FPGA Configuration

L2 Cache JTAG Debug/Trace (1) NANDFlash Hard Memory Controller* Transceivers* Hard PCIe*
*Optional Configuration
(1) (2)

64Kbyte RAM QSPI Flash Controller

Timers (x11) SD/SDIO/ MMC (1) HPS to FPGA

SPI (x2) DMA FPGA to HPS

Shared Multiport DDR SDRAM Controller (2)

(1)

Integrated DMA

(2)

Integrated ECC

ARM-Based Hard Processor System

The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of peripherals, and a multiport memory controller shared with logic in the FPGA. The HPS gives you the flexibility of programmable logic combined with the performance and cost savings of hard IP. Embedded peripherals eliminate the need to implement these functions in programmable logic, leaving more FPGA resources for application-specific custom logic and reducing power consumption The hard multiport SDRAM memory controller, shared by the processor and FPGA logic, supports DDR2, DDR3, and LPDDR2 devices with an integrated error-correction code (ECC) support for high reliability and safety-critical applications.

High-Speed Interconnect
High-throughput data paths between the HPS and FPGA fabric provide interconnect performance not possible in two-chip solutions. The tight integration between the HPS and FPGA fabric provides over 125-Gbps peak bandwidth with integrated data coherency between the processors and the FPGA.

Flexible FPGA Fabric

The flexibility offered by the FPGA logic fabric lets you differentiate your system by implementing custom IP or off-the-shelf preconfigured IP from Altera or its partners into your designs. This allows you to: Adapt quickly to varying or changing interface and protocol standards Add custom hardware in the FPGA to accelerate time-critical algorithms and create a compelling competitive edge Reduce power consumption and FPGA resource requirements by leveraging hard logic functions within the FPGA, including PCI Express (PCIe) ports and additional multiport memory controllers
SoC FPGAs

2012

www.altera.com/socfpga

SoC FPGAs: Extending the 28 nm FPGA Portfolio

Altera offers a full 28 nm device portfolio that is tailored to your design requirements. Our SoC FPGAs join this family of Cyclone V and Arria V FPGAs. Youll find dozens of devices that optimize requirements in areas such as performance, I/O resources, package size, power, and cost. Whats more, you can take advantage of the 28 nm device families common, productivity-enhancing design environment for faster design.

FPGAs for All Your Needs

Cyclone V FPGAs provide the industrys lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. You get up to 40 percent lower total power versus the previous generation, efficient logic integration capabilities, and integrated transceiver options. You also get up to 150-GMACS and 100-GFLOPS digital signal processing (DSP) performance with our variable-precision DSP blocks. Cyclone V SoC FPGA devices offer a single- or dual-core Cortex-A9 processor, depending on your performance needs. The Cyclone V family comes in six tailored options: Cyclone V E FPGA with logic only Cyclone V GX FPGA with 3.125-Gbps transceivers Cyclone V GT FPGA with 5-Gbps transceivers Cyclone V SE SoC FPGA with ARM-based HPS Cyclone V SX SoC FPGA with ARM-based HPS and 3.125-Gbps transceivers Cyclone V ST SoC FPGA with ARM-based HPS and 5-Gbps transceivers

Arria V FPGAs balance cost and power with performance for mid-range applications such as remote radio heads, LTE base stations, and multifunction printers. You get high system performance due to a fast FPGA fabric, fast I/Os, and fast transceiver data rates. The DSP-rich Arria V FPGA fabric delivers up to 1,600-GMACS and 300-GFLOPS performance while helping you meet your cost and power requirements for applications in this space. The Arria V family comes in four tailored options: Arria V GX FPGA with 6.5536-Gbps transceivers Arria V GT FPGA with up to 10.3125-Gbps transceivers Arria V SX SoC FPGA with ARM-based HPS and 6.5536-Gbps transceivers Arria V ST SoC FPGA with ARM-based HPS and up to 10.3125-Gbps transceivers

SoC FPGAs

2012

www.altera.com/socfpga

SoC FPGA Family1

Family KLE 25 Cyclone V SoC 40 85 110 Arria V SoC 350 460 Block Memory Bits (Mb) 1.4 2.2 4.0 5.1 17.3 22.8 Var. Prec. Multiplier Blocks 36 58 87 112 809 1,068 Max. FPGA User I/Os 145 145 288 288 528 528 HPS Dedicated I/Os 188 188 188 188 216 216 Max. Transceivers (GP) 6 6 9 9 30 / 16 30 / 16 Per -Transceiver Max. Data Rate (Gbps) 3.125 3.125 5 5 6 / 10 6 / 10 SOC Hard Memory Controller 1 1 1 1 1 1 FPGA Hard Memory Controllers 1 1 1 1 3 3 Hard PCIe 2 ea, Gen1 2 ea, Gen1 2 ea, Gen2 2 ea, Gen2 2 ea, Gen2 2 ea, Gen2

SoC FPGA Packages1

Non-Transceiver Devices (FPGA User I/Os) Family KLE U484-WB 19x19 66 66 66 66 161 U672-WB 23x23 145 145 145 145 188 F896-WB 31x31 288 288 188 U672-WB 23x23 (I/O, 3G) 145, 6 145, 6 145, 9 145, 9 188 Transceiver Devices (FPGA User I/Os, Transceivers) F896-WB 31x31 (I/O, 3G/5G) 288, 9 288, 9 188 F896-FC 31x31 (I/O, 6G, 10G) 178, 12, 4 178, 12, 4 216 F1152-FC 35x35 (I/O, 6G, 10G) 350, 18, 8 350, 18, 8 216 F1517-FC 40x40 (I/O, 6G, 10G) 528, 30, 16 528, 30, 16 216

25 Cyclone V SoC Arria V SoC FPGA HPS I/O

1

40 85 110 350 460

All data is preliminary

28 nm SoC Enhancements
Built on TSMCs 28 nm low power (28LP) process technology, the Cyclone V and Arria V SoC FPGA families provide low power consumption and feature significant architecture enhancements including: Efficient 8-input adaptive logic module (ALM) New 10-Kb (M10K) internal memory blocks New 640-bit memory logic array blocks (MLABs) Variable-precision DSP blocks Fractional phase-locked loops (fPLLs) to reduce external oscillator needs Highly flexible clocking network Power-optimized MultiTrack routing architecture Both families integrate an abundance of hard IP blocks. These hard IP blocks consume less power, ease your design process, and provide you with more logic resources for developing differentiated product features versus soft logic implementations and include: Hard memory controllers PCIe Gen2 with multifunction support To protect your valuable IP investments, the SoC FPGAs provide additional design protection, including features such as 256-bit Advanced Encryption Standard with volatile and non-volatile keys.
SoC FPGAs

2012

www.altera.com/socfpga

Why Design with an SoC FPGA?

SoC FPGAs provide the performance, power, and cost savings of hard logic with the flexibility and time-to-market benefits of programmable logic.

Lower System Power

SoC FPGAs leverage the Altera-optimized low-power 28 nm (28LP) process technology and integrate low-power serial transceivers to meet increasing bandwidth needs.
Cyclone V SoC FPGA 3.125 Gbps 75 mW per channel 5 Gbps 88 mW per channel Arria V SoC FPGA 3 Gbps <80 mW per channel 6.5536 Gbps <100 mW per channel 10.3125 Gbps <140 mW per channel

The HPS running at 800 MHz delivers 4,000 MIPS* while consuming less than 1.8 W. HPS power can be controlled dynamically through on-chip clock frequency management, CPU clock gating, wait for event/interrupt sleep modes, and low-power memory controller I/O modes. To reduce SoC FPGA power further, you can power down the FPGA independently, then power up and configure the FPGA under program control when needed.

Lower System Cost

To help you lower your system cost, we have designed our SoC FPGAs so you can reduce design time and bill of materials (BOM) compared to multichip solutions. Fewer power supplies required two power rails for Cyclone V SoC FPGA and three for Arria V SoC FPGA Fewer oscillators required fractional PLLs reduce the number of oscillators required on your board, and the number of clock pins used in the device by synthesizing multiple clock frequencies from a single reference clock source Fewer FPGA resources required hard PCIe ports and multiport memory controllers in the FPGA fabric eliminate the need to implement these features in programmable logic FPGA Configuration via Protocol using PCIe reduces the cost for non-volatile configuration devices

* Dhrystones 2.1 benchmark

6 SoC FPGAs

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Smaller Board Size

Integrating the FPGA, microprocessor, and DSP discrete devices into a single chip allows you to minimize the number of devices on the board, saving board space, reducing complexity, routing constraints, and PCB cost.

Increased Performance
SoC FPGAs offer the best of both worlds, combining the performance and broad embedded software ecosystem of a dual-core ARM Cortex-A9 MPCore processor with the flexibility of Alteras latest 28 nm FPGA fabric. Tight integration between the two provides system interconnect performance not possible in two-chip solutions. More than 125-Gbps processor to FPGA interconnect backbone 4,000 MIPS CPU processing performance (for < 1.8 W) Up to 150-GMACS and 100-GFLOPS peak DSP performance in Cyclone V SoC FPGA Up to 1,600-GMACS and 300-GFLOPS peak DSP performance in Arria V SoC FPGA

Customize Your SoC

Choose from a broad range of soft IP cores from Altera and third-party IP partners to quickly create a custom ARM processor system with our Qsys system integration tool. Create your own custom IP to accelerate time-critical functions, or add functionality to create a unique competitive advantage and extend your product life. The flexible FPGA fabric lets you design for changing industry standards and market requirements. Reuse collections of IP functions as subsystems for scalable system development.

Rich ARM Ecosystem

Alteras SoC FPGAs inherit the rich ARM ecosystem, giving you the ability to leverage the extensive ARM ecosystem with software development tools, operating systems, middleware, and debuggers. The ARM Cortex-A9 MPCore processor architecture builds on ARMs success in the embedded systems market and is widely supported by industry-leading embedded software providers.

SoC FPGAs

2012

www.altera.com/socfpga

Where You Can Use Our SoC FPGAs

We understand the requirements of end market solutions that drive silicon and IP development. Thats why we optimized the SoC FPGAs for real-world applications. Example applications ideally suited for Cyclone V and Arria V SoC FPGAs:
Applications for SoC FPGA by Device Industry Target Applications Industrial I/O Factory Automation Industrial networking Programmable logic controllers (PLCs)/human machine interface (HMI), drives, servos Renewable energy, transmission and distribution, secure communication IP camera Key Functions Sensor interfaces, safety Industrial communication/network protocol bridging, safety Control loop, energy-efficient inverter, communication protocols, I/O, safety Inverter, power management, protection relays, communication standards, security, and safety Wide dynamic range (WDR) camera, high-definition (HD )video, advanced video analytics Video processing, video analytics, communication Signal processing, baseband processing Routing protocols, link management, OAM Audio and video CODEC, video over IP, PCIe capture, video and image processing Video and image processing Data processing, control and deep packet inspection Ultrasound imaging, signal processing Scan and print algorithms, temperature voltage monitoring/remote access Cyclone V SoC 25 40 85 110 Arria V SoC 350 460

Smart Energy Video Surveillance Automotive Wireless Infrastructure Wireline Communications Broadcast Defense & Aerospace Medical Compute and Storage

Advanced driver assistance, infotainment Remote radio unit, LTE mobile backhaul Router, access, Edge equipment Studio, video conferencing, professional audio/visual (A/V) Night vision, secure communications Intelligence, instrumentation Diagnostic imaging, instrumentation Multifunction printer, chassis management

SoC FPGAs

2012

www.altera.com/socfpga

Common Development Tools Make Design Easier

Software Tools
A set of common software tools and design resources equips you to swiftly turn your concepts into revenue-generating applications. Our SoC FPGAs inherit the rich software development ecosystem available for ARM Cortex-A9 MPCore processors, including software development tools, operating systems, and middleware. This ecosystem compatibility ensures you can stay productive with familiar tools and reuse legacy software to shorten the development cycle. You can follow the same software development process for our SoC FPGA devices that you do with other embedded processors. Altera and its ecosystem partners provide tool choices for each step of the process, from board bring-up to building Linux kernels to debugging application software. We provide comprehensive operating system (OS) support including Linux, Wind River VxWorks, and more. Using our reference Linux kernel or board support packages for other operating systems, you can immediately start OS-based application development.

Hardware Tools
Our productivity-enhancing Quartus II software development environment, featuring the Qsys system integration tool, makes development easier for hardware designers. Qsys saves you time and effort in the FPGA design process, simplifying development of complex hardware systems.

Faster Development
Easy-to-use GUI interface enables quick integration of IP functions and subsystems Automatic generation of interconnect logic and automatic HDL generation of your system Hierarchical design flow enables scalable designs, supports team-based design, and maximizes design reuse Support for a wide range of IP interface standards including ARM AMBA/AXI, Avalon Memory-Mapped, and Avalon Streaming interfaces Automatic generation of a simulation model, software header file, and data sheet to expedite development across hardware and software teams

Faster Timing Closure

High-performance Qsys interconnect based on the network-on-a chip (NoC) architecture User control of pipelining to meet fMAX and latency system requirements

Faster Verification
Automatic testbench generation and verification IP suite let you start your simulation faster Ability to bring your board up faster by sending read and write transactions into a live system for debug
SoC FPGAs

2012

www.altera.com/socfpga

Start Developing Software Today

We provide virtual prototyping tools for SoC FPGA devices, enabling you to start early, work more productively, improve your software quality, and ultimately, get to market faster. The SoC FPGA Virtual Target provides development and debugging capabilities that are hard or impossible to find for real hardware.

Real I/O Connectivity on Host PC

PC-Based Simulation for SoC FPGA Development Board

Optional FPGA-in-the-Loop Extension

Ethernet Peripherals Peripherals DDR USB Flash

FPGA for Custom IP

Hardened CPU Hardened CPU

Interface IP

Custom IP

Custom IP

The Virtual Target is a fast functional simulation of an embedded development board. Its a register- and binarycompatible equivalent to the hardware that it simulates. While the Virtual Target runs on a Windows or Linux PC, you can use it the same way you use a development board run your OS and application code, connect to it using standard ARM development tools, and then develop and debug your firmware and application software.

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SoC FPGAs

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Ready to Learn More?

With Alteras ARM-based SoC FPGAs, you can reduce board size, system power, and system cost while increasing system performance. Our 28 nm portfolio continues to reinvent programmable logic, enabling you to create differentiated and more complex solutions with less time and effort. If youre ready to learn more, contact your local Altera representative or visit our website for white papers, webcasts, and technical details on SoC FPGAs.

Visit: www.altera.com/socfpga

SoC FPGAs

2012

www.altera.com/socfpga

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2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and are trademarks or registered trademarks in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal. September 2012 Broch 1004-1.1