3 - STM32F General Purpose Lines

STM32 Seminar STM32F General G l Purpose P Lines Li
COMPEL/STM Seminar November 2010
Seminar Agenda
Overview of ST Microcontroller Portfolio Introduction to Cortex-M Core STM32 General Purpose Lines
Product-Line Overview (F100/F101/F103) Walk through the main peripherals ST Standard Peripheral Library Live demonstration of the STM32 Value Discovery Kit Product-Line Overview (L15x) Low-Power modes and consumption Specific Peripherals Product-Line Overview (F105/7 & next) Ethernet & USB Host Peripherals Third Party Stacks Audio Support pp Product-Line Overview (W108) RF Performances Wireless Stacks (Zigbee, RF4CE, proprietary) Third Party Compiler & IDE Boards and Debuger ST Libraries
STM32 Low Low-Power Power Line

STM32 Connectivity Line

STM32 Wireless

STM32 Tools

STM32 Seminar November 2010
STM32F10x Product Lines

All lines include:
Multiple communication peripherals Up to 5 x USART, 3xSPI, 2xIC ETM* FSMC** Dual 12-bit DAC*** Multiple 16-bit Timers Main Osc 4-16MHz (25MHz on 105/107) Internal I t l 8 MHz MH RC and 40 kHz RC Real Time Clock with Battery domain & 32KHz ext osc 2 x Watchdogs Reset circuitry and Brown Out Warning Up to 12 DMA cnls
* Performance/Access Lines 256KB, 384KB, or 512KB devices and ALL Connectivity devices
Connectivity Line: STM32F107

72MHz CPU Up to 256 KB Flash / 64KB SRAM 2x12-bit ADC (1s) TempSensor USB 2.0 OTG (FS) 2 x Audio Class I2S 2x CAN PWM timer Ethernet IEEE158 8
Connectivity Line: STM32F105

72MHz CPU Up to 256 KB Flash / 64KB SRAM 2x12-bit ADC (1s) TempSensor USB 2.0 OTG (FS) 2 x Audio Class I2S 2x CAN PWM timer
Performance Line: STM32F103

72MHz CPU Up to 1MB Flash / 96KB SRAM 2/3x12-bit ADC (1s) TempSensor USBFS Device SDIO* I2S* CAN PWM timer
USB Access Line: STM32F102

48MHz CPU Up to 128KB Flash / 16KB SRAM 1x12-bit ADC (1s) T Temp sensor USBFS Device
Access Line: STM32F101

36MHz CPU Up to 1MB Flash / 80KB SRAM 1x12-bit ADC (1s) Temp sensor
Value Line: STM32F100

24MHz CPU Up to 512KB Flash / 32KB SRAM 1x12-bit ADC (1 2s) (1.2s) Temp sensor HDMICEC PWM timer
** 256KB, 384KB, or 512KB Performance and Access devices *** 256KB, 384KB, or 512KB devices except Value line where present on all memory range
STM32 General Purpose Portfolio

Flash (bytes)
1 MB 768 K 512 K 384 K 256 K

Connectivity line Performance and Access line Value line
STM32F103/1RE STM32F103/1RE STM32F103/1RE STM32F100RE STM32F103/1RD STM32F100RD STM32F105/7RC STM32F103/1RC STM32F100RC STM32F105/7RB
STM32F103/1VE STM32F103/1VE STM32F103/1VE STM32F100VE STM32F103/1VD STM32F100VD STM32F105/7VC STM32F103/1VC STM32F100VC STM32F105/7VB STM32F103VB STM32F101VB STM32F105V8 STM32F103/1V8 STM32F100V8
STM32F103/1ZE STM32F103/1ZE STM32F103/1ZE STM32F100ZE STM32F103/1ZD STM32F100ZD
PIN TO PIN C COMPAT TIBLE
STM32F103/1ZC STM32F100ZC
128 K
STM32F103/2/1CB STM32F100CB
STM32F103/2/1RB STM32F100RB STM32F105R8
64 K 32 K 16 K
STM32F103/1T8
STM32F103/2/1C8 STM32F100C8
STM32F103/2/1R8 STM32F100R8 STM32F103R6 STM32F100R6 STM32F103/2/1R4 STM32F100R4
STM32F103/1T6
STM32F103/2/1C6 STM32F100C6
CortexTM-M3 CPU
4- to 4 t 64-Kbyte 64 Kb t SRAM 6 lines Full compatibility across 115part numbers
STM32F103/1T4
STM32F103/2/1C4 STM32F100C4
36 pins i QFN
48 pins i LQFP
64 pins i LQFP/BGA(1)
100 pins i LQFP
144 pins i LQFP/BGA(1)
STM32s I/O peripherals

High-performance analog
12-bit ADC with 1 s conversion 12 12-bit bit DAC DAC*
General-purpose I/O
Fully configurable 18 MHz max toggle rate
Advanced timers
Multi-mode 16-bit timers Motor control timers* Watchdog and SysTick timers Real-time clock with battery backup
*Device dependant
STM32s connectivity and system peripherals

Connectivity
4.5 Mbit/s USARTs 18 Mbit/s SPI with SDIO support* 400 kHz IC USB device* de ice* CAN* IS* USB OTG* Ethernet*
System S t peripherals i h l
12-channel DMA controller* Flexible system memory controller (FSMC)*
*Device dependant
STM32 maximum integration Clocks
Advanced PLLs for single Xtal operation or core and a d pe peripherals p e as Accurate RC oscillator with trimming register Power-on reset Low-voltage detect (brown-out) Watchdog timers Tamper detect
Reset circuitry
System security Power management
I Integrated t t d low-voltage l lt regulator l t for f single i l 2.0 2 0 V to t 3.3 V operation Clock enable/disable for each peripheral
STM3210x low-power characteristics

Typ @ 25 C
Low-voltage 2.0 V to 3.6 V operation
<14 A
Run mode ~ 0.5 mA/MHz 0.27 mA/MHz peripheral off Startup time from stop <6 s Startup time from standby 50 s
3.4 A
Stop - All clocks off, reset active, RAM on (register content preserved)
Stop 2 A Standby RTC on 0 9 A 0.9 A Standby RTC off RTC Vbat
Standby - All clocks off, reset active, RAM off but 20 bytes available for backup
STM32F103 Performance Line

Flash I/F
FSMC ETM SDIO IS 12 channels DMA 2 PWM ti 2xPWM timers 3xADCs Up to 112 I/Os (144 pins package)
JTAG/SW Debug ETM
Nested vect IT Ctrl
A ARM Lite Hi-Speed Bus Ma atrix / Arbiter (max 36/ 72MHz z)
2-channel 12-bit DAC
CORTEXTM-M3 CPU
72 MHz
256kB - 512kB Flash Memory
Power Supply
Reg 1.8V
POR/PDR/PVD XTAL oscillators

32KHz + 4~16MHz
32kB - 64kB SRAM 84B Backup Data FSMC

SRAM/ NOR/NAND/CF/ LCD parallel interface
Int. RC oscillators
40KHz + 8MHz
PLL RTC / AWU
1 x Systick Timer DMA up to 12 Channels

SDIO
SD/SDIO/MMC/CE-ATA
Clock Control Bridge

ARM Peripheral Bus
(max 36MHz)
Bridge
Synchronized AC Timer
1 x USB 2.0FS 1 x CAN 2.0B 2 x SPI / IS 4 x USART/LIN

Smartcard / IrDa M d Modem C Control t l
ARM P Peripheral Bus s
2 x 16-bit PWM
6 x 16-bit 16 bi Timer Ti
(ma ax 72MHz)
Up to 16 Ext. ITs Up to 112 I/Os 1 x SPI 1 x USART/LIN

Smartcard/IrDa Modem Control
2 x Watchdog
(independent & window)
2-channel 12-bit DAC 3 x 12-bit ADC / 1Msps up to 21 channels
Temperature Sensor
2 x I2C
STM32F103 Access Line

Flash I/F
FSMC ETM 12 channels DMA Up to 112 I/Os (144 pins package)

JTAG/SW Debug ETM
Nested vect IT Ctrl
A ARM Lite Hi i-Speed 36us Ma atrix / Arbiter (max 36/ 72MHz z)
2-channel 12-bit DAC
CORTEXTM-M3 CPU
36 MHz
256kB - 512kB Flash Memory
Power Supply
Reg 1.8V

32KHz + 4~16MHz
4kB - 48kB SRAM 84B Backup Data FSMC

Int. RC oscillators
40KHz + 8MHz
PLL RTC / AWU

ARM Peripheral Bus
(max 36MHz)
Bridge ARM P Peripheral Bus s 6 x 16-bit 16 bi Timer Ti

(ma ax 36MHz)

2 x Watchdog
2 x SPI 4 x USART/LIN
Smartcard / IrDa M d Modem C Control t l
Temperature Sensor
2 x I2C
More flexibility with STM32 XL Density

Doubles available Flash up to 1 Mbyte with p to 96 Kbytes y of SRAM up
New devices in both Access and Performance lines
Additional extra features

Six additional 16-bit timers Memory Protection Unit (MPU)
News features benefit in application

Two 512-Kbyte banks of Flash for safe inapplication software upgrading Additional timers for motor control or factory automation applications MPU to protect specific code or data
STM32F10x XL Density
Fla ash I/F
up to 1MB Flash up to t 96KB RAM MPU (transparent for the user if not used) 6 additional timers RWW Flash
CORTEXTM-M3 CPU + MPU

72 MHz ARM M Lite Hi-Speed Bus Matri ix / Arbiter (ma ax 36/ 72MHz)
784KB 1MB Flash Memory
Power Supply
Reg 1.8V

32KHz + 4~16MHz
80kB-96KB SRAM 84B Backup p Data FSMC

JTAG/SW Debug g ETM

Nested vect IT Ctrl
Int. RC oscillators
40KHz + 8MHz
PLL RTC / AWU

SDIO
SD/SDIO/MMC/CE-ATA

ARM Peripheral Bus
(max 36MHz)
Bridge g
1 x USB 2.0FS 1 x CAN 2.0B 2 x SPI / IS 4 x USART/LIN

Smartcard / IrDa Modem Control
ARM Peri ipheral Bus
2 x 16-bit PWM
10 x 16-bit Timer
(max 7 72MHz)

2 x Watchdog
T Temperature t Sensor S
2 x I2C
STM32 Value line 256K-512KBytes

Flash I/F
Core and operating conditions

ARM Cortex-M3 Cortex M3 1 1.25 25 DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 C
CORTEXTM-M3 CPU 24 MHz ARM Lite HiA -Speed 36us

Matrix / Arbiter (max 24MHz)
256KB-512kB Flash Memory
Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators

32KHz + 4~25MHz
24KB-32kB SRAM 84B Backup Data FSMC SRAM/ NOR/ LCD parallel interface Clock Control
ARM Peripheral Bus
JTAG/SW Debug
Nested Vect IT Ctrl
Int. RC oscillators
40KHz + 8MHz
Rich connectivity
11 communications peripherals
1 x Systick Timer
PLL RTC / AWU
DMA
FSMC
SRAM, NOR, memories support. LCD Parallel interface 8/16-bit Intel 8080 and Motorola 68K
up to t 12 Ch Channels l
Bridge Bridge
(max 24MHz)
1 x 16-bit PWM
ARM P Peripheral Bus
10 x 16-bit Timer
(ma ax 24MHz)
Enhanced control
16-bit motor control timer 10x 16-bit PWM timers
1 x CEC
Up to 16 Ext. ITs 51/80/112 I/Os 1 x SPI
2 x Watchdog
4 x USART/LIN
2 x12-bit DAC
Smartcard / IrDa Modem Control
LQFP64, LQFP100, LQFP144
1 x 12-bit ADC
up to 16 channels
1 x USART/LIN
2 x SPI 2 x I2C
Temperature Sensor
STM32 Value line key features

High-performance core
ARM Cortex-M3 zero wait state 1.25 DMIPS/MHz
up to 30 DMIPS at 24 MHz max
Essential features for appliances, consumer and industrial

Seven PWM 16-bit timers including motor control timer, fast 1.2 s 12-bit ADC & dual 12-bit DAC Consumer Electronic Control (CEC) hardware function Fl ibl St Flexible Static ti M Memory C Controller t ll (FSMC) addressing dd i SRAM, SRAM PSRAM, PSRAM NOR external t l memories LCD parallel interface support
Devices s >=256 KB B Flash only ly
From 16-Kbyte up to 512-Kbyte Flash From 48-pin to 144-pin packages Under $1 most accessible STM32
From $0 $0.85 85 (resale 10 Ku) for 16-Kbyte devices in LQFP48 package
STM32 in action (alarm control panel)

To phone line, alarm sensors and I/Os
5 UARTs, 3 SPI, 2 IC 5 timers, up to 112 I/Os 3 ADC, 21 channels 2 DACs
Serial coms and I/Os
FSMC IS
Interface to audio DAC for hi fi audio hi-fi di quality lit Parallel interface to graphic module
Audio for the user Voice and music SD card for software upgrade
SDI O
QVGA LCD
SD Wi-Fi card to home network
STM32 W Walk-Through lk Th h the th Peripherals
Memory Mapping and Boot Modes - MD

Addressable memory space of 4 GBytes RAM : up to 96 kBytes FLASH : up to 1024 kBytes Boot modes D Depending di on th the B Boot t configuration, fi ti E Embedded b dd d Fl Flash h Memory, System Memory or Embedded SRAM Memory is aliased at @0x00
BOOT Mode Selection Pins BOOT1 x
0x1FFF F80F 0x1FFF F800 0x1FFF F7FF 0x1FFF F000
0xFFFF FFFF
Reserved
0xE010 0000 0xE00F FFFF
0xE000 0000
Cortex-M3 internal peripherals
Boot Mode
Aliasing
BOOT0 0 1 1 User Flash User Flash is selected as boot space SystemMemory is selected as boot space Embedded SRAM is selected as boot space
Reserved Reserved O ti Bytes Option B t SystemMemory
0 1
SystemMemory Embedded SRAM
Reserved
0x4000 0000
Peripherals
Reserved
0x0801 FFFF
SystemMemory: contains the Bootloader used to re-program the FLASH through USART1.
For more details refer to AN2606 & UM0462 A PC Windows Demonstrator is available as well.
Flash
0x0800 0000
0x2000 0000
SRAM
Reserved
0x0000 0000
CODE
Bit-Band region
Boot from SRAM : In the application initialization code you have to Relocate the Vector Table in SRAM using the NVIC Exception Table and Offset register
System Architecture - MD
Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
BusMatrix added to Harvard architecture allows parallel access
Effi i t DMA and Efficient d Rapid R id data d t flow fl

Direct path to SRAM through arbiter, guarantees alternating access Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
Increase Peripherals Speed for better performance

Dual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and Low Speed APB (APB1) up to 36MHz
Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz toggling I/Os)
Flash I/F
I-bus
CORTEX-M3
D-bus
FLASH
Bu usMatrix x
Master 1
System
SRAM Slave
APB2 AHB
GP-DMA GP DMA Master 2
AHB-APB2 AHB APB2 AHB-APB1

Bridges
GPIOA,B,C,D,E - AFIO USART1- SPI1 - ADC1,2 TIM1 - EXTI USART2,3 - SPI2 - I2C1,2 TIM2,3,4 - IWDG WWDG USB CAN BKP PWR
APB1
Arbiter
Buses are not overloaded with data movement tasks
Embedded FLASH
Flash Features Overview

Flash Features:
Up to 1024KBytes 1 or 2 KByte KB t Page P size i Endurance: 10k cycles Memory organization:
Main memory block Information block
Access time: 35ns Halfword (16-bit) program time: 52.5 s (Typ) Page / Mass Erase Time: 20ms
Flash interface (FLITF) Features:

Read Interface with pre-fetch buffer Option Bytes loader Flash program/Erase operations Types of Protection:
Readout Protection Write Protection
Flash Memory Accelerator

Mission: Support 72 MHz operation directly from Flash memory (2 64bits buffers) ) 64-bits wide Flash with Prefetch ( Memory Accelerator
64 b bits 64 b bits 64 bits ARBITER * FLASH MEMO RY
InstructionsBUS
16 bits Thumb 32 bits Thumb-2
16 bits Thumb-2
32 bits Thumb-2
CORTEXM3 CPU Data/Debugg BUS
Thumb-2 64 b bits
32 bits
32 16 16 Bits Thumb-2
64 bit ts
ARRAY
32 bits Data 8 bit Data
16-bit Data
* The data (constant or literals ) are provided with the highest priority using the D-Bus.
Cyclic y Redundancy y Check ( (CRC) )
CRC Features
CRC-based techniques are used to verify data transmission or storage integrity Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Single input/output 32-bit data register CRC computation p done in 4 AHB clock cycles y (HCLK) General-purpose 8-bit register (can be used for p p g ( temporary storage)
AHB Bus 32-bit (read access) Data register (Output)
CRC computation (polynomial: 0x4C11DB7) Data D t register i t (Input) (I t)
32-bit (write access)
Di t Memory Direct M Access A (DMA)
DMA Features
7/12 independently configurable channels: hardware requests or software trigger on each channel. Software programmable priorities: Very high, High, Medium or Low. (Hardware priority in case of equality). Programmable and Independent source and destination transfer data size: Byte, Halfword or Word. 3 event flags for each channel: DMA Half Transfer Transfer, DMA Transfer complete and DMA Transfer Error. Memory-to-memory, y y, peripheral-to-memory, p p y, memory-to-peripheral y p p transfers and peripheral-to-peripheral transfers Faulty channel is automatically hardware disabled in case of bus access error Programmable number of data to be transferred: up to 65535. Support for circular buffer management
DMA Request Mapping

The DMA controller provides access to 7 channels
USART1_TX ADC1 USART3_TX TIM2_UP TIM2_CC3 TIM4_CC1 TIM1_CC1 SPI1 RX SPI1_RX TIM3_CC3 USART3_RX TIM4_CC2 TIM1_CC4 TIM1_CCU TIM1_TRIG TIM1_UP SPI2_TX I2C2_RX SPI2_RX I2C2 TX I2C2_TX USART1_RX TIM2_CC1 TIM3_CC1 TIM4_CC3 I2C1_TX TIM1_CC3 TIM4_UP TIM3 TRIG TIM3_TRIG I2C1_RX USART2_RX USART2_TX TIM2_CC2 TIM2_CC4
TIM3_CC4 SPI1_TX
TIM1_CC2 TIM3_UP
OR
OR
OR
OR
OR
OR
OR
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
SW TRIGGER
Channel1
Channel2
Channel3
Channel4
Channel5
Channel6
Channel7
D DMA
High Priority Request
DMA REQUEST
Low Priority Request
DMA Latency: 1 transfer

Request 1 Request 2
1 cycle
1 cycle
5 cycles
1 cycle
Request1 sample & arbitration phase
Address computation
Bus access
Acknowledgement phase
Request2 sample & arbitration phase
8 cycles for each request (source and destination on AHB)

9
If source or destination is a peripheral on APB, Bus access will include more cycles due to the AHB/APB bridge latency and APB transfer duration, depending on the AHB/APB ratio.
9 9
APB AHB = 1:1 APB:AHB 1 1 -> + 2 cycles l APB:AHB = 1:2 -> + 3-4 cycles
=> total t t l = 10 cycles l => total = 11-12 cycles
9 9
If the CPU is running, the DMA access (AHB or APB) may be delayed by 1 bus cycle on each of the buses For RAM access, , any y read after write access takes 1 extra cycle y
9
Example: APB:AHB = 1:1 ,DMA APB->AHB transfer and CPU is only accessing RAM (no APB access) The maximum latency between 2 DMA accesses will be 12 cycles
Reset and Clock Control (RCC)
RESET Sources
System RESET
Resets except R t all ll registers i t t some RCC registers and BKP domain Sources Low level on the NRST p pin (External Reset) WWDG end of count condition IWDG end of count condition A soft software (through are reset (thro gh NVIC) Low power management Reset
External RESET NRST
VDD
RPU
Filter
SYSTEM RESET WWDG RESET IWDG RESET Software RESET Power RESET Low power management RESET
PULSE GENERATOR (min 20s)
P RESET Power
Resets all registers except BKP domain Sources Power On/Power down Reset (POR/PDR) When exiting STANDBY mode
B k domain Backup d i RESET

Resets all BKP domain Sources Setting BDRST bit in RCC BDCR register VDD or VBAT power on, if both supplies have previously been powered off. off
On-Chip Oscillators
Multiple clock sources for full flexibility in RUN/Low Power modes
HSE (High Speed External oscillator): 4MHz to 16MHz main osc which can be multiplied by the PLL to frequencies t provide id a wide id range of ff i Can be bypassed with external clock HSI (High Speed Internal RC): factory trimmed internal RC oscillator 8MHz +/- 1% over 0-70C temp range
Feeds System clock after reset or exit from STOP mode for fast startup ( p time : 2us max) ) (startup Backup clock in case HSE osc is failing Note: When the HSI is used as a PLL clock input input, the maximum system clock frequency that can be achieved is 64 MHz.
LSI (Low Speed Internal RC): 40KHz internal RC for IWDG and optionally for the RTC used for Auto Wake-Up Wake Up (AWU) from STOP/STANDBY mode LSE (Low Speed External oscillator): 32.768kHz osc provides a precise time base with very low power consumption (max 1A). Optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode. Can be bypassed with external clock
Clock Scheme
System Clock (SYSCLK) sources RTC Clock (RTCCLK) sources
9 LSE 9 LSI 9 HSE clock divided by 128
9 HSI
9 HSE 9 PLL
USB Clock (USBCLK) provided from the internal PLL Clock-out capability p y on the MCO pin (PA.08) / max 50MHz
Configurable dividers provides AHB, APB1/2, ADC and TIM clocks
Clock Security System (CSS) to backup clock in case of HSE clock failure (HSI feeds the system clock)
Enabled by SW w/ interrupt capability linked to Cortex NMI
HCLK up to 72MHz PCLK1 up to 36MHz PLLCLK SYSCLK up to 72 MHz AHB Prescaler /1,2512 APB1 Prescaler /1,2,4,8,16
If (APB1 pres =1) Else
HSI RC
8MHz
/2 4 -16 MHz OSC_OUT HSE Osc OSC_IN /2 x2...x16 PLL x1 x2
TIMxCLK TIM2,3,4
PCLK2 up to 72MHz SYSCLK HSI MCO HSE /2 PLLCLK /128 OSC32_IN LSE OSc OSC32_OUT ADC Prescaler /2,4,6,8 USB Prescaler /1,1.5 ~40KHz 40KHz LSI RC IWDGCLK ADCCLK CSS APB2 Prescaler /1,2,4,8,16
If (APB2 pres =1) Else
x1 x2
TIM1CLK
32.768KHz
RTCCLK
USBCLK 48MHz
General G l Purpose P and d Alternate Alt t Function I/O (GPIO and AFIO)
62
GPIO Features
Up to 80 multifunction bi-directional I/O ports available: 80% IO ratio
Standard I/Os 5V tolerant The GPIOs can sink 25mA ( total currents sunk is 150mA ) 18 MHz Toggling Configurable Output Speed up to 50 MHz Up to 16 Analog Inputs Alternate Functions pins (like USARTx, TIMx, I2Cx, SPIx, CAN, USB) Up to 80 GPIOs can be set-up as external interrupt (up to 16 lines at time) One I/O can be used as Wake-Up from STANDBY (PA.00) One I/O can be set-up as Tamper Pin (PC.13) All Standard I/Os are shared in 5 ports (GPIOA..GPIOE) Atomic Bit Set and Bit Reset using BSRR and BRR registers Locking mechanism to avoid spurious write in the IO registers
When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the configuration of the port bit until the next reset (no write access to the CRL and CRH registers corresponding bit).
GPIO Configuration Modes

Configuration Mode CNF1 CNF0 MOD1 MOD0
Analog Input
To On-chip Peripherals
Analog Input Input Floating (Reset State) Input Pull-Up 0 0
VDD Pull - UP ON/OFF
Alternate Function Input

0 1 00 1 0
In nput Data R Register
ON OFF
Read
Input Pull-Down Output Push-Pull Output Open-Drain AF Push-Pull AF Open-Drain
1 0
1 0
TTL Schmitt Trigger Input Driver ON/OFF VSS VDD Output Driver
Pull - Down P
VDD or VDD_FT(1)
Write
1 1
Bit Set/Re B eset Register rs
01: 10 MHz 10: 2 MHz 11: 50 MHz
Output Data R Register
VSS
OUTPUT CONTROL
VSS
(1)
VDD for standard I/Os and VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
Read / Write From On-chip Peripherals
Push-Pull or O Open Drain D i or disabled
Alternate Function Output
I/O pin
Real-Time Real Time Clock (RTC)
RTC Features
Clock sources 32.768 kHz dedicated oscillator (LSE) Low frequency (40kHz), low power internal RC(LSI) HSE divided by 128 3 Event/Interrupt sources Second Overflow Alarm (also connected to EXTI Line 17 for Auto Wake-Up from STOP) Register protection against unwanted write operations RTC core & clock configuration in Backup domain Independent VBAT voltage supply Reset only by Backup domain reset up from STANDBY RTC config kept after reset or wake wake-up Calibration Capability RTC clock divided by 64 can be output on Tamper pin for calibration Then the clock can be adjusted from 0 to to 121ppm by a step of 1ppm Possibility to output the Alarm pulse or Second pulse on Tamper pin (even when the device is in STANDBY mode)
RTC Control Register (CR) RTC Counter RTC Divider RTC Alarm RTC Prescaler = fRTC
RTCSEL [1:0]
HSE OSC
LSI RC 1/128 LSE OSC or EXT Clock
Backup Domain
Alarm IT Overflow IT Second IT
Window Watchdog g (WWDG) ( )
WWDG features
Configurable time-window, can be programmed to detect abnormally late or early application behavior Conditional reset
Reset (if watchdog activated) when the down counter value becomes less than 40h (T6=0) Reset (if watchdog activated) if the down counter is reloaded outside id the h time-window i i d
WWDG Reset eset WWDG_CFR comparator = 1 when T6:0 > W6:0 CM P Write WWDG_CR WDGA T6 T5 T4 T3 T2 T1 T0 W6 W5 W4 W3 W2 W1 W0
To prevent WWDG reset: write T[6:0] bits (with T6 equal to 1) at regular intervals while the counter value is lower than the time-window value ( (W[6:0]) [ ]) Early Wakeup Interrupt (EWI): occurs whenever the counter reaches 40h can be used to reload the down counter WWDG reset flag (in RCC_CSR) to inform when a WWDG reset occurs Min-max timeout value @36MHz (PCLK1): 113s / 58.25ms
WWDG_CR
6-Bit Down Counter
PCLK1 (up to 36MHz)
PRESCALER (WDGTB)
T[6:0] CNT down counter
W[6:0] 3Fh
Refresh not allowed
Refresh Window
time
Best suited to applications which require the watchdog to react within an accurate timing window
T6 bit Reset
Independent Watchdog (IWDG)
IWDG features
Selectable HW/SW start through option byte Advanced security features:
IWDG clocked l k db by it its own dedicated d di t d low-speed l d clock l k (LSI) and thus stays active even if the main clock fails Once enabled the IWDG cant be disabled (LSI cant be disabled too) S f Reload Safe R l d Sequence S (k ) (key) IWDG function implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY)
12-bit reload value LSI (40KHz) 8-bit PRESCALER 12-bit down counter
VDD voltage domain 1.8V voltage domain
Prescaler Register
Status Register
Reload Register
Key Register
To prevent IWDG reset: write IWDG_KR with AAAAh key value at regular intervals before the counter reaches 0 CSR) to inform when a IWDG reset flag (in RCC RCC_CSR) IWDG reset occurs Min-max timeout value @40KHz (LSI): 100s / 26.2s
IWDG Reset
Best suited to applications which require the watchdog to run as a totally independent process outside the main application
Analog-to-Digital Converter (ADC)
ADC Features (1/2)

ADC conversion rate 1 MHz and 12-bit resolution
conversion time at 56 MHz ( y X*14Mhz) ) 1s (or any 1.17s conversion time at 72 MHz
Conversion range: 0 to 3.6 V 2 4V to 3.6 36V ADC supply requirement: 2.4V ADC input range: VREF- VIN VREF+ (VREF+ and VREF- available only in LQFP100
package)
Dual mode (on devices with 2 ADCs): 8 conversion mode Up to 18 multiplexed channels:
16 external channels 2 internal channels: connected to Temperature sensor and internal reference voltage (VREFINT = 1.2V)
Channels conversion groups:

Up to 16 channels regular group Up to 4 channels injected group
Single and continuous conversion modes
ADC Features (2/2)

Sequencer-based scan mode for up to 16 conversion External trigger option for both regular and injected conversion Channel by channel programmable sampling time Discontinuous mode on regular and injected groups Left or right Data alignment with inbuilt data coherency Analog Watchdog on high and low thresholds Interrupt generation on:
End of Conversion End of Injected conversion Analog watchdog
DMA capability (only on ADC1)
ADC Block Diagram

VREF+ VREFVDDA VSSA
ADCCLK
ADC Prescalers: Div2, Div4, Div6 and Div8
PCLK2
ADC_IN0 ADC_IN1
ADC GPIO Ports

Up to 4
DMA Request Address/data bus

Injected I j t d data d t registers i t (4x12bits) Regular data register (12bits)
End of injected conversion
. . .
ADC_IN15
ANA ALOG MUX
Injected Channels
Up to 16
Regular Channels
Temp Sensor VREFINT
End of conversion
Analog Watchdog
TIM1_TRGO TIM1_CC4 TIM1_TRGO CC1 TIM2_CC TIM3_CC4 TIM4_TRGO Ext_IT_15 JEXTSEL[2:0] bits JEXTRIG bit Start Trigger (injected group)
High Threshold register (12bits) Low Threshold register (12bits)
Analog watchdog event
AWD
EOC
JEOC
Flags
AWDIE
TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 Ext_IT_11 EXTSEL[2:0] bits EXTRIG bit Start Trigger (regular group)
EOCIE JEOCIE
Interrupt enable bits
ADC interrupt to NVIC
Analog sample time

ADCCLK, up to 14MHz, taken from PCLK2 through a prescaler (Div2, Div4, , Div6 and Div8) ) Three bits programmable g sample time cycles y for each channel:
1.5 cycles 7.5 cycles 13.5 cycles 28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles 239.5 cycles
PCLK2
ADC Prescalers: Div2, Div4, Div6 and Div8
ADC
1.5 cycles 7.5 cycles Sa ample Time Selectio on 13.5 cycles
ADCCLK
28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles 239.5 cycles
SMPx[2:0]
Total conversion = Sample time + 12.5 cycles (fixed time)

@ 14MH 14MHz and d Sample S l time=1.5cycle ti 15 l total t t l conversion: i 1 (14 cycles) 1s
Sequencer
Up to 16 conversions with different order, different sampling time and d oversampling li possibility. ibili
Example: - Conversion of channels: 1, 2, 8, 4, 7, 3 and 11 - Different sampling time. - Oversampling of channel 7.
Channel1
Channel2
Channel8
Channel4
Channel7
Channel7
Channel7
Channel3
Channel11
1.5 cycles
13.5 cycles
7.5 cycles
7.5 cycles
71.5 cycles
28.5 cycles
1.5 cycles
ADC conversion modes

Four conversion mode are available:
Start Start CHx Start
CHx Start
Stop
Single channel single conversion mode
CHx
. . .
Single channel continuous conversion mode
CHx
. . .
CHn
CHn
Stop
Multi-channels (Scan) Multisingle conversion mode
Multi-channels (Scan) Multicontinuous conversion mode
ADC discontinuous conversion mode

Split channels conversion sequence into sub-sequences Available for both regular and injected groups:
Up to 8 conversion for regular channel 1 conversion for injected channel
Example: - Conversion of channels: 0 0, 1 1, 2 2, 4 4, 5 5, 8 8, 9 9, 11 11, 12 12, 13 13, 14 and 15 - Discontinuous mode - Number of channel is 3
1st trigger gg
2nd trigger gg
3rd trigger gg
Channel0
Channel1
Channel2
Channel4
Channel5
Channel8
Channel9
Channel11
Channel12
4th trigger
h trigger 5th
Note: Do not use discontinuous mode for both Channel13 Channel14 Channel15 Channel0 Channel1 Channel2 regular and injected together. It can be used only for one group channel
End of Conversion
ADC Analog Watchdogs

12-bit programmable analog watchdog low and high thresholds Enabled on one, or all converted channels: one regular or/and injected channel, all injected or/and regular channels. Interrupt p g generation on low or high g thresholds detection
ADC_IN0 ADC_IN1
. . .
ADC_IN15
Analog Watchdog
Low Threshold High Threshold
AWD
Status Register
Temp Sensor VREFINT
DMA
DMA available only on ADC1 DMA request generated on each ADC1 end of regular channel conversion (Not in injected channels)
DMA Request Channel0 Channel1 DMA Request Channel2 DMA Request Channel3 DMA Request Channel4 DMA Request Channel5 DMA Request Channel6 DMA Request Channel7 DMA Request Channel8 DMA Request
ConvertedValue_Tab[9]
Channel8 conversion result Channel7 conversion result Channel6 conversion result
Example: - Conversion of regular channels: 0, 1, 2, 3, 4, 5, 6, 7 and 8 - Converte data stored in ConvertedValue_Tab[9] - DMA transfer enabled (destination address auto incremented)
ADC1 DR register
. . .
Channel5 conversion result Channel4 conversion result Channel3 conversion result Channel2 conversion result Channel1 conversion result Channel0 conversion result
Note: EOC flag cleared at end of regular channels conversion due to DMA access to ADC1 DR register
ADC dual modes

Available in devices with two ADCs: ADC1 master and ADC2 slave ADC1 and ADC2 triggers are synchronized internally for regular and injected channels conversion 8 ADC dual modes
ADC_IN15 Temp Sensor ADC_IN1 ADC_IN0
Up to 4 injected channels
VREFINT
GPIO Ports
ANALOG MUX
Up to 16 regular channels
ADC1 Analog
External event (Regular group) External event synchronization
ADC2 Analog
External event (Injected group)
Data register
Digital g ta Master aste
Digital g ta S Slave a e
EOC/JEOC
Advanced Control And General Purpose Timers
Features overview
General Purpose Feature 16-bit Counter
Auto Reload Up down and centered counting Up, modes Programmable direction of the channel: Output Compare: Toggle, PWM Input Capture PWM Input Capture input/output
ETR
Clock ITR 1 ITR 2 ITR 3 ITR 4
Trigger/Clock Controller
Trigger Output
4x 16 High resolution Capture Compare channels

16-Bit Prescaler Auto Reload REG +// 16-Bit 16 Bit Counter C t

CH1 CH1 CH2 CH3 CH4 CH1N
Synchronization Up to 8 IT/DMA Requests Motor Control Specific Feature OC Signal Management

6 Complementary outputs Dead-time management Repetition p Unit
Encoder Interface Hall sensor Interface Embedded Safety features

Break sources: BKIN pin/ CSS Lockable unit configuration
Capture Compare Capture Compare Capture Compare Capture Compare
CH2 CH2N CH3 CH3N CH4
BKIN
Counter Modes
There are three counter modes:
9 Up counting mode 9 Down counting D ti mode d 9 Center-aligned mode
When using the Repetion Counter (case of TIM1 only)

Center Aligned
RCR = 0
Up counting
Down counting
UEV
RCR = 2
UEV
105
Counter Clock Selection

Clock can be selected out of 8 sources
Internal clock TIMxCLK provided by the RCC TIMxCLK Internal trigger input 1 to 4:
ITR1 / ITR2 / ITR3 / ITR4 Using one timer as prescaler for another timer
Trigger Controller
External Capture Compare pins

Pin 1: TI1FP1 or TI1F TI1F_ED ED Pin 2: TI2FP2
ETR ITR1 ITR2 ITR3 ITR4
Polarity selection & Edge Detector & Prescaler & Filter

Controller TRGO
External pin ETR

Enable/Disable bit Programable polarity 4 Bits External Trigger Filter External Trigger Prescaler: Prescaler off Division by 2 Division by 4 Division by 8
TI1F_ED TI1FP1 TI2FP2
Serial Peripheral Interface (SPI)
SPI Features (1/2)

Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1 Full duplex synchronous transfers on 3 lines Simplex synchronous transfers on 2 lines with or without a bi-directional data line Programmable data frame size :8- or 16-bit transfer frame format selection Programmable data order with MSB-first or LSB-first shifting Master or slave operation Programmable bit rate: up to 18 MHz in Master/Slave mode NSS management by hardware or software for both master and slave: Dynamic change of Master/Slave operations
SPI Features (2/2)

Programmable clock polarity and phase Dedicated transmission and reception flags (Tx buffer Empty and Rx buffer Not Empty) with interrupt capability SPI bus busy status flag Master mode fault and overrun flags with interrupt capability Hardware CRC feature for reliable communication Support for DMA
Data Frame Format

Data frame format :
Programmable data frame size :8- or 16-bit transfer frame format selection Programmable data order with MSB-first or LSB-first shifting
0xD7
MSB first LSB first
M t Master
SCK MISO MOSI NSS
8-bit long g
0xD7
VDD
0xD739
MSB first LSB first
1616 -bit long

0xD739
Full Duplex Communication

SPI supports t Full F ll duplex d l and dT Tx-Only O l communication i ti mode d :
Full-duplex, three-wire synchronous transfer
Master
SCK MISO MOSI NSS SS VDD NSS SCK MISO MOSI
Slave
Full Duplex
Simplex Communication
SPI supports simplex communication mode:
Bidirectional: 1 Clock and 1 bi-directional data wire (One
bit direction transfer
control)
Rx-Only: 1 Clock and 1 unidirectional data wire Tx-Only
Master
SCK MISO MOSI NSS SCK MISO MOSI VDD NSS
Slave
Master
SCK MISO MOSI NSS VDD NSS SCK MISO MOSI
Slave
BiBi -directional
Rx Only (Slave)
NSS Hardware & Software Management

Hardware NSS Software NSS
Slave
Slave
Both Master and Slave NSS pins i could ld b be used df for other th purpose
SCK MISOMOSI NSS
SCK MISOMOSI NSS
Provides the possibility of

VDD
dynamic change of
SCK MISOMOSI NSS
SCK MISOMOSI NSS
Master/Slave operations: No hardware limitation to switch from master to slave or slave to t master t in i the th same application
Master
Master
Multi Master: SS output Management
Slave
Enable SS output capability bili
Slave
Each device can be a unique master by enabling its NSS as output and driving it low: all
SCK MISOMOSI NSS
SCK MISOMOSI NSS
other devices became slaves. Rx-only mode
SCK MISOMOSI NSS
SCK MISOMOSI NSS
N need No df for external t l GPIO pin to drive slaves NSS pins
Master
Slave
Inter Integrated Circuit (I2C)
I2C Features (1/2)

Multi Master and slave capability Controls all IC bus specific p sequencing, q g p protocol, arbitration and timing g Standard and fast IC mode (up to 400kHz) 7-bit and 10-bit addressing modes Dual Addressing Capability to acknowledge 2 slave addresses Status flags:
Transmitter/Receiver mode flag Byte transfer finished flag I2C busy flag
Configurable PEC (Packet Error Checking) Generation or Verification:

PEC value can be transmitted as last byte in Tx mode PEC error checking for last received byte
SMBus 2.0 Compatibility PMBus Compatibility
Dual Addressing Mode
I2C supports dual addressing capability to acknowledge 2 slave addresses
VDD
Master
SDA SCL SDA SCL
Slave
Slave address 1 Slave address 2
Universal Synchronous Asynchronous y Receiver Transmitter (USART)
USART Features (1/2)

Three USART: USART1 High speed APB2 and USART2,3 on Low speed APB1 Data can be 8 or 9 bits Even, odd or no-parity bit generation and detection 0.5, 1, 1.5 or 2 stop bit generation Programmable baud rate generator
Integer part (12 bits) Fractional part (4 bits)
Up to 4 4.5 5 Mbps
Support pp hardware flow control ( (CTS and RTS) ) Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability S Support t for f DMA
Receive DMA request Transmit DMA request q
Synchronous Mode
USART supports Full duplex synchronous communication mode
Full-duplex, F ll d ple three three-wire ire s synchronous nchrono s transfer USART Master mode only Programmable clock polarity (CPOL) and phase (CPHA) Programmable Last Bit Clock generation Transmitter Clock output (SCLK)
Master
SCLK Rx Tx SCK MISO MOSI NSS
Slave
USART
Full Duplex
SPI
IrDA SIR Encoder Decoder
USART supports the IrDA Specifications

Half-duplex, NRZ modulation, Max bit rate 115200 bps 3/16 bit duration for normal mode
USART
SIR Transmit Encoder
Tx/ SW_Rx
IrDA OUT
USART Tx
SIR Receive Decoder

IrDA IN
Half Duplex
Smart Card mode

USART supports Smart Card Emulation ISO 7816-3
Half Duplex, Clock Output (SCLK) Half-Duplex, 9Bits data, 0.5 Stop Bit in receive, 1.5 Stop Bits in transmit Parity Error Generation with NACK transmission P Programmable bl Guard G d Time Ti (data (d t processing) i ) Programmable Clock Prescaler to guarantee a wide range clock input
USART
Tx
SCLK
Single Wire Half Duplex mode

USART supports Half duplex synchronous communication mode
Only Tx pin is used (Rx is no longer used)
Used to follow a single wire Half duplex protocol.

VDD R = 10 K
USART1 Tx
USART2 Tx
Half Duplex
Controller Area Network (bxCAN)
CAN Features (1/2)

Main features:
Supports CAN protocol version 2.0 A, B Active Bit rates up to 1Mbit/s Support the time Triggered Communication option
Transmission
Three transmit mailboxes Configurable transmit priority Time Stamp on SOF transmission
Reception
Two receive FIFOs with three stages 14 scalable filter banks
Identifier list features
Configurable FIFO overrun p on SOF reception p Time Stamp
Universal Serial Bus interface (USB D Device) i )
USB Features
Full speed USB 2 2.0 0 transfer (certified on USB USB.org). org) Configurable endpoints transfer mode type: control, bulk, interrupt and Isochronous. Configurable number of endpoints: up to 8 bidirectional endpoints and 16 monodirectional endpoints. USB suspend/resume support. Dedicated SRAM Area (Packet Memory Area) up to 512bytes (shared with bxCAN). Dynamic buffer allocation according to the user needs. transfers Special double buffer support for Isochronous and Bulk transfers.
Double Buffering transfer mode

Up p to 7 mono-directional Double buffer endpoints p ( (in Bulk or Isochronous transfer types). yp ) Highest possible transfer rate. Number of NAKed transactions is limited by y the Application pp elaboration time.
PMA
Endpointx Buff 1
USB IP
Endpointx Buff 0
CPU
Peripherals added in Hi h & XL HighXL-Density D it STM32
STM32F10x High/XL-Densities Main Changes

Memories
SRAM: from 32 KB to 96 KB FLASH: from 256 KB to 1024 KB w/ 2 KB p pages g size ( (instead of 1 KB) )
New IPs
SDIO I2S2 and I2S3 (multiplexed with SPI2 and SPI3) DAC FSMC
Added and updated IPs

DMA2 w/ 5 channels ADC3 SPI3 UART 4 and 5, doesnt support hardware flow control, Smart Card mode (ISO 7816 compliant) and SPI lik communication SPI-like i ti capability bilit TIM8 (Advanced Control Timer) TIMER 5 (General Purpose Timer) TIMER 6 and 7 (Basic Timer used to trig the DAC)
STM32F10x High-density Series Block Diagram

ARM 32-bit Cortex-M3 CPU Nested Vectored Interrupt Controller (NVIC) w/ 60 maskable IT + 16 prog. priority levels Embedded Memories : ARM Lite Hi-Speed Bus Matrix / Arbite er (max 72MHz) FLASH: up to 512kB SRAM: up to 64kB External memory interface FSMC: support NAND, SRAM, NOR, PC Cards and others memory devices 2 x DMA w/ 12 channels SDIO: support SD, SDIO, MMC and CE-ATA cards Power Supply with internal regulator and low power modes : 2V to 3V6 supply 4 Low Power Modes with Auto Wake-up Integrated g Power On Reset (POR)/Power ( ) Down Reset (PDR) ( )+ Programmable voltage detector (PVD) Backup domain w/ 84B user data Up to 72 MHz frequency managed & monitored by the Clock Control w/ Clock Security System Rich set of peripherals & IOs Embedded low power RTC with VBAT capability Dual Watchdog Architecture 9 Timers w/ advanced control features (including Cortex SysTick) 12 communications Interfaces Up to 112 I/Os (144 pin package) w/ 16 external interrupts/event Up to 3x12-bits 1Msps ADC w/ up to 21 channels and Embedded temperature sensor w/ +/-1.5 linearity with T 12-bits DAC w/ 2 channels Up to 16 Ext. ITs Up to 112 I/Os 1x SPI 1x USART/LIN Smartcard/IrDa Modem-Ctrl JTAG/SW Debug ETM Nested vect IT Ctrl 1x Systic Timer 2 x DMA 12 Channels SDIO
SD/SDIO/MMC/ CE-ATA
Flash I/F
CORTEXM3 CPU 72 MHz
Up to 512kB Flash Memory
Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators 32KHz + 4~16MHz Int. RC oscillators 40KHz + 8MHz PLL
Up to 64kB SRAM
SRAM/NOR/NAND/ PC C Cards d
FSMC
84B Backup data Reset Clock Control CRC ARM Peripheral Bus Bridge (max 36MHz) 1x bxCAN 2.0B 6 x 16-bit Timer 4x USART/LIN Smartcard / IrDa Modem Control 2x SPI/I2S 2x I2C 12-bit DAC Temp Sensor 2 channels 1x USB 2.0FS RTC / AWU
2 x 1616-bit PWM
Bridge
ARM Peripheral Bus
(m max 72MHz)
Independent Watchdog Window Watchdog 3x 12-bit ADC 21 channels / 1Msps
174
Flexible Static Memory Controller (FSMC)
FSMC Features
4 Banks to support External memory FSMC external access frequency is 36MHz when HCLK is at 72MHz Independent chip select control for each memory bank Independent configuration for each memory bank Interfaces with static memory-mapped devices including:
static random access memory (SRAM) read-only memory (ROM) NOR Flash memory PSRAM
Interfaces parallel LCD modules: Intel 8080 and Motorola 6800 Interfaces with Cellular RAM and COSMO RAM, both synchronous and asynchronous random accesses NAND Flash and 16-bit PC Cards
With ECC hardware up to 8 Kbyte for NAND memory 3 possible interrupt sources (Level, Rising edge and falling edge)
Programmable timings to support a wide range of f devices External asynchronous wait control Code execution only from external SRAM or NOR Flash
FSMC Block Diagram

The FSMC consists of four main blocks:
The AHB interface (including the IP configuration registers) The NOR Flash/PSRAM controller The NAND Flash/PC Card controller The external devices interface
FSMC Interrupt to NVIC NOR Memory Controller FSMCCLK from RCC
NOR Signals
Shared Signals
AHB Bus
Configuration g Registers NAND Signals NAND/PC Card Memory y Controller PC Card Signals
FSMC Bank memory mapping

For the FSMC, the external memory is divided into 4 fixed size banks of 4x64 MB each: Bank 1 can be used to address NOR Flash or PSRAM memory devices. Banks 2 and 3 can be used to address NAND Flash devices. Bank 4 can be used to address a PC Card device.
0x6000 0000
Supported Memory Type

Bank 1 4x64 MB NOR / PSRAM / SRAM / CRAM
0x6FFF FFFF 0x7000 0000
Bank 2 256 MB
0x7FFF FFFF 0x8000 0000
NAND Flash Bank 3 256 MB
0x8FFF FFFF 0x9000 0000
Bank 4 256 MB
PC Card
0x9FFF FFFF
LCD modules interface signals
FSMC_NE[4:1] LCD /CS FSMC_Ax LCD RS LCD D[15:0] LCD /RD LCD /WR
LCD /RD: The ready signal indicates to the 8080 that valid memory or input data is available on the 8080 data bus. LCD /WR: The /WR signal is used for memory write or I/O output control. The data on the data bus is stable while the /WR is active low (/WR = 0). LCD RS: RAM Data/ Register Data Selection LCD /CS: Chip Select LCD D[0:15]: D[0 15] Bidirectional Bidi ti l data d t bus b
NOR Memory Controller
FSMC_D[15:0] FSMC_NOE FSMC_NWE
NOR/SRA M Bank
LCD Intel 8080 Controller
FSMC_Ax: where x can be (0..25)
All LCD Signals are controlled by FSMC

Application Note is available from www.st.com/mcu AN2790: TFT LCD interfacing with the High-density STM32F10xxx FSMC
Digital to Analog Converter (DAC) Digital-to-Analog
DAC Features
Two DAC converters: one output channel for each one 8-bit or 12-bit monotonic output Left or right data alignement in 12-bit mode Synchronized update capability Noise-wave or Triangular-wave generation Dual DAC channel independent or simultaneous conversions DMA capability for each channel External triggers for conversion DAC supply 2.4V to 3.6 V pp y requirement: q Conversion range: 0 to 3.6 V DAC outputs range: 0 DAC_OUTx VREF+ (VREF+ and VREF- available only in 100
and 144 pins package)

ADC and DAC share the same VREF+
DAC Channelx Block Diagram

DAC Control Register
SWTRIGx
Triger sel lection
TIM2_TRGO TIM4_TRGO TIM5 TRGO TIM5_TRGO TIM6_TRGO TIM7_TRGO TIM8_TRGO Ext_IT_9
neration Wave gen
Mask Amplitude
Triger ena able
Control Logic x DMA Request x

12 bits
DHRx
LFSRx
Trianglex
12 bits
DORx
12 bits
VREF+ VDDA VSSA
Digital to Analog Converter x
DMA ena able
DAC OUTx DAC_OUTx
Triangle Wave Generation

Add a small-amplitude triangular waveform on a DC or slowly varying signal: used as basic waveform generator for example Calculated triangle value, updated through external trigger, is added to the DAC_DHRx content without overflow to reach the configurable g max amplitude p Up-Down triangle counter:
Incremented to reach defined max amplitude value Decremented to return to the initial base value
Triangle max amplitude values are: (2N1) with N=[1..12]

MAMPx[3:0]: Max amplitude
DAC_DHRx: Base value
Dual DAC Channel mode

Both DAC channels can be used together: generate differential or stereo signals in simultaneous conversion mode 11 DAC dual modes:
Independant I d d t trigger, ti without ith t or with, ith same or different diff t wave generation (LFSR or Triangle) Simultaneous Si lt software ft start t t Simultaneous trigger, without or with, same or different wave generation ti (LFSR or Triangle) Ti l )
SDIO interface
SDIO Features (1/2)

Full compliance with
MMC - Multimedia Card System Specification Version 4.2. Card support for three different data bus modes: 1-bit (default), 4-bit and 8-bit Full compatibility with previous versions of Multimedia Cards (forward compatibility) SD Memory Card Specifications Version 2.0 SD I/O Card Specification Version 2.0 : card support for two different data bus modes: 1-bit (default) and 4-bit
Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1 Rev1.1) 1) Data transfer up to 48 MHz
SDIO Features (2/2)

Cards Clock Management: Rising and Falling edge, 8-bit prescaler, bypass divider divider, power save (clock output disabled) Hardware Flow Control: indicate FIFO contain 2 words or 2 words before full to avoid underrun/overrun . A 32-bit wide, 32-word FIFO for Transmit and Receive p y DMA Transfer Capability Data Transfer: Configurable mode (Block or Stream), configurable data block size from1 to 16384 bytes, configurable TimeOut 24 interrupt sources to ease software implementation CRC Check and generation SD I/O mode: SD I/O Interrupt, suspend/resume and Read Wait CE-ATA: CE-ATA end of completion command (CMD61), CE-ATA i t interrupt t
SDIO Block Diagram

Interrupts and DMA requests
SDIO_CK SDIO_CMD
The SDIO consists of two parts:

The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. The AHB interface accesses the SDIO adapter registers, and generates interrupt and DMA request signals.
AHB Interface
SDIO Adapter
SDIO_D[7:0]
AHB Bus
HCLK/2
SDIOCLK (HCLK)
SDIO Adapter
The SDIO adapter: bus master that p provides an interface to a multimedia card stack or to a secure digital memory card.
Adapter register block: contains all t i t SDIO system registers . Control unit: contains the power management functions and the clock divider for the memory card clock. Adapter Registers g
Control Unit Command Path Data Path
SDIO_CK
SDIO_CMD
Command path: sends commands to and receives responses from the d I l t command d cards. Implement transmission state machine Data path: transfers data to and from cards. Implement p data transmission state machine
AHB Bus
SDIO_D[7:0]
FIFO
HCLK/2
SDIOCLK (HCLK)
Data FIFO: contains a 32-bit wide, 32word deep data buffer, and transmit and receive logic logic.
SD/SDIO & MMC Cards

The SDIO has 10 pins to control different kinds of memory cards
Only 6 pins (SDIO_CMD, SDIO_CK, SDIO_D[3:0]) at most for SD cards (SD full size miniSD, size, miniSD microSD) Only 6 pins (SDIO_CMD, SDIO_CK, SDIO_D[3:0]) at most for SDIO cards (SD full size, miniSD, microSD) 10 pins (SDIO_CMD, (SDIO CMD, SDIO SDIO_CK, CK, SDIO SDIO_D[7:0]) D[7:0]) at most for MMC cards (MMC full size, RS-MMC, MMC+ and MMCMobile)
VDD
SDIO SDIO_CMD
SDIO_CK SDIO_D0 SDIO D1 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_D4 SDIO_D5 SDIO_D6 SDIO_D7
7 6 5 4 3 2 1 11 10 9 8 13 12
CE-ATA Devices
1
SDIO SDIO_CMD
SDIO_CK SDIO D0 SDIO_D0 SDIO_D1 SDIO_D2 SDIO_D3 SDIO_D4 SDIO_D5 SDIO_D6 SDIO_D7 _
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C CE-ATA A
SPI Interface I2S mode
I2S Features (1/2)

Two I2Ss: Available on SPI2 and SPI3 peripherals. p p Simplex communication (only transmitter or receiver) Master or slave operations. 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8KHz to 48KHz) Programmable data format (16-, 24- or 32-bit data formats) Programmable packet frame (16-bit and 32-bit packet frames). Underrun flag in slave transmit mode and Overrun flag in receive mode. 16-bit register for transmission and reception reception.
I2S Features (2/2)

I2S protocols supported:
I2S Philli Phillips standard. t d d MSB Justified standard (Left Justified). LSB Justified standard (Right Justified). PCM standard (with short and long frame synchronization on 16-bit channel frame or 16-bit data frame extended to 32-bit channel frame)
Master clock may be output to drive an external audio component. Ratio is fixed at 256xFs (where Fs i is th the audio frequency). 256 F ( h F di sampling li f ) Support for DMA (16-bit wide).
230
I2S audio protocol (1/2)

The I2S protocol is used for audio data communication between a microcontroller/DSP and an audio Codec/DAC. The Data are coded according to a specific audio protocol (I2S Phillips/MSB/LSB/PCM) and are time-multiplexed time multiplexed on two channels (Left and Right). The protocol uses three/four communication lines:
CK : Serial clock SD : Serial data WS : Word Select, control signal MCLK : Master Clock signal (optional)
MCLK
I2S
CK SD WS
Application Note is available from www.st.com/mcu AN2739: Using high-density STM32F103xx to play audio files with an external IS audio codec
Data format and packet frame

Data frame format :
Programmable data size :16-, 24- or 32-bit data format selection Programmable packet frame : 16-bit (for 16-bits data size) and 32-bits (for 16-, 24- and 32-bit data size).
1616 -bit Left Data 0xD7 WS 16-bit Right 16Data
1616 -bit packet

1616 -bit Left Data
1616 -bit data length
I2S
CK (SCK) SD (MISO) WS (NSS) MCLK *
0xD7 WS
3232 -bit packet
2424 -bit Left Data
24-bit data 24length
0xD73 WS 3232 -bit Left Data
3232 -bit packet
* Optional feature activated by software
32-bit data 32length
0xD739 WS
3232 -bit packet
232
Simplex Communication
I2S supports t only l simplex i l communication i ti mode d :
Simplex, three-wire synchronous audio transfer
I2C controls t l *
The Th master t and d slave l configuration is managed only y by y software. The master device is the CK and WS generator.
STM32F10x
CK SD WS ** MCLK
Audio Codec
SD WS MCLK Digital Interface e Analog Interfac ce CK
The master/slave modes and transmit/receive directions can be switched dynamically y y by y software.
Simplex synchronous audio transmission
** Optional feature activated by software * Depends on the Codec control method
233
ST STANDARD PERIPHERAL LIBRARY
Software libraries speed time to market

ST software libraries free at www.st.com/mcu C source code for easy implementation of all STM32 peripherals in any application
Standard library source code for implementation of all standard
peripherals; code implemented in demos for STM32 evaluation board
Motor control library sensorless vector control for 3-phase

brushless motors
DSP library PID, IIR, FFT, FIR (free with license agreement)
Free USB device library from ST: ANSI-C source code available, supporting many USB classes (mass storage, HID, DFU, CDC, audio)
23
STM32 FW library API structure

App plication layer
User Interrupt handlers
Application code
User library configuration g
To be modified in project
stm32f10x_it.c stm32f10x_it.h t 32f10 it h
stm32f10x_conf.h
Include this file to your application files
API layer
stm32f10x_ppp.c stm32f10x ppp h stm32f10x_ppp.h
stm32f10x.h
STM32 HW W
HW Peripherals registers(PPP)
Do not modify you can share between projects 23
STM32 library how to use it ?

Function and constant for each peripheral has prefix with its name, like: GPIO, TIM1:
ie. GPIO_Init(), ADC_Channel_0, USART_IT_TXE
Most of the settings is in 1fromN convention and allow to use concatenation, like:
GPIO_Pin_0 | GPIO_Pin_1, what means that pins 0 and 1 from will be configured in the same time
There are predefined types in stm32f10x_type.h file, like:

u8 unsigned char u16 unsigned short RESET / SET FALSE / TRUE DISABLE / ENABLE Most of the peripherals (PPP) has set of instruction: PPP_DeInit(...) set all PPP register to its reset state PPP_Init(...) validation of the configuration for the peripheral PPP_Cmd(ENABLE/DISABLE) turn on/off PPP peripheral (not affects its clock) PPP_ITConfig(...) configuration (on/off) of sources of interrupts for PPP peripheral PPP_GetFlagStatus(...) read flags from the peripheral (polling) PPP_ClearFlag PPP ClearFlag(...) ( ) clear flags from the peripheral PPP_ClearITPendingBit(...) clear IRQ flag
STM32 VALUE-LINE DISCOVERY KIT
STM32 Discovery-kit
Development Toolchain support
ECLIPSE Dev Tools : Free Atollic TrueSTUDIO lite version with unlimited code-size and usage-time. IAR EWARM KEIL MDK-ARM
Price: $9.90
Large number of software examples available at www.st.com/stm32-discovery for a quick start to evaluate and p with the STM32 Value line develop
24
STM32 Value line Discovery Board

On-board ST-LINK with selection mode switch to use the kit as stand-alone STLINK with SWD connector Designed to be powered by USB or by external t l power 5V or 3 3.3V 3V supply l Can supply target application with 5 Volts or 3 Volts
STM32F100RBT6B ST-LINK SWD connector
84mm
Two User LEDs (Green and Blue) One user Push Button Extension E i h header d f for all ll QFP64 I/O I/Os for quick connection to prototyping board or easy probing
User button Led Blue Led Green
42mm
STM32 Discovery Web-Support

www.st.com/stm32-discovery Manuals, Getting started, examples... For Keil, IAR and Atollic
Forum with dozens of posts
24
Thank You !
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STM32 Seminar STM32F General G l Purpose P Lines Li

COMPEL/STM Seminar November 2010

STM32 Low Low-Power Power Line

STM32 Connectivity Line

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STM32F10x Product Lines

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