HC VIN K THUT QUN S

B MN K THUT XUNG S, VI X L KHOA V TUYN IN T

THIT K LOGIC S
(Dng cho i tng o to chnh quy h qun s v dn s)

LU HNH NI B

H NI -2011

LI GII THIU
Thit k logic s l mn hc k tip ca chng trnh in t s. Ni dung chnh ca chng trnh mn hc tp trung vo hai vn kin thc chnh. Th nht l bi ton thit k v mt chc nng cho cc khi s c mt tch hp ln c LSI, VLSI v ln hn. Vn th hai l gii thiu cn bn v cc cng ngh gip hin thc ha thit k chc nng thnh sn phm ng dng, trong tp trung chnh vo cng ngh FPGA, mt nn tng cng ngh mi v ang pht trin rt mnh hin nay. Khc vi bi ton tng hp v phn tch trong in t s ch yu l bi ton cho cc mch c SSI, MSI, cc bi ton y c hng ti cc ng dng c th thc tin vi quy m ln hn v buc phi s dng cc cng c tr gip thit k trn my tnh v ngn ng thit k VHDL Chng trnh Thit k logic s nhm vo trang b kin thc c s ngnh cho tt c cc i tng sinh vin thuc chuyn ngnh k thut in t vin thng, iu khin t ng. Trc khi hc mn ny cc sinh vin ny phi hc qua cc mn c s ngnh gm Cu kin in t, in t s, K thut Vi x l trong hai mn u l bt buc. Thit k logic s l mt mn hc mang tnh thc hnh cao nn trong cu trc chng trnh s dnh nhiu thi gian hn cho thc hnh th nghim cng nh bt buc sinh vin khi kt thc mn hc phi thc hin cc n bi tp thit k c va v ln theo nhm di dng Bi tp ln hoc n mn hc. Kin thc v k nng ca sinh vin s gip ch rt ln cho cc bi ton chuyn ngnh v n tt nghip sau ny bi trong cc ng dng x l s ang dn chim vai tr quan trng trong cc h thng k thut. Bn cnh nhng cng c truyn thng l Vi x l, my tnh th thit k phn cng trn FPGA hoc trn nn cc cng ngh tng t ang l mt hng pht trin mang li hiu nng vt tri v kh nng ng dng thch nghi tt hn. Gio trnh chnh thc cho mn hc c hon thin sau hn 2 kha o to cho sinh vin h o to dn s, qun s ti Hc vin K thut qun s. Nhm tc gi xin chn thnh cm n s ng h nhit tnh ca lnh o Khoa V tuyn in t, lnh o b mn K thut xung s, vi x l, cc ng nghip trong khoa v b mn c nhiu kin ng gp qu bu gp phn hon thin ni dung cho gio trnh, cm n anh ch em nhn vin ca b mn gp nhiu cng sc cho cng vic ch bn cho gio trnh. Nhm tc gi cng gi li cm n ti 3

ton b cc sinh vin cc kha o to bng qu trnh hc tp, nghin cu thc t c nhng kin ng gp gip tc gi iu chnh v khung chng trnh v ni dung ngy hp l v hiu qu hn. V thi gian hn ch v l mt mn hc mi do vy chc chn s cn nhiu nhng khim khuyt trong gio trnh. Nhm tc gi rt mong tip tc nhn c nhng kin ng gp ca ngi s dng, mi kin c th gi v B mn K thut Xung s, Vi x l Hc vin KTQS hoc vo hm th in t quangkien82@gmail.com.

H ni 12-2011

Mc lc
LI GII THIU ........................................................................................ 3 DANH SCH CC K HIU VIT TT .............................................. 11 Chng 1: CC KIN THC C S ..................................................... 15 1. Cc khi nim chung .......................................................................... 16 1.1. Transitor ....................................................................................... 16 1.2. Vi mch s tch hp ..................................................................... 17 1.3. Cng logic .................................................................................... 18 1.4. Phn t nh .................................................................................. 20 1.5 Mch logic t hp ......................................................................... 23 1.6. Mch logic tun t ....................................................................... 24 1.7 Cc phng php th hin thit k. .............................................. 25 2. Yu cu i vi mt thit k logic ..................................................... 27 3. Cc cng ngh thit k mch logic s ................................................ 28 4. Kin trc ca cc IC kh trnh ........................................................... 31 4.1. Kin trc PROM, PAL, PLA, GAL............................................. 31 4.2. Kin trc CPLD, FPGA ............................................................... 36 Cu hi n tp chng 1 ........................................................................ 39 Chng 2: NGN NG M T PHN CNG VHDL ......................... 41 1. Gii thiu v VHDL........................................................................... 42 2. Cu trc ca chng trnh m t bng VHDL ................................... 43 2.1. Khai bo th vin......................................................................... 44 2.2. M t thc th .............................................................................. 45 2.3. M t kin trc ............................................................................. 48 2.4. Khai bo cu hnh ........................................................................ 53 3. Chng trnh con v gi .................................................................... 56 5

3.1. Th tc ......................................................................................... 56 3.2. Hm.............................................................................................. 58 3.3. Gi ............................................................................................... 59 4. i tng d liu, kiu d liu .......................................................... 62 4.1. i tng d liu ......................................................................... 62 4.2. Kiu d liu ................................................................................. 63 5. Ton t v biu thc .......................................................................... 70 5.1. Ton t logic ................................................................................ 70 5.2. Cc php ton quan h ................................................................. 71 5.3. Cc php ton dch ...................................................................... 72 5.4. Cc php ton cng tr v hp .................................................... 74 5.5. Cc php du................................................................................ 74 5.6. Cc php ton nhn chia, ly d .................................................. 75 5.7. Cc php ton khc ...................................................................... 76 6. Pht biu tun t ................................................................................ 76 6.1. Pht biu i ................................................................................ 76 6.2. Pht biu xc nhn v bo co ..................................................... 79 6.3. Pht biu gn bin........................................................................ 80 6.4. Pht biu gn tn hiu .................................................................. 81 6.5. Lnh r nhnh v lnh lp............................................................ 83 7. Pht biu ng thi ............................................................................ 87 7.1. Pht biu khi .............................................................................. 88 7.2. Pht biu qu trnh ....................................................................... 89 7.3. Pht biu gn tn hiu ng thi .................................................. 92 7.4. Pht biu generate ........................................................................ 95 7.5. Pht biu ci t khi con ............................................................ 97 8. Phn loi m ngun VHDL................................................................ 99 9. Kim tra thit k bng VHDL. ......................................................... 101 6

9.1. Kim tra nhanh .......................................................................... 102 9.1. Kim tra t ng nhiu t hp u vo ..................................... 104 Bi tp chng 2 .................................................................................. 111 Bi tp .................................................................................................. 111 Cu hi n tp l thuyt ....................................................................... 116 Chng 3: THIT K CC KHI MCH DY V T HP THNG DNG ................................................................................................................. 117 1. Cc khi c bn ................................................................................ 118 1.1. Khi cng n gin ................................................................... 118 1.2. Khi tr ...................................................................................... 119 1.3. Khi cng thy nh trc. ......................................................... 121 1.4. Thanh ghi ................................................................................... 125 1.5. B cng tch ly ......................................................................... 127 1.6. B m ....................................................................................... 129 1.7. B dch ....................................................................................... 131 1.8. Thanh ghi dch ........................................................................... 133 2. Cc khi nh .................................................................................... 136 2.1. B nh RAM ............................................................................. 136 2.2. B nh ROM ............................................................................. 139 2.3. B nh FIFO .............................................................................. 141 2.4. B nh LIFO.............................................................................. 142 3. My trng thi hu hn .................................................................... 143 4. Khi nhn s nguyn........................................................................ 145 4.1. Khi nhn s nguyn khng du dng phng php cng dch 146 4.2. Khi nhn s nguyn c du...................................................... 150 4.3. Khi nhn dng m ha Booth c s 4 ..................................... 155 5. Khi chia s nguyn ......................................................................... 158 5.1. Khi chia dng s khi phc phn d .................................. 159 7

5.2. Khi chia dng s khng khi phc phn d ....................... 162 5.3. Khi chia s nguyn c du ....................................................... 164 6. Cc khi lm vic vi s thc .......................................................... 169 6.1. S thc du phy tnh ................................................................ 169 6.2. S thc du phy ng .............................................................. 170 6.3. Ch lm trn trong s thc du phy ng........................... 173 6.4. Php cng s thc du phy ng ............................................. 176 6.5. Php nhn s thc du phy ng ............................................. 181 6.6. Php chia s thc du phy ng .............................................. 183 Bi tp chng 3 .................................................................................. 186 Bi tp ............................................................................................... 186 Cu hi n tp l thuyt .................................................................... 194 Chng 4: THIT K MCH S TRN FPGA ................................... 195 1. Tng quan v kin trc FPGA ......................................................... 196 1.2. Khi nim FPGA ....................................................................... 196 1.3. ng dng ca FPGA trong x l tn hiu s ............................. 198 1.4. Cng ngh ti cu trc FPGA .................................................... 199 1.5. Kin trc tng quan ................................................................... 200 2. Kin trc chi tit Xilinx FPGA Spartan-3E. .................................... 201 2.1. Khi logic kh trnh ................................................................... 204 2.2. Khi iu khin vo ra............................................................... 221 2.3. H thng kt ni kh trnh ......................................................... 224 2.4. Cc phn t khc ca FPGA ...................................................... 227 3. Quy trnh thit k FPGA bng ISE .................................................. 237 3.1. M t thit k ............................................................................. 238 3.2. Tng hp thit k ....................................................................... 239 3.3. Hin thc ha thit k ................................................................ 244 3.4. Cu hnh FPGA ......................................................................... 250 8

3.5. Kim tra thit k trn FPGA ...................................................... 250 4. Mt s v d thit k trn FPGA bng ISE ...................................... 251 4.1. Thit k khi nhn thng tin UART .......................................... 253 4.2. Thit k khi iu khin PS/2 cho Keyboard, Mouse ............... 267 4.3. Thit k khi tng hp dao ng s NCO ................................. 270 4.4. Thit k khi iu khin LCD1602A ........................................ 282 4.5. Thit k iu khin VGA trn FPGA. ....................................... 294 Bi tp chng 4 .................................................................................. 308 1. Bi tp c s ................................................................................. 308 2. Bi tp nng cao............................................................................ 309 3. Cu hi n tp l thuyt ................................................................ 312 PH LC ................................................................................................ 313 Ph lc 1: THNG K CC HM, TH TC, KIU D LIU CA VHDL TRONG CC TH VIN CHUN IEEE. ........................................ 314 1. Cc kiu d liu h tr trong cc th vin chun IEEE ............... 314 2. Cc hm thng dng h tr trong cc th vin chun IEEE ........ 315 3. Cc hm phc v cho qu trnh m phng kim tra thit k ........ 319 4. Cc hm bin i kiu d liu dng trong VHDL ....................... 322 Ph lc 2: THC HNH THIT K VHDL ...................................... 325 Bi 1: M phng VHDL trn ModelSim .......................................... 326 Bi 2: Xy dng b cng tr trn c s khi cng bng ton t...... 338 Bi 3: Khi dch v thanh ghi dch ................................................... 344 Bi 4: B cng bit ni tip dng 1 FA (serial-bit adder) .................. 353 Ph lc 3: MCH PHT TRIN NG DNG FPGA ...................... 364 1. Gii thiu tng quan ..................................................................... 364 2. Cc khi giao tip c trn mch FPGA ........................................ 366 2.4. Khi giao tip Keypad .................................................................. 367 2.5. Khi 8x2 Led-Diod ....................................................................... 367 9

2.6. Khi Switch................................................................................... 367 2.7. Khi giao tip 4x7-seg Digits ....................................................... 367 2.9. Khi giao tip USB ....................................................................... 368 2.10. Khi giao tip PS/2 ..................................................................... 368 Ph lc 4: THC HNH THIT K MCH S TRN FPGA ........ 371 Bi 1: Hng dn thc hnh FPGA bng Xilin ISE v Kit SPARTAN 3E ................................................................................................................. 372 Bi 2: Thit k khi giao tip vi 4x7Seg -digits ............................. 397 Ph lc 5: CC BNG M THNG DNG ..................................... 407 1. M ASCII iu khin .................................................................... 408 2. M ASCII hin th ........................................................................ 410 3. Bng m k t cho LCD 1602A ................................................... 414 TI LIU THAM KHO ....................................................................... 415

10

DANH SCH CC K HIU VIT TT

AES ALU ASIC BJT BRAM CLA CLB CMOS : Advance Encryption Standard : Arithmetic Logic Unit : Aplication Specific Intergrated Circuit : Bipolar Junction Transitor : Block RAM : Carry Look-Ahead Adder : Configurable Logic Block : CMOS (ComplementarySymmetry Metal-Oxide Sermiconductor) : Complex Programmable Logic Device : Digital Clock Manager Thut ton m ha AES Khi thc thi s hc logic Vi mch tch hp vi chc nng chuyn dng. Transitor lng cc Khi nh truy cp ngu nhin trong FPGA Khi cng thy nh trc Khi Logic kh trnh trong FPGA Cng ngh bn dn dng trn cp b PN transitor trng.

Vi mch kh trnh phc tp( c ln) Khi qun l v iu chnh DCM xung nhp h thng trong FPGA : Double Data Rate Truyn d liu vi tc gp DDR i tc cung nhp h thng : Data Encryption Standard Thut ton m ha DES DES : Digital Frequency Synthesis Khi tng hp tn s DFS : Delay Locked Loop Khi lp kha tr DLL : Dynamic RAM RAM ng DRAM : Design Rule Check Kim tra cc vi phm trong thit DRC k : Device Under Test i tng c kim tra DUT 2 E PROM : Electric-Eraseable Programmable PROM c th xa bng in ROM : Electronic Design Interchange Chun cng nghip m t EDIF Format cc khi in t. :Embbed Develovepment Kit T hp phn mm thit k h EDK nhng trn FPGA CPLD 11

PROM c th xa oc Khi chn knh m rng trong FPGA : Field Effect Transitors Transitor dng hiu ng trng FET : First In First Out B nh c d liu vo trc s FIFO c c ra trc. Khi chn knh m rng trong FiMUX : Wide-Multiplexer FPGA : Field-Programmable Gate Array IC kh trnh cp ngi dng FPGA cui : Floating Point Unit Khi x l s thc du phy FPU ng : Generic Array Logic IC kh trnh trn cng ngh GAL CMOS : Hardware Description Language Ngn ng m t phn cng HDL : Inter-Integrated Circuit Giao tip I2C truyn d liu I2C gia cc IC : Integrated Circuit Vi mch tch hp IC : Institute of Electrical and Vin k thut in v in t IEEE Electronics Engineers : Input/Output Buffer Khi m vo ra trong FPGA IOB Thit k c ng k s hu IP Core : Intellectual Property core tr tu : Integrated Software Enviroment T hp phn mm thit k ISE FPGA ca Xilinx : Last In First Out Khi nh LIFO, d liu vo sau LIFO cng s ra trc nht : Large scale integration Vi mch tch hp c ln LSI : Look-Up Table Bng tham chiu trong FPGA LUT Transitor trng dng tip gio MOSFET : Metal-oxide-sermiconductor Field-Effect-Transitors kim loi bn dn : Medium scale integration Vi mch tch hp c trung MSI Khi nhn chuyn dng trong MULT18 : Dedicated Multiplier 18 x18 FPGA : Native Circuit Database nh dng sau qu trnh nh x NCD EPROM : Eraseable Programmable ROM F5MUX : Wide-Multiplexer 12

NCF NGD PAL PAR PCF PLA PLD PROM PS/2

: Native Constraint File : Native Generic Database : Programmable Array Logic : Place and Route : Physical Constraint File : Programmable Logic Array : Programmable Logic Device : Programmable Read-Only Memory : IBM Personal System 2

cng v Sp t kt ni ca Xilinx ISE. Tp ci t iu kin rng buc c bn ca thit k. nh dng sau qu trnh Translate ca Xilinx ISE Mng logic kh trnh Sp t v kt ni (trong qu trnh hin thc ha FPGA Tp quy nh cc rng buc vt l ca thit k trn ISE Mng cc khi logic kh trnh Vi mch kh trnh B nh ROM kh trnh Chun giao tip cho cc ngoi vi nh chut, bn phm trn my tnh ca IBM B nh truy cp ngu nhin Thut ton m ha RSA

RAM RSA

RTL SDK

: Read Only Memory : Ronald Rivest, Adi Shamir & Leonard Adleman Cryption Schema : Register Tranfer Level : Software Development Kit

: Shift-Register 16 bit SHL16 SLICEL : SLICE Logic SLICEM : SLICE Memory

SoC SPI SPLD

: System On a Chip : Serial Peripheral Interface : Simple Programmable Logic

M t lp thanh ghi truyn ti T hp cc chng trnh h tr thit k phn mm nhng ca Xilinx Thanh ghi dch 16 bit Phn t Logic trong FPGA Phn t Logic c kh nng thc hin chc nng nh trong FPGA H thng tch hp trn mt chp n. Chun kt ni ngoi vi ni tip

13

SRAM SSI UART UCF

ULSI VGA VHDL VLSI WSI XPS XST

Device : Static Random Access Memory RAM tnh : Small scale integration Vi mch tch hp c nh : Universal Asynchronous Receiver Chun truyn tin d b ni tip Transceiver : User Constraint File Tp quy nh cc iu kin rng buc cho thit k bi ngi dng. : Ultra large scale intergration : Video Graphic Array Chun kt ni vi mn hnh my tnh : Very Hi-speed Integrated Circuit Ngn ng m t vi mch s tch Hardware Description Language hp : Very large scale integration Vi mch tch hp c rt ln : Wafer scale intergration : Xilinx Platform Studio Chng trnh phn mm h tr xy dng h nhng trn FPGA : Xilinx Synthesis Technology Chng trnh tng hp thit k ca Xilinx

14

Chng 1 CC KIN THC C S

Chng m u c nhim v cung cp cho ngi hc nhng kin thc, khi nim c bn v thit k cc khi s, trong c nhng kin thc c nhc li vi nhng b xung ph hp vi mc ch mn hc. Ngi hc c gii thiu qua v cch thc thit khi lm vic vi tn hiu s c thit k ch to, phn loi cc dng vi mch s v cc tham s c bn cn quan tm khi thit k hay lm vic vi vi mch s. Chng ny cng gii thiu qua v s pht trin ca mt lp cc IC kh trnh phn cng t PROM cho ti FPGA. Mc ch ca phn ny gip cho ngi hc c mt ci nhn tng quan v lch s ca thit k logic s trc khi tp trung vo cc vn kin thc chnh cc chng sau l ngn ng m t phn cng VHDL v cng ngh FPGA.

15

1. Cc khi nim chung

1.1. Transitor L linh kin bn dn c kh nng lm vic nh mt cng tc bt tt hoc dng khuch i tn hiu. Transitor l phn t c bn ca mi vi mch s tch hp, t cc cng logic n gin AND, OR, NOT... n cc loi phc tp nh cc mch iu khin ngoi vi, vi iu khin, vi x l Transitor c lm t vt liu bn dn (sermiconductor), l vt liu va c kh nng dn in va c kh nng lm vic nh nhng vt liu cch in, kh nng ny thay i ty theo kch thch t bn ngoi nh nhit , nh sng, trng in t, dng in Cht bn dn dng cu to transitor thng l Germany (Ge) hoc Silicon (Si) c kch tp mt lng nh Photpho(P) hoc Boron (B) vi mc ch tng mt electron (kiu N) t do hoc tng mt l trng (kiu P) tng ng trong tinh th bn dn. Cu trc nguyn l ca cc dng transitor c trnh by hnh di y:

Hnh 1-1. Cu trc transitor lng cc BJTS, n cc FETs, diode Transitor lng cc BJT (Bipolar Junction Transitor) s dng nhiu trong thp k 80s, c im ca BJT l tc chuyn mch nhanh nhng nhc im l mc tiu th nng lng ln ngay c trong trng thi ngh v chim nhiu din tch. Sau BJTs dn c thay th bng transitor n cc FETs(Field Effect Transitors) lm vic trn hiu ng trng v knh dn ch dng mt loi bn dn loi p hoc n. MOSFETs (Metal-oxide-sermiconductor Field-Effect-Transitors) l transitor FETs nhng dng cc Cng metal (v sau lp metal c thay bng polysilicon) ph trn mt lp oxide cch in v lp ny ph trn vt liu bn 16

dn, ty theo loi vt liu bn dn m transitor ny c tn gi l NMOS (knh dn n) v PMOS (knh dn p). CMOS (Complementary-Symmetry Metal-Oxide Sermiconductor) l transitor to thnh t vic ghp cp b PMOS v NMOS, c nhiu u im so vi cc dng transitor c nh hiu in th lm vic thp, chng nhiu cao, tiu tn t nng lng v cho php tch hp trong IC s vi mt cao. CMOS l cng ngh transitor c s dng rng ri nht hin nay. 1.2. Vi mch s tch hp Cn c gi l IC Intergrated Circuits, chip, l cu trc mch in c thu nh bng cch tch hp ch yu t cc transitor vi mt cao, ngoi ra cn c th c cc linh kin in th ng khc trn mt khi bn dn mng. Cc vi mch tch hp u c mt s lng tn hiu u vo v u ra thc hin mt chc nng c th no . Trong khun kh gio trnh ny ch yu nghin cu v vi IC s, tc l dng IC ch lm vic vi cc tn hiu s.

...

Hnh 1-2: a) M hnh Vi mch s tch hp b) Vi mch tch hp thc t Vi mch tch hp ra i t nhng nm 1960s v c ng dng rng ri trong thc t, v ang to ra cuc cch mng trong lnh vc in t. V d v vi mch tch hp nh cc IC a dng (general purposes IC) h 7400, 4000, cc dng vi x l 80x86 dng trong my vi tnh, chp x l dng cho in thoi di ng, my nh k thut s, cc vi iu khin dng trong cc thit b dn dng, ti vi, my git, l vi sng Cc vi mch ny c mt tch hp t hng vi chc n hng trm triu, v hin nay n hng t transitor trong mt ming bn dn c kch thc xp x kch thc ng xu. Mt tch hp c nh ngha l tng s nhng phn t tch cc (transitor hoc cng logic) cha trn mt n v

...
a)

IC

b)

17

din tch ca khi tinh th bn dn. Theo mt tch hp chia ra cc loi vi mch sau: - Vi mch c nh SSI (Small scale integration), c hng chc transitor trong mt vi mch. - Vi mch c va MSI (Medium scale integration), c hng trm transitor trong mt vi mch. - Vi mch c ln LSI (Large scale integration), c hng ngn n hng chc ngn transitor trong mt vi mch. - Vi mch cc ln VLSI (Very large scale integration), c hng vn, hng triu, hng chc triu transitor v ln hn trong mt vi mch, ti thi im hin nay xut hin nhng vi mch c tch hp n hng t transitor. - Vi mch siu ln ULSI (Ultra large scale intergration), vi mch c tch hp vi mc hng triu transitor tr ln. - WSI (Wafer-scale-Intergration) l gii php tch hp nhiu vi mch chc nng trn mt tm silicon (wafer) tng hiu sut cng nh gim gi thnh sn phm, v d h vi x l nhiu nhn c tch hp bng WSI. - SoC (System-on-a-Chip) Khi nim ch mt h tnh ton, x l m tt c cc khi chc nng s v c tng t c thit k tch hp vo trong mt chip n. Trong khun kh chng trnh ny s dnh thi lng chnh cho vic nghin cu c bn v cng ngh, phng php, qu trnh thit k cc vi mch c LSI, VLSI. 1.3. Cng logic Cng logic hay logic gate l cu trc mch in (s khi hnh ) c lp rp t cc linh kin in t thc hin chc nng ca cc hm logic c bn y = f(xn, xn-1,..., x1, x0). Trong cc tn hiu vo xn-1, xn-2,..., x1, x0 ca mch tng ng vi cc bin logic xn-1, xn-2,..., x1, x0 ca hm . Tn hiu ra y ca mch tng ng vi hm logic y. Vi cc cng c bn thng gi tr n 4.
x0 y x1
-------

LOGIC GATE

xn

Hnh 1-3. M hnh cng logic c bn

18

Gi tr ca cc tn hiu vo v ra ch c hai mc l mc thp (Low - L) v mc cao (High - H) tng ng vi vi hai gi tr 0 v 1 ca cc bin logic v hm logic. V d: Mt cng NOT loi CMOS (hnh 1.4) tng ng hm NOT hai bin Q = not A.

Hnh 1-4. Mch in cng NOT Trn s d nhn thy rng, ch khi A c mc tch cc cao th transitor trn ng cn transitor di m, Q c mc tch cc thp, khi A c mc tch cc thp th transitor trn m v di ng nn Q c mc tch cc cao, nh vy mch in vi s trn thc hin vai tr ca cng NOT. Cc mch logic u c biu din bng cc h hm logic v do c th pht biu l: Mi mch logic u c th xy dng t cc cng logic c bn. i vi cc cng logic c bn th c hai tham s thi gian c bn:

Hnh 1.5. Tham s thi gian ca cng NOT Thi gian tr lan truyn Tpd (Propagation delay) l thi gian ti thiu k t thi im bt u xy ra s thay i t u vo X cho ti khi s thay i ny to ra ra thay i xc nh ti u ra Y, hay ni mt cch khc cho ti khi u ra Y n nh gi tr. 19

Tcd (Contamination delay) l khong thi gian k t thi im xut hin s thay i ca u vo X cho ti khi u ra Y bt u xy ra s mt n nh. Sau giai on mt n nh hay cn gi l giai on chuyn tip tn hiu ti u ra s thit lp trng thi xc nh vng bn. Nh vy Tpd > Tcd v khi nhc n tr ca cng th l ch ti gi tr Tpd. 1.4. Phn t nh 1.4.1. D-Latch v D flip-flop Latch v Flip-Flop l cc phn t nh quan trng trong thit k VLSI, s cu to chi tit v m t c trnh by k trong phn K thut s. phn ny ch nhc li nhng tnh cht c bn nht ca cc Flip-Flop v b xung thm cc tham s thi gian thc ca cc phn t ny. Bng 1-1 D-Flip flop v D-latch D-flip flop D-latch D Q Clock D Q Qprev Clock D Q Q Rising edge 1 1 x 0 X Qprev Rising edge 0 0 x 1 D Non-rising x Qprev D-Latch l phn t nh lm vic theo mc xung, c th khi tn hiu Clock bng 1 th gi tr Q u ra bng gi tr u vo, khi tn hiu Clock = 0 th gi tr u ra khng i. Ni mt cch khc D-latch lm vic nh mt ca ng m gia tn hiu Q v D tng ng vi mc in p ca xung Clock. D-flip-flop l phn t nh lm vic theo sn xung, c hai dng sn l sn ln (rising edge) khi xung thay i t 0->1 v sn xung (falling edge) khi xung thay i t 1->0. Khi khng c yu cu g c bit th Flip-flop lm vic vi sn xung ln thng c s dng. Khc vi D-latch gi tr u ra ca FlipFlop ch thay vo thi im sn xung . Vi cch lm vic nh vy gi tr u ra s khng thay i trong sut thi gian mt chu k xung nhp d cho tn hiu u vo thay i. D Flip-flop rt hay c dng trong mch c nh v vy i khi ni n phn t nh thng ngm hiu l D Flip-flop.
SET CLR

20

In Clk

Out

In Out Clk

In Clk

Out

In Out Clk

Latch

Flip-Flop

Hnh 1-6. th thi gian ca D Flip-flop v D Latch i vi D-flip-flop v D-latch nh th c hai tham s thi gian ht sc quan trng l Tsetup, v Thold. y l tham s thi gian i vi d liu u vo cng Din m bo vic truyn d liu sang cng ra Qout l chnh xc, c th i vi Flip-flop. Tsetup: l khong thi gian cn thit cn gi n nh u vo trc sn tch cc ca xung nhp Clock Thold: L khong thi gian ti thiu cn gi n nh d liu u vo sau sn tch cc ca xung nhp Clock.
Din Tsetup Thold CLK Tclk_q Qout

Hnh 1-7. Tham s thi gian ca D-Flip-Flop 1.4.2 Cc flip-flop khc - RS Flip-flop: Bng 1-2 RS Flip-flop
R 0 0 1 1 S 0 1 0 1 Qnext Qprev 1 0 Chy ua
S
SET

CLR

21

RS Flip-flop c u vo l hai tn hiu Reset v Set. Set =1 th tn hiu u ra nhn gi tr 1 khng ph gi tr hin ti Q, Reset =1 th u ra Q = 0 khng ph thuc gi tr hin ti Q. i vi RS-flipflop khng ng b th gi tr Q thay i ph thuc R/S ngay tc th, cn i vi RS flip-flop ng b th tn hiu Q ch thay i ti thi im sn xung Clock. Trng thi khi R= 1, S= 1 l trng thi cm v kh u ra nhn gi tr khng xc nh, thc cht s xy ra s thay qu trnh chy ua hay t dao ng gi tr Q t 0 n 1 v ngc li vi chu k bng tr chuyn mch ca flip-flop. - JK-flip-flop Bng 1-3 JK Flip-flop
J 0 0 1 1 K 0 1 0 1 Qnext Qprev 0 1 NOT Qprev
J
SET

CLR

Theo bng chn l JK-flip flip hot ng kh linh hot thc hin chc nng ging nh D-flip flop hoc RS flip-flop, trng thi kh J=0, K=1 l Reset, J=1, K=0 l Set. Tuy khng c u vo d liu D nhng JK flip-flop lm vic nh mt D-flip flip th tn hiu D ni vi J cn K cho nhn gi tr i ca J. T- flip-flop Bng 1-4 T Flip-flop
T 0 0 1 1 Q 0 1 0 1 Qnext 0 1 1 0

Khi T bng 1 th gi tr Qnextbng o ca gi tr trc Qprev khi T = 0 th gi tr u ra khng thay i

22

1.5 Mch logic t hp Mch logic t hp (Combinational logic circuit) l mch m gi tr t hp tn hiu ra ti mt thi im ch ph thuc vo gi tr t hp tn hiu vo ti thi im . Hiu mt cch khc mch t hp khng c trng thi, khng cha cc phn t nh m ch cha cc phn t thc hin logic chc nng nh AND, OR, NOT i vi mch t hp tham s thi gian tr Tdelay l khong thi gian ln nht k t thi im xc nh tt c cc gi tr u vo cho ti thi im tt c cc kt qu u ra tr nn n nh. Trn thc t vi vi mch tch hp vic thi gian tr rt nh nn vic tm tham s tr ca mch c thc hin bng cch lit k tt c cc ng bin i tn hiu c th t tt c cc u vo ti tt c u ra sau da trn thng s v thi gian ca cc cng v tr ng truyn c th tnh c tr ca cc ng truyn ny v tm ra ng truyn c tr ln nht, gi tr chnh l Tdelay.

Hn h 1-8. tr ca mch t hp Minh ha cho tr trong mch t hp nh hnh 1-8. V l thuyt xc nh tr ca mch cn lit k tt c cc ng tn hiu t 4 u vo In1, In2, In3, In4 n 2 u ra Out1, Out2. i vi mi cp u ra u vo tn ti nhiu ng truyn khc nhau v vy tng s lng cc ng truyn ny thng rt ln. Chnh v th i vi nhng mch t hp ln th vic xc nh tr u phi thc hin bng s h tr ca my tnh. V d xc nh tr ca hai ng truyn 1 v 2 trn hnh v: ng 1 ln lt i qua cc cng NOT, AND_4, NOR, AND_3, OR. ng 2 ln lt i qua cng NOT, AND, OR_4, AND_4, OR_4. tr ca cc ng truyn ny tnh bng tr ca cc cng n i qua cng vi tr dy dn (TWrite). 23

T1 = TNOT + TAND_4 + TNOR + TAND_3 + T AND_3 + TWire1 (1.1) T2 = TNOT + TAND + TOR_4 + TAND_4 + T OR_4 + TWire2 (1.2) Do tr ca cng nhiu u vo ln hn tr ca cng t u vo nn mc d s cng i qua trn ng truyn nh nhau nhng ng truyn 2 s c tr ln hn ng 1. Cc ng truyn c tr ln nht c gi l Critical paths. Cc ng truyn ny cn c bit quan tm trong qu trnh ti u ha tr ca mch. 1.6. Mch logic tun t Mch logic dy (Sequential logic circuits) cn c gi l mch logic tun t l mch s m tn hiu ra ti mt thi im khng nhng ph thuc vo t hp tn hiu u vo ti thi im m cn ph thuc vo tn hiu vo ti cc thi im trc . Hiu mt cch khc mch dy ngoi cc phn t t hp c cha cc phn t nh v n lu tr ln hn mt trng thi ca mch. Tham s thi gian ca mch tun t c tnh khc vi mch t hp, s khc bit c quan h mt thit vi c im ca tn hiu ng b Clock. V d vi mt mch tun t in hnh di y. Mch to t hai lp thanh ghi s dng Flip-flop A v B, trc gia v sau thanh ghi l ba khi logic t hp Combinational logic 1, 2, 3, cc tham s thi gian c th nh sau: Td1, Td2, Td3. L thi gian tr tng ng ca 3 khi mch t hp 1, 2, 3. Tsa, Tsb l thi gian thit lp (Tsetup) ca hai Flipflop A, B tng ng Tclk-q. l khong thi gian cn thit d liu ti u ra Q xc nh sau thi im kch hot ca sn Clock
D
Combinational logic1
CLR SET

Q
Combinational logic2

SET

Q
Combinational logic3

CLR

Tskew Td1 Tsa Tclk-q Td2 Tsb Tclk-q Td3

Hnh 1-9. Tham s thi gian ca mch tun t i vi mch ng b th s l l tng nu nh im kch hot (sn ln hoc sn xung) ca xung nhp Clock ti cc Flip-flop cng mt thi im. Tuy vy trn thc t bao gi cng tn ti tr gia hai xung Clock n hai Flip-flop khc nhau. Tskew l tr ln nht ca xung nhp Clock n hai Flip-flop khc 24

nhau trong mch. Thi gian chnh lch ln nht gia tn hiu xung nhp , thi gian tr ny sinh ra do tr trn ng truyn ca xung Clock t A n B. Trn thc t Tskew gia hai Flip-flop lin tip c gi tr rt b so vi cc gi tr tr khc v c th b qua, nhng i vi nhng mch c ln khi s lng Flip-flop nhiu hn v phn b xa nhau th gi tr Tskew c gi tr tng i ln. Nhng tham s trn cho php tnh ton cc c trng thi gian ca mch tun t l: - Thi gian tr trc xung nhp Clock ti u vo Tinput_delay = Td1 + Tsa (1.3) - Thi gian tr sau xung nhp Clock ti u ra. Toutput_delay = Td3 + Tclk_q (1.4) - Chu k ti thiu ca xung nhp Clock, hay l khong thi gian ti thiu m bo cho d liu trong mch c x l v truyn ti gia hai lp thanh ghi lien tip m khng xy ra sai st. Nu xung nhp u vo c chu k nh hn Tclk_min th mch s khng th hot ng theo thit k. Tclk_min = Tclk-q + Td2 + Tsb + Tskew (1.5) - T tnh c xung nhp ti a ca vi mch l Fmax = 1/ Tclk_min = 1/( Tclk-q + Td2 + Tsb + Tskew) (1.6) 1.7 Cc phng php th hin thit k. C hai phng php c bn c s dng m t vi mch s l m t bng s logic (schematic) v m t bng ngn ng m t phn cng HDL (Hardware Description Language). M t bng s : vi mch c m t trc quan bng cch ghp ni cc phn t logic khc nhau mt cch trc tip ging nh v d hnh v di y. Thng thng cc phn t khng n thun l cc i tng ha m cn c cc c tnh vt l gm chc nng logic, thng s ti vo ra, thi gian tr Nhng thng tin ny c lu tr trong th vin logic thit k. Mch v ra c th c m phng kim tra chc nng v pht hin v sa li mt cch trc tip.

25

D1

U1 U14 AND-2 U2 NOR

D2

AND-2

U3

U13 NOR U12

AND-2 D3 U4

NOR AND-2 U5 U11 AND-2 U6 AND-2 AND-2 U7 R AND-2 U8 NOR U10

S
AND-2 U9 AND-2 U15 AND-2

SET

CLR

Hnh 1-10. M t mch s bng s u im ca phng php ny l cho ra s cc khi logic r rng thun tin cho vic phn tch mch, tuy vy phng php ny ch c s dng thit k nhng mch c nh, phc tp khng cao. i vi nhng mch c ln hng trm ngn cng logic th vic m t ha l gn nh khng th v nu c th cng tn rt nhiu thi gian, cha k nhng kh khn trong cng vic kim tra li trn mch sau . M t bng HDL: HDL cho php m t vi mch bng cc c php tng t nh c php ca ngn ng lp trnh. C ba ngn ng m t phn cng ph bin hin nay l: Verilog: Ra i nm 1983, do hai k s Phil Moorby v Prabhu Goel lm vic ti Automated Integrated Design Systems (sau ny thuc s hu ca Cadence). Verilog c IEEE chnh thc tiu chun ha vo nm 1995 v sau l cc phin bn nm 2001, 2005. y l mt ngn ng m t phn cng c cu 26

trc v c php gn ging vi ngn ng lp trnh C, ngoi kh nng h tr thit k logic th Verilog rt mnh trong vic h tr cho qu trnh kim tra thit k. VHDL: VHDL vit tt ca Very-high-speed intergrated circuits Hardware Description Language, hay ngn ng m t cho cc mch tch hp tc cao. VHDL ln u tin c pht trin bi B Quc Phng M nhm h tr cho vic thit k nhng vi mch tch hp chuyn dng (ASICs). VHDL cng c IEEE chun ha vo cc nm 1987, 1991, 2002, v 2006 v mi nhts 2009. VHDL c pht trin da trn cu trc ca ngn ng lp trnh Ada. Cu trc ca m t VHDL tuy phc tp hn Verilog nhng mang tnh logic cht ch v gn vi phn cng hn. AHDL: Altera HDL c pht trin bi cng ty bn dn Altera vi mc ch dng thit k cho cc sn phm FPGA v CPLD ca Altera. AHDL c cu trc ht sc cht ch v l ngn ng rt kh s dng nht so vi 2 ngn ng trn. B li AHDL cho php m t thc th logic chi tit v chnh xc hn. Ngn ng ny t ph bin tuy vy n cng c rt nhiu chng trnh phn mm h tr m phng bin dch. Bn cnh cc ngn ng trn th mt lot cc ngn ng khc v ang pht trin cng h tr kh nng m t phn cng, ng ch l System Verilog l phin bn m rng ca Verilog hng ca C++ nh h tr cc kiu d liu khc nhau, s dng Class v nhiu hm h thng bc cao. SystemC khng hon ton phi l mt HDL m l mt dng m rng ca C++ cho php h tr kim tra cc thit k bng VHDL hay Verilog.

2. Yu cu i vi mt thit k logic
Yu cu i vi mt thit k IC bao gm: Yu cu chc nng: mch gm c cc u vo u ra nh th no, thc hin nhim v g Yu cu v mt cng ngh: Mch thit k s dng nn cng ngh bn dn no PLD, ASIC, FPGA Yu cu v mt ti nguyn: Gii hn v s lng cng, s lng transitors, v din tch quy i chun, v kch thc ca IC thit k. Yu cu v kh nng lm vic (performance): l yu cu v cc tham s thi gian ca mch bao gm tr cng vo, tr cng ra, tr logic vi mch t hp, cc xung nhp lm vic, s lng xung nhp cho mt chu trnh x l d liu, s lng d liu x l trn mt n v thi gian. 27

 Yu cu v mc tiu hao nng lng (power consumtion). Yu cu v chi ph cho qu trnh thit k v ch to (design cost). Cc yu cu k trn c quan h mt thit vi nhau v thng thng chng khng th ng thi t c ti u. V d nng lng tiu th ca mch mun nh th s lng cng s dng hn ch v s hn ch tc lm vic, hoc vic s dng cc cng ngh r tin hn hoc dng cc cng cng xut thp cng l nhn t gim hiu nng lm vic ca mch. Trong thc t Cc IC phc v cc mc ch khc nhau th c yu cu khc nhau v ngi lp k hoch thit k ch to IC cn phi cn i gia cc tiu ch c mt phng n ti u nht. V d cng l vi x l nhng nu dng th khng c yu cu c bit v mt tiu hao nng lng do ngun cp l c nh, khi Chip phi c thit k c hiu sut lm vic ti a. Trong khi vi x l cho my tnh xch tay th cn phi thit k c mc tiu th nng lng thp nht c th hoc c th hot ng nhiu mc tiu th nng lng khc nhau nhm ko di thi gian s dng. Chip iu khin cho cc thit b di ng th cn phi ti u ht mc mc tiu tn nng lng bng cch thu gn thit k, gim thiu nhng tp lnh khng cn thit v s dng cc phn t tit kim nng lng nht

3. Cc cng ngh thit k mch logic s

Vi mch s n gin c th c thit k th cng (Manual IC design), nhng vi cc vi mch s c ln th qu trnh thit k buc phi s dng cc chng trnh h tr thit k trn my tnh (Design Automation) Manual design: Vi mch s c th c thit k bi cch ghp ni cc linh kin bn dn ri rc. S ra i cc IC a dng h 74XX hay 40XX cho php ngi s dng c th t thit k nhng mch s c nh v c va bng cch ghp ni trn mt bn mch in. Nh c cu trc chun ha, c th d dng ghp ni, to nhng mch chc nng khc nhau. Trn thc t nhng mch dng ny v vn ang c ng dng rng ri. im hn ch duy nht ca nhng thit k dng ny l chng ch ph hp cho nhng thit k SSI n gin do gii hn v mt tch hp v tc lm vic thp.

28

IC Design

Manual Design

Design Automation

7400 Series (TTL)

4000 Series (CMOS)

Discrete components

Programable Device Based

Full-custom Semi-custom ASIC ASIC

SPLD

CPLD

Field PD (FPGA)

PROM (EPROM, E2PROM)

PLA

PAL

GAL

Hnh 1-11. Phn loi thit k vi mch s Design Automation My tnh l mt sn phm c trng nht ca nn cng nghip sn xut ch to bn dn nhng ngay sau khi ra i tr thnh cng c c lc cho vic thit k m phng IC ni ring v cc thit b khc ni chung. T ng ha thit k khng nhng gip n gin ha v rt ngn ng k thi gian thit k sn phm m cn em li nhng kh nng m qu trnh thit k th cng bi con ngi khng lm c l: Kh nng lm vic vi nhng thit k phc tp ti c hng nghn n hng t transitor. Kh nng x l nhng bi ton ti u vi nhiu tiu ch v nhiu iu kin rng buc phc tp. Kh nng t ng tng hp thit k t cc mc tru tng cao xung cc mc tru tng thp hn mt cch chnh xc, nhanh chng. n gin ha vic lu tr v trao i d liu thit k. Cc phn mm h tr thit k gi chung l CAD Tools, trong lnh vc thit k ASIC c 3 h thng phn mm ph bin ca Cadence, Synopsys, Magma Design Automation Inc. Trong thit k trn FPGA ph bin c Xilinx, Altera.

29

Trong t ng ha thit k IC thng phn bit thnh nhng quy trnh nh sau: Full-custom ASIC: l quy trnh thit k IC c mc chi tit cao nht nhm thu c sn phm c hiu qu lm vic cao nht trong khi vn t ti u v mt ti nguyn trn nn mt cng ngh bn dn nht nh. t c mc ch thit k khng nhng c ti u nhng mc cao m cn c ti u mc b tr transitor v kt ni gia chng, v dng hai khi logic cng thc hin hm OR nhng phn b hai v tr khc nhau th c cu trc bng cc mch transitor khc nhau, ph thuc vo cc thng s khc nh ti u vo u ra, v tr, nh hng cc khi lin kChnh v th Full-custom ASIC i khi cn c gi l random-logic gate networks ngha l mch to bi nhng cng khng ng nht. Semi-custom ASIC design: Phn bit vi Full-custom ASIC design, khi nim ny ch quy trnh thit k m mc chi tit khng t n ti a, thng thng thit k t chi tit n mc cng logic hoc cao hn. Do Full-custom ASIC c phc tp cao nn khng nhng chi ph cho qu trnh thit k rt ln mt khc thi gian dnh cho thit k c th ko di hng vi nm tr ln, trong thi gian c th c nhng cng ngh mi ra i, mi mt thay i nh ko theo vic phi lm li gn nh ton b thit k v pht sinh thm chi ph rt nhiu do vy li nhun sn phm bn ra thp hay thm ch thua l. Semi-custom ASIC cn bng gia chi ph thit k v li nhun thu c sn phm bng cch y nhanh v gim thiu chi ph cho qu trnh thit k, d nhin b li sn phm lm ra khng t c mc ti u l thuyt nh Full-custom design. C nhiu dng Semi-custom design nhng mt trong nhng kiu c bn m thng c s dng l thit k trn c s th vin cng chun (Standard Cell Library), th vin ny l tp hp ca cc cng logic nh AND, OR, XOR, thanh ghi v v chng c cng kch thc chiu cao nn c gi l cng chun. ASIC based on Programmable Device: Thit k ASIC trn c s IC kh trnh. Chp kh trnh (Programmable device) c hiu l IC cha nhng phn t logic c th c lp trnh can thip ti cu trc nhm thc hin mt chc nng no . Qu trnh ti cu trc thc hin thng qua ngn ng m t phn cng nn thng c gi ngn gn l lp trnh. IC kh trnh c chia thnh cc dng sau: SPLD (Simple Programmable Logic Device) Nhm nhng IC kh trnh PROM, PAL, PLA, GAL. c im chung ca nhm ny l cha mt s lng 30

cng tng ng t vi chc (PROM) n vi trm (PAL, GAL) cng, nhm ny s dng cu trc ca b nh ROM lu cu hnh IC, (v vy nhm ny cn gi l Memory-based PLD), cu trc ny bao gm mt mng ma trn AND v mt mng ma trn OR c th cu trc c. Trong cc chip dng ny li chia lm hai, th nht l loi ch lp trnh mt ln, v loi c kh nng ti lp trnh dng cc cng ngh nh EEPROM hay EPROM. Cu trc c th v nguyn l lm vic ca PROM, PAL, PLA, GAL, FPGA, CPLD s c ln lt c trnh by chi tit phn tip theo. CPLD (Complex Programmable Logic Device) CPLD l IC lp trnh phc tp thng c ghp t nhiu cc SPLD trn mt chip n. S cng tng ng ca CPLD t t hng nghn n hng chc nghn cng. FPGA (Field-Programmable Gate Array) l IC kh trnh cu trc t mng cc khi logic lp trnh c. Nu nh i vi cc PLD khc vic ti cu trc IC c thc hin trong iu kin ca nh my sn xut bn dn, qu trnh ny cn nhng mt n cho quang khc nn s dng lp nhng PLD ny c gi chung bng thut ng Mask-Programmable Device. FPGA phn bit chnh vi cc loi trn kh nng ti cu trc IC bi ngi dng cui hay chnh l ngi lp trnh IC.

4. Kin trc ca cc IC kh trnh

Trong K thut s ta ch ra mi hm logic t hp u c th biu din di dng chun tc tuyn tc l di dng tng ca cc tch y , hoc chun tc hi, tc l dng tch ca cc tng y . Hai cch biu din ny l hon ton tng ng. Nguyn l ny cho php hin thc ha h hm logic t hp bng cch ghp hai mng ma trn nhn (AND) v ma trn cng (OR). Nu mt trong cc mng ny c tnh kh trnh th IC s c tnh kh trnh. Ta s ln lt nghin cu cu trc ca mt s loi IC hot ng trn nguyn l ny. 4.1. Kin trc PROM, PAL, PLA, GAL 4.1.1. PROM PROM (Programmable Read-Only Memory) c pht minh bi Wen Tsing Chow nm 1956 khi lm vic ti Arma Division ca cng ty American Bosch Arma ti Garden, New York. PROM c ch to theo n t hng t lc lng khng qun ca M lc by gi vi mc ch c c mt thit b lu 31

tr cc tham s v mc tiu mt cc an ton v linh ng. Thit b ny dng trong my tnh ca h thng phng tn la Atlas E/F v c gi b mt trong vng vi nm trc khi Atlas E/F tr nn ph bin. PROM l vi mch lp trnh u tin v n gin nht trong nhm cc vi mch bn dn lp trnh c (Programmable Logic Device). PROM c s u vo hn ch, thng thng n 16 n 32 u vo, v vy ch thc hin c nhng hm n gin. Cu trc ca PROM to bi ma trn to bi mng c nh cc phn t AND ni vi mng cc phn t OR lp trnh c.
a b c Mng OR lp trnh c

T1

x
T2

x x x

x x

T3

T4 T5

x x x x x

T6

T7 T8

x x x

Mng AND c nh x y z w

Hnh 1-12. Cu trc PROM Ti mng nhn AND, cc u vo s c tch thnh hai pha, v d a thnh pha thun a v nghch , cc chm () trong mng lin kt th hin kt ni cng, tt c cc kt ni trn mi ng ngang sau c thc hin php logic AND, nh vy u ra ca mi phn t AND l mt nhn t tng ng ca cc u vo. V d nh hnh trn thu c cc nhn t T1,T3 nh sau:

32

Cc nhn t c gi tip n mng cng OR, mng ny X dng biu din kt ni lp trnh c. trng thi cha lp trnh th tt c cc im ni u l X tc l khng kt ni, tng t nh trn, php OR thc hin i vi ton b cc kt ni trn ng ng v gi ra cc u ra X, Y, Z,... Tng ng vi mi u ra nh vy thu c hm di dng tng ca cc nhn t, v d tng ng vi u ra Y: + (1.6)

Tnh kh trnh ca PROM c thc hin thng qua cc kt ni antifuse (cu ch ngc). Antifuse l mt dng vt liu lm vic vi c ch nh vt liu cu ch (fuse) nhng theo chiu ngc li. Nu nh cu ch trong iu kin kch thch (qu ti v dng in) th nng chy v ngt dng th antifuse trong iu kin tng t nh tc ng hiu th ph hp s bin i t vt liu khng dn in thnh dn in. trng thi cha lp trnh th cc im ni l antifuse ngha l ngt kt ni, khi lp trnh th ch nhng im ni xc nh b t to kt ni vnh vin. Qu trnh ny ch c thc hin mt ln v theo mt chiu v PROM khng th ti lp trnh c. Nhng IC dng PROM c kh nng ti lp trnh l UEPROM (UltravioletEraseable PROM) s dng tia cc tm v EEPROM (Electric-Eraseable PROM) s dng hiu in th ngng cao thit lp li cc kt ni trong ma trn lp trnh. 4.1.2. PAL PAL(Programmable Array Logic) ra i cui nhng nm 1970s. Cu trc ca PAL k tha cu trc ca PROM, s dng hai mng logic nhng nu nh PROM mng OR l mng lp trnh c th PAL mng AND lp trnh c cn mng OR c gn cng, ngha l cc thnh phn tch c th thay i nhng t hp ca chng s c nh, ci tin ny to s linh hot hn trong vic thc hin cc hm khc nhau. Ngoi ra cu trc cng ra ca PAL cn phn bit vi PROM mi u ra ca mng OR lp trnh c c dn bi khi logic gi l Macrocell. Hnh di y minh ha cho cu trc ca macrocell. Mi macrocell cha 1 Flip-Flop Register, hai b dn knh (Multiplexers) 2 v 4 u vo Mux2, Mux4. u ra ca Mux2 thng qua mt cng 3 trng thi tr li mng AND, thit k ny cho

33

kt qu u ra c th s dng nh mt tham s u vo, tt nhin trong trng hp th kt qu u ra buc phi i qua Flip-flop trc.
a b c Mng OR c nh

T1

T2

T3

T4

x
T5

Mng AND lp trnh c

macrocell

y macrocell

z macrocell

w macrocell

Hnh 1-13. Cu trc PAL u ra ca macrocell cng thng qua cng 3 trng thi c th lp trnh c ni vi cng giao tip ca PAL. Tn hiu iu khin ca Mux4 c th c lp trnh cho php dn tn hiu ln lt qua cc u vo 0,1,2,3 ca Mux4 v gi ra ngoi cng giao tip IO, ty thuc vo cu hnh ny m tn hiu ti IO c th b chn (khng gi ra), dn trc tip t mng OR, thng qua thanh ghi Register. Nh cu trc macrocell PAL c th c s dng khng nhng thc hin cc hm logic t hp m c cc hm logic tun t.

2
D
SET

3 0 Mux4
ENB

IO

CLR

1 S0

S1 programmable

ENB

Mux2

0 1

Hnh 1-14. Cu trc Macrocell 34

4.1.3. PLA PLA (Programable Logic Array) ra i nm 1975 v l chp lp trnh th hai sau PROM. Cu trc ca PLA khng khc nhiu so vi cu trc ca PAL, ngoi tr kh nng lp trnh c hai ma trn AND v OR. Nh cu trc PLA c kh nng lp trnh linh ng hn, b li tc ca PLA thp hn nhiu so vi PROM v PAL v cc sn phm cng loi khc. Thc t PLA c ng dng khng nhiu v nhanh chng b thay th bi nhng cng ngh mi hn nh PAL, GAL, CPLD
a b c Mng OR lp trnh c

T1

T2

T3

T4

x
T5

Mng AND lp trnh c

macrocell

macrocell

macrocell

macrocell

Hnh 1-15. Cu trc PLA 4.1.4. GAL GAL (Generic Array Logic) c pht trin bi Lattice Semiconductor company vo nm 1983, cu trc ca GAL khng khc bit PAL nhng thay v lp trnh s dng cng ngh antifuse th GAL dng CMOS electrically erasable PROM, chnh v vy i khi tn gi GAL t c s dng thay v GAL c hiu nh mt dng PAL c ci tin.

35

4.2. Kin trc CPLD, FPGA 4.2.1. CPLD Tt c cc chip kh trnh PROM, PAL, GAL, thuc nhm SPLD (Simple Programmable Logic Devices) nhng IC ny c u im l thit k n gin, chi ph thp cho sn xut cng nh thit k, c th chuyn d dng t cng ngh ny sang cng ngh khc tuy vy nhc im l tc lm vic thp, s cng logic tng ng nh do khng p ng c nhng thit k phc tp i hi nhiu v ti nguyn v tc . CPLD (Complex Programmable Logic Devices) c Altera tin phong nghin cu ch to u tin nhm to ra nhng IC kh trnh dung lng ln MAX5000, MAX7000, MAX9000 l h nhng CPLD tiu biu ca hng ny. Sau s thnh cng ca Altera mt lot cc hng khc cng bt tay vo nghin cu ch to CPLD, Xilinx vi cc sn phm XC95xx series, Lattice vi isp Mach 4000 serise, ispMarch XO

Logic block

Logic block

Logic block

Logic block

Programmable Interconnect matrix

Logic block Logic block

Logic block

Logic block

Hnh 1-16. Cu trc CPLD Mt cch n gin nht c th hiu CPLD c cu trc bng cch ghp nhiu cc chp SPLD li, thng thng l PAL. Tuy vy v bn cht phc tp ca CPLD vt xa so vi cc IC nhm SPLD v cu trc ca cc CPLD cng rt

36

a dng, ph thuc vo tng hng sn xut c th. Di y s trnh by nguyn l chung nht ca cc chip h ny. CPLD c to t hai thnh thnh phn c bn l nhm cc khi logic (Logic block) v mt ma trn kt ni kh trnh PIM (Programmable Interconnect Matrix). Logic block l cc SPLD c ci tin thng cha t 8 n 16 macrocells. Tt c cc Logic block ging nhau v mt cu trc. PIM l ma trn cha cc kt ni kh trnh, nhim v ca ma trn ny l thc hin kt ni gia cc LB v cc cng vo ra IO ca CPLD. V mt l thuyt th ma trn ny c th thc hin kt ni gia hai im bt k. CPLD thng thng s dng cc cng ngh lp trnh ca EEPROM, im khc bit l i vi CPLD thng khng th dng nhng programmer n gin cho PAL, PLA v s chn giao tip ca CPLD rt ln. thc hin cu hnh cho CPLD mi mt cng ty pht trin ring cho mnh mt b cng c v giao thc, thng thng cc chip ny c gn trn mt bo mch in v d liu thit k c ti vo t my vi tnh. Tuy vy cc quy trnh np trn ang dn b thay th bi giao thc chun JTAG (Join Test Action Group) chun, y cng l giao thc dng cu trc cho FPGA m ta s nghin cu k hn chng k tip. Nh k tha cu trc ca SPLD nn CPLD khng cn s dng b nh ROM ngoi lu cu hnh ca IC, y l mt c im c bn nht phn bit CPLD vi cc IC kh trnh c ln khc nh FPGA. 4.2.2. FPGA V cu trc chi tit v c ch lm vic ca FPGA s c dnh ring gii thiu trong chng sau. y ch gii thiu kin trc tng quan nht ca IC dng ny. FPGA c cu thnh t cc khi logic (Logic Block) c b tr di dng ma trn, chng c ni vi nhau thng qua h thng cc knh kt ni lp trnh c H thng ny cn c nhim v kt ni vi cc cng giao tip IO_PAD ca FPGA.

37

IO_PAD

IO_PAD

IO_PAD

..

FPGA l cng ngh IC lp trnh mi nht v tin tin nht hin nay. Thut ng Field-Programmable ch qu trnh ti cu trc IC c th c thc hin bi ngi dng cui, trong iu kin bnh thng. Ngoi kh nng FPGA c mt tch hp logic ln nht trong s cc IC kh trnh vi s cng tng ng ln ti hng trm nghn, hng triu cng. FPGA khng dng cc mng lp trnh ging nh trong cu trc ca PAL, PLA m dng ma trn cc khi logic. im khc bit c bn th ba ca FPGA so vi cc IC k trn l c ch ti cu trc, ton b cu hnh ca FPGA thng c lu trong mt b nh ng (RAM), chnh v th m khi ng dng FPGA thng phi km theo mt ROM ngoi vi np cu hnh cho FPGA mi ln lm vic. Kin trc v cch thc lm vic ca FPGA s c nghin cu c th chng th 3 ca gio trnh ny.

IO_PAD IO_PAD IO_PAD

IO_PAD

LOGIC BLOCK

LOGIC BLOCK

..

LOGIC BLOCK

LOGIC BLOCK

LOGIC BLOCK

..

IO_PAD

LOGIC BLOCK

LOGIC BLOCK

IO_PAD

LOGIC BLOCK

IO_PAD

Hnh 1-17. Kin trc tng quan ca FPGA

IP_COREs, RAM, ROM...

Interconnect wires

IO_PAD

..

LOGIC BLOCK

..

IO_PAD

38

Cu hi n tp chng 1
1. Transitor khi nim, phn loi. 2. Khi nim, phn loi vi mch s tch hp. 3. Cng logic c bn, tham s thi gian ca cng logic t hp. 4. Cc loi Flip-flop c bn, tham s thi gian ca Flip-flop. 5. Khi nim mch logic t hp, cch xc nh tr trn mch t hp, khi nim critical paths. 6. Khi nim mch dy, cch tnh thi gian tr trn mch dy, khi nim RTL, phng php tng hiu sut mch dy. 7. Cc yu cu chung i vi thit k mch logic s. 8. Cc phng php th hin thit k mch logic s. 9. Cc cng ngh thit k mch logic s, khi nim, phn loi. 10. Trnh by s lc v cc cng ngh thit k IC s trn chip kh trnh. 11. Nguyn l hin thc ha cc hm logic trn cc IC kh trnh dng PROM, PAL, PLA, GAL. 12. Khi nim thit k ASIC, cc dng thit k ASIC. 13. Khi nim FPGA, c im FPGA.

39

40

Chng 2 NGN NG M T PHN CNG VHDL

Chng 2 tp trung vo gii thiu v ngn ng m t phn cng VHDL, y l mt ngn ng m t phn cng c tnh ng dng cao nhng cng c c php khng quen thuc v d tip cn. Ni dung kin thc trnh by trong chng ny theo nh hng nh mt ti liu tra cu hn l bi ging. Ngi hc khng nht thit phi theo ng trnh t kin thc trnh by m c th tham kho tt c cc mc mt cch c lp, bn cnh l tra cu bng cc ti liu khc cng nh ti liu gc bng ting Anh. Cc v d c trong gio trnh u c gng trnh by l cc v d y c th bin dch v m phng c ngay v vy khuyn khch ngi hc tch cc thc hnh song song vi nghin cu l thuyt. Kt thc ni dung ca chng ny yu cu ngi hc phi c k nng s dng VHDL cp c bn, c kh nng thit k cc khi s va v nh nh Flip-flop, khi chn knh, phn knh, khi cng, dch, cc khi gii m bit trong chng trnh in t s, cng l cc khi nn tng cho cc thit k ln hn v phc tp hn chng tip theo.

41

1. Gii thiu v VHDL

VHDL vit tt ca VHSIC HDL (Very-high-speed-intergrated-circuit Hardware Description Language) hay ngn ng m t phn cng cho cc vi s mch tch hp tc cao. Lch s pht trin ca VHDL tri qua cc mc chnh nh sau: 1981: Pht trin bi B Quc phng M nhm to ra mt cng c thit k phn cng tin dng c kh nng c lp vi cng ngh v gim thiu thi gian cng nh chi ph cho thit k 1983-1985: c pht trin thnh mt ngn ng chnh thng bi 3 cng ty Intermetrics, IBM and TI. 1986: Chuyn giao ton b bn quyn cho Vin K thut in v in t (IEEE). 1987: Cng b thnh mt chun ngn ng IEEE-1076 1987. 1994: Cng b chun VHDL IEEE-1076 1993. 2000: Cng b chun VHDL IEEE-1076 2000. 2002: Cng b chun VHDL IEEE-1076 2002 2007: cng b chun ngn ng Giao din ng dng theo th tc VHDL IEEE-1076c 2007 2009: Cng b chun VHDL IEEE-1076 2009 VHDL ra i trn yu cu ca bi ton thit k phn cng lc by gi, nh s dng ngn ng ny m thi gian thit k ca sn phm bn dn gim i ng k, ng thi vi gim thiu chi ph cho qu trnh ny do c tnh c lp vi cng ngh, vi cc cng c m phng v kh nng ti s dng cc khi n l. Cc u im chnh ca VHDL c th lit k ra l: Tnh cng cng: VHDL l ngn ng c chun ha chnh thc ca IEEE do c s h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng, hu nh tt c cc cng c thit k ca cc hng phn mm ln nh u h tr bin dch VHDL. c h tr bi nhiu cng ngh: VHDL c th s dng m t nhiu loi vi mch khc nhau trn nhng cng ngh khc nhau t cc th vin ri rc, CPLD, FPGA, ti th vin cng chun cho thit k ASIC. Tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng chc nng dng VHDL thit k mc thanh ghi truyn ti RTL c th c tng hp thnh cc mch trn cc cng ngh bn dn khc nhau. Ni mt cch khc khi mt cng ngh phn cng mi ra i n 42

c th c p dng ngay cho cc h thng thit k bng cch tng hp cc thit k li trn th vin phn cng mi. Kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc thanh ghi truyn ti (RTLRegister Tranfer Level) cho n mc cng (Netlist). Hiu mt cch khc VHDL c mt cu trc m t phn cng cht ch c th s dng lp m t chc nng cng nh m t cng trn mt th vin cng ngh c th no . Kh nng trao i, ti s dng: Vic VHDL c chun ha gip cho vic trao i cc thit k gia cc nh thit k c lp tr nn ht sc d dng. Bn thit k VHDL c m phng v kim tra c th c ti s dng trong cc thit k khc m khng phi lp li cc qu trnh trn. Ging nh phn mm th cc m t HDL cng c mt cng ng m ngun m cung cp, trao i min ph cc thit k chun c th ng dng nhiu h thng khc nhau.

2. Cu trc ca chng trnh m t bng VHDL

Cu trc tng th ca mt khi thit k VHDL gm ba phn, phn khai bo th vin, phn m t thc th v phn m t kin trc.

Khai bo th vin LIBRARY declaration

M t thc th ENTITY Declaration

M t kin trc ARCHITECTURE Hnh vi Behavioral Lung d liu DataFlow Cu trc Structure

Hnh 2-1. Cu trc ca mt thit k VHDL

43

2.1. Khai bo th vin Khai bo th vin phi c t u tin trong mi thit k VHDL, lu rng nu ta s dng mt tp m ngun cha nhiu khi thit k khc nhau th mi mt khi u phi yu cu c khai bo th vin u tin, nu khng khi bin dch s pht sinh ra li. V d v khai bo th vin
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

Khai bo th vin bt u bng t kha Library Tn th vin (ch l VHDL khng phn bit ch hoa ch thng). Sau trn tng dng k tip s khai bo cc gi th vin con m thit k s s dng, mi dng phi kt thc bng du ;. Tng t nh i vi cc ngn ng lp trnh khc, ngi thit k c th khai bo s dng cc th vin chun hoc th vin ngi dng.Th vin IEEE gm nhiu gi th vin con khc nhau trong ng ch c cc th vin sau: - Gi IEEE.STD_LOGIC_1164 cung cp cc kiu d liu std_ulogic, std_logic, std_ulogic_vector, std_logic_vector, cc hm logic and, or, not, nor, xor cc hm chuyn i gia cc kiu d liu trn. std_logic, std_ulogic h tr kiu logic vi 9 mc gi tr logic (xem 4.2) - Gi IEEE.STD_LOGIC_ARITH nh ngha cc kiu d liu s nguyn SIGNED, UNSIGNED, INTEGER, SMALL INT cung cp cc hm s hc bao gm +, -, *, /, so snh <, >, <=, >=, cc hm dch tri, dch phi, cc hm chuyn i t kiu vector sang cc kiu s nguyn. - Gi IEEE.STD_LOGIC_UNSIGNED Cung cp cc hm s hc logic lm vic vi cc kiu d liu std_logic, integer v tr v gi tr dng std_logic vi gi tr khng c du - Gi IEEE.STD_LOGIC_SIGNED Cung cp cc hm s hc logic lm vic vi cc kiu d liu std_logic, integer v tr v gi tr dng std_logic vi gi tr c du - Gi IEEE.NUMERIC_BIT Cung cp cc hm s hc logic lm vic vi cc kiu d liu signed, unsigned c l chui ca cc BIT. - Gi IEEE.NUMERIC_BIT Cung cp cc hm s hc logic lm vic vi cc kiu d liu signed, unsigned c l chui ca cc STD_LOGIC. 44

Gi IEEE.STD_LOGIC_TEXTIO cha cc hm, th tc vo ra READ/WRITE c ghi d liu cho cc nh dng STD_LOGIC, STD_ULOGIC t FILE, STD_INPUT, STD_OUTPUT, LINE. - Gi STD.TEXTIO cha cc hm vo ra READ/WRITE c ghi d liu vi cc nh dng khc nhau gm, BIT, INTEGER, TIME, REAL, CHARATER, STRING t FILE, STD_INPUT, STD_OUTPUT, LINE. - Gi IEEE.MATH_REAL, IEEE.MATH_COMPLEX cung cp cc hm lm vic vi s thc v s phc nh SIN, COS, SQRT hm lm trn, CIEL, FLOOR, hm to s ngu nhin SRAND, UNIFORM v nhiu cc hm tnh ton s thc khc. - Gi STD.ENV cung cp cc hm, th tc h thng phc v m phng gm stop dng m phng, finish thot chng trnh, resolution_limit tr v bc thi gian m phng. C th v chi tit hn v cc th vin chun ca IEEE c th tham kho thm trong ti liu ca IEEE (VHDL Standard Language reference), v xem thm phn Ph lc 1 cui sch lit k v phn loi y cc hm ca cc th vin chun.
-

2.2. M t thc th Khai bo thc th (entity) l khai bo v mt cu trc cc cng vo ra (port), cc tham s tnh dng chung (generic) ca mt khi thit k VHDL.
entity identifier is generic (generic_variable_declarations); port (input_and_output_variable_declarations); end entity identifier ;

Trong
identifier l tn ca khi thit k.

khai bo generic l khai bo cc tham s tnh ca thc th, khai bo ny rt hay s dng cho nhng thit k c nhng tham s thay i nh rng knh, kch thc nh, tham s b m v d chng ta c th thit k b cng cho cc hng t c di bit thay i, s bit c th hin l hng s trong khai bo generic (xem v d di y) Khai bo cng vo ra: lit k tt c cc cng giao tip ca khi thit k, cc cng c th hiu l cc knh d liu ng ca thit k phn bit vi cc tham s tnh trong khai bo generic. kiu ca cc cng c th l: - in: cng vo, 45

out: cng ra, inout vo ra hai chiu. buffer: cng m c th s dng nh tn hiu bn trong v output. linkage: C th lm bt k cc cng no k trn. V d cho khai bo thc th nh sau:
entity adder is generic ( N : port ( A : B : cin : Sum : Cout : end entity adder ; natural := 32); in bit_vector(N-1 downto 0); in bit_vector(N-1 downto 0); in bit; out bit_vector(N-1 downto 0); out bit);

on m trn khai bo mt thc th cho khi cng hai s, trong khai bo trn N l tham s tnh generic ch di bit ca cc hng t, gi tr ngm nh N = 32, vic khai bo gi tr ngm nh l khng bt buc. Khi khi ny c s dng trong khi khc nh mt khi con khc th c th thay i gi tr ca N thu c thit k theo mong mun. V cc cng vo ra, khi cng hai s nguyn c 3 cng vo A, B N-bit l cc hng t v cng cin l bt nh t bn ngoi. Hai cng ra l Sum N-bit l tng v bt nh ra Cout. Khai bo thc th c th cha ch mnh khai bo cng nh sau:
entity full_adder is port ( X, Y, Cin : in bit; Cout, Sum : out bit ); end full_adder ;

Khai bo thc th khng cha c khai bo generic ln khai bo port vn c xem l hp l, v d nhng khai bo thc th s dng m phng kim tra thit k thng c khai bo nh sau:
entity TestBench is end TestBench;

V d v cng dng buffer v inout: Cng buffer c dng khi tn hiu c s dng nh u ra ng thi nh mt tn hiu bn trong ca kh thit k, in hnh nh trong cc mch dy lm vic ng b. Xt v d sau v b cng tch ly 4-bit n gin sau (accumulator):
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.STD_LOGIC_arith.ALL;

46

----------------------------------------entity accumulator is port( data : in std_logic_vector(3 downto 0); nRST : in std_logic; CLK : in std_logic; acc : buffer std_logic_vector(3 downto 0) ); end accumulator; ----------------------------------------architecture behavioral of accumulator is begin ac : process (CLK) begin if CLK = '1' and CLK'event then if nRST = '1' then acc <= "0000"; else acc <= acc + data; end if; end if; end process ac; end behavioral; -----------------------------------------

B cng tch ly sau mi xung nhp CLK s cng gi tr hin c lu trong acc vi gi tr u vo data, tn hiu nRST dng thit lp li gi tr bng 0 cho acc. Nh vy acc ng vai tr nh thanh ghi kt qu u ra cng nh gi tr trung gian c khai bo di dng buffer. Trn thc t thay v dng cng buffer thng s dng mt tn hiu trung gian, khi cng acc c th khai bo nh cng ra bnh thng, cch s dng nh vy s trnh c mt s li c th pht sinh khi tng hp thit k do khai bo buffer gy ra. V d sau y l m t VHDL ca mt khi m ba trng thi 8-bit, s dng khai bo cng INOUT. Cng ba trng thi c iu khin bi tn hiu OE, khi OE bng 0 gi tr ca cng l trng thi tr khng cao ZZZZZZZZ, khi OE bng 1 th cng kt ni u vo inp vi outp.
-----------------------------------------------------library ieee; use ieee.std_logic_1164.ALL; -----------------------------------------------------entity bidir is port( bidir : inout std_logic_vector (7 downto 0); oe, clk : in std_logic_LOGIC;

47

inp : in std_logic_vector (7 downto 0); outp : out std_logic_vector (7 downto 0) ); END bidir; ----------------------------------------------------architecture behav of bidir is signal a : std_logic_vector (7 downto 0); signal b : std_logic_vector (7 downto 0); begin process(clk) begin if clk = '1' and clk'event then a <= inp; outp <= b; end if; end process; process (oe, bidir) begin if( oe = '0') then bidir <= "ZZZZZZZZ"; b <= bidir; else bidir <= a; b <= bidir; end if; end process; end maxpld; --------------------------------------------------

* Trong thnh phn ca khai bo thc th ngoi khai bo cng v khai bo generic cn c th c hai thnh phn khc l khai bo kiu d liu, th vin ngi dng chung, chng trnh con... V phn pht biu chung ch cha cc pht biu ng thi. Cc thnh phn ny nu c s c tc dng i vi tt c cc kin trc ca thc th. Chi tit hn v cc thnh phn khai bo ny c th xem trong [5] IEEE VHDL Standard Language reference (2002 Edition). 2.3. M t kin trc M t kin trc (ARCHITECTURE) l phn m t chnh ca mt khi thit k VHDL, nu nh m t entity ch mang tnh cht khai bo v giao din ca thit k th m t kin trc cha ni dung v chc nng ca i tng thit k. Cu trc ca m t kin trc tng qut nh sau:
architecture identifier of entity_name is [ declarations] begin

48

[ statements ] end identifier ;

Trong - identifier l tn gi ca kin trc, thng thng phn bit cc kiu m t thng dng cc tn behavioral cho m t hnh vi, dataflow cho m t lung d liu, structure cho m t cu trc tuy vy c th s dng mt tn gi hp l bt k no khc. - [declarations] c th c hoc khng cha cc khai bo cho php nh sau: Khai bo v m t chng trnh con (subprogram) Khai bo kiu d liu con (subtype) Khai bo tn hiu (signal), hng s (constant), file Khai bo khi con (component) -[statements] pht biu trong khi {begin end process;} cha cc pht biu ng thi (concurrent statements) hoc cc khi process cha cc pht biu tun t (sequential statements). C ba dng m t cu trc c bn l m t hnh vi (behavioral), m t lung d liu (dataflow) v m t cu trc (structure). Trn thc t trong m t kin trc ca nhng khi phc tp th s dng kt hp c ba dng m t ny. tm hiu v ba dng m t kin trc ta s ly v d v khi full_adder c khai bo entity nh sau:
entity full_adder is port ( A : in B : in cin : in Sum : out Cout : out end entity full_adder; std_logic; std_logic; std_logic; std_logic; std_logic);

2.3.1. M t hnh vi i vi thc th full_adder nh trn kin trc hnh vi (behavioral) c vit nh sau
--------------------------------------------------architecture behavioral of full_adder is begin add: process (A,B,Cin) begin if (a ='0' and b='0' and Cin = '0') then S <= '0';

49

Cout <='0'; elsif (a ='1' and b='0' and Cin = '0') or (a ='0' and b='1' and Cin = '0') or (a ='0' and b='0' and Cin = '1') then S <= '1'; Cout <='0'; elsif (a ='1' and b='1' and Cin = '0') or (a ='1' and b='0' and Cin = '1') or (a ='0' and b='1' and Cin = '1') then S <= '0'; Cout <= '1'; elsif (a ='1' and b='1' and Cin = '1') then S <= '1'; Cout <= '1'; end if; end process add; end behavioral; ---------------------------------------------------

M t hnh vi gn ging nh m t bng li cch thc tnh ton kt qu u ra da vo cc gi tr u vo. Ton b m t hnh vi phi c t trong mt khi qu trnh {process (sensitive list) end process;} ngha ca khi ny l n to mt qu trnh theo di s thay i ca tt c cc tn hiu c trong danh sch tn hiu (sensitive list), khi c bt k mt s thay i gi tr no ca tn hiu trong danh sch th n s thc hin qu trnh tnh ton ra kt qu tng ng u ra. Chnh v vy trong rt hay s dng cc pht biu tun t nh if, case, hay cc vng lp loop. Vic m t bng hnh vi khng th hin r c cch thc cu to phn cng ca vi mch nh cc dng m t khc v ty theo nhng cch vit khc nhau th c th thu c nhng kt qu tng hp khc nhau. Trong cc mch dy ng b, khi lm vic ng b thng c m t bng hnh vi, v d nh trong on m sau m t thanh ghi sau:
process(clk) begin if clk'event and clk='1' then Data_reg <= Data_in; end if; end process;

2.3.2. M t lung d liu M t lung d liu (dataflow)l dng m t tng i ngn gn v rt hay c s dng khi m t cc khi mch t hp. Cc pht biu trong khi 50

begin end l cc pht biu ng thi (concurrent statements) ngha l khng ph thuc thi gian thc hin ca nhau, ni mt cch khc khng c th t u tin trong vic sp xp cc pht biu ny ng trc hay ng sau trong on m m t. V d cho khi full_adder th m t lung d liu nh sau:
architecture dataflow of full_adder is begin sum <= (a xor b) xor Cin; Cout <= (a and b) or (Cin and (a xor b)); end dataflow;

2.3.3. M t cu trc M t cu trc (structure) l m t s dng cc m t c sn di dng khi con (component). Dng m t ny cho kt qu st vi kt qu tng hp nht. Theo m t lung d liu nh trn ta thy dng hai cng XOR, mt cng OR v 2 cng AND thc hin thit k ging nh hnh di y:
A B Cout

Sum Cin

Hnh 2-2. S logic ca khi cng y (FULL_ADDER) Trc khi vit m t cho full_adder cn phi vit m t cho cc phn t cng AND, OR, XOR nh sau
------------ 2 input AND gate --------library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------entity AND2 is port( in1, in2 : in std_logic; out1 : out std_logic ); end AND2; --------------------------------------architecture model_conc of AND2 is begin out1 <= in1 and in2; end model_conc; --------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

51

------------ 2 input OR gate ---------entity OR2 is port ( in1, in2 : in std_logic; out1 : out std_logic ); end OR2; --------------------------------------architecture model_conc2 of AND2 is begin out1 <= in1 or in2; end model_conc2; ------------ 2 input XOR gate --------library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------entity XOR2 is port ( in1, in2 : in std_logic; out1 : out std_logic); end XOR2; --------------------------------------architecture model_conc2 of XOR2 is begin out1 <= in1 xor in2; end model_conc2;

Sau khi c cc cng trn c th thc hin vit m t cho full_adder nh sau
----------------------------------------architecture structure of full_adder is signal t1, t2, t3: std_logic; component AND2 port ( in1, in2 : in out1 : out ); end component; component OR2 port ( in1, in2 : in out1 : out end component; component XOR2 port ( in1, in2 : in

std_logic; std_logic

std_logic; std_logic);

std_logic;

52

out1 ); end component; begin u1 : XOR2 u2 : XOR2 u3 : AND2 u4 : AND2 u5 : OR2 port port port port port map map map map map

: out std_logic

(a, b, t1) (t1, Cin, Sum) (t1, Cin, t2) (a, b, t3) (t3, t2, Cout);

end structure; ------------------------------------

Nh vy m t cu trc tuy kh di nhng l m t c th v cu trc mch, u im ca phng php ny l khi tng hp trn th vin cng s cho ra kt qu ng vi tng thit k nht. Vi m t full_adder nh trn th gn chc chn trnh tng hp a ra s logic s dng 2 cng XOR, hai cng AND v 1 cng OR. Mt khc m t cu trc cho php gp nhiu m t con vo mt khi thit k ln m vn gi c cu trc m r rng v khoa hc. Nhc im l khng th hin r rng chc nng ca mch nh hai m t cc phn trn. v d trn c s dng khai bo ci t khi con, chi tit v khai bo ny xem trong mc 7.5. 2.4. Khai bo cu hnh Mt thc th c th c rt nhiu kin trc khc nhau. Bn cnh cu trc ca ngn ng VHDL cho php s dng cc khi thit k theo kiu lng ghp, v vy i vi mt thc th bt k cn c thm cc m t quy nh vic s dng cc kin trc khc nhau. Khai bo cu hnh (Configuration declaration) c s dng ch ra kin trc no s c s dng trong thit k. Cch th nht s dng khai bo cu hnh l s dng trc tip khai bo cu hnh bng cch to mt on m cu hnh c lp khng thuc mt thc th hay kin trc no theo cu trc:
configuration identifier of entity_name is [declarations] [block configuration] end configuration identifier;

V d sau to cu hnh c tn add32_test_config cho thc th add32_test, cu hnh ny quy nh cho kin trc c tn circuits ca thc th add32_test, khi ci t cc khi con c tn add32 s dng kin trc tng ng l WORK.add32(circuits), vi mi khi con add4c ca thc th add32 th s dng 53

kin trc WORK.add4c(circuit), tip l quy nh mi khi con c tn fadd trong thc th add4c s dng kin trc c tn WORK.fadd(circuits).
configuration add32_test_config of add32_test is for circuits -- of add32_test for all: add32 use entity WORK.add32(circuits); for circuits -- of add32 for all: add4c use entity WORK.add4c(circuits); for circuits -- of add4c for all: fadd use entity WORK.fadd(circuits); end for; end for; end for; end for; end for; end for; end configuration add32_test_config; Cp lnh c bn ca khai bo cu hnh l cp lnh for use end for c tc dng quy nh cch thc s dng cc kin trc khc nhau ng vi cc

khi khc nhau trong thit k. Bn thn configuration cng c th c s dng nh i tng ca lnh use, v d:
configuration adder_behav of adder4 is for structure for all: full_adder use entity work.full_adder (behavioral); end for; end for; end configuration;

Vi mt thc th c th khai bo nhiu cu hnh khc nhau ty theo mc ch s dng. Sau khi c khai bo nh trn v bin dch th s xut hin thm trong th vin cc cu hnh tng ng ca thc th. Cc cu hnh khc nhau xc nh cc kin trc khc nhau ca thc th v c th c m phng c lp. Ni mt cch khc cu hnh l mt i tng c cp c th cao hn so vi kin trc. Cch thc th hai quy nh vic s dng kin trc l dng trc tip cp lnh for use end for; nh minh ha di y, cch thc ny cho php khai bo cu hnh trc tip bn trong mt kin trc c th:
----------------------------------------library IEEE;

54

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder4 is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic ); end adder4; ----------------------------------------architecture structure of adder4 is signal C: std_logic_vector(2 downto 0); -- declaration of component full_adder component full_adder port( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic ); end component; for use for use for use for use u0: full_adder entity work.full_adder(behavioral); u1: full_adder entity work.full_adder(dataflow); u2: full_adder entity work.full_adder(structure); u3: full_adder entity work.full_adder(behavioral);

begin -- design of 4-bit adder u0: full_adder port map (A => A(0), B => B(0), Cin => CI, S =>Sum(0), Cout => C(0)); u1: full_adder port map (A => A(1), B => B(1), Cin => C(0), S =>Sum(1), Cout => C(1)); u2: full_adder port map (A => A(2), B => B(2),

55

Cin => C(1), S =>Sum(2), Cout => C(2)); u3: full_adder port map (A => A(3), B => B(3), Cin => C(2), S =>Sum(3), Cout => CO); end structure; -----------------------------------------

v d trn mt b cng 4 bit c xy dng t 4 khi full_adder nhng vi cc kin trc khc nhau. Khi u tin dng kin trc hnh vi (behavioral), khi th hai l kin trc kiu lung d liu (dataflow), khi th 3 l kin trc kiu cu trc (structure), v khi cui cng l kin trc kiu hnh vi.

3. Chng trnh con v gi

3.1. Th tc Chng trnh con (subprogram) l cc on m dng m t mt thut ton, php ton dng x l, bin i, hay tnh ton d liu. C hai dng chng trnh con l th tc (procedure) v hm (function). Th tc thng dng thc hin mt tc v nh bin i, x l hay kim tra d liu, hoc cc tc v h thng nh c ghi file, truy xut kt qu ra mn hnh, kt thc m phng, theo di gi tr tn hiu. Khai bo ca th tc nh sau:
procedure identifier [(formal parameter list)] is [declarations] begin sequential statement(s) end procedure identifier;

v d:
procedure print_header ; procedure build ( A : in constant integer; B : inout signal bit_vector; C : out variable real; D : file);

Trong formal parameter list cha danh sch cc bin, tn hiu, hng s, hay d liu kiu FILE, kiu ngm nh l bin. Cc i tng trong danh sch ny tr dng file c th c khai bo l dng vo (in), ra (out), hay hai chiu (inout), kiu ngm nh l in. Xt vi d y di y:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use STD.TEXTIO.all; -----------------------------------------

56

entity compare is port( res1, res2 : in bit_vector(3 downto 0) ); end compare; ----------------------------------------architecture behavioral of compare is procedure print_to_file( val1, val2 : in bit_vector(3 downto 0); FILE fout : text) is use STD.TEXTIO.all; variable str: line; begin WRITE (str, string'("val1 = ")); WRITE (str, val1); WRITE (str, string'(" val2 = ")); WRITE (str, val2); if val1 = val2 then WRITE (str, string'(" OK")); elsif WRITE (str, string'(" TEST FAILED")); end if; WRITELINE(fout, str); WRITELINE(output, str); end procedure print_to_file; FILE file_output : text open WRITE_MODE is "test_log.txt"; -- start here begin proc_compare: print_to_file(res1, res2, file_output); end behavioral; -------------------------------------------

Trong v d trn chng trnh con dng so snh v ghi kt qu so snh ca hai gi tr kt qu res1, res2 vo trong file vn bn c tn "test_log.txt". Phn khai bo ca hm c t trong phn khai bo ca kin trc nhng nu hm c gi trc tip trong kin trc nh trn th khai bo ny c th b i. Thn chng trnh con c vit trc tip trong phn khai bo ca kin trc v c gi trc tip cp begin end behavioral.

57

3.2. Hm Hm (function) thng dng tnh ton kt qu cho mt t hp u vo. Khai bo ca hm c c php nh sau:
function identifier [parameter list] return a_type;

v d
function random return float; function is_even ( A : integer) return boolean;

Danh sch bin ca hm cng c cch nhau bi du ; nhng im khc l trong danh sch ny khng c ch r dng vo/ra ca bin m ngm nh tt c l u vo. Kiu d liu u ra ca hm c quy nh sau t kha return. Cch thc s dng hm cng tng t nh trong cc ngn ng lp trnh bc cao khc. Xt mt v d y di y:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity function_example is end function_example; ----------------------------------------architecture behavioral of function_example is type bv4 is array (3 downto 0) of std_logic; function mask(mask, val1 : in bv4) return bv4; signal vector1 : bv4 := "0011"; signal mask1 : bv4 := "0111"; signal vector2 : bv4; function mask(mask, val1 : in bv4) return bv4 is variable temp : bv4; begin temp(0) := mask(0) and val1(0); temp(1) := mask(1) and val1(1); temp(2) := mask(2) or val1(2); temp(3) := mask(3) or val1(3); return temp; end function mask; -- start here begin masking: vector2 <= mask(vector1, mask1); end behavioral;

V d trn minh ha cho vic s dng hm thc hin php tnh mt n (mask) c bit trong hai bit thp ca gi tr u vo c thc hin php logic OR vi gi tr mask cn hai bit cao th thc hin mask bnh thng vi 58

php logic AND. Phn khai bo ca hm c t trong phn khai bo ca kin trc, nu hm c gi trc tip trong kin trc nh trn th khai bo ny c th b i. Phn thn ca hm c vit trong phn khai bo ca kin trc trc cp {begin end behavioral}. Khi gi hm trong phn thn ca kin trc th gi tr tr v ca hm phi c gn cho mt tn hiu, v d trn l vector2. 3.3. Gi Gi (package) l tp hp cc kiu d liu, hng s, bin, cc chng trnh con v hm dng chung trong thit k. Mt cch n gin gi l mt cp thp hn ca th vin, mt th vin cu thnh t nhiu gi khc nhau. Ngoi cc gi chun ca cc th vin chun nh trnh by 2.1, ngn ng VHDL cho php ngi dng to ra cc gi ring ty theo mc ch s dng. Mt gi bao gm khai bo gi v phn thn ca gi. Khai bo gi c cu trc nh sau:
package identifier is [ declarations] end package identifier ;

Phn khai bo ch cha cc khai bo v kiu d liu, bin dng chung, hng v khai bo ca hm hay th tc nu c. Phn thn gi c c php nh sau:
package body identifier is [ declarations] end package body identifier ;

Phn thn gi cha cc m t chi tit ca hm hay th tc. Ngoi ra gi cn c dng cha cc khai bo component dng chung cho cc thit k ln. V d cc phn t nh khi cng, thanh ghi, khi dch, thanh ghi dch, b m, khi chn knh l cc khi c bn cu thnh ca hu ht cc khi thit k phc tp, v vy s rt tin dng khi ng gi tt c cc thit k ny nh mt th vin dng chung ging nh cc gi chun v s dng trong cc thit k ln khc nhau vi iu kin cc khi ny c khai bo s dng gi trn. V d y mt gi c cha hai chng trnh con lit k 3.1 v 3.2 v cha cc khai bo thit k dng chung nh sau:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use STD.TEXTIO.all; ----------------------------------------package package_example is type bv4 is array (3 downto 0) of std_logic; function mask(mask, val1 : in bv4) return bv4;

59

procedure print_to_file(val1, val2 : in bit_vector(3 downto 0); FILE fout :text); end package package_example; ----------------------------------------package body package_example is function mask(mask, val1 : in bv4) return bv4; signal vector1 : bv4 := "0011"; signal mask1 : bv4 := "0111"; signal vector2 : bv4; component adder_sub is generic (N: natural := 32); port( SUB : in std_logic; Cin : in std_logic; A : in std_logic_vector(N-1 downto 0); B : in std_logic_vector(N-1 downto 0); SUM : out std_logic_vector(N-1 downto 0) ; Cout : out std_logic ); end component; component counter is generic (N: natural := 3); PORT( clk : in std_logic; reset : in std_logic; counter_enable : in std_logic; end_num : in std_logic_vector (N-1 downto 0); cnt_end : out std_logic ); end component; component reg is generic (N: natural := 32); port( D : in std_logic_vector(N-1 downto 0); Q : out std_logic_vector(N-1 downto 0); CLK : in std_logic; RESET : in std_logic ); end component; component mux is generic (N: natural := 32); port( Sel : in std_logic; Din1 : in std_logic_vector(N-1 downto 0);

60

Din2 : in std_logic_vector(N-1 downto 0); Dout : out std_logic_vector(N-1 downto 0) ); end component; function mask(mask, val1 : in bv4) return bv4 is variable temp : bv4; begin temp(0) := mask(0) and val1(0); temp(1) := mask(1) and val1(1); temp(2) := mask(2) or val1(2); temp(3) := mask(3) or val1(3); return temp; end function mask; --------------------------------------------procedure print_to_file( val1, val2 : in bit_vector(3 downto 0); FILE fout : text) is use STD.TEXTIO.all; variable str: line; begin WRITE (str, string'("val1 = ")); WRITE (str, val1); WRITE (str, string'(" val2 = ")); WRITE (str, val2); if val1 = val2 then WRITE (str, string'(" OK")); elif WRITE (str, string'(" TEST FAILED")); end if; WRITELINE(fout, str); WRITELINE(output, str); end procedure print_to_file; end package body package_example; --------------------------------------------

s dng gi ny trong cc thit k th phi khai bo th vin v gi s dng tng t nh trong cc gi chun phn khai bo th vin. V theo ngm nh cc gi ny c bin dch vo th vin c tn l work nn khai bo nh sau:
-------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use STD.TEXTIO.all; library work;

61

use work.package_example.all; -------------------------------------------entity pck_example is port( res1, res2 : in bit_vector(3 downto 0) ); end pck_example; -------------------------------------------architecture behavioral of pck_example is signal vector2 : bv4; signal vector1 : bv4 := "0011"; signal mask1 : bv4 := "0111"; FILE file_output : text open WRITE_MODE is "test_log.txt"; begin proc_compare: print_to_file(res1, res2, file_output); masking : vector2 <= mask(vector1, mask1); end behavioral; --------------------------------------------

4. i tng d liu, kiu d liu

4.1. i tng d liu Trong VHDL c phn bit 3 loai i tng d liu l bin, hng v tn hiu. Cc i tng c khai bo theo c php
Object_type identifier : type [:= initial value];

Trong object_type c th l Variable, Constant hay Signal. 4.1.1. Hng Hng (Constant) l nhng i tng d liu dng khi to cha cc gi tr xc nh trong qu trnh thc hin. Hng c th c khai bo trong cc gi, thc th, kin trc, chng trnh con, cc khi v qu trnh. C php
constant identifier : type [range value] := value;

V d;
constant PI : REAL := 3.141569; constant vector_1 : std_logic_vector(8 downto 0):= 11111111;

62

4.1.2. Bin Bin (Variable) l nhng i tng d liu dng cha cc kt qu trung gian, bin ch c th c khai bo bn trong cc qu trnh hoc chng trnh con. Khai bo bin bao gi cng i km vi kiu, c th c xc nh gii hn gi tr v c gi tr khi to ban u, nu khng c gi tr khi to ban u th bin s nhn gi tr khi to l gi tr nh nht trong min gi tr. C php
variable identifier : value]; type [range value] [:= initial

V d
variable count : variable vector_bit : integer range 0 to 15 := 0; std_logic_vector(8 downto 0);

4.1.3. Tn hiu Tn hiu (Signal) l cc i tng d liu dng kt ni gia cc khi logic hoc ng b cc qu trnh. Tn hiu c th c khai bo trong phn khai bo gi, khi ta s c tn hiu l ton cc, khai bo trong thc th khi tn hiu l tn hiu ton cc ca thc th, trong khai bo kin trc, v khai bo trong cc khi. Cc tn hiu tuyt i khng c khai bo trong cc qu trnh v cc chng trnh con m ch c s dng trong chng, c im ny th hin s khc bit r nht gia bin v tn hiu. C php
signal identifier : type [range value] [:= initial value];

V d:
signal a : signal vector_b : std_logic := 0; std_logic_vector(31 downto 0);

4.2. Kiu d liu 4.2.1. Cc kiu d liu tin nh ngha Trong cc kiu d liu ca VHDL c chia ra d liu tin nh ngha v d liu ngi dng nh ngha. D liu tin nh ngha l d liu c nh ngha trong cc b th vin chun ca VHDL, d liu ngi dng nh ngha l cc d liu c nh ngha li da trn c s d liu tin nh ngha, ph hp cho tng trng hp s dng khc nhau. Cc d liu tin nh ngha c m t trong cc th vin STD, v IEEE, c th nh sau: 63

- BIT, v BIT_VECTOR, c m t trong th vin STD.STANDARD, BIT ch nhn cc gi tr 0, v 1. Ngm nh nu nh cc bin dng BIT khng c khi to gi tr ban u th s nhn gi tr 0. V BIT ch nhn cc gi tr tng minh nn khng ph hp khi s dng m t thc th phn cng tht, thay v thng s dng cc kiu d liu STD_LOGIC v STD_ULOGIC. Tuy vy trong mt s trng hp v d cc lnh ca php dch, hay lnh WRITE ch h tr cho BIT v BIT_VECTOR m khng h tr STD_LOGIC v STD_LOGIC_VECTOR. - STD_ULOGIC v STD_ULOGIC_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR c m t trong th vin IEEE.STD_LOGIC_1164, STD_ULOGIC, v STD_LOGIC c th nhn mt trong 9 gi tr lit k bng sau: Bng 2-1 Gi tr ca kiu d liu STD_LOGIC/STD_ULOGIC U Khng xc nh (Unresolved) 'X' X Bt buc '0' 0 Bt buc '1' 1 Bt buc 'Z' Tr khng cao 'W' X Y u 'L' 0 Y u 'H' 1 Y u '-' Khng quan tm Tn y ca STD_ULOGIC l Standard Unresolved Logic, hay kiu logic chun cha quy nh v cch kt hp cc gi tr logic vi nhau,do vy i vi kiu STD_ULOGIC th khi thit k khng cho php mt tn hiu c nhiu ngun cp. Kiu STD_LOGIC l kiu d liu cng c th nhn mt trong 9 gi tr logic nh trn nhng c quy nh cch thc cc gi tr kt hp vi nhau bng hm resolved. Nu quan st trong file stdlogic.vhd ta s gp on m m t hm ny, hai tn hiu gi tr kiu STD_LOGIC khi kt hp vi nhau s thu c 1 tn hiu gi tr logic theo quy tc trong bng rosolved table di y.
SUBTYPE std_logic IS resolved std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -------------------------------------------

64

------------------------------------------------CONSTANT resolution_table : stdlogic_table := ( ----------------------------------------------------- | U X 0 1 Z W L H ---------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) | - | ); FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved;

V d on m sau y s gy ra li bin dch:

----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; ----------------------------------------entity logic_expample is port( A : in std_ulogic_vector(8 downto 0); U : out std_ulogic_vector(8 downto 0) ); end logic_expample; ----------------------------------------architecture dataflow of logic_expample is begin U <= A; U <= "X01ZWLH-1";

65

end dataflow;

Li bin dch s bo rng tn hiu U c hai ngun u vo.

# ** Error: logic_example.vhd(19): Nonresolved signal 'u' has multiple sources.

Nh i vi on m trn nu khai bo U l tn hiu dng STD_LOGIC th vn bin dch c bnh thng. Trn thc t ty vo i tng c th m dng cc kiu tng ng nhng m bo trnh vic ghp nhiu u vo chung (vic ny bt buc trnh khi thit k mch tht), th nn s dng STD_ULOGIC. Cc d liu tin nh ngha khc c trong ngn ng VHDL lit k di y: - BOOLEAN: c cc gi tr TRUE, FALSE (ng/sai). -INTEGER: s nguyn 32 bits ( t -2.147.483.647 n +2.147.483.647) - NATURAL: s nguyn khng m ( t 0 n +2.147.483.647) - REAL: s thc nm trong khong ( t -1.0E38 n +1.0E38). -TIME: s dng i vi cc i lng vt l, nh thi gian,in p,Hu ch trong m phng - CHARACTER: k t ASCII. -FILE_OPEN_KIND: kiu m file gm cc gi tr MODE, WRITE_MODE,
APPEND_MODE.

-FILE_OPEN_STATUS: Trng thi m file vi cc gi tr

STATUS_ERROR, NAME_ERROR, MODE_ERROR.

OPEN_OK,

-SEVERITY_LEVEL: trng thi li

ERROR, FAILURE.

vi cc gi tr

NOTE, WARNING,

4.2.2. Cc kiu d liu v hng D liu v hng trong VHDL (Scalar types) bao gm kiu lit k (enumeration), kiu nguyn (integer), kiu s thc du phy ng (real), kiu d liu vt l (physical type). Cc kiu d liu di y c xt nh cc i tng d liu ngi dng nh ngha t cc i tng d liu tin nh ngha trn. Kiu lit k Kiu lit k (Enumeration) c nh ngha bng cch lit k tt c cc gi tr c th c ca kiu, khai bo nh sau
type enum_name is (enum_literals list);

V d:
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING,AMBIGUOUS);

66

type BIT is ('0','1'); type SWITCH_LEVEL is ('0','1','X');

Cc kiu lit k nh sn trong VHDL l: -kiu k t (CHARACTER). -kiu (BIT) gm hai gi tr 0, 1. -kiu logic (BOOLEAN) gm cc gi tr TRUE, FALSE. -kiu SEVERITY kiu cnh bo li gm cc gi tr NOTE, WARNING, ERROR, FAILURE. -kiu dng v trng thi File (FILE_OPEN_KIND vi cc gi tr READ_MODE, WRITE_MODE, APPEND_MODE, kiu FILE_OPEN_STATUS vi cc gi tr OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR). Kiu s nguyn Kiu s nguyn (integer) c nh ngha sn trong VHDL l INTEGER c gii hn t 2147483647 n +2147483647. Cc php ton thc hin trn kiu nguyn l +, -, *, /. Cc kiu nguyn th sinh c khai bo theo c php sau:
type identifier is range interger_range;

Trong interger_range l mt min con ca tp s nguyn, cc gi tr gii hn ca min con phi vit di dng s nguyn v c th nhn gi tr m hoc dng, v d:
type word_index is range 30 downto 0; type TWOS_COMPLEMENT_INTEGER is range 32768 to 32767;

Kiu s thc Kiu s thc (Real) c nh ngha sn trong VHDL l Real c gii hn t 1.0E38 ti +1.0E38. Cc kiu thc th sinh c khai bo theo c php sau:
type identifier is range real_range;

Trong real_range l min con ca min s thc cc gi tr gii hn ca min ny c th l cc gi tr dng hoc m c vit bng mt trong nhng dng cho php ca s thc nh dng du phy ng hay dng thp phn v khng nht thit phi ging nhau, v d:
type my_float1 is range 1.0 to 1.0E6; type my_float2 is range -1.0e5 to 1.0E6;

Kiu gi tr i lng vt l Kiu gi tr i lng vt l (physical) c dng nh ngha cc n v vt l nh thi gian, khong cch, din tch, Ch c mt kiu gi tr i lng vt l c nh ngha sn trong VHDL l kiu TIME 67

type Time is range --implementation defined-- ; units fs; -- femtosecond ps = 1000 fs; -- picosecond ns = 1000 ps; -- nanosecond us = 1000 ns; -- microsecond ms = 1000 us; -- millisecond sec = 1000 ms; -- second min = 60 sec; -- minute hr = 60 min; -- hour end units;

Cc kiu gi tr i lng vt l c khai bo vi c php tng t nh trn, sau t kha units l n v chun v cc n v th sinh bng mt s nguyn ln cc n v chun, danh sch cc n v c kt thc bi t kha end units, v d:
type distance is range 0 to 1E16 units Ang; -- angstrom nm = 10 Ang; -- nanometer um = 1000 nm; -- micrometer (micron) mm = 1000 um; -- millimeter cm = 10 mm; -- centimeter dm = 100 mm; -- decameter m = 1000 mm; -- meter km = 1000 m; -- kilometer mil = 254000 Ang; -- mil (1/1000 inch) inch = 1000 mil; -- inch ft = 12 inch; -- foot yd = 3 ft; -- yard fthn = 6 ft; -- fathom frlg = 660 ft; -- furlong mi = 5280 ft; -- mile lg = 3 mi; -- league end units;

4.2.2. D liu phc hp D liu phc hp (composite) l d liu to thnh bng cc t hp cc dng d liu c bn trn theo cc cch khc nhau. C hai dng d liu phc hp c bn l kiu mng d liu khi cc phn t d liu trong t hp l ng nht v c sp th t, dng th hai l dng bn ghi khi cc phn t c th c cc kiu d liu khc nhau. Kiu mng Kiu mng (Array) trong VHDL c cc tnh cht nh sau: 68

Cc phn t ca mng c th l mi kiu trong ngn ng VHDL. S lng cc ch s ca mng (hay s chiu ca mng) c th nhn mi gi tr nguyn dng. - Mng ch c mt v mt ch s dng truy cp ti phn t. - Min bin thin ca ch s xc nh s phn t ca mng v hng sp xp ch s trong ca mng t cao n thp hoc ngc li. - Kiu ca ch s l kiu s nguyn hoc lit k. Mng trong VHDL chia lm hai loi l mng rng buc v mng khng rng buc. Mng rng buc l mng c khai bo tng minh c kch thc c nh. C php khai bo ca mng ny nh sau:
type array_name is array (index_range) of type;

Trong array_name l tn ca mng, index_range l min bin thin xc nh ca ch s nu mng l mng nhiu chiu th cc chiu bin thin cch nhau du ,, v d nh sau:
type mem is array (0 to 31, 3 to 0) of std_logic; type word is array (0 to 31) of bit; type data is array (7 downto 0) of word;

i vi mng khai bo khng tng minh th min gi tr ca ch s khng c ch ra m ch ra kiu ca ch s:

type array_name is array (type of index range <>) of type;

V d:
type mem is array (natural range <>) of word; type matrix is array (integer range <>, integer range <>) of real;

Cch truy cp ti cc phn t ca mng ca mt mng n chiu nh sau:

array_name (index1, index 2,, indexn)

v d:
matrix(1,2), mem (3).

Kiu bn ghi Bn ghi (Record) l nhm ca mt hoc nhiu phn t thuc nhng kiu khc nhau v c truy cp ti nh mt i tng. Bn ghi c nhng c im nh sau: - Mi phn t ca bn ghi c truy cp ti theo trng. - Cc phn t ca bn ghi c th nhn mi kiu ca ngn ng VHDL k c mng v bn ghi. v d v bn ghi
type stuff is record I : integer;

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X Day name prob end record;

: : : :

real; integer range 1 to 31; string(1 to 48); matrix(1 to 3, 1 to 3);

Cc phn t ca bn ghi c truy cp theo tn ca bn ghi v tn trng ngn cch nhau bng du ., v d:
node.data; stuff.day

5. Ton t v biu thc

Trong VHDL c tt c 7 nhm ton t c phn chia theo mc u tin v trt t tnh ton. Trong bng sau lit k cc nhm ton t theo trt t u tin tng dn: Bng 2-2 Cc ton t trong VHDL Ton t logic and, or, nand, nor, xor Cc php ton quan h =, /=, <, <=, >, >= Cc php ton dch sll, srl, sla, sra, rol, ror Cc php ton cng, hp +, -, & Ton t du +, Cc php ton nhn *, /, mod, rem Cc php ton khc **, abs, not Cc quy nh v trt t cc php ton trong biu thc c thc hin nh sau: - Trong cc biu thc php ton c mc u tin ln hn s c thc hin trc. Cc du ngoc n (, ) phn nh min u tin ca tng nhm biu thc. - Cc php ton trong nhm vi cng mt mc u tin s c thc hin ln lt t tri qua phi. 5.1. Ton t logic Cc php ton logic gm and, or, nand, nor, xor, v not. Cc php ton ny tc ng ln cc i tng kiu BIT v Boolean v mng mt chiu kiu BIT. i vi cc php ton hai ngi th cc ton hng nht nh phi cng kiu, nu hng t l mng BIT mt chiu th phi c cng di, khi cc php ton logic s thc hin i vi cc bit tng ng ca hai ton hng c cng ch s.

70

Php ton not ch c mt ton hng, khi thc hin vi mng BIT mt chiu th s cho kt qu l mng BIT ly o tt c cc v tr ca mng c. V d:
------------------------------------------library ieee; use ieee.std_logic_1164.all; ------------------------------------------entity logic_example is port( in1 : in std_logic_vector (5 downto 0); in2 : in std_logic_vector (5 downto 0); out1 : out std_logic_vector (5 downto 0) ); end entity; ------------------------------------------architecture rtl of logic_example is begin out1(0) <= in1(0) and in2 (0); out1(1) <= in1(1) or in2 (1); out1(2) <= in1(2) xor in2 (2); out1(3) <= in1(3) nor in2 (3); out1(4) <= in1(4) nand in2 (4); out1(5) <= in1(5) and (not in2 (5)); end rtl; --------------------------------------------

5.2. Cc php ton quan h Cc php ton quan h gm =, /=, <, <=, >, >= thc hin cc php ton so snh gia cc ton t c cng kiu nh Integer, real, character. V cho kt qu dng Boolean. Vic so snh cc hng t trn c s min gi tr ca cc i tng d liu. Cc php ton quan h rt hay c s dng trong cc cu lnh r nhnh V d y v php ton so snh th hin on m sau:
--------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --------------------------------------------entity compare_example is port( val1 : in std_logic_vector (7 downto 0); val2 : in std_logic_vector (7 downto 0); res : out std_logic_vector (2 downto 0) ); end entity;

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--------------------------------------------architecture rtl of compare_example is begin compare: process (val1, val2) begin if val1 > val2 then res(0) <= '1'; else res (0) <= '0'; end if; if val1 = val2 then res(1) <= '1'; else res (1) <= '0'; end if; if val1 < val2 then res(2) <= '1'; else res (2) <= '0'; end if; end process compare; end rtl;

5.3. Cc php ton dch Cc php ton quan h gm sll, srl, sla, sra, rol, ror c h tr trong th vin ieee.numeric_bit, v ieee.numeric_std. C php ca cc lnh dch c hai tham s l sho (shift operand) v shv (shift value), v d c php ca sll nh sau
sha sll shv;

Bng 2-3 Cc php ton dch trong VHDL Ton Php ton Kiu ca sho Kiu ca Kiu k t t shv qu sll Dch tri logic Mng 1 chiu kiu BIT Integer Cng kiu hoc BOOLEAN sho srl Dch phi logic Mng 1 chiu kiu BIT Integer Cng kiu hoc BOOLEAN sho sla Dch tri s hc Mng 1 chiu kiu BIT Integer Cng kiu hoc BOOLEAN sho sra Dch phi s hc Mng 1 chiu kiu BIT Integer Cng kiu hoc BOOLEAN sho rol Dch vng trn Mng 1 chiu kiu BIT Integer Cng kiu sang tri hoc BOOLEAN sho ror Dch vng trn Mng 1 chiu kiu BIT Integer Cng kiu phi hoc BOOLEAN sho i vi dch logic th ti cc v tr b trng s c in vo cc gi tr 0 cn dch s hc th cc cc v tr trng c thay th bng bit c trng s cao nht (MSB) nu dch phi, v thay bng bit c trng s thp nht (LSB) nu dch 72

tri. i vi dch vng th cc v tr khuyt i s c in bng cc bit dch ra ngoi gii hn ca mng. Quan st v d di y Gi s c gi tr sho = 11000110 , shv = 2, xt on m sau
---------------------------------------library ieee; USE ieee.Numeric_STD.all; USE ieee.Numeric_BIT.all; library STD; use STD.TEXTIO.ALL; ---------------------------------------entity shift_example is end entity; ----------------------------------------architecture rtl of shift_example is signal sho: bit_vector(7 downto 0) := "11000110"; begin shifting: process (sho) variable str:line; begin write(str, string'("sho sll 2 = ")); write(str, sho sll 2); writeline(OUTPUT, str); write(str, string'("sho srl 2 = ")); write(str, sho srl 2); writeline(OUTPUT, str); write(str, string'("sho sla 2 = ")); write(str, sho sla 2); writeline(OUTPUT, str); write(str, string'("sho sra 2 = ")); write(str, sho sra 2); writeline(OUTPUT, str); write(str, string'("sho rol 2 = ")); write(str, sho rol 2); writeline(OUTPUT, str); write(str, string'("sho ror 2 = ")); write(str, sho ror 2); writeline(OUTPUT, str); end process shifting; end architecture; ----------------------------------------------

Vi on m trn khi m phng s thu c kt qu:

# # # # sho sho sho sho sll srl sla sra 2 2 2 2 = = = = 00011000 00110001 00011000 11110001

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# sho rol 2 = 00011011 # sho ror 2 = 10110001

5.4. Cc php ton cng tr v hp Cc php ton +, - l cc php tnh hai ngi, cc php ton cng v tr c c php thng thng, hng t ca php ton ny l tt c cc kiu d liu kiu s gm INTEGER, REAL. Bng 2-4 Cc php ton cng dich v hp Ton Php ton Kiu ton t tri Kiu ca ton t Kiu kt qu t phi + Php cng D liu kiu s Cng kiu Cng kiu Php tr D liu kiu s Cng kiu Cng kiu & Php hp Kiu mng hoc phn Kiu mng hoc Kiu mng t mng phn t mng Php ton hp (concatennation) & c i s c th l mng hoc phn t mng v kt qu hp to ra mt mng mi c cc phn t ghp bi cc phn t ca cc ton t hp, cc v d di y s minh ha r thm cho php hp
----------------------------------------library ieee; use ieee.std_logic_1164.all; ----------------------------------------entity dublicate is port( in1 : in std_logic_vector(3 downto 0); out1 : out std_logic_vector(7 downto 0) ); end entity; ----------------------------------------architecture rtl of dublicate is begin out1 <= in1 & in1; end rtl; -----------------------------------------

Trong v d trn nu gn gi tr in1 = 1100 thu c tng ng u ra out1 = 11001100. 5.5. Cc php du Cc php ton quan h gm +, -, thc hin vi cc gi tr dng s v tr v gi tr dng s tng ng. 74

5.6. Cc php ton nhn chia, ly d Cc php ton *, /, mod, rem l cc php ton hai ngi tc ng ln cc ton t kiu s theo nh bng sau: Bng 2-5 Cc php ton nhn chia v ly d s nguyn Ton Php ton Ton t tri Ton t phi Kiu kt qu t * Php nhn S nguyn Integer Cng kiu Cng kiu S thc du phy Cng kiu Cng kiu ng REAL / Php chia S nguyn Integer Cng kiu Cng kiu S thc du phy Cng kiu Cng kiu ng REAL Mod Ly module S nguyn Integer S nguyn S nguyn Integer Integer Rem Ly phn d S nguyn Integer S nguyn S nguyn (remainder) Integer Integer C th kim tra cc php ton s hc bng on m sau:
---------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --------------------------------------entity mul_div_example is port( m1, m2 : in integer; res1, res2, res3, res4 : out integer ); end entity; ---------------------------------------architecture rtl of mul_div_example is begin res1 <= m1 * m2; res2 <= m1 / m2; res3 <= m1 mod m2; res4 <= m1 rem m2; end rtl; ---------------------------------------

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5.7. Cc php ton khc Cc php ton **, abs l cc php ton ly m e v ly gi tr tuyt i mt ngi tc ng ln cc ton t kiu s theo nh bng sau: Bng 2-6 Cc php ton khc Ton Php ton Ton t Kiu kt qu t ** Ly m e S nguyn Integer Cng kiu a ** a = e S thc du phy ng REAL Cng kiu abs Ly tr tuyt i S nguyn Integer Cng kiu S thc du phy ng REAL Cng kiu

6. Pht biu tun t

Trong ngn ng VHDL pht biu tun t (sequential statement) c s dng din t thut ton thc hin trong mt chng trnh con (subprogram) tc l dng function hoc procedure hay trong mt qu trnh (process). Cc lnh tun t s c thc thi mt cch ln lt theo th t xut hin ca chng trong chng trnh. Cc dng pht biu tun t bao gm: pht biu i (wait statement), xc nhn (assert statement), bo co (report statement), gn tn hiu (signal assignment statement), gn bin (variable assignment statement), gi th tc (procedure call statement), cc lnh r nhnh v vng lp, lnh iu khin if, loop, case, exit, return, next statements), lnh trng (null statement). 6.1. Pht biu i Pht biu i (wait) c cu trc nh sau
wait [sensitivity clause] [condition clause] [time clause];

Trong :
sensitivity clause = on sensitivity list, danh sch cc

tn hiu cn theo di, nu cu lnh wait dng cu trc ny th n c ngha bt qu trnh i cho ti khi c bt k s thay i no ca cc tn hiu trong danh sch theo di. Cu trc ny tng ng vi cu trc process dng cho cc pht biu ng thi s tm hiu 7.2.

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Condition clause = until condition: trong condition

l iu kin dng Boolean. Cu trc ny bt qu trnh dng cho ti khi iu kin trong condition c tha mn. - Time clause = for time_expression; c ngha bt qu trnh dng trong mt khong thi gian xc nh ch ra trong tham s lnh. V d v cc kiu gi lnh wait:
wait delay wait wait wait on any for 10 ns; -- timeout clause, specific time until clk='1'; -- Boolean condition until S1 or S2; -- Boolean condition on sig1, sig2;-- sensitivity clause, any event

Cu lnh wait nu s dng trong process th process khng c c danh sch tn hiu theo di (sensitive list), lnh wait on tng ng vi cch s dng process c danh sch tn hiu theo di. Xem xt v d y di y.
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity AND3 is port ( A : in std_logic; B : in std_logic; C : in std_logic; S : out std_logic ); end AND3; ----------------------------------------architecture wait_on of AND3 is begin andd: process begin S <= A and B and C; wait on A, B, C; end process andd; end wait_on; ----------------------------------------architecture use_process of AND3 is begin andd: process (A, B, C) begin S <= A and B and C; end process andd;

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end use_process; -----------------------------------------

Khi m t trn thc hin mt hm AND 3 u vo, vi kin trc wait_on s dng cu trc cu lnh wait on km theo danh sch tn hiu theo di A, B, C. Cch s dng tng ng vi cch vit trong kin trc use_process khi khng dng wait_on m s dng danh sch tn hiu theo di ngay sau t kha process. Vi lnh wait for xem xt v d y di y:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------entity wait_for is port( A : out std_logic; B : out std_logic ); end wait_for; -------------------------------------------architecture behavioral of wait_for is begin waiting: process begin A <= 'Z'; B <= 'X'; wait for 100 ns; A <= '1'; B <= 'Z'; wait for 200 ns; A <= '0'; B <= '1'; wait for 300 ns; A <= '1'; B <= '0'; wait; end process waiting; end behavioral; ---------------------------------------------

Hnh 2-3. Kt qu m phng gn tn hiu v lnh Wait Trong v d ny cc tn hiu A, B, c gn cc gi tr thay i theo thi gian, khong thi gian c quy nh bng cc lnh wait for. v d trn ban 78

u A, B nhn cc gi tr l Z v X sau 100 ns A bng 1 cn B bng Z, sau tip 200 ns A nhn gi tr bng 0 v B bng 1. y ta cng gp cu trc lnh wait khng c tham s, lnh ny tng ng lnh i trong khong thi gian l v hn, cc tn hiu A, B khi c gi nguyn gi tr c gn cu lnh trc. Cu trc ny l cc cu trc ch dng cho m phng, c bit hay dng trong cc khi kim tra, phc v cho vic to cc xung u vo ca cc khi kim tra. V d sau y l v d v lnh wait until
------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ------------------------------------------entity wait_until is port (D : in std_logic; Q : out std_logic ); end wait_until; ------------------------------------------architecture behavioral of wait_until is signal clk : std_logic := '0'; begin create_clk: process begin wait for 100 ns; clk <= not clk after 100 ns; end process create_clk; latch: process begin wait until clk = '1'; Q <= D; end process latch; end behavioral; -----------------------------------------

V d ny m t phn t latch, gi tr u ra nhn gi tr u vo ti mi thi im m gi tr tn hiu ng b bng 1 trong xung nhp clk c to bng cu trc clk <= not clk after 100 ns; ngha l chu k tng ng bng 200 ns. 6.2. Pht biu xc nhn v bo co Pht biu xc nhn v bo co (assert and report statement) c cu trc nh sau 79

assert boolean_condition [report string][severity name];

Trong :
boolean_condition: iu kin dng Boolean. Cu trc ny

kim tra gi tr ca boolean_condition. report string: bo co li nu c s dng th phi i cng mt chui thng bo li severity name:thng bo mc li nu c s dng th phi i km vi cc gi tr nh sn bao gm NOTE, WARNING, ERROR, FAILURE Lnh report c th c s dng c lp vi assert khi n c cu trc
[severity name]; Cc v d v lnh assert v report: assert a =(b or c); assert j<i report "internal error, tell someone"; assert clk='1' report "clock not up" severity WARNING; report "finished pass1"; -- default severity name is NOTE report "inconsistent data." severity FAILURE; Kt hp gia lnh assert v cnh bo severity cp FAILURE c report string

th dng ngt qu trnh m phng, khi trong qu trnh m phng m lnh ny c thc thi th chng trnh s dng li. Cu trc ny v th c s dng trong qu trnh kim tra t ng cc thit k. (Xem thm mc 9.1.1) 6.3. Pht biu gn bin Trong ngn ng VHDL c php ca pht biu gn bin (variable assignment statement) tng t nh php gn gi tr ca bin nh trong cc ngn ng lp trnh khc, c php nh sau:
variable := expression;

Trong variable l cc i tng ch c php khai bo trong cc chng trnh con v cc qu trnh, cc bin ch c tc dng trong chng trnh con hay qu trnh khai bo n, expression c th l mt biu thc hoc mt hng s c kiu ging kiu ca variable. Qu trnh gn bin din ra tc th vi thi gian m phng bng 0 v bin ch c tc dng nhn cc gi tr trung gian. V d v gn bin.
A := -B + C * D / E mod F rem G abs H; Sig := Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg; V d sau y minh ha cho pht biu gn bin v pht biu assert.

Trong v d ny mt b m c khai bo di dng bin, ti cc thi im 80

sn ln ca xung nhp ng h gi tr counter c tng thm 1 n v. Lnh assert s kim sot v thng bo khi no gi tr counter vt qu 100 v thng bo ra mn hnh.
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity assert_example is end assert_example; ----------------------------------------architecture behavioral of assert_example is signal clk: std_logic := '0'; begin create_clk: process begin wait for 100 ns; clk <= not clk after 100 ns; end process create_clk; count: process (clk) variable counter : integer := 0; begin if clk'event and clk = '1' then counter := counter + 1; end if; assert counter <100 report "end of counter" severity NOTE; end process count; end behavioral; ----------------------------------------------

Khi m phng ta thu c thng bo sau mn hnh khi counter vt qu gi tr 100.

# ** Note: end of counter # Time: 20 us Iteration: 0 /assert_example Instance:

6.4. Pht biu gn tn hiu Pht biu gn tn hiu (signal assignment statement) c cu trc nh sau
target <= [ delay_mechanism ] waveform;

Trong :
target: i tng cn gn tn hiu. - Delay mechanism: c ch lm tr tn hiu c cu trc nh sau: transport [ reject time_expression ] inertial

81

Trong nu c t kha transport th tn hiu c lm tr theo kiu ng truyn l dng lm tr m khng ph thuc vo dng tn hiu u vo, xung u vo d c rng xung nh th no vn c truyn ti y . Nu khng c c ch lm tr no c ch ra hoc s dng cu trc inertial th c ch lm tr l c ch qun tnh (inertial delay), theo c ch ny th s c mt gii hn rng xung u vo c ch ra gi l pulse reject limit c ch ra cng t kha reject, nu tn hiu vo c rng xung b hn gii hn ny th khng cho phn t logic k tip thc hin thao tc chuyn mch v gy ra li. Nu gii hn thi gian ch ra sau reject l gi tr m cng gy ra li.
waveform := wave_form elements := signal + {after time_expression}; - Ch ra tn hiu gn gi tr v thi gian p dng cho c ch lm tr

trnh by phn trn. V d v gn tn hiu tun t:

-- gn vi tr qun tnh, cc lnh sau tng ng O_pin <= i_pin after 10 ns; O_pin <= inertial i_pin after 10 ns; O_pin <= reject 10 ns inertial I_pin after 10 ns; -- gn vi kim sot rng xung u vo O_pin <= reject 5 ns inertial I_pin after 10 ns; O_pin <= reject 5 ns inertial I_pin after 10 ns, not I_pin after 20 ns; -- Gn vi tr transport O_pin <= transport I_pin after 10 ns; O_pin <= transport I_pin after 10 ns, not I_pin after 20 ns; -- tng ng cc lnh sau O_pin <= reject 0 ns inertial I_pin after 10 ns; O_pin <= reject 0 ns inertial I_pin after 10 ns, not I_pin after 10 ns;

Xt mt v d y v lnh ny nh sau nh sau:

----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity signal_assign is port ( S0 : out std_logic; S1 : out std_logic; S2 : out std_logic ); end signal_assign;

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------------------------------------------architecture behavioral of signal_assign is signal A: std_logic:= '0'; begin create_data: process begin wait for 100 ns; A <= '1'; wait for 100 ns; A <= not A after 30 ns; end process create_data; andd: process (A) begin S0 <= transport A after 200 ns; S1 <= reject 30 ns inertial A after 200 ns; S2 <= reject 100 ns inertial A after 200 ns; end process andd; end behavioral;

Sau khi m phng thu c kt qu trn waveform nh sau:

Hnh 2.4. Kt qu m phng v d gn tn hiu Tn hiu A l dng tn hiu xung nhp c chu k 60 ns, A thay i gi tr sau mi na chu k tc l sau mi 30 ns. Tn hiu S0 c gn bng A theo phng thc transport v vy trng lp hon ton vi A. Tn hiu S1 gn theo phng thc inertial vi thi gian reject bng 30 ns do vy vn thu c gi tr ging A. Tn hiu S2 cng c gn bng phng thc inertial nh vi reject time bng 100 ns > 30 ns nn c gi tr khng thay i. 6.5. Lnh r nhnh v lnh lp Lnh r nhnh l lnh lp l cc pht biu iu khin qu trnh trong cc chng trnh con hoc trong cc qu trnh. Cc pht biu ny c c php ging nh cc pht biu tng t trong cc ngn ng lp trnh khc. 6.5.1. Lnh r nhnh if
if condition1 then sequence-of-statements elsif condition2 then [sequence-of-statements ]

83

elsif condition3 then [sequence-of-statements ] .. else [sequence-of-statements end if;

Trong :
condition : cc iu kin dng boolean. [sequence-of-statements] : khi lnh thc thi nu iu kin

c tha mn. V d sau minh ha cch s dng lnh if m t D-flipflop bng VHDL, iu kin sn dng ca tn hiu xung nhp c kim tra bng cu trc clk = '1' and clk'event trong clkevent th hin c s kin thay i gi tr trn clk v iu kin clk = 1 xc nh s thay i l sn dng ca tn hiu.
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity D_flipflop is port( D : in std_logic; CLK : in std_logic; Q : out std_logic ); end D_flipflop; ----------------------------------------architecture behavioral of D_flipflop is begin DFF: process (clk, D) begin if clk = '1' and clk'event then Q <= D; end if; end process DFF; end behavioral; -----------------------------------------

6.5.2. Lnh chn case Lnh la chn (case) c c php nh sau:

case expression is when choice1 => [sequence-of-statements]

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when choice2 => [sequence-of-statements] ... when others => -- optional if all choices covered [sequence-of-statements] end case; Lnh case bt u bng t kha case theo sau l mt biu thc

(expression). Cc trng hp c chn bt u bng t kha when gi tr c th ca expresstion v m thc thi tng ng bt u sau du =>. When others s qut ht tt c cc gi tr c th c ca expression m cha c lit k ra trn (tng ng vi t kha default trong ngn ng lp trnh C). V d v lnh case:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity mux2 is port( A : in std_logic; B : in std_logic; Sel : in std_logic; S : out std_logic ); end mux2; ----------------------------------------architecture behavioral of mux2 is begin mux: process (A, B, sel) begin CASE sel IS WHEN '0' => S <= A; WHEN others => S <= B; end case; end process mux; end behavioral; -----------------------------------------

6.5.3. Lnh lp C ba dng lnh lp dng trong VHDL l lnh loop, lnh while, v lnh for:
loop sequence-of-statements -- use to get out

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end loop; for variable in range loop sequence-of-statements end loop; while condition loop sequence-of-statements end loop; i vi lnh lp dng loop th vng lp ch kt thc nu n gp lnh exit trong . i vi lnh lp dng for th vng lp kt thc khi qut ht

tt c cc gi tr ca bin chy. Vi vng lp dng while th vng lp kt thc khi iu kin trong condition l FALSE. V d y v ba dng lnh lp:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity loop_example is port( vector_in : in std_logic_vector(7 downto 0); out1 : out std_logic ); end loop_example; -----------------------------------------architecture loop1 of loop_example is begin loop_p: process (vector_in) variable I : integer; variable p : std_logic :='1'; begin for i in 7 downto 0 loop p := p and vector_in(i); end loop; out1 <= p; end process loop_p; end loop1; ------------------------------------------architecture loop2 of loop_example is begin loop_p: process (vector_in) variable i: integer := 7; variable p: std_logic :='1'; begin while i > 0 loop p := p and vector_in(i); i := i-1;

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end loop; i := 7; out1 <= p; end process loop_p; end loop2; ------------------------------------------architecture loop3 of loop_example is begin loop_p: process (vector_in) variable i: integer := 7; variable p: std_logic :='1'; begin loop p := p and vector_in(i); i := i-1; exit when i < 0; end loop; i := 7; out1 <= p; end process loop_p; end loop3; --------------------------------------------

V d trn th hin ba phng php khc nhau dng lnh hin thc ha hm AND cho t hp 8 bit u vo. Phng php th nht s dng lnh lp xc nh, phng php th hai v th ba s dng vng lp kim sot iu kin i vi bin chy i, v c bn c ba phng php u cho hiu qu m t ging nhau.

7. Pht biu ng thi

Pht biu ng thi (concurrent statements) c s dng m t cc kt ni gia cc khi thit k, m t cc khi thit k thng qua cch thc lm vic ca n (process statement). Hiu mt cch khc cc pht biu ng thi dng m t phn cng v mt cu trc hoc cch thc lm vic ng nh n vn c. Khi m phng th cc pht biu ng thi c thc hin song song c lp vi nhau. M VHDL khng quy nh v th t thc hin ca cc pht biu. Bt k pht biu ng thi no c quy nh th t thc hin theo thi gian u gy ra li bin dch. V tr ca cc pht biu ng thi nm trc tip trong khi begin end ca m t kin trc:
architecture identifier of design is {declarative_part} begin {concurrent_statements}

87

end iddentifier;

C tt c 7 dng pht biu ng thi: khi (block statement), qu trnh (process statement), gi th tc (procedure call statement), xc nhn gn tn hiu (signal assignment statement), khai bo khi con (component declaration statement), v pht biu sinh (generate statement). 7.1. Pht biu khi Pht biu khi (Block statement) l mt khi cc cu lnh song song th hin mt phn ca thit k, cc khi c th c khai bo lng ghp trong nhau v c tnh cht k tha. Pht biu khai bo block c cu trc nh sau:
block [(guard_expression)] [is] block_header block_declarative_part begin block_statement_part end block;

Trong : - guard_expression: nu c s dng th c mt tn hiu tn l GUARD c kiu Boolean c khai bo mt cch khng tng minh bng mt biu thc gn gi tr cho tn hiu , tn hiu GUARD c th s dng iu khin cc thao tc bn trong khi. - block_header v block_declarative_part: l cc khai bo v gn gi tr cho cc tham s generics, ports. - block_statement_part: khi chnh ca block cha cc lnh ng thi. V d v cc s dng block:
clump : block begin A <= B or C; D <= B and not C; end block clump ; maybe : block ( B'stable(5 ns) ) is port (A, B, C : inout std_logic ); port map ( A => S1, B => S2, C => outp ); constant delay: time := 2 ns; signal temp: std_logic; begin temp <= A xor B after delay; C <= temp nor B; end block maybe;

88

Xt mt v d y v s dng guarded block m phng mt bus ba trng thi nh sau:

---------------------------------------------library ieee; use ieee.std_logic_1164.all; ---------------------------------------------entity bus_drivers is end bus_drivers; ---------------------------------------------architecture behavioral of bus_drivers is signal TBUS: STD_LOGIC := 'Z'; signal A, B, OEA, OEB : STD_LOGIC:= '0'; begin process begin OEA <= '1' after 100 ns, '0' after 200 ns; OEB <= '1' after 300 ns; wait; end process; ----------------------------------------------B1 : block (OEA = '1') begin TBUS <= guarded not A after 3 ns; end block; ----------------------------------------------B2 : block (OEB = '1') begin TBUS <= guarded not B after 3 ns; end block; end behavioral;

Trong v d trn TBUS c kt ni gi tr o ca A, B ch trong trng hp cc tn hiu cho php tng ng OEA, OEB bng 1. iu kin ny c khai bo n trong tn hiu GUARD ca hai block B1 v B2. 7.2. Pht biu qu trnh Qu trnh (process) l mt khi cha cc khai bo tun t nhng th hin cch thc hot ng ca mt phn thit k. Trong m t kin trc ca khi thit k c th c nhiu khai bo process v cc khai bo ny c thc hin song song, c lp vi nhau khng ph thuc vo th t xut hin trong m t. Chnh v th mc d trong khi qu trnh ch cha cc khai bo tun t nhng mt khi c coi l mt pht biu ng thi. Cu trc ca qu trnh nh sau:
[postponed] process [(sensitivity_list)] [is] process_declarative_part

89

begin [process_statement_part] end [ postponed ] process [ process_label ];

Trong :
postponed: nu c s dng th qu trnh l mt qu trnh c tr

hon, nu khng l mt qu trnh thng thng. Qu trnh tr hon l qu trnh c thc hin ch sau khi tt c cc qu trnh khng tr hon (nonpostponded) bt u v kt thc. - sensitivity_list: tng t nh danh sch tn hiu c theo di i vi lnh wait. N c ngha l mi thay i ca cc tn hiu trong danh sch ny th cc lnh trong qu trnh ny s c thc hin. Khi m t cc khi logic t hp th cc danh sch ny chnh l cc tn hiu u vo, cn i vi mch dy th l tn hiu xung nhp ng b clk. - process_declarative_part: phn khai bo ca qu trnh, lu l cc khai bo tn hiu khng c t trong phn ny. - process_statement_part: Phn ni dung ca process. V d v cch s dng process:
---------------------------------------library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---------------------------------------entity counter4 is port( count : out std_logic_vector( 3 downto 0); enable : in std_logic; clk : in std_logic; reset : in std_logic ); end entity; ----------------------------------------architecture rtl of counter4 is signal cnt :std_logic_vector ( 3 downto 0) := "0000"; begin process (clk, reset) begin if (reset = '1') then cnt <= "0000"; elsif (rising_edge(clk)) then if (enable = '1') then cnt <= cnt + 1;

90

end if; end if; end process; count <= cnt; end architecture; ------------------------------------------------

v d trn m t cu trc mt b m 4 bit bng c php ca process, danh sch sensitive list bao gm tn hiu ng b CLK v tn hiu RESET, tn hiu RESET lm vic khng ng b, mi khi RESET bng 1 th gi tr m count c t gi tr 0. Nu RESET bng 0 v c sn dng ca xung nhp CLK th gi tr m c tng thm 1. Khi process cn rt hay c s dng m t cc t hp, khi tt c cc u vo ca mch t hp phi c a vo danh sch sensitive list, nu b st tn hiu u vo trong danh sch ny th mc d c php lnh vn ng nhng chc chn mch s hot ng sai v chc nng. Cc lnh bn trong khi process s m t s ph thuc logic ca u ra vi cc u vo.
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity mux2 is port(A : in std_logic; B : in std_logic; sel : in std_logic; S : out std_logic); end mux2; ---------------------------------------architecture behavioral of mux2 is begin mux: process (A, B, sel) begin CASE sel IS WHEN '0' => S <= A; WHEN others => S <= B; end case; end process mux; end behavioral; -----------------------------------------

v d trn m t mt khi chn knh (MUX) dng lnh case, cc u vo ca gm A, B v tn hiu chn Sel, u ra l S, S s chn bng A nu sel = 0 v bn B nu sel = 1. 91

7.3. Pht biu gn tn hiu ng thi Pht biu gn tn hiu ng thi

[label :] [postponed ] conditional_signal_assignment |[label:] [postponed ] selected_signal_assignment options ::= [ guarded ] [ delay_mechanism ]

Trong :
postponed: nu c s dng th lnh gn c tr hon, nu khng

l mt lnh gn thng thng. Lnh gn tr hon c thc hin ch sau khi tt c cc lnh khng tr hon (non-postponded) bt u v kt thc. - options: trong mc ny nu d liu c khai bo ty chn bo v (guarded) th s thc hin di s iu khin ca tn hiu n GUARD nh trnh by trn. delay_mechanism l phng thc lm vic theo tr ca tn hiu, c hai dng l transport v inertial nh trnh by 6.4. Pht biu gn tn hiu ng thi thng s dng trong cc kin trc dng dataflow. Cc lnh gn ny cng c th s dng cc c php c iu kin kin s dng WHEN hoc s dng t hp WITH/SELECT/WHEN. 7.3.1. Gn tn hiu dng WHEN C php tng qut nh sau:
target <= waveform1 when condition1 else waveform2 when condition2 else waveformN1 when conditionN1 else waveformN when conditionN else default_waveform;

Trong default_waveform c th chn gi tr UNAFFECTED. Tng ng vi on m trn c th s dng process v lnh tun t if nh sau:
process(sel1, waveform) begin if condition1 then target <= waveform1 elsif condition2 then target <= waveform2

92

elsif conditionN1 then target <= waveformN-1 elsif conditionN then target <= waveformN end if ; end process;

7.3.2. Gn tn hiu dng WITH/SELECT/WHEN C php tng qut nh sau:

WITH expression SELECT target <= options waveform1 WHEN choice_list1 , waveform2 WHEN choice_list2 , waveformN1 WHEN choice_listN1, waveformN WHEN choice_listN default_value WHEN OTHERS ; Trong default_value c th nhn gi tr UNAFFECTED on m

trn cng c th thay th bng lnh case trong mt process nh sau:

CASE expression IS WHEN choice_list1 => target <= waveform1; WHEN choice_list2 => target <= waveform2; WHEN choice_listN1 => target <= waveformN_1; WHEN choice_listN => target <= waveformN; END CASE;

minh ha cho s dng cu trc WHEN, v WITH/SELECT/WHEN xt m t mt b chn knh nh sau, khi thit k gm hai b gii m knh 4 u vo v 1 u ra c lp vi nhau, iu khin bi cc tn hiu sel1, sel2, b gii m th nht s dng cu trc WHEN, cn t hp th hai s dng cu trc WITH/SELECT/WHEN.
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity concurrent_expample is port(

93

A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); sel1, sel2 : in std_logic_vector(1 downto 0); O1, O2 : out std_logic ); end concurrent_expample; ----------------------------------------architecture dataflow of concurrent_expample is begin O1 <= A(0) WHEN sel1 = "00" else A(1) WHEN sel1 = "01" else A(2) WHEN sel1 = "10" else A(3) WHEN sel1 = "11" else UNAFFECTED; WITH sel2 SELECT O2 <= B(0) WHEN "00", B(1) WHEN "01", B(2) WHEN "10", B(3) WHEN "11", UNAFFECTED WHEN others; end dataflow; ------------------------------------------

M ngun trn c th thay th bng m s dng cc pht biu tun t tng ng nh sau:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity sequential_expample is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); sel1, sel2 : in std_logic_vector(1 downto 0); O1, O2 : out std_logic ); end sequential_expample; ----------------------------------------------architecture dataflow of sequential_expample is begin decodeA: process (A, sel1) begin if sel1 = "00" then O1 <= A(0); elsif sel1 = "01" then O1 <= A(1); elsif sel1 = "10" then O1 <= A(2); elsif sel1 = "11" then O1 <= A(3);

94

end if; end process decodeA; decodeB: process (B, sel2) begin CASE sel1 IS WHEN "00" => O2 <= B(0); WHEN "01" => O2 <= B(1); WHEN "10" => O2 <= B(2); WHEN "11" => O2 <= B(3); WHEN others => O2 <= 'X'; END CASE; end process decodeB; end dataflow; -----------------------------------------------

7.4. Pht biu generate Pht biu generate (generate statement) l mt c php lnh song song khc. N tng ng vi khi lnh tun t LOOP trong vic cho php cc on lnh c thc hin lp li mt s ln no . Mu dng ca pht biu ny nh sau:
for generate_parameter_specification | if condition generate [ { block_declarative_item } begin ] { concurrent_statement } end generate [label]; Lu rng cc tham s dng cho vng lp for phi l cc tham s tnh,

nu tham s dng ng s gy ra li bin dch. Di y l on m minh ha m t b cng 4 bit, thay v vic m t tng minh tt c cc bt ca u ra ta dng vng lp FOR/GENERATE gn cc gi tr cho chui nh C v tng O theo s quy:
---------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ---------------------------------------entity adder4_gen is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic

95

); end adder4_gen; ---------------------------------------------architecture dataflow of adder4_gen is signal C: std_logic_vector (4 downto 0); begin C(0) <= CI; CO <= C(4); Carry: for i in 1 to 4 generate C(i) <= (A(i-1) and B(i-1)) or (C(i-1) and (A(i-1) or B(i-1))); end generate Carry; Suma: FOR i IN 0 to 3 GENERATE SUM(i) <= A(i) xor B(i) xor C(i); END GENERATE Suma; end dataflow; ---------------------------------------------

Cu lnh GENERATE cn c th c s dng di dng cu trc IF/GENERATE . V d di y minh ha cho cch s dng . Khi thit k gm hai u vo 4 bit v mt u ra 2 bt, ti cc v tr bt chn ca a, b th u ra bng php AND ca cc tn hiu u vo:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity generate_expample2 is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); O : out std_logic_vector(1 downto 0) ); end generate_expample2; -----------------------------------------architecture dataflow of generate_expample2 is begin msk: FOR i IN 0 to 3 GENERATE ifgen: IF i rem 2 = 0 GENERATE O(i/2) <= A(i) and B(i); END GENERATE ifgen; END GENERATE msk; end dataflow;

Nh thy cc v d trn lnh GENERATE thng c s dng ci t cc khi x l logic ging nhau v mt cu trc, s lng cc khi ny c th 96

rt nhiu nn c php generate cho php vit m ngn gn. Ngoi ra trong mt s trng hp s lng cc khi ci t ph thuc vo cc tham s tnh m khng phi hng s th vic ci t bt buc phi thc hin bng lnh ny. 7.5. Pht biu ci t khi con Pht biu ci t khi con (component installation statement) s dng cho m t dng cu trc ca thit k khi khi thit k tng c cu to t nhiu nhng khi nh (xem v d thm 2.2.1). C php tng qut nh sau:
component component_name is generic (generic_variable_declarations ); port (input_and_output_variable_declarations); end component component_name;

on m trn ta khai bo s dng cc cng AND2, OR2 v XOR2. Sau khi c khai bo component th cc cng ny c th c s dng nhiu ln vi c php y nh sau:
identifier : component_name generic map( generic_variables => generic values) port map(input_and_output_variables => signals);

Trong -identifier l tn ca khi con s s dng cho ci t c tn l component_name -danh sch cc bin generic v cc cng c gn tng minh bng ton t =>, khi th t gn cc bin hoc cng khng quan trng. Cch th hai l gn cc cng khng tng minh, khi th t cc cng phing nh th t khai bo trong component. Tuy vy khng khuyn khch vit nh vy v khi ch cn nhm ln v th t c th lm sai chc nng ca thit k. minh ha r hn quay li v d v b cng nhiu bit trn:
entity adder is generic ( N port ( A B cin Sum Cout end entity adder : : : : : : ; natural := 32 ) ; in std_logic_vector(N-1 downto 0); in std_logic_vector(N-1 downto 0); in std_logic; out std_logic_vector(N-1 downto 0); out std_logic );

Khai bo component tng ng s l

component adder is generic (N : natural := 32) ; port ( A : in std_logic_vector(N-1 downto 0);

97

B : in std_logic_vector(N-1 downto 0); cin : in std_logic; Sum : out std_logic_vector(N-1 downto 0); Cout : out std_logic ); end component adder ; ---------------------------------------------------

Khai bo s dng component adder 16 bit dng tng minh s l:

U1: adder generic map (N => 16) port map (A => in_a, B=> in_b, Cin => in_c Sum => out_s, Cout => out_C );

Khai bo s dng component adder 16 bit dng khng tng minh s l:

U1: adder generic map (16) port map ( in_a, in_b, in_c out_s, out_C );

Xt mt v d y v ci t khi con di y, phn 6.4 khi nghin cu v pht biu gn tn hiu tun t ta c m t VHDL ca D_flipflop, v d sau dng pht biu ci t component m t mt thanh ghi dch gm 3 Dflipflop. S logic ca shift_reg:
CLK Din

SET

SET

SET

Dout

CLR

CLR

CLR

Hnh 2-5. S khi ca thanh ghi dch M t VHDL:

----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity shift_reg is port( Din : in std_logic; CLK : in std_logic; Dout : out std_logic );

98

end shift_reg; ----------------------------------------architecture structure of shift_reg is signal Q1, Q2 : std_logic; component D_flipflop port( D : in std_logic; CLK : in std_logic; Q : out std_logic ); end component; begin DFF1: D_flipflop port map (D => Din, CLK => CLK, Q => Q1); DFF2: D_flipflop port map (D => Q1, CLK => CLK, Q => Q2); DFF3: D_flipflop port map (D => Q2, CLK => CLK, Q => Dout); end structure; ------------------------------------------

v d trn cc 3 flipflop D c t ni tip v ta s ci t cng sao cho u ra ca thanh ghi trc s l u vo ca thanh ghi sau v sau mi xung nhp chui bit Q1, Q2, Q3 s dch sang bn phi mt bit.

8. Phn loi m ngun VHDL

HDL FOR SPECIFICATION

HDL FOR SIMULATION HDL FOR SYNTHESIS

HDL FOR SYNTHESIS

Hnh 2-6. Cc dng m ngun VHDL 99

Ngn ng VHDL c xem l mt ngn ng cht ch v phc tp, VHDL h tr vic m t thit k t mc cao cho n mc thp v trn thc t khng th xp ngn ng ny thuc nhm bc cao, bc thp hay bc chung nh cc ngn ng lp trnh khc. V phn loi m ngun VHDL c th chia lm ba dng chnh nh sau: - M ngun ch dnh cho tng hp (HDL for Synthesis): L nhng m ngun nhm ti m t thc ca cu trc mch. Ngoi vic tun th cht ch cc cu trc ca ngn ng th m ngun dng ny cn phi tun th nhng tnh cht, c im vt l ca mt mch tch hp nhm m bo m ngun c th c bin dch trn mt cng ngh phn cng c th no . - M ngun m phng c (HDL for Simulation): Bao gm ton b m tng hp c v nhng m m ch chng trnh m phng c th bin dch v th hin trn mi trng phn mm, v d cc m s dng cc lnh tun t dng gn tn hiu theo thi gian, cc vng lp c nh. - M ngun dnh cho m t c tnh (HDL for Specification): Bao gm ton b m m phng c v nhng cu trc dng m t cc c tnh khc nh tr (delay time), in dung (capacitance) thng gp trong cc m t th vin cng hay th vin i tng cng ngh. Trong khun kh ca chng trnh ny ta khng tm hiu su v dng m t ny. Mt s dng m ngun khng tng hp c m ch dnh cho m phng c lit k di dy: - Cc m m t tr thi gian ca tn hiu, trn thc t tr cc mch do tnh cht vt l ca phn cng quy nh, m ngun VHDL c lp vi phn cng nn cc m quy nh tr u khng tng hp c m ch dnh cho m phng:
wait for 5 ns; A <= B after 3 ns; - Cc m ci t gi tr, ban u signal a :std_logic_vector (3 downto 0) := 0001; signal n : BIT := 0; - M t flip-flop lm vic c hai sn xung nhp, trn thc t cc Flip-

flop ch lm vic mt sn m hoc sn dng, on m sau khng tng hp c thnh mch.

PROCESS ( Clk ) BEGIN

100

IF rising_edge(Clk) or falling_edge(CLk) THEN Q <= D ; END IF ; END PROCESS ; - Cc m lm vic vi kiu s thc, cc trnh tng hp hin ti mi ch

h tr cc mch tng hp vi s nguyn, cc code m t sau khng th tng hp c:

signal a, b, c: real begin C <= a + b; end architechture;

- Cc lnh bo co v theo di (report, assert), cc lnh ny phc v qu trnh m phng kim tra mch, khng th tng hp c:
assert a='1' report "it OK" severity NOTE; report "finished test";

9. Kim tra thit k bng VHDL.

Mt trong nhng phn cng vic kh khn v chim nhiu thi gian trong qu trnh thit k vi mch l phn kim tra thit k. Trn thc t c rt nhiu phng php, cng c khc nhau ra i nhm n gin ha v tng tin cy qu trnh kim tra. Mt trong nhng phng php ph bin v d dng l phng php vit khi kim tra trn chnh HDL, bn cnh mt s hng pht trin hin nay l thc hin cc khi kim tra trn cc ngn ng bc cao nh System C, System Verilog, cc ngn ng ny h tr nhiu hm bc cao cng nh cc hm h thng khc nhau. Trong khun kh ca chng trnh chng ta s nghin cu s dng phng php th nht l s dng m t VHDL cho khi kim tra. Lu rng m hnh kim tra di y l khng bt buc phi theo, ngi thit k sau khi nm c phng php c th vit cc m hnh kim tra khc nhau ty theo mc ch v yu cu. Chng ta bt u vi vic kim tra cho khi khi cng 4 bit c vit bng cu lnh generate c phn 7.4:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity adder4_gen is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0);

101

CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic ); end adder4_gen; ---------------------------------------------architecture dataflow of adder4_gen is signal C: std_logic_vector (4 downto 0); begin C(0) <= CI; CO <= C(4); Carry: for i in 1 to 4 generate C(i) <= (A(i-1) and B(i-1)) or (C(i-1) and (A(i-1) or B(i-1))); end generate Carry; --SUM(0) <= A(0) xor B(0) xor CI; Suma: FOR i IN 0 to 3 GENERATE SUM(i) <= A(i) xor B(i) xor C(i); END GENERATE Suma; end dataflow; ---------------------------------------------

Nhim v ca chng ta l cn kim tra xem vi m t nh trn th b cng c lm vic ng chc nng khng. Quy trnh thit k chia lm hai bc, bc th nht s tin hnh kim tra nhanh vi mt vi gi tr u vo, bc th hai l kim tra ton b thit k: 9.1. Kim tra nhanh S kim tra nhanh nh sau:

INPUTs ASIGNMENT

DUT

Hnh 2-7. Kim tra nhanh thit k s trn DUT l vit tt ca Device Under Test ngha l i tng b kim tra, trong trng hp ny l b cng 4 bit, khi Input generator s to ra mt hoc mt vi t hp u vo gn cho cc cng input ca DUT. hiu k hn ta phn tch m ngun ca khi kim tra nh sau:
----------------------------------------library IEEE;

102

use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity test_adder4_gen is end test_adder4_gen; ----------------------------------------architecture testbench of test_adder4_gen is component adder4_gen is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic ); end component; -- khai bao cac tin hieu vao ra cho DUT signal A : std_logic_vector(3 downto 0) := "0101"; signal B : std_logic_vector(3 downto 0) := "1010"; signal CI : std_logic := '1'; -- output--signal SUM : std_logic_vector(3 downto 0); signal CO : std_logic; begin DUT: component adder4_gen port map ( A => A, B=> B, CI => CI, SUM => SUM, CO =>CO ); end testbench; ------------------------------------------------

Khi kim tra thng l mt thit k m khng c cng vo hoc ra ging nh trn. Trong khi kim tra s khai bo DUT nh mt khi thit k con do vy component adder4_gen c khai bo trong phn khai bo ca kin trc. Bc tip theo cn c vo cc cng vo ra ca DUT s tin hnh khai bo cc tn hiu tng ng, trnh nhm ln cho php dng tn cc tn hiu ny trng vi tn cc tn hiu vo ra ca DUT. Cc tn hiu tng ng vi cc chn input c gn gi tr khi to l cc hng s hp l bt k, vic gn ny tng ng vi ta s gi ti DUT cc gi tr u vo xc nh. Cc tn hiu tng ng vi chn output s trng v khng c php gn gi tr no c. 103

Bc cui cng l ci t DUT l mt khi con adder4_gen vi cc chn vo ra c gn tng ng vi cc tn hiu khai bo trn. Khi chy m phng ta thu c kt qu nh sau:

Hnh 2-8. Gin sng kim tra khi cng 4 bit 9.1. Kim tra t ng nhiu t hp u vo Vic kim tra nhanh cho php pht hin nhng li n gin v mt chc nng v khng th da vo kt qu ca bc kim tra ny kt lun khi ca chng ta lm vic ng hay cha. V mt l thuyt, khi thit k c coi l lm vic ng nu nh n cho ra kt qu ng vi mi t hp u vo. v d trn ta c 3 tn hiu u vo l a(3:0), b(3:0), CI, v vy t hp tt c cc tnh hiu u vo l 24 * 2 *4 *21 = 29 = 512 t hp. R rng i vi kh nng ca my tnh hin i y l mt con s rt nh. Nh vy khi adder4 c th c kim tra vi tin cy ln ti 100%. S ca kim tra t ng nh sau:

DUT
INPUTs GENERATOR OUTPUTs COMPARATOR

ETALON

Hnh 2-9. M hnh kim tra t ng Hnh 16: M hnh chung ca khi kim tra thit k t ng Trong : - DUT (device under test) i tng kim tra, v d nh trong trng hp ca chng ta l adder4 104

ETALON: l mt thit k chun thc hin chc nng ging nh DUT nhng c th s dng cc cu trc bc cao dng khng tng hp c (simulation only), s dng thut ton n gin nht c th, etalon thng c m t lm vic nh mt function trnh cc cu trc ph thuc thi gian hay pht sinh ra li. Nhim v ca Etalon l thc hin chc nng thit k mt cch n gin v chnh xc nht lm c s so snh vi kt qu ca DUT. - INPUTs GENERATOR: khi to u vo, khi ny s to cc t hp u vo khc nhau v ng thi gi n hai khi l DUT v ETALON. - OUTPUTs COMPARATORs: Khi ny s so snh kt qu u ra ti nhng thi im nht nh v a ra tn hiu cho bit l hai kt qu ny c nh nhau khng. c th gn nhiu u vo ti cc im khc nhau trong khi kim tra phi to ra mt xung nhp ng h dng nh CLK, cc t hp gi tr u vo mi s c gn ti cc thi im nht nh ph thuc CLK, thng l vo v tr sn m hoc sn dng ca xung nhp. Quay tr li vi mudule cng 4 bit adder4_gen trn, vi thit k ny ta c th thc hin kim tra cho tt c cc t hp u vo (512 t hp), trc ht ta vit mt khi chun etalon cho b cng 4 bit nh sau:
----------- adder 4-bit etalon ---------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder4_etalon is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic); end adder4_etalon; -----------------------------------------architecture behavioral of adder4_etalon is signal s_sig: std_logic_vector(4 downto 0); signal a_sig: std_logic_vector(4 downto 0); signal b_sig: std_logic_vector(4 downto 0); begin a_sig <= '0' & A;

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b_sig <= '0' & B; plus: process (a_sig, b_sig, CI) begin s_sig <= a_sig + b_sig + CI; end process plus; SUM <= s_sig (3 downto 0); CO <= s_sig (4); end behavioral; -----------------------------------------

adder4_etalon thc hin php cng 4 bit bng lnh + ca VHDL, kt qu php cng ny l tin cy 100% nn c th s dng kim tra thit k adder4_gen trn ca chng ta. thc hin cc thao tc kim tra t ng, s dng mt khi kim tra c ni dung nh sau:
-----------adder 4 testbench_full ------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; library STD; use STD.TEXTIO.ALL; ----------------------------------------entity adder4_testbench is end adder4_testbench; ----------------------------------------architecture testbenchfull of adder4_testbench signal a_t : std_logic_vector(3 downto 0) := signal b_t : std_logic_vector(3 downto 0) := signal sum_t : std_logic_vector(3 downto 0); signal sum_e : std_logic_vector(3 downto 0); signal ci_t : std_logic := signal co_t : std_logic; signal co_e : std_logic; signal clk : std_logic :=

is "0000"; "0000"; '0'; '0';

component adder4_gen port (A : in std_logic_vector (3 downto 0); B : in std_logic_vector (3 downto 0); CI : in std_logic; SUM : out std_logic_vector (3 downto 0); CO : out std_logic ); end component; component adder4_etalon port (A : in std_logic_vector (3 downto 0);

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B : in std_logic_vector (3 downto 0); CI : in std_logic; SUM : out std_logic_vector (3 downto 0); CO : out std_logic ); end component; BEGIN --create clock create_clock: process begin wait for 15 ns; CLK <= not CLK after 50 ns; end process create_clock; check: process (clk) variable info: line; variable test_cnt: integer := 0; begin if clk = '1' and clk'event then write(info, string'("Test # ")); write(info, integer'(test_cnt + 1)); write(info, string'(" a = ")); write(info, integer'(conv_integer(a_t))); write(info, string'(" b = ")); write(info, integer'(conv_integer(b_t))); write(info, string'(" CI = ")); write(info, integer'(conv_integer(ci_t))); write(info, string'(" sum = ")); write(info, integer'(conv_integer(sum_t))); write(info, string'(" CO = ")); write(info, integer'(conv_integer(co_t))); write(info, string'(" sum_e = ")); write(info, integer'(conv_integer(sum_e))); write(info, string'(" CO_e = ")); write(info, integer'(conv_integer(co_e))); if sum_e /= sum_t or co_e /= co_t then write(info, string'("FAILURE")); else write(info, string'(" OK")); end if; writeline(output, info); -- input data generator. test_cnt := test_cnt + 1; ci_t <= not ci_t; if ci_t = '1' then

107

a_t <= a_t +1; end if; if a_t = "1111" then b_t <= b_t + 1; end if; assert test_cnt < 512 report "end simulation" severity NOTE; end if; end process check; -- component installation dut: adder4_gen port map ( A => a_t, B => b_t, CI => ci_t, SUM =>sum_t, CO => co_t); etalon: adder4_etalon port map (A => a_t, B => b_t, CI => ci_t, SUM =>sum_e, CO => co_e); END testbenchfull; -----------------------------------------

Khi kim tra ci t ng thi cc khi con l adder4_gen (DUT) v adder4_etalon (ETALON), cc khi ny c cc u vo d liu y ht nh nhau ly t cc tn hiu tng ng l a_t, b_t, ci_t. Cc u ra ca hai khi ny tng ng l sum_t, co_t cho DUT v sum_e, co_e cho ETALON. Khi kim tra t ng ny thc cht lp li chc nng ca khi kim tra nhanh nhiu ln vi nhiu t hp u vo, mt khc s dng kt qu tnh ton t khi thit k chun ETALON kim tra t ng tnh ng n ca kt qu u ra t khi DUT cn kim tra. lm c vic , mt xung nhp clk c to ra, chu k ca xung nhp ny c th nhn gi tr bt k, v d on m trn ta to xung nhp clk c chu k T = 2 x 50 ns = 100 ns. C xung nhp ny ta s to mt b m theo xung m l clk m s lng test, khi m 512 test th s thng bo ra mn hnh vic thc hin test xong. Ti mi thi im sn dng ca clk gi tr m ny tng thm 1 ng thi ti thi im t hp gi tr u vo thay i tun t qut ht 512 t hp gi tr khc nhau. u tin cc gi tr a_t, b_t, ci_t nhn gi tr khi to l 0, 0, 0. Ti cc sn dng ca xung nhp thay i gi tr ci_t trc, nu ci_t = 1 th tng a_t thm 1 n v, sau kim tra nu a_t = 1111 th s tng b_t thm 1 n v.

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Cc u ra sum_t, sum_e, co_t, co_e s c so snh vi nhau sau mi xung nhp, nu nh sum_t = sum_e v co_t = co_t th kt lun l adder4_gen lm vic ng (TEST OK) v ngc li l lm vic sai (TEST FAILURE) V s lng t hp u vo l ln nn khng th quan st bng waveform na, kt qu khi c thng bo trc tip ra mn hnh. Khi chy m phng ta thu c thng bo nh sau:
#Test#1a = 0b = 0 CI = 0 sum = 0 CO = 0sum_e = 0CO_e = 0 OK #Test#2a = 0b = 0 CI = 1 sum = 1 CO = 0sum_e = 1CO_e = 0 OK #Test#3a = 1b = 0 CI = 0 sum = 1 CO = 0sum_e = 1CO_e = 0 OK #Test#4a = 1b = 0 CI = 1 sum = 2 CO = 0sum_e = 2CO_e = 0 OK #Test#5a = 2b = 0 CI = 0 sum = 2 CO = 0sum_e = 2CO_e = 0 OK #Test#6a = 2b = 0 CI = 1 sum = 3 CO = 0sum_e = 3CO_e = 0 OK #Test#7a = 3b = 0 CI = 0 sum = 3 CO = 0sum_e = 3CO_e = 0 OK #Test#8a = 3b = 0 CI = 1 sum = 4 CO = 0sum_e = 4CO_e = 0 OK #Test#9a = 4 b = 0 CI = 0 sum = 4 CO = 0sum_e= 4CO_e = 0 OK #Test#10a =4 b = 0 CI = 1sum = 5 CO = 0sum_e = 5CO_e = 0 OK #Test#11a =5 b = 0 CI = 0sum = 5 CO = 0sum_e = 5CO_e = 0 OK #Test#511a =15b = 14CI = 0sum =13CO = 1sum_e =13CO_e= 1OK #Test#512a =15b = 15CI = 1sum= 15CO = 1sum_e =15CO_e = 1 OK # ** Note: end simulation # Time: 61385 ns Iteration: 0 Instance: /adder4_testbench

Nu nh tt c cc trng hp u thng bo l OK th c th kt lun DUT lm vic ng, qu trnh kim tra hon tt. Lu rng khi thc hin kim tra t ng th ETALON khng phi lc no cng c chnh xc 100% nh trn v i khi rt kh vit c khi ny ny. Khi ta phi c phng n kim tra khc. im lu th hai l trn thc t vic kim tra vi mi t hp u vo (full_testbench) thng l khng th v s lng cc t hp ny trong a s cc trng hp rt ln v d nh nu khng phi b cng 4 bit m l b cng 32 bit th s lng t hp u vo l 232x2+1 = 265 l mt con s qu ln kim tra ht d bng cc my tnh nhanh nht. Khi qu trnh kim tra chia thnh hai bc: Bc 1 s tin hnh kim tra bt buc vi cc t hp c tnh cht ring nh bng 0 hay bng s ln nht, hoc cc t hp gy ra cc ngoi l, cc t hp gy pht sinh li. Nu kim tra vi cc t hp ny khng c li s chuyn sang bc th hai l RANDOM_TEST. B phn kim tra s cho chy RANDOM_TEST vi s lng u vo khng gii hn. Nu trong qu trnh ny pht hin ra li th t hp 109

gi tr gy ra li s c b xung vo danh sch cc t hp bt buc phi kim tra bc 1 v lm li cc bc kim tra t u sau khi sa li. Kim tra c coi l thc hin xong nu nh vi mt s lng rt ln RANDOM_TEST m khng tm thy li.

110

Bi tp chng 2 Bi tp
1. Thit k full_adder trn VHDL, trn c s thit k b cng 4 bit tng t IC 7483.
A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3

7483

Cin

Cout

2.

Thit k b gii m nh phn 2_to_4 c u ra thun, nghch tng t IC 74LS139

74LS139
Ya0 Aa Ba Ea Ya1 Ya2 Ya3

Ab Bb Eb

Yb0 Yb1 Yb2 Yb3

3.

Thit k b gii m nh phn 3_to_8 c u ra thun, nghch tng t IC 74LS138.

Y0 A B C E E1 E2 Y1 Y2 Y3 Y4 Y5 Y6 Y7

74LS138

4.

Thit b chn knh 4 u vo 1 u ra MUX4_1 tng t IC 74153 nhng ch h tr mt knh chn (IC ny c hai knh chn ring bit nh hnh v)

111

I0a I1a Ya I2a I3a Ea

74LS153

I0b I1b I2b I3b Eb S0 S1 Yb

5. 6. 7.

Thit b phn knh 1 u vo 4 u ra DEMUX1_4. Thit k b cng/ tr 4 bit s dng ton t cng trn VHDL. Thit k b so snh hai s khng du 4 bit tng t IC 7485.
A0 A1 A2 A3 B0 B1 B2 B3

7485

A>B A=B A<B

A>B A=B A<B

8.

Thit k cc b chuyn i m t NBCD 7-SEG(LED 7 on) tng t IC 7447, h tr cng LamTest, khi cng ny c gi tr bng 1, tt c n phi sng khng ph thuc m u NBCD u vo. n gin, cc chn RBI, RBO khng cn thit k.
A A B C D B C

7447

D E F G

BI/RBO RBI LT

9.

Thit k cc flip-flop ng b D vi y cc chn tn hiu nh sau:

112

SET

CLK
CLR

10. Thit k cc flip-flop ng b JK.vi y ut cc chn tn hiu nh sau:

SET

CLR

11. Thit k trn VHDL thanh ghi dch tri qua phi 32-bit, s lng bit dch l mt s nguyn t 1-31 trn VHDL (s dng ton t dch). 12. Thit k thanh ghi dch ng b ni tip 4 bit sang bn tri, vi u vo ni tip SL, h tr tn hiu Reset khng ng b v tn hiu Enable. 13. Thit k thanh ghi dch ng b ni tip 4 bit sang bn phi, vi u vo ni tip SR, h tr tn hiu Reset khng ng b v tn hiu Enable. 14. Thit k IC m nh phn theo cu trc ca IC 7493, IC c cu thnh t mt b m 2 v 1 b m 8 c th lm vic c lp hoc kt hp vi nhau.
7493
INA INB Qa Qb Qc R0(1) R0(2) Qd

15. Thit k IC m theo cu trc ca IC 7490, IC c cu thnh t mt b m 2 v 1 b m 5 c th lm vic c lp hoc kt hp vi nhau to thnh b m thp phn.

113

7490
INA INB Qa Qb Qc R0(1) R0(2) R9(1) R9(2) Qd

16. Thit k IC m theo cu trc ca IC 4510, c kh nng m ngc, xui (up/Dn), t li trng thi (PL v D[3:0]), cho php m (CE), Reset khng ng b (MR) nh hnh v sau:

D0

D2 D1

D3

PL

Qa Qb Qc MR CE Un/Dn CP TC Qd

MC14510

17. Thit k b m thp phn ng b, RESET khng ng b, c tn hiu ENABLE. 18. S dng b m n 25 thit k b chia tn t tn s 50Hz thnh 1Hz, tn hiu tn s a ra c dng i xng. 19. Thit k khi m ha u tin, u vo l chui 4 bit u ra l m nh phn 2 bit th hin v tr u tin t tri qua phi xut hin bit 1. Trng hp khng c bt 1, th u ra nhn gi tr khng xc nh. (XX). 20. Thit k khi m ha u tin, u vo l chui 4 bit u ra l m nh phn 2 bit th hin v tr u tin t tri qua phi xut hin bit 0. Trng hp khng c bt 0, th u ra nhn gi tr khng xc nh. (XX). 21. Thit k khi tnh gi tr Parity cho mt chui 8 bit vi quy nh Parity = 1 nu s bt bng 1 l s l. 22. Thit k b m ha thp phn tng t IC 74147 vi 9 u vo v 4 u ra.Ti mt thi im ch c 1 trong s 9 u vo tch cc Gi tr 4 bit u

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23.

24. 25. 26. 27.

ra l s th t ca u vo tch cc tng ng. Nu khng u vo no tch cc th u ra bng 0. Thit k cc b chuyn i m t BINARY BCD, BCD BINARY cho cc s c gi tr t 0-99. BCD GRAY, GRAY BCD. BCD 7SEG, 7SEG BCD. 7SEG GRAY, GRAY-7SEG Thit k b m nh phn K = 12 dng JK Flip-flop Hin thc s m CRC ni tip v song song bng VHDL. Thit k khi cng cho 2 s NBCD, kt qu thu c l mt s c hai ch s biu din di dng NBCD. Thit k khi thc thi nhim v hon v cc v tr bit ca mt chui 32 bit theo ma trn hon v sau:
18 9 17 26 2 15 1 25 3 23 6 14 28 16 20 4 5 13 22 29 19 27 21 7 30 10 11 31 8 12 24 0

28. Theo ma trn trn th bit th 31 ca kt qu bng bit th 18 ca chui u vo, bt th 30 l bit th 2 v tip tc nh vy cho ti ht. 29. Vit m t VHDL cho khi thit k c s sau, trong cc ma trn hon v ly t ma trn bi 25.
64-bit data_in

32-bit high

32-bit low

Hon v

Hon v

32-bit

32-bit

64-bit data_out

30. Vit m t VHDL cho khi bin i d liu sau, d liu u vo c tc thnh hai phn 32 bit thp v 32 bit cao, sau tng phn c x l ring nh trn s v kt qu u ra c hp bi kt qu ca tng phn ny.

115

32-bit Key

64-bit data_in

32-bit high

32-bit low

32-bit

32-bit

64-bit data_out

Cu hi n tp l thuyt
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Trnh by s lc v ngn ng m t phn cng, cc ngn ng ph bin, u im ca phng php dng HDL thit k phn cng Cu trc ca thit k bng VHDL. Cc dng m t kin trc khc nhau trong VHDL, u im, nhc im v ng dng ca tng loi. Trnh by v i tng d liu trong VHDL. Trnh by v cc kiu d liu trong VHDL, kiu d liu tin nh ngha v d liu nh ngha bi ngi dng. Ton t v biu thc trong VHDL. Pht biu tun t, bn cht, ng dng, ly v d VHDL n gin v pht biu ny. Pht biu ng thi, bn cht, ng dng, ly v d VHDL n gin v pht biu ny. Phn loi m ngun VHDL, th no l m tng hp c v m ch dng m phng. Yu cu chung i vi kim tra thit k trn VHDL, cc dng kim tra thit k trn VHDL. Vai tr v phng php t chc kim tra nhanh khi thit k VHDL. Vai tr v phng php t chc kim tra t ng khi thit k VHDL. M t khi t hp trn VHDL, ly v d. M t mch tun t trn VHDL, ly v d.

116

Chng 3 THIT K CC KHI MCH DY V T HP THNG DNG

Ni dung ca chng II cung cp cho ngi hc nhng k nng c bn ca VHDL, trn c s chng III s gii thiu tip cho ngi hc bt u thit k cc khi s phc tp bng cch ghp ni cc khi c bn li thnh thit k ln hon chnh. Bn cnh chng III cng cung cp mt s lng ln cc thut ton khc nhau cho nhng khi thit k thng dng t b cng, b m, thanh ghi, khi nhn, chia cho ti cc khi lm vic vi s thc. Ngi hc c th trn c s nghin cu hon thin, pht trin v mt thut ton v cu trc cng bit cch tip cn vi cc thut ton phc tp hn trong ti liu tham kho, bn cnh l kh nng s dng cc khi thit k lm nn tng cho cc thit k cp phc tp hn gp trong cc bi ton chuyn ngnh. Nhng k nng ngi hc phi c c sau khi thc hin cc bi tp thc hnh chng ny l lm ch c thit k v mt cu trc cng nh v mt hnh vi, ni mt cch khc l hiu r cu to ca mch v cch thc mch ny thc hin chc nng thit k hay l gin thi gian lm vic ca mch. Phn thc hnh ca chng III bao gm nhng bi tp t d n kh, vi mc ch gip ngi c rn luyn t duy thit k cc khi mch s t vic xy dng s thut ton, s hin thc ha cho ti m t bng VHDL v m phng kim tra.

117

1. Cc khi c bn
1.1. Khi cng n gin Khi cng n gin: thc hin php cng gia hai s c biu din di dng std_logic_vector hay bit_vector. Cc cng vo gm hng t A, B, bit nh Cin, cc cng ra bao gm tng Sum, v bit nh ra Cout:
A B Cin

Cout

Sum

Hnh 3-1. S khi b cng Hm cng c th c m t trc tip bng ton t + mc d vi kt qu ny th mch cng tng hp ra s khng t c ti u v tc cng nh ti nguyn, m t VHDL ca b cng nh sau:
--------- Bo cong don gian -------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder32 is port( Cin : in std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); SUM : out std_logic_vector(31 downto 0); Cout: out std_logic ); end adder32; ----------------------------------------architecture behavioral of adder32 is signal A_temp : std_logic_vector(32 downto 0);

118

signal B_temp : std_logic_vector(32 downto 0); signal Sum_temp : std_logic_vector(32 downto 0); begin A_temp <= '0'& A; B_temp <= '0'& B; sum_temp <= a_temp + b_temp + Cin; SUM <= sum_temp(31 downto 0); Cout <= sum_temp(32); end behavioral; -----------------------------------------

Kt qu m phng cho thy gi tr u ra Sum v Cout, thay i tc th mi khi c s thay i cc gi tr u vo A, B hoc Cin.

Hnh 3-2. Kt qu m phng b cng 1.2. Khi tr V cc s c du trn my tnh c biu din di dng s b 2 (2complement), do thc hin php tr A-B th tng ng vi thc hin A + b2(B) Xt v d A = 10 = 1010, B = 5 = 0101 biu din di dng s c du 5bit ta phi thm bit du bng 0 vo trc.
A = 01010, B2(A) = not (A) + 1 = 10101 + 1 B = 00101, B2(B) = not (B) + 1 = 11010 + 1 = 10110 = 11011

Tnh A B:
A 01010 01010 - = = + B 00101 11011 ------1 00101

Loi b bit nh kt qu cui cng ta c A B = 00101 = 5. Tnh B A:

B 00101 00101 - = = + A 01010 10110 -------0 11011

119

Loi b bit nh ta c B A = 11101, y l s m, mun tnh gi tr tuyt i kim tra li ly b 2 ca 11101

B 2 (11101) = 00100 + 1 = 00101 = 5

vy B A = -5 Da trn tnh cht trn ca s b hai ta ch cn thc hin mt thay i nh trong cu trc ca b cng n c kh nng thc hin c php cng ln php tr m khng lm thay i ln v ti nguyn logic cng nh tr ca mch. Ti u vo s b xung thm tn hiu SUB, tn hiu ny quyt nh s thc hin php cng hay php tr. Khi SUB = 1 ly b 2 ca B s ly o B v cho gi tr u vo Cin =1, hin thc trn mch cu trc b cng c b xung mt khi MUX trc cng B, khi ny c hai u vo l B v not B, nu SUB= 0 th B c chn, nu SUB = 1 th not B c chn. u vo Cin c OR vi SUB trc khi vo b cng.
A B Sub Cin

MUX

Cout

Sum

Hnh 3-3. S khi b cng tr n gin Trong m ngun cho khi cng/tr adder32 nh mt khi con (component). adder_sub.vhd s dng b cng

------------ Bo cong tr n gin ---------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -------------------------------------------entity adder_sub is

120

port( SUB : in std_logic; Cin : in std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); SUM : out std_logic_vector(31 downto 0); Cout: out std_logic ); end adder_sub; --------------------------------------------architecture rtl of adder_sub is signal B_temp : std_logic_vector(31 downto 0); signal Cin_temp : std_logic; component adder32 is port ( Cin : in std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); SUM : out std_logic_vector(31 downto 0); Cout : out std_logic ); end component; -------------------------------------------begin Cin_temp <= SUB or Cin; MUX32: process (B, SUB) begin if SUB = '1' then B_temp <= not B; else B_temp <= B; end if; end process MUX32; add: component adder32 port map (Cin_temp, A, B_temp, SUM, Cout); end rtl; --------------------------------------------

1.3. Khi cng thy nh trc. tr t hp ca khi cng gy ra bi chui bit nh, b cng ni tip c c im l tr cao do c im ca chui bit nh l bit nh sau phi i bit nh trc n.

121

A B

Cout

Sum Cin

Hnh 3-4. S khi b cng 1 bit y Nh thy trn hnh v th thi gian tr ca chui bit nh phi thng qua ti thiu mt cng AND v mt cng OR, nu l b cng 32-bit th tng thi gian tr l thi gian tr ca 32 cng AND v 32 cng OR. Trn thc t tr ca cng AND, cng OR gn tng ng nn n gin ta xem tr ca mt trong hai cng ny l mt lp tr hay mt level logic. Nh vy b cng ni tip c 32x2 = 64 lp tr. Php cng l mt php ton c bn v s dng nhiu do vy vic nghin cu, s dng cc thut ton tng tc b cng v ang c thc hin rt nhiu. Trong phn ny ta xem xt mt thut ton ph bin nhm rt ngn thi gian thc hin tnh ton chui bit nh l thut ton Cng thy nh trc (Carry Look-Ahead Adder). tng ca phng php ny l s dng s c kh nng pht huy ti a cc php ton song song tnh cc i lng trung gian c lp vi nhau nhm gim thi gian i khi tnh cc bit nh. Gi s cc u v l a(31:0), b(31:0) v u vo Cin. Khi nh ngha: gi = ai and bi = ai .bi nh pht sinh (generate carry) Nu ai, bi bng 1 th gi bng 1 khi s c bit nh sinh ra v tr th i ca chui. pi = ai or bi = ai + bi nh lan truyn (propogation carry). Nu hoc ai, bi bng 1 th v tr th i bt nh s c chuyn tip sang v tr i+1, nu c hai ai, bi bng 0 th chui nh trc s dng li v tr i. Cc gi tr p, g c th c tnh song song sau mt lp tr. T ngha ca pi v gi c th xy dng cng thc cho chui nh nh sau, gi ci l bit nh sinh ra v tr th i. Khi ci = 1 nu hoc gi bng 1 ngha l c sinh nh ti v tr ny, hoc c mt bit nh sinh ra ti v tr th -1 j < i gj = 1 (vi quy uc g1 = Cin) v bit nh ny lan truyn qua cc bt tng ng t j+1, j+2, i. ngha l tch gj . pj+1 .pj+2 .pi = 1. V d bit nh v tr th 0 l c0 = 1 nu nh c nh sang v tr th 1 v bng 0 nu nh khng c nh. C0 bng 1 nu nh hoc ti v tr 0 c sinh nh (g0 = 1), hoc c nh ca Cin v nh ny c lan truyn qua v tr th 0 (Cin = 1 v P0 = 1). 122

Cng thc cho cc bit nh c th vit theo quy lut sau: c0 = g0 + Cin . p0 , c1 = g1 + g0 . p1 + Cin . p0 . p1 = g1 + c0 .p1 , c2 = g2 + g0 . p1 . p2 + g1 . p2 + Cin . p0 . p1 . p2 = g2 + c1 .p2 , c3 = g3 + g0 . p1 . p2 . p3 + g1 . p2 . p3 + g2 . p3 + Cin . p0 . p1 . p2 . p3= g3 + c2 .p3 , (3.1) Cc cng thc v thc cht l mt cch trnh by khc ca thut ton cng ni tip. Nhng cch trnh by ny gi cho mt s c th rt ngn thi gian tnh cc gi tr c: theo cng thc trn th cc gi tr bit nh sau vn ph thuc vo gi tr bit nh trc, tnh c0, c1, c2, c3 th phi c Cin xc nh. S ph thuc ny l t nhin v khng th thay i. Nu b ht cc yu t ph thuc vo Cin v tnh cc i lng trung gian sau: pi = ai + bi (vi i =0 -3) gi = ai . bi (vi i =0 -3) p01 = p0 . p1 p02 = p0 . p1. p2 p03 = p0 . p1 . p2 . p3 g01 = g1 + g0 . p1 g02 = g2 + g0 . p1 . p2 + g1 . p2 g03 = g3 + g0 . p1 . p2 . p3 + g1 . p2 . p3 + g2 . p3 = g01p23+g23 (3.2) Khi nu chia khi cng N-bit thnh cc khi 4 bit th cc i lng trn ca tt c cc khi s c tnh song song vi nhau. Ta gi khi thc thi cc tnh ton l CLA (Carry Look Ahead), khi c th phn tch c tr ca mt CLA nh sau Bng 3-1 Tnh s lp tr ca CLA Lp tr p G 1 pi = ai + bi (vi i =0 - gi = ai . bi (vi i =0 -3) 3) 2 p01, p12, p23 g0p1, g1p2, g2,p3 3 P03 g01, g23 = (g3+g2p3) 4 -g02, g01p23 5 -g03

123

C th tnh c tnh xong p03 phi cn 3 lp tr logic, tnh c g03 cn 5 lp tr logic. Ngha l cc gi tr p lun c tnh trc g. Mt cch tng qu nu nhn li s thy ngha ca cc i lng p, g tnh bi CLA vn khng thay i, v d p03 = 1 ni ln rng cm cc bit t 0 ti 3 c kh nng lan truyn bit nh, g02 = 1 ni ln rng cm cc bit t 0 ti 2 sinh ra bit nh. Ta vit li cng thc cho cc bit nh c3, v tng t cho c7, c11, c15 nh sau c3 = g03 + Cin . p03 c7 = g47 + g03 .p47 + Cin . p03 . p47 c12 = g811 + g47 . p811 + g03 .p47 . p811 + Cin . p03 . p47 . p811 c15 = g1215 + g811 . p1215 + g47 . p811 . p1215 + g03 .p47 . p811 . p1215 + Cin . p03 . p47 . p811. p1215 (3.3) Trong cc i lng g03, p03, g47, p47 , g811, p811, g1215, p1215 c tnh song song. Cc cng thc trn hon ton trng lp vi cng thc tnh bit nh cho mt b cng 4 bit (1), do vy khi trn li c xy dng trn c s mt khi CLA. T bng tnh tr ca mt CLA c th suy ra tnh c c3 cn 6 lp tr logic, tnh c c7 cn 7 lp tr logic, c11 cn 8 lp tr logic, c15 cn 9 lp tr logic Nu so snh vi b cng 16 bt cn 16 x 2 = 32 lp tr logic th l mt s ci thin ng k v tc , b li ta s mt nhiu ti nguyn hn do vic s dng tnh cc gi tr trung gian trn. Trn thc t b cng Carry Look Ahead Adder thng c xy dng t cc b 4 bt CLA, mi b ny c nhim v tnh ton cc gi tr trung gian. S khi ca chui bit nh nh sau.

124

A(15:12)

B(15:12)

A(11:8)

B(11:8)

A(7:4)

B(7:4)

A(3:0)

B(3:0)

PG2

PG2

PG1

PG0

g(15:12)

p(15:12)

g(11:8)

p(11:8)

g(7:4)

p(7:4)

g(3:0)

p(3:0)

CLA3

CLA2

CLA1

CLA0

g1512

p1512

g118

p118

g74

p74

g30

p30

A(3:0)

B(3:0)

CLA4

g015

p015

Hnh 3-5. S khi chui bit nh dng CLA Lu l s trn l s ca chui bit nh, cn hin thc ha khi cng th cn phi thm cc thnh phn tnh gi tr ca cc bit tng (SUM), ngi c c th t tm hiu hon thin bc ny. 1.4. Thanh ghi Thanh ghi l chui cc phn t nh c ghp vi nhau v l thnh phn khng th thiu ca cc thit k mch dy, c im quan trng nht phn bit thanh ghi vi cc khi t hp l thanh ghi bao gi cng chu s iu khin ca xung nhp ng b, gi tr u ra l gi tr lu trong cc nh ca thanh ghi c gn bng gi tr ca u vo ti cc thi im nht nh (sn dng hoc sn m) theo iu khin xung nhp ng b, nu so snh vi khi t hp th gi tr u ra ca mch t hp thay i tc th ngay sau khi c s thay i ca cc u vo. Thng gp v ph bin nht l cc thanh ghi s dng D-flipflop v lm vic ng b theo sn dng ca xung nhp h thng. Gin sng v biu din ca thanh ghi th hin hnh di y: 125

Hnh 3-6. S khi v gin sng ca thanh ghi Nh quan st trn gin sng, gi tr u ra Q thay i ch ti cc thi im c sn dng ca tn hiu clk, ti thi im gi tr ca Q s c gn bng gi tr u vo D ca thanh ghi. Ti cc thi im khc gi tr ca Q c gi khng i. M t thanh ghi trn VHDL kh n gin nh sau:
------------- register 32-bit ----------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity reg_32 is port( D : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0); CLK : in std_logic; RESET : in std_logic ); end reg_32; -----------------------------------------architecture behavioral of reg_32 is begin reg_p: process (CLK, RESET) begin if RESET = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then Q <= D; end if; end process reg_p; end behavioral; ------------------------------------------

Cu trc 126

if CLK = '1' and CLK'event then quy nh thanh ghi lm vic theo tn hiu sn dng ca xung nhp clk, mt cch vit khc tng ng l if rising_edge(clk) then

1.5. B cng tch ly B cng tch ly l s kt hp gia b cng v thanh ghi, cu trc ca khi ny th hin hnh di y:
clk, reset A B

Sum

REG1

Hnh 3-7. S khi b cng tch ly u ra ca b cng c ni vi u vo ca thanh ghi, cn u ra ca thanh ghi c dn vo cng B ca b cng, sau mi xung nhp ng h gi tr ny c cng thm gi tr cng A v lu li vo thanh ghi. Vi m t ca b cng v thanh ghi trn, m t ca b cng tch ly nh sau:
------------accumullator----------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity accumulator_32 is port( A : in std_logic_vector(31 downto 0); Q : buffer std_logic_vector(31 downto 0); CLK : in std_logic; RESET : in std_logic ); end accumulator_32; ----------------------------------------

127

architecture signal sum32 signal Q_sig signal Cout signal Cin

structure of accumulator_32 is : std_logic_vector(31 downto 0); : std_logic_vector(31 downto 0); : std_logic; : std_logic;

----COMPONENT ADD_32---component adder32 is port ( Cin: std_logic; A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); SUM : out std_logic_vector(31 downto 0); Cout: out std_logic ); end component; ----COMPONENT REG_32---component reg_32 is port ( D : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0); CLK : in std_logic; RESET: in std_logic ); end component; begin Q_sig <= Q; Cin <= '0'; add32: component adder32 port map (Cin, A, Q_sig, sum32, Cout); reg32: component reg_32 port map (sum32, Q, CLK, RESET); end structure;

Kt qu m phng thu c gin sng nh sau:

Hnh 3-8. Kt qu m phng b cng tch ly 128

Sau xung nhp reset gi tr q ca thanh ghi bng 0, sau c mi xung nhp gi tr ny tng thm 17, bng gi tr u vo ca A. Quan st trn gin sng cng d dng nhn thy gi tr ti u ra q ca thanh ghi bao gi cng chm hn gi tr u vo sum ca thanh ghi mt xung nhp clk. 1.6. B m B m l mt trng hp c bit ca b cng tch ly, nu ta cho u vo ca b cng A lun nhn gi tr bng 1 th sau mi xung nhp gi tr trong thanh ghi tng thm 1. Trong trng hp m ngc th cho gi tr ca A bng 1. Gi tr m l gi tr lu trong thanh ghi cn xung m chnh l xung nhp h thng. Cch m t b m trn VHDL nh sau:
------------------Counter---------------library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity counter4 is port ( count :out std_logic_vector( 3 downto 0); enable :in std_logic; clk :in std_logic; -- Dau vao xung m clock reset :in std_logic ); end entity; ---------------------------------------architecture rtl of counter4 is signal cnt :std_logic_vector ( 3 downto 0) := "0000"; begin process (clk, reset) begin if (reset = '1') then cnt <= "0000"; elsif (rising_edge(clk)) then if (enable = '1') then cnt <= cnt + 1; end if; end if; end process; count <= cnt; end architecture; ---------------------------------------

Trong on m trn tn hiu reset c m t ch khng ng b, ngha l khi reset = 1 th ngay lp tc gi tr m cnt b reset v 0. Trong trng 129

hp ng b th gi tr m b reset ch ti sn dng ca xung nhp clk. Ngoi tn hiu reset, b m cn c iu khin bi enable, nu enable =1 th b m lm vic, nu enable = 0 th gi tr m c gi nguyn. B m trn ch m s m nh phn vi K = 2i, cc gi tr m thay i t t 0 n 15 sau li bt u m t 0, trong trng hp mun t Kd bng mt gi tr khc cn thm mt khi t hp lm nhim v so snh gi tr m vi Kd t li gi tr m nh m t di y, b m vi Kd = 10:
--------------Counter set--------------library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---------------------------------------entity counter4_set is port ( count :out std_logic_vector( 3 downto 0); enable :in std_logic; clk :in std_logic; reset :in std_logic ); end entity; ---------------------------------------architecture rtl of counter4_set is signal cnt :std_logic_vector ( 3 downto 0) := "0000"; begin process (clk, reset) begin if (reset = '1') then cnt <= "0000"; elsif (rising_edge(clk)) then if (enable = '1') then if cnt = "1010" then -cnt = 10-reset cnt <= "0000"; else cnt <= cnt + 1; end if; end if; end if; end process; count <= cnt; end architecture; ---------------------------------------

Kt qu m phng ca hai b m nh sau: 130

Hnh 3-9. Kt qu m phng cc b m Cc gi tr m b reset ng b v 0, sau m ln lt t 0 n 8, tn hiu enable sau bng 0, nn gi tr ny gi nguyn, khi enable =1 cc b m tip tc m, b m t li trng thi (count4_set) ch m n 10 ri quay li m t 0, trong khi b m bnh thng (count2) m n 15. 1.7. B dch
Shift_in

Shift_value

SHIFTER

Shift_out

Hnh 3-10. S khi dch B dch l khi logic t hp thc hin ng tc dch chui bt u vo, c tt c 6 php ton dch gm dch tri logic, dch tri s hc, dch phi logic, dch phi s hc, dch trn tri, dch trn phi, chi tit v cc lnh dch ny xem trong mc 5.3 ca chng 2. u vo ca khi dch gm chui nh phn cn phi dch shift_in v gi tr s lng bit cn phi dch shift_value. u ra l gi tr chui nh phn sau khi thc hin dch. Khi vit m cho b dch lu nu dng cc ton t dch ca VHDL th cc chui nh phn dch phi c khai bo di dng bit_vector. V d di y l mt b dch vi u vo 32-bit:
------------- SHIFTER-------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL; USE ieee.Numeric_STD.all;

131

USE ieee.Numeric_BIT.all; ----------------------------------------entity shifter_32 is port( shift_in : in std_logic_vector(31 downto 0); shift_value: in std_logic_vector(4 downto 0); shift_out : out std_logic_vector(31 downto 0) ); end shifter_32; ----------------------------------------architecture behavioral of shifter_32 is signal shi: bit_vector(31 downto 0); signal sho: bit_vector(31 downto 0); signal sa : integer; begin shi <= TO_BITVECTOR(shift_in); sa <= CONV_INTEGER('0' & shift_value); sho <= shi sll sa; shift_out <= TO_STDLOGICVECTOR(sho); end behavioral; --------------------------------------- v d trn v u vo dch shift_in l gi tr 32-bit nn s bt dch ti

a l 31, biu din di dng nh phn cn 5-bit nn shift_value c khai bo l std_logic_vector(4 downto 0). Kt qu m phng nh sau:

Hnh 3-11. Kt qu m phng khi dch t hp Tng ng vi phn m t, gi tr shift_out bng shift_in c dch logic sang bn tri 3-bit. Phng php s dng trc tip ton t dch ca VHDL khng c mt s trnh tng hp h tr, ngha l khng tng hp c mch, trong trng hp khi dch phi c vit chi tit hn. Nhn xt rng phc tp ca khi dch trn nm ch gi tr dch l khng xc nh, nu gi tr dch xc nh th php dch c th thc hin ht sc d dng bng ton t hp &. V d dch chui bit i 4 bit logic sang phi
shift_out = 0000 & shift_in(31 downto 4);

132

T c th xy dng khi dch bng s thut ton n gin nh sau. Gi s ta cn thit k khi dch cho d liu dch shift_in 32 bit, gi tr dch shift_value c biu din l 5 bit. Cc bit ca shift_value t cao nht ti thp nht s c xt. V d, vi bit u tin shift_value(4) c a vo lm tn hiu iu khin cho khi chn knh th nht, nu shift_value(4) = 1 gi tr c chn s l u vo shift_in c dch i 16 bit bi b dch SH16, nu shift_value(4) = 0 th gi tr shift_in c chn, ngha l u vo khng b dch i. S c tip tc nh vy cho n bit cui cng shift_value(0), u ra ca khi chn knh cui cng chnh l gi tr shift_out.
Shift_in

SH16 Shift16 Shift_value(4)

Shift_in4

SH8 Shift8 Shift_value(3)

. .
SH1 Shift1 Shift_value(0)

Shift_in3

.
Shift_in1

Shift_out

Hnh 3-12. S thut ton khi dch n gin 1.8. Thanh ghi dch Tng t nh trng hp ca khi cng tch ly, kt hp khi dch v thanh ghi ta c cu trc ca thanh ghi dch nh hnh sau:

133

clk, reset

WE

Shift_value

Shift_in

SHIFTER

Shift_out MUX

REG1

Hnh 3-13. S thanh ghi dch Thanh ghi c th lm vic hai ch , ch th nht d liu u vo c ly t u vo D, ch th hai l ch dch, khi d liu u vo ca thanh ghi ly t khi dch, u ra ca thanh ghi c gn bng u vo ca khi dch. ch ny d liu s b dch mi xung nhp mt ln. M m t thanh ghi dch nh sau:
---------- SHIFTER_REG module--------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -------------------------------------------entity shift_reg_32 is port( shift_value: in std_logic_vector(4 downto 0); D : in std_logic_vector(31 downto 0); Q : buffer std_logic_vector(31 downto 0); CLK : in std_logic; WE : in std_logic; RESET : in std_logic ); end shift_reg_32; ------------------------------------------architecture structure of shift_reg_32 is signal shift_temp : std_logic_vector(31 downto 0); signal D_temp : std_logic_vector(31 downto 0); ----COMPONENT SHIFTER---component shifter_32 is port ( shift_in : in std_logic_vector(31 downto 0);

134

shift_value : in std_logic_vector(4 downto 0); shift_out : out std_logic_vector(31 downto 0) ); end component; ----COMPONENT REG_32---component reg_32 is port ( D : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0); CLK : in std_logic; RESET: in std_logic ); end component; begin process (WE, shift_temp) begin if WE = '1' then D_temp <= D; else D_temp <= shift_temp; end if; end process; sh32: component shifter_32 port map (Q, shift_value, shift_temp); reg32: component reg_32 port map (D_temp, Q, CLK, RESET); end structure; --------------------------------------------

Kt qu m phng ra nh sau:

Hnh 3-14. Kt qu m phng thanh ghi dch Khi tn hiu WE bng 1 (mc tch cc cao) gi tr thanh ghi c gn bng gi tr ca cng D, su E chuyn v thp, gi tr trong thanh ghi Q c dich sang tri mi ln shift_value = 00101 = 5 bit.

135

2. Cc khi nh
2.1. B nh RAM RAM (Random Access Memory) l mt phn t rt hay c s dng trong thit k cc h thng s. RAM c th phn loi theo s lng cng v cch thc lm vic ng b hay khng ng b ca cc thao tc c v ghi.
CLKA WEA CLK CSA OEA DATA_INA ADDRESSA ADDR_decoder

WE CS OE

MxN-bit

ADDRESS

DATA_OUTA

ADDR_decoder

DATA_IN

CLKB WEB

DATA_OUT

CSB OEB DATA_INB ADDRESSB DATA_OUTB

Single-port RAM

Dual-port RAM

Hnh 3-15. S khi Single-port RAM v Dual-port RAM - Single port RAM l RAM ch c mt knh c v ghi, mt ng vo a ch, cc ng tc c ghi trn knh ny ch c th thc hin ln lt. - Dual-port RAM l RAM c hai knh c ghi ring bit tng ng hai knh a ch, cc knh c ghi ny c th dng chung xung nhp ng b cng c th khng dng chung. i vi Dual-port RAM c th c v ghi ng thi trn hai knh. - Synchronous RAM - RAM ng b l RAM thc hin thao tc c hoc ghi ng b. - Asynchronous RAM- RAM khng ng b l RAM thc hin thao tc c hoc ghi khng ng b, thi gian k t khi c cc tn hiu yu cu c ghi cho ti khi thao tc thc hin xong thun ty l tr t hp. Kt hp c hai c im trn c th to thnh nhiu kiu RAM khc nhau, v d single-port RAM synchronous READ synchronous WRITE ngha l RAM mt cng c ghi ng b, hay Dual-port RAM synchronous WRITE 136

MxN-bit

asynchronous READ l RAM hai cng ghi ng b c khng ng b Khi RAM c cu thnh t hai b phn l khi gii m a ch v dy cc thanh ghi, khi gii m a ch s c a ch v quyt nh s truy cp ti v tr thanh ghi no thc hin thao tc c hoc ghi. Kch thc ca khi RAM thng c k hiu l Mx N-bit trong M l s lng thanh ghi, N l s bit trn 1 thanh ghi. V d 128 x 8 bit l khi RAM gm 128 thanh ghi, mi thanh ghi 8 bit. S bit cn thit cho knh a ch l ADDR_WIDTH = [log2 M], nu M = 128 nn s ADDR_WIDTH = 7. M t VHDL mt khi single-port RAM synchronous READ/WRITE di y:
----------- simple RAM unit -------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -----------------------------------------------entity simple_ram is generic ( DATA_WIDTH :integer := 8; ADDR_WIDTH :integer := 4 ); port( clk :in std_logic; address :in std_logic_vector (ADDR_WIDTH-1 downto 0); data_in :in std_logic_vector (DATA_WIDTH-1 downto 0); data_out :out std_logic_vector (DATA_WIDTH-1 downto 0); cs :in std_logic; -- Chip Select we :in std_logic; -- we = 1 write, we = 0 read oe :in std_logic -- OutputEnable when reading ); end entity; -----------------------------------------------architecture rtl of simple_ram is constant RAM_DEPTH :integer := 2**ADDR_WIDTH; type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); signal mem : RAM (0 to RAM_DEPTH-1); begin WRITTING: process (clk) begin if (rising_edge(clk)) then if (cs = '1' and we = '1') then

137

mem(conv_integer(address)) <= data_in; end if; end if; end process; READING: process (clk) begin if (rising_edge(clk)) then if (cs = '1' and we = '0' and oe = '1') then data_out <= mem(conv_integer(address)); end if; end if; end process; end architecture; -------------------------------------------------

Cc tn hiu iu khin thao tc i vi RAM bao gm CS chip select, vi mi thao tc th u yu cu CS phi mc cao. WE write enable bng 1 nu cn ghi d liu vo RAM. Tn hiu OE output enable bng 1 nu l c d liu t RAM, vi thit k nh vy th WE v OE khng bao gi ng thi bng 1. Hnh di y m phng lm vic ca mt khi RAM.

Hnh 3-16. Kt qu m phng khi RAM Khi tn hiu CS, WE mc tch cc cao, thc hin ng tc ghi vo RAM, mi xung nhp ta ghi mt gi tr bt k, sau gi tr a ch c tng ln mt n v thc hin ghi vo nh k tip. C nh th khi RAM ta s thc 138

hin ghi 8 gi tr 174, 178. 182 202 vo cc thanh ghi c a ch tng ng l 1,2,8. Sau thc hin ng tc c gi tr t RAM, tn hiu CS gi mc cao, WE by gi c mc thp cn OE c y ln mc cao, ln lt thc hin c gi tr t thanh ghi th 7 n thanh ghi th 1, mi ln c ta gim gi tr a ch i mt n v. 2.2. B nh ROM ROM (Read-only Memory) l cu trc nh ch c trong cc gi tr nh c lu c nh khi khi to ROM v khng thay i trong qu trnh s dng, thm ch khi khng c ngun cp gi tr trong ROM vn c gi nguyn.

CS DATA_OUT RE ADDRESS ADDR_decoder

DATA

ROM

Hnh 3-17. S khi ROM Cu trc ca ROM v c bn ging nh ca RAM, c mt khi cha d liu c nh, khng nht thit phi s dng xung nhp CLK, khi gii m a ch. Cc tn hiu u vo l a ch ADDRESS, tn hiu CS chip select, tn hiu cho php c RE read enable. u ra ca khi ROM l gi tr DATA M t VHDL ca khi ROM kh n gin nu so snh vi khi RAM, thng thng khi ROM c m t di dng mt khi t hp, on m di y m t mt khi ROM 16x8-bit
-------------------- Simple ROM unit -----------library ieee; use ieee.std_logic_1164.all; ------------------------------------------------entity simple_rom is

MxN-bit

139

port ( cs :in std_logic; re :in std_logic; address :in std_logic_vector (3 downto 0); data :out std_logic_vector (7 downto 0) ); end entity; ------------------------------------------------architecture behavioral of simple_rom is -- Du lieu trong ROM duoc nap cac gia tri co dinh begin process (re, cs, address) begin if re = '1' and cs = '1' then case (address) is when x"0" => data <= x"00"; when x"1" => data <= x"1a"; when x"2" => data <= x"2f"; when x"3" => data <= x"21"; when x"4" => data <= x"50"; when x"5" => data <= x"ff"; when x"6" => data <= x"11"; when x"7" => data <= x"01"; when x"8" => data <= x"15"; when x"9" => data <= x"01"; when x"A" => data <= x"10"; when x"B" => data <= x"17"; when x"C" => data <= x"50"; when x"D" => data <= x"80"; when x"E" => data <= x"e0"; when x"F" => data <= x"f0"; when others => data <= x"0f"; end case; end if; end process; end architecture; -------------------------------------------------

M phng thao tc c d liu nh gin sng di y:

Hnh 3-18. Kt qu m phng khi ROM

140

 v d trn khi ROM c c ln lt cc nh t th 1 n th 11, thc hin thao tc c th tn hiu CS v RE phi ng thi mc cao. 2.3. B nh FIFO FIFO (First-In-First-Out) l mt khi nh c bit, rt hay ng dng trong cc h thng truyn dn s, dng lm cc khi m trong cc thit b lu tr c im duy nht cng l yu cu khi thit k khi ny l d liu no vo trc th khi c s ra trc. i vi FIFO khng cn khi nim a ch m ch cn cc cng iu khin c v ghi d liu. Ty theo yu cu c th m FIFO c th c thit k bng cc cch khc nhau. S n gin v tng qut nht ca FIFO l s s dng khi RAM ng b hai cng c ghi c lp.
CLK WRITE
CLKA WEA CSA OEA

DATA_IN WRITE_CS

WRITE_FIFO

DATA_INA

ADDRESSA DATA_OUTA

ADDR_decoder

CLKB

READ

WEB CSB

READ_CS

OEB

READ_FIFO
DATA_INB ADDRESSB

DATA_OUT
DATA_OUTB

Dual-port RAM
FIFO_STATE

FIFO_EMPTY

FIFO_FULL

Hnh 3-19. S khi FIFO s dng Dual-port RAM FIFO lm vic ng nh yu cu cn thm 3 khi iu khin sau: 141

MxN-bit

- Khi xc nh trng thi FIFO (FIFO_STATE) to ra hai tn hiu FIFO_FULL, v FIFO_EMPTY thng bo v tnh trng dy hoc rng tng ng ca b nh. to ra cc tn hiu ny s dng mt b m, ban u b m c khi to bng 0. B m ny thay i nh sau: - Nu c thao tc c m khng ghi th gi tr b m gim xung 1. - Nu c thao tc ghi m khng c th gi tr b m tng ln 1. - Nu c thao tc c v ghi th gi tr b m khng thay i. Bng cch - FIFO_EMPTY = 1 nu gi tr b m bng 0 - FIFO_FULL = 1 nu gi tr b m bng gi tr tng s nh ca RAM l 2addr_width 1 - Khi iu khin ghi vo FIFO (WRITE_FIFO) thc hin tin x l cho thao tc ghi d liu trn mt knh c nh trong khi RAM. a ch ca knh ny c khi to bng 0 v c tng thm 1 sau mi ln ghi d liu. Khi gi tr a ch t ti gi tr cao nht bng 2addr_width 1 th c tr li bng 0. Thao tc ghi d liu c thc hin ch khi FIFO cha y (FIFO_FULL = 0) - Khi iu khin c vo FIFO (READ_FIFO) thc hin tin x l cho thao tc c d liu theo knh cn li ca khi RAM. a ch ca knh ny c khi to bng 0 v c tng thm 1 sau mi ln c d liu. Khi gi tr a ch t ti gi tr cao nht bng 2addr_width 1 th c tr li bng 0. Thao tc c d liu c thc hin ch khi FIFO cha y (FIFO_EMPTY = 0). 2.4. B nh LIFO LIFO (Last-In-First-Out) hay cn c gi l STACK cng l mt khi nh tong t nh FIFO nhng yu cu l d liu no vo sau cng th khi c s ra trc. LIFO cng c th c thit k s dng khi RAM ng b hai cng c ghi c lp. iu khin ca LIFO kh n gin v nu c N nh c lu trong LIFO th cc ny s ln lt c lu cc t 0 n N-1, do khi thit k ta ch cn mt b m duy nht tr ti v tr gi tr N. - Nu c thao tc ghi d liu m khng c th d liu c lu vo c a ch N v N tng thm 1. - Nu c thao tc c d liu m khng ghi th d liu c c c a ch N-11 v N gim i 1. - Nu c thao tc c, ghi d liu ng thi th N khng thay i v d liu c chnh l d liu ghi. 142

Trng thi ca LIFO cng c xc nh thng qua gi tr ca N, nu N=0 th LIFO_EMPTY = 1 v nu N = 2addr_width 1 th LIFO_FULL = 1.

3. My trng thi hu hn
FSM (Finish-state machine) my trng thi hu hn l mch c hu hn cc trng thi v hot ng ca mch l s chuyn i c iu kin gia cc trng thi . FSM rt hay c s dng trong cc bi ton s phc tp, thc hin m t ny u tin ngi thit k phi phn tch thng k cc trng thi cn c th ca mch, ti gin v tm iu kin chuyn i gia cc trng thi, v gin chuyn trng thi c dng nh sau.

IDLE

CNT = 8 and RX = 1 CNT_BIT = 8

RX = 0

RECEIVE DATA

START FRAME DETECT

CNT = 8 and RX = 0

Hnh 3-20. S trng thi b thu UART n gin S th hin cch chuyn trng thi ca mt khi nhn d liu t ng truyn UART mt cch n gin nht.
Stop bits 1 0
Start

B0

B1

B2

B3

B4

B5

B6
Parity

1 bit time

Hnh 3-21. Tn hiu vo Rx ca khi thu UART 143

V d d liu u vo ca mt ng truyn UART nh hnh v, khi trng thi khng truyn d liu th khi tn hiu RX mc cao v khi nhn nm trng thi ch IDLE. Khi RX chuyn t mc cao xung mc thp th khi nhn chuyn sang trng thi th hai gi l trng thi d tn hiu start, START_FRAME_DETEC. Bt START c xem l hp l nu nh mc 0 ca RX c gi trong mt khong thi gian lu xc nh, khi nhn s dng mt b m xc nhn s kin ny, nu b m m CNT n 8 m RX bng 0 th s chuyn sang trng thi tip theo l trng thi nhn d liu RECEIVE DATA. Nu CNT = 8 m RX = 1 th y khng phi bit START, khi nhn s quay v trng thi ch IDLE. trng thi nhn d liu th khi ny nhn lin tip mt s lng bit nht nh, thng l 8 bit, khi CNT_BIT = 8, sau s tr v trng thi ch. IDLE. M t VHDL ca khi FSM trn nh sau:
------------ Simply UART FSM -----------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity fsm_receiver is generic (n: positive := 8); port( cnt_bit : in std_logic_vector (3 downto 0); cnt8 : in std_logic_vector (2 downto 0); Rx : in std_logic; CLK : in std_logic; reset : in std_logic; receiver_state: inout std_logic_vector (1 downto 0) ); end fsm_receiver; -----------------------------------------architecture behavioral of fsm_receiver is constant Idle : std_logic_vector (1 downto 0) := "00"; constant start_frame_detect : std_logic_vector (1 downto 0) := "01"; constant receive_data :std_logic_vector (1 downto 0) := "11"; begin receiving: process (CLK, RESET) begin if RESET = '1' then receiver_state <= Idle;

144

elsif clk = '1' and clk'event then case receiver_state is when Idle => if Rx = '0' then receiver_state <= start_frame_detect; end if; when start_frame_detect => if cnt8 = "111" then if Rx = '0' then receiver_state <= receive_data; else receiver_state <= Idle; end if; end if; when receive_data => if cnt_bit = "0111" then receiver_state <= Idle; end if; when others => receiver_state <= Idle; end case; end if; end process receiving; end behavioral; ------------------------------------------

Vi m t nh trn trng thi ca mch c lu bng hai bt ca thanh ghi receiver_state, trng thi ca mch s thay i ng b vi xung nhp h thng CLK. (*) Code trn dng minh ha cch vit FSM, trn thc t khi iu khin trng thi b nhn UART phc tp hn do cn phn iu khin trng thi cc b m, thanh ghi

4. Khi nhn s nguyn

Php nhn cng l mt php ton rt hay s dng trong tnh ton x l, vic thit k khi nhn phc tp v cn nhiu ti nguyn hn khi cng, trn thc t mt s dng vi x l n gin php nhn c thc hin thng qua khi cng bng phn mm. Trong cc vi x l hin i th khi nhn c h tr phn cng hon ton. Di y ta s ln lt nghin cu hai thut ton c bn ca khi nhn. Cc thut ton khc c th tham kho trong cc ti liu [11], [12]

145

4.1. Khi nhn s nguyn khng du dng phng php cng dch Khi nhn dng thut ton cng dch (shift-add multiplier), xt php nhn hai s 4 bit khng du nh sau: x . a = x0.a+2.x1.a+ 22x2.a+23.x3.a (3.4) vi x = x3x2x1x0, b = b3b2b1b0
0101 0111 ------0101 0101 0101 0000 ------0100011 - s b nhn - s nhn - tch ring multiplicand multiplier partial products

- kt qu nhn product

Theo s trn th s b nhn (multiplicand) s c nhn ln lt vi cc bit t thp n cao ca s nhn (multiplier), kt qu ca php nhn ny bng s b nhn 0101 nu bit nhn tng ng bng 1, v bng 0000 nu nh bit nhn bng 0, nh vy bn cht l thc hin hm AND ca bit nhn vi 4 bit ca s b nhn. thu c cc tch ring (partial products) ta phi dch cc kt qu nhn ln lt sang tri vi bt nhn th 0 l 0 bit, th 1 l 1 bt, th 2 l hai bit v th 3 l 3 bt. Kt qu nhn (product) thu c sau khi thc hin php cng cho 4 tch ring. S trn gip chng ta hiu php nhn c thc hin nh th no nhng khi xy dng phn cng da trn s ny c mt nhc im l cc tch ring b dch bi cc gi tr dch khc nhau. Nu xy dng khi nhn thun ty l khi t hp th nhn hai s 4 bit cn 4 khi dch v 3 khi cng 8 bit, nu s lng bit ca cc nhn t tng ln th ti nguyn phn cng tng ln rt nhiu v khng ph hp vi thc t. Nu xy dng khi nhn theo dng mch t hp kt hp thanh ghi dch v b cng tch ly th cn thm mt b m m gi tr dch, vic ny lm cho khi nhn tr nn phc tp. Gii php n gin ha cu trc ca khi nhn c th s dng mt trong hai s thut ton cng dch tri v cng dch phi. Vi s cng dch phi php nhn c thc hin theo cng thc sau: x . a = x0.a+2.x1.a+ 22x2.a+23.x3.a = x0.a+2.(x1.a+ 2(x2.a+2.x3.a) (3.5) 146

V d s cho thut ton cng dch phi:

---------------------a 0 1 0 1 x 0 1 1 1 ---------------------P(0) 0 0 0 0 2P(0) 0 0 0 0 0 +x0.a 0 1 0 1 ---------------------2p(1) 0 0 1 0 1 P(1) 0 0 1 0 1 +x1.a 0 1 0 1 ---------------------2p(2) 0 0 1 1 1 1 P(2) 0 0 1 1 1 1 +x2.a 0 1 0 1 ---------------------2p(3) 0 1 0 0 0 1 1 P(3) 0 1 0 0 0 1 1 +x3.a 0 0 0 0 ---------------------P(4) 0 0 1 0 0 0 1 1 P 0 0 1 0 0 0 1 1

Vi s ny th s nhn c dch t tri qua phi, tc l s b nhn s c nhn ln lt vi cc bit t thp n cao x0, x1, x2, x3. Cc gi tr p(i) l gi tr tch ly ca cc tch ring. Gi tr p(0) c khi to bng 0. P(1) = p(0) + x0.a, y l php cng 4 bit v p(1) cho ra kt qu 5 bit trong bit th 5 l bit nh, ring trng hp p(1) th bit nh ny chc chn bng 0 do p(0) = 0. Kt qu p(2) c 6 bit s bng kt qu php cng ca x1.a dch sang phi 1 bt v cng vi gi tr p(1). Nhn xt rng bit cui cng ca x1.a khi dch sang tri lun bng 0 do vy hay v phi dch x1.a sang phi 1 bit ta xem nh p(1) b dch sang tri 1 bit, ngha l phi ly 4 bit cao ca p(1) cng vi x1.a. Kt qu thu c ca php cng ny l mt s 5 bit em hp vi bit cui cng ca p(1) s thu c p(2) l mt s 6 bit. Tip tc nh vy thay v dch x2.a ta li xem nh p(2) dch sang tri 1 bit v cng 4 bit cao ca p(2) vi x2.a, kt qu php cng hp vi 2 bit sau ca p(2) thu c p(3) l mt s 7 bit. Lm nh vy vi tch ring cui cng thu c kt qu (product) l mt s 8 bit. Nh vy trn s trn ta lun cng 4 bt cao ca kt qu tch ly vi kt qu nhn. 147

S hin thc ha khi nhn dng thut ton cng dch phi cho K bit s dng thanh ghi dch v b cng tch ly nh sau:

K-bit

Multiplicand

K-1 bit

Multiplier

product
K bit K-1 bit

0
SHIFT_REG MUX K-bit

lower

opa

opb

k bit

Cout

SUM

Hnh 3-22. S hin thc ha thut ton nhn cng dch phi cho hai s K-bit Khi cng c mt hng t c nh K-bit l u vo tch ring (opb), tnh cc tch ring s dng mt khi chn knh MUX k-bit, khi ny chn gia gi tr s b nhn (multiplicand) v 0 ph thuc vo bit tng ng ca s nhn (multiplier) l 1 hay 0. a ln lt cc bit ca s nhn vo cng iu khin cho khi chn ny th gi tr ca s nhn c lu trong mt thanh ghi dch sang phi mi xung nhp 1 bit. u vo th hai ca b cng ly t k bit cao ca thanh ghi 2k-bit. Thanh ghi ny trong qua trnh lm vic lu tr kt qu tch ly ca cc tch ring. u vo ca thanh ghi ny bao gm K+1 bit cao, ghp bi bit nh (Cout) v K-bit (Sum) t b cng, cn K-1 bit thp (lower) ly t bt th K-1 n 1 lu trong thanh ghi xung nhp trc xung nhp trc , ni mt cch khc, y l thanh ghi c phn K-1 bit thp hot ng trong ch dch sang phi 1 bit, cn K+1 bit cao lm vic ch np song song. Php nhn c thc hin sau K xung nhp, kt qu nhn lu trong thanh ghi cng dch 2k-bit. Vi s cng dch tri php nhn c thc hin theo cng thc sau: x . a = x0.a+2.x1.a+ 22x2.a+23.x3.a 148

= ((x3.a.2 + x2.a ).2+ x1.a ).2+x0.a V d s cho thut ton cng dch tri:
---------------------a 0 1 0 1 x 0 1 1 1 ---------------------P(0) 0 0 0 0 2 p(0) 0 0 0 0 0 +x3.a 0 0 0 0 ---------------------p(1) 0 0 0 0 0 2P(1) 0 0 0 0 0 0 +x2.a 0 1 0 1 ---------------------2p(2) 0 0 0 1 0 1 P(2) 0 0 0 1 0 1 0 +x2.a 0 1 0 1 ---------------------2p(3) 0 0 0 1 1 1 1 P(2) 0 0 0 1 1 1 1 0 +x3.a 0 1 0 1 --------------------P 0 0 1 0 0 0 1 1

(3.6)

S cng dch tri khc s cng dch phi ch s nhn c dch dn sang tri, cc tch ring c tnh ln lt t tri qua phi, tc l t bit cao n bit thp, kt qu tch ly khi dch sang tri trc khi cng vi kt qu nhn ca bit k tip. Kt qu tch ly ban u c khi to bng p(0) = 0 v thc hin dch sang tri 1 bit trc khi cng vi x3.a thu c p(1) l mt s 5 bit. P(1) tip tc c dch tri 1 bit v cng vi x2.a thu c p(2) l mt s 6 bt. Lm tng t nh vy cho ti cui ta thu c p l mt s 8 bit. Nh vy cng ging nh s cng dch phi s cng dch tri s ch cn dng mt khi dch c nh cho kt qu trung gian, im khc bit l php cng s ny lun cng cc bit thp vi nhau, bit nh ca php cng ny s nh hng ti gi tr cc bit cao nn buc phi s dng mt khi cng 2Kbit thc hin cng. S hin thc thut ton cng dch tri trn phn cng nh sau:

149

Multiplicand 2K bit Multiplier 0 SHIFT_REG MUX Kbit SHIFT LEFT

product

0000000000

K-bit

2K bit

2k bit
Hnh 3-23. S hin thc ha thut ton nhn cng dch tri cho hai s K-bit i vi s dng thut ton cng dch tri, khi dch cho s nhn phi l khi dch phi mi xung nhp mt bit do cc tch ring c tnh ln lt t tri qua phi. Khi cng s lun l khi cng 2-K bit, mc d hng t th nht (opa) c K bit cao bng K-bit t u ra MUX, K bit thp ca opa lun bng 0. Thanh ghi kt qu trung gian l thanh ghi 2K bit, Gi tr trong thanh ghi c dch sang tri 1 bt bng khi dch trc khi i vo khi cng qua cng opb. Gi tr cng SUM c lu tr li vo thanh ghi trong xung nhp k tip 4.2. Khi nhn s nguyn c du S nguyn c du trong my tnh c biu din di dng b 2 (2scomplements) theo gi tr ca s biu din bng mt chui bit nh phn c tnh theo cng thc: xn-1 xn-2 x1 x0 = -2n-1xn-1 +2n-2xn-2 + + 2x1 + x0 (3.7) trong xn-1xn-2x1x0 l biu din di dng nh phn.

150

Cng thc trn ng cho c s m ln s dng, nu s l m th bit c trng s ln nht xn-1 bng 1 v ngc li. Trong h thng biu din ny nh ngha: B 1 ca s xn-1xn-2x1x0 l s nhn bi cc bit ny nhng ly o B 2 ca s xn-1xn-2x1x0 l s b 1 ca s cng thm 1. Mt tnh cht quan trng ca s b 2 l s b hai ca mt s A bng s i ca s , hay ni cch khc b2 (A) + A = 0. Tnh cht ny cho php ta xy dng khi nhn s c du bng cch n gin nht l a cc s v dng biu din khng m, hay tr tuyt i ca cc s v nhn vi nhau s dng mt trong cc s cng dch tri hay cng dch phi trn. Ring bit du ca kt qu c tnh ring. Nu nh hai s nhn v s b nhn khc du a v dng biu din ng ca kt qu cn ly b 2 ca kt qu php nhn khng du. Cch thc hin trn kh n gin tuy vy i hi nhiu ti nguyn logic cng nh tng tr ca khi nhn do phi b xung cc khi tnh b 2 vo u v cui chui tnh ton. Ta li c nhn xt rng nu biu din gi tr a di dng s b hai bng k bit, gi tr ny c biu din tng ng bng k+m bit bng cch in vo m bt m rng bn tri gi tr du (bit th k-1) ca s , ton b k bit bn phi gi nguyn. ng tc b xung cc du nh th c gi l m rng c du (signedextend) V d
-4 = (1100)4
bit

= (11111100)8-bit

Vi nhn xt ny c th thc hin mt vi iu chnh nh trong s nhn cng dch s ny cng ng vi s c du. Yu cu l khi m rng cc kt qu tch ly cn phi m rng theo kiu c du (signed-extend), c th hn nu bt m rng trng hp nhn s khng du l bit nh th trong trng hp ny l bit du. Yu cu khc l khi s nhn l s m th khi nhn vi bit du (bit cao nht) th theo cng thc (2) kt qu thu c l s i ca s b nhn hay l s b 2 ca s b nhn. Nhc im ca phng php ny l phi thit k hai khi nhn ring cho s c du v khng du. Xt v d v php nhn ca hai s c du 4 bit dng thut ton cng dch phi.
---------------------a 1 1 0 1 B 2 a = 0011 (a = -3) x 1 1 0 0 x = -4

151

---------------------P(0) 0 0 0 0 +x0.a 0 0 0 0 ---------------------2p(1) 0 0 0 0 0 v p(1) >= 0 P(1) 0 0 0 0 0 +x1.a 0 0 0 0 ---------------------2p(2) 0 0 0 0 0 0 v p(2) >= 0 P(2) 0 0 0 0 0 0 +x2.a 1 1 0 1 ---------------------2p(3) 1 1 1 0 1 0 0 v p(2) < 0 P(3) 1 1 1 0 1 0 0 -x3.a 0 0 1 1 ---------------------P(4) 0 0 0 0 1 1 0 0 v p(2) >=0 P 0 0 0 0 1 1 0 0 = +12 chn thm 0 vo tri

chn thm 0 vo tri

chn thm 1 vo tri

chn thm 0 vo tri

S hin thc khi nhn c du trn phn cng nh sau:

SHIFTER _ SIGNED EXTEND Multiplicand 2s complement product 2K bit Multiplier 0 SHIFT_REG MUX

Hnh 3-24. S hin thc ha thut ton nhn s c du cho 2 s K-bit V c bn s ny khng khc nhiu so vi s nhn khng du, im khc bit l y trc khi kt qu tch ly c lu vo thanh ghi trung gian th c dch v chn cc bit du m rng theo quy tc i vi s c u khi SHIFTER SIGNED-EXTEND. V MUX thc hin la chn gia 3 gi tr l s b nhn, 0 v s i ca n. S i ca s b nhn c chn nu bit nhn l bit du v bit ny bng 1. 152

Mt phng php khc thc hin php nhn vi s c du biu din di dng b 2 l s dng m ha Booth. y bc u ta s xt m ha Booth c s 2 (Radix 2 Booth encoding). hiu v m ha Booth quay tr li vi cng thc (3.7) tnh gi tr cho s biu din dng b 2. Cng thc ny c th c bin i nh sau: xn-1 xn-2 x1 x0 = -2n-1xn-1 +2n-2xn-2 + + 2x1 + x0 = -2n-1xn-1 + 2n-1xn-2 -2n-2xn-2 + + 22 x1 2 x1 + 2 x0 x0 + 0 = 2n-1 (- xn-1 + xn-2) +2n-2 (-xn-2 + xn-3 )+ + 2(-x1 + x0) + (-x0 + 0) (3.8) T xy dng bng m nh sau, cp hai bit lin tip xi+1, xi s c thay bng gi tr bi = (-xi+1 + xi) vi i = -1, n-2, v x-1 = 0. Cng thc trn c vit thnh: xn-1 xn-2 x1 x0 = -2n-1xn-1 +2n-2xn-2 + + 2x1 + x0 = 2n-1 bn-1 +2n-2 bn-2 + + 2b1 + b0 (3.9) Cng thc ny c dng tng t cng thc cho s nguyn khng du. im khc bit duy nht l bi c m ha theo bng sau: Bng 3-2 M ha Booth c s 2 xi+1 xi Radix-2 booth encoding bi 0 0 0 0 1 1 1 0 -1 1 1 0 Theo bng m trn hai bit nh phn tng ng s c m ha bng cc gi tr 0, 1, -1. V d chui bit v m ha Booth c s hai tng ng:
2s complemnt 1 1 1 0 0 1 0 1 1 0 1 0 0 1(0) Radix-2 booth 0 0-1 0 1-1 1 0-1 1-1 0 1-1

thc hin php nhn s c du u tin s m ha s nhn di dng m Booth, khi thc hin php nhn nu bit nhn l 0, 1 ta vn lm bnh thng, nu bit nhn l -1 th kt qu nhn bng s b hai ca s b nhn. C th p dng m ha Booth cho c s cng dch tri v cng dch phi v h tr thao tc m rng c du.

153

S trn c th sa i mt cht n vn ng vi c php nhn vi s khng du, khi ta b xung thm bit 0 vo bn tri ca s b nhn v chui Booth s di hn mt bit.
2s complemnt (0) 1 1 1 0 0 1 0 1 1 0 1 0 0 1(0) Radix-2 Booth (1) 0 0-1 0 1-1 1 0-1 1-1 0 1-1

V d y v php nhn c du s dng m ha Booth c s 2 nh sau:

---------------------a 1 1 0 1 B 2 a = 0 0 1 1 (a = -3) x 0 1 1 1 x = + 7 b 1 0 0-1 Radix 2 booth encoding of x ---------------------P(0) 0 0 0 0 +b0.a 0 0 1 1 ---------------------2p(1) 0 0 0 1 1 P(1) 0 0 0 1 1 +b1.a 0 0 0 0 ---------------------2p(2) 0 0 0 0 1 1 P(2) 0 0 0 0 1 1 +x2.a 0 0 0 0 ---------------------2p(2) 0 0 0 0 0 1 1 P(3) 0 0 0 0 0 1 1 +x3.a 1 1 0 1 ---------------------2p(3) 1 1 0 1 0 1 1 P 1 1 1 0 1 0 1 1 m rng vi bit du 0

m rng vi bit du 0

m rng vi bit du 0

m rng vi bit du 1 = -21

S ca khi nhn c du dng m ha Booth c s 2

154

-multiplicand

Multiplicand Sign 0 Multiplier & 0 MUX3-1 Kbit K bit K-1 bit 1bit product RADIX 2 BOOTH ENCODING K bit K-1 bit

SHIFT_REG

k+1-bit

Hnh 3-25. S khi nhn dng thut ton nhn dng m ha Booth c s 2 S nhn c chn thm mt bit 0 vo tn cng bn phi v c a dn vo khi m ha BOOTH, khi ny s a ra kt qu m ha v y kt qu ny ra khi chn knh MUX3_1, khi ny chn gia cc gi tr multiplicand, multiplicand v 0 tng ng php nhn vi 1, -1, 0 v a vo khi cng. Hng t th hai ca khi cng ly t K bit cao thanh ghi dch 2*K bit. Thanh ghi ny hot ng khng khc g thanh ghi trong s cng dch phi, im khc cng cn lu l cc bit m rng trong cc kt qu tch ly khng phi l bit nh nh trong trng hp s c du m phi l bit du, ni mt cch khc php dch sang phi y l php dch s hc ch khng phi php dch logic. 4.3. Khi nhn dng m ha Booth c s 4 M ha Booth c s 2 khng c ng dng thc t nhng l c s gip hiu cc dng m ha Booth cao hn. Trong n lc tng tc cho php nhn trong phn cng mt trong nhng phng php l thc hin nhn khng phi tng bit ca s nhn m nhn vi mt nhm bit cng mt lc. Khi nhn theo c s 4 (Radix-4 multiplier) s dng s nhn vi cp 2 bit, vi cp 2 bit th c th c 4 gi tr 0, 1, 2, 3. D dng nhn thy cc php nhn mt s vi 0 bng 0 vi 1 bng chnh n, nhn vi 2 l php dch sang phi 1 bit, tuy vy nhn vi 3 l mt php ton m thc hin khng d dng nu so vi php nhn vi 0, 1, 2 do phi dng ti b cng. Tuy vy khi nhn vn c th tng tc theo s ny bng cch tnh trc s b nhn vi 3.

155

Nhm trnh vic nhn vi 3, s nhn theo c s 4 trn c ci tin bng m ha Booth (radix-4 Booth encoding), m ha ny gip vic tnh cc tch ring tr nn d dng hn, c th cng thc (3.7)biu din gi tr ca s b 2 c th bin i v dng sau: x2n-1x2n-2x1x0 = -22n-1x2n-1 +22n-2x2n-2 + + 2x1 + x0 = -22n-22.x2n-1 + 22n-2x2n-2 +22n-2x2n-3 - 22n-42.x2n-3 + 22n-4x2n-4 +22n-4x2n-5 + - 2.2. x1 + 2 x0 + 2. 0 = 22n-2 (- 2x2n-1 + x2n-2 + x2n-3) +22n-4 (-2x2n-3 + x2n-4 + x2n-5)+ + (-2x1 + x0 + 0) (3.10) Trong trng hp tng s bit biu din khng phi l chn (2n) th thu c biu din nh trn rt n gin l b xung thm mt bit du tn cng bn tri do vic b xung thm bit du khng lm thay i gi tr ca s biu din. Nh vy nu ta xy dng bng m ha theo cng thc bi = (- 2x2i+1 + x2i + x2i-1) vi i = 0, 1, 2, n-1 (3.11) ta s m ha 2n bit ca s nhn bng [n] gi tr theo bng m sau: Bng 3-3 Bng m ha Booth c s 4 xi+1 xi xi-1 Radix-4 Booth encoding 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 2 1 0 0 -2 1 0 1 -1 1 1 0 -1 1 1 1 0 V d y v php nhn c du s dng m ha Booth c s 4 nh sau:
----------------------a 1 1 0 1 0 1 11) x 0 1 1 0 1 0 (0) x = + 26 b 2 -1 -2 Radix 4 booth encoding of x ---------------------4P(0) 0 0 0 0 0 0 0 P(0) 0 0 0 0 0 0 0 +b0.a 0 0 1 0 1 1 0 ---------------------B 2 a = 0 0 0 1 0 1 1(a = -

156

4p(1) 0 0 0 0 1 0 1 1 0 m rng vi bit du 0 0 P(1) 0 0 0 0 1 0 1 1 0 +b1.a 0 0 0 1 0 1 1 ---------------------4p(2) 0 0 0 0 1 0 0 0 0 1 0 m rng vi bit du 0 0 P(2) 0 0 0 0 1 0 0 0 0 1 0 +b2.a 1 1 0 1 0 1 0 ----------------------------4p(3) 1 1 1 1 0 1 1 1 0 0 0 1 0 m rng vi bit du 1 1 P 1 1 1 1 0 1 1 1 0 0 0 1 0 = -286

S hin thc trn phn cng ca thut ton nhn dng m ha Booth c s 4 ging ht s ca php nhn s c du dng m ha Booth c s 2. u ra ca khi m ha c s 4 l cc chui 3 bt c dch t gi tr ca Multiplier sau khi thm 1 bit 0 vo bn phi, mi ln dch hai bt. T 3 bt ny ta s chn mt trong 5 gi tr gm 0, multiplicand, - multiplicand, -2 multiplican v +2 multiplicand bi khi chn knh MUX5_1, u ra ca khi ny c gi vo khi cng K+1 bit. L do khi cng y l khi cng K+1 bit l do gi tr 2.multiplicand phi biu din bng K+1 bit. Phn cn li khng khc g s php nhn dng thut ton cng dch phi. im khc l thanh ghi cha kt qu s dch sang phi khng phi 1 bit m dch 2 bit ng thi v php dch y l php dch s hc, ngha l 2 v tr bit b trng i s in gi tr du hin ti ca s b dch. B cng y buc phi dng b cng K+1 bit v u vo c th nhn gi tr 2.multiplicand biu din di dng K+1 bit. Kt qa cui cng cng cha trong thanh ghi tch ly 2K+1 bit tuy vy chng ta ch ly 2K bit thp ca thanh ghi ny l , l do l hai bit c trng s cao nht ca thanh ghi ny ging nhau nn vic lc b bt 1 bit tn cng bn tri i khng lm thay i gi tr ca chui s biu din.

157

-multiplicand

2*multiplicand

-2*multiplicand

Multiplicand Sign Sign 0 Multiplier &0 MUX5-1 Kbit K+1 bit RADIX 4 BOOTH ENCODING K-2 bit 2bit product K+1 bit K-2 bit

SHIFT_REG

k+1-bit

Hnh 3-26. S khi nhn dng thut ton nhn dng m ha Booth c s 4 Bng cch tng t c th xy dng s nhn vi m ha Booth cho cc c s cao hn.

5. Khi chia s nguyn

Khi chia l mt khi s hc kh phc tp nu so snh vi khi cng hay khi nhn, trn thc t cc vi iu khin v vi x l trc y thng khng h tr php chia cp phn cng m c thc hin bng phn mm. cc vi x l hin i th php chia c h tr hon ton, tuy vy nu so snh v tc thc hin th php chia vn chm hn nhiu so vi cc php ton khc, hay ngay c i vi cc php ton trn s thc. Thng thng php nhn vi s nguyn 32 bit dng 4 xung nhp Clk, cn php chia dng ti 35 xung nhp. Di y ta s nghin cu cc thut ton c bn thc hin php chia trn phn cng, y cha phi l nhng thut ton nhanh nht ca php chia nhng l l nhng thut ton c s ngi c nghin cu cc thut ton khc. K hiu z : s b chia (dividend) d: s chia (divisor) q: thng s (quotient) s: s d (remainder) S thc hin ca php chia s nh phn tng t nh s thc hin php chia i vi s thp phn. V d di y minh ha mt php chia s 8 bit cho s 4 bit khng c du.
----------------------z 1 1 0 0 0 1 0 1 2^4d 1 1 1 0 z d = 197 = 14

158

---------------------s(0) 1 1 0 0 0 1 0 1 2s(0) 1 1 0 0 0 1 0 1 -q3.2^4d 1 1 1 0 ---------------------s(1) 1 0 1 0 1 0 1 2s(1) 1 0 1 0 1 0 1 -q2.2^4d 1 1 1 0 ---------------------s(2) 0 1 1 1 0 1 2s(2) 0 1 1 1 0 1 -q1.2^4d 1 1 1 0 ----------------------------s(3) 0 0 0 0 1 2s(3) 0 0 0 0 1 -q.0^4d 0 0 0 0 ----------------------------s = 0 0 0 1 = 1

q3 = 1

q2 = 1

q1 = 1

q0 = 0 q = 1 1 1 0 = 14

Php chia c thc hin bng cch dch s chia sang bn phi 4 bit v tr bit c trng s cao nht trng vi bt c trng s cao nht ca s b chia. Tip khi to s d bng s b chia, nu s ny ln hn 24.d th bit th 4 tng ng ca thng s bng q3 = 1, Trong trng hp ngc li q3 = 0. Thc hin php tr s d hin tai cho q3.24.d. Kt qu php tr c dch sang phi 1 bit thu c s d trung gian mi v lp li qu trnh trn. Cho ti bc th 4, s d bc cui cng thu c l s d cn tm. Thng s c ghp bi cc bit t cao n thp t bc 1 n 4. 5.1. Khi chia dng s khi phc phn d Khi chia trn phn cng c xy dng trn c s nguyn l nh trn, im khc bit l php tr c thay tng ng bng php cng vi s b hai, v cn thc hin php tr trc xc nh gi tr ca q4, q3, q2, q1, q0. S sau c gi l s chia c khi phc phn d v sau mi php tr nu kt qu l m th phn d s c khi phc li thnh gi tr c v dch thm mt bit trc khi thc hin tr tip. V d mt php chia thc hin theo s nh sau:
----------------------z 1 1 1 0 0 1 0 1 2^4d 1 1 1 0 ---------------------z d = 197 = 14

159

s(0) 0 1 1 0 0 1 0 1 2s(0) 0 1 1 0 0 0 1 0 1 +(-2^4d) 1 0 0 1 0 ---------------------s(0) (0) 1 1 1 1 0 1 0 1 2s(0) 1 1 0 0 0 1 0 1 +(-2^4d) 1 0 0 1 0 ---------------------s(1) (0) 1 0 1 0 1 0 1 2s(1) 1 0 1 0 1 0 1 +(-2^4d) 1 0 0 1 0 ---------------------s(2) (0) 0 1 1 1 0 1 2s(2) 0 1 1 1 0 1 +(-2^4d) 1 0 0 1 0 ----------------------------s(3) (0) 0 0 0 0 1 2s(3) 0 0 0 0 1 +(-2^4d) 1 0 0 1 0 ----------------------------s(4) = (0) 0 0 1 1 = 1 2s(4)= 0 0 0 1 s = 2s(4) = 0 0 0 1 = 1

kt qu m q4 = 0 phc hi. kt qu dng q3 = 1

kt qu dng q2 = 1

kt qu dng q1 = 1

kt qu m q0 = 0 tr v gi tr d c q = 0 1 1 1 0 = 14

(*) Trong v d trn s trong ngoc l bit nh ca php cng cc s 4 bit bn tay phi ch khng phi l kt qu cng ca ct cc bt c trng s cao nht.

S phn chi tit phn cng c thit k nh sau:

160

K+1-bit(quotient) MUX Sel (SHIFT LEFT)

K-bit divisor remainder K-bit

K-bit

K-bit (SHIFT LEFT)

2s complement opb opa

SUB =1

k-bit

Cout

SUM

Hnh 3-27. S khi chia c khi phc phn d Gi k l s bit ca s chia v thng s. Thanh ghi dch Remainder 2k+1bit trong s trn c s dng lu tr gi tr d trung gian. Thanh ghi ny c khi to gi tr bng gi tr ca s b chia hp vi mt bit 0 tn cng bn tri v mi xung nhp c dch sang bn tri mt bit. Bit nh c bit th 2k+1 lun lu tr bt c trng s cao nht ca phn d. B cng K-bit c s dng thc hin php tr K bit bng cch cng phn K bit cao ca thanh ghi s d k t bit th 2 t bn tri vi b hai ca s chia. V d l s khng du nn khi i sang s b hai phi dng K+1 bit biu din. Cng v d l s nguyn khng m nn khi i sang s b 2 bit cao nht thu c lun bng 1. (v d d = 1011, b 1 d = 10100, b 2 d = 10101). Li dng tnh cht vic cng K bit cao ca s b chia vi s b 2 ca d ng l phi s dng b cng K+1 bit nhng thc t ch cn dng b cng K bit. Bit du ca kt qu khng cn tnh m c th thu c thng qua gi tr ca bit nh Cout v gi tr bt c trng s cao nht ca phn d trong thanh ghi. Nu gi tr bit c trng s cao nht ca phn d ny bng 1 th d nhin phn d ln hn s chia do thc t ta ang tr mt s 5 bit thc s cho 1 s 4 bit, cn nu bit ny bng 0, nhng php tr a ra bit nh Cout = 1, tng ng kt qu l s dng th phn d cng 161

ln hn hoc bng s chia. Trong c hai trng hp ny qi =1, trong cc trng hp khc qi =0, l l do ti sao trc thanh ghi quotient t mt cng logic OR hai u vo. Thanh ghi dch quotient k+1-bit c s dng lu ln lt cc bit qk, qk-1, q0 ca thng s q, thanh ghi ny cng c dch sang phi mi ln mt bit. Khi hin thc s ny trn VHDL c th b qua, thay vo K+1 bit thng s c th c y vo K+1 bit thp ca thanh ghi phn d 2K+1 bit m khng nh hng ti chc nng lm vic ca c khi. 5.2. Khi chia dng s khng khi phc phn d Khi phn tch v s thut ton chia c phc hi s d, c mt nhn xt l khng nht thit phi thc hin thao tc phc hi gi tr phn d, v trn c s c th xy dng s khi chia khng khi phc hi phn d. V mt ton hc, gi s gi tr ti thanh ghi cha phn d l s, bc tip theo ta s thc hin s 24d, php tr ny cho ra kt qu m, tc l kt qu khng mong mun, nu nh vi s khi phc phn d bc tip theo ta s tr li gi tr u, dch sang phi 1 bit v thc hin php tr 2.s -24d. Tuy vy nu lu rng 2.s 24d = 2(s-24d) + 24d. Ta c th thay i s i mt cht m chc nng ca mch vn khng thay i, bc trn ta vn lu gi tr sai vo thanh ghi, bc sau ta s vn dch gi tr trong thanh ghi sang phi 1 bit nhng thay v cng vi s b 2 ca 24d ta s cng trc tip vi 24d, vic m bo kt qu ca bc tip theo vn ng. Quy lut chung l: Nu gi tr trong thanh ghi l m -> thc hin cng vi 24d. Nu gi tr trong thanh ghi l m -> thc hin tr vi 24d. V d mt php chia theo s khng phc hi phn d nh sau:
-----------------------------z 1 0 0 0 0 1 0 1 z 2^4d 1 1 1 0 d ------------------------------d s(0) 0 |0 0 1 0 0 0 0 1 0 1 2s(0) 0 |0 1 0 0 0|0 1 0 1 +(-2^4d) 1 |1 0 0 1 0| -----------------------------s(1) (0)|1 1 0 1 0|0 1 0 1 kt qu 2s(1) 1 |1 0 1 0 0|1 0 1 +(+2^4d) 0 |0 1 1 1 0 -----------------------------s(2) (1)|0 0 0 1 0 1 0 1 kt qu = 133 = +14 = 01110 = -14 = 10010

m q4 = 0

dng q3 = 1

162

2s(2) 0 |0 0 1 0 1 0 1 +(-2^4d) 1 |1 0 0 1 0 -----------------------------s(3) (0)|1 0 1 1 1 0 1 kt qu m q2 = 0 2s(3) 1 |0 1 1 1 0 1 +(+2^4d) 0 |0 1 1 1 0 -----------------------------s(4) (0)|1 1 1 0 0 1 kt qu m q1 = 0 2s(4) 1 |1 1 0 0 1 +(+2^4d) 0 |0 1 1 1 0 -----------------------------S(5) = (1)|0 0 1 1 1 kt qu dng q0 = 1 s = 2s(5) = 0 1 1 1 = 7 q = 0 1 0 0 1 = 9 - bit nm trong du ngoc l bit nh ca khi cng 4 bit. - Cc bit tn cng bn tri du | l bit du ca cc ton hng, lit k ch lm r gi tr cng, cc bit ny lun l 1,0 hoc 0,1.

Vi quy lut nh trn c th d dng suy ra rng hai ton t ca php cng trn lun ngc du, do vy bit du ca cc hng t ny lun tri ngc nhau. Li dng c im ta c th lc bt gi tr bit du m vn thu c ng du hiu ln hn hay nh hn 0 ca kt qu cng. Nu php cng c nh (Cout = 1) th kt qu l dng cn php cng khng c nh (Cout = 0) kt qu l m. Cng v th mc d gi tr phn d biu din l s c du nhng khi dch sang tri thu c 2.s th phi s dng thm mt bit, bit ny thc cht n i nhng vn m bo xc nh c du ca kt qu theo quy lut trn. Khi chia s dng s khi phc phn d d hiu, tuy vy nu nghin cu k v tr logic ta s thy tn ng d liu di nht (trong 1 xung nhp ng b) phi tri qua ba thao tc: thao tc dch thanh ghi, thao tc cng b cng, v thao tc lu gi tr vo thanh ghi Quotient v thanh ghi Remainder. Thao tc cui c thc hin sau khi bit nh Cout ca chui cng xc nh. Nu chp nhn lun lu tr gi tr kt qu php tr vo thanh ghi, khng quan tm d l gi tr ng hay sai, b qua thao tc phc hi gi tr phn d th ng thi s b s l thuc vo Cout v tc ca b chia c th c ci thin thm mt lp tr. V mt ti nguyn th khng c s thay i nhiu v thay cho thao tc phc hi m thc cht l khi chn knh K bit th phi thc hin chn hng t cho khi cng gia d v b 2 ca d cng l mt khi chn knh K bit. S phn chi tit phn cng c thit k nh sau: 163

qoutient K+1-bit divisor (SHIFT LEFT)

K-bit 2s complement remainder K-bit

K-bit

K-bit (SHIFT LEFT)

MUX

opb

opa Cout 1-bit

k+1-bit
SUM

Hnh 3-28. S khi chia khng phc phn d S v c bn ging nh s khi chia thc hin bng thut ton khng phc hi phn d, im khc bit duy nht l b chn knh c chuyn xung v tr trc b cng chn gi tr u vo tng ng cho khi ny, vic chn gi tr cng cng nh thc hin php ton cng hay tr trong b cng c quyt nh bi bit Cout c lm tr 1 xung nhp, ngha l Cout ca ln cng trc. 5.3. Khi chia s nguyn c du Hai s trn ch ng cho php chia i vi s khng du, thc hin php chia i vi s c du cng ging nh trng hp ca khi nhn, php chia c thc hin bng cch chuyn ton b s chia v s b chia thnh hai phn gi tr tuyt i v du, phn gi tr tuyt i c th tin hnh chia theo mt trong hai s trn, phn du c tnh ton n gin bng mt cng XOR, kt qu thu c li chuyn ngc li thnh biu din di dng s b 2. Di y ta s tm hiu mt thut ton khc nhanh hn v tit kim hn thc hin php chia c du. tng ca thut ton ny xut pht t s chia khng phc hi phn d. Mc ch ca php chia l i tm biu din sau: z = qk-1 . 2k-1 .d + qk-2 .2k-2 .d + +q0.d + s.

164

Trong z l s b chia, d l s chia, s l phn d cn thng s chnh l gi tr nh phn ca qk-1qk-2q0. Qi nhn gi tr 0 hay 1 tngm ng bc th i phn d c cng thm hoc tr i tng ng gi tr d tng ng vi gi tr phn d l dng hay m. Mt cch tng qut cho php chia: mc ch ca cc s trn l lm gim dn tr tuyt i ca phn d bng cch tr nu n cng du vi s chia v cng nu n khc du vi s chia, qu trnh ny kt thc khi c hai iu kin sau c tha mn: 1. Phn d s cng du vi z 2. Tr tuyt i ca s nh hn tr tuyt i ca d. Cng tng qut ha t s chia khng phc hi phn d, nu ta m ha qi khc i nh sau: pi = 1 nu s(i) v d cng du pi = -1 nu s(i) v d khc du. Khi ng thc biu din trn z = pk-1 . 2k-1 .d + pk-2 .2k-2 .d + +p0.d + s, vn ng, ch khc tp gi tr ca qi l {-1, 1}. Trong trng hp trin khai z nh trn nhng cui cng thu c s khc du vi z th phi tin hnh iu chnh s bng cch cng thm hay tr i d, ng thi cng thm hoc bt i mt vo gi tr ca q. p c th thu c thng qua s chia khng phc hi phn d, vn cn li l phi chuyn q v dng biu din thng thng ca s b 2. C th chng minh rng nu ta lm ln lt cc bc sau th c th a q = qk-1qk-2q0

v dng biu din nh phn p = pkpk-1p0 vi pi = {0,1} v gi tr p = q. - Chuyn tt c cc pi gi tr -1 thnh 0. Gi gi tr ny l r = rk1rk-2r0.

C th d dng chng minh qi = 2ri 1.

Ly o ca rk-1, thm 1 vo cui r, gi tr thu c di dng b 2 chnh l thng s q = ( k-1rk-2r01)2s complement

k-1rk-2r01)2s complement

C th chng minh nh sau:

q=(

= - (1-pk-1). 2k + 1 + = -(2k -1) +2. = =p

165

V d mt php chia hai s c du, kt qu cui cng khng phi iu chnh:

-----------------------------z 1 1 0 1 0 1 0 1 2^4d 0 1 1 0 z = -43 d = 6 = 0 1 1 0 -d = -6 = 1 0 1 0

-----------------------------s(0) 1 1 1 0 1 0 1 0 1 2s(0) 1 1 1 0 1 0 1 0 1 d,s khc du q4 = -1 +(2^4d) 0 0 1 1 0 thc hin cng ----------------------------s(1) (1) 0 0 1 1 0 1 0 1 d,s cng du q3 = +1 2s(1) 0 0 1 1 0 1 0 1 thc hin tr +(-2^4d) 1 1 0 1 0 ----------------------------s(2) (1) 0 0 0 0 1 0 1 d,s cng du q2 = +1 2s(2) 0 0 0 0 1 0 1 thc hin tr +(+2^4d) 1 1 0 1 0 ----------------------------s(3) (0) 1 0 1 1 0 1 d,s khc du q1 = -1 2s(3) 1 0 1 1 0 1 thc hin cng +(+2^4d) 0 0 1 1 0 ----------------------------S(4) = (0) 1 1 0 0 1 s, q khc du q0 = -1 2S(4) 1 1 0 0 1 thc hin cng +(-2^4d) 0 0 1 1 0 ----------------------------S = 1 1 1 1 1 = - 1 s, z cng du khng cn iu chnh s d p = -1 +1 +1 -1 -1 r = 0 1 1 0 0 q = (1 1 1 0 0 1)2s complement = -7 - bit nm trong du ngoc l bit nh ca khi cng 4 bit. - Cc bit tn cng bn tri l bit du ca cc ton hng, lit k ch lm r gi tr cng, cc bit ny lun l 1,0 hoc 0,1. -43 = +6((-1)24 + (+1)23 +(+1)22 +(-1)21 +(-1)20 ) + (1) ------------------------------

V d sau th hin trng hp cn phi iu chnh thng s v s d:

z 2^4d 1 1 0 1 1 0 0 1 0 1 1 0 z = -39 d = 6 = 0 1 1 0 -d = -6 = 1 0 1 0

166

-----------------------------s(0) 1 1 1 0 1 1 0 0 1 2s(0) 1 1 1 0 1 1 0 0 1 d,s khc du q4 = -1 +(2^4d) 0 0 1 1 0 thc hin cng ----------------------------s(1) (1) 0 0 1 1 1 0 0 1 d,s cng du q3 = +1 2s(1) 0 0 1 1 1 0 0 1 thc hin tr +(-2^4d) 1 1 0 1 0 ----------------------------s(2) (1) 0 0 0 1 0 0 1 d,s cng du q2 = +1 2s(2) 0 0 0 1 0 0 1 thc hin tr +(+2^4d) 1 1 0 1 0 ----------------------------s(3) (0) 1 1 0 0 0 1 d,s khc du q1 = -1 2s(3) 1 1 0 0 0 1 thc hin cng +(+2^4d) 0 0 1 1 0 ----------------------------S(4) = (0) 1 1 1 0 1 s,d khc du q0 = -1 2S(4) 1 1 1 0 1 thc hin cng +(-2^4d) 0 0 1 1 0 ----------------------------S = (1) 0 0 1 1 = 3 s, z khc du, iu chnh -d 1 1 0 1 0 (0) 1 1 0 1 = -3 p = -1 +1 +1 -1 -1 r = 0 1 1 0 0 q = (1 1 1 0 0 1)2s complement = -7, do trn c iu chnh s d bng cch tr d nn phi tng q thm 1 q = q + 1 = -6. - bit nm trong du ngoc l bit nh ca khi cng 4 bit. - Cc bit tn cng bn tri du | l bit du ca cc ton hng, lit k ch lm r gi tr cng, cc bit ny lun l 1,0 hoc 0,1. -39 = +6((-1)24 + (+1)23 +(+1)22 +(-1)21 +(-1)20 + 1) + (-3)

S phn chi tit phn cng c thit k nh sau:

167

divisor

K-bit 2s complement K-bit

K-bit

K-bit

MUX opb opa K+1-bit

k+1-bit
SUM

quotient Correct quotient

Hnh 3.29. S khi chia c du S trn c pht trin t s chia khng phc hi phn d, im khc bit l tn hiu la chn vic thc hin php cng hay php tr tng ng c thc hin bng mt cng XNOR vi hai u vo l gi tr du ca phn d hin ti v du ca s chia, nu hai gi tr ny khc nhau th gi tr pi tng ng bng -1, trn thc t ta khng biu din gi tr -1 m quy c biu din l s 0, nu du hai s nh nhau th gi tr pi bng 1. Cc gi tr ny c y dn vo thanh ghi k-bit, gi tr r = rk-1rk-2r0 thu c ti thanh ghi ny sau k xung nhp cha phi l gi tr thng cn tm, tm ng gi tr thng ta phi c mt khi thc hin vic chuyn i r (Correct quotient) v gi tr q theo quy tc trnh by trn. Khi ny ngoi nhim v bin i r v q cn c th thc hin iu chnh gi tr cui cng bng cch cng hoc tr i 1 n v trong trng hp phn d thao tc cui cng thu c khng cng du vi s b chia. Lu rng vi biu din bng chui {-1, 1} th gi tr ca q lun l s l, v vy trong trng hp kt qu thng s l chn th vic iu chnh li thng s bc cui cng l khng th trnh khi.

168

6. Cc khi lm vic vi s thc

Trong k thut tnh ton c hai dng nh dng c bn biu din s thc bng chui cc bt nh phn l dng biu din s thc du phy tnh (fixpoint number) v s thc du phy ng (floating-point number). 6.1. S thc du phy tnh S nguyn l mt dng c bit ca s thc du phy tnh khi m du phy nm v tr 0, hay phn thp phn lun bng 0, khi vic thay i v tr du phy sang phi k bit ta thu c gi tr ca s mi bng s c nhn vi 2-k l mt gi tr khng nguyn. Mt im na cn ch l tnh cht trn vn ng nu nh s nguyn ca chng ta l s c du biu din di dng s b 2. Nh vy nh dng s thc du phy tnh ch l mt tng qut ca nh dng s nguyn chng ta hay dng. Cc tham s ca nh dng ny gm Fixed(s, w, f) trong s = 1 nu l biu din s c du, trong trng hp s c du gi tr c biu din di dng b 2, w l s lng bit dng cho biu din phn nguyn v f l s lng bit dng biu din cho phn thp phn. Khi gi tr mt s thc khng du c tnh ton theo cng thc sau

(3.12) V d s biu din bng s thc 8 bit khng du vi w = 4, f = 4 s l

1,5 = 0001 1000 3,75 = 0011 1100 = 24.2-4 = 60 . 2
-4

Gi tr ca mt s thc c du vi bit du l s c tnh bng

(3.13) V d s biu din bng s thc 8 bit khng du vi w = 4, f = 4 s l

+ 1,5 - 4,25 = 0001 1000 = 1011 1100 = 24.2-4 = -68.2-4

Nh trnh by trn s nguyn l mt trng hp ring ca s thc du phy tnh, ton b cc khi logic s hc lm vic vi s nguyn nh trnh by cc phn trn u c th s dng cho cc khi tnh ton trn thc du 169

phy tnh. y l mt li th rt ln ca nh dng ny, tuy vy nhc im rt ln ca s thc du phy tnh l min biu din s nh v phn gii, hay cn gi l chnh xc khng cao. Chng ta s tm hiu v s thc du phy ng trc khi a ra so snh thy c nhc im ny. 6.2. S thc du phy ng S thc du phy ng c ng dng thc t trong my tnh v cc h x l. m bo cho cc thit b phn cng cng nh cc chng trnh phn mm c th trao i d liu v lm vic vi nhau mt cch chnh xc khi thc hin x l tnh ton trn s thc dng ny, t chc IEEE nghin cu v xy dng cc chun lin quan n s thc du phy ng (IEEE 754) cng nh quy nh v cc php ton trn . Trong khun kh gio trnh s gii thiu v nh dng, cc php tnh v mt s quy tc lm trn c bn ca s thc dng ny, trn c s s xy dng thut ton cho cc khi thc hin php ton s thc. 6.2.1. Chun s thc ANSI/IEEE-754 nh dng chung ca s thc du phy ng th hin hnh sau:
FRACTION(Nm-bit) EXPONENT(NE-bit) S

Ek

E1 E0

Mn

M1

M0

Hnh 3-30. nh dng s thc du phy ng Gi tr ca s biu din tnh bng cng thc: (3.14) Trong : Bt trng s cao nht S biu din du, nu S = 1 th du m, S=0 th du dng. K bit tip theo EkEk-1E1 biu din s m (exponent), Cc bit ny biu din cc gi tr khng du t 0 n 2k - 1. Chun s thc quy nh gi tr thc biu din thc cht bng e = exponent (2k-1-1), gi tr (2k-1-1) gi l dch ca s m (exponent bias) c ngha l min gi tr ca s m t -(2k-1-1) n +(2k-1-2) N bt cui cng dng biu din phn thp phn FRACTION vi gi tr tng ng l m = 1, mnmn-1m1 , Vi s thc chun th s 1 trong cng thc ny 170

cng khng c biu din trc tip m ngm nh lun lun c nn cn gi l bit n. Cc s biu din theo quy tc trn c gi l cc s chun (Normalized), ngoi ra cn quy nh cc s thuc dng khng chun v cc gi tr c bit bao gm:
Denormalized : Zero 0 : Infinity : Not a Number NaN: EXPONENT EXPONENT EXPONENT EXPONENT + + + + BIAS BIAS BIAS BIAS = = = = 0, FRACTION <> 0 0, FRACTION = 0 2k-1-1,FRACTION = 0 2k-1-1,FRACTION <> 0

S khng chun (Denormalized) l nhng s c s m thc t bng 0 (EXPONENT + BIAS =0) v s thp phn biu din di dng m = 0, mnmn1m1, ngha l s 1 n c thay bng s 0, s khng chun c s dng biu din cc s c tr tuyt i nh hn tr tuyt i s b nht trn min s chun l Chun s thc 32bit (Float) v 64-bit (Double) l hai nh dng c s dng ph bin trong cc IC tnh ton c nh ngha bi IEEE-754 1985.

31

30

23

22

IEEE - 754 Single Precission

63

62

52

51

IEEE - 754 Double Precission Hnh 3-31. Chun s thc ANSI/ IEEE - 754 Bng thng k thuc tnh ca nh dng s thc du phy ng theo chun ANSI/IEEE 754 1985 Bng 3-4 Cc tham s ca s thc du phy ng chun IEEE 754 Thuc tnh Single Precission (Float) Double Precission ( Double) Tng s bit 32 64 Phn thp phn 23 + 1 n 52 + 1 n Phn s m 8 11 -23 Min thp phn [1, 2- 2 ] [1, 2- 2-52] 171

 lch s m (BIAS) Min s m S khng chun (Denormalized) Zero (0)

127 [-127, +127] EXPONENT = 0, FRACTION 0 EXPONENT = 0, FRACTION = 0 EXPONENT = FRACTION = 0

1023 [-1023, +1023] EXPONENT = FRACTION 0 EXPONENT = FRACTION = 0 255, EXPONENT = 1023, FRACTION = 0 EXPONENT = 1023, FRACTION 0 EXPONENT (12046) 2-1022 (2- 2-23).21023 21024

0, 0,

V cng (Infinity ()) Khng l s (Not a EXPONENT = 255, Number NaN) FRACTION 0 S chun EXPONENT (1254) (Normalized) Gi tr ln nht 2-126 Gi tr nh nht (2- 2-23).2127 2128

6.2.3. So snh min biu din v phn gii ca cc dng biu din Bng sau th hin cc tham s ca cc dng s thc: Bng 3-5 phn gii v min biu din ca cc nh dng s thc Dng biu Gi tr dng ln Gi tr Gi tr Gi tr m nh phn din nht dng m ln nht gii cao nh nht nht nht 23 -8 -8 -8 23 -8 Fix(1, 23, +2 + 1-2 +2 +2 -(2 + 1-2 ) 2-8 8) Float32 +2126.(2-2-8) +2-127 -2-127 -2128.(2-2-8) -2-127 Float64 +21022.(2-2-52) +2-128 -2-128 -21023.(2-2-52) -2-1023 T bng trn c th thy u im ca biu din s thc theo nh dng du phy ng, th nht l min biu din ln hn rt nhiu, nu so snh cng biu din bng 32 bit th min biu din ca s thc du phy ng ln gp ~2102 ln, cn v phn gii cao nht th gp 2119 ln. Tuy vy lu rng s lng t hp cc gi tr khc nhau biu din bng N-bit l c nh v vy s thc du phy ng c min biu din ln nhng phn gii cc min gi tr khng ng u, cao min gi tr tuyt i nh v thp min gi tr tuyt i ln. Khc vi s thc du phy tnh c phn b u nhng phn gii thp. 172

overflow

normalized

denormalized

normalized

overflow

- 0
Floating point

overflow

normalized

overflow

- 0
Fix point

Hnh 3-32.Phn b ca cc dng biu din Trn thc t hu ht cc thit b tnh ton s s dng nh dng du phy ng c chun ha bi IEEE (ANSI/IEEE-754), nh s chun ha m d liu tnh ton c th c trao i s dng ln nhau m khng gy ra sai st. Vi cc h thng tnh ton c chng phc v cho nhng bi ton hoc lp bi ton c th th ngi thit k thng t nh ngha li dng biu din ca s thc nhm ti u ha thit k v tt c cc mt gm chnh xc, hiu sut s dng phn cng v tc . V nhc im, s thc du phy ng l cc khi thit k thc hin php ton trn s dng ny phc tp hn rt nhiu vi cc khi lm vic vi s thc du phy tnh. Ngoi ra vic kim sot sai s cho cc php ton bng s thc dy phy ng thng phc tp hn do s phn b khng u trn trc s, trnh t tnh ton mt cng thc c th dn n nhng sai s rt khc bit. Trc khi i vo thit k cc khi tnh ton ta s xem xt v cc ch lm trn h tr bi s thc du phy ng v nh hng ca n ti sai s. 6.3. Ch lm trn trong s thc du phy ng. Lm trn (Rounding) l chuyn gi tr biu din dng chnh xc hn v dng khng chnh xc hn nhng c th biu din ng nh dng quy nh ca s ang xt. Gi tr mun biu din dng chnh xc hn cn phi s dng s 173

lng bit ln hn so vi bnh thng. Lm trn thng l ng tc cui cng trong chui cc ng tc thc hin php tnh vi s thc du phy ng. C nhiu phng php lm trn s, khng mt tnh tng qut c th xem chui s u vo l mt s thp phn c dng: X,Y = xn-1xn-2x0,y0y1..ym Chui s u ra l mt s nguyn c dng: Z = zn-1zn-2z0 Phng php n gin nht l b ton b phn gi tr sau du phy. Nu vi s biu din dng du-gi tr th vic ct b phn tha s mi c gi tr tuyt i nh hn hoc bng s c. Vi s gi tr dng th s sau lm trn nh hn s trc lm trn, cn vi s m th ngc li, chnh v vy phng php ny c gi l lm trn hng ti 0 (Round toward 0).

Hnh 3-33.Lm trn hng ti 0 Vi s biu din dng b 2 th c th ch ra rng vic ct b phn tha lun lm cho gi tr s sau lm trn nh hn gi tr s trc lm trn, chnh v vy phng php lm trn ny c gi l lm trn hng ti -(round toward -). Hnh v bn th hin c ch lm trn ny

174

Hnh 3-34.Lm trn hng ti - Nu nh s lm trn c lm trn ln gi tr cao hn, thay v lm trn vi gi tr thp hn th ta c kiu lm trn ti +(round toward +). Vi kiu ny th gi tr sau lm trn lun ln hn gi tr trc lm trn.

Hnh 3-35.Lm trn hng ti + Ba kiu lm trn trn hoc lm trn ln cn trn hoc lm trn xung cn di nn khng mang li hiu qu ti u v mt sai s. Kiu lm trn c h tr ngm nh trong chun ANSI/IEEE 754 l lm trn ti gi tr gn nht, vi cch 175

t vn nh trn th gi tr lm trn s c ly l s nguyn cn trn hay di ty thuc vo khong cch gia s cn lm trn ti cc cn ny. Cn no gn hn th s c lm trn ti. Trong trng hp gi tr cn lm trn nm chnh gia th s phi quy nh thm l s lm trn ln hoc xung.

(a)

(b)

Hnh 3-36. Lm trn ti s gn nht chn (a) v Lm trn ti s gn nht l (b) Nu quy nh rng trong trng hp gi tr cn lm trn nm chnh gia v d 1,50 ta lun lm trn ln 2,0 khi gi tr sai s trung bnh c chiu hng lun dng. Chnh v vy trn thc t c thm mt quy nh na l vic lm trn ln hay xung ca s chnh gia ph thuc vo vic phn nguyn hin ti l chn hay l, nu phn nguyn hin ti l chn th ta lun lm trn xung cn di (ti gi tr chn). Cch lm trn ny gi l lm trn ti s gn nht chn (Round to nearest even), vi cch ny th xc xut lm trn ti cn trn v di l bng nhau v v vy trung bnh sai s bng 0. Tng t ta cng c kiu lm trn ti s gn nht l (Round to nearest odd). V l thuyt th hai phng php ny c hiu qu tng ng nhau nhng trn thc t kiu lm trn ngm nh trong chun ANSI/IEEE754 l lm trn ti s gn nht chn. 6.4. Php cng s thc du phy ng thc hin php cng ca hai s thc A, B vi cc gi tr nh sau.

176

Trong ea, eb l cc gi tr biu din cn ea-BIAS, eb-BIAS l cc gi tr thc t ca s m. Mt trong nhng bc u tin l quy i hai s v cng mt s m chung, nu xt v mt ton hc c th thc hin quy i v s m chung ea hoc eb u cho kt qu nh nhau nu nh khi cng m bo s chnh xc tuyt i . Tuy vy trn thc t php cng s thc theo chun xt trn a phn khng c kt qu tuyt i chnh xc do nhng gii hn v thc t phn cng. L thuyt khi ch ra rng quy i hai s v biu din ca s m ca s ln hn bao gi cng mang li chnh xc cao hn cho php ton (do gim thiu nh hng ca thao tc lm trn ln chnh xc ca kt qu). Gi s nh ea>eb khi B c vit li thnh: (3.15) Tip theo tin hnh cng phn thp phn ca hai s (3.16) Vi l thuyt c bn trn khi cng c hin thc ha bng nhiu s khc nhau ty theo mc ch ca thit k nhng v c bn chng u c cc khi chnh c biu din hnh sau:

177

Operands unpack sa
PHASE 1

sb

ea

ea

ma

mb

Compare_exponent

REG1

Sel
PHASE 2

MUX

Correct _exponent shift_value shifter

REG2

ma3
Sign logic PHASE 3

mb3

Significand_adder

Adjust exponent

Nomalize

REG3

Rounding and selective component

Adjust exponent PHASE 4

Nomalize

result pack

REG_OUT

Hnh 3-37. S khi cng s thc du phy ng d theo di ta xem cc s ang xt c kiu s thc 32 bit, phn thp phn n= 23 bit, ea, eb s biu din bng 8 bit, BIAS = 127. Cc hng t (operands) c phn tch thnh cc thnh phn gm du (sa, sb), s m (ea, eb) v phn thp phn (ma, mb). s trnh by trn cc thanh ghi pipelined l khng bt buc v khng nh hng ti chc nng ca mch. 178

Khi cng u tin c chc nng tm gi tr chnh lch gia gi tr s m, ng thi xc nh ton t no c gi tr b hn s b dch sang phi bc tip theo. Khi ny lun thc hin php tr hai s khng du 8 bit cho nhau. Kt qu thu c ea-eb nu l s m th a<b v phi lm mt bc na l tr li ng gi tr tuyt i cho kt qu, thao tc ny c thc hin bi khi Correct exponent, (thc cht l ly b 2 ca ea-eb). Trong trng hp ea-eb>=0 th a>=b, kt qu ea-eb c gi nguyn. Khi mux v shifter c nhim v chn ng hng t b hn v dch v bn phi mt s lng bit bng |ea-eb|. chnh l php nhn vi 2-(ea-eb) nh trnh by trn. y ch lu mt im l mc d kt qu ea-eb l mt s 8 bit tuy vy khi dch ch thc hin dch nu gi tr tuyt i ea-eb 26, l do l v phn thp phn c biu din bng 23 bit, nu tnh thm cc bit cn thit cho qu trnh lm trn l 3 bit na l 26, trong trng hp gi tr ny ln hn 26 th kt qu dch lun bng 0. Sigfinicand_adder l khi cng cho phn thp phn, u vo ca khi cng l cc hng t c quy chnh v cng mt s m, s lng bit ph thuc vo gi tr tuyt i |ea-eb| tuy vy cng nh i vi trng hp khi dch trn, do gii hn ca nh dng s thc hin ti ch h tr 23 bit cho phn thp phn nn thc t ch cn khi cng 25 bit nu tnh c bit n v bit du cho php cng s biu din dng b 2. Cc bit tha ra pha bn phi s c iu chnh ph hp cho cc kiu lm trn tng ng.
M(n-1) M(n-2) ... M1 M0 Round Sticky

Hnh 3-38. Dng kt qu cn lm trn y ta xt kiu lm trn ph bin l lm trn ti s gn nht chn vi cch lm trn ny ta s phi quan tm ti cc bit c bit gm bit cui cng M0 ca phn biu din xc nh tnh chn l, bt u tin ngoi phn biu din l bit lm trn Round, nu bit ny bng 0 s ang xt c lm trn xung cn di (phn tha b ct b), nu bt ny bng 1 th phi quan tm xem phn cn li c bng 0 hay khng. Phn cn li c i din bng 1 bit duy nht gi l Sticky bit ny thu c bng php OR logic i vi tt cc cc bt tha th 2 tr i. Nu gi tr ny khc 0 s ang xt c lm trn ln cn trn (cng thm 1). Nu nh phn ny bng 0 th s ang xt c lm trn ti gi tr chn gn nht, ngha l ph thuc gi tr M0, nu bng 1 th c lm trn ln, nu l 0 th lm trn xung. 179

Quay tr li vi khi cng s thc ang xt yu cu i vi kt qu php cng s phi c cc bit nh sau:
Cout M 23 M 22 M 21 M 20 M 19 M 18 M 17 M 16 ... M2 M1 M0 G R S

Hnh 3-39. Dng kt qu cng ca phn thp phn trc lm trn Ngoi phn kt qu ca php cng t bit Cout n M0 gm 25 bit, thc hin lm trn trong thnh phn kt qu cn phi thm 3 bit vi tn gi l Guard bit (G), Round bit (R) v Sticky bit (S). Trc khi lm trn kt qu (Rounding) cn phi thc hin chun ha gi tr thu c trong khi Normalize, khi ny a gi tr v dng biu din cn thit 1, xx..xxx chnh v vy cn phi xc nh xem s 1 u tin xut hin trong chui trn t bn tri sang nm v tr no. V tr bit ny c th d dng xc nh bng mt khi m ha u tin. Trng hp thc hin cng hai gi tr ma, mb khi s 1 u tin bn tri c th nm v tr ca Cout hoc M23. Nu kt qu thu c khng c bt nh Cout, v bit M23 = 1, khi theo quy tc lm trn ta s quan tm ti gi tr ca M0 xc nh tnh chn l, G c vai tr nh bit lm trn, cn R, S c vai tr nh nhau cung cp thng tin v phn cn li c khc 0 hay khng. Trn thc t S thu c t php OR ca tt cc cc bit tha ra t v tr S v bn phi. Nu kt qu thu c c nh th khi lm trn s quan tm ti gi tr ca M1 xt tnh chn l, M0 lm trn, cc bt G, R, S cung cp thng tin cho phn cn li c khc 0 hay khng. i vi trng hp php tr ma cho mb th c 3 kh nng cho v tr ca bit 1 u tin t tri sang. Trng hp |ea-eb| > 1 th c th xy ra trng hp th nht l bit ny ri vo v tr M23 nh xt trn. Trng hp th hai l s 1 ri vo v tr M22 (c th d dng ch ra l s 1 khng th nm v tr thp hn). Khi tnh chn l ca s lm trn quy nh bi G (chnh v th G c gi l Guard bit), bit lm trn l R cn S c vai tr xc nh cho gi tr phn cn li. Cn trng hp khi s 1 u tin nm v tr nh hn 22 th ch xy ra khi |ea- eb| 1 khi th cc bit R, S ng thi bng 0, vic lm trn l khng cn thit. Sau khi thc hin lm trn m thc cht l quyt nh xem c cng thm 1 hay khng vo kt qu cng phn thp phn. Vic cng thm d 1 n v c th 180

gy ra trn kt qu v lm hng nh dng chun ca s (s 1 u tin dch sang tri mt bit). l khi cng thm 1 vo s c dng 1, 11111. + 0, 00001 = 10,00000. Do sau khi lm trn buc phi c thm mt khi chun ha th hai iu chnh kt qu thu c khi cn thit. R rng trng hp trn ny l duy nht v vi ln iu chnh ny th thao tc lm trn khng cn thc hin li. Nh vy thao tc chun ha v lm trn tuy khng phc tp nhng nhiu trng hp c bit m ngi thit k phi tnh n. Sau mi thao tc chun ha th cn phi thc hin iu chnh s m tng hay gim ph thuc vo v tr u tin ca s 1 t bn tri kt qu cng. Vic iu chnh s m tuy n gin nhng khi thit k mt cch y cn tnh n cc kh nng trn s, ngha l s m sau iu chnh nm ngoi min biu din, ngi thit k c th t tm hiu thm cc trng hp ny khi lm hin thc ha s . 6.5. Php nhn s thc du phy ng Ngc li vi cc khi tnh ton trn s nguyn, khi nhn trn s thc du phy ng n gin nu so snh vi khi cng. Xt hai s sau:

Trong ea, eb l cc gi tr biu din cn ea-BIAS, eb-BIAS l cc gi tr thc t ca s m. Khi kt qu php nhn. A.B = (3.17) S khi nhn s dng s thc du phy ng c trnh by hnh di y:

181

Operands unpack sa sb ea ea ma mb

PHASE 1

Exponent_adder

Significand Multiplier

REG1

Adjust exponent

Nomalize

Rounding PHASE 4

Adjust exponent

Nomalize

result pack

REG_OUT

Hnh 3-40. S khi nhn s thc du phy ng Cng cho mc ch tin theo di ta xt trng hp php nhn vi s thc 32-bit theo nh dng ANSI/IEEE 754. Ti khi cng s m, sau khi cng cc gi tr ea, eb ta thu c gi tr ea + eb. Cn gi tr thc t l ea+eb -2 * BIAS nh cng thc trn, ngha l gi tr cn biu din l ea+eb 2*BIAS + BIAS = ea+eb BIAS. Chnh v vy thu c gi tr biu din ca s m ta cn tr kt qu cng i BIAS. tr 127 th lu BIAS = 127 = 11111111 = 28-1, do vy ta s cho 1 vo bit Cin ca b cng sau tr i 28 = 100000000, php tr ny thc t rt 182

n gin v cc bit thp u bng 0, do vy ta tit kim c mt b cng dng iu chnh BIAS.
M 48 M 47 M 46 ... M 25 M 24 R S

Hnh 3-41. Dng kt qu nhn ca phn thp phn Khi nhn phn thp phn (Significand multiplier)thc cht l khi nhn s nguyn 24-bit x 24-bit trong trng hp ny. Ti a ta thu c s 48 bit, v lu rng cui cng kt qu ny c thu gn ch cn 24 bit chnh v vy chng ta c th thit k mt khi nhn khng hon chnh thu c gi tr 24 bit cn thit. Do bit 1 u tin bn tri sang ca kt qu nhn lun ri vo v tr th M48 hoc M47 nn trong trng hp ny khng cn thit phi c bit Guard khi lm trn, nh vy ch cn 2 bit thm vo phn biu din l bit R (Round) v bit S (Sticky). Ngi thit k cn ch cc c im trn c mt khi nhn ti u v mt ti nguyn logic cng nh tc thc thi. Phn di ca khi nhn s thc khng khc g khi cng, im khc bit l khi iu chnh s m n gin hn v ch phi iu chnh nhiu nht 1 n v trong c hai trng hp trc v sau khi lm trn. 6.6. Php chia s thc du phy ng Xt hai s sau:

Trong ea, eb l cc gi tr biu din cn ea-BIAS, eb-BIAS l cc gi tr thc t ca s m. Khi kt qu php chia: A.B = (3.18) Mt im lu duy nht l khi thc hin chia phn gi tr kt qu thu c cng phi c dng chun 1. . c kt qu nh vy phi m rng thm phn gi tr thp phn ca A thm ti thiu n+1 bit: Trn thc t ta s phi thc hin php chia s nguyn khng du nh sau:

(3.19) 183

Kt qu php chia thu c thng s l mt s q =

r.

Trong cc bit qi l kt qu chia, cn r thm vo i din cho phn s d . r = 0 nu s d bng 0 cn r =1 nu s d khc 0, bit ny ch c ngha khi thc hin lm trn.
q 22 q 21 q 20 ... q1 q0 q-1 (R) q-2 (S) R (S)

Hnh 3-42. Dng kt qu chia ca phn thp phn Tip theo s thc hin lm trn q thu c Mc. Mc = Round ( r) Khng mt tng qut v d theo di xt trng hp s thc du phy ng theo chun IEEE/ANSI 754 vi n = 23, kt qu chia th hin hnh 3.42. C th d dng ch ra rng do c im ca s chia v s b chia u l cc s 24 bit v 48 bit vi bit u tin bng 1 nn trong kt thng q s 1 xut hin u tin t bn tri s s ri vo hoc q22 hoc q21 . V vy phc v cho vic lm trn thng s cn thit phi tnh thm 2 bit sau bit cui cng q0 l q-1 v q-2. Trng hp bit 1 ri vo bit q24 th bit q0 quyt nh chn l, q-1 l bit lm trn, q2, r i din cho phn cn li. Trng hp bit 1 ri vo v tr q23 th bt quyt nh chn l l q-1 bit lm trn l q-2 cn r i din cho phn cn li. Khi chia phn thp phn Significand division l khi phc tp v chim nhiu ti nguyn logic nht. Tuy vy kt qu ca php chia ny l 24 bit v vic hiu chnh thu c dng biu din chun kh n gin. Phn di ca khi chia cng bao gm hai khi chun ha v lm trn nh trong trng hp khi nhn. Ti khi tr s m, sau khi tr cc gi tr ea, eb ta thu c gi tr ea eb, gi tr ny trng vi gi tr thc t. thu c gi tr biu din ca s m ta cn cng kt qu vi BIAS. Cng nh i vi trng hp php nhn, ta s thm bit Cin = 1 vo khi tr sau thc hin cng vi gi tr 128 ti u v mt ti nguyn. S khi chia s dng s thc du phy ng c trnh by hnh di y:

184

Operands unpack sa sb ea ea ma mb

PHASE 1

Exponent_adder

Significand Division

REG1

Adjust exponent

Nomalize

Rounding PHASE 2

Adjust exponent

Nomalize

result pack

REG_OUT

Hnh 3-43.S khi chia s thc du phy ng

185

Bi tp chng 3
Bi tp 1. Thit k v kim tra b cng 32 bit ni tip dng thanh ghi dch v mt FULL_ADDER. 2. Thit k v kim tra b cng 2N bit ni tip dng thanh ghi dch v 2 FULL_ADDER. 3. Thit k v kim tra b cng 32 bit dng thut ton Carry look ahead adder, so snh vi cc thut ton khc. 4. Thit k v kim tra khi nhn s nguyn khng du 4x4 = 8bit dng thut ton cng dch tri. 5. Thit k v kim tra khi nhn s nguyn khng du 4x4 = 8bit dng thut ton cng dch phi. 6. Xy dng s tng qu cho khi nhn s nguyn khng du K bit x K bit = Kbit c kim sot trng hp trn kt qu. 7. Thit k v kim tra khi nhn s nguyn c du 4x4 = 8bit dng m ha Booth c s 2. 8. Thit k v kim tra khi nhn s nguyn c du 4x4 = 8bit dng thut ton m ha Booth c s 4. 9. Xy dng s tng qu cho khi nhn s nguyn c du K bit x K bit = Kbit c kim sot trng hp trn kt qu. 10. Thit k v kim tra khi chia s nguyn khng du 8 bit / 4bit = 4 bit dng thut ton phc hi phn d. 11. Thit k v kim tra khi chia s nguyn khng du 8 bit / 4bit = 4 bit dng thut ton khng phc hi phn d. 12. Thit k v kim tra khi chia s nguyn c du 8 bit / 4bit = 4 bit trn c s khi chia s khng du khng phc hi phn d. 13. Xy dng thut ton tng qut cho php chia s nguyn c du K-bit/ K-bit = K-bit. Trong s s b chia, s chia, thng s, s d u biu din tng qut di dng K-bit nhng. 14. Thit k v m phng khi FIFO 16x16bit. 15. Thit k v m phng khi RAM 32x8bit. mt cng c ghi ng b. 16. Thit k v m phng khi RAM 16x16bit. mt cng c khng ng b, ghi ng b. 186

17. Thit k v m phng khi RAM 16x16bit. hai cng c ghi ng b. 18. Thit k v m phng khi RAM 16x16bit. hai cng cng c khng ng b, ghi ng b. 19. Thit k khi Ram 1 cng c ghi ng b. 16x9 trong mi mt hng cha 8 bit thp l 1 byte d liu cn bt cao nht l bit parity ca d liu tng ng trn hng. 20. Thit k khi thanh ghi a nng General Purpose Register trong vi x l, kch thc 16x16bit h tr hai cng c ng b v 1 cng ghi ng b. 21. Thit k v m phng khi LIFO 16x16bit. 22. Thit k v m phng khi ROM 64x8 bit lu tr gi tr ri rc ha ca mt chu k hnh SIN. 23. Thit k khi ROM ng b 64x8 bit lu tr gi tr ri rc ha ca mt chu k hnh COSIN. 24. Thit k khi ROM CHARACTER vi kch thc cc nh l 24x 200 bit lu tr hnh nh cc ch ci t A ti Z, nh 200 bit c chia thnh 20 hng v 10 ct vi cc gi tr 0, 1 lu tr hnh dng ca tng ch ci. 25. Thit k v kim tra thanh ghi dch h tr thao tc ghi d liu song song iu khin bi tn hiu LOAD v cc lnh dch logic v arithmetich tri khng s dng ton t dch, gi tr dch l mt s 5 bit, d liu dch l chui 32 bit. Tn hiu iu khin LOG = 1 nu nh php dch logic, LOG = 0 nu dch s hc. 26. Thit k v kim tra thanh ghi dch h tr thao tc ghi d liu song song iu khin bi tn hiu LOAD v cc lnh dch logic v arithmetic phi khng s dng ton t dch, gi tr dch l mt s 5 bit, d liu dch l chui 32 bit. Tn hiu iu khin LOG = 1 nu nh php dch logic, LOG = 0 nu dch s hc. 27. Thit k v kim tra thanh ghi dch h tr thao tc ghi d liu song song iu khin bi tn hiu LOAD v php dch vng tri, phi khng s dng ton t dch, gi tr dch l mt s 5 bit, d liu dch l chui 32 bit. Tn hiu iu khin LEFT = 1 nu dch tri v LEFT = 0 nu dch phi. 28. Vit m t VHDL cho my trng thi c s sau:

187

IDLE SEND_REQUEST = 1 RECEIVE_DATA = 1

CNT_SENT = 7 CNT_SENT = 7 RECEIVE DATA SEND_DATA

29.

Vit m t VHDL cho my trng thi c s sau:

IDLE

CNT = 8 and RX = 1 CNT_BIT = 8

RX = 0

RECEIVE DATA

START FRAME DETECT

CNT = 8 and RX = 0

30. Thit k v kim tra b so snh hai s 8 bit c du v khng du. 31. Thit k v kim tra b cng tch ly 32 bit. 32. Thit k khi m lnh chng trnh cho vi x l (Program Counter), ngoi cc cng thng thng khi m h tr thm cc thao tc : tng b m ln 1 n v bng tn hiu Pcinc, t li gi tr b m bng gi tr PC_in v tn hiu iu khin PC_set. 33. Thit k khi thc hin thut ton MontGomery tnh module ca tch hai s A.B cho 1 s nguyn t N theo s thit k sau, rng bit K= 128, 256, 512:

188

MONTGOMERY MULTIPLICATION S = A.B mod N

A A B
B MUX Kbit

k bit k bit

MUX Kbit

34. Thit k hon chnh khi cng s thc du phy ng cho chun ANSI/IEEE 754 32 bit, kiu lm trn ngm nh l lm trn ti gi tr chn gn nht. 35. Thit k hon chnh khi nhn s thc du phy ng cho chun ANSI/IEEE 754 32 bit, kiu lm trn ngm nh l lm trn ti gi tr chn gn nht. 36. Thit k hon chnh khi chia s thc du phy ng cho chun ANSI/IEEE 754 32 bit, kiu lm trn ngm nh l lm trn ti gi tr chn gn nht. 37. Da trn cc khi s hc logic c hc, xy dng khi thc thi lnh n gin trong vi x l ALU, p dng cho cc nhm lnh dch, s hc v logic. 38. Thit k khi cng s thc du phy ng 32-bit s dng 8 bit thp cho phn thp phn v 24 bit cao cho phn nguyn. 39. Thit k khi nhn s thc du phy ng 32-bit s dng 8 bit thp cho phn thp phn v 24 bit cao cho phn nguyn. 40. Thit k khi chia s thc du phy ng 32-bit s dng 8 bit thp cho phn thp phn v 24 bit cao cho phn nguyn. 41. Thit k khi MAC (Multiplication Accumulation) cho s nguyn khng du thc hin thao tc cng v nhn: A = B.C + D. Nghin cu ti u ha khi thit k. 42. Thit k khi MAC (Multiplication Accumulation) cho s nguyn c du thc hin thao tc cng v nhn: A = B.C + D. Nghin cu ti u ha khi thit k. 189

43. Thit k khi MAC (Multiplication Accumulation) cho s thc du phy ng thc hin thao tc cng v nhn: A = B.C + D. Nghin cu ti u ha khi thit k. 44. Thit k khi MAC (Multiplication Accumulation) cho thc du phy tnh vi 8 bit thp phn thp phn v 24 bit phn nguyn thc hin thao tc cng v nhn: A = B.C + D. Nghin cu ti u ha khi thit k. 43. Thit k khi thu v x l tn hiu. Tn hiu u vo l cc t hp 32-bit, vi yu cu thc hin gii nn d liu vi cc tham s u vo nh sau: N S lng bit ca mi n v khi d liu u vo N: 2, 4, 8, 16, 32. M S lng bit ca mi n v khi d liu u ra.(N <= M). M: 2, 4, 8, 16, 32) Tn hiu SE = 1 gii nn c du, SE= 0 gii nn khng du. V d N=4, M= 8, SE = 0

Vi N=4, M= 8, SE = 1:
1 0 0 1

1111

0000

0000

1111

44. Thit k khi thu v x l tn hiu. Tn hiu u vo l cc t hp 32-bit, vi yu cu nn d liu vi cc tham s u vo nh sau: N S lng bit ca mi n v khi d liu u vo N: 2, 4, 8, 16, 32. M S lng bit ca mi n v khi d liu u ra.(N <= M). M: 2, 4, 8, 16, 32) V d N=4, M= 8

190

45. Thit k khi x l tn hiu. Tn hiu u vo l cc t hp 32-bit, vi yu cu bin i d liu nh sau: N S lng bit ca mi n v khi d liu u vo N: 2, 4, 8, 16, 3 COL, DIAG quy nh kiu ma trn u ra m gi tr ch v tr ct trong trng hp COL = 1 T hp u vo: 3 2 1 0 Ma trn u ra nu DIAG = 1, COL = 0: 0 1 2 3 Ma trn u ra nu COL = 1 0 1 2 3 46. Thit k khi x l tn hiu. Tn hiu u vo l cc t hp 32-bit, vi yu cu thc hin cc php bin i ngc vi bi ton 45. 47. Thit k khi nhn 2 vector 4 s nguyn khng du theo cc tiu ch khc nhau v ti nguyn v v tc thc thi. 48. Thit k khi nhn ma trn s nguyn khng du cho 2 ma trn 4x4 theo cc tiu ch khc nhau v ti nguyn v tc thc thi. 49. Thit k khi nhn ma trn 4x4 vi vector 4 s nguyn theo cc tiu ch khc nhau v ti nguyn v tc thc thi. 50. Thit k b gii m knh s hc logic ALC1 thc hin cc lnh sau y trong t hp lnh ca kin trc MIPS

191

Mnem onic

Opcod e

ALU instructions set I Unit description functi on

ARITHMETRIC INSTRUCTIONS

1 2 3 4 5 6

ADD A-28 ADDI

00000 0 00100 0 ADDU 00000 0 ADDI 00100 U 1 SUB 00000 0 SUBU 00000 0 AND ANDI OR ORI NOR XOR A-172 XORI 00000 0 00110 0 00000 0 00110 1 00000 0 00000 0 00111 0 00000 0

10000 IA 0 IA 10000 IA 1 IA 10001 IA 0 10001 IA 1 10010 LOG 0 LOG 10010 LOG 1 LOG 10011 LOG 1 10011 LOG 0 LOG

To add 32-bit integers. To add a constant to 32-bit integer To add 32 bit integer without setting OV To add a constant to 32-bit integer without setting OV To subtract 32-bit integers To subtract 32-bit integer without setting OV To do a bitwise logical AND To do a bitwise with a constant To do a bitwise logical OR To do a bitwise logical OR with a constant To do a bitwise logical NOT OR To do a bitwise logical EXCLUSIVE OR To do a bitwise logical EXCLUSIVE OR with a constant To logical left shift a word by a fixed number of bits 192

LOGICAL INSTRUCTIONS

7 8 9 10 11 12 13

SHIFT INSTRUCTIONS

14

SLL

00000 SH 0

15

00000 00010 SH To logical left shift a word by a 0 0 variable number of bits 16 SRA 00000 00001 SH To arithmetic right shift a word by a A-140 0 1 fixed number of bits 17 SRAV 00000 00011 SH To arithmetic right shift a word by a 0 1 variable number of bits 18 SLR 00000 00001 SH To logical right shift a word by a fixed 0 0 number of bits 1 SLRV 00000 00011 SH To logical right shift a word by a 9 0 0 variable number of bits Chi tit v cc lnh xem trong ti liu [22] Mips Instruction Set Reference Vol I

SLLV

193

Cu hi n tp l thuyt
1. Trnh by thut ton cng Carry look ahead adder, so snh vi thut ton cng ni tip. 2. Trnh by thut ton cng dng 1 full_adder, u nhc im ca thut ton ny. 3. Trnh by cu trc thanh ghi dch, thut ton dch khng dng ton t dch, v d ng dng thanh ghi dch. 4. Trnh by cu trc b m. 5. Trnh by thut ton v cu trc khi nhn s khng du thng thng dng mch t hp. 6. Trnh by thut ton v cu trc khi nhn cng dch tri cho s khng du. 7. Trnh by thut ton v cu trc khi nhn cng dch phi cho s khng du, so snh vi khi nhn cng dch tri. 8. Trnh by thut ton v cu trc khi nhn s c du dng m ha BOOTH c s 2. 9. Trnh by thut ton v cu trc khi nhn s c du dng m ha BOOTH c s 4, so snh vi cc thut ton nhn thng thng. 10. Trnh by thut ton v cu trc khi chia s khng du phc hi phn d. 11. Trnh by thut ton v cu trc khi chia s khng du khng phc hi phn d. 12. Trnh by thut ton v cu trc khi chia s c du. 13. Cc loi khi nh RAM, ROM. 13. Trnh by thut ton xy dng FIFO v LIFO trn c s Dual-port RAM. 14. My trng thi, cu trc my trng thi m t bng VHDL, ng dng. 15. Chun s thc du phy ng, so snh vi chun s thc du phy tnh. 16. Trnh by s khi cng s thc du phy ng theo chun ANSI/IEEE 754. 17. Trnh by s khi nhn s thc du phy ng theo chun ANSI/IEEE 754 17. Trnh by s khi chia s thc du phy ng theo chun ANSI/IEEE 754

194

Chng 4 THIT K MCH S TRN FPGA

Kin thc ca nhng chng trc cung cp kin thc t c bn ti nng cao ca cc thit k s v mt chc nng bng HDL. chng ny chng ta s nghin cu v mt cng ngh cho php chuyn cc thit k logic thnh sn phm ng dng, l cng ngh FPGA. FPGA l cng ngh mang li s thay i ln lao trong k thut in t s hin i. Nu nh cc IC tch hp s trc kia c sn xut bng cng ngh phc tp, s hu bi s t cc quc gia c nn tng khoa hc k thut pht trin, khi thit k cc h thng s ngi thit k khng c c s ty bin linh ng cng nh nhng gii php ti u m phi l thuc vo cc phn t c sn. HDL v FPGA ra i cho php ngi thit k c kh nng t thit k IC chc nng theo mc ch s dng mt cch nhanh chng d dng, y cng chnh l mt trong nhng c s mn hc thit k vi mch tch hp c a vo ging dy cho i tng i hc. Bn cnh s tip cn trc tip v n gin FPGA cn em li hiu qu thit k cao v tnh ng dng thc tin cho nhng bi ton s c xem rt phc tp i vi cc cng ngh c hn. Sinh vin s c gii thiu cn bn v cu trc ca FPGA v cc cch thc lm vic vi FPGA. Song song l cc bi thc hnh gip sinh vin lm quen v s dng thnh tho cc cng c thit k trn FPGA, trn c s thc hin cc bi tp c bn v mt s hng nghin cu chuyn su s dng cng ngh FPGA.

195

1. Tng quan v kin trc FPGA

1.2. Khi nim FPGA FPGA l cng ngh vi mch tch hp kh trnh (PLD - Programmable Logic Device) trnh mi nht v tin tin nht hin nay. Thut ng FieldProgrammable ch qu trnh ti cu trc IC c th c thc hin bi ngi dng cui, trong iu kin thng thng thng, hay ni mt cch khc l ngi k s lp trnh IC c th d dng hin thc ha thit k ca mnh s dng FPGA m khng l thuc vo mt quy trnh sn xut hay cu trc phn cng phc tp no trong nh my bn dn. y chnh l mt trong nhng c im lm FPGA tr thnh mt cng ngh IC kh trnh c nghin v cu pht trin nhiu nht hin nay. c c kh nng , FPGA ra i hon ton l mt cng ngh mi ch khng phi l mt dng m rng ca cc chip kh trnh kiu nh PAL, PLA... S khc bit th nht nm c ch ti cu trc FPGA, ton b cu hnh ca FPGA thng c lu trong mt b nh truy cp ngu nhin (thng thng SRAM), qu trnh ti cu trc c thc hin bng cch c thng tin t RAM lp trnh li cc kt ni v chc nng logic trong IC. C th so snh c ch lm vic ging nh phn mm my tnh cng c lu tr trong RAM v khi thc thi s c np ln lt vi x l, ni cch khc vic lp trnh li cho FPGA cng d dng nh lp trnh li phn mm trn my tnh. Nh vy v mt nguyn tc th qu trnh khi ng ca FPGA khng din ra tc th m cu hnh t SRAM phi c c trc sau mi din ra qu trnh ti cu trc theo ni dung thng tin cha trong SRAM. D liu cha trong b nh RAM ph thuc vo ngun cp, chnh v vy lu gi cu hnh cho FPGA thng phi dng thm mt ROM ngoi vi. n nhng dng sn phm FPGA gn y th FPGA c thit k c th giao tip vi rt nhiu dng ROM khc nhau hoc FPGA thng c thit k km CPLD np nhng thnh phn c nh, vic tch hp ny lm FPGA np cu hnh nhanh hn nhng c ch np v lu tr cu hnh vn khng thay i. Ngoi kh nng im th hai lm FPGA khc bit vi cc PLD th h trc l FPGA c kh nng tch hp logic vi mt cao vi s cng logic tng ng ln ti hng trm nghn, hng triu cng. Kh nng c c nh s t ph trong kin trc ca FPGA. Nu hng m rng ca CPLD tch hp nhiu mng PAL, PLA ln mt chip n, trong khi bn thn cc mn g ny c kch thc ln v cu trc khng n gin nn s lng mng tch hp nhanh chng b hn ch, dung lng ca CPLD nhiu nht cng ch t c con s trm nghn cng tng ng. i vi FPGA th phn t logic c bn khng cn l mng PAL, PLA m thng l cc khi logic lp trnh c cho 4-6 bit u vo v 1 u ra ( thng c gi l LUT). Vic chia nh n v logic cho php 196

to mt cu trc kh trnh linh hot hn v tch hp c nhiu hn s lng cng logic trn mt khi bn dn. Bn cnh hiu qu lm vic v tc lm vic ca FPGA cng vt tri so vi cc IC kh trnh trc . V c mt tch hp ln v tc lm vic cao nn FPGA c th c ng dng cho lp nhng bi ton x l s phc tp i hi hiu sut lm vic ln m cc cng ngh trc khng p ng c. Thit k trn FPGA thng c thc hin bi cc ngn ng HDL v hu ht cc dng FPGA hin ti h tr thit k theo hai ngn ng chnh l Verilog v VHDL, tt c nhng thit k nhng chng trc u c th hin thc ha trn FPGA bng mt quy trnh n gin. Ngoi HDL, thit k trn FPGA cn c th c thc hin thng qua h nhng ngha l bng ngn ng phn mm (thng l C/C++). Mt phng php na thng dng trong cc bi ton x l s tn hiu l s dng System Generator mt chng trnh kt hp ca Matlab vi phn mm thit k FPGA ca Xilinx. Hin nay cng ngh FPGA ang c pht trin rng ri bi nhiu cng ty bn dn khc nhau. Dn u l Xilinx vi cc dng sn phm nh Virtex 3, 4, 5, 6 v Spartan3, 6, Altera vi Stratix, Cyclone, Arria, Bn cnh cn c sn phm ca Lattice Semiconductor Company, Actel, Achronix, Blue Silicon Technology Khi nim FPGA board, hay FPGA KIT l khi nim ch mt bo mch in trn c gn chp FPGA v cc phn t khc nh cng giao tip, mn hnh, led, nt bm v bao gi cng c phn giao tip vi my tnh np cu hnh cho FPGA. Ngoi ra board cn cha cc thit b ngoi vi c lin kt vi cc cng vo ra ca FPGA nhm mc ch th nghim. Theo bng so snh 1-4 di y trn c th thy kh nng tch hp ca FPGA l rt ln, nhng FPGA mi nht hin nay c kh nng tch hp ln tng ng nh cc chp chuyn dng cho my ch nh Xenon 6-core. Cn bn thn cc chip c nh nh Pentium hay thm ch Core duo nu so snh v mc tch hp th chng c th c np hon ton vo mt FPGA c trung bnh. Kh nng ny ca FPGA m ra mt hng mi cho ng dng FPGA l s dng FPGA nh mt phng tin kim tra thit k ASIC (ASIC prototyping with FPGA). K tha ca phng php ny l cng ngh c tn gi Hard-copy l cng ngh cho php sao chp ton b cc thit k c np vo FPGA thnh mt IC chuyn dng (ASIC) c lp. Tnh ti u ca thit k ny khng cao nhng n gin v gim ng k chi ph nu so snh vi thit k ASIC chun. Ti nguyn logic ca FPGA c th hin bng so snh sau:

197

Bng 4-1 IC Intel 4004 Zilog Z80 Intel 80286 Pentium 2 Pentium 4 Core 2 Duo Six core Xenon 7400 AMD K8 Spartan 3E Virtex 4 Virtex 5 Starix IV Starix V Virtex 6 Virtex 7 Mt tch hp ca mt s IC thng dng Transitor count Process Manufacture Year 2 300 8 500 164 000 7 500 000 42 000 000 291 000 000 1 900 000 000 106 000 000 ~40 000 000 1 000 000 000 1 100 000 000 2 500 000 000 3 800 000 000 ~2 600 000 000 ~6 800 000 000 10 um 4 um 1.5 um 0.35um 180 nm 65 nm 45 nm 32 nm 130 nm 90 nm 90 nm 65 nm 40 nm 28 nm 65 nm 28nm Intel Zilog Intel Intel Intel Intel Intel Intel AMD Xilinx Xilinx Xilinx Altera Altera Xilinx Xilinx 1971 1976 1982 1997 2000 2006 2008 2010 2003 1998 2004 2006 2008 2011 2010 2011

10-Core Xeon Westmere-EX 2 600 000 000

Ngun http://en.wikipedia.org/wiki/Transistor_count 1.3. ng dng ca FPGA trong x l tn hiu s Do kh nng ti cu trc n gin v s hu mt khi ti nguyn logic ln FPGA c th c ng dng cho nhiu cc lp bi ton x l tn hiu s c ln m cc cng ngh trc khng lm c hoc lm c nhng vi tc v hiu sut thp. Cc lp ng dng l: - Cc ng dng chung v x l s nh lc tn hiu, tm kim, phn tch, gii m, iu ch tn hiu, trn tn hiu - Cc ng dng v m ha, gii m ging ni, nhn dng ging ni, tng hp ging ni. X l tn hiu m thanh bao gm lc nhiu , trn, m ha, gii m, nn, tng hp m thanh

198

- ng dng trong x l nh s, nn v gii nn, cc thao tc bin i, chnh sa, nhn dng nh s - ng dng trong cc h thng bo mt thng tin, cung cp cc khi gii m v m ha c th thc thi vi tc rt cao v d dng tham s ha hoc iu chnh. - ng dng trong cc h thng thng tin nh cc h thng Voice IP, Voice mail. Modem, in thoi di ng, m ha v gii m truyn thng trong mng LAN, WIFI trong truyn hnh KTS, radio KTS - ng dng trong iu khin cc thit b in t: cng, my in, my cng nghip , dn ng, nh v, robots. Cc sn phm ng dng FPGA hin ti vn nm con s khim tn nu so snh vi cc gii php truyn thng tuy vy vi cc th mnh k trn FPGA chc chn s l mt cng ngh quan trng ca tng lai. Mt s nhng kin trc thch nghi Vi x l FPGA vi nn tng chp vi x l v FPGA c t trong mt chip n mang li hiu qu x l mnh m do kt hp c tnh linh ng ca phn mm v hiu sut, tc ca phn cng ang l nhng hng nghin cu mi v c th to nn s thay i ln vi cc thit k s truyn thng. 1.4. Cng ngh ti cu trc FPGA Trong lnh vc cng ngh ti cu trc IC hin nay c tt c 5 cng ngh fuse, EPROM, EEPROM, SRAM based, Antifuse trong SRAM-based l cng ngh ph bin c s dng cho FPGA. SRAM-based Cu hnh ca FPGA bn cht l m t cc im kt ni gia cc thnh phn c cha trong IC, c hai dng kt ni c bn l kt ni gia cc ng kt ni dn bng ma trn chuyn mch (switch matrix), v kt ni ni b trong cc khi logic. Kt ni trong ma trn chuyn l kt ni gia hai knh dn c thc hin thng qua cc pass-transitor, hay gi l transitor dn. 1 bit thng tin t b nh SRAM c s dng ng hoc m pass-transitor ny, tng ng s ngt hay kt ni gia hai knh dn. Kiu cu trc th hai ph bin trong cc khi logic l lp trnh thng qua khi chn knh (Multiplexer). Thng tin iu khin t SRAM cho php khi chn knh chn mt trong s cc u vo a ra. Nu khi lng u vo l 2n, th yu cu s bit iu khin t SRAM l n-bit. Kiu cu trc th 3 c gi l Look-Up Table (LUT), mi mt LUT c th c lp trnh thc hin bt k mt hm logic bt k no ca u ra ph thuc cc u vo. C ch lm vic ca LUT c th tm tt nh sau, gi s cn 199

thc hin mt hm m u vo v n u ra th cn mt b nh 2mx(n), cha thng tin v n u ra i vi tt c cc kh nng u vo. Khi lm vic th m-bit u vo ng vai tr nh a ch truy cp (Look-up) ln b nh (Table). V bn cht cu trc ny cng ging nh khi chn knh c ln. Trong FPGA ph bin s dng cc LUT c 4-6 bit u vo v 1 bit u ra.

Logic cell

sRAM SRAM

Logic cell

GRAM

SRAM

Logic cell

Logic cell

Hnh 4-1. SRAM-based FPGA Nh vy tnh kh trnh ca FPGA c thc hin nh tnh kh trnh ca cc khi logic v tnh kh trnh ca h thng knh kt ni, ngoi ra l tnh kh trnh ca cc khi iu khin cng vo ra. Sau y ta s i vo nghin cu cu trc c th ca h FPGA Spartan 3E ca Xilinx, v c bn, cu trc ca cc h Xilinx FPGA khc u tng t nh cu trc ny. 1.5. Kin trc tng quan Hnh 4.2 trnh by cu trc tng quan nht cho cc loi FPGA hin nay. Cu trc chi tit v tn gi ca cc thnh phn c th thay i ty theo cc hng sn xut khc nhau nhng v c bn FPGA c cu thnh t cc khi logic (Logic Block) s lng ca cc khi khi ny thay i t vi trm (Xilinx Spartan) n vi chc nghn (Xilinx Virtex 6, 7) c b tr di dng ma trn, chng c ni vi nhau thng qua h thng cc knh kt ni kh trnh. H 200

thng ny cn c nhim v kt ni vi cc cng giao tip vo ra (IO_PAD) ca FPGA. S lng cc chn vo ra thay i t vi trm n c hn mt nghn. Bn cnh cc thnh phn chnh , nhng FPGA c ln cn c tch hp cng nhng khi thit k sn m thut ng gi l Hard IP cores, cc IP cores ny c th l cc b nh RAM, ROM, khi thc hin php nhn, khi thc hin php nhn cng (DSP)... b vi x l c va v nh nh PowerPC hay ARM.
IO_PAD IO_PAD IO_PAD

..

2. Kin trc chi tit Xilinx FPGA Spartan-3E.

hiu chi tit v cu trc ca FPGA phn di y ta s i nghin cu mt cu trc c th ca FPGA Spartan 3E, ti liu gc [20], [21] c th tm thy trn trang ch ca Xilinx, ngi c nn tham kho thm hiu k v y hn vn . Spartan 3E FPGA c nhiu loi khc nhau khc nhau v kch thc, ti nguyn logic, cch thc ng gi, tc , s lng chn vo ra bng sau lit k cc tham s ca cc dng FPGA Spartan 3E. 201

IO_PAD IO_PAD IO_PAD

IO_PAD

LOGIC BLOCK

LOGIC BLOCK

..

LOGIC BLOCK

LOGIC BLOCK

LOGIC BLOCK

..

IO_PAD

LOGIC BLOCK

LOGIC BLOCK

IO_PAD

LOGIC BLOCK

IO_PAD

Hnh 4-2. Kin trc tng quan ca FPGA

IP_COREs, RAM, ROM...

Interconnect wires

IO_PAD

..

LOGIC BLOCK

..

IO_PAD

Bng 4-2 XILINX SPARTAN 3E Ma trn CLB Khi nhn chuyn dng DCM Cng vo ra vi sai (**)
40 68 92 124 156

Cng logic tng ng Hng

Tng s CLBs

RAM phn tn

S lng cng (Xilinx) (*)

Tng s Slices

XC3S100E 100K XC3S250E 250K XC3S500E 500K XC3S1200E 1200K XC3S1600E 1600K

2160 5508 10476 19512 33192

22 34 46 60 76

16 26 34 46 58

240 960 15K 72K 4 612 2448 38K 216K 12 1164 4656 73K 360K 20 2168 8672 136K 504K 28 3688 14752 231K 648K 36

2 4 4 8 8

108 172 232 304 376

(*) Khi nim cng tng ng ca Xilinx c tnh mt cch c bit, thng thng nn nh gi ti nguyn FPGA thng qua s lng CLBs (**) Cng ra vo vi sai - mt cp tn hiu vo ra c x l nh mt tn hiu vi sai dng s. V d theo bng trn XC3S500 c s Slices l 4656, tng ng 1164 CLBs (10,476 cng tng ng) c b tr trn 46 hng v 24 ct. Cc ti nguyn khc bao gm 4 khi iu chnh/to xung nhp h thng Digital Clock Manager (DCM) c b tr 2 trn v 2 di. Cc khi nh bao gm 360K Block RAM v ti a 73K RAM phn tn. Tch hp 20 khi nhn 18x18 bt c b tr st cc Block Ram. V ti nguyn cng vo ra XC3S500E vi gi PQ208 h tr 208 chn vo ra trong c 8 cng cho xung nhp h thng, ti a 232 cng vo ra s dng t do, trong c 158 chn Input/Output, s cn li l chn Input. XC3S500E c thit k trn cng ngh 90nm v cho php lm vic xung nhp ti a n 300Mhz, vi tc nh vy XC3S500 c th p ng hu ht nhng bi ton x l s c va v nh. Hnh v di y th hin cu trc tng quan ca h FPGA ny.

Cng vo ra

IC

Khi RAM

C t

202

IOBs

DCM text

CLBs

CLBs

CLBs (Configurable Logic Blocks) L cc khi logic lp trnh c cha cc LUTs v cc phn t nh flip-flop c th c cu trc thc hin cc hm khc nhau. IOBs (Input/Output Blocks) l cc khi iu khin giao tip gia cc chn vo ca FPGA vi cc khi logic bn trong, h tr c nhiu dng tn hiu khc nhau. Cc khi IO c phn b xung quanh mng cc CLB. Block RAM cc khi RAM 18Kbit h tr cc cng c ghi c lp, vi cc FPGA h Spartan 3 block RAM thng phn b hai ct, mi ct cha mt vi khi RAM 18Kbit, mi khi RAM c ni trc tip vi mt khi nhn 18 bit. Dedicated Multiplier: Cc khi thc hin php nhn vi u vo l cc s nh phn khng du 18 bit. DCM (Digital Clock Manager) Cc khi lm nhim v iu chnh, phn phi tn hiu ng b ti tt cc cc khi khc. DCM thng c phn b gia, vi hai khi trn v hai khi di. mt s i FPGA Spartan 3E DCM cn c b tr gia. Interconnect: Cc kt ni kh trnh v ma trn chuyn dng lin kt cc phn t chc nng ca FPGA vi nhau.

IOBs
IOBs

Hnh 4-3. Kin trc tng quan ca Spartan 3E FPGA FPGA Spartan 3E c cu trc t cc thnh phn sau:

IOBs

203

2.1. Khi logic kh trnh Khi logic kh trnh ca FPGA Xilinx c tn gi y l Configurable Logic Blocks (CLBs). CLBs l phn t c bn cu thnh FPGA, l ngun ti nguyn logic chnh to nn cc mch logic ng b ln khng ng b. Mi CLB c cu thnh t 4 Slices, mi Slice li c cu thnh t 2 LUTs (Look Up Tables). Phn b ca cc CLB th hin Hnh 4.4:

X0Y3

X1Y3

X2Y3

X3Y3

X0Y2

X1Y2

X2Y2

X3Y2

X0Y1

X1Y1

X2Y1

X3Y1

X0Y0 Spartan 3E FPGA

X1Y0

X2Y0

X3Y0

IOBs

CLB

Slice

Hnh 4-4. Phn b ca cc CLB trong FPGA Cc CLB c phn b theo hng v theo ct, mi mt CLB c xc nh bng mt ta X v Y trong ma trn, i vi Spartan 3E s lng hng thay i t 22 n 76, s lng ct t 16 n 56 ty thuc vo cc gi c th. 2.1.1. SLICE Mi CLB c cu to thnh t 4 slices v cc slices ny chia lm hai nhm tri v phi. Nhm 2 slices bn tri c kh nng thc hin cc chc nng logic v lm vic nh phn t nh nn c gi l SLICEM (SLICE Memory). Nhm 2 silces bn phi ch thc hin c cc chc nng logic nn c gi l SLICEL (SLICE Logic). Thit k nh vy xut pht t thc t l nhu cu thc hin chc nng logic thng ln hn so vi nhu cu lu tr d liu, do vic

204

h tr ch mt na lm vic nh phn t nh lm gim kch thc v chi ph cho FPGA, mt khc lm tng tc lm vic cho ton khi.

Hnh 4-5. B tr slice bn trong mt CLB SLICEL ch thc hin chc nng logic nn ch cha cc thnh phn gm LUT, chui bt nh (Carry Chain), chui s hc (Arithmetic chain), cc b chn knh m rng (wide-multiplexer) F5MUX v FiMUX, 2 Flip-flop. Cn i vi SLICEM th ngoi cc thnh phn trn LUT cn c th c cu hnh lm vic nh mt thanh ghi dch 16 bit Shift-Register (SRL16), hoc RAM phn tn 16x1bit (Distributed RAM), nh trnh by trn Hnh 4.6.
SRL16 FiMUX RAM16 LUT4(G) Carry Register F5MUX F5MUX SRL16 RAM16 LUT4(F) Arithmetic logic Carry Register Arithmetic logic LUT4(F) Carry Register FiMUX LUT4(G) Carry Register

SLICEM

SLICEL

Hnh 4-6. Phn b ti nguyn trong SLICEM v SLICEL 205

Cu trc chi tit ca mt Slices c th hin hnh di y:

Hnh 4-7. Cu trc chi tit ca Slice Nhng ng gch t th hin nhng kt ni ti cc ti nguyn m ch SLICEM mi c, nhng ng gch lin ch nhng kt ni m c hai dng SLICEs u c. 206

Mi mt slice chia lm hai phn vi cu trc gn nh nhau phn trn v phn di, mi phn cha cc khi chc nng ging nhau nhng c k hiu khc nhau, v d G-LUT ch LUT phn trn, F-LUT ch LUT phn di . Tn hiu ng b CLK, tn hiu cho php ca xung nhp CE (Clock Enable), tn hiu cho php ghi d liu vo SLICEM SLICEWE1 v tn hiu RS (Reset/Set) l cc tn hiu dng chung cho c phn trn v phn di ca SLICE. Cc ng d liu c bn trong Slices l cc ng bt u t cc u vo F[4:1] v G[4:1] thng ti F-LUT v G-LUT tng ng, ti y s thc hin hm logic t hp theo yu cu v gi ra cc u ra D. T y u ra D c gi ra cc cng ra ca SLICE thng qua cc ng sau: Kt thc trc tip ti cc u ra X, Y v ni ra ngoi vi ma trn kt ni. Thng qua FMUX (GMUX) ri DMUX lm u vo cho phn t nh FFX (FFY) sau gi ra thng qua cc u ra QX (QY) tng ng ca cc phn t nh. iu khin CYMUXF (CYMUXG) ca chui bit nh (chi tit v Carry chain xem mc 2.1.5). Gi ti cng XORF (XORF) tnh tng hoc tch ring trong chui nh. Lm u vo cho F5MUX (FIMUX) trong trng hp thit k cc khi logic, cc chui nh, thanh ghi dch, RAM m rng. Bn cnh cc ng d liu c bn trn th trong Slice tn ti cc ng d liu tt bt u t cc u vo BX, BY v kt thc qua mt trong nhng ng sau: B qua c LUT ln phn t nh v kt thc cc u ra BXOUT, BYOUT ri ra ma trn kt ni. B qua LUT nhng lm u vo cho cc phn t nh v kt thc cc u ra QX, QY. iu khin F5MUX hoc FiMUX. Thng qua cc b chn knh, tham gia nh mt u vo ca chui bit nh. Lm vic nh u vo DI ca LUT (khi LUT lm vic ch Distributed RAM hay Shift Register). BY c th ng vai tr ca tn hiu REV cho phn t nh (xem chi tit v REV ti m t v phn t nh)

207

2.1.2. Bng tham chiu LUT

Y 4 G[4:1] G - LUT A[4:1] D FFY YQ

X 4 F[4:1] F - LUT A[4:1] D FFX XQ

Hnh 4-8. Phn b cc LUT trn mt Slice Bng tham chiu (Look-Up Table) gi tt l cc LUT c phn b gc trn tri v gc di phi ca Slice v c gi tn tng ng l F-LUT v GLUT. Phn t nh ng vai tr l u ra ca cc LUT c gi tng ng l Flip-Flop X (FFX) v Flip-Flop Y FFY. LUT l n v logic v l ti nguyn logic c bn ca FPGA, LUT c kh nng c cu trc thc hin mt hm logic bt k vi 4 u vo. Cu trc ca LUT c th hin hnh sau:
1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1

A[3:0]

Hnh 4-9. Cu trc ca LUT LUT bn cht l mt b chn knh 16 u vo, cc u vo ca LUT A[3:0] ng vai tr tn hiu chn knh, u ra ca LUT l u ra ca b chn knh. Khi cn thc hin mt hm logic bt k no , mt bng nh SRAM 16 bit c to lu tr kt qu bng chn l ca hm, t hp 16 gi tr ca hm tng ng s l cc knh chn ca khi chn knh. Khi lm vic ty vo gi tr ca A[3:0] u ra D s nhn mt trong s 16 gi tr lu tr tng ng trong SRAM. Bng cch mt hm logic bt k vi 4 u vo 1 u ra c th thc hin c trn LUT. 208

2 LUTs c trong SLICEM c th c cu trc lm vic nh 16x1 RAM gi l Ram phn tn (Distributed RAM) hoc c cu trc lm vic nh mt thanh ghi dch 16-bit SHL16. Cu trc ca cc phn t ny s c nghin cu k hn phn 2.1.7 v 2.1.8 Cc LUT c th c kt hp vi nhau thc hin cc hm logic ty bin c s lng u vo ln hn 4 thng qua cc b chn knh m rng. cc th h FPGA v sau ny, nguyn l lm vic ca LUT vn khng thay i nhng s lng u vo c th nhiu hn, v d trong Virtex-5, s lng u vo l 6. 2.1.3. Phn t nh Phn t nh (Storage elements) c trong CLBs l Flip-Flop FFX, FFY c th c cu hnh lm vic nh D-flip-flop hoc Latch, lm vic vi cc tn hiu iu khin ng b hoc khng ng b v vy cu trc ca phn t nh trong FPGA phc tp hn so vi cu trc ca D-flip-flop thng thng. Cc u ra QX, QY ca phn t nh cng l cc u ra ca Slices. Trong phn ln cc ng dng thng gp phn t nh c cu trc lm vic nh D-flipflop ng b. Cc cng giao tip ca mt phn t nh bao gm: D, Q l cc cng d liu vo v ra tng ng. C l cng vo xung nhp ng b. GE (Gate Enable) cng cho php xung nhp C khi lm vic ch latch CE (Clock Enable) cng cho php xung nhp C khi lm vic ch flipflop S, R l cc cng Set v Reset ng b cho Flip-flop. PRE, CLR Cng Set v Clear khng ng b RS Cng vo ca CLB cho S, R, PRE, hay CLR. REV Cng vo pha nghch so vi RS, thng c u vo t BY, c tc dng ngc vi RS. Khi c hai cng ny kch hot th gi tr u ra ca phn t nh bng 0. 2.1.4. B chn knh m rng Trong cu trc ca Slice c cha hai b chn knh c bit gi l B chn knh m rng - Wide-multipexer F5MUX v FiMUX.

209

FiMUX

FXINA FXINB BY

1 FX Local Feed Back to FXIN 0 D

F5MUX

Y General Connect Q YQ

F[4:1] G[4:1] BX

LUT

1 0 D Q

LUT

F5 Local Feed Back to FXIN X General Connect XQ

Hnh 4-10. FiMUX v F5MUX Mi mt LUT c thit k c th thc hin c mi hm logic 4 u vo. Mc ch ca cc b chn knh ny l tng tnh linh ng ca FPGA bng cch kt hp cc phn t logic chc nng nh LUT, chui bit nh, Thanh ghi dch, RAM phn tn cc Slices, CLBs khc nhau to ra cc hm ty bin vi nhiu u vo hn. V d bng sau th hin cch s dng 2 LUT 4 u vo v 1 F5MUX to ra mt hm logic ty bin 5 u vo.

LUT0

OUT0

OUT

OUT1

LUT1

Hnh 4-11. Nguyn l lm vic va F5MUX 210

MUX

u tin i vi hm 5 bin OUT = F(X1, X2, X3, X4, X5) bt k ta thnh lp bng chn l tng ng, bng ny c chia lm hai phn, phn trn vi tt c cc gi tr ca X5 bng 0, ta gi hm ny c tn l: OUT0 = F(X1, X2, X3,X4,0) = F0(X1, X2, X3, X4) phn di vi tt c cc gi tr ca X5 bng 1, ta gi hm ny c tn l: OUT1 = F(X1, X2, X3, X4,1). = F1(X1, X2, X3, X4) Hai hm F1, F2 l cc hm 4 u vo c thc hin tng ng bi LUT1, LUT2. Tn hiu X5 c s dng lm tn hiu chn knh cho F5MUX chn 1 trong hai gi tr u ra ca LUT1, LUT2, u ra ca F5MUX chnh l kt qu ca hm 5 bin cn thc hin. OUT = F0(X1, X2, X3, X4) nu X5 = 0 = F1(X1, X2, X3, X4) nu X5 = 1

Hnh 4-12. Cu to ca F5MUX F5MUX c thit k da trn nguyn l trn nhng trn FPGA thc t ngoi cng ra thng thng O theo kt qu gi ra phn t nh ca CLB, th kt qu cn c gi ra tn hiu tr v LO (Local Output) theo kt qu c th c gi ngc li cc FiMUX tip tc thc hin cc hm logic c nhiu cng vo hn. Tng t nh vy c th thnh lp cc hm vi s lng u vo ln hn bng 6, 7, 8 tng ng FiMUX s c gi l F6MUX, F7MUX, F8MUX V d 1 hm 6 bin th phi thc hin bng cch ghp ni 2 CLB lin tip thng qua F6MUX. Ngoi thc hin cc hm y vi s kt hp hai LUT to ra hm logic ty bin 5 u vo th c th kt hp to ra cc hm logic khng y vi 6, 7, 8, 9 u vo. 2.1.5. Chui bit nh v chui s hc Trong Spartan-3E cng nh trong cc FPGA th h sau ny u c tch hp cc chui bit nh (carry chain) v cc chui s hc (arithmetic chain) c bit, cc chui ny kt hp vi cc LUT c s dng t ng hu ht trong cc 211

php ton s hc thng gp nh cng, nhn, gp phn rt ln vo vic tng tc cho cc php ton ny, ng thi tit kim ti nguyn logic (LUTs). Cc chui ny c to thnh bng cc khi chn knh v cc cng logic ring bit, cc phn t cng c th c s dng c lp thc hin cc hm logic n gin khc. Chui bit nh thng gp trong php ton cng, vi mi SLICE chui bit nh c bt u t tn hiu CIN v kt thc COUT. Cc chui n l trong c th c ni trc tip gia cc CLB vi nhau to thnh cc chui di hn theo yu cu. Mi mt chui bit nh ny c th c bt u ti bt k mt u vo BY hoc BY no ca cc Slices. Cc chui s hc logic bao gm chui thc hin hm XOR vi cc cng XORG, XORF phn b phn trn v phn dui ca Slice, chui AND vi cc cng GAND, FAND. Cc chui ny kt hp vi cc LUT thc hin php nhn hoc to thnh cc b m nh phn. Cc thnh phn c bn ca Chui bit nh v Chui s hc bao gm: CYINIT: nm phn di ca Slice, chn tn hiu t BX u vo ca (Slice) nu l im u ca chui hoc CIN t Slice k cn trong trng hp mun ko di chui nh. CYOF/CYOG: Khi chn nh pht sinh tng ng phn di v trn ca Slices, c kh nng chn mt trong s cc u vo F1,F2/ G1,G2 l u vo ca cc LUT, u vo t cng AND, u vo t BX/BY, u vo vi cc gi tr c nh 0, 1 nu s dng nh cc hm logic thng thng CYMUXG la chn gia hai dng nh l CYINIT nu l nh lan truyn (carry propagation), CYOG nu l nh pht sinh (carry generation), tng ng vi gi tr t CYSELG l 0 v 1. u ra COUT hoc cng YB ca Slice. CYMUXF la chn gia hai dng nh l CMUXF nu l nh lan truyn (carry propagation), CYOF nu l nh pht sinh (carry generation), tng ng vi gi tr t CYSELF l 0 v 1. u ra ti u vo ca chui nh ti phn trn ca Slice hoc cng XB ca Slice CYSELF/G la chn gia mt trong hai tn hiu: u ra ca F/GLUT nu l nh pht sinh, v gi tr bng 1 cho trng hp nh lan truyn. XORF cng XOR cho chui thc hin hm cng b 2 thuc na di ca Slice, hai u vo t u ra ca FLUT v t u vo chui nh CYINIT,

212

u ra ca cng c gi ti cng D ca phn t nh FFX hoc trc tip ti u ra X ca Slices XORG cng XOR cho chui thc hin hm cng b 2 thuc na trn ca Slice, hai u vo t u ra ca GLUT v t u vo chui nh CMUXF, u ra ca cng c gi ra cng D ca phn t nh FFY hoc trc tip ti cng Y ca Slice FAND cng AND cho chui thc hin hm logic nhn thuc na di ca Slice, cc u vo ly trc tip t u vo F1, F2 ca cc LUT, u ra c gi ti CYOF tr thnh tn hiu nh pht sinh cho chui bit nh. FAND cng AND cho chui thc hin hm logic nhn thuc na di ca Slice, cc u vo ly trc tip t u vo F1, F2 ca cc LUT, u ra c gi ti CYOF tr thnh tn hiu nh pht sinh cho chui bit nh.

1
4 G[4:1] A[4:1] CYSELG 0 1 CYMUXG

YB

G -LUT
G1 G2 D XORG FFY BY D Q YQ

GAND 1 0

CYOG

XB

1
0 F[4:1] A[4:1] CYSELF X 1 CYMUXF

F -LUT
F1 F2 D XORF BX D Q XQ

FFX

CYOF FAND 1 0 CYINIT

Hnh 4-13. Chui bit nh 213

Minh ha v cch s dng cc chui ny ti u ha ti nguyn v tng tc cho FPGA nh sau: V php cng, thit k in hnh ca b cng bt u t thit k quen thuc ca b cng 1 bit y gi l FULL_ADDER.
Half Adder A B Half Adder Sum

Carry Out

Carry in

Hnh 4-14. S logic truyn thng ca FULL_ADDER Vi cu trc ny thc hin mt FULL_ADDER trn FPGA cn ti thiu hai LUT, mi LUT s dng vi 3 u vo A, B, CIN. Trn thc t cu trc trn c th c thit k khc i nhm tng tc thc hin cng nh gim thiu ti nguyn bng s cng thy nh trc. nh ngha cc tn hiu sau g = A and B; generation carry - nh pht sinh p = A xor B; propagation delay nh lan truyn khi Sum = p xor CIN COUT = (CIN and (not p)) or (a and p); T hai cng thc trn c th thit lp mt s khc ca FULL_ADDER nh sau
Function Generator COUT MUXCY A B 0 1 SUM

XORCY

Hnh 4-15. S logic ca FULL_ADDER trn FPGA

214

Vi s trn ta c th thy thay v s dng hai phn t AND ta s dng mt b chn knh 2 u vo. Quay li vi s Hnh 4.12 v so snh vi s trn ta c th thy FULL_ADDER c th thc hin vi 1 LUT hai u v kt hp vi chui bit nh c sn trong FPGA. Khi CYMUXF, CYMUXG ng vi tr nh b chn knh trn Hnh 4.14. Bn thn LUT thc hin hm XOR. Vi cch thit k nh vy mi Slice c th to c chui nh cho 2 bit. Cc u vo CIN, COUT ca cc CLB c ni trc tip v c ti u ha tr lan truyn gn nh bng 0 chui nh thc hin vi mt tc rt nhanh. V php nhn, thc hin php nhn th phi thc hin vic tnh cc tch ring (partial products) sau cng cc tch ny vi nhau to thnh kt qu y (full product). Khi biu din cc s di dng nh phn, tch ring hoc bng s b nhn nu nh bit nhn l 1 v tch ring bng 0 nu nh bit nhn bng 0. cng cc tch ring th phi s dng chui bt nh tng t nh v d trn. Cn tch ring c to bi cc phn t AND. Xt s tnh tch ring nh hnh di y:

A3

P4

A2

P3

A1

P2

A0

P1

+
0 B1 B0

P0

Hnh 4-16. Cch tnh tng cc tch ring trong php nhn

215

S trn biu din php nhn B0B1 vi A0A1A2A3. i vi mch dng tnh cho mt bit ca tch ring P2 c khoanh vng trn Hnh 4.16 th cn ti thiu 1 cng XOR 3 u vo (tng ng 2 cng XOR 2 u vo) v hai cng AND 2 u vo. Nu thc hin theo s trn v ch dng LUT c th thy mi u vo phn t XOR xut pht t 1 phn t AND, iu c ngha l mi phn t AND chim 1 LUT. Nh vy nu nhn hai s 8-bit ta phi cn 8x8 = 64 LUT = 32 Slices. Quan st li s 4.7, nu s dng cc ti nguyn khc ca chui bit nh c th thit k nh sau:
COUT

0 Bn

1 Pm+1

CIN

Hnh 4-17. Ti u ha khi MULT_AND dng chui bit nh Vi s nh trn tng Am*Bn+1 + Am+1*Bn c thc hin trong 1 LUT, ngoi ra tch Am+1*Bn c lp li nh phn t AND (FAND hay GAND) gi ti b chn knh (CYMUXF, hoc CYMUXG). Vi cch lm nh vy th s lng LUT i vi php nhn 8x8 gim xung ch cn mt na tc l 32LUTs = 16 Slices. Bn cnh cc phn t MULT_AND c ti u ha v tr gia cc kt ni nn c th lm vic rt nhanh. Tuy vy s nhn nh trn ch c thc hin vi cc php nhn c s bit u vo nh. Vi cc php nhn c s lng bit ln hn th FPGA s s dng cc khi nhn chuyn dng (dedicated multipliers) 18-bit x 18-bit s c trnh by di. 2.1.6. RAM phn tn Trong mi CLB ca Xilinx FPGA c cha 4 x 16 = 64 bit RAM tng ng vi 4 LUT nm trong 2 SLICEM ca CLB. Phn RAM c th s dng nh mt khi 64-bit RAM mt cng (Single-port RAM) hoc khi 32-bit RAM hai cng(Dual-port RAM), khi khi RAM c to thnh t hai mng nh 32-bit v lu tr d liu y ht nh nhau. V cc RAM ny phn b ri rc theo CLB bn trong cu trc ca FPGA nn chng c gi l cc RAM phn tn (Distributed 216

RAM) phn bit vi cc khi RAM nm tp trung v c kch thc ln hn khc l Block RAM.
Single Port RAM D Address Write WCLK D o Address Read Write WCLK Read Port Address DPO Read Read Dual Port RAM R/W Port

R/W Port

SPO

Hnh 4-18. RAM phn tn trong FPGA RAM phn tn trong FPGA c th s dng mt trong hai dng nh hnh v trn. i vi kiu single-port RAM th c mt ghi d liu 1 cng c d liu. i vi dual-port RAM th c 1 cng c ghi d liu v mt cng ch thc hin c d liu t RAM. i vi thao tc ghi d liu cho c hai kiu RAM c thc hin ng b trong 1 xung nhp WCLK, tn hiu cho php ghi l WE (Write Enable, theo ngm nh tch cc nu WE = 1). i vi Dual-port RAM th mi ng tc ghi s thc hin ghi d liu t cng D vo hai phn nh ca RAM. Thao tc c d liu hai dng RAM u c thc hin khng ng b v thun ty s dng cc khi logic t hp, thi gian tr ca thao tc c d liu bng thi gian tr t hp v thng thng c ti u nh hn so vi thi gian 1 xung nhp ng h. Gin sau th hin thao tc c ghi d liu:

Hnh 4-19. Thao tc c ghi d liu ca Distributed RAM trong Xilinx FPGA 217

Ti nguyn RAM phn tn trong FPGA c s dng ht sc linh ng, mt khi CLB n l c th c cu hnh to thnh cc khi 64x1, 32x2, 16x4 Distributed RAM, cc u vo G[4:1] v F[4:1] c dng nh cc u vo a ch. Cc khi RAM ln hn c th cu to bng cch ghp ti nguyn trong cc CLB khc nhau li s dng cc b chn knh m rng, khi cc cng BX, BY c s dng nh cc bit a ch b xung. 2.1.7. Thanh ghi dch Mt dng s dng khc ca cc LUTG, v LUTF trong SLICEM l dng nh mt thanh ghi dch (Shift Register) 16 bit k hiu l SRL16.
DIN CLK D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Hnh 4-20. S dng LUT nh thanh ghi dch 16-bit Khi s dng LUT nh mt thanh ghi dch, cu trc ca LUT v c bn gi nguyn, cc knh chn c ni vi chui cc D flip-flop lm vic ng b. u ra D vn nhn gi tr ti u ra Q ca D-flip-flop quy nh bi gi tr a ch A[3:0], chnh v vy SRL16 cn c gi l thanh ghi dch c a ch. Ngoi u ra D thanh ghi dch c u ra cui cng c tn l Q15 hoc MC15 quy nh trong th vin cc phn t chun ca FPGA. u vo DI c th c bt u t cng BY. BX hoc u vo SHIFTIN t ngoi CLB. Tn hiu xung nhp ng b CLK v CE c ly t tn hiu ng b chung ca Slices. u ra ca MC15 ca SRL16 c th c ni tip vi cng SHIFTOUT ca Slice hoc YB. u ra a ch D c th c gi trc tip ra ngoi Slice hoc thng qua FFX hoc FFY, khi chui dch tnh thm mt n v, trn thc t tr ca FFX, FFY thng nh hn so vi tr ca cc D-flip-flop trong thanh ghi dch.

218

SHIFT IN

SRLC16

4 A[3;0]

SHIFT-REG A[3:0] D MC15 WS DI D Q Registered Output Output

DI(BY) WSG CE(SR) CLK WE CK (Optional)

SHIF OUT or YB

Hnh 4-21. Cu trc ca thanh ghi dch trong FPGA Thanh ghi dch c th s dng ch a ch hoc khng. Khi mun m rng thanh ghi dch ch a ch th phi s dng thm cc Widemultiplexers, v d nh trong mt SLICEM, c th kt hp LUTG, LUTF ch thanh ghi dch to thnh 32-bit thanh ghi dch ch a ch nh hnh sau:

SRL16 LC A[3:0] SRL16 LC

F5MUX

A4

Hnh 4-22. M rng thanh ghi dch ch a ch 219

Tng t nh vy c th s dng F6MUX, F7MUX m rng kch thc ca thanh ghi dch ch a ch.
IN DI SRLC16 MC15 D FF

DI SRLC16

FF SLICEN S1

MC15 SHIFT OUT SHIFT IN DI SRLC16 MC15 SLICEN S0 DI SRLC16 MC15 CASCADABLE OUT
OUT

FF

FF

Hnh 4-23. M rng thanh ghi dch ch khng a ch Khi s dng thanh ghi ch khng a ch, ngha l thc hin dch 16 bit t D-flip-flop th nht cho n u ra MC15 vic m rng thanh ghi dch n gin l vic ni tip cc u ra ca thanh ghi dch trc vi u vo ca thanh ghi dch sau, v d SHIFTOUT ca CLB trn vi SHIFTOUT ca CLB di nh hnh v di y. Cng nh i vi Ram phn tn hay chui bit nh, thanh ghi dch c cc cng kt ni c ti u ha v mt tc lm vic, vic ghp ni cc thanh ghi 220

lin k khng gy ra tr ng truyn ln. Vic s dng thanh ghi dch trong Xilinx FPGA thng t ng nhng ngi cng c th ch ng khai bo s dng ty theo mc ch thit k. 2.2. Khi iu khin vo ra S nguyn l ca khi iu khin vo ra (Input/Output Block) trong Spartan 3E c trnh by nh hnh di y:

Hnh 4-24. S nguyn l ca khi m vo ra IOB

221

Cc khi Input/Output Blocks (IOB) trong FPGA cung cp cc cng vo ra lp trnh c mt chiu hoc hai chiu gia cc chn vo ra ca FPGA vi cc khi logic bn trong. Cc khi mt chiu l cc khi Input-only ngha l ch ng vai tr cng vo, s lng ca cc cng ny thng chim khng nhiu khong 25% trn tng s ti nguyn IOB ca FPGA. Hnh 4.24 m t s tng quan ca mt IOB, i vi cc khi Inputonly th khng c nhng phn t lin quan n Output. Mt IOB in hnh c ba ng d liu chnh, ng input, ng output, ng cng 3 trng thi (Three state path), mi ng ny u cha cc khi lm tr lp trnh c v cp phn t nh c kh nng lm vic nh Latch hoc D-flipflop. ng Input dn d liu t cc chn vo ra ca FPGA c th qua hoc khng qua khi lm tr kh trnh vo gi ti thng chn d liu I. ng Input th hai i qua cp phn t nh ti cc chn IQ1, IQ2. Cc chn I, IQ1, IQ2 dn trc tip ti phn logic bn trong ca FPGA. Khi s dng cc khi lm tr kh trnh th thng c cu hnh m bo ti u cho yu cu v gi tr hold time ca phn t nh. ng Output bt u ti cc chn O1, O2 c nhim v dn lung d liu t cc khi logic bn trong ti cc chn vo ra ca FPGA. ng dn trc tip l ng dn t O1, O2 qua khi chn knh ti khi dn 3 trng thi ti cc chn vo ra. ng dn th hai ngoi cc phn t trn cn i qua hai phn t nh. u ra cn c ni vi h thng pull-up, pull-down resisters t cc gi tr cng ra l logic 1 hoc 0. ng 3 trng thi xc nh khi no ng dn ra l trng thi tr khng cao. ng trc tip t cc chn T1, T2 ti khi iu khin 3 trng thi. ng gin tip i qua hai phn t nh trc khi ti khi iu khin 3 trng thi.

2.2.1. Cng vo vi tr kh trnh Mi mt ng d liu vo (input path) cha cc khi lm tr lp trnh c gi l programmable input delay block. Cc khi ny bao gm mt phn t lm tr th (Coarse delay) c th c b qua, khi ny lm tr tn hiu mc chnh xc va phi. Tip theo l chui 6 phn t lm tr c iu khin bi cc b chn knh. i vi ng vo ng b thng qua cc phn t nh ti IQ1, IQ2 th c th chn 3 mc lm tr. Cn i vi ng vo khng ng b ti cng I th c th thay i 6 mc lm tr. Tt c khi lm tr c th c b qua, khi tn hiu c gi ng thi ti cc chn ra ng b v khng ng b.

222

Hnh 4-25. Khi lm tr kh trnh Mt trong nhng ng dng ca khi lm tr l m bo khng vi phm iu kin ca Thold khi phn t nh hot ng (Thold l thi gian ti thiu cn gi n nh d liu sau thi im kch hot ca xung nhp ng b), v d nh hnh v sau:

Hnh 4-26. iu chnh u vo bng khi lm tr kh trnh 2.2.2. Cng vo ra ch DDR Khi nim DDR (Double Data Rate transmission) ch dng ng truyn d liu ng b tc gp 2 ln tc cho php ca xung nhp ng h bng cch kch hot ti c thi im sn ln v sn xung ca xung nhp. Vi c 3 ng d liu c trong IOB, mi ng u c mt cp phn t nh cho php thc hin truyn d liu theo phng thc DDR.

223

Hnh 4-27. Nguyn l DDR Hnh 4.27 th hin cc thc hin thc DDR trong FPGA. Hai phn t nh hot ng ch Flip-flop. u ra c ni vi Multiplexer DDR_MUX iu khin vo ra d liu. Cng mt thi im c hai xung nhp ng h lch pha nhau 180o gi ti u vo xung nhp CLK1, CLK2 vi chu k T ca Flip-flops. Gi s ti thi im sn dng ca tn hiu CLK1 Flip-Flop 1 hot ng, sau na chu k ti thi im sn m ca xung nhp CLK1 tng ng vi sn dng ca CLK2 th Flip-flop 2 lm vic. Nh vy chu k nhn/gi d liu l T/2 hay tc nhn gi d liu tng gp i. to ra hai xung nhp lch pha nhau c th dng khi DCM (Digital Clock Manager) t mt tn hiu xung nhp chun sinh ra tn hiu xung nhp th hai bng cch dch pha 180o(hnh bn tri). Phng php ny t c tr xung nhp (Clock skew) thp nht. Bn cnh phng php th hai nh m t hnh bn phi l dng cng o c trong IOB to lch pha 180o. 2.3. H thng kt ni kh trnh H thng kt ni kh trnh (Progammable Interconnects) ca FPGA dng lin kt cc phn t chc nng khc nhau bao gm IOB, CLB, Block RAM, khi nhn chuyn dng, DCM vi nhau. H thng kt ni ca FPGA c thit k cn bng gia yu t linh ng v tc lm vic (gim thiu tr do ng truyn gy ra). i vi cc FPGA h Spartan 3E c 4 loi kt ni sau: kt ni xa (long lines), kt ni kp (double lines), kt ni ba (hex lines), kt ni trc tip (direct line). Cc dng kt ni ny lin h vi nhau thng qua cu trc ma trn chuyn (switch matrix).

224

2.3.1. Ma trn chuyn Ma trn chuyn (Switch matrix) l cc khi thc hin kt ni gia cc dng ti nguyn kt ni ca FPGA bao gm kt ni xa, kt ni kp, kt ni ba, kt ni trc tip. lin kt (interconnect tiles) c nh ngha l mt khi bao gm ma trn chuyn v cc phn t chc nng ca FPGA nh IOB, CLB, Block RAM, Dedicated Multipliers, DCM.

Hnh 4-28. Cc thnh phn ni khc nhau trong Xilinx FPGA Vi CLB, IOB, DCM ch cn 1 ma trn chuyn to thnh mt kt ni nhng vi cc phn t ln hn nh Block RAM hay MULT18 th cn nhiu ma trn kt ni tng ng c s kt ni ln hn. 2.3.2. Cc dng kt ni Cc kiu kt ni c trong FPGA bao gm: Kt ni di - Long lines

Hnh 4-29. ng kt ni di ng kt ni xa gm t hp 24 ng ni 1 trong 4 CLB lin tip theo phng ngang hoc phng dc. T mi kt ni c 4 ng kt ni 225

thng qua ma trn chuyn ni vi cc cn li. ng kt ni xa c tr khng thp do vy thch hp cho nhng tn hiu ton cc kiu nh CLK hay Reset. Kt ni ba Hex lines

Hnh 4-30. ng kt ni ba Kt ni 3 l knh kt ni gm 8 ng ni ti 1 trong 3 CLB lin tip, i vi kt ni dng ny tn hiu ch c th truyn t mt u xc nh ti cc u khc theo hng mi tn nh trong hnh 4.30. Kt ni kp - Double lines

Hnh 4-31. ng kt ni kp Kt ni kp l knh kt ni gm 8 ng ni ti 1 trong 2 CLB lin tip, i vi kt ni dng ny tn hiu ch c th truyn t mt u xc nh ti cc im khc nh hex lines. S lng ca double lines trong FPGA ln hn nhiu so vi hai dng long lines v hex line do kh nng kt ni linh ng. Kt ni trc tip - Direct lines

Hnh 4-32. ng kt ni trc tip Kt ni trc tip kt ni cc CLB cnh nhau theo phng ngang, dc v cho m khng cn thng qua ma trn kt ni. 226

Vic phn cp cc ti nguyn kt ni trong FPGA tuy lm cho vic thit k bn thn FPGA phc tp hn cng nh tng phc tp cho thut ton kt ni ng truyn nhng gp phn rt ln vo vic tit kim din tch v ti u ha thit k trn FPGA. Trn thc t vic s dng ti nguyn kt ni trong FPGA c thc hin t ng, bn thn ngi thit k t tham gia vo qu trnh ny hoc nu c ch l to cc tn hiu ton cc kiu nh CLK, RS, TST s dng phn b c ti u ha ca cc tn hiu ny. 2.4. Cc phn t khc ca FPGA Ngoi cc thnh phn lit k hai phn trn, trong FPGA cn c tch hp thm cc phn t chc nng c bit khc, i vi Spartan 3E l Khi RAM (Block RAM), v khi nhn chuyn dng (Dedicated multiplier) 18 bit MULT18. Mt s nhng dng FPGA khc c tch hp thm DSP l khi nhn-cng 18 bit ng dng cho cc bi ton x l tn hiu s, mt s FPGA cn c nhng cng vi x l nh PowerPC 405, ARM c th lp trnh phn mm trc tip. 2.4.1. Khi RAM Bn cnh ngun ti nguyn lu tr d liu nh trnh by trn l RAM phn tn (Distributed RAM) vi bn cht l mt hnh thc s dng khc ca LUT th trong Xilinx FPGA cn c tch hp cc RAM (Block RAM) ring bit c cu hnh nh mt khi RAM hai cng, s lng ny trong Spartan 3E thay i t 4 n 36 ty theo tng IC c th. Tt c Block RAM hot ng ng b v c kh nng lu tr tp trung mt khi lng ln thng tin. Giao din ca mt Khi RAM nh sau:

Hnh 4-33. Giao din khi RAM Khi RAM c hai cng A v B vo ra cho php thc hin cc thao tc c ghi c lp vi nhau, mi mt cng c cc tn hiu xung nhp ng b, knh d liu v cc tn hiu iu khin ring. C 4 ng d liu c bn nh sau: 227

1. c ghi cng A 2. c ghi cng B 3. Truyn d liu t A sang B 4. Truyn d liu t B sang A. V tr ca cc Block RAM ny trong FPGA thng c b tr nh hnh sau:

Hnh 4-34. Phn b ca cc khi RAM trong Spartan 3E FPGA Ty theo tng FPGA c th m c th c t mt n 5 ct b tr Block RAM, cc ct ny thng c b tr bn cnh cng cc khi nhn 18-bit. 16-bit cng A phn thuc khi nh bn trn dng chung vi 16 bit cng A, tng t nh vy vi 16 bit cng B ca Block RAM c chia s vi 16 bit cng B ca khi nhn. V kch c ca cc khi RAM c th c cu hnh mt trong cc dng sau, nu k hiu M l s hng, W l s bt d liu, P l s bit kim tra chn l (Parity) trn mt hng Size = M x (W+P) bit Cu hnh 16K x 1 khng c bit kim tra chn l Cu hnh 8K x2 khng c bit kim tra chn l Cu hnh 4K x 4 khng c bt kim tra chn l Cu hnh 2K x (8+1), c 1 bit kim tra chn l Cu hnh 1K x (16+2) vi hai bit kim tra chn l Cu hnh 512 x (32+4) vi 4 bit kim tra chn l. Cch kim tra chn l nh sau, mi bit kim tra tng ng vi 1 byte hay 8 bit d liu, tnh chn l xc nh bng s ln xut hin bit 1 trong chui 8 bit. 228

V d nu cu hnh ca RAM l 1K x(16+2) c ngha l bit Pi l bit kim tra chn l ca Bytei nh hnh v di y..

Hnh 4-35. Parity bit calculation Block RAM trm thc t u l cc khi RAM hai cng nhng cc phn t tng ng c m t trong th vin chun ca Xilinx v c th c khi to hot ng nh RAM 2 cng (Dual-port RAM) hoc RAM 1 cng (Single-port RAM). Cc cng vo ra ca Block RAM c m t hnh v sau:

Hnh 4-36. Chi tit v khi RAM Tn gi ca cc RAM c t theo c php RAMB16_S(Wa)_S(Wb), trong Wa = W +P l tng rng knh d liu v s bit kim tra. RAM mt cng c tn tng ng RAM16_SW lc b i phn tn ca mt cng. V d RAM16B_S18_S9 ngha l RAM hai cng vi tng rng knh d liu cng A l 18 bit v cng B l 9 bit, RAM16B_S34 l khi RAM mt cng vi rng knh d liu l 34 bit. i vi Block RAM hai cng cc tn hiu vo ra c m t nh sau: CLKA, CLKB l xung nhp ng b cho cc cng A, B tng ng WEA, WEB l tn hiu cho php ghi vo cng A, B tng ng, ENA, ENB l tn hiu cho php cc cng A, B hot ng, SSRA, SSRB l cc tn hiu Set v Reset ng b cho cc u ra DOA, DOB,

229

 ADDRA, ADDRB [r-1] l knh a ch ca cc cng A, B tng ng trong gi tr R tnh bng cng thc: r = 14 log2(W) trong W l s bit ca knh d liu. DIA, DIB[W-1:0] l cc knh d liu voca cng A, B. DIPA, DIPB[p-1:0] l knh d liu kim tra chn l vo ca cng A, B. DOA, DOB[W-1:0] knh d liu ra ca cng A, B. DOPA, DOPB[P-1] knh d liu kim tra chn l ra ca cng A, B. i vi Block RAM mt cng tn cc tn hiu gi nguyn nh trn nhng b bt hu t A hoc B v ch c mt cng duy nht. 2.4.2. Khi nhn chuyn dng 18x18 Cc khi nhn chuyn dng 18bitx18bit (Dedicated Multiplier) c thit k ring, thng c ng dng trong cc bi ton x l tn hiu s, k hiu l MULT18X18SIO trong th vin chun ca Xilinx. Cc khi nhn c t ti cc v tr st vi cc Block RAM nhm kt hp hai khi ny cho nhng tnh ton ln vi tc cao. S lng ca cc khi ny bng vi s lng ca cc khi RAM trong FPGA, ngoi ra hai thnh phn ny cn chia s vi nhau cc cng A, B 16 bit dng chung.. Khi nhn trong Spartan 3E thc hin php nhn hai s 18 bit c du, kt qu l mt s 36 bit c du. Php nhn khng du c thc hin bng cch gii hn min ca s nhn v s b nhn (bit du lun bng 0). M t cc cng vo ra ca phn t nhn MULT18X18SIO th hin hnh sau:

Hnh 4-37. Cng vo ra ca khi nhn 18 bit Khi nhn c tt c 13 cng vo ra vi cc chc nng nh sau: A, B[17:0] l cng vo 18 bit s nhn v s b nhn. 230

 P[35:0] l 36 bit kt qu nhn (Product) CEA, CEB l tn hiu cho php xung nhp cc u vo A, B RSTA, RSTB, RSTP l cc cng Set/Reset ng b tng ng cho cc gi tr A, B, P. CLK l tn hiu xung nhp ng b cho cc Flip-flop trong khi nhn BCIN, BCOUT[17:0] l cc cng vo ra tng ng nhm chia s gi tr s b nhn gia cc khi nhn vi nhau nhm mc ch to thnh cc khi nhn nhiu bit hn. BCOUT = BCIN. Pipelined option: Khi nhn c th c thc hin nh mt khi t hp thun ty hoc c th chia nh bi cc thanh ghi t hiu sut lm vic cao hn. Cu trc pipelined ca khi nhn th hin hnh sau:

Hnh 4-38. Cu trc pipelined ca khi nhn Cc nhn t A, B v kt qu P c th c lu trong cc thanh ghi trung gian gm AREG, BREG, PREG, mi thanh ghi l mt chui cc Flip-flop. Trong cu trc pipelined th REGA, REGB c cng mc. Bn cnh kh nng cu trc dng pipelined tng tc cho php ton, cc khi nhn c th c kt hp vi nhau thng qua cng BCIN v BCOUT thc hin php nhn vi cc nhn t ln hn. V d khi tin hnh php nhn hai s 22 bit x 16 bit c th c thc hin theo s sau:

231

Hnh 4-39. Hin thc php nhn 22 x 16 bng khi nhn 18 bit thc hin php nhn trn s nhn 22 bt c phn tch thnh 4 bit thp v 18 bt cao, cc phn ny ln lt c gi ti mt khi nhn thng 16 bit x 4 bit v mt khi nhn 18bit x 18bit MULT18X18SIO. Kt qu hai php nhn khi nhn thng l mt s 20 bit trong 16 bt cao c gi ti b cng cng vi 34-bit kt qu t khi nhn MULT18X18SIO. Kt qu thu c bng cch ghp 4 bit thp vi 34 bit tng to thnh s 38-bit 2.4.3. Khi iu chnh xung nhp ng b Digital Clock Manager (DCM) l mt khi c bit trong FPGA c nhim v iu chnh v to ra xung nhp ng b (Clock) theo nhng yu cu c th ca bi ton. DCM c cu to khng n gin v c s lng hn ch (2-4 DCM trong Spartan 3E). 3 thao tc chnh m khi DCM c th thc hin l: - Loi b tr gia cc xung Clock cc v tr khc nhau (Clock Skew Elimination). Xung ng b gi ti cc thnh phn khc nhau trong FPGA c th khng n ng thi do s khc bit v ti ng truyn. DCM c kh nng tng cc gi tr Thold, Tsetup ca xung ng b v thi gian t im kch hot cho ti khi u ra n nh Tclk_q ng nht cc xung ng b. Trong cc bi ton i hi lm vic vi tn s cao th y l mt trong nhng thao tc khng th b qua. - Tng hp tn s (Frequency Synthesis): Tng hp tn s y bao gm nhn v chia tn s, vi tn s c nh u vo DCM c th thc hin thao tc nhn tn s vi 1 s M, chia cho mt s D hoc ng thi nhn v chia M/D. y l mt kh nng c bit quan trng cho nhng bi ton yu cu tn s lm vic l c nh nh iu khin VGA, DAC, ADC, LCD - Dch pha (Phase shifting) Dch pha ca xung nhp ng b i 0, 90, 180, hoc 270 .

232

Hnh 4-40. S khi DCM Khi DCM c cu to t 4 khi chnh, khi dch pha PhS (Phase shifter), khi lp kha pha DLL (Delay Locked Loop), khi tng hp tn s DFS (digital Frequency Synthesis) v khi Trng thi logic ca DCM. Khi DLL: Khi DLL c cu to bi mt chui cc phn t lm tr m thc cht cc khi m. DLL c u vo xung nhp CLKIN, u vo CLKFB (CLOCK FEEBACK), xung nhp ny s c s dng so snh pha khi Phase detection thc hin iu chnh pha thng qua mt vng lp hi tip dng, ty thuc vo cu hnh ci t m CLKFB c th l u ra CLK2X hoc CLK0 (y cng l c im khc bit gia DLL v PLL).

233

Hnh 4-41. S khi DLL DLL c 7 u ra xung nhp CLK0, CLK90, CLK180, CLK270, CLK2X (nhn i tn s), CLKDV (chia tn) v mt u ra LOCKED bo hiu khi pha gia CLKFB v CLKIN trng nhau. Khi DLL c cc tham s nh sau: Bng 4-3 Khi DLL Tham s ngha CLOCK_FEEDBACK La chn xung nhp phn NONE : khng hi so snh pha 1X: CLK0 2X: CLK2X CLKIN_DIVIDE_BY_2 Chia i tn s xung TRUE : c chia CLKIN FALSE : khng chia CLKDV_DIVIDE Gi tr chia tn Nhn cc gi tr 1.5, 2, 2.5,3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5,7, 7.5, 8, 9, 10, 11, 12, 13, 14,15 CLKIN_PERIOD Thng tin b xung vChu S thc biu din tn k CLKIN u vo theo s u vo [ns]

234

Khi tng hp tn s DFS c th c thc hin c lp hoc trn nn tng ca DLL, chi tit xem thm trong ti liu ca Xilinx. DFS c u vo l CLKIN v hai u ra l CLKFX v CLKFX180, trong CLKFX = CLKIN * M/D Cn CLKFX180 l CLKFX b dch pha 180 . M l h s nhn, D l h s chia c nh ngha khi ci t DCM bi cc tham s tng ng CLKFX_MULTIPLY (gi tr nguyn t 2-32) v CLKFX_DIVIDE, (gi tr nguyn t 1 32). Khi dch pha PS: Bn thn DLL cung cp cc u ra vi lch pha chun ln lt l 0, 90, 180, 270, ngoi ra trong DCM cn c khi PS cho php tinh chnh lch pha ca tn hiu CLKIN v CLKFB vi phn gin (-255 + 255) trn min (-360 + 360) nh hnh sau.

Hnh 4-42. S khi dch pha Trong ch khng dch pha th CLKIN v CLKFB ng pha, trong ch dch pha th CLKFB c th lch so vi CLKIN mt i lng pha tng ng tPS= P/256 * TCLKIN. Khi CLKFB v CLKIN lch pha th s dn ti s lch pha tng ng ca tt c cc u ra k trn. Cc tham s v tn hiu ca khi dch pha lit k hai bng sau:

235

Bng 4-4 Tham s ca khi dch pha Tham s ngha Ghi ch CLOCK_OUT_PHASESHIFT Chn ch dch pha NONE : khng FIX: dch pha Gi tr dch pha S nguyn t -255 PHASE_SHIFT n +255 Cc tn hiu ca khi dch pha bao gm: Bng 4-5 Tn hiu ca ca khi dch pha Tham s ngha Ghi ch PSEN Tn hiu cho php dch pha Tn hiu khng ng b Tn hiu ng b cho khi PS Xung ng b PSCLOCK Khi bng 1 th tng gi tr dch Tn hiu thay i ng PSINCDEC pha, khi bng 0 th gim gi tr b bi PSCLOCK dch pha Bo hiu qu trnh ng b pha PSDONE kt thc.

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3. Quy trnh thit k FPGA bng ISE

Trong chng trnh ca in t s cc mch s sau khi xc nh c chc nng th s tin hnh tng hp mch trn cc cng logic c bn kt thc bng xy dng s logic cho mch. Vi kch thc va phi th bc tng hp mch c th lm bng tay. Tuy vy qu trnh tng hp mch s trong chng trnh nghin cu y y rt phc tp do kch thc thit k ln (c hng trm nghn cng) nn thc hin trn giy bt l khng th m phi thc hin nh s tr gip ca phn mm my tnh. Cc phn mm ny bn thn c tch hp nhng thut ton tng hp t n gin ti phc tp v trn l thuyt c th tng hp cc vi mch s vi kch thc bt k. Ni mt cch khc khi c cc bn thit k VHDL cho chc nng ca mch nh cc chng trc th quy trnh bin thit k thnh mch lm vic gn nh t ng hon ton. Mt trong nhng yu t gp phn vo s thnh cng ca FPGA phi k n l c mt quy trnh thit k n gin, hon thin c thc hin bng cc b phn mm chuyn dng. Cc phn mm ny c tch hp nhiu cc thut ton x l ti u khc nhau nhm tng tnh t ng ha cho quy trnh thit k. Ni dung ca nhng phn di y c vit da trn c s cc bc thit k FPGA bng t hp phn mm Xilinx ISE (Integrated Software Enviroments). tm hiu k hn ngi c c th tham kho thm cc ti liu gc c trn trang ch ca Xilinx. C mt s im khc nhau cho tng loi FPGA hay cho FPGA ca tng hng nhng quy trnh thit k IC s s dng FPGA chung u c th chia thnh nm bc th hin s di y:

237

Hnh 4-43. Quy trnh thit k trn FPGA 3.1. M t thit k Sau khi c s thut ton chi tit, tin hnh m t chc nng vi mch ngi thit k c th s dng mt s phng php khc nhau nh trnh by di y. Khi chn m t bng s (schematic) th ISE cung cp mt th vin cc phn t di dng ha (graphic symbols) nh cc khi cng, tr, buffer, thanh ghi, khi nhn, RAM, cng vo ra Ngi thit k s s dng cc phn t ny v thc hin kt ni trn s to thnh mch hon chnh. M t theo s tuy r rng nhng khng ph hp cho nhng thit k phc tp. i vi nhng thit k ln th nn s dng phng php m t bng ngn ng HDL, c hai dng HDL l HDL do ngi dng thit k, l dng m t trung tnh c th s dng cho bt k i tng phn cng no m chng ta tng thc hin nhng chng trc. R rng vi u im nh vy th trong thit k ta nn tn dng ti a dng thit k ny. 238

Bn cnh dng m t HDL ca ngi dng th c dng m t HDL th hai s dng cc khi thit k c sn. Loi m t ny c hai dng, th nht l cc khi thit k c nh ngha trong th vin UNISIM ca Xilinx. Khi mun ci t cc khi ny th phi khai bo thm th vin Unisim u thit k:
library UNISIM; use UNISIM.VCOMPONENTS.all;

Mt s khi thit k in hnh l cc LUT, thanh ghi dch, Block RAM, ROM, DCMc th tm thy trong Language template ca ISE, cc khi ny gi chung l cc phn t c bn ca FPGA (FPGA primitives), c im ca cc khi ny l ph thuc vo i tng FPGA c th.
FPGA FUNCTIONAL DESIGN

USERs HDL

SCHEMATIC

Reused BLOCK (Templates, IP Cores)

Hnh 4-44. Cc dng m t thit k trn FPGA Ngoi FPGA primitives th ISE cho php ngi dng s dng mt s khi thit k sn dng IPCore (Intellectual Property core). IP core l cc khi thit k sn c ng k s hu tr tu v thng l cc thit k kh phc tp v d nh cc khi FIFO, khi lm vic vi s thc (Floating Point Unit), khi chia, cc khi CORDIC, cc khi giao tip Ethernet, PCI EXPRESS, SPI, cc khi x l s tn hiu Trong khun kh chng trnh hc th vic s dng ny l c php tuy vy nu mun s dng cc khi ny vi mc ch to ra sn phm ng dng th cn xem xt k vn bn quyn. Vi s h tr phong ph ca cc IP Cores ny cho php thc hin nhng thit k ln v hu dng trn FPGA. Lu l khi s dng cc khi ny th phn thit k HDL thc s cng b giu i m chng trnh ch cung cp cc m bin dch v m t giao din (wrapper file) ca IPCore c s dng. 3.2. Tng hp thit k Qu trnh tng hp FPGA (FPGA Synthesis) bng chng trnh ISE bao gm cc bc nh sau. 239

LOGIC SYNTHESIS

CHECK SYNTAX & SYNTHESIS

GENERATE NETLIST

CREATE TECHNOLOGY SCHEMATIC

CREATE RTL SCHEMATIC

Hnh 4-45. Tng hp thit k FPGA trn Xilinx ISE Check Syntax & Synthesis: Trc khi thit k c tng hp th m ngun VHDL c bin dch v kim tra trc. Nu xut hin li c php m ngun th qua trnh tng hp s dng li. Nu m t VHDL khng c li th chuyn sang bc th hai l tng hp (synthesis). Tng hp thit k l chuyn m t t mc tru tng cao (con ngi c th c hiu) xung mc tru tng thp hn (my tnh mi c kh nng c hiu). i vi FPGA qu trnh tng hp logic l qu trnh bin dch t m t chc nng sang m t cng (netlist). M t cng bn cht vn l cc m t VHDL nhng s dng cc phn t ca FPGA, hiu mt cch khc nu m t chc nng l s nguyn l th m t netlist l s chi tit ha s nguyn l. C th so snh m di dng Netlist nh m Assembly ca chng trnh gc m t bng cc ngn ng lp trnh bc cao C/C++, Pascal, Basic... Cc m ngun VHDL c chia thnh hai dng l tng hp c (Synthesizable code) v khng tng hp c (Simulation-only code), vic phn bit hai dng m ngun ny c ISE lm t ng. Khi c tnh tng hp mt cu trc ch dng cho m phng th s gy ra li. Ngi thit k v vy ngoi vic m bo chc nng lm vic ng cho mch cn lun phi m bo rng nhng cu trc vit ra l nhng cu trc c th to thnh mch tht ngha l tng hp c. im ng lu ti thi im ny l qu trnh tng hp bao gm c qu trnh ti u logic cho thit k, v d nu chng ta s dng b tr lm php so snh nhng v thc cht so snh hai s ch cn thit lp bt nh cui cng ca php tr m khng cn quan tm n bn thn gi tr thu c ca php tnh. Chnh v vy sau khi tng hp ta nhn c cnh bo (Warning) t chng trnh.
Xst:646 - Signal <sub<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

240

Tt c nhng tn hiu tha s b b i sau khi tng hp nhm tit kim ti nguyn FPGA, nu mun b cnh bo ny chng ta c th thay i thit k ca b so snh bng cch m t chi tit chui nh thay v dng c b cng/tr 4 bit. Nhng cnh bo dng ny thuc dng v hi v n khng nh hng ti chc nng ca mch. Tuy vy kinh nghim thc t cho thy trong mi trng hp vic kim tra cc cnh bo l cc k cn thit v mt thit k c bin dch v m phng ng rt c th chc nng ca mch b thay i do vic ti u (ct b cc tn hiu b coi l tha), hoc nh nhng cnh bo ny c th tm ra nhng sai st trong thit k nguyn l, nht l vi nhng thit k ln v phc tp. Synthesis report: Kt qu tng hp c ghi di dng mt tp vn bn, trong thng k v cc phn t logic, cc phn t nh, s LUT, s cng vo ra (IO_BUF) v tham s v mt thi gian, v d kt qu tng hp nh sau:
====================================================== * Final Report * ====================================================== Final Results RTL Top Level Output File Name : sp3_led.ngr Top Level Output File Name : sp3_led Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Device utilization summary: --------------------------Selected Device : 3s500epq208-4 Number of Slices: 4 out of 4656 0% Number of 4 input LUTs: 8 out of 9312 0% Number of IOs: 16 Number of bonded IOBs: 16 out of 158 10% ===================================================== TIMING REPORT Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.320ns

Khi phn tch kt qu tng hp cn lu hai thng tin c bn. Th nht l thng tin v ti nguyn, trong bo co s lit k cc dng ti nguyn v s lng ca tng loi c s dng cho ton khi thit k (Device utilization summary). Thng tin ny trong mt s trng hp cn gip ngi thit k kim nh li s 241

 thut ton ban u bng cch so snh gia ti nguyn thc t sau tng hp vi ti nguyn c tnh s b ban u. Thng tin th hai l thng tin v mt thi gian, theo ngm nh thit k s c ti u vi tiu ch u tin l gim ti a thi gian tr (Optimization Goal : Speed). Cc thng tin thi gian c lit k bao gm thi gian tr t hp (combinational delay) v chu k ca xung nhp (Clock informations) nu c. Trong bo co cng s lit cc ng gy tr cc i (Critial paths), cc thng tin ny c th gip ngi thit k ti u ha li m t VHDL hoc thut ton t c tr thp hn mt cch hiu qu. Kt xut m t netlist: m t netlist l m t VHDL ca thit k nhng c nh x ln th vin phn t logic ca FPGA. M t netlist l dng m t mc cng v vy khng m t trc quan c chc nng ca vi mch m ch th hin c cu trc ca mch, trong cc khi con (components) l cc phn t c bn c m t trong th vin UNISIM ca FPGA. V d mt m t netlist c dng nh sau:
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity sp3_led is port ( LED1 : out STD_LOGIC; LED2 : out STD_LOGIC; ... SW7 : in STD_LOGIC := 'X'; SW8 : in STD_LOGIC := 'X'); end sp3_led; architecture Structure signal LED1_OBUF_1 : signal LED2_OBUF_3 : ... signal SW7_IBUF_29 : signal SW8_IBUF_31 : begin LED81 : LUT2 generic map( INIT => X"1" ) of sp3_led is STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;

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port map ( I0 => SW8_IBUF_31, I1 => SW7_IBUF_29, O => LED8_OBUF_15); ... LED8_OBUF : OBUF port map ( I => LED8_OBUF_15, O => LED8); LED51_INV_0 : INV port map ( I => SW5_IBUF_25, O => LED5_OBUF_9); end Structure; ----------------------------------------

Netlist c th khng phn nh ng bn cht thc t ca mch m m t ny ny ch s dng kim tra li chc nng ca vi mch sau khi nh x ln th vin phn t FPGA. Vic kim tra ny c thc hin ging nh kim tra m t VHDL ban u, tc l c th dng bt k chng trnh m phng logic no m h tr th vin UNISIM. Create Technology schematic (S cng ngh chi tit) Sau khi tng hp chng trnh cng cho php kt xut s cng ngh chi tit ca thit k m bn cht l m t trc quan bng hnh nh ca netlist, v d mt s cng ngh chi tit hnh sau:

Hnh 4-46. S cng ngh Vic so snh s ny vi s nguyn l bc ban u cho php kim tra trc quan s b vic thc hin ng s nguyn l ca m t VHDL. 243

Create RTL schematic (S logic chi tit) S logic chi tit l s th hin chc nng ca thit k s dng cc cng logic chun nh AND, OR, NOT, FFD thay v s dng cc phn t chun ca FPGA, s ny v th khng ph thuc vo i tng cng ngh c th.

Hnh 4-47. S logic 3.3. Hin thc ha thit k Hin thc ha thit (Implementation) k FPGA l qu trnh chun b d liu cho vic cu hnh FPGA t thng tin u vo l m t netlist. Qu trnh ny bt u bng qu trnh bin dch v nh x thit k ln i tng FPGA cho ti khi thit k vt l c phn b c th v kt ni vi nhau Qu trnh gm 3 bc nh sau:
TRANSLATE Post-translate simulation model

IMPLEMENTATION

Post-translate simulation model MAPING Post-translate simulation model Post-translate simulation model PLACE & ROUTE Post-translate simulation model

Hnh 4-48. Qu trnh hin thc ha FPGA 244

3.3.1. Translate Netlist ca chng trnh c dch thnh nh dng EDIF (Electronic Device Interchangeable Format) hoc NGC format (mt nh dng netlist ring ca Xilinx) sau kt hp vi hai file quy nh iu kin rng buc ca thit k. - NCF (Native Constraint File) cha nhng thng tin vt l v thi gian, tc , cc tham s ti, tham s vt l k sinh ca chip vt l FPGA l i tng s tin hnh cu hnh. - UCF (User Constraint File) cha nhng rng buc yu cu t pha ngi thit k vi vi mch ca mnh. UCF c xem l mt phn quan trng trong thit k, nu nh m t chc nng ch quy nh vi mch nh lm g th trong file UCF s cha nhng yu cu i hi v tc lm vic (timing constraint) cng nh mc s dng ti nguyn. Cc yu cu ny l c s cho cc trnh bin dch trong ISE ti u ha thit k. c th vit c nhng yu cu ny th ngi thit k trc ht phi hiu rt r thit k ca mnh, chng hn trong thit k c dng nhng tn hiu xung nhp nh th no, khu vc t hp no c kh nng gy ra thi gian tr ln nht v c tnh c gi tr ca tr. Phn tch ni dung mt file UCF c ni dung nh di y.
# IO location defination NET "HIGH_voltage" LOC = P102; NET "LOW_voltage" LOC = P100; NET "voltage[0]" LOC = P160; NET "voltage[1]" LOC = P161; NET "voltage[2]" LOC = P162; NET "voltage[3]" LOC = P163; # Timing constraint INST "LOW_voltage" TNM = "OUT_REG"; INST "HIGH_voltage" TNM = "OUT_REG"; NET "voltage[0]" OFFSET = IN 2 ns VALID "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[1]" OFFSET = IN 2 ns VALID "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[2]" OFFSET = IN 2 ns VALID "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[3]" OFFSET = IN 2 ns VALID "CLK" TIMEGRP "OUT_REG" RISING;

0.5 ns BEFORE 0.5 ns BEFORE 0.5 ns BEFORE 0.5 ns BEFORE

Nhm m t th nht quy nh cch gn chn vo ra ca FPGA, cch gn chn ny ph thuc th nht vo tng loi FPGA, th hai vo bn mch ng dng FPGA c th, chng hn nh trn cc chn voltage c gn cho cc 245

cng t P160 n P163, cn hai tn hiu LOW_voltage v HIGH_voltage c gn cho chn P102 v P100. Nhm th hai m t iu kin rng buc v mt thi gian: hai lnh u ghp hai Flip-flop u ra ca mch thnh mt nhm c tn l OUT_REG, 4 lnh sau quy nh thi gian tr ca 4 tn hiu u vo c thi gian:
OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING

ngha l thi gian tr ca cc tn hiu ny trc khi n cc Flip-Flop ca nhm OUT_REG khng qu 2 ns v thi gian gi tn hiu n nh cho Flip-Flop (Setup time) khng qus 0,5 ns. Xilinx ISE h tr trnh son tho vi giao din ha cho UCF tuy vy c th s dng trnh son tho Text bt k son file UCF, yu cu duy nht l t tn file UCF trng vi tn thit k. (*) Chi tit hng dn v UCF c th xem trong ti liu hng dn ca Xilinx http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf
LOGIC SYNTHESIS (NCD or EDIF files)

Native Constraint File (NCF)

User Constraint File (UCF)

TRANSLATE

Native Generic Database (NGD)

Hnh 4-49. Qu trnh bin dch Qu trnh translate s c cc thng tin t 3 file trn v chuyn v nh dng NGD (Native Generic Database) ca Xilinx phc v cho hai bc k tip l Mapping v Routing. NGD bn cht l mt m t cu trc ca mch trn c s cc phn t chc nng c m t trong th vin c tn SIMPRIM (simulation primitves) ca Xilinx. Cc phn t ny khng ph thuc vo FPGA c th, n c th c s dng cho tt c cc dng FPGA v CPLD ca Xilinx. 246

Ngi thit k c th to ra file netlist phc v m phng kim tra sau Translate (Post-translate simulation model). V d file netlist nh sau:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity sp3_led is port ( LED1 : out STD_LOGIC; LED2 : out STD_LOGIC; ... SW7 : in STD_LOGIC := 'X'; SW8 : in STD_LOGIC := 'X' ); end sp3_led; architecture Structure of sp3_led is signal LED1_OBUF_1 : STD_LOGIC; signal SW8_IBUF_31 : STD_LOGIC; begin LED81 : X_LUT2 generic map( INIT => X"1" ) port map ( ADR0 => SW8_IBUF_31, ADR1 => SW7_IBUF_29, O => LED8_OBUF_15); ... SW8_IBUF : X_BUF port map ( I => SW8, O => SW8_IBUF_31); LED51_INV_0 : X_INV port map ( I => SW5_IBUF_25, O => LED5_OBUF_9); LED8_OBUF : X_OBUF port map ( I => LED8_OBUF_15, O => LED8); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR);

247

NlwBlockTOC : X_TOC port map (O => GTS); end Structure;

3.3.2. Maping Mapping l ng tc gn cc khi s logic vo cc khi c s ca mt FPGA c th, u vo ca qu trnh l d liu c lu trong file NGD bao gm m t logic s dng cc phn t chc nng c lp vi cng ngh c trong th vin SIMPRIM v cc thng tin v cc khi, ng kt ni c nh. u ra ca qu trnh ny l mt file dng NCD (Native Circuit Database), file ny cha m t chc nng mch thit k trn i tng FPGA c th. Qu trnh maping tri qua cc bc c s nh sau. - c thng tin ca i tng FPGA. - c thng tin thit k t file NGD. - Thc hin DRC (Design Rule Check) Kim tra thit k bao gm: kim tra khi (Block check) l kim tra s kt ni ca cc khi, kim tra s tn ti ca cc m t khi con. Kim tra cc ng ni logic (Net check) bao gm kim tra cc khi u vo u ra v vic tun th cc quy tc ni cc u vo u ra . Ngoi ra cn c cc kim tra khc nh kim tra cc v tr vo ra (PAD check), kim tra cc khi m cho tn hiu ng b (Clock buffer check), kim tra s trng lp tn gi(Name check). - Nu nh bc DRC khng pht sinh ra li th qu trnh maping c thc hin tip tc, bc ny s tin hnh lc b cc phn t tha trong thit k v nh x cc khi thit k ln cc khi chc nng ca i tng FPGA c th - To ra mt file cha cc iu kin rng buc ca m t vt l ca mch sinh ra bi bc trn PCF (Physical Constrait File), vi ni dung l tp hp tt c cc iu kin rng buc ca thit k cp cng (NCF, UCF) v i tng FPGA c th. - Thc hin DRC vi thit k nh x, nu DRC bc ny khng gy ra li th s thc hin bc cui cng l to ra file NCD. 3.3.3. Place and Routing Placing & Routing (PAR) l qu trnh nh x nhng khi logic c phn chia phn Maping sang nhng khi logic (LUT, IOBUF) c v tr c c 248

th trn FPGA v kt ni chng li vi nhau thng qua khi ti nguyn kt ni . ngi thit k c th can thip vo qu trnh ny bng FPGA editor, mt cng c giao din ha tch hp trong ISE, nhng trn thc t th qu trnh ny thng thc hin hon ton t ng bng cng c PAR (Place and Route). Hnh di y minh ha cho qu hai qu trnh trn.

Hnh 4-50. Phn b v kt ni Placing: bc ny PAR la chn cc khi logic chc nng c th phn b trn FPGA gn cho cc khi chc nng trn m t thit k, vic la chn da trn cc tiu ch nh ngun ti nguyn, di kt ni, iu kin rng buc trong PCF file Qu trnh ny thc hin thng qua mt s pha, kt thc mi pha th thit k c ti u thm mt mc, kt thc Placing mt kt qu NCD mi c to ra. Routing: l qu trnh tin hnh s dng cc ti nguyn kt ni (interconnects), cc kt ni c thc hin nhm t thi gian tr thp nht c th, khi kt ni PAR s phi quan tm ti thng tin trong PCF file. Qu trnh ny cng c thc hin thnh nhiu pha, mi pha mt file NCD mi s c lu li nu nh c c s ti u v thi gian so vi phng n trc . Floorplaning: L qu trnh cho php ngi thit k s dng FPGA editor can thip vo qu trnh Placing v Routing, bc ny c th lm trc hoc sau cc bc ca PAR. 249

3.4. Cu hnh FPGA Sau khi thit k c hin thc ha bc 3.3 th c th thc hin cu trc FPGA (FPGA Configuration), qu trnh cu trc nh trnh by phn 2 l vic ghi d liu vo SRAM, d liu ny s quy nh cch thc lm vic, kt ni ca cc phn t trong FPGA. Thit k c dch sang 1 file cu hnh (BIT file) v np vo trong FPGA thng qua giao thc JTAG. File BIT ny cng c th c bin i thnh cc nh dng PROM khc nhau np vo trong ROM, khi cn s c c ti cu trc FPGA m khng cn phi np li t my tnh. 3.5. Kim tra thit k trn FPGA Thit k trn FPGA c th c kim tra nhiu mc khc nhau v c chc nng ln v cc yu cu khc v mt ti nguyn hay hiu sut lm vic.
VERIFICATION

FUNCTION

TIMING

ON-CIRCUIT TESTING

Hnh 4-51. Kim tra thit k FPGA 3.5.1. Kim tra bng m phng. Cc cng c m phng c th dng m phng chc nng (Functional Simulation) ca mch thit k v m phng v mt thi gian (Timing simulation). Kim tra c th c thc hin t bc u tin ca qu trnh thit k (m t VHDL) cho ti bc cui cng (PAR). - Sau khi c m t bng VHDL thit k cn c kim tra k v mt chc nng ti thi im ny trc khi thc hin cc bc bn di. - Kim tra sau tng hp: mt m t netlist sau tng hp (post-synthesis simulation model), th vin UNISIM c to ra phc v cho qu trnh kim tra sau tng hp. kim tra thit k ny trnh m phng cn c m t tng ng ca th vin UNISIM, nu c pht sinh li v mt chc nng th phi quay li bc m t VHDL sa li. - Kim tra sau Translate: m t netlist sau translate (post-synthesis simulation model) l m t trn th vin SIMPRIM. Chng trnh m phng cng phi cn c tch hp hoc h tr th vin SIMPRIM. 250

Kim tra sau Map: m t netlist sau translate (post-map simulation model, v post-map static timing) l m t trn th vin SIMPRIM, th vin ny c tham s m t v mt thi gian thc v k t bc ny ngoi m phng kim tra v mt chc nng th thit k c th c kim tra cc tham s chnh xc v mt thi gian. Kim tra sau Place and Route: Tng t nh kim tra sau Mapping, im khc l m phng kim tra cc tham s thi gian tnh y c chnh xc gn vi mch tht trn FPGA nht.

3.5.2. Phn tch tham s thi gian tnh. Phn tch thi gian tnh (Static timing analysis) cho php nhanh chng xc nh cc tham s v mch thi gian sau qu trnh Place & Routing, kt qu ca bc kim tra ny cho php xc nh c hay khng cc ng truyn vi phm cc iu kin rng buc v mt thi gian, ch ra cc ng gy tr vi phm ngi thit k tin hnh nhng thay i ti u mch nu cn thit. 3.5.3. Kim tra trc tip trn mch Kim tra trc tip trn mch (On-circuit Testing) l qu trnh thc hin sau khi cu hnh FPGA c np vo IC, i vi nhng thit k n gin th mch c np c th c kim tra mt cch trc quan bng cc i tng nh mn hnh, LED, switch, cng COM. Vi nhng thit k phc tp Xilinx cung cp cc cng c phn mm kim tra ring. ChipScope l mt phn mm cho php kim tra trc tip thit k bng cch nhng thm vo trong khi thit k nhng khi c bit c kh nng theo di gi tr cc tn hiu vo ra hoc bn trong khi cu hnh c np v lm vic. ChipScope s dng chnh giao thc JTAG giao tip vi FPGA. Vic thm cc khi g ri vo trong thit k lm tng kch thc v thi gian tng hp thit k ln ng k. Chi tit hn v cch s dng Chipscope Pro c th xem trong ti liu hng dn ca Xilinx. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/chips cope_pro_sw_cores_11_1_ug029.pdf

4. Mt s v d thit k trn FPGA bng ISE

S mt khi thit k chun trn FPGA c th chia thnh cc khi chnh nh hnh v sau:

251

iu khin ngoi vi u vo (Bn phm, switch, line)

KHI X L CHNH (CORE FUNCTION) Adder, Multiplier, MAC, ALU, FPU, Memory...

iu khin ngoi vi u ra (LCD, VGA, LED, line)

Hnh 4.52. S khi thit k y trn FPGA Khi x l chnh c th l bt k khi thit k logic chc nng no chng ta thc hin nhng chng trc, lu rng nhng thit k c cp trong gio trnh hu ht ch chim rt t trn tng s ti nguyn ca FPGA. Khi iu khin ngoi vi chia thnh khi ngoi vi u vo v u ra. Ty c tnh tng loi m phc tp khi thit k s khc nhau. Cc v d trnh by di y l nhng v d thin v cc giao tip c bn trn mch FPGA. Tt c u c c tng hp v kim tra trn mch pht trin ng dng FPGA ca b mn k thut Xung, s, vi x l (c hnh v i km). Trn c s cc v d ny ngi hc c th thc hin np cc thit k chc nng nghin cu t nhng chng trc vi ty bin u vo u ra bng cc ngoi vi c sn to nn nhng thit k hon chnh v c th kim tra cc thit k trn mch thc t.

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POWER SUPPLY

XCF04 Platform Flash LED0

P144 P145 P146 P147 P150 P151 P152 P153

EXPANSION
DIP SWITCH
P106 P107 P108 P109 P112 P113 P115 P116 P98 P99 P100 P102

ADC/DAC

SWITCH1

LED1

SD/MMC holder

P119 P120 P122 P124 P126 P127 P128 P129

P160 P161 P162 P163 P164 P165 P167 P168 P171 P172 P177 P178 P179 P180 P181 P185 P190 P192 P193 P196

P97 P96 P90 P94 P93 P84 P83 P82 P78 P89

PS/2

XILINX SPARTAN 3E XC3S500E

48MHZ
P75 P74 P68 P65 P64 P64 P62 P61

VGA

P200 P199 P202 P203

LCD1602A

KEYPAD

CAN connector

USB connector

Ethernet connector

Hnh 4-53. S mch th nghim FPGA Trong mch s dng IC FPGA Spartan 3E XCS500K, Flash ROM XFC04 vi 4M cho lu tr c nh cu hnh. Mch c np thng qua giao thc chun JTAG. Cc ngoi vi h tr bao gm: Khi to xung nhp tn s 48Mhz, H thng cc 7 phm n a chc nng, 2 khi Switch 8-bit, 2 khi Led 8-bit, Led 7 on vi c kh nng hin th 4 k t s, 2 cng giao tip PS/2, cng giao tip RS232, cng giao tip USB-RS232, cng giao tip VGA, mn hnh LCD1602A hin th cc k t vn bn, cng giao tip CAN, cng giao tip Ethernet, khi AD/DA s dng IC PCF8591. Mch dng mt ngun ngoi duy nht 5V vi dng ti thiu 1A. Chi tit v mch pht trin ng dng FPGA xem trong ph lc 3. 4.1. Thit k khi nhn thng tin UART UART l khi thc hin giao thc truyn tin d b ni tip (Universal Asynchronous Receiver/Transmitter), c im giao thc ny l n gin, ph bin, nhc im l tc trao i thng tin hn ch. Trong v d di y ta s 253

RS232

P50 P49 P48 P47 P45 P42 P41 P40

P11 P9 P8 P5 P4

P19 P18 P16 P15

P33 P31 P30 P29

P39 P36 P35

P28 P25 P24 P23

minh ha mt thit k s dng FPGA cu hnh mt khi nhn thng tin ni tip UART. hiu v thit k ny trc ht ta tm hiu qua v giao thc truyn nhn thng tin ni tip. Thng tin ni tip c truyn theo mt dy dn duy nht v cc bit thng tin c m ha theo mc in p trn dy dn.
IDLE RX START DATA PARITY STOP IDLE

Tbraud

Bit counter

3 SAMPLE

ONE BIT RECEIVING RX Sample counter 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

Hnh 4-54. Giao thc truyn tin d b ni tip Hnh trn m t tn hiu u vo cho mt khi nhn tn hiu t ng truyn ni tip, trng thi ngh (IDLE), khng c d liu th tn hiu c gi mc cao, bt u truyn thng tin tn hiu Rx s chuyn v mc thp trong mt khong thi gian ln, thi gian ny bng thi gian nhn 1 bit thng tin tng ng vi tc truyn ca cng gi l Tbraud. = 1/Fbraud. Sau bit START ny th cc bit d liu c truyn ni tip trn Rx, tng ng trng thi DATA trn hnh v, cng COM c th c cu hnh truyn nhn 6, 7 hay 8 bit thng tin. Sau khi kt thc truyn cc tin ny c th c thm mt bit kim tra chn l ca khi tin PARITY, mt bit STOP (mc logic 1) c gi vi thi gian bng 1, 1.5 hay 2 Tbraud. Khi kt thc qu trnh truyn tin th Rx tr v trng thi ngh mc in p cao. ng truyn ni tip n gin v tc khng cao, thng thng Fbraud thay i t 1200 n 115200 Bit/s. ng truyn ny s dng cc thit b c lp vi nhau v b nh hng ca nhiu khng nh, mt khc b nhn v b chia hot ng khng ng b (khng cng xung nhp h thng) do cn phi c c ch thu nhn nhm trnh li pht sinh. C ch cng c minh ha trn hnh 4.49. Mt bit thng tin c chia thnh 16 im ly mu (Samples), cc im ny c xc nh bng mt b m mu (sample counter). V xc sut li 254

 cc v tr mu u v cui l cao nht cn xc sut li v tr gia l thp nht do ta chn im ly mu gia, ngha l bit thng tin ang nhn bng Rx trng thi counter = 8. Vi tc cao nht c th l 115200 Bit/s th tn s ca b m ly mu bng 115200 x16 = 1 843 200 Hz < 2Mhz vn l mt tc khng cao i vi cc thit k s trn FPGA. Trn thc t cng khng phi lc no cng phi chia bit thng tin thnh 16 mu m c th chia ln hn hoc nh hn. Trn c s giao thc nh trn c th thit k mt khi nhn thng tin t cng COM vi cu hnh: - Tc truyn Braud rate = 9600 - 7 bit d liu (truyn k t ASCII) Data bit = 7, - H tr Bit Parity, - 1 bit STOP. S khi ca khi nhn nh hnh di y:
SAMPLE COUNTER BIT COUNTER

CLK

CLOCK DIVIDER

CLK16 CNT RESET ENABLE CNT RESET ENABLE

nRESET
FSM (FINITE STATE MACHINE)

RX_REG Rx RECEIVE_REG

RX_REG

SHIFT_ENABLE

DATA REG

LOAD

LEDs

Hnh 4-55. S khi nhn thng tin ni tip Tn hiu Rx l u vo ca cng COM. Dao ng c s ca mch ly t b dao ng thch anh c tn s CLK = 27Mhz, tn s ny c chia nh mt b chia tn vi h s chia l (9600 x 16)trc khi s dng lm xung nhp h thng CLK16 cho ton khi, trong 9600 l tc Braud. Tn hiu nRESET cng ly t 1 chn iu khin ca FPGA. Hai tn hiu CLK16 v nRESET dng chung cho 255

tt c cc khi khc trong b nhn. kim tra d liu vo th n gin cc bit thng tin s c gn cho cc LEDs tng ng trn mch. B nhn c xy dng di dng my trng thi hu hn (Finite State Machine), v d minh ha ny ta ch s dng 3 trng thi l trng thi nhn bit bit START t Rx - STATE FRAME DETECTOR, trng thi nhn d liu (k c PARITY bit v STOP bit) - DATA_RECEIVING. Trng thi ngh IDLE. S chuyn trng thi nh sau:

IDLE

CNT16 = 8 and RX = 1 CNT_BIT = 8

RX = 0, Rx_Reg = 1

RECEIVE DATA

START FRAME DETECTOR

CNT16 = 8 and RX = 0

Hnh 4-56. My trng thi khi nhn thng tin ni tip T trng thi IDLE s chuyn sang trng thi STATE FRAME DETECT nu nh ng truyn chuyn t mc 1 xung mc 0, bt c bc chuyn ny ta s dng mt thanh ghi gi chm tn hiu Rx c tn l Rx_Reg, my trng thi ghi nhn Rx chuyn xung mc 0 nu Rx = 0 v Rx_Reg = 1. Khi chuyn sang trng thi STATE FRAME DETECT my trng thi s khi ng b m mu, ti v tr ly mu nu Rx vn bng 0 th kt lun y chnh l tn hiu START v s chuyn sang trng thi nhn d liu RECEIVE DATA. Theo l thuyt trng thi ny chng ta s m n 8 v ly mu im chnh gia nhng v khi xc nhn tn hiu START ta xc nhn im gia CNT = 8 v RESET ngay b m mu ti im ny nn im ly mu ca ta khng phi v tr CNT = 8 na m i vi cc bit d liu ta s ly ti cc im CNT = 15. Trong trng thi nhn d liu th b m bit cng lm vic, khi c 1 bit thng tin c nhn b m ny cng thm 1, ng thi my trng thi cng s 256

iu khin thanh ghi dch nhn d liu RECEIVE_REG thng qua tn hiu SHIFT_ENABLE thanh ghi ny dch qua tri mi ln 1 bit, cc bit thng tin c y dn vo thanh ghi ny cho ti y. Khi nhn thng tin gi tr CNT_BIT = 9 th ton b thng tin t RECEIVE_REG c ghi song song sang thanh ghi d liu DATA_REG, my trng thi chuyn v trng thi ngh v ch nhn d liu tip theo. M thit k VHDL ca khi ny c ghp t 6 khi nh bao gm khi chia tn, 2 khi m, thanh ghi dch, thanh ghi song song, my trng thi fsm.vhd, v khi tng receiver.vhd. Ni dung ca cc khi c lit k di y: Khi chia tn clk_div.vhd:
----------------------------------------LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; --------------------------------------ENTITY clk_div IS GENERIC(baudDivide : std_logic_vector(7 downto 0) := "10101110"); PORT( clk : in std_logic; clk16 : inout Std_logic); END clk_div; --------------------------------------ARCHITECTURE rtl OF clk_div IS SIGNAL cnt_div : Std_logic_vector(7 DOWNTO 0); BEGIN --Clock Dividing Functions-process (CLK, cnt_div) begin if (Clk = '1' and Clk'event) then if (cnt_div = baudDivide) then cnt_div <= "00000000"; else cnt_div <= cnt_div + 1; end if; end if; end process; process (cnt_div, clk16, CLK) begin if CLK = '1' and CLK'Event then if cnt_div = baudDivide then clk16 <= not clk16;

257

else clk16 <= clk16; end if; end if; end process; END rtl; -------------------------------------B m counter.vhd s dng tham s tnh thit lp s bit cho gi tr

m:
-------------------------------------LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; -------------------------------------ENTITY counter IS GENERIC(n : Positive := 3); PORT( clk : in std_logic; reset : in std_logic; clock_enable : in std_logic; count_out : out std_logic_vector((n-1) DOWNTO 0) ); END counter; -------------------------------------ARCHITECTURE rtl OF counter IS SIGNAL cnt : std_logic_vector((n-1) DOWNTO 0); BEGIN PROCESS (clk, reset) BEGIN if reset = '1' then cnt <= (others =>'0'); elsif rising_edge(clk) then if clock_enable = '1' then cnt <= cnt + 1; end if; end if; END PROCESS; count_out <= cnt; END rtl; --------------------------------------Thanh ghi dch shifter.vhd: --------------------------------------library ieee; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------

258

entity shifter is generic (n : positive := 8); port ( clk : in std_logic; reset : in std_logic; Rx : in std_logic; shift_enable : in std_logic; shift_value : inout std_logic_vector(n-1 downto 0) ); end entity; ---------------------------------------architecture rtl of shifter is begin shifting: process (clk, reset) begin if reset = '1' then shift_value <= (others => '0'); elsif clk = '1' and clk'event then if shift_enable = '1' then shift_value <= Rx & shift_value(n-1 downto 1); end if; end if; end process shifting; end architecture; ----------------------------------------Thanh ghi song song reg.vhd: ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity reg is generic (n: positive := 8); port( WE : in std_logic; -- write enable D : in std_logic_vector(n-1 downto 0); Q : out std_logic_vector(n-1 downto 0); CLK : in std_logic; RESET : in std_logic ); end reg; -----------------------------------------architecture behavioral of reg is signal Q_sig : std_logic_vector(n-1 downto 0); begin

259

reg_p: process (CLK, RESET) begin if RESET = '1' then Q_sig <= (others => '0'); elsif CLK = '1' and CLK'event then if WE = '1' then Q_sig <= D; end if; end if; end process reg_p; Q <= Q_sig; end behavioral; -----------------------------------------My trng thi hu hn fsm.vhd: ----------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; ----------------------------------------ENTITY fsm IS PORT( RESET : in std_logic; Rx : in std_logic; cnt16 : in std_logic_vector (3 downto 0); cnt_bit : in std_logic_vector (3 downto 0); clk16 : in std_logic; cnt_bit_reset : out std_logic; cnt_bit_enable: out std_logic; cnt16_reset : out std_logic; cnt16_enable : out std_logic; shift_enable : out std_logic; data_reg_WE : out std_logic); END fsm; ----------------------------------------architecture rtl of fsm is signal signal constant constant := "01"; constant := "10"; Rx_reg : std_logic; state : std_logic_vector (1 downto 0); Idle_state std_logic_vector (1 downto 0) := "00"; start_frame_state : std_logic_vector (1 downto 0) receive_state : std_logic_vector (1 downto 0)

Begin reg_RX: process (clk16) begin

260

if clk16 = '1' and clk16'event then Rx_reg <= Rx; end if; end process reg_RX; receiving: process (clk16, Rx, RESET, Rx_reg) begin if RESET = '1' then state <= Idle_state; elsif clk16 = '1' and clk16'event then case state is when Idle_state => cnt16_reset <= '0'; data_reg_WE <= '0'; cnt_bit_reset <= '0'; if Rx = '0' and Rx_reg = '1' then state <= start_frame_state; cnt16_enable <= '1'; cnt16_reset <= '1'; end if; when start_frame_state => cnt16_reset <= '0'; if cnt16 = "0101" then if Rx = '0' then cnt16_enable <= '1'; cnt16_reset <= '1'; cnt_bit_reset <= '1'; state <= receive_state; else cnt16_enable <= '0'; state <= Idle_state; end if; end if; when receive_state => cnt_bit_reset <= '0'; cnt16_reset <= '0'; if cnt16 = "1110" then --luu data Rx cnt_bit_enable <= '1'; shift_enable <= '1'; else cnt_bit_enable <= '0'; shift_enable <= '0'; end if; if cnt_bit = "1000" then --nhan den bit thu 8 data_reg_WE <= '1'; cnt16_enable <= '0'; cnt16_reset <= '1';

261

cnt_bit_enable <= '0'; cnt_bit_reset <= '1'; shift_enable <= '0'; state <= Idle_state; end if; when others => cnt16_enable <= '0'; cnt_bit_enable <= '0'; shift_enable <= '0'; state <= Idle_state; end case; ---------------------------------------------Khi tng (receiver) receiver.vhd: ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity Receiver is generic (n: positive := 8); port( Rx : in std_logic; data_out : out std_logic_vector(7 downto 0); CLK : in std_logic; nRESET : in std_logic ); end Receiver; -----------------------------------------architecture behavioral of Receiver is signal RESET : std_logic; signal clk16 : std_logic; signal shift_enable : std_logic; signal shift_value : std_logic_vector(9 downto 0); signal cnt_bit_reset : std_logic; signal cnt_bit_enable : std_logic; signal cnt_bit : std_logic_vector (3 downto 0); signal cnt16_reset : std_logic; signal cnt16_enable : std_logic; signal cnt16 : std_logic_vector (3 downto 0); signal data_reg_WE : std_logic; -----------------------------------------component clk_div is GENERIC( baudDivide : std_logic_vector(7 downto 0) := "10101110"); PORT(

262

clk : in std_logic; clk16 : inout Std_logic); end component; -------------------------------------------component reg is generic (n: positive := 8); port( WE : in std_logic; D : in std_logic_vector(n-1 downto 0); Q : out std_logic_vector(n-1 downto 0); CLK : in std_logic; RESET : in std_logic); end component; -------------------------------------------component counter IS GENERIC(n : Positive := 3); PORT( clk, reset, clock_enable : IN Std_logic; count_out: out Std_logic_vector((n-1) DOWNTO 0)); END component; -------------------------------------------component shifter is generic (n : positive := 8); port( clk : in std_logic; RESET : in std_logic; Rx : in std_logic; shift_enable : in std_logic; shift_value : inout std_logic_vector(n-1 downto 0)); end component; -------------------------------------------component fsm is PORT( RESET : in std_logic; Rx : in std_logic; cnt16 : in std_logic_vector (3 downto 0); cnt_bit : in std_logic_vector (3 downto 0); clk16 : in std_logic; cnt_bit_reset : out std_logic; cnt_bit_enable : out std_logic; cnt16_reset : out std_logic; cnt16_enable : out std_logic; shift_enable : out std_logic; data_reg_WE : out std_logic); end component; ------------------------------------------

263

begin RESET <= not nRESET; finish_state_machine: component fsm port map ( RESET, Rx, cnt16, cnt_bit, clk16, cnt_bit_reset, cnt_bit_enable, cnt16_reset, cnt16_enable, shift_enable, data_reg_WE); clock_divide16: component clk_div generic map ("01011001") -- = 27Mhz/9600/16/2 port map (clk, clk16); receive_reg: component shifter generic map (10) port map (clk16, RESET, Rx,shift_enable, shift_value); counter16: component counter generic map (4) port map (clk16, cnt16_reset, cnt16_enable, cnt16); counter_bit: component counter generic map (4) port map (clk16, cnt_bit_reset, cnt_bit_enable, cnt_bit); data_reg: component reg generic map (8) port map (data_reg_WE, shift_value(9 downto 2), data_out, clk16, RESET); end behavioral; ------------------------------------------

Kt qu m phng trn Modelsim

Hnh 4-57. Kt qu m phng khi nhn UART Sau khi khi ng hoc sau khi tn hiu nRESET tch cc khi nhn u chuyn v sng thi IDLE (state = 00). trng thi ny khi Rx = 0 v Rx_reg = 1 b m mu cnt16 bt u m v trng thi chuyn sang START_FRAME_DETECT (state = 01), khi cnt16 m n gi tr bng 5 tc l 6 mu, nu k c 1 mu tr do Rx_reg th v tr mu 7/16, nu n v tr ny m Rx bng 0 th khi nhn xem tn hiu trn Rx l tn hiu START v bt u chuyn sang trng thi nhn d liu RECEIVE DATA(state = 10), trng thi 264

ny b m mu cnt16 m lin tc t 0 n 15, v tr ly mu l v tr khi cnt16 = 15. v d m phng trn tn hiu Rx c 16 xung nhp ca clk16 th thay i t 0 ln 1 hoc 1 xung 0 do ta s thu c tun t cc bit 0101 tng ng y dn vo thanh ghi dch shift_value. Qu trnh thu kt thc khi b m bit counter_bit = 8, tng ng nhn 7 bit d liu, 1 bit PARITY v 1 bit STOP. Trc khi tng hp v hin thc thit k trn FPGA cn thc hiu gn cc chn tn hiu, thit lp rng buc cho mch trn Kit FPGA. gn cc chn tn hiu trn FPGA ta s dng giao din ha trong chng trnh PlandAhead hoc to mt tp c ui m rng receiver.ucf vi ni dung nh sau:
INST "CLK_BUFGP" LOC = BUFGMUX_X2Y10; NET "CLK" LOC = P184; NET "nRESET" LOC = P29; NET "Rx" LOC = P109; NET "data_out[0]" LOC = P102; NET "data_out[1]" LOC = P100; NET "data_out[2]" LOC = P99; NET "data_out[3]" LOC = P98; NET "data_out[4]" LOC = P97; NET "data_out[5]" LOC = P96; NET "data_out[6]" LOC = P94; NET "data_out[7]" LOC = P93; NET "clock_divide16/clk161" TNM_NET = "clock_divide16/clk161"; TIMESPEC TS_clock_divide16_clk161 = PERIOD "clock_divide16/clk161" 20 ns HIGH 50 %; NET "CLK" TNM_NET = "CLK"; TIMESPEC TS_CLK = PERIOD "CLK" 10 ns HIGH 50 %; (*) Lu rng v tr cc cng c th khc nhau cho cc mch FPGA khc nhau.

Cc dng bt u bng t kha NET thit lp ci t cho cc cng vo ra ca thit k tng ng vi cc v tr trn mch tht, mi v tr c mt k hiu v s th t ring. Cng CLK c ly t chn to dao ng thch anh P184 trn mch, tng ng trn s FPGA di y chn CLK nm gn hai khi DCM trn. Chn nRESET c ly t v tr P29 l mt nt n to xung RESET, nt n trn mch c mc tch cc m, v tr ca nRESET nm gia cnh tri. Cc chn d liu ra c gn cho v tr ca 8 n LED trn mch, v tr ca cc cng ny ti gc di phi ca mch. V cui cng l tn hiu Rx ly t chn Rx mch tng ng P109 ca FPGA, v tr cng ny nm gn v tr chn cc n LED trn cnh phi. 265

Ngoi thit lp v v tr, trong tp ny cn thit lp iu kin rng buc cho cc tn hiu CLK v CLK16, cc tn hiu ny c nh ngha l tn hiu ng b vi yu cu v chu k tng ng khng ln hn 10 ns v 20 ns. Trn thc t nhng yu cu v thi gian khng quan trng v khi nhn ca chng ta lm vic xung nhp nh hn 2Mhz hay vi Tmin = 1/2Mhz = 500 ns. Cc lnh ny ch c ngha bo cho trnh bin dch bit khi kt ni cn phi xem cc tn hiu ny l tn hiu ng b. Kt qu tng hp trn FPGA
Device utilization summary: --------------------------Selected Device : 3s500epq208-4 Number of Slices: 30 out of 4656 0% Number of Slice Flip Flops: 41 out of 9312 0% Number of 4 input LUTs: 44 out of 9312 0% Number of IOs: 11 Number of bonded IOBs: 11 out of 158 6% Number of GCLKs: 2 out of 24 8% ================================================= TIMING REPORT Speed Grade: -4 Minimum period: 4.851ns (Maximum Frequency: 206.143MHz) Minimum input arrival time before clock: 5.216ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns)

Kt qu sau tng hp bao gm kt qu v s dng ti nguyn v kt qu v thi gian. V s dng ti nguyn, khi nhn cng COM s dng mt lng ti nguyn rt nh 30/4656 SLICEs. V mt thi gian, thi gian tr ln nht trc xung nhp l 5,2 ns, tn s cc i ca mch l ~ 200Mhz, trn thc t mch ca chng ta hot ng xung nhp nh hn 2Mhz nn nhng kt qu trn hon ton p ng yu cu thit k. Kt qu v thi gian tnh sau khi thc hin kt ni v phn b (Post place & route static timming) l kt qu chnh xc thu c trn mch np, nh quan st sau kt qu ny thay i khng ng k so vi kt qu sau tng hp.
All constraints were met. Data Sheet report: ----------------All values displayed in nanoseconds (ns) Clock to Setup on destination clock CLK

266

Source Clock|Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -----------+---------+---------+---------+---------+ CLK | 5.004| | | | -----------+---------+---------+---------+---------+

4.2. Thit k khi iu khin PS/2 cho Keyboard, Mouse

Hnh 4-58. Mch giao tip PS/2 Cng giao tip PS/2 xut pht t tn gi sn phm my tnh th hai (Personal System/2) ca IBM. Cng ny ny dng ni my tnh vi cc thit b ngoi vi nh chut v bn phm.Cng giao tip ny c tt c 6 chn nh s t 1 n 6. Chn s 3 v 4 tng ng l GND v ngun. Ngun s dng l 5V nhng thc t vi thit k trn FPGA c th s dng mc in p 3.3V. Chn 5 l chn tn hiu ng b CLK. Cn chn 1, 2 l cc chn d liu DATA1 v DATA2, ngm nh bn phm giao tip qua DATA1, bn phm qua chn DATA2 v c th dng mt cng PS/2 vi 1 thit b chia kt ni vi c bn phm v chut, tuy vy n gin ta dng hai cng ring bit v ni cng DATA1 v DATA2 vi nhau nh trn hnh v, c ngha l cng ny c th kt ni vi c hai loi ngoi vi. Giao thc iu khin cho cc thit b ny rt ging vi giao thc ca cng COM nh trnh by trn.im khc bit duy nht l cc thit b ny lm vic ng b vi thit b tip nhn thng tin (chung mt tn hiu CLK), giao thc truyn d liu c th hin hnh sau:

267

PS2_DATA

IDLE

START

8BIT-SCANCODE

PARITY

STOP

Tbraud

Bit counter

10

PS2_CLK

Hnh 4-59. Gin sng ca giao tip PS/2 Tn hiu CLK thng c to bi khi giao tip trong trng hp ny l FPGA, cn DATA l tn hiu hai chiu. Yu cu v mt thi gian cho cc tn hiu ny th hin bng sau: Bng 4-6 Yu cu v mt thi gian ca giao tip PS/2 K hiu Tn gi Ti a Ti thiu TPS2_CLK Chu k xung Clock 30us 50us TSU Thi gian Setup ca PS2_CLK 5us 25us THold Thi gian Hold ca PS2_CLK 5us 25us T bng trn c th tnh c tn s ca tn hiu CLK vo khong 20kHz -30Khz, vi tn s thp nh vy c th yn tm v i hi i vi Tsu v Thold nu thit k trn FPGA. Khi mi phm c n, bn phm vi giao tip PS/2 chun s gi mt m tng ng gm 11-bit trong c 1 bit 0 l START BIT, theo sau l 8 bit m qut phm (Scan code), bit tip theo l bit parity, 1 STOP bit (bng 1). M Scan code l m tng ng duy nht 1 k t trn bn phm chun vi 8 bit nh phn, bng m cho cc k t thng dng c lit k hnh v di y (ngun Xilinx.com):

Hnh 4-60. Bng m SCAN CODE ca bn phm chun 268

Nu mt phm c n v gi th bn phm s lin tc gi chui gi tr tng ng trong vi tn sut 100ms/m. Khi phm c th th bn phm s gi m c ga tr scan code l F0 theo sau l m phm c n. Kh mt phm chc nng nh Alt, Control phi, cc phm mi tn gi chung l cc phm m rng th bn phm gi m l E0 km theo m phm n, khi phm dng ny th th t hp E0, F0 c gi v sau l m phm n. Khng c cc m khc nhau phn bit ch ci hoa v thng m phn bit phi s dng thm c trng thi phm SHIFT c ang c gi khng, bn thn phm SHIFT c coi nh mt phm thng thng. Ngoi vic nhn m phm n th thit b tip nhn u vo t bn phm c th s dng giao thc ng truyn trn gi mt s lnh iu khin n gin ti bn phm, cc lnh lit k bng sau: Bng 4-7 Cc lnh giao tip vi bn phm chun Lnh M t ED Bt/ tt cc n iu khin. Khi nhn lnh ny bn phm tr li bng gi tr FA. K tip mt gi tr c gi ti bn phm vi ni dung nh sau: Bit t 7 n 3: Khng quan tm Bt 2: CapLock Led Bit 1: NumLock Led Bit 0: Scholl Lock Led EE Echo: bn phm nhn lnh ny s tr li bng gi tr EE, s dng kim tra bn phm. F3 t thi gian lp phm hay nhy phm, sau lnh ny bn phm gi gi tr FA, 8bit k tip gi ti bn phm xc lp thi gian lp. FE Khi gp lnh ny bn phm gi li m phm c n gn nht. FF Lnh Reset li bn phm. Lu rng bn phm c th hot ng m khng nht thit phi c mt qu trnh khi to v vy n gin c th thit k khi giao tip n thun ch nhn tn hiu t bn phm. S sau th hin mt thit k n gin giao tip vi bn phm.

269

PS2CLK CLK(24Mhz)
CLOCK DIVIDER SAMPLE COUNTER (CNT) BIT COUNTER (CNT_BIT)

CNT CLOCK DIVIDER CLK16x24Khz

RESET ENABLE

CNT_BIT RESET ENABLE

RESET
FSM (FINITE STATE MACHINE)

RX_REG Rx RECEIVE_REG

RX_REG

SHIFT_ENABLE

DATA REG

LOAD

DATA_OUT
SCANCODE to ASCII BUFFER (optional)

Hnh 4-61. S khi giao tip PS/2 S ny v c bn gi nguyn phn nhn thng tin vi giao thc UART ca phn 4.1. Ta thc hin iu chnh khi chia tn s, vi gi s ban u tn s thch anh c sn l 24Mhz, ta chia 1000 c tn s PS2_CLK = 24kHz. Ngoi ra ton b khi nhn hot ng di s iu khin ca 1 xung Clock c tn s bng PS2_CLK x 16 = 16 x24 = 384kHz, tn s ny c to bi khi chia tn th 2. V m thu c l m SCANCODE do vy cn mt khi ROM chuyn gi tr ny thnh m ASCII (khi SCANCODE to ASCII). Kt qu sau khi ROM c lu tr trong BUFFER trc khi a n cc khi x l cp cao hn, ty theo mc ch m BUFFER ny c th c thit k hay khng. 4.3. Thit k khi tng hp dao ng s NCO NCO vit tt ca Numerically Controler Osillator.l khi tng hp dao ng bng vi mch s. Khi ny c kh nng tng to ra dao ng vi tn s mong mun mt cc trc tip bng mt vi mch s tch hp. C s ton hc ca NCO th hin nh hnh sau:

270

2^N

t 0

360

t 0 +Uo

-Uo

Dt
Tout

Hnh 4-62. C s ton hc ca NCO Sng m ta mun tng hp c hm s ph thuc thi gian v tn s nh sau Y(t)= Uo sin ( Nu t = th ) = Uo sin ( . l mt hm ph thuc tuyn tnh

theo thi gian, nu biu din gi tr pha theo thang 0-360o th th theo thi gian tng ng l th th hai t trn xung di hnh trn. Nu chia nh trc thi gian thnh cc im cch u nhau lin tip mt khong , gi cc im chia trn trc thi gian ln lt l 0, , 2 , Ta c Gi tr bin tng ng l

271

p dng nh l Kachenhikov v ri rc ha v khi phc tn hiu c ph gii hn ta c th tnh ton gi tr thu c t hp cc gi tr uk khi phc hon ton sng ban u gi tr phi tha mn Trong f l tn s cn tng hp. Chuyn sang bi ton trn mch s, cc gi tr tch ly pha v gi tr bin th nht phi c s ha, tc l biu din di dng s. Gi tr tch ly pha khng nht thit thay i t 0-360o m trn thc t ta chn mt min gi tr 0-2N, trong 2N >360, thu c chnh xc v phn gii cao hn. Gi p0, pk l gi tr ri rc pha c s ha cc gi tr ny c tnh bng mt khi tch ly pha N bit, bn cht l mt khi cng tch ly. u vo ca khi cng ny l gi tr tch ly N bit m. Sau mt khong thi gian = 1/f0 trong f0 l tn s c s ca mch (tn s lm vic ca b cng tch ly) gi tr ln nht m khi cng tch ly biu din c

khi c th tnh c gi tr bin uk c s ha tng ng trong bng SIN l:

Bng SIN tng ng 1 chu k ca sng sin, thc hin ht mt chu k ny th cn mt khong thi gian bng

Suy ra tn s ca sng thu c tnh gn ng theo cng thc:

Nh vy tn s u ra ph thuc trc tip vo 3 tham s N l s bit ca dng cho thanh ghi ca b tch ly pha. m l t iu khin tn s u vo. l tn s xung nhp c s ca mch.

272

Cng t cng thc trn c th gii hn c min thay i ca tn s ra ca NCO

Hnh di y l m t s khi ca NCO:

DATA_REG

ACC_REG

Data

DAC

27 MHz

NCO

Hnh 4-63 S khi ca NCO - Khi tch ly pha l b cng tch ly c nhim v to ra t hp cc gi tr pk theo thi gian, khi cng tch ly c u vo xung nhp l xung nhp c s ca mch, gi tr tch ly m hay cn gi l t iu khin tn s. - Khi tham chiu bng SIN : t gi tr pha tch ly pk tham chiu gi tr bin sng SIN uk tng ng, khi ny bn cht l mt khi ROM hoc RAM lu tr cc gi tr ca chu k sng c lng t v s ha. u ra ca NCO l cc gi tr s ri rc theo thi gian, thu c sng SIN cn thm mt khi bin i tn hiu s-tng t DAC. Khi thit k khi SIN ROM cn lu mt c im ca sng SIN l hm l nn trong mt chu k gi tr bin hai na chu k l i nhau, cn trong mt na chu k th sng SIN l mt hm chn, i xng qua trc k/2. Do lu tr cc gi tr trong mt chu k sng ch cn lu tr gi tr ca chu k. hiu c th hn quan st hnh sau:

273

0011 0010 0001

0100 0101 0110 0000

0000

1000 1001 1010 1011 1111 1101 1100

Hnh 4-64. M ha bng SIN ROM cho N = 4 Vi trng hp N=4 ta c m ha cho bng SIN ROM nh hnh trn, cc gi tr 4-bit x3x2x1x0 trn hnh tng ng l a ch u vo ca khi ROM. Vi nhn xt nh trn ta thy thay v s dng bng ROM 16 gi tr c th s dng bng ROM 4 gi tr (min nh du m), bng ROM ny c a ch biu din bng 2 bit x1x0. Ta gi s gi tr bin SIN cng biu din di dng 4-bit d3d2d1d0. Khi : Nu x3x2 = 00 th gi tr tng ng gi nguyn.

Nu x3x2 = 01 th gi tr tng ca bin

Nu x3x2 = 10 th gi tr tng ca bin

Nu x3x2 = 11 th gi tr tng ca bin

Ton b thao tc trn c th c thc hin bng mt khi logic khng phc tp, b li ta s tit kim c s lng nh cn cho bng ROM. Vic m ha ch bng ROM cng gip tit kim 1 bit du dng biu din gi tr v min gi tr ca bng ROM lun l gi tr dng. 274

Di y l m ngun ca mt khi NCO dng 6 bit cho gi tr tch ly pha, tng ng bng ROM s c 26/4 = 16 a ch m ha bng 4 bit, gi tr trong bng ROM m ha bng 4 bit vi gi tr thay i t 0 n 15. M ngun khi SIN ROM sin_rom.vhd
----------------------------------------library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_signed.ALL; use IEEE.STD_LOGIC_arith.ALL; ----------------------------------------entity sin_rom16 is port ( clk : in std_logic; cs : in std_logic; rst : in std_logic; address : in std_logic_vector(5 downto 0); dataout : out std_logic_vector (4 downto 0) ); end sin_rom16; ----------------------------------------architecture behavioral of sin_rom16 is signal addr :std_logic_vector (3 downto 0); signal data :std_logic_vector (3 downto 0); signal data1, data2 :std_logic_vector (4 downto 0); ----- Du lieu trong ROM duoc nap cac gia tri co dinh begin sinrom: process (rst, cs, addr) begin if rst='0' and cs='1'then case addr is when x"0" => data <= x"0"; when x"1" => data <= x"1"; when x"2" => data <= x"3"; when x"3" => data <= x"4"; when x"4" => data <= x"6"; when x"5" => data <= x"7"; when x"6" => data <= x"8"; when x"7" => data <= x"A"; when x"8" => data <= x"B"; when x"9" => data <= x"C"; when x"A" => data <= x"C"; when x"B" => data <= x"E"; when x"C" => data <= x"E"; when x"D" => data <= x"F"; when x"E" => data <= x"F";

275

when x"F" => data <= x"F"; when others => null; end case; end if; end process sinrom; data1 <= '0' & data; data2 <= not (data1) + 1; mod_address: process(address) begin case address (4) is when '0' => addr <= address (3 downto 0); when '1' => addr <= not address (3 downto 0); when others => null; end case; end process mod_address; get_data: process (clk, data) begin if clk = '1' and clk'event then case address (5) is when '0' => dataout <= data1; when '1' => dataout <= data2; when others => null; end case; end if; end process get_data; end behavioral; ----------------------------------------B cng n gin ch c cng a, b v sum adder.vhd: ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder is generic (N : natural := 32); port( A : in std_logic_vector(N-1 downto 0); B : in std_logic_vector(N-1 downto 0); SUM : out std_logic_vector(N-1 downto 0) ); end adder; ----------------------------------------architecture behavioral of adder is

276

begin plus: process (A, B) begin sum <= a + b; end process plus; end behavioral; ----------------------------------------Thanh ghi reg.vhd: ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity reg is generic (N : natural := 32); port( D : in std_logic_vector(N-1 downto 0); Q : out std_logic_vector(N-1 downto 0); CLK : in std_logic; RESET : in std_logic ); end reg; -----------------------------------------architecture behavioral of reg is begin reg_p: process (CLK, RESET) begin if RESET = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then Q <= D; end if; end process reg_p; end behavioral; -----------------------------------------Khi cng tch ly accumulator.vhd: -----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity accumulator is generic (N : natural := 32); port( A : in std_logic_vector(N-1 downto 0);

277

Q : out std_logic_vector(N-1 downto 0); CLK : in std_logic; RESET : in std_logic ); end accumulator; ----------------------------------------architecture structure of accumulator is signal sum : std_logic_vector(N-1 downto 0); signal Q_sig : std_logic_vector(N-1 downto 0); ----COMPONENT ADDER---component adder is generic (N : natural := 32); port( A : in std_logic_vector(N-1 downto 0); B : in std_logic_vector(N-1 downto 0); SUM : out std_logic_vector(N-1 downto 0) ); end component; ----COMPONENT REG---component reg is generic (N : natural := 32); port( D : in std_logic_vector(N-1 downto 0); Q : out std_logic_vector(N-1 downto 0); CLK : in std_logic; RESET : in std_logic ); end component; begin add: component adder generic map (6) port map (A, Q_sig, sum); regg: component reg generic map (6) port map (sum, Q_sig, CLK, RESET); Q <= Q_sig; end structure; ----------------------------------------Khi nco nco.vhd: ----------------------------------------library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity nco is

278

port ( m : in std_logic_vector(5 downto 0); clk : in std_logic; nRESET : in std_logic; cs : in std_logic; dataout : out std_logic_vector(4 downto 0) ); end entity; ----------------------------------------architecture behavioral of nco is signal RESET : std_logic; signal m_reg : std_logic_vector(5 downto 0); signal address : std_logic_vector(5 downto 0); ----------------------------------------component accumulator is generic (N : natural := 32); port( A : in std_logic_vector(N-1 downto 0); Q : out std_logic_vector(N-1 downto 0); CLK : in std_logic; RESET : in std_logic ); ----------------------------------------end component; component sin_rom16 is port ( clk : in std_logic; cs : in std_logic; rst : in std_logic; address : in std_logic_vector(5 downto 0); dataout : out std_logic_vector(4 downto 0) ); end component; ----------------------------------------begin RESET <= not nRESET; process (clk, RESET) begin if RESET = '1' then m_reg <= (others => '0'); elsif clk = '1' and clk'event then m_reg <= m; end if; end process; u1: accumulator

279

generic map (6) port map (m_reg, address , clk , RESET); u2: sin_rom16 port map (clk, cs, RESET, address, dataout); end architecture behavioral; -----------------------------------------

Kt qu m phng trn Modelsim

Hnh 4-65. Kt qu m phng khi NCO Nh quan st trn gin sng gi tr tn hiu u ra c dng sng Sin ng nh mong mun, tng phn gii v thu c dng sng u ra tt hn th tng s bit dnh cho thanh ghi tch ly v s bit s dng cho biu din gi tr bin sng. Ni dung nco.ucf:
NET "dataout[0]" LOC = "P102"; NET "dataout[1]" LOC = "p100"; NET "dataout[2]" LOC = "P99"; NET "dataout[3]" LOC = "p98"; NET "dataout[4]" LOC = "P97"; NET "m[0]" LOC = "P161"; NET "m[1]" LOC = "p162" ; NET "m[2]" LOC = "P163"; NET "m[3]" LOC = "p164"; NET "m[4]" LOC = "P165"; NET "m[5]" LOC = "P167"; NET "CLK" LOC = P184; NET "nRESET" LOC = P29; NET "CLK" TNM_NET = "CLK"; TIMESPEC TS_CLK = PERIOD "CLK" 5.2 ns HIGH 50 %;

T iu khin tn s c t gi tr tng ng bng 6 switch trn mch, tn hiu ra c gi n 5 LEDs. V xung nhp lm vic ta hn ch xung CLK l 3.2 ns, con s ny c c sau tng hp s b. Kt qu tng hp trn FPGA
Device utilization summary: ---------------------------

280

Selected Device : 3s500epq208-4 Number of Slices: 11 out of 4656 0% Number of Slice Flip Flops: 20 out of 9312 0% Number of 4 input LUTs: 20 out of 9312 0% Number of IOs: 14 Number of bonded IOBs: 14 out of 158 8% IOB Flip Flops: 1 Number of GCLKs: 1 out of 24 4% =============================================== Timing Summary: --------------Speed Grade: -4 Minimum period: 3.702ns (Maximum Frequency: 270.124MHz) Minimum input arrival time before clock: 2.360ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found -------------All values displayed in nanoseconds (ns)

Kt qu sau tng hp bao gm kt qu v s dng ti nguyn v kt qu v thi gian. V s dng ti nguyn, NCO s dng 11/4656 SLICEs. V mt thi gian, xung nhp cc i l 270Mhz, con s ny cng l gii hn cho tn s s tng hp c u ra v y l gii hn ca tn s c s. Kt qu v thi gian tnh sau khi thc hin kt ni v phn b thu c xung nhp cc i chnh xc l 302Mhz.
All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -------------+---------+---------+---------+---------+ clk | 3.303| | | | -------------+---------+---------+---------+---------+ Timing summary: --------------Timing errors: 1 Score: 103 (Setup/Max: 103, Hold: 0) Constraints cover 61 paths, 0 nets, and 28 connections Design statistics: Minimum period: 3.303ns{1} (Maximum frequency: 302.755MHz)

Lu do DAC nhn cc bit u vo di dng s nguyn khng du cn gi tr biu din trn sng SIN khi m phng l s c du di dng b 2. DAC lm vic ng v quan st chnh xc tn hiu cn iu chnh li m ngun xut cc gi tr u ra dng s nguyn dng.

281

4.4. Thit k khi iu khin LCD1602A Mn hnh LCD1602A n sc hin th 2x16 k t chun c s dng kh rng ri trong cc ng dng va v nh v tnh n gin trong giao tip cng nh trong iu khin. Ti liu chi tit v mn hnh loi ny c th xem thm [24], trong v d ny ch trnh by thit k giao tip LCD trong ch 8-bit vi phn khi to ti thiu. Mch giao tip LCD c th hin hnh sau.

Hnh 4-66. Mch giao tip vi LCD1602A 4.3.1. Cc chn giao tip ca LCD1602A - VDD, GND v Vo: Cp ngun - 5v v t, chn Vo c dng iu chnh tng phn trn mn hnh LCD, thng thng ta mc mt bin tr c 510K iu chnh mc in p vo chn ny. Mc d in p ngun ca LCD l 5V nhng LCD c th giao tip vi FPGA bng mc in p 3.3V. - Hai chn LED+, LED- dng cp ngun cho n Back Light tch hp pha sau LCD tng sng cho mn hnh, c th ni hoc khng. - LCD_RS (Register Select): S dng la trn truy cp vo mt trong hai dng thanh ghi c tch hp trong LCD: thanh ghi d liu v thanh ghi lnh. Nu RS = 1 th thanh ghi m lnh c chn cn RS = 0 th thanh ghi d liu c chn. - LCD_R/W: Tn hiu quy nh chiu trao i thng tin trn knh d liu DB[7:0], nu R/W = 1 th thit b iu khin c thng tin t LCD, nu R/W = 0 282

th thit b iu khin ghi thng tin ln LCD. Thng thng thng tin c ghi ln LCD l chnh nn R/W = 0. - LCD_E (Enable): Chn cho php E dng cht d liu trn knh d liu. cht d liu xung ny phi gi tch cc trong khong thi gian ti thiu Tw >=450ns. Hnh v di y th hin gin sng cho qu trnh c v ghi d liu trn LCD, vi cc tham s thi gian khc xem thm trong ti liu tham kho v LCD1602A.

Hnh 4-67. Chu trnh ghi d liu ln LCD1602A

Hnh 4-68. Chu trnh c d liu ln LCD1602A - Chn DB0 - DB7: Cc chn d liu ca LCD - Nu R/W = 1, RS = 0 khi D7 = 1 ngha l LCD ang bn thc thi cc tc v bn trong v thi im LCD khng nhn thm bt c d liu no, thng thng ta dng bit D7 trong trng hp ny kim tra trng thi LCD mi khi mun gi tip d liu vo LCD.

283

4.3.2. Cc lnh c bn ca LCD1602A Bng sau lit k cc lnh c bn ca LCD1602A:

Bng 4-8 Bng cc lnh c bn ca LCD1602

LCD_R/W

Lnh
LCD_RS

Clear Display

0 S B A0 A0 A0 D0

Return Cursor 0 0 0 0 0 0 0 0 Home Entry Mode Set 0 0 0 0 0 0 0 0 I/D Display On/Off 0 0 0 0 0 0 1 D C Cursor and 0 0 0 0 0 1 S/C R/L Display Shift Function Set 0 0 0 0 1 0 1 0 Set CG RAM 0 0 0 1 A5 A4 A3 A2 A1 Address Set DD RAM 0 0 1 A6 A5 A4 A3 A2 A1 Address Read Busy Flag 0 1 BF A6 A5 A4 A3 A2 A1 and Address Write to CG 1 0 D7 D6 D5 D4 D3 D2 D1 RAM or DDRAM Read to CG 1 1 D7 D6 D5 D4 D3 D2 D1 RAM or DDRAM Clear Display: Xa ht mn hnh bng cch ghi cc k t DDRAM v tr con tr DDRAM v v tr 0.

82us1.64ms 40us1.6ms 40us 40us 40us 40us 40us 40us 1us 40us

D0

40us

trng 0x20 ln

gian Thi thc hin

DB[7]

DB[6]

DB[5]

DB[4]

DB[3]

DB[2]

DB[1]

DB[0]

284

Return Cusore Home: a con tr v v tr ban u nhng khng xa d liu trong DDRAM. Entry mode set: t ch cho con tr tng hay gim bng bt I/D, I/D =1 con tr tng ln 1 mi khi c mt k t c ghi vo RAM, I/D = 0 con tr gim 1. Ch chun ta t I/D = 1. Ton mn hnh s dch khi y nu S = 1, gi nguyn nu S = 0. Display on/off: Bt hay tt mn hnh, con tr v trng thi nhp nhy ca con tr tng ng bng cc bit D, C, B. Cursor and Display Shift: Di chuyn con tr v dch ton b mn hnh m khng thay i ni dung trong DD RAM. Function Set: Thit lp ch lm vic/8bit hay 4 bit, 1 hay hai dng hin th, chn b k t. Set CG RAM Adress: t a ch truy cp ti b nh to k t Character Generation RAM (trong trng hp mun to v s dng cc k t theo mong mun) Set DD RAM Adress: t a ch cho b nh d liu, ni lu tr cc k t hin th ln mn hnh. Read Busy Flag and Address: Kim tra trng thi bn ca LCD, trng thi bn c tr v bt DB[7], cc bit cn li DB[6:0] l gi tr a ch DD RAM hin hnh. Write Data to CGRAM or DDRAM: Ghi d liu vo cc RAM tng ng trong LCD. Lnh ny s dng in cc k t ra mn hnh, khi con tr a ch RAM tng ng t ng dch chuyn ln 1 hoc xung 1 ty thit lp bi Entry mode set. Read Data from CGRAM or DDRAM: c vo cc RAM tng ng trong LCD. Con tr a ch RAM tng ng cng t ng tng hay gim 1 n v ty thuc thit lp bi Entry mode set. 4.3.3. Qu trnh khi to LCD cho ch lm vic 8 bit. Vic khi to cho LCD1602A phi tun th chnh xc cc yu cu v thi gian ngh ti thiu gia cc lnh khi to, s di y th hin quy trnh khi to cho LCD1602A vi ch lm vic 8-bit. Qu trnh ny gm 5 bc, khi mi cp ngun cn phi i ti thiu 30ms cho in p ngun n nh mc cn thit. Sau LCD phi c np tng ng 4 lnh khi to vi gi tr s di y v tun th ng khong thi gian ngh gia cc lnh. Sau khi tri qua 285

chnh xc 6 bc ny LCD tr v trng thi ch d liu/lnh mi, mi lnh k tip thc hin trong vi thi gian ti thiu l 40us.
Bt ngun i ti thiu 30ms
N 1 Ci t ch (Function Set) 0 R/S 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 N DB2 F DB1 X DB0 X F 1 Bt mn hnh Tt mn hnh 2-dng

1-dng

i ti thiu 39us
C Bt tt mn hnh R/S 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 F DB1 C DB0 B B

0 1 0 1

Tt con tr Bt con tr Tt nhp nhy Bt nhp nhy

i ti thiu 39us
Xa mn hnh R/S 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1

i ti thiu 1.53ms
0 Ci t ch vo d liu R/S 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 I/D DB0 SH 0 SH 1 I/D 1

Ch gim dn Ch tng dn Ghi Dch chuyn ton b

Khi to xong

Hnh 4-69. Khi to LCD1602A cho ch 8-bit 4.3.4. S thit k khi iu khin LCD1602A bng FPGA S khi iu khin LCD c th hin hnh sau:

286

RESET
COUNTER4

CLK(24Mhz)
CLOCK DIVIDER CLK1Mhz

CNT

RESET ENABLE

LCD_DB[7:0]

FSM (FINITE STATE MACHINE)

LCD WRAPPED

LCD_EN LCD_RS LCD_RW

FIFO_EMPTY FIFO_FULL FIFO_DATA_IN

Fifo_empty Fifo_full

MUX

FIFO_DATA_OUT

FIFO

Data_in1

READY

FIFO_INITIALIZATION BLOCK

Ready

wr_en1

FIFO_WE_EN

CNT

RESET ENABLE

MUX

COUNTER_CMD

LCD_DRIVER BLOCK

Hnh 4-70. S khi LCD DRIVER trn FPGA Vi mc ch c th d dng ghp ni vi cc khi thit k khc nh mt khi kt xut hin th thng tin, khi LCD c thit k trong mt tp VHDL duy nht bao gm ba khi chc nng chnh. Tn hiu ng b c s l tn hiu xung nhp 1Mhz, c th dng b m chia tn m khng cn DCM trong trng hp ny. Khi my trng thi FSM: Khi FSM c nhim v c cc lnh c m trong FIFO v to cc tn hiu iu khin cn thit gi ti LCD. Khi trng thi IDLE FSM s lun lun kim tra trng thi ca khi FIFO, nu pht hin trong FIFO c d liu (FIFO_EMPTY <> 0) FSM chuyn sang trng thi gi d liu SEND_DATA. Khi trng thi ny FSM khi to b m 64 v c d liu t FIFO gi ti LCD.
CNT[5:4] = 11

IDLE

SEND_DATA

FIFO_EMPTY = 0

Hnh 4-71. My trng thi ca khi iu khin LCD 287

Khi thc hin gi lnh ti LCD, nhim chnh l to ra tn hiu iu khin LCD_EN vi yu cu v mt thi gian nh di y:
CNT[5:4] x 00 01 10 11 00 01 10 11 LCD_E

LCD_DATA

DATA

DATA

Hnh 4-72. Cch thc to tn hiu LCD_EN Tn hiu LCD_EN phi tch cc khi d liu trn LCD_DATA n nh t nht 450ns v thi gian thc hin lnh khng t hn 40us vi khong ngh gia cc lnh c 10us nn trong thit k thc ta khong thi tch cc gian ny l 32us, v khong ngh l 16us, ngha l 1 lnh thc thi trong 16+32+16 = 64us. lm c nh th ta dng mt b m CNT 6 bit v gn: LCD_EN = CNT[4] xor CNT[5]; Khi gn nh vy LCD_EN s tch cc (bng 1) kh CNT[5:4] nhn cc gi tr gia 01, 10 v khng tch cc cc gi tr u v cui 00, 11. Khi LCD_EN tch cc khi FSM ng thi c d liu t FIFO v gi ti LCD. Khi m d liu FIFO: hot ng tn s 1Mhz c nhim v lu cc gi tr m trc khi thc s gi ti LCD bng khi FSM. FIFO c kch thc 16 hng v mi hng 10 bit tng ng cc gi tr [LCD_RS, LCD_RW, LCD_DB[7:0]], Tn hiu iu khin LCD_EN c to bi khi FSM. S lng hng ca FIFO c th thay i ty theo c im ng dng. Khi mun kt xut kt qu ra LCD, cc khi bn ngoi ch cn thc hin ghi m lnh tng ng vo FIFO, tt c cc cng vic cn li do FSM m nhn. Thit k nh vy lm n gin ha vic truy xut LCD v s khng cn phi quan tm n cc tham s thi gian. (*)Ngi thit k c th la chn s dng FIFO c sn nh mt IPCore c trong ISE h tr bi Xilinx hoc t thit k FIFO bng VHDL t u gii thiu trng chng trc. Cch to v s dng IPCore xem thm trong phn ph lc thc hnh thit k trn FPGA. Khi khi to LCD: khi khi to LCD c thc hin t ng ngay sau khi h thng bt u lm vic (sau RESET), n bao gm cc bc c nu 4.3.3. Cch thc hin thc ha quy trnh khi to l s dng mt b m 18 bit v tng ng vi cc gi tr ca b m gi cc lnh cn thit vo FIFO. S d kch thc b m ln l do ti bc u tin ca qu trnh khi to LCD cn khong 30ms n nh in p u vo, 30ms = 30000us ~ 215. Khi quy trnh 288

khi to ny c kch hot th FIFO ch c php ghi d liu bi khi khi to LCD, tn hiu READY khi bng 0 bo cho cc khi bn ngoi khng c php truy cp vo FIFO. Khi qu trnh khi to hon tt READY = 1 v FIFO tr v trng thi ch d liu t bn ngoi. Trn s READY iu khin hai khi MUX la chn cc tn hiu FIFO_DATA_IN v FIFO_WR_EN t bn trong hoc bn ngoi. M ngun khi lcd_driver c lit k di y:
-------------------------------------------- lcd_driver.vhd -- Company: BMKTVXL -- Engineer: Trinh Quang Kien ------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; Library XilinxCoreLib; -----------------------------------------entity lcd_driver is port ( clk1Mhz : in std_logic; reset : in std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic; lcd_e : out std_logic; data_in : in std_logic_vector (9 downto 0); wr_en : in std_logic; -- Write Enable FIFO full : out std_logic; -- FIFO full ready : out std_logic; -- LCD ready lcd_data : out std_logic_vector (7 downto 0) ); end lcd_driver; -----------------------------------------architecture Behavioral of lcd_driver is signal cnt : std_logic_vector(5 downto 0); signal cnt_reset : std_logic; signal cnt_enable : std_logic; signal lcd_state : std_logic; signal cnt_cmd_enable : std_logic; signal rd_en : std_logic; -- Read enable signal data_out : std_logic_vector (9 downto 0); signal lcd_code : std_logic_vector (9 downto 0);

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signal

empty

: std_logic; -- FIFO empty : std_logic := '0'; : std_logic := '1';

constant LCD_IDLE constant lcd_SEND_DATA

signal data_in1, data_in2 : std_logic_vector(9 downto 0); signal wr_en1, wr_en2 : std_logic; signal cnt_cmd : std_logic_vector (17 downto 0):= "000000000000000000"; ---------------------------------------------component fifo_16x10 port ( clk: IN std_logic; rst: IN std_logic; din: IN std_logic_VECTOR(9 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(9 downto 0); full: OUT std_logic; empty: OUT std_logic); end component; ---------------------------------------------begin ff : fifo_16x10 port map ( clk => clk1Mhz, rst => reset, din => data_in2, wr_en => wr_en2, rd_en => rd_en, dout => data_out, full => full, empty => empty); -- INST_TAG_END -- End INSTANTIATION Template ----counter: process (clk1Mhz, reset) begin if cnt_reset = '1' then cnt <= (others => '0'); elsif clk1Mhz = '1' and clk1Mhz'event then if cnt_enable = '1' then cnt <= cnt +1; end if; end if ; end process counter;

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process (clk1Mhz, reset, lcd_state, cnt) begin if reset = '1' then lcd_state <= lcd_idle; cnt_enable <= '0'; elsif clk1Mhz = '1' and clk1Mhz'event then case lcd_state is when lcd_idle => cnt_reset <= '0'; lcd_code <= "01" & x"00"; if empty = '0' then -- existing data in fifo cnt_reset <= '1'; cnt_enable <= '1'; lcd_state <= lcd_SEND_DATA; lcd_e <= '0'; rd_en <= '1'; end if; when lcd_SEND_DATA => cnt_reset <= '0'; lcd_code <= data_out; lcd_e <= cnt(5) xor cnt(4) ; rd_en <= '0'; if cnt(5 downto 4) = "11" then cnt_reset <= '1'; cnt_enable <= '0'; lcd_e <= '0'; lcd_state <= lcd_idle; end if; when others => lcd_state <= lcd_idle; end case; end if; end process; lcd_data <= lcd_code(7 downto 0); lcd_rs <= lcd_code(9); lcd_rw <= lcd_code(8); counter_cmd: process (clk1Mhz, reset, cnt_cmd_enable) begin if reset = '1' then cnt_cmd <= (others => '0'); elsif clk1Mhz = '1' and clk1Mhz'event then if cnt_cmd_enable = '1' then cnt_cmd <= cnt_cmd +1; end if; end if ;

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end process counter_cmd; process (cnt_cmd) begin case cnt_cmd(16 downto 0) is when "10000000000000001" => data_in1 <= "00"& x"38"; wr_en1 <= '1'; -- 8bit 2line mode/display on when "10000000000000010" => data_in1 <= "00"& x"38"; wr_en1 <= '1'; -- 8bit 2line mode/display on when "10000000000000011" => data_in1 <= "00"& x"38"; wr_en1 <= '1'; -- 8bit 2line mode/display on/off -- delay minimum 39us when "10000000001000000" => data_in1 <= "00"& x"0c"; wr_en1 <= '1'; -- display on -- delay minimum 39us when "10000000010000000" => data_in1 <= "00"& x"01"; wr_en1 <= '1'; -- clear display -- delay minimum 1530us when "10000100000000000" => data_in1 <= "00"& x"06"; wr_en1 <= '1'; -- entry mode set incrementer/shiff off -- delay 1000us -when "10001000000000001" => data_in1 <= "10"& x"31"; wr_en1 <= '1'; -- write charater "1" for testing only; when "10001000000011100" => data_in1 <= "00"& x"00"; wr_en1 <= '1'; -- do nothing finished initialization process when others => data_in1 <= "00"& x"00"; wr_en1 <= '0'; end case; if cnt_cmd(17) = '1' then cnt_cmd_enable <= '0'; else cnt_cmd_enable <= '1'; end if; end process; -- finished initialation process, set ready for new data ready <= not cnt_cmd_enable;

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--when ready, the fifo receives data from higer module --when not ready, the fifo receives data from this module for initizalation process process (data_in,data_in1,wr_en,wr_en2,cnt_cmd_enable) begin if cnt_cmd_enable = '0' then data_in2 <= data_in; wr_en2 <= wr_en; else data_in2 <= data_in1; wr_en2 <= wr_en1; end if; end process; end Behavioral;

Kt qu tng hp thit k trn FPGA Spartan 3E 3s500-pq208 vi tn s xung nhp c s 24Mhz thu c nh sau:
Selected Device : 3s500epq208-5 Number of Slices : 47 out of 4656 1% Number of Slice Flip Flops : 48 out of 9312 0% Number of 4 input LUTs : 90 out of 9312 0% Number of Ios : 14 Number of bonded IOBs : 14 out of 158 8% Number of GCLKs : 2 out of 24 8% --------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | --------------------+------------------------+-------+ cd/clk161 | BUFG | 39 | clk | BUFGP | 9 | --------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 4.188ns (Maximum Frequency: 238.780MHz) Minimum input arrival time before clock: 3.569ns Maximum output required time after clock: 7.739ns Maximum combinational path delay: 3.476ns --------------

Kt qu cho thy khi LCD_Driver chim kh t ti nguyn vi ch 90 LUT, hon ton ph hp cho vic gn vo cc thit k ln hn vi vai tr khi kt xut hin th thng tin. V tc th mch iu khin theo kt qu c th chy c tc 200Mhz trong khi yu cu thc t l 1Mhz. Kt qu thc t v thi gian sau kt ni v phn b nh sau:
Data Sheet report:

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All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk --------+---------+---------+---------+---------+ clk | 3.744| | | | --------+---------+---------+---------+---------+

Kt qu trn mch FPGA th hin hnh sau:

Hnh 4-73. Kt qu trn mch FPGA ca khi iu khin LCD 4.5. Thit k iu khin VGA trn FPGA 4.5.1 Yu cu giao tip VGA n gin Giao tip VGA trong ch n gin nht gm 5 tn hiu iu khin, cc tn hiu ny c ni vi chm cm 15-PIN theo s sau:

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Hnh 4-74. Mch giao tip VGA n gin Tn hiu RED, GREEN, BLUE tng ng th hin mu sc, vi 3 bit tn hiu ny th ti a c 8 mu hin th. c nhiu mu hin th hn s dng mt h thng cc in tr mc song song tng t nh h thng DAC, tc l in tr sau c gi tr ln gp hai ln in tr trc . Vi cch mc nh th vi mt t hp n u vo s sinh ra 2^n mc in p tng ng hay tng ng c 2^n mu sc khc nhau u ra. Tn hiu VS (Vertical Synchronous) v HS (Horizontal Synchronous) l cc tn hiu qut mn hnh theo phng ng v phng ngang tng ng, dng tn hiu v yu cu v mt thi gian ca cc tn hiu ny nh sau.

Hnh 4.75. Gin sng tn hiu qut ngang v dc cho mn hnh VGA Mn hnh s lm vic theo c ch qut theo tng hng t trn xung di, chu k lm ti mn hnh Trefresh c tnh bng tng thi gian qut ht ton 295

b mt lt mn hnh, tn s ny ty thuc vo ch phn gii mn hnh s hin th v ph thuc tn s qut h tr c bi mn hnh. Cc mn hnh hin i khc nhau v thng c gi tr tn s qut khong t 50Hz -100Hz. Thng tin chi tit yu cu v mt thi gian qut ca mn hnh c th tham kho t ngun. http://www.epanorama.net/documents/pc/vga_timing.html Ch phn cc ca xung qut c th dng hoc m, tham s xung qut trn hnh v theo phn cc dng, xung ng b mc thp, cc xung cn li c mc cao. V d cho ch 800x600 60Hz th cc tham s c th c tnh nh sau: Tham s vi xung qut ngang, xung nhp qut im nh F0 = 40Mhz, T0 = 1/40Mhz = 25ns. Bng 4-9 Tham s qut ngang VGA K Tn gi Gi tr S lng Tng thi gian hiu (xT0) m (us) Tpw Thi gian ng b 128 xT0 128 3,20 Tdisplay Thi gian hin th 800 xT0 800 20,00 Ths Tng thi gian qut 1056 xT0 1056 26,40 Tbp Thi gian vm sau 88 xT0 88 2,20 Tfp Thi gian vm trc 40 xT0 40 1,00 Tng thi gian qut ht 1 hng l Ths = 1056 xT0 = 26400 ns, t tnh c tn s qut hng l Fh = 1/26400 ns = 37,87Khz Tham s vi xung qut dc: Bng 4-10 K hiu Tpw Tdisplay Tvs Tbp Tfp Tham s qut dc VGA Tn gi Gi tr S lng Tng thi gian (xThs) m (us) Thi gian ng b 4 x Ths 4 105,60 Thi gian hin th 600 x Ths 600 15840,00 Tng thi gian qut 628 x Ths 628 1657,92 Thi gian vm sau 23 x Ths 23 607,20 Thi gian vm trc 1 x Ths 1 26,40 T tnh c chu k lm ti v tn s lm ti mn hnh 296

Trefresh = Tvs = 628 x Ths = 628 x 26400 = 16579200 ns = 16, 5792 us Trefresh = 1/ Trefresh = 1/ 16, 5792 us = 60Hz. 4.5.2. S khi iu khin VGA Theo nh l thuyt trn th vic iu khin VGA tng ng vi vic to ra xung cc xung qut VS v HS theo ng cc yu cu v mt thi gian. Cch n gin nht l s dng hai b m c ghp ni tip. S khi thit k nh sau:
DCM_CLK CLK_IN DCM_BLOCK (optional) VERTICAL COUNTER VS HORIZONTAL COUNTER HS

vcount CHARACTER_ ROM (optional) DATA_RAM (optional)

hcount

R G

RGB GENERATOR

Hnh 4-76 S khi iu khin VGA 4.5.3. Khi DCM Vi tn s qut 60Hz nh v d trn th xung nhp u vo l 40Mhz, nu dao ng thch anh trn mch FPGA c tn s ng bng tn s ny th khng cn thit phi c khi DCM, trong cc trng hp cn li th buc phi c khi DCM. DCM l khi c sn trong FPGA c kh nng iu chnh v pha tn s v dng ca xung nhp ng b. Trong v d ny ta dng DCM iu chnh tn s t 25Mhz ln tn s 40Mhz bng cch t cc tham s nhn v chia tn ln lt l 8 v 5 v: 40 Mhz = 25 Mhz * 8 / 5 Dng m t chun ca DCM c th tm trong menu Edit/Language Templates, m t di y c chnh sa cho DCM ca FPGA SPARTAN-3E (dcm.vhd)
----------------------------------------------- Engineer: Trinh Quang Kien

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---------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; ---------------------------------------------entity dcm_block is Port ( CLK_IN : in STD_LOGIC; DCM_CLK : out STD_LOGIC ); end dcm_block; ---------------------------------------------architecture Behavioral of dcm_block is Begin DCM_SP_inst : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 5, CLKFX_MULTIPLY => 8, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 40.0, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map ( CLKFX => DCM_CLK, -- DCM CLK synthesis out (M/D) CLKFB => CLK_IN, -- DCM clock feedback CLKIN => CLK_IN -- Clock input); end Behavioral; ------------------------------------------

4.5.4. Khi to xung qut ngang v dc y l khi ht nhn ca iu khin VGA, nhim v ca khi ny l to cc xung HS v VS bng hai b m c ghp ni tip, b m c s l b m cho xung qut ngang (HORIZONTAL COUNTER) vi xung u vo m l xung nhp DCM_CLK = 40 Mhz ly t DCM. B m th hai l cho xung qut ngang hay cn gi l b m hng (VERTICAL COUNTER) c tng ln 1 sau 298

khi mi hng c m xong. Tham s cho cc b m c t trong mt gi m t c tn vga_pkg.vhd vi ni dung nh sau:

library IEEE; use IEEE.STD_LOGIC_1164.all; package vga_pkg is -- horizontal timing (in pixels count ) constant H_DISPLAY : natural := 800; constant H_BACKPORCH : natural := 88; constant H_SYNCTIME : natural := 128; constant H_FRONTPORCH : natural := 40; constant H_PERIOD : natural := 1056; constant H_ONDISPLAY : natural := H_SYNCTIME + H_BACKPORCH; constant H_OFFDISPLAY : natural := H_ONDISPLAY + H_DISPLAY; constant H_COUNT_W : natural := 11; -- vertical timing (in lines count) constant V_DISPLAY : natural := 600; constant V_BACKPORCH : natural := 23; constant V_SYNCTIME : natural := 4; constant V_FRONTPORCH : natural := 1; constant V_PERIOD : natural := 628; constant V_ONDISPLAY : natural := V_SYNCTIME + V_BACKPORCH; constant V_OFFDISPLAY : natural := V_ONDISPLAY + V_DISPLAY; constant V_COUNT_W : natural := 10; end vga_pkg; package body vga_pkg is end vga_pkg;

Cc tham s ny phi khp vi cc yu cu v mt thi gian ca cc tn hiu HS v VS bng trn. M t ca khi to xung qut nh sau (vga_800x600x60Hz.vhd)
-- VGA controler for 800x600x60Hz -- the dcm_clk must around 40Mhz (generate by DCM if require) -- All timming information is get from http://www.epanorama.net/documents/pc/vga_timing.html -- Based on reference VGA project from Digilent -- Recreated by TQ KIEN library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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library work; use work.vga_pkg.all; library UNISIM; use UNISIM.VComponents.all; ------------------------------------------entity vga_800_600_60 is port( rst : in std_logic; dcm_clk : in std_logic; HS : out std_logic; VS : out std_logic; hcount : out std_logic_vector(H_COUNT_W-1 downto 0); vcount : out std_logic_vector(V_COUNT_W-1 downto 0); video_ena : out std_logic ); end vga_800_600_60; ------------------------------------------architecture Behavioral of vga_800_600_60 is -- horizontal and vertical counters signal hcnt : std_logic_vector(H_COUNT_W-1 downto 0) := (others => '0'); signal vcnt : std_logic_vector(V_COUNT_W-1 downto 0) := (others => '0'); signal SIG_POL : std_logic := '0'; -----------------------------------------begin hcount <= hcnt; vcount <= vcnt; -- increment horizontal counter at dcm_clk rate to H_PERIOD SIG_POL <= '0'; h_counter: process(dcm_clk) begin if(rising_edge(dcm_clk)) then if(rst = '1') then hcnt <= (others => '0'); elsif(hcnt = H_PERIOD) then hcnt <= (others => '0'); else hcnt <= hcnt + 1; end if; end if; end process h_counter; -- Horizotal timming detail -______________________ ________ --________| VIDEO |________|VIDEO(next line)

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-|-C-|----------D-----------|-E-| --__ ______________________________ ___________ -- |_| |_| -- |B| -- |---------------A----------------| --A (1056) Scanline time --B (128) Sync pulse lenght --C (88) Back porch --D (800) Active video time --E (40) Front porch -- SIG_POL is polarity of SYN signals, the Horizotal SYN is active by SIG_POL during sync time (B) ------------------------------------------hs_generate: process(dcm_clk) begin if(rising_edge(dcm_clk)) then if(hcnt >= H_SYNCTIME) then HS <= SIG_POL; else HS <= not SIG_POL; end if; end if; end process hs_generate; -- verital timming detail -______________________ ________ --________| VIDEO |________|VIDEO(next line) -|-C-|----------D-----------|-E-| --__ ______________________________ ___________ -- |_| |_| -- |B| -- |---------------A----------------| --A (628) Scanline time --B (4) Sync pulse lenght --C (23) Back porch --D (600) Active video time --E (1) Front porch -- SIG_POL is polarity of SYN signals, the Vertiacal SYN is active by SIG_POL during sync time (B) -----------------------------------------v_counter: process(dcm_clk) begin if(rising_edge(dcm_clk)) then if(rst = '1') then vcnt <= (others => '0'); elsif(hcnt = H_PERIOD) then

301

if(vcnt = V_PERIOD) then vcnt <= (others => '0'); else vcnt <= vcnt + 1; end if; end if; end if; end process v_counter; vs_generate: process(dcm_clk) begin if(rising_edge(dcm_clk)) then if (vcnt >= V_SYNCTIME) then VS <= SIG_POL; else VS <= not SIG_POL; end if; end if; end process vs_generate; -- enable video output when pixel is in visible area video_ena <= '1' when (hcnt > H_ONDISPLAY and hcnt < H_OFFDISPLAY and vcnt > V_ONDISPLAY and vcnt < V_OFFDISPLAY) else '0'; end Behavioral; --------------------------------------

4.5.5. Khi to im nh (RGB_Generator) Khi to im nh c u vo l cc gi tr ta hcount v vcount ca im nh v u ra l mu sc tng ng ca im nh , khi ny c th cha cc khi CHARACTER_ROM lu tr dng ca font ch trong ch TEXT hoc lu tr d liu (hnh nh) trong khi RAM. Trong v d ny ta s tm thi b qua cc khi trn v ch to mt khi n gin to s thay i mu sc theo mt s bit ca gi tr ta nhm mc ch quan st v kim tra, vi tng ng dng c th ngi s dng s phi thit k li cc khi ROM, RAM cho ph hp vi yu cu.
----------------------------------------- Company: BM KTVXL -- Engineer: Trinh Quang Kien ---------------------------------------library IEEE;

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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.vga_pkg.all; ---------------------------------------entity RGB_gen is port ( dcm_clk : in std_logic; video_ena: in std_logic; hcount : in std_logic_vector(H_COUNT_W-1 downto 0); vcount : in std_logic_vector(V_COUNT_W-1 downto 0); RED : out std_logic; BLUE : out std_logic; GREEN : out std_logic); end RGB_gen; ---------------------------------------architecture Behavioral of RGB_gen is begin process (dcm_clk) begin if rising_edge(DCM_CLK) then if video_ena = '1' then RED <= vcount(3); BLUE <= vcount(5); GREEN <= hcount(6); end if; end if; end process; end Behavioral; ---------------------------------------

4.5.6. Khi tng qut Khi tng qut c tn VGACOMP cha m t thit k c dng np vo FPGA ghp bi cc khi trn. Ni dung ca khi ny nh sau
-- vgacomp.vhd -- Trinh Quang Kien - BMKTVXL -------------------------------------------library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; library work; use work.vga_pkg.all;

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-----------------------------------------entity VgaComp is port ( CLK_25MHz : in std_logic; RST : in std_logic; RED : out std_logic; BLUE : out std_logic; GREEN : out std_logic; HS : out std_logic; VS : out std_logic); end VgaComp; architecture Structural of VgaComp is signal nRST : std_logic; signal video_ena : std_logic; signal dcm_clk : std_logic; signal CLK_IN : std_logic; signal hcount : std_logic_vector(H_COUNT_W-1 downto 0); signal vcount : std_logic_vector(V_COUNT_W-1 downto 0); -----------------------------------------component dcm_block is Port ( CLK_IN : in STD_LOGIC; DCM_CLK : out STD_LOGIC); end component; -----------------------------------------component vga_800_600_60 is port( rst : in std_logic; dcm_clk : in std_logic; HS : out std_logic; VS : out std_logic; hcount : out std_logic_vector(H_COUNT_W-1 downto 0); vcount : out std_logic_vector(V_COUNT_W-1 downto 0); video_ena : out std_logic); end component; -----------------------------------------component RGB_gen is port( dcm_clk : in std_logic; video_ena : in std_logic; hcount :in std_logic_vector(H_COUNT_W-1 downto 0); vcount :in std_logic_vector(V_COUNT_W-1 downto 0); RED : out std_logic; BLUE : out std_logic; GREEN : out std_logic);

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end component; -----------------------------------------begin CLK_IN <= CLK_25MHz; nRST <= not RST; dcm_gen: component dcm_block port map ( CLK_IN => CLK_IN, DCM_CLK => DCM_CLK); VgaCtrl800_600 : vga_800_600_60 port map ( dcm_clk => DCM_CLK, rst => nRST, video_ena => video_ena, HS => HS, hcount => hcount, vcount => vcount, VS=>VS); p_RGB : component RGB_gen port map ( dcm_clk => dcm_clk, video_ena => video_ena, hcount => hcount, vcount => vcount, RED => RED, BLUE => BLUE, GREEN => GREEN); end Structural;

Thit lp ci t cho u vo u ra ca thit k nh sau: (vgacomp.ucf). Thit lp ny c th khc nhau cho cc mch thc t khc nhau:
NET "BLUE" LOC = P83; NET "GREEN" LOC = P89; NET "RED" LOC = P90; NET "RST" LOC = P29; NET "CLK_25MHz" LOC = P184; NET "HS" LOC = P78; NET "VS" LOC = P82; NET "CLK_25MHz" TNM_NET = "CLK_25MHz"; TIMESPEC TS_CLK_25MHz = PERIOD "CLK_25MHz" 35 ns HIGH 50 %; NET "BLUE" SLEW = FAST; NET "CLK_25MHz" SLEW = FAST; NET "GREEN" SLEW = FAST; NET "HS" SLEW = FAST;

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NET "RED" SLEW = FAST; NET "VS" SLEW = FAST; OFFSET = OUT 35 ns AFTER "CLK_25MHz"; OFFSET = IN 35 ns VALID 35 ns BEFORE "CLK_25MHz" RISING;

V d trn minh ha cho qu trnh iu khin VGA bng thit k VHDL, ngi hc c th trn c s thit k cc khi iu khin VGA hon chnh c kh nng hin th k t vn bn, i tng ha theo yu cu. Kt qu tng hp cho thy khi thit k chim mt lng ti nguyn Logic rt nh v c th hot ng vi tc ln ti c 200Mhz ngha l c th p ng c nhng mn hnh c phn gii ln v tc qut cao.
Device utilization summary: --------------------------Selected Device : 3s500epq208-5 Number of Slices: 28 out of 4656 0% Number of Slice Flip Flops: 26 out of 9312 0% Number of 4 input LUTs: 49 out of 9312 0% Number of IOs: 7 Number of bonded IOBs: 7 out of 158 4% Number of GCLKs: 1 out of 24 4% Number of DCMs: 1 out of 4 25% ================================================== TIMING REPORT Clock Information: Clock Signal | Clock buffer(FF name) | Load | -------------+--------------------------+-------+ CLK | dcm_gen/DCM_SP_inst:CLKFX| 26 | -------------+--------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 4.770ns (Maximum Frequency: 209.651MHz) Minimum input arrival time before clock: 3.838ns Maximum output required time after clock: 4.040ns Maximum combinational path delay: No path found

Kt qu v mt thi gian tnh ca mch VGA sau khi kt ni v sp t nh sau:

Data Sheet report: ----------------All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk -------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

306

Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -------------+---------+---------+---------+---------+ clk | 3.744| | | | -------------+---------+---------+---------+---------+

Vi m ngun trn quan st trn thc t s thu c hnh nh c dng sau sau trn mn hnh:

Hnh 4.77. Kt qu trn mch FPGA ca khi iu khin VGA

307

Bi tp chng 4
1. Bi tp c s 1. Thit k, tng hp cc cng logic c bn trn FPGA kim tra trn mch th nghim. 2. Thit k, tng hp cc flip-flop D, JK, T, RS trn FPGA. Kim tra hot ng trn mch th nghim. 3. Tng hp cc khi m chia tn s t tn s ca b to dao ng ra tn s 1HZ, quan st kt qu bng Led Diod. 4. Thit k khi m nh phn 4 bit, tng hp v hin th trn Led 7 on. 5. Thit k, tng hp ng h s trn FPGA hin th gi ph thng qua 4 k t s ca led 7 on. S dng phm n t li gi pht, giy. 6. Thit k, tng hp b cng NBCD cho 2 s c 1 ch s trn FPGA hin th u vo v u ra trn led 7 on, trong u vo c ly t switch. 7. Thit k, tng hp b tr NBCD 1 s c 2 s cho 1 s c 1 ch s trn FPGA hin th kt qu v u ra trn led 7 on, trong u vo c ly t cc switch. 8. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc khi dch theo cc cch khc nhau: s dng ton t, khng dng ton t trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 9. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b cng theo cc cch khc nhau: s dng ton t, ni tip, ni tip bit, thy nh trc trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 10. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b nhn s nguyn khng du theo cc cch khc nhau: s dng ton t, cng dch tri, cng dch phi trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 11. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b nhn s nguyn khng du dng thut ton: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 12. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b chia s nguyn khng du theo cc cch khc nhau: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 308

13.

14.

15.

16.

17.

18.

S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b chia s nguyn c du theo cc cch khc nhau: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi cng s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi nhn s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi chia s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. Thit k tng hp khi FIFO trn FPGA bng cch s dng thut ton khi FIFO chng III v dng IP Core c sn, so snh kt qu tng hp theo tng cch. Xy dng khi nhn s dng Dedicated Multiplier, so snh kt qu tng hp vi cc b nhn s nguyn lm cc bi chng III. 2. Bi tp nng cao

1. Thit k khi truyn nhn thng tin d b ni tip (UART) hin thc ha trn FPGA thc hin truyn v nhn k t chun thng qua Hyper Terminal. 2. Thit k khi truyn nhn thng tin qua chun I2C, hin thc ha v kim tra trn FPGA vi IC AD/DA PCF8591. 3. Thit k khi truyn nhn thng tin qua giao thc chun SPI bng VHDL, hin thc ho v kim tra trn FPGA. 4. Thit k hon chnh khi truyn nhn chun PS/2 giao tip vi bn phm chun. 5. Thit k hon chnh khi truyn nhn chun PS/2 giao tip vi chut my tnh. 6. Thit k hon chnh khi giao tip vi mn hnh LCD 1602A cc ch lm vic 4 bit v 8 bit. 309

7. Thit k khi nhp liu t bn phm chun PS/2, d liu nhp vo c hin th ln mn hnh LCD1602A. 8. Thit k khi nhp liu t bn phm chun PS/2, d liu nhp vo c truyn thng qua cng giao tip RS232. 9. B tng hp tn s NCO, xut ra dng sng hnh sin vi tn s c th thay i c. 10. B iu ch, thu v bin i tn hiu AM n gin s dng khi NCO kt hp vi bin iu bin U0theo quy lut c gii tn thp hn nhiu so vi gii tn ca sng iu ch theo hnh v sau:

11. Thit k khi kt xut tn hiu iu ch xung di rng PWM (pulse wide modulation) nh hnh v sau
t1 t2 t3 t4

PWM

T0

T0

T0

T0

Tn hiu u ra l tn hiu xung vung c chu k khng i l T0 nhng c rng xung (mc 1) thay i theo thi gian t1, t2, t3, t4theo mt quy lut ty (ph thuc thng tin iu ch). 12. Thit k khi kt xut tn hiu iu ch xung di rng PPM (pulse phase modulation) nh hnh v sau

t1 PPM T

t2 T

t3 T

t3

310

Tn hiu u ra l tn hiu xung vung c c rng xung (mc 1) khng i T nhng c lch pha so vi xung chun ln lt cc gi tr t1, t2, t3, t4theo mt quy lut ty (ph thuc thng tin iu ch). Quan st kt qu trn Osiloscope. 13. Thit k v kim tra khi m thi gian v nh thi vi xung vo chun 1Mhz (chia t DCM) c chc nng lm vic tng t nh Timer0 v Timer1 trong vi iu khin 89c51. Cu to ca b m/nh thi gm c thanh ghi cu hnh TCON, hai thanh ghi m THLx, THx (vi x = 0, 1) Timers c th hot ng ch 8 bit t ng khi to li hoc ch 16-bit. Cc Timers phi sinh ra tn hiu bo ngt mi khi m xong. Chi tit xem thm trong ti liu hng dn ca 89c51 14. Thit k v kim tra khi m thi gian v nh thi vi xung vo chun 1Mhz (chia t DCM) c chc nng lm vic tng t nh Timer2 trong vi iu khin 89c52, ngoi nhng chc nng nh Timer1 v timer 2 cn c h tr cng vo ra tc cao. Chi tit xem thm trong ti liu hng dn ca 89C52. 15. Nghin cu xy dng khi m ha theo thut ton AES, m t bng VHDL, tng hp v hin thc ha trn FPGA. Xem thm trong ti liu [36]. 16. Nghin cu xy dng khi m ha theo thut ton DES, m t bng VHDL v hin thc ha trn FPGA. Xem thm trong ti liu gii thiu trong [37] 17. Nghin cu xy dng khi m ha theo thut ton RSA-128bit vi yu cu tnh c bn l thc hin php ton tnh module ca ly tha AB theo s N, Chi tit v RSA xem trong ti liu [38]. Trong thit k s dng khi nhn MontGomery phn bi tp chng III. Hin thc ha, kim tra trn FPGA. 18. Nghin cu thut ton CORDIC (Coordinate Rotation Digital Computer) ng dng tnh ton cc hm SIN, COSIN. Xem thm ti liu gii thiu trong [35]. 19. Nghin cu thut ton CORDIC (Coordinate Rotation Digital Computer) ng dng tnh ton cc hm ARCTAN. Xem thm ti liu gii thiu trong [35]. 20. Nghin cu xy dng s hin thc ha cho bin i Fourier DFT (Discret Fourier Transform ) v s hin thc ha trn FPGA vi N= 4, 8, 16. 21. Nghin cu xy dng s hin thc ha thit k bin i Fourier nhanh cho dy gi tr ri rc FFT (Fast Fourier Transform) cho N = 16 v phn chia theo c s 2, c s 4 theo thi gian. 22. Thit k mch lc s theo s di y:

311

 s trn k hiu Z tng ng l cc Flip-flop gi chm, k hiu tam gic l cc khi nhn, k hiu sig-ma l cc khi cng, ton b khi hot ng ng b. bi l cc hng s ca b lc, x[n], y[n] l chui tn hiu ri rc vo v ra t b lc. 23. Hin thc giao thc VGA trn mch FPGA c kh nng truy xut hnh nh v vn bn. Trong thit k s dng cc khi c bn trnh by trong mc 4.5 v b xung y khi ROM cho k t v khi RAM lu nh i tng hin th. 3. Cu hi n tp l thuyt 1. nh ngha FPGA, u im ca FPGA vi cc chip kh trnh khc. 2. Nguyn l lm vic ca FPGA, kh nng ti cu trc, ti nguyn FPGA. 3. Trnh by kin trc tng quan ca FPGA, cc dng ti nguyn ca FPGA. 4. Trnh by kin trc tng quan ca Spartan 3E FPGA, cc ti nguyn ca FPGA ny. 5. Trnh by cu trc chi tit ca CLB, SLICE, LUT. 6. Trnh by cu trc v nguyn l lm vic ca Arithmetic chain, Carry Chain, vai tr ca cc chui ny trong FPGA 7. Trnh by cu trc ca Programable Interconnects trong FPGA 8. Trnh by cu trc ca IOB trong FPGA. 9. Trnh by c im, cu trc v cch s dng ca Distributed RAM v Shift Register trong FPGA. 10. Trnh by c im, cu trc v cch s dng ca Block RAM v Multiplier 18x18 trong Spartan 3E FPGA. 11. Quy trnh thit k trn FPGA. 12. Khi nim tng hp thit k. Cch thit lp cc iu kin rng buc cho thit k. 13. Cc bc hin thc thit k (Translate, Mapping, Place & Routing) 14. Cc dng kim tra thit k trn FPGA 312

PH LC

313

Ph lc 1: THNG K CC HM, TH TC, KIU D LIU CA VHDL TRONG CC TH VIN CHUN IEEE.
1. Cc kiu d liu h tr trong cc th vin chun IEEE Tn kiu BIT BITVECTOR STD_ULOGIC STD_LOGIC STD_ULOGIC_VE CTOR STD_LOGIC_VEC TOR X01 X01Z UX01 UX01Z UNSIGNED SIGNED SMALL_INT CONV_INTEGER CONV_INTEGER SIGNED UNSIGNED SIGNED UNSIGNED Gii thch Th vin IEEE.STD_LOGIC_1164 STD_ULOGIC STD_LOGIC_VECTOR 9 mc logic chun gm X, 0, 1, L, H, Z, W, - , U Ging STD_ULOGIC nhng c nh ngha cch thc cc gi tr hp vi nhau Chui STD_ULOGIC Chui STD_LOGIC Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, X) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, X, Z) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, U, X) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, U, X, Z) Th vin IEEE.STD_LOGIC_ARITH Chui STD_LOGICc xem nh s khng du Chui STD_LOGIC c xem nh s c du Kiu INTEGER vi ch cc gi tr 0, 1 Th vin IEEE.STD_LOGIC_UNSIGNED STD_LOGIC_VECTOR INTEGER Th vin IEEE.STD_LOGIC_SIGNED STD_LOGIC_VECTOR INTEGER Th vin IEEE.NUMERIC_BIT Chui BIT c xem nh s c du Chui BIT c xem nh s khng du Th vin IEEE.NUMERIC_STD Chui STD_LOGICc xem nh s c du Chui STD_LOGIC c xem nh s khng du 314

2. Cc hm thng dng h tr trong cc th vin chun IEEE Tn hm (i bin) Gi tr tr v Ghi ch

Th vin IEEE.STD_LOGIC_1164 AND( l : std_ulogic; r : std_ulogic ) UX01 NAND( l : std_ulogic; r : std_ulogic ) UX01 OR( l : std_ulogic; r : std_ulogic ) UX01 NOR( l : std_ulogic; r : std_ulogic ) UX01 XOR( l : std_ulogic; r : std_ulogic ) UX01 XNOR( l : std_ulogic; r : std_ulogic ) UX01 NOT( l : std_ulogic; r : std_ulogic ) UX01 AND( l, r : std_logic_vector ) std_logic_vector NAND( l, r : std_logic_vector) std_logic_vector OR( l, r : std_logic_vector) std_logic_vector NOR( l, r : std_logic_vector ) std_logic_vector XOR( l, r : std_logic_vector) std_logic_vector XNOR( l, r : std_logic_vector) std_logic_vector NOT(( l, r : std_ulogic_vector) std_logic_vector AND( l, r : std_ulogic_vector ) std_ulogic_vector NAND( l, r : std_ulogic_vector) std_ulogic_vector OR( l, r : std_ulogic_vector) std_ulogic_vector NOR( l, r : std_ulogic_vector ) std_ulogic_vector XOR( l, r : std_ulogic_vector) std_ulogic_vector XNOR( l, r : std_ulogic_vector) std_ulogic_vector NOT(( l, r : std_ulogic_vector) std_ulogic_vector rising_edge (SIGNAL s : std_ulogic) BOOLEAN falling_edge (SIGNAL s : std_ulogic) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic) BOOLEAN Th vin IEEE.STD_LOGIC_ARITH 315

+, - (L, R: SIGNED, SIGNED) +, - (L, R: UNSIGNED, UNSIGNED) +, - (L, R: UNSIGNED, SIGNED) +, - (L: SIGNED, R: INTEGER) +, - (L: UNSIGNED, R: INTEGER) +, - (L: STD_ULOGIC, R: SIGNED) +, - (L : STD_ULOGIC, R: UNSIGNED) +, - (L: SIGNED, R: UNSIGNED) +, - (L: INTEGER, R: SIGNED, UNSIGNED) +, - (L: STD_ULOGIC, R: SIGNED, UNSIGNED) * (L, R: SIGNED, SIGNED) * (L, R: UNSIGNED, UNSIGNED) * (L, R: UNSIGNED, SIGNED) * (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) <, <=, >, >=, = (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) <, <=, >, >=, = (L: INTEGER, R: SIGNED, UNSIGNED) SHL(ARG: SIGNED; COUNT: UNSIGNED) SHL(ARG: UNSIGNED; COUNT: UNSIGNED) SHR(ARG: SIGNED; COUNT: UNSIGNED) SHR(ARG: UNSIGNED; COUNT: UNSIGNED)

SIGNED UNSIGNED SIGNED SIGNED UNSIGNED SIGNED UNSIGNED STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR SIGNED UNSIGNED SIGNED STD_LOGIC_VECTOR BOOLEAN BOOLEAN SIGNED UNSIGNED SIGNED UNSIGNED

Th vin IEEE.STD_LOGIC_UNSIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) <, <=, >, >=, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) <, <=, >, >=, = (L: STD_LOGIC_VECTOR, R: BOOLEAN 316

STD_LOGIC_VECTOR) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Th vin IEEE.STD_LOGIC_SIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) <, <=, >, >=, = (L: STD_LOGIC_VECTOR, R: BOOLEAN STD_LOGIC_VECTOR) <, <=, >, >=, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Th vin IEEEE.NUMERIC_BIT +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED <, <=, >, >=, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN <, <=, >, >=, = (L: SIGNED, R: SIGNED) BOOLEAN <, <=, >, >=, = (L: INTEGER, R: SIGNED) BOOLEAN <, <=, >, >=, = (L: NATURAL, R: UNSIGNED) BOOLEAN 317

UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED RESIZE(L: UNSIGNED, R: NATURAL) UNSIGNED RESIZE(L: SIGNED, R: NATURAL) SIGNED Th vin IEEEE.NUMERIC_STD +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED <, <=, >, >=, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN <, <=, >, >=, = (L: SIGNED, R: SIGNED) BOOLEAN <, <=, >, >=, = (L: INTEGER, R: SIGNED) BOOLEAN <, <=, >, >=, = (L: NATURAL, R: UNSIGNED) BOOLEAN UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED 318

RESIZE(L: UNSIGNED, R: NATURAL) RESIZE(L: SIGNED, R: NATURAL)

UNSIGNED SIGNED

3. Cc hm phc v cho qu trnh m phng kim tra thit k Tn hm (i bin) Gi tr tr v Th vin IEEE.STD_LOGIC_TEXTIO READ(l : inout LINE, R: out std_ulogic ) std_ulogic trong R READ(l : inout LINE, R: out std_ulogic, Good: std_ulogic trong R Boolean ) READ(l : inout LINE, R: out std_ulogic_vector ) std_ulogic_vector trong R READ(l : inout LINE, R: out std_ulogic_vector, std_ulogic_vector Good: Boolean) trong R WRITE(l : inout LINE, R: in std_ulogic_vector ) LINE WRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) READ(l : inout LINE, R: out std_logic_vector) std_logic trong R READ(l : inout LINE, R: out std_logic_vector, std_logic trong R Good: Boolean) WRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_ulogic_vector) std_logic trong R HREAD(l : inout LINE, R: out std_ulogic_vector, std_logic trong R Good: Boolean) HWRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_logic_vector) std_logic trong R HREAD(l : inout LINE, R: out std_logic_vector, std_logic trong R Good: Boolean) HWRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) OREAD(l : inout LINE, R: out std_ulogic_vector) std_logic trong R OREAD(l : inout LINE, R: out std_ulogic_vector, std_logic trong R Good: Boolean) Ghi ch

319

OWRITE(l : inout LINE, R: in std_ulogic_vector, Good: Boolean) OREAD(l : inout LINE, R: out std_logic_vector) OREAD(l : inout LINE, R: out std_logic_vector, Good: Boolean) OWRITE(l : inout LINE, R: in std_logic_vector, Good: Boolean) Th vin STD.ENV STOP (STATUS: INTEGER) FINISH (STATUS: INTEGER) RESOLUTION_LIMIT ()

LINE std_logic trong R std_logic trong R LINE

PROCEDURE UNSIGNED Delay_length (Bc thi gian c s ca qu trnh m phng) Th vin IEEE.STD_TEXTIO READLINE (file f: TEXT; L: out LINE) String trong LINE READ(L:inout LINE; VALUE: out bit; GOOD : BIT trong VALUE out BOOLEAN) READ(L:inout LINE; VALUE: out bit) BIT trong VALUE READ(L:inout LINE; VALUE: out bit_vector; bit_vector trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out bit_vector) bit_vector trong VALUE READ(L:inout LINE; VALUE: out BOOLEAN; BOOLEAN trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out BOOLEAN) BOOLEAN trong VALUE READ(L:inout LINE; VALUE: out Charater; Charater trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out Charater) Charater trong VALUE READ(L:inout LINE; VALUE: out INTEGER; INTEGER trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out INTEGER) INTEGER trong 320

READ(L:inout LINE; VALUE: out REAL; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out REAL) READ(L:inout LINE; VALUE: out STRING; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out STRING) READ(L:inout LINE; VALUE: out TIME; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out TIME) SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL); OREAD(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN) OREAD(L:inout LINE; VALUE: out bit_vector)

VALUE REAL VALUE REAL VALUE STRING VALUE STRING VALUE TIME VALUE TIME VALUE STRING VALUE bit_vector VALUE bit_vector VALUE

trong trong trong trong trong trong trong trong trong

HREAD(l : inout LINE, R: out bit_vector) Bit_vector trong R HREAD(l : inout LINE, R: out bit_vector, Good: Bit_vector trong R Boolean) WRITELINE (file f : TEXT; L : inout LINE) Ghi LINE ra file WRITE(L : inout LINE; VALUE : in bit) WRITE(L : inout LINE; VALUE : in bit_vector) WRITE(L : inout LINE; VALUE : in BOOLEAN) WRITE(L : inout LINE; VALUE : in CHARACTER) WRITE(L : inout LINE; VALUE : in INTEGER) WRITE(L : inout LINE; VALUE : in REAL) WRITE(L : inout LINE; VALUE : in TIME) SWRITE(L : inout LINE; VALUE : in STRING) OWRITE(l : inout LINE, R: in BIT_VECTOR) 321

HWRITE (l : inout LINE, R: in BIT_VECTOR) 4. Cc hm bin i kiu d liu dng trong VHDL Tn hm (i bin) Gi tr tr v Th vin IEEE.STD_LOGIC_1164 TO_BIT(Arg: STD_ULOGIC) BIT TO_BITVECTOR (Arg: STD_LOGIC_VECTOR) BIT_VECTOR BIT_VECTOR TO_BITVECTOR (Arg:STD_ULOGIC_VECTOR) TO_STD_ULOGIC (Arg: BIT) STD_ULOGIC TO_STD_LOGICVECTOR (Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_STD_LOGICVECTOR (Arg: STD_LOGIC_VEC STD_ULOGIC_VECTOR) TOR TO_STD_ULOGICVECTOR (Arg: STD_ULOGIC_VE BIT_VECTOR) CTOR TO_STD_ULOGICVECTOR(Arg: STD_ULOGIC_VE STD_LOGIC_VECTOR); CTOR TO_X01(Arg: STD_LOGIC_VECTOR) STD_LOGIC_VEC TOR TO_X01 (Arg: STD_ULOGIC_VECTOR) STD_ULOGIC_VE CTOR TO_X01 (Arg: STD_ULOGIC) X01 TO_X01(Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_X01 (Arg: BIT_VECTOR) STD_ULOGIC_VE CTOR TO_X01 (Arg: BIT) X01 TO_X01Z(Arg: STD_LOGIC_VECTOR) STD_LOGIC_VEC TOR TO_X01Z(Arg: STD_ULOGIC_VECTOR) STD_ULOGIC_VE CTOR TO_X01Z(Arg: STD_ULOGIC) X01Z Ghi ch

322

TO_X01Z(Arg: BIT_VECTOR)

STD_ULOGIC_VE CTOR TO_X01Z(Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_X01Z(Arg: BIT) X01Z TO_UX01(Arg: STD_LOGIC_VECTOR) STD_LOGIC_VEC TOR TO_UX01(Arg: STD_ULOGIC_VECTOR) STD_ULOGIC_VE CTOR TO_UX01(Arg: STD_ULOGIC) X01Z TO_UX01(Arg: BIT_VECTOR) STD_ULOGIC_VE CTOR TO_UX01(Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_UX01(Arg: BIT) X01Z Th vin IEEE.STD_LOGIC_ARITH CONV_INTEGER (Arg: INTEGER) INTEGER CONV_INTEGER (Arg: UNSIGNED) INTEGER CONV_INTEGER (Arg: SIGNED) INTEGER CONV_INTEGER (Arg: STD_ULOGIC) SMALL_INT CONV_UNSIGNED (Arg: INTEGER, Size UNSIGNED INTEGER) CONV_UNSIGNED (Arg: UNSIGNED, Size UNSIGNED INTEGER) CONV_UNSIGNED (Arg: SIGNED, Size UNSIGNED INTEGER) CONV_UNSIGNED (Arg: STD_ULOGIC, Size UNSIGNED INTEGER) CONV_SIGNED (Arg: INTEGER, Size INTEGER) SIGNED CONV_SIGNED (Arg: UNSIGNED, Size SIGNED INTEGER) CONV_SIGNED (Arg: SIGNED, Size INTEGER) SIGNED CONV_SIGNED (Arg: STD_ULOGIC, Size SIGNED INTEGER) 323

CONV_STD_LOGIC_VECTOR (Arg: INTEGER, STD_LOGIC_VEC Size INTEGER) TOR CONV_STD_LOGIC_VECTOR (Arg: STD_LOGIC_VEC UNSIGNED, Size INTEGER) TOR CONV_STD_LOGIC_VECTOR(Arg: SIGNED, STD_LOGIC_VEC Size INTEGER) TOR CONV_STD_LOGIC_VECTOR(Arg: STD_LOGIC_VEC STD_ULOGIC, Size INTEGER) TOR EXT (Arg: STD_LOGIC_VECTOR, Size STD_LOGIC_VEC INTEGER) TOR SXT (Arg: STD_LOGIC_VECTOR, Size STD_LOGIC_VEC INTEGER) TOR Th vin IEEE.STD_LOGIC_UNSIGNED CONV_INTEGER (STD_LOGIC_VECTOR) INTEGER Th vin IEEE.STD_LOGIC_SIGNED CONV_INTEGER (STD_LOGIC_VECTOR) INTEGER Th vin IEEE.NUMERIC_BIT TO_INTEGER (Arg: UNSIGNED) INTEGER TO_INTEGER(Arg: UNSIGNED) INTEGER TO_SIGNED (Arg: INTEGER, Size NATURAL) SIGNED TO_UNSIGNED (Arg: INTEGER, Size UNSIGNED NATURAL) Th vin IEEE.NUMERIC_STD TO_INTEGER (UNSIGNED) INTEGER TO_INTEGER (UNSIGNED) INTEGER TO_SIGNED (Arg: INTEGER, Size NATURAL) SIGNED TO_UNSIGNED (Arg: INTEGER, Size UNSIGNED NATURAL)

324

Ph lc 2: THC HNH THIT K VHDL

325

Bi 1: M phng VHDL trn ModelSim

326

1. Mc ch Gip sinh vin lm quen vi chng trnh m phng Modelsim, lm quen vi cu trc chng trnh VHDL v cch kim tra nhanh mt thit k trn VHDL.Yu cu sinh vin phi c kin thc c s v VHDL 2. Gii thiu v chng trnh m phng Modelsim. Do cc ngn ng m t phn cng nh VHDL c chun ha bi IEEE v c cng b rng ri nn c rt nhiu cc phn mm m phng mch s c nhiu cng ty khc nhau pht trin. im chung ca cc chng trnh ny l u phi c mt trnh bin dch v c kh nng m phng mch theo thi gian thc, kt xut kt qu mt s dng nht nh nh File text, file nh kiu, hay ph bin v trc quan nht l di dng gin sng. Di y s gii thiu chng trnh m phng l ModelSim, y l mt chng trnh m phng kh mnh v chnh xc c pht trin bi Mentor Graphics.

ModelSim l mt chng trnh phn mm thng mi, tuy vy bn cnh cc phin bn phi tr tin license, c phin bn min ph dnh cho sinh vin v ngi nghin cu khng s dng vi mc ch thng mi. Phin bn ny c tn 327

l ModelSim Student Edition c th c ti trc tip t trang ch ca Mentor Graphics theo a ch http://model.com/content/modelsim-pe-student-edition-hdlsimulation Sau khi ci chng trnh s i hi ci t cp php s dng (license). c c license cn phi iu vo bn khai bo cc thng tin c nhn nh hm th, a ch vv... Mentor Graphic s gi vo hm th ca bn mt file license c tn l student_license.dat, file ny cho php s dng phn mm trong vng 180 ngy, kch hot license ch vic copy vo th mc gc ca modelSim (thng l C:\Modeltech_pe_edu_6.5 trong 6.5 l s hiu phin bn ca chng trnh) Ch : Hng dn m phng mt thit k v s dng chng trnh c trong th mc C:\Modeltech_pe_edu_6.2f\docs\pdfdocs, i vi cc phin bn khc nhau th c th ng dn s khc nhau. Sau y chng ta s ln lt hc cch s dng chng trnh thng qua mt v d c th. 3. Vit m ngun VHDL Trong Modelsim cng tch hp mt trnh son tho file ngun tuy vy cng nh cc ngn ng lp trnh khc m ngun VHDL ca thit k c th c son tho bng bt k mt chng trnh son tho no. Mt trong nhng chng trnh son tho kh tt v tin dng l Notepad++ (http://notepad-plusplus.org/download), chng trnh ny h tr hin th nhiu ngn ng lp trnh khc nhau trong c VHDL v Verilog. File ngun ca m VHDL c ui l .vhd. Khi son tho file c ui dng ny bng Notepad th ton b cc t kha, cu trc ngn ng c lm m hoc i mu cho d quan st v sa li.

328

Chng trnh Notepad++ n gin v d hiu phn ny ta s minh ha bng v d quen thuc v b cng 4 bit. B cng c thit k n gin nht bng cch ghp ni tip 4 khi full_adder 1 bit.
b3 a3 b2 a2 b1 a1 b0 a0

FULL_ADDER

C(2)

FULL_ADDER

C(1)

FULL_ADDER

C(0)

FULL_ADDER

CI

CO

S3

S2

S1

S0

Cu trc ca 4 bit - adder Khi full_adder nh trn l thuyt c th m t theo cc kin trc khc nhau, y n gin ta chn kiu m t theo lung d liu (dataflow) Bc 1: To trong th mc D:\Student mt th mc c tn adder4. Th mc chng ta lm vic s l D:\Student\adder4 Bc 2: Trong Notepad++ to mi mt file bng cach chn menu File/new, son tho file vi ni dung sau, son tho xong chn File/Save, v lu file di tn full_adder.vhd trong th mc lm vic D:\Student\adder4, lu lu di dng vhd chn File types phi chn l All files(*) 329

Ni dung full_adder.vhd
------------ full_adder ----------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity full_adder is port (A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic ); end full_adder; ----------------------------------------architecture dataflow of full_adder is begin S <= A xor B xor Cin; Cout <= (A and B) or (Cin and (a or b)); end dataflow; -----------------------------------------

330

Bc 3: To m ngun ca b cng 4-bit, lu thnh file adder4.vhd vi ni dung nh sau:

-------------- 4-bit adder -------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder4 is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic); end adder4; -----------------------------------------architecture structure of adder4 is signal C: std_logic_vector(2 downto 0); -- declaration of component full_adder component full_adder port ( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic ); end component; begin u0: component full_adder port map (A => A(0), B => B(0), Cin => CI, S =>Sum(0), Cout => C(0)); u1: component full_adder port map (A => A(1), B => B(1), Cin => C(0), S =>Sum(1), Cout => C(1)); u2: component full_adder port map (A => A(2), B => B(2), Cin => C(1), S =>Sum(2), Cout => C(2)); u3: component full_adder port map (A => A(3), B => B(3), Cin => C(2), S =>Sum(3), Cout => CO); end structure;

4. Bin dch thit k. to bin dch thit k ta lm ln lt cc bc sau: 331

Bc 4: Khi ng Modelsim, ti menu File chn Change Directory, ti menu Change directory chn Chn ng dn ti th mc lm vic D:\Student\adder4\ cha cc ngun va to adder4.vhd, full_adder.vhd.

Bc 5: To th vin work bng cch g lnh sau vo ca s Transcript ca Modelsim:

vlib work

332

Bc 6: Bin dch cc m ngun bng cch g cc lnh sau vo ca s Transcript

vcom full_adder.vhd vcom adder4.vhd

333

Khi trnh bin dch pht hin ra li v mt c php th n s thng bo chnh xc dng tng ng gy ra li. Nu nh m ngun ca thit k khng c li th bin dch xong s cho ra kt qu nh hnh trn. 5. M phng v kim tra thit k. Kim tra nhanh thit k bng cch a vo u vo ca DUT cc gi tr c nh v kim tra trc tip kt qu u ra. Kim tra nhanh cho php pht hin v sa nhng li v mt chc nng n gin trc khi bc vo bc kim tra vi s lng ln t hp gi tr u vo. Bc 7: kim tra nhanh b cng thit k trn to thm mt file adder4_test.vhd trong th mc lm vic vi ni dung nh sau nh sau:
-----------------adder4_test--------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ------------------------------------------entity adder4_test is end adder4_test; ------------------------------------------architecture test of adder4_test is component adder4 is port( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); CI : in std_logic; SUM : out std_logic_vector(3 downto 0); CO : out std_logic ); end component; -- khai bao cac tin hieu vao ra cho DUT signal A : std_logic_vector(3 downto 0) := "0101"; signal B : std_logic_vector(3 downto 0) := "1010"; signal CI : std_logic := '1'; -- output--signal SUM : std_logic_vector(3 downto 0); signal CO : std_logic; begin DUT: component adder4 port map ( A => A, B=> B, CI => CI, SUM => SUM, CO =>CO );

334

end test; --------------------------------------------test_adder4 l mt thit k m khng cha bt c cng vo ra no

phn khai bo. Kin trc ca n gm hai phn, phn khai bo tn hiu s khai bo cc tn hiu vo ra ca adder4 trong i vi cc tn hiu u vo A = 0101, B = 1010, CI_t = 1; i vi cc tn hiu u ra th trng. Phn hai l khai bo s dng adder4 nh mt khi con c tn l dut (device under test) v gn cc cng vo ra tng ng nh trn. Bc 8: Tin hnh bin dch file adder4_test.vhd ny bng lnh sau trong ca s transcript tng t lm trong bc 6).
vcom adder4_test.vhd

Bc 9: Khi to m phng thit k bng lnh:

vsim adder4_test

Bc 10: B xung cc tn hiu vo ca s wave form quan st, thc hin g cc lnh sau vo ca s Transcript
add add add add wave wave wave wave sim:/adder4_test/dut/a sim:/adder4_test/dut/b sim:/adder4_test/dut/CI sim:/adder4_test/dut/CO

335

add wave sim:/adder4_test/dut/SUM

Mi lnh trn s hin th mt tn hiu tng ng vo gin sng, bng cch ta c th la chn cc tn hiu nht nh theo di. Sau khi thc hin cc bc trn th c th tin hnh chy m phng. M phng c th chy bng nt cng c Run trn thanh cng c ca ca s gin sng:

Bc 11: Chy m phng v quan st kt qu trn waveform bng cch g lnh run 100 ns vo ca s Transcript sau m rng ca s Waveform bn phi quan st.
run 1000 ns

Khi gp lnh ny chng trnh s chy m phng trong 1000 ns. Kt qu ra nh sau:

336

Quan st trn hnh c v so snh vi m ngun ca adder4_testbench c th thy vi a = 0101 = 5, b=1010 = 15, CI = 1 th cho ra kt qu sum = 0000 = 0 v CO = 1. Bc 12: To mt file run.do lu vo trong th mc lm vic vi ni dung nh sau:
quit -sim vlib work vcom full_adder.vhd vcom adder4.vhd vcom adder4_test.vhd vsim adder4_test add add add add add wave wave wave wave wave sim:/adder4_test/a sim:/adder4_test/b sim:/adder4_test/CI sim:/adder4_test/CO sim:/adder4_test/SUM

run 1000 ns

Dng th nht kt thc bt k m phng no ang thc thi nu n tn ti, dng th hai to th vin work nu n cha tn ti, tip n l cc lnh vcom bin dch cc file m ngun t thp n cao. Lnh vsim tin hnh m phng, sau l cc lnh b xung tn hiu cn theo di vo gin sng. Lnh cui cng l lnh run dng chy m phng. Bc 13: Trong ca s transcript ca modelsim bin dch v chy li m phng ta ch nh sau.
do run.do

6. Bi tp sau thc hnh - Da trn quy trnh hc, xy dng b cng 8 bit v thc hin m phng kim tra b cng trn modelsim theo cc bc trn. - Vit m t Full adder bng kin trc kiu hnh vi v thc hin m phng theo cc bc trn - Xy dng b cng trn c s Full adder theo kiu hnh vi.

337

Bi 2: Xy dng b cng tr trn c s khi cng bng ton t

338

1. Mc ch Thng qua v d xy dng khi cng tr s dng ton t +, trong bi thc hnh ny sinh vin t vit m t cho cc khi thit k, qua n tp li cc cu trc lnh VHDL, cch s dng tham s tnh, cch ci t khi con, cch thc kim tra thit k. Yu cu vi sinh vin c kin thc c s v VHDL, s dng thnh tho Modelsim. 2. Khi cng n gin Khi cng n gin: thc hin php cng gia hai s c biu din di dng std_logic_vector hay bit_vector. Cc cng vo gm hng t A, B, bit nh Cin, cc cng ra bao gm tng Sum, v bit nh ra Cout:
A B Cin

Cout

Sum

Bc 1: Vit m t (adder.vhd) cho khi cng s dng trc tip ton t cng, u vo A, B v u ra Sum c kiu STD_LOGIC_VECTOR 32 bit, Cout v Cin c kiu STD_LOGIC. Hng dn: Khi buc phi khai bo th vin nh sau:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

Khi cng n gin c th vit bng c php

SUM <= a +b;

Lnh ny t trc tip m t kin trc (dng m t Dataflow). Tuy vy c c bit nh Cout th cn b xung thm 1 bit 0vo cc gi tr A, B nh sau: Khai bo cc tn hiu b xung trong phn khai bo kin trc:
Signal A1 : std_logic_vector(32 downto 0); Signal B1 : std_logic_vector(32 downto 0);

339

Signal Sum1 : std_logic_vector(32 downto 0);

V thc hin trong phn m t kin trc nh sau:

A1 <= 0 & A; B1 <= 0 & B; Sum1 <= A1 + B1 + Cin;

Khi gi tr Cout l bit cao nht ca Sum1

Cout <= Sum1(32);

Cn Sum l 32 bit thp:

Sum <= Sum1(31 down to 0);

Bc 2: Vit khi kim tra cho b cng va vit bng VHDL, thc hin m phng kim tra. Kt qu m phng phi th hin c nh sau:

Hng dn: S kim tra nhanh nh sau:

INPUTs ASIGNMENT

DUT

Khi kim tra nhanh l khi khng c u ra u vo, nhim v chnh l t cc gi tr cho cc cng u vo ca khi kim tra. Khi kim tra c khai bo thc th l
entity test_adder4_gen is end test_adder4_gen;

ci t khi thit k con ca khi adder cn khai bo khi con (khai bo component) nh sau trong phn khi bo kin trc:
component adder is port( A : in std_logic_vector(31 downto 0); B : in std_logic_vector(31 downto 0); Cin : in std_logic; SUM : out std_logic_vector(31 downto 0); Cout : out std_logic );

Ci t khi con trc tip trong phn m t kin trc (khi begin/end chnh): 340

DUT: component adder port map ( A, B, Cin, Sum, Cout);

Bc 3: Xem li phn l thuyt v khai bo tham s tnh, b xung vo b cng tham s tnh N l s bit. Hng dn: Tham s tnh khai bo trong khai bo thc th ca thit k. V d:
entity adder is generic (N : natural :=32); port (

S dng gi tr tham s tnh ny trong thit k ty bin s Bit ca cc hng t v kt qu nh sau: Vi cc cng
A : in std_logic_vector(N-1 downto 0); Sum : out std_logic_vector(N-1 downto 0);

Vi cc tn hiu:
signal A1 : std_logic_vector(N downto 0);

Bc 4: Thc hin thay i khi kim tra kim tra cho b cng dng tham s tnh N, thay i gi tr N = 16 v thc hin kim tra li nh bc 2. Hng dn: ci t khi con c tham s tnh th phi ci t tham s tnh tng t nh ci t cc tn hiu cho cng, xem v d sau y:
adder32: component adder generic map (32) port map (A, B, Cin, Sum, Cout);

*Lu l sau generic map () khng c du ; hay , m trng. 3. Khi tr Bc 5: Nghin cu cu trc khi tr nh sau: V cc s c du trn my tnh c biu din di dng s b 2 (2complement), do thc hin php tr A-B th tng ng vi thc hin A + b2(B) Xt v d A = 10 = 1010, B = 5 = 0101 biu din di dng s c du 5bit ta phi thm bit du bng 0 vo trc.
A = 01010, B2(A) = not (A) + 1 = 10101 + 1 B = 00101, B2(B) = not (B) + 1 = 11010 + 1 = 10110 = 11011

Tnh A B:
A 01010 01010 - = = + B 00101 11011

341

1 00101

Loi b bit nh kt qu cui cng ta c A B = 00101 = 5. Tnh B A:

B 00101 00101 - = = + A 01010 10110 0 11011

Loi b bit nh ta c B A = 11101, y l s m, mun tnh gi tr tuyt i kim tra li ly b 2 ca 11101

B 2 (11101) = 00100 + 1 = 00101 = 5

vy B A = -5 Da trn tnh cht trn ca s b hai ta ch cn thay i mt cht trong cu trc ca b cng n c kh nng thc hin c php cng ln php tr m khng phi thay i nhiu v cu trc phn cng. Ti u vo c thm tn hiu SUB, tn hiu ny quyt nh s thc hin php cng hay php tr. Khi SUB = 1 ly b 2 ca B s ly o B v cho gi tr u vo Cin =1, hin thc trn mch cu trc b cng c b xung mt khi MUX trc cng B, khi ny c hai u vo l B v not B, nu SUB= 0 th B c chn, nu SUB = 1 th not B c chn. u vo Cin c OR vi SUB trc khi vo b cng.
A B Sub Cin

MUX

Cout

Sum

Bc 6: Vit m t cho khi MUX 2 u vo trn hnh v, s bit ca cc d liu u ci t bng tham s tnh N nh trng hp ca khi cng, vit khi kim tra hot ng ca khi MUX. 342

Hng dn: vit khi MUX c th dng cu trc process c danh sch sensitive list l cc tn hiu u vo v cu trc IF THEN / END IF;
process (Sel, data_in1, data_in2) if Sel = '1' then data_out <= data_in1; else data_out <= data_in1; end if;

kim tra khi MUX c th thc hin tng t nh kim tra khi cng. Bc 7: Vit m t b cng tr theo s trn, khi trn thc hin php cng nu nh tn hiu Sub = 0 v thc hin tr nu nh Sub = 0. Hng dn: Khi tr c ghp bi khi cng, khi MUX, v cng OR hai u vo, vi cng OR hai u vo dng trc tip ton t logic OR, cn hai khi cng v MUX m t nh trn. Khi cng/tr vit theo kiu cu trc. Bc 8: Thc hin m phng kim tra khi cng tr, tn hiu SUB cn c thay i theo thi gian quan st kt qu vi cc php ton khc nhau. Hng dn: thay i tn hiu SUB (hoc bt k tn hiu no theo thi gian dng cu trc WAIT FOR ca VHDL:
wait for 20 ns; SUB <= '0'; wait for 100 ns; SUB <= '0'; wait for 100 ns; SUB <= '1';

4. Bi tp sau thc hnh - Nm l thuyt cu trc ca khi cng/tr. - Thay i m t ca b cng theo s trn bng b cng ni tip m t bi th nghim th nht. - Xy dng khi cng NBCD trn dng ton t cng. - Xy dng khi tr NBCD dng ton t cng.

343

Bi 3: Khi dch v thanh ghi dch

344

1. Mc ch Vit m t v kim tra cho khi dch bng cc phng php khc nhau: bng ton t dch, bng s thut ton dch. Cc to nhiu gi tr kim tra bng m VHDL, cch vit v s dng thc th c nhiu kin trc. Yu cu vi sinh vin C kin thc c s v VHDL, s dng thnh tho Modelsim. 2. Khi dch dng ton t dch Cc php ton quan h gm sll, srl, sla, sra, rol, ror c h tr trong th vin ieee.numeric_bit, v ieee.numeric_std. C php ca cc lnh dch c hai tham s l sho (shift operand) v shv (shift value), v d c php ca sll nh sau
sha sll shv;

Kiu Kiu kt ca qu shv sll Dch tri logic Mng 1 chiu kiu BIT hoc Integer Cng kiu BOOLEAN sho srl Dch phi logic Mng 1 chiu kiu BIT hoc Integer Cng kiu BOOLEAN sho sla Dch tri s Mng 1 chiu kiu BIT hoc Integer Cng kiu hc BOOLEAN sho sra Dch phi s Mng 1 chiu kiu BIT hoc Integer Cng kiu hc BOOLEAN sho rol Dch vng trn Mng 1 chiu kiu BIT hoc Integer Cng kiu sang tri BOOLEAN sho ror Dch vng trn Mng 1 chiu kiu BIT hoc Integer Cng kiu phi BOOLEAN sho i vi dich logic th ti cc v tr b trng s c in vo cc gi tr 0 cn dch s hc th cc cc v tr trng c thay th bng bit c trng s cao nht MSB nu dch phi, v thay bng bit c trng s thp nht LSB nu dch tri. i vi dch vng th cc v tr khuyt i s c in bng cc bit dch ra ngoi gii hn ca mng. Quan st v d di y Ton t Php ton
# sho = 11000110

Kiu ca sho

345

# # # # # #

sho sho sho sho sho sho

sll srl sla sra rol ror

2 2 2 2 2 2

= = = = = =

00011000 00110001 00011000 11110001 00011011 10110001

Bc 1: Vit cho khi dch logic phi. Hng dn: (file m t c tn shifter.vhd) S khi ca khi dch nh sau:
Shift_in

Shift_value

SHIFTER

Ton t dch c cu trc:

Shift_out = Shift_in sll shift_value;

Trong bt buc shift_in v shift_out c kiu BIT_VECTOR, cn shift_value c kiu INTEGER. Trn thc t cc u vo ny cn c khai bo dng STD_LOGIC_VECTOR tng thch vi cc khi khc do vy c cc hm chuyn i sau:
TO_BITVECTOR(shift_in) - chuyn sang kiu BIT_VECTOR; CONV_INTEGER(0 & shift_value) chuyn sang kiu INTEGER; TO_STDLOGICVECTOR(sho) chuyn ngc li STD_LOGIC_VECTOR;

Ch rng khi chuyn sang kiu INTEGER cn thm bit 0 ng trc ly ng gi tr biu din khng du ca gi tr dch. Khi buc phi khai bo th vin nh sau:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE ieee.Numeric_STD.all; USE ieee.Numeric_BIT.all;

346

Vi cc tn hiu du vo l STD_LOGIC_VECTOR ta phi khai bo cc tn hiu trung gian kiu tng thch vi lnh dch phn khai bo kin trc:
signal shi: bit_vector(31 downto 0); signal sho: bit_vector(31 downto 0); signal sa : integer;

Da trn hng dn trn vit khi dch dng ton t cho php dch phi cho chui 32-bit u vo. Bc 2: Vit khi kim tra cho khi dch bc 1. Hng dn: bi thc hnh trc chng ta quen vi cch kim tra nhanh vi 1 t hp u vo. bi ny s lm quen vi phng php kim tra nhanh cho mt s t hp gi tr u vo. lm c nh cn b xung vo phn m t kin trc ca khi kim tra on m to cc d liu u vo bng lnh wait for. V d nh sau:
create_data: process begin shift_in <= x"19107111" after 50 ns; shift_value <= "00011"; wait for 150 ns; shift_in <= x"19107000" after 50 ns; shift_value <= "00111"; wait for 170 ns; shift_in <= x"1abc7111" after 50 ns; shift_value <= "00011"; wait; end process create_data;

on m trn gn cc gi tr khc nhau cho cc u vo khc nhau, tng ng trn gin sng s quan st c s thay i ny. Bc 3: Vit m t khi dch c kin trc m khng s dng thut ton dch. Hng dn: Mt thc th c th c nhiu kin trc v cc kin trc c th c m t c lp vi nhau trong 1 m t VHDL. C th bc ny cn b xung vo file ngun to Bc 1 m t kin trc th hai bt u bng architecture (phn in m cui file)
-- SHIFTER ----------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL; USE ieee.Numeric_STD.all; USE ieee.Numeric_BIT.all; -----------------------------------------

347

entity shifter_32 is port( shift_in : in std_logic_vector(31 downto 0); shift_value: in std_logic_vector(4 downto 0); shift_out : out std_logic_vector(31 downto 0) ); end shifter_32; -- khoi dich su dung toan tu dich architecture behavioral of shifter_32 is begin ... --Mo ta kien trc 1 end behavioral; -- khoi dich su dung thuat toan dich don gian architecture rtl of shifter_32 is begin --mota kien trc 2 end rtl;

hiu v l thuyt xy dng khi dch khng s dng ton t xem mc 1.7 chng III. S khi dch th hin hnh sau
Shift_in

SH16 Shift16 Shift_value(4)

Shift_in4

SH8 Shift8 Shift_value(3)

. .
SH1 Shift1 Shift_value(0)

Shift_in3

.
Shift_in1

Shift_out

348

S thut ton khi dch n gin hin thc s trn bng VHDL ta s dng cu trc cu lnh song song WITH/SELECT. Trc ht cn khai bo trong khai bo kin trc cc tn hiu trung gian shift_in4, shift_in3,
signal signal signal signal signal shift_in4 shift_in3 shift_in2 shift_in1 shift_in0 : : : : : std_logic_vector(31 std_logic_vector(31 std_logic_vector(31 std_logic_vector(31 std_logic_vector(31 downto downto downto downto downto 0); 0); 0); 0); 0);

Sau cho mi bc dch trn ta s dng cu lnh WITH/SELECT

with shift_value(4) select shift_in4 <= x"0000" & shift_in(31 downto 16) when '1', shift_in when others;

Bc 4: Vit Kim tra ng thi cho hai kin trc ca khi dch m t bc 3. Hng dn: V trn khi dch c hai kin trc nn kim tra khi dch ta s ci t c hai kin trc ny trong khi kim tra (trong phn m t kin trc), lu rng cc u vo ca cc khi dch vi kin trc khc nhau c th dng chung nhng u ra bt buc phi khc nhau. y ta khai bo hai u ra l shift_out0, shift_out1.
sh320: component shifter_32 port map (shift_in, shift_value, shift_out0); sh321: component shifter_32 port map (shift_in, shift_value, shift_out1);

Tuy vy xc nh kin trc no s c m phng ta phi c m quy nh trc trong phn khai bo kin trc nh sau:
for sh320: shifter_32 use entity work.shifter_32(behavioral); for sh321: shifter_32 use entity work.shifter_32(rtl);

Vi quy nh trn th khi con sh320 dng kin trc behavioral cn khi sh321 dng kin trc rtl. M phng kim tra s thu c kt qu l cc kin trc khc nhau thc hin chc nng ging nhau, v d kt qu nh hnh sau:

349

3. Thanh ghi Bc 5: Vit m t cho thanh ghi N- bit c cu trc v gin sng nh sau:

Hng dn: Thanh ghi N-bit cn khai bo N l tham bin tnh generic. Tn hiu RESET y l tn hiu RESET khng ng b, cn tn hiu CLK kch hot ti sn dng. Thanh ghi vit buc phi dng cu trc IF/THEN trong khi lnh tun t (khi PROCESS).
if RESET = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then Q <= D; end if;

ngha ca lnh Q <= (others => '0'); l gn tt c cc bit ca Q gi tr bng 0. Bc 6: M phng kim tra thanh ghi, nhn xt v s thay i d liu trn thanh ghi v so snh vi cc khi t hp m t trc . Hng dn: Khc vi cc khi t hp thanh ghi l mch dy do khi kim tra cn to ng dng cho xung nhp CLK. to xung nhp CLK dng mt khi process khng c danh sch sensitive list, trong ta dng mt lnh wait for trnh cnh bo khi bin dch v vic thiu danh sch sensitive list. Tn hiu CLK s c gn bng o ca n sau mi na chu k. Ch rng con s ch thi gian y c th bt k v ch s dng cho m phng. 350

--create clock create_clock: process begin wait for 15 ns; CLK <= not CLK after 50 ns; end process create_clock;

Tn hiu RESET v d liu u vo D c to bng lnh Wait for trong mt khi khc, v d nh sau:
reset <= '0'; enable <= '1'; wait for 10 ns; reset <= '1'; D <= x923856c8; wait for 100 ns; reset <= '0'; D <= x10245608; wait for 250 ns; D <= xa23400a8; wait for 200 ns; D <= xc00456c8; wait;

Bc 7: Vit m t cho thanh ghi dch phi s hc. Hng dn: Kt hp khi dch phi s hc v thanh ghi ta c cu trc ca thanh ghi dch phi s hc nh hnh sau:
clk, reset WE D Shift_value Shift_in

SHIFTER

Shift_out MUX

REG1

Thanh ghi c th lm vic hai ch , ch th nht d liu u vo c ly t u vo D nu tn hiu WE = 1, ch th hai l ch dch, khi d liu u vo ca thanh ghi ly t khi dch khi WE = 0, u ra ca thanh ghi 351

c gn bng u vo ca khi dch. ch ny d liu s b dch lin tc mi xung nhp mt ln. vit thanh ghi dch th ta vit m t ca khi dch, ca khi MUX v thanh ghi ring sau ghp li. i vi khi dch s dng kin trc dch dng thut ton. V d gin sng sau l ca thanh ghi dch tri logic:

4. Bi tp sau thc hnh - Thit k cc khi dch khng s dng ton t vi 6 php dch khc nhau - Thit k thanh ghi dch cho cc khi dch trn - Thit k khi dch a nng c th thc hin tt c cc php dch trn. Php dch c thc hin quy nh bi tn hiu iu khin u vo.

352

Bi 4: B cng bit ni tip dng 1 FA (serial-bit adder)

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1. Mc ch Vit m t v kim tra cho khi mch dy phc tp l khi cng 8 bt dng mt duy nht 1 full_adder. Khi mch cu trc t b m, thanh ghi dch mt bit ni tip v mt full_adder. K nng chnh cn thc hin bi ny l cch thc ghp ni cc khi n gin to thnh khi mch phc tp v kim tra hot ng ca khi mch dy. Yu cu sinh vin c kin thc c s v VHDL v s dng thnh tho Modelsim. 2. Khi cng bit ni tip (Serial bit adder)
reset, clk A shifter_reg.vhd 0' reset counter.vhd WE SHIFTER_REGA cnt_reset temp= cnt=111" COUNTER CNT cnt_enable
REG

Din bitin WE Dout

Shift_enable

B shifter_reg.vhd reg_temp

RESULT

Din bitin WE
SHIFTER_REGB

Dout
shift_enable

Shift_enable

B bitCout CO

FA
S

CINCIN

Cout

X00"

full_adder.vhd CIN

MUX

bitcin mux1.vhd

REG_CIN

reg_in bitSum

Din bitin

Shift_enable
SHIFTER_REGB

Dout

SUM

WE
shifter_reg.vhd reg.vhd shifter.vhd mux.vhd

WE

S tng qut ca khi cng bit ni tip th hin trn hnh v. Php cng c thc hin bng cch s dng cc thanh ghi dch u vo y dn cc bit Ai, Bi tng ng vo mt b Full_adder v thc hin cng tng bit, kt qu t full_adder c y dn ra 1 thanh ghi lu kt qu. B cng N bit sau N xung nhp s cho ra kt qu. Bc 1: Chun b cc m ngun c sn: Trong s trn cho php s dng cc m ngun c sn bao gm: 1-Khi full_adder c m t trong tp full_adder.vhd
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity full_adder is port (A : in std_logic;

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B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic ); end full_adder; ---------------------------------------architecture dataflow of full_adder is begin S <= A xor B xor Cin; Cout <= (A and B) or (Cin and (a or b)); end dataflow; ---------------------------------------1-Khi chn knh MUX c m t trong tp mux.vhd ---------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ---------------------------------------------entity mux is port( Sel : in std_logic; Din1 : in std_logic_vector(7 downto 0); Din2 : in std_logic_vector(7 downto 0); Dout : out std_logic_vector(7 downto 0) ); end mux; ----------------------------------------------architecture rtl of mux is begin selm: process (Sel, Din1, Din2) begin if Sel = '1' then Dout <= Din1; else Dout <= Din2; end if; end process selm; end rtl; -----------------------------------------------

1-Khi shifter c m t trong tp shifter.vhd

------------------------------------------------library ieee; use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------

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entity shifter is port( bitin : in std_logic; shift_enable : in std_logic; shift_in : in std_logic_vector(7 downto 0); shift_out : out std_logic_vector(7 downto 0) ); end entity; -------------------------------------------------architecture rtl of shifter is begin shifting: process (bitin, shift_enable, shift_in) begin if shift_enable = '1' then shift_out <= bitin & shift_in(7 downto 1); end if; end process shifting; end architecture; --------------------------------------------------

Khi ny thc hin dch sang bn phi 1 bit v v tr bt trng b dch i s c lu gi tr u vo bitin 1-Khi thanh ghi c m t trong tp reg.vhd
----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity reg is port( D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0); CLK : in std_logic; RESET : in std_logic ); end reg; -----------------------------------------architecture behavioral of reg is begin reg_p: process (CLK, RESET) begin if RESET = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then Q <= D;

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end if; end process reg_p; end behavioral; ------------------------------------------

Sinh vin c th sao chp hoc to cc m ngun c sn trn vo trong mt th mc trong D:/student/name/ bt u lm vic. Bc 2: Bin dch ton b cc file to bc 1. Hng dn: V y l mt bi c nhiu m ngun nn bc ny ta s to mt file script c tn run.do phc v bin dch m phng cho c qu trnh. Ni dung file bc ny tm thi nh sau, cc bc sau ta s b xung thm cc lnh vo script ny.
quit vlib vcom vcom vcom vcom vcom -sim work counter.vhd full_adder.vhd mux.vhd reg.vhd shifter.vhd

Sau khi to xong file ny lu vo trong th mc lm vic cha m ngun v thc hin chy script cho bin dch bng lnh
do run.do

Bc 3: Vit m t khi thanh ghi dch da trn cc khi c sn. Hng dn: Thanh ghi dch ny khc vi thanh ghi dch bi th nghim trc. php dch lun dch sang bn phi 1 bit v bit trng c in gi tr t bn ngoi vo t cng bitin. Cng shift_enable l cng cho php dch hoc khng dch.
REG

bitin

REG

357

clk, reset

WE

Din

bitin

shift_enable Shift_in

SHIFTER

shifter.vhd

shift_out MUX
mux.vhd

mux_out
REG1

reg.vhd

Dout

S ca khi dch nh hnh trn, m ngun ca thanh ghi dch ni tip c lit k di y. y l mt v d v cch ghp ni cc khi con to thnh thit k ln hn. Cc bc ci t khi con lm tng t nh khi vit khi kim tra nhanh (ci t DUT). Trong trng hp ny khi ca chng ta c nhiu khi con hn. u tin trong phn khai bo kin trc khai bo cc component s s dng trong hnh v d cho khi reg:
component reg is port( D : in Q : out CLK : in RESET : in ); end component; std_logic_vector(7 downto 0); std_logic_vector(7 downto 0); std_logic; std_logic

Sau cng trong phn khai bo kin trc cn khai bo tt c cc tn hiu bn trong, tn hiu bn trong l tn hiu kt ni gia cc khi ca thit k, v d:
signal shift_out: std_logic_vector(7 downto 0); signal reg_in: std_logic_vector(7 downto 0);

Cui cng l ci t cc khi con tng ng vi cc tn hiu trn hnh, phn ny vit trc tip trong phn m t kin trc, v d: 358

sh1 : component shifter port map (bitin => bitin, shift_enable => shift_enable, shift_in => shift_in, shift_out => shift_out); mux1: component mux port map (Sel => WE, Din1 => Din, Din2 => shift_out, Dout => reg_in);

Trong v d trn sh1, mux1 l cc tn gi ca cc khi ci t v c th bt k, trnh trng vi cc tn khc dng. Bc 4: Vit m t cho b m. Hng dn: Mc ch ca b m y l m s ln dch, v c 8 bit cng nn ta s vit mt b m n 8. Cc cng ca bt m nh hnh v sau:
CNT

Clk, reset

COUNTER

Cnt_enable

Trong cng cnt_enable l cng cho php m, khi cnt_enable = 1 th b m lm vic bnh thng, khi cnt_enable = 0 th b m dng li v gi nguyn gi tr m. Cng clk chnh l cng xung m, cng reset l cng khng ng b, cng cnt l gi tr hin ti ca b m. Bn cht ca b m l mt b cng tch ly c bit vi gi tr tch ly bng 1, thng c m t nh sau:
if reset = '1' then temp_cnt <= (others =>'0'); elsif rising_edge(clk) then if counter_enable = '1' then temp_cnt <= temp_cnt + 1; end if; end if;

Bc 5: M t khi cng ni tip.

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reset, clk A shifter_reg.vhd 0'

reset counter.vhd WE SHIFTER_REGA cnt_reset temp= cnt=111" COUNTER CNT cnt_enable

REG

Din bitin WE Dout

Shift_enable

B shifter_reg.vhd reg_temp

RESULT

Din bitin WE
SHIFTER_REGB

Dout
shift_enable

Shift_enable

B bitCout CO

FA
S

CINCIN

Cout

X00"

full_adder.vhd CIN

MUX

bitcin mux1.vhd

REG_CIN

reg_in bitSum

Din bitin

Shift_enable
SHIFTER_REGB

Dout

SUM

WE
shifter_reg.vhd reg.vhd shifter.vhd mux.vhd

WE

Cc thnh phn ca khi cng y bao gm thanh ghi dch ni tip (shifter_reg.vhd), khi chn knh 1 bit (mux1.vhd), khi m (counter.vhd). khi FA (full_adder.vhd). Cc cng vo ra ca khi trn bao gm cng A, B 8-bit l cc hng t, Cin l bit nh u vo, Sum l kt qu cng , Cout l bt nh ra. Cc tn hiu ton cc l CLK v RESET, ngoi ra cng WE l tn hiu khi tch cc WE = 1 cho bit l d liu cc u vo A, B ang c np vo cc thanh ghi SHIFTER_REGA, SHIFTER_REGB thc hin cng. Tn hiu ra RESULT = 1 cho bit gi tr SUM v Cout ng. - Thanh ghi dch SHIFTER_REGA, SHIFTER_REGB: Cc thanh ghi s dch sang bn phi mt bit nu nh khng phi thi im c kt qu ra, thi im ny b m m xong 8 xung nhp do vy cc tn hiu ny c m t nh sau: Tn hiu temp bo hiu cnt m n 111
with cnt select temp <= '1' when "111", '0' when others;

Tn hiu ny c lm tr mt xung nhp bng mt mt D-flip-flop nh m t sau:

reg_p: process (CLK) begin if CLK = '1' and CLK'event then temp_reg <= temp; end if;

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end process reg_p;

Cui cng tn hiu shift_enable l o ca temp b lm tr.

shift_enable <= not temp_reg;

Tn hiu bitin ca hai thanh ghi dch SHIFTER_REGA, SHIFTER_REGB khng quan trng v gn bng hng s bt k, trn hnh ta gn bng 0. Tn hiu vo song song ca thanh ghi SHIFTER_REGA, SHIFTER_REGB ly ln lt t cc cng A, B 8 bit, cng WE ca cc thanh ghi ly t cng WE ca khi serial_bit_adder. - B m COUNTER. Tn hiu counter_enable chnh l tn hiu shift_enable cho cc thanh ghi SHIFTER_REGA, SHIFTER_REGB.
counter_enable <= shift_enable;

B m reset nu bt u np d liu thc hin php ton (WE =1 ) hoc khi c reset khng ng b ca ton khi.
cnt_reset <= WE or reset;

Khi Full_Adder

Cc tn hiu bn trong bitA, bitB chnh l cc bit thp nht ca hai thanh ghi dch SHIFTER_REGA, SHIFTER_REGB, cc bit ny c a vo khi FA.
bitA <= regA(0); bitB <= regB(0);

Trong regA, regB chnh l cc gi tr ca cc thanh ghi dch tng ng cng Dout. m t chui bit nh cn c mt khi chn knh mt bit vi cc u vo l bitCout, v Cin, tn hiu chn knh l WE, nu nh ti thi im u tin(WE = 1) th u ra reg_cin = Cin, cn ti cc thi im khc u vo bit nh chnh l gi tr u ra bit nh ln trc nn Reg_cin = bitCout. Tn hiu bitCin vo cng CIN ca khi full_adder chnh l reg_cin c lm tr mt xung nhp vad c m t nh sau:
if CLK = '1' and CLK'event then bit_Cin <= Reg_cin; end if;

Thanh ghi SHIFTER_SUM Tn hiu bitSum l u ra ca Full_Adder ng vai tr l u vo cho thanh ghi SHIFTER_SUM.

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Tn hiu RESULT bng 1 nu nh kt qu xut hin cng ra SUM v Cout kt qu chnh xc c sau 8 xung nhp cho b cng 8 bit, do d RESULT trng vi tn hiu temp_reg trnh by trn.
--tin hieu result tre nhip hon temp 1 xung nhip RESULT <= temp_reg;

Cng vo d liu song song ca thanh ghi REG_SUM khng quan trng, c th gn bng gi tr bt k 8 bit, trn hnh ta gn bng gi tr ca x00. Cng vo WE ca thanh ghi ny cng khng quan trng, ta ly lun tn hiu WE. Bc 6: Kim tra khi thit k: Hng dn: kim tra khi thit k th cch thc khng khc g vi nhng bi lm trc y. Quan trng nht l phi to c tn hiu xung clk:
--create clock create_clock: process begin wait for 2 ns; CLK <= not CLK after 50 ns; end process create_clock;

Sau l to tn hiu iu khin hp l gm reset v WE, v d nh sau

A <= x"1B"; B <= x"0c"; Cin <= '0'; reset <= '0'; WE <= '0'; wait for 150 ns; reset <= '1'; wait for 170 ns; reset <= '0'; WE <= '1'; wait for 150 ns; WE <= '0'; wait;

Kt qu m phng c dng nh sau:

362

3. Bi tp sau thc hnh - Xy dng khi cng bit ni tip cho trng hp N-bit - Xy dng khi cng bit ni tip s dng 2 Full-adder - Ti u ha thit k bng cch sa li thit k ca cc thanh ghi dch u vo v u ra ca khi cng (b nhng tn hiu khng s dng n)

363

Ph lc 3: MCH PHT TRIN NG DNG FPGA

1. Gii thiu tng quan
POWER SUPPLY
XCF04 Platform Flash LED0
P144 P145 P146 P147 P150 P151 P152 P153

EXPANSION
DIP SWITCH
P106 P107 P108 P109 P112 P113 P115 P116 P98 P99 P100 P102

ADC/DAC

SWITCH1

LED1

SD/MMC holder

P119 P120 P122 P124 P126 P127 P128 P129

P160 P161 P162 P163 P164 P165 P167 P168 P171 P172 P177 P178 P179 P180 P181 P185 P190 P192 P193 P196

P97 P96 P90 P94 P93 P84 P83 P82 P78 P89

PS/2

XILINX SPARTAN 3E XC3S500E

48MHZ
P75 P74 P68 P65 P64 P64 P62 P61

VGA

P200 P199 P202 P203

LCD1602A

KEYPAD

CAN connector

USB connector

Ethernet connector

S mch khi thit k

364

RS232

P50 P49 P48 P47 P45 P42 P41 P40

P11 P9 P8 P5 P4

P19 P18 P16 P15

P33 P31 P30 P29

P39 P36 P35

P28 P25 P24 P23

Mch th nghim hon thin Mch th nghim FPGA c xy dng v ch to bi b mn K thut xung s, Vi x l vi mc ch phc v cc i tng o to h chnh quy dn s, qun s, hc vin cao hc v phc v cng tc nghin cu khoa hc. Mch c thit k trn nn tng Xilinx Spartan 3E FPGA XCS500 PQG208. Mch in v mch nguyn l c v trn cng c Altium Designer. Phn trung tm ca mch l FPGA v FLASH ROM np cu hnh, thit k ca phn ny l ni cng m bo tt s hot ng ca FPGA. 10 ngoi vi cn li c thit k a phn m nhm to s linh ng v d kim sot trong qu trnh lm vic cng nh ph hp vi mc ch nghin cu th nghim. Cc ngoi vi khi cng c th s dng c lp giao tip vi cc khi bn ngoi 365

m khng l thuc vo FPGA. Ngoi phn ngun c ni sn, cc chn tn hiu ca ngoi vi khi mun lm vic vi FPGA phi c ni bng cp chuyn dng. 2. Cc khi giao tip c trn mch FPGA 2.1.Khi FPGA XCS500 Cc tham s chnh ca Xilinx Spartan 3E Spartan3E dng FPGA trung bnh c thit k cho nhng ng dng c va v nh vi chi ph khng ln. C tt c 5 loi Spartan 3E vi mt tch hp t 960 Slices(XC3S200) cho ti 14752 Slices (XC3S1600), nu tnh theo n v cng tng ng l 2000 cho ti 30000 cng (cng tng ng c tnh l mt cng AND hoc OR hai u vo). FPGA s dng trong mch th nghim l XC3S500 PQG208 vi s Slices l 4656 tng ng 1164 CLBs (10,476 cng tng ng) c b tr trn 46 hng v 24 ct. Cc ti nguyn khc bao gm 4 khi iu chnh/to xung nhp h thng Digital Clock Manager (DCM) c b tr 2 trn v 2 di. Cc khi nh bao gm 360K Block RAM v ti a 73K RAM phn tn. Tch hp 20 khi nhn 18x18 bt c b tr st cc Block Ram. V ti nguyn cng vo ra XC3S500 vi gi PQ208 h tr 208 chn vo ra trong c 8 cng cho xung nhp h thng, ti a 232 cng vo ra s dng t do, trong c 158 chn IO, s cn li l chn Input. XC3S500 c thit k trn cng ngh 90nm v cho php lm vic xung nhp ti a n 300Mhz, vi tc nh vy XC3S500 c th p ng hu ht nhng bi ton x l s c va v nh. 2.2. Mch np JTAG/PLATFORM FLASH XCF04 Mch np cho FPGA s dng Xilinx platform Flash ROM XCF04 dung lng 4Mb, c kh nng np trc tip cu hnh vo FPGA thng qua giao tip JTAG hoc np gin tip cu hnh lu tr c nh trong ROM, khi cn np li cu hnh vo FPGA ch vic n phm PROG. Chng trnh lu trong ROM c th c c/xa v ghi mi li 2.3. Khi ngun Power Supply Khi ngun l mt khi quan trng cung cp cho chip FPGA yu cu cp cc ngun in p mt chiu 3,3V, 2.5V v 1.2 V. Cho Xilinx Flash Platform XFC04 yu cu ngun 3.3V. Vi tt c cc ngoi vi cn li s dng cc mc in p ph bin l 5.0V v 3.3V. Tt c cc mc in p ny c to bi cc IC

366

ngun chuyn dng tch hp trn mch. mch hot ng ch cn cung cp in p u vo DC 5V.

2.4. Khi giao tip Keypad

Trong s s dng 5 Keypad c lp c th s dng cho nhiu mc ch khc nhau, cc phm ny c treo mc cao. Ngoi ra c hai Keypads c ni cng vi FPGA thng qua cc chn P90 v P89 s dng trc tip trong cc thit k.

2.5. Khi 8x2 Led-Diod

Khi hin th LED c thit k gm 2x8 LED n treo tr 10K trong 8LEDs c gn cng vi FPGA thng qua cc chn P153, P152, P151, P150, P147, P145, P146, P144. 8LEDs cn li m khi s dng phi kt ni bng cp ring. Tt c cc LED ny c tr 1K v c mc tch cc l 1.

2.6. Khi Switch

Khi switch c thit k gm 2x8 SWITCHS, 8 SWITCH s dng DIPSWITCH loi nh v gn cng vi cc chn FPGA qua cc chn P129, P128, P127, P126, P124, P122, P120, P119. 8 SWITCHs cn li c cu to t cc SWITCH n loi ln v u ra m, khi s dng cn ni vi cc chn FPGA bng cp ring. Tt c cc Switch ny u c treo mc cao thng qua tr 10K.

2.7. Khi giao tip 4x7-seg Digits

Cung cp giao phng php hin th n gin thng qu Led 7 thanh, khi Led ny c cu to t 4 s v hot ng theo nguyn l qut cc cc ANOD chung. Cc chn qut ANOD s c khuych i bng pnp transitor A1015 m bo sng ca cc LED. Tc qut cho 4 LED cn duy tr tn s c 200Hz c c hin th tt nht. 2.8. Khi giao tip RS232 Khi giao tip RS232 thc hin truyn thng ni tip gia FPGA v cc thit b s khc. Trong mch ny s dng IC MAX232ACSE. S nguyn l th hin hnh di y. MAX232 c to ra hai kt ni truyn thng ni tip c lp gia FPGA v cc thit b khc trn my tnh trong 1 cng COM 367

(DTE) v mt cng khc di dng kt ni t do. Tc Baud h tr t 110 n 11520 bit/Sec. FPGA giao tip vi khi ny thng qua 2 cp tn hiu Rx, Tx c t do.

2.9. Khi giao tip USB RS232

Khi giao tip USB c thit k da trn IC FT232RL ca FTDI. IC ny chuyn i giao tip USB sang cc giao tip RS232 / RS422 / RS485 vi tc truyn t 300-3M Baud. Vi thit k ny giao tip USB thc s c thc hin nh giao tip UART, ton b giao thc USB2.0 c thc thi bng FP232RL. IC ny cong c tch hp sn dao ng bn trong v hot ng ch vi mt in p ngun +5V. Khi c kt ni cng USB, ngun 5V t thit b bn ngoi nh my tnh c th dng cp cho mch FPGA hot ng bnh thng. Giao tip vi khi ny ging nh giao tip vi khi RS232 trnh by trn gm c 2 tn hiu Rx, Tx. Ti liu chi tit v FT232RL v Driver cho my tnh c thm xem trn trang Wed ca nh sn xut http://www.ftdichip.com/Products/ICs/FT232R.htm

2.10. Khi giao tip PS/2.

FPGA c th thc hin iu khin cc ngoi vi c bn nh mn hnh, bn phm chut thng qua cc giao thc chun PS/2. Mch c th nghim vi tc giao tip t 20-30 Khz vi bn phm chun cho kt qu n nh. ng truyn PS/2 c giao thc ging ng truyn ni tip nhng cc thit b s dng chung xung nhp ng b. 2 tn hiu ti thiu giao tip l CLK vi tn s t 10-20Khz, v tn hiu Data cho ng d liu. Trn mch FPGA cc tn hiu ny cng di dng t do v ch kt ni khi cn thit. Trn mch thit k hai cng PS/2 cho giao tip ng thi c MOUSE v KEYBOARD.

2.11. Khi giao tip VGA.

i vi khi VGA, c thit k c th giao tip vi ti a ch 12 bit mu. Cc chn tn hiu RGB c treo tr vi gi tr 500, 1K, 2K v 4K. Mch c kim tra vi ch phn gii 600x800 v tc lm ti 60Hz cho kt qu n nh (tng ng xung nhp h thng ca mch iu khin 50Mhz). Mch iu khin VGA l mt trong nhng mch i hi tc cao v vy khi thit k nn s dng DCM m bo chnh xc cho xung CLK. 368

Tn hiu giao tip gm HS, VS tng ng l cc xung qut ngang v dc. 12 tn hiu R[3:0], G[3:0] v B[3:0] a 12 bit mu hin th ln mn hnh.

2.12. Khi giao tip LCD1602A.

LCD1602A l dng LCD n sc cho php hin th cc k t chun ASCCI vi mt gio thc c th d thc hin trn cc khi phn cng bng FPGA. Tn hiu giao tip vi LCD gm 8 chn tn hiu LCD_Data[7:0], 3 chn iu khin LCD_RS, LCD_EN, v LCD_RW. Chi tip v giao thc vi LCD1602A xem trong v d chng 4 v ti liu hng dn. LCD c thit k c th thc hin giao tip ch 4 bit cng nh 8 bit. Vi tc c 100-300Khz cc chn giao tip ny cng khng gn cng vi cc chn FPGA, ngha l LCD ngoi lm vic vi FPGA c th s dng c lp vi cc mc ch khc. LCD c cp ngun 5V, c chit p iu chnh tng phn ca mn hnh. 2.13. Khi giao tip ADC/DAC Giao tip DAC/ADC c thc hin trn cng 1 IC l PCF8591, IC ny c kh nng lm vic nh mt khi DAC hay mt khi ADC 8-8bit ph thuc vo cch thc cu hnh cho IC. Thng tin trao i gia PCF8951 v FPGA thng qua giao tip chun I2C, tc ti a h tr cho l 100Khz. PCF8591 hot ng vi mt ngun cp duy nht vi mc in p u vo cho php dao ng t 2.5V n 6V. Trn mch IC ny c cp ngun 3.3V, ngun tham chiu thay i nh mt bin tr 10K t 0-3.3V. PCF8591 c 4 u vo tng t AIN0, AIN1, AIN2, AIN3 vi a ch c lp trnh, mt u ra tng t AOUT. IC hot ng ch Slave c th c a ch ha bi 3-bit a ch cc chn A0, A1, A2, 8 IC PCF8591 c th kt ni trn cng mt knh truyn I2C m khng cn thm phn cng h tr. V trn mch ch c 1 IC duy nht nn c th ngm nh a ch lun l 000. PCF8591 c th s dng xung nhp (cho giao tip I2C) t u vo SCL hoc xung nhp t mt dao ng ngoi. n gin thit k nn dng xung nhp t chn SCL khi chn EXT cn phi ni t. Chi tit v giao tip I2C cng nh c th v cch thc cu hnh iu khin cho PCF8591 c th xem trong Datasheet ca IC.

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2.14. Khi giao tip Ethernet Khi giao tip Ethernet c thit k trn nn tng IC ENC28J60 ca Microchip thc hin chc nng giao tip lp Media Access Control(MAC) v Physical Layer(PHY) trong lp PHY thc hin bin i xung tn hiu tng t t ng truyn thnh tn hiu s, cn lp MAC thc hin ng gi cc tn hiu ny theo chun IEEE 802.3 truyn tip cho cc thit b x l lp trn. IC iu khin lm vic vi ENC28J60 thng qua giao tip chun SPI (Serial Peripheral Interface) vi tc ti a ln ti 20Mhz. Cc tham s, ch lm vic c lu tr trong cc thanh ghi iu khin cho php c v ghi t bn ngoi. B nh m ca ENC28J60 c thit k l mt khi RAM hai cng (Dual-port RAM) vi kh nng lu tr tm thi cc gi d liu gi i, nhn v cng nh h tr thao tc DMA. Gi d liu lp MAC hon ton tng thch chun. Cc chn tn hiu giao tip SPI trn mch l CLK0, INT, S0, S1, SCK, CS, RESET. Chi tit v cu trc v cch thc lm vic ca ENC28J60 xem trong Datasheet ca IC v trn trang thng tin ca Microchip http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en02 2889.

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Ph lc 4: THC HNH THIT K MCH S TRN FPGA

371

Bi 1: Hng dn thc hnh FPGA bng Xilin ISE v Kit SPARTAN 3E

1. Mc ch Lm quen vi chng trnh XilinxISE, hc cch np cu hnh cho FPGA thng qua mt v d n gin. Thc hnh np cu hnh trn mch Spartan 3E. Phn di y hng dn s dng chng trnh bng mt v d ht sc n gin l vit khi iu khin cc 8-led c sn trn mch FPGA bng cc 8Switch tng ng. 2. Hng dn thc hnh Bc1: To Project Sau khi khi ng phn mm Xilinx ISE ( y dng phin bn 12.4), chn File -> New Project. t tn project l sp3_led (tn c th t ty ). ng thi, chn mc Top-level source type l HDL thit k bng ngn ng m t phn cng.

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Tip theo, chn NEXT sang ca s thit lp cc thuc tnh cho project, y ta phi chn ng tn, gi (package), v tc cho FPGA m chng ta mun np, nhng thng tin ny ghi trn mt trn ca chip FPGA. C th i vi Kit ca chng ta s chn Spartan 3E, gi PQ208 v Speed bng -5. Ngm nh th chng trnh dng m phng kim tra s l Modelsim SE. i vi Prefer Language ta chn l VHDL

Sau khi n Next s xut hin hp thoi Project Summary. Chn Finish ISE to ra mt project mi vi cc thuc tnh nh trn v.

373

Hnh 3.50. Project sumary Sau khi to Project thnh cng, chng trnh chuyn sang ch lm vic vi Project, C 4 ca s chnh bao gm - Design: Cha s cu trc ca cc khi thit k trong project bao gm m ngun, cc file constraint nu c v cc file khc. - Process: Ni thc hin cc thao tc ca quy trnh thit k FPGA. - View/Editor l ca s lm vic chnh, ni c th chnh sa file ngun, xem thng tin tng hp..vvv - Command line (Console): L ca s h tr dng lnh trc tip (ging ca s TCL script trong ModelSim) T ca s chng trnh ta nhp chut p vo file sp3_led.vhd thuc ca s Design (pha gc tri trn) bt u tin hnh son tho m ngun.

374

ISE Project Windows Bc 2: Chun b m ngun To mt file m ngun c tn Board_demo1.vhd vi ni dung di y. C th to m ngun c lp bn ngoi (bng Notepad++) nh lm nhng phn trc hoc c th to trc tip trong ISE bng cch n chut phi vo ca s Design v chn New Source v lm theo hng dn.
--------------------------------------------------- Company: BMKTVXL -- Engineer: Trinh Quang Kien -- Module Name: board_demo1 - Behavioral -------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity board_demo2 is Port ( sw0 : in STD_LOGIC_VECTOR (7 downto 0); led0 : out STD_LOGIC_VECTOR (7 downto 0); ); end board_demo2; architecture Behavioral of board_demo2 is

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------------------------------------------------begin led0 <= not sw0; end Behavioral;

Bc 3: B xung m ngun vo Project B xung file m ngun vo trong Project nu to file c lp bng Notepad++. (n chut phi vo ca s Design chn Add Source v lm theo hng dn, ch nn m ngun trong th mc cng vi Project d qun l. Nu file to trc tip trong ISE th s t ng c b xung vo trong Project.

Bc 4: M phng kim tra chc nng thit k. m phng thit k ca s Design chn Behavioral Simulation sau chn khi cn kim tra v d trong trng hp ny chng ta ch c duy nht khi thit k board_demo1. Kch p chut vo biu tng Simulate Behavioral Model ca s Process chng trnh s gi Modelsim chy m phng khi tng ng. 376

Ngi s dng c th lm theo cch truyn thng l m phng bng Modelsim m khng nht thit phi gi t Xilinx ISE. n gin v thng nht t by gi v sau cc ng tc kim tra ta u lm theo phng php truyn thng l chy ring Modelsim m khng cn gi t ISE. Ngoi m phng bng ModelSim c th s dng trnh m phng tch hp Isim ca Xilinx, cch s dng trnh m phng ny ngi dng c th t tm hiu thm. Bc 5: Kim tra c php (Bin dch m ngun VHDL) Ti ca s Process, n chut m rng qu trnh Synthesis XST v chn Check Syntax. Chng trnh kch hot khi kim tra c php m thc cht l thc hin bin dch m VHDL bng lnh Vcom, thng thng nu chng ta lm m phng kim tra chc nng bc th bc ny khng th pht sinh li. Kt qu thng bo ca s Command line

377

Bc 6: Tng hp thit k (Synthesis) Click p chut vo Synthesis XST kch hot trnh tng hp thit k XST (Xilinx Synthesis Technology). Kt qu ca qu trnh tng hp thng bo ca s Command Line.

378

Bc 7: c kt qu tng hp. Ti ca s lm vic chnh (View/Editor) chn Tab Design Summary sau chn Symmary, Click chut vo Synthesis Report hin th file text cha thng tin kt qu tng hp.

Thit k ca chng ta c kt qu tng hp kh n gin, ni dung thu c c dng sau:

====================================================== * Final Report * ====================================================== Final Results RTL Top Level Output File Name : board_demo2.ngr Top Level Output File Name : board_demo2 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Design Statistics # IOs Cell Usage : # IO Buffers # IBUF # OBUF : 16 : 16 : 8 : 8

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===================================================== Device utilization summary: --------------------------Selected Device : 3s500epq208-5 Number of Slices: 0 out of 4656 0% Number of IOs: 16 Number of bonded IOBs: 16 out of 158 10% ===================================================== TIMING REPORT Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 4.632ns Timing Detail: -------------All values displayed in nanoseconds (ns)

Bc 8: Kt xut s cng ngh, v s RTL (khng bt buc) S cng ngh v s RTL c th thu c bng cch chn tng ng View Technology Schematic v View RTL Schematic. Sau chn tt c hoc mt phn Top Level Port b xung vo s , chn Create Schematic. Mt s c s c to ra, quan st cc i tng khc c th click chut vo cc i tng hoc kt ni trn m rng hoc chi tit ha s . S cng ngh thu c nh hnh sau, lm tng t nh vy thu c s RTL.

380

Bc 9: Kim tra thit k sau tng hp (khng bt buc) Kim tra thit k sau tng hp l thc hin m phng file netlist sinh ra sau qu trnh tng hp. y cng l mt m t VHDL nhng cp cng v i hi chng trnh m phng phi h tr th vin UNISIM ca Xilinx.

i vi ModelSim chun khng tch hp th vin ny, tch hp cc th vin ca Xilinx ni chung chy trnh n Compxlib c th tm thy trong th 381

mc /bin/nt ni ci chng trnh Xilinx ISE (thng thng l C:\Xilinx\12.4\ISE_DS\ISE\bin\nt). Chn cc tham s cn thit, y ta chn ModelSim v kim tra li v tr ci t Modelsim trn my (thng l C:\Modeltech_6.x\win32). Chn Next

ca s ny chn Both VHDL and Verilog nu ta mun ci t th vin h tr cho c hai loi ngn ng thit k. Sau chn Next. Ca s tip theo cho php la chn cc th vin IC FPGA v CPLD s c tch hp sang trnh m phng, ta chn mt s cc FPGA in hnh nh hnh sau

382

Ca s tip cho php la chn cc dng th vin s c tch hp sang trnh m phng, ta chn All Library v Next, qu trnh bin dch s c bt u v thng thng mt t 10-30 pht thc hin xong, ph thuc cu hnh my v s lng th vin c chn.

383

Nu s dng Isim m phng th khng phi thc hin cc bc nh trn v lu rng cc bc trn ch phi thc hin mt ln duy nht. to ra file netlist phc v cho vic kim tra sau m phng click vo Generate Post-synthesis simulation model nh hnh sau.

Nu qu trnh to file thnh cng s c thng bo tng ng Process "Generate Post-Synthesis Simulation Model" completed successfully ca s Command line. Sau m th mc ni cha cc file ca project ta s thy xut hin th mc c tn netgen/synthesis c cha file m t VHDL c tn sp3_led_synthesis.vhd.

384

Nu Modelsim h tr thit k trn th vin UNISIM th c th tin hnh m phng kim tra bnh thng file ngun ny. Bc m phng ny nhm khng nh chc nng ca mch khng b thay i sau khi tng hp. Ngi s dng cng c th copy file netlist trn v tin hnh m phng c lp khng ph thuc vo ISE. Bc 10. Gn chn vo ra sau tng hp Bc ny lm nu nh chng c Kit kim tra, trong trng hp khng c Kit th khng c th b qua bc ny, chng trnh s t ng gn cc chn vo ra ca thit k cho cc IO_pad bt k ca FPGA. Chng trnh thc hin gn chn l PlanAhead, khi ng ta chn lnh IO planing (PlanAhead) post synthesis trong ca s Process mc User Constraint. V chn Yes to file UCF vi tn gi ngm nh l Board_demo1.ucf

385

Khi c ca s PlanAhead thc hin gn a ch cho tng chn tng ng ca thit k, v d nh hnh di y ta gn chn P100 cho u ra LED2 nh trn hnh( ca s IO port chn cng LED2 sau khi in chn vo site trn ca s IO Properties chn Apply) trn mch tng ng vi cc v tr n led trn mch FPGA. Tng t nh vy ta gn cc chn cn li nh sau:
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "led0[0]" LOC = P160; "led0[1]" LOC = P161; "led0[2]" LOC = P162; "led0[3]" LOC = P163; "led0[4]" LOC = P164; "led0[5]" LOC = P165; "led0[6]" LOC = P167; "led0[7]" LOC = P168; "sw0[0]" LOC = P171; "sw0[1]" LOC = P172; "sw0[2]" LOC = P177; "sw0[3]" LOC = P178; "sw0[4]" LOC = P179; "sw0[5]" LOC = P180; "sw0[6]" LOC = P181; "sw0[7]" LOC = P185;

386

Sau khi hon tt vic gn chn Save lu li thng tin gn chn v ng PlanAhead, quay tr li vi chng trnh ISE. Thng tin gn chn c lu trong mt file text c tn l board_demo1.ucf. Khi m file ny bng trnh son tho s thy ni dung ging nh trn. Mt cch khc n gin hn gn chn l ta to mt file UCF c tn trng vi tn khi thit k chnh v son tho vi ni dung nh vy. Bc 11: Hin thc ha thit k Bc 11.1 Translate thc hin Translate, chn lnh Translate, v nu cn to file netlist sau Translate bng lnh tng ng Generate Post-translate simulation model nh hnh di y:

387

Sau khi to file netlist thnh cng cng s c thng bo tng ng ca s dng lnh: Process "Generate Post-Translate Simulation Model" completed successfully. Nu ta m li th mc netgen s thy xut hin thm th mc con translate, file VHDL tng ng board_demo2_translate.vhdl netlist to ra sau bc ny, netlist ny vit trn th vin c lp SIMPRIM. Ta cng c th tin hnh m phng kim tra thit k sau translate ging bc m phng kim tra sau Tng hp trnh by trn. Bc 11.2 Mapping thc hin qu trnh Mapping chn lnh Map trong ca s Process, qu trnh s c thc hin t ng. bc ny chng ta bt u c th kim tra cc tham s v mt thi gian i vi thit k, thc hin bc ny (ngm nh khi Mapping bc ny khng thc hin) chn Analyze Post-map Static Timing nh hnh di y

388

Kt qu s c hin ra mt file text tng ng bn ca s VIEW/EDITOR, i vi v d ny ta thu c bng thi gian tr nh sau:
Data Sheet report: ----------------All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ sw0<0> |led0<0> | 4.118| sw0<1> |led0<1> | 4.118| sw0<2> |led0<2> | 4.118| sw0<3> |led0<3> | 4.118| sw0<4> |led0<4> | 4.118| sw0<5> |led0<5> | 4.118| sw0<6> |led0<6> | 4.118| sw0<7> |led0<7> | 4.118| ---------------+---------------+---------+

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Sau khi maping cng c th to file netlist m phng kim tra chc nng bng lnh Generate Post-map simulation model tng t nh vi cc bc trn lm. Bc 11.3 Routing Bc cui cng sn sng to ra file bitstrem np vo FPGA. bc ny ta cng thc hin cc bc c bn nh i vi cc bc lit k phn Mapping. im khc bit l y kt qu Analyze v mt thi gian l chnh xc khi m cc khi thc s kt ni vi nhau.

Kt qu v mt thi gian th hin bng sau:

Data Sheet report: ----------------All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ SW1 |LED1 | 5.095| SW2 |LED2 | 4.835| SW3 |LED3 | 4.835| SW4 |LED4 | 4.835| SW5 |LED5 | 4.835| SW6 |LED6 | 4.835| SW7 |LED7 | 4.818|

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SW8 |LED8 | 4.853| ---------------+---------------+---------+

Bc 12: To cu hnh FPGA to tp bitstream cu hnh FPGA chn lnh Generate Programming File nh hnh di y

Sau qu trnh ny 1 file c tn board_demo1.bit c to ra trong th mc cha thit k. Thc hin cc bc sau np cu hnh FPGA vo mch tht. Bc 13. Np cu hnh vo FPGA. np cu hnh vo file FPGA cn phi c kit FPGA tht c kt ni vi my tnh bng dy np JTAG (thng thng qua cng LPT hoc USB). Ti ca s Process chn Configure Target Device

391

Lnh ny khi to chng trnh ISE imPACT, chng trnh s c thng bo v vic to file np cu hnh, nhn OK b qua hp thoi ny. Giao din chng trnh imPACT nh di y. Bn ca s imPACT Flow chn Boundary Scan. Click chut phi bn ca s chnh chn Initial Chain. Nu thnh cng s thy xut hin biu tng FPGA v mt khi ROM nh hnh di y.

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Chng trnh s hi c mun gn file cu hnh khng chn Yes.

Ti ca s ny chn file bitstream l sp3_led.bit, chn Open. Hp thoi tip theo chn No 393

Chng trnh tip tc hi np cu hnh vo ROM, chn Bypass, cu hnh s c np vo FPGA trc tip.

Ca s tip theo thng bo v cu hnh chn, n OK tip tc quay tr v ISE imPACT, Click chut vo biu tng Spartan FPGA v chn lnh Program trong ca s imPACT Process.

394

Chng trnh tin hnh np cu hnh vo FPGA, nu qu trnh thnh cng s c thng bo PROGRAM SUCCESSED v n DONE trn mch FPGA s sng.

395

C th kim tra trc tip trn mch thit k bng cch iu chnh cc SWITCH v quan st cc LED tng ng.

3. Bi tp v cu hi sau thc hnh 1. Thay i file ngun VHDL theo hng thay i s ph thuc ca u vo v u ra bng cc hm logic c bn AND, OR, XOR , thc hin cc bc tng hp v hin thc thit k nh trn, quan st kt qu thu c trn mch tht 2. Thit k khi chia tn s, chia tn s c sn trn mch ra tn s c 1Hz c th quan st c bng LED. 3. Thit k thanh ghi dch 8 bit dch bng xung Clock 1Hz quan st kt qu dch trn mch. 4. S dng cc khi Led v Switch thit k v kim tra b cng 4 bt trn mch.

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Bi 2: Thit k khi giao tip vi 4x7Seg -digits

1. Mc ch Minh ha cch thc xy dng mt thit k mch dy n gin trn FPGA thng qua v d iu khin khi LED 7 thanh gm 4 k t. Yu cu sinh vin phi c k nng c bn v VHDL, bit cch s dng Xilinx ISE. 2. M t hot ng ca khi thit k
RESET CLK
CLOCK DIVIDER CLK200Hz
Anod(3:0)

NBCD adder

MUX

CLOCK DIVIDER

S khi thit k c trnh by nh hnh v trn. Khi Led 7 on trn mch c tt c 4 k t s. Nguyn l c bn s dng cc led ny l s dng chn ANOD chung ca cc n bt hoc tt vi mt tn s ln lm cho mt thng khng phn bit c. Gii hn ti thiu l 25ln/1s vi 1 Led nhng thc nghim cho thy qut tc 50ln/1s vi 1Led cho kt qu hin th tt nht. Khi qut led c thit k l mt thanh ghi dch vng 4 bit, thanh ghi ny c khi to ngm nh gi tr 0111 v dch vi xung clock 200Hz ly t khi chia tn. D liu cho cc Led gm 7 gi tr a, b, c,d, e ,f g, h v p cho hin th du chm. D liu ca cc LED t 0 n 3 ny c a vo tng ng vi thi im tn hiu ANOD tng ng ca n bng 0. V vy tn hiu qut ANOD cn c s dng iu khin khi chn knh chn 1 trong 4 gi tr u vo cho cc LED. minh ha trong v d ny ta thit k mt khi cng NBCD v hai b m, tn s m ca b m nh hn nhiu so vi tn s qut v thng gi tr c 1-3Hz. V vy ta dng thm mt khi chia tn chia tn s 200Hz ra tn s 1Hz. y ta dng 2 b m NBCD ni tng, mt b m hng chc v mt b m hng n v.

Counter 0 Counter1

digit0

digit2

Seg7(7:0)

NBCD7SEG

digit3 digit1

7SEG - Driver

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Khi cng NBCD s cng gi tr cc b m v a ra kt qu l s NBCD c 2 ch s. Gi tr 2 b m v kt qu ny c a ra khi chn knh hin th trn LED. Gi tr s sau khi chn knh c m NBCD v vy ta s dng thm mt khi NBCD 7SEG gii m trc khi gi ti LED. 3. Phn thc hnh Cc thao tc c bn lm vic vi Xilinx ISE c cung cp bi s 1. Di y ch lit k ni dung ca cc khi thit k VHDL. Bc 1: Chun b m ngun thit k. Khi chia tn clk_div20.vhd:
------------------------------------------ Company : BM KTVXL -- Engineer: Trinh Quang Kien ----------------------------------------LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ----------------------------------------ENTITY clk_div20 IS GENERIC ( baudDivide : std_logic_vector(19 downto 0) := x"00000" ); PORT( clk_in : in std_logic; clk_out : inout Std_logic ); END clk_div20; ----------------------------------------ARCHITECTURE rtl OF clk_div20 IS SIGNAL cnt_div : Std_logic_vector(19 DOWNTO 0); BEGIN process (clk_in, cnt_div) begin if (clk_in = '1' and clk_in'event) then if (cnt_div = baudDivide) then cnt_div <= x"00000"; else cnt_div <= cnt_div + 1; end if; end if;

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end process; process (cnt_div, clk_out, clk_in) begin if clk_in = '1' and clk_in'event then if cnt_div = baudDivide then clk_out <= not clk_out; end if; end if; end process; END rtl; ----------------------------------------B m BCD counter10.vhd s dng tham s tnh thit lp s bit

cho gi tr m:
-------------------------------------------------- Company : BM KTVXL -- Engineer: Trinh Quang Kien ------------------------------------------------LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ------------------------------------------------ENTITY counter10 IS PORT( clk : in std_logic; reset : in std_logic; clock_enable : in std_logic; count_out : out std_logic_vector(3 DOWNTO 0)); END counter10; ------------------------------------------------ARCHITECTURE rtl OF counter10 IS SIGNAL cnt : std_logic_vector(3 DOWNTO 0); BEGIN PROCESS (clk, reset) BEGIN if reset = '1' then cnt <= (others =>'0'); elsif rising_edge(clk) then if clock_enable = '1' then if cnt = x"9" then cnt <= x"0"; else cnt <= cnt + 1; end if; end if; end if;

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END PROCESS; count_out <= cnt; END rtl; ------------------------------------------------Khi cng NBCD bcd_adder.vhd: -------------------------------------------------- Company : BM KTVXL -- Engineer: Trinh Quang Kien -- Module Name: bcd_adder - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ------------------------------------------------entity bcd_adder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); s1 : out STD_LOGIC_VECTOR (3 downto 0); s2 : out STD_LOGIC_VECTOR (3 downto 0)); end bcd_adder; architecture Behavioral of bcd_adder is signal opa, opb, sum : STD_LOGIC_VECTOR (4 downto 0); signal temp : STD_LOGIC_VECTOR (3 downto 0); begin opa <= '0' & a; opb <= '0' & b; sum <= opa + opb; temp <= sum(3 downto 0) - "1010"; process (sum, temp) begin if sum < "1010" then s2 <= sum(3 downto 0); s1 <= "0000"; else s1 <= "0001"; s2 <= temp(3 downto 0); end if; end process; end Behavioral; ------------------------------------------------Khi qut LED scan_digit.vhd -------------------------------------------------

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-- Company : BM KTVXL -- Engineer: Trinh Quang Kien -- Module Name: scan_digit - Behavioral ------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------entity scan_digit is Port ( CLK : in STD_LOGIC; ANOD : out STD_LOGIC_VECTOR(3 downto 0); RESET : in STD_LOGIC); end scan_digit; -------------------------------------------------architecture Behavioral of scan_digit is signal anod_sig : std_logic_vector(3 downto 0); begin scan: process (CLK, RESET) begin if RESET = '1' then ANOD_sig <= "1110"; elsif CLK = '1' and CLK'event then ANOD_sig <= ANOD_sig(0) & ANOD_sig(3 downto 1); end if; end process scan; ANOD <= ANOD_sig; end Behavioral; ------------------------------------------------Khi tng qut numeric_led.vhd -------------------------------------------------- Company: BM KTVXL -- Engineer: Trinh Quang Kien -- Module Name: numeric_led - Behavioral -------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------

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entity numeric_led is Port ( CLK : in STD_LOGIC; nRESET : in STD_LOGIC; ANOD : out STD_LOGIC_VECTOR (3 downto 0); SEG7 : out STD_LOGIC_VECTOR (7 downto 0) ); end numeric_led; architecture Behavioral of numeric_led is ------------------------------------------------component counter10 IS PORT( clk : in std_logic; reset : in std_logic; clock_enable : in std_logic; count_out : out std_logic_vector(3 DOWNTO 0) ); END component; ------------------------------------------------component clk_div20 IS GENERIC(baudDivide : std_logic_vector(19 downto 0) := x"00000"); PORT( clk_in : in std_logic; clk_out : inout Std_logic ); END component; ------------------------------------------------component scan_digit is Port ( CLK : in STD_LOGIC; ANOD : out STD_LOGIC_VECTOR(3 downto 0); RESET : in STD_LOGIC); end component; ------------------------------------------------component bcd_adder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); s1 : out STD_LOGIC_VECTOR (3 downto 0); s2 : out STD_LOGIC_VECTOR (3 downto 0)); end component; ------------------------------------------------component BCD_7seg is Port ( nbcd : in STD_LOGIC_VECTOR (3 downto 0);

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seg : out STD_LOGIC_VECTOR (7 downto 0)); end component; ------------------------------------------------signal reset, cnt1_enable : std_logic; signal clk0, clk1 : std_logic; signal nbcd0, nbcd1 : std_logic_vector(3 downto 0); signal nbcd2, nbcd3 : std_logic_vector(3 downto 0); signal nbcd : STD_LOGIC_VECTOR(3 downto 0); signal anod_sig, nanod : std_logic_vector(3 downto 0); ------------------------------------------------begin reset <= not nreset; cnt0: component counter10 port map (clk1, reset, '1', nbcd0); cnt1_enable <= '1' when nbcd0 = "1001" else '0'; cnt1: component counter10 port map (clk1, reset, cnt1_enable, nbcd1); bcda: component bcd_adder port map (nbcd0, nbcd1, nbcd2, nbcd3); nanod <= not anod_sig; nbcd(0) <= (nanod(0) and nbcd0(0)) or (nanod(1) and nbcd1(0)) or(nanod(2) and nbcd2(0)) or (nanod(3) and nbcd3(0)); nbcd(1) <= (nanod(0) and nbcd0(1)) or (nanod(1) and nbcd1(1)) or(nanod(2) and nbcd2(1)) or (nanod(3) and nbcd3(1)); nbcd(2) <= (nanod(0) and nbcd0(2)) or (nanod(1) and nbcd1(2)) or(nanod(2) and nbcd2(2)) or (nanod(3) and nbcd3(2)); nbcd(3) <= (nanod(0) and nbcd0(3)) or (nanod(1) and nbcd1(3)) or(nanod(2) and nbcd2(3)) or (nanod(3) and nbcd3(3)); bcd_seg0: component BCD_7seg

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port map (nbcd, SEG7); clk_div0 : component clk_div20 generic map (x"1D4C0") port map (clk, clk0); clk_div1 : component clk_div20 generic map (x"00042") port map (clk0, clk1); scan0: scan_digit port map (clk0, anod_sig, reset); ANOD <= anod_sig; end Behavioral; --------------------------------------------------

Bc 2: To Project To mt Project trn FPGA c tn l Board_demo2, b xung cc file VHDL trn vo Project, thc hin tng hp thit k, nu qu trnh tng hp thnh cng th chuyn sang bc tip theo. Vi code trn ta s c kt qu tng hp nh sau: Kt qu tng hp trn FPGA
==================================================== * Final Report * ==================================================== Device utilization summary: --------------------------Selected Device : 3s500epq208-5 Number of Slices: 45 out of 4656 0% Number of Slice Flip Flops: 54 out of 9312 0% Number of 4 input LUTs: 88 out of 9312 0% Number of IOs: 14 Number of bonded IOBs: 14 out of 158 8% Number of GCLKs: 2 out of 24 8% --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. --------------------------TIMING REPORT Clock Information: -------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -------------------+------------------------+-------+ CLK | BUFGP | 21 | clk_div0/clk_out1 | BUFG | 25 | clk_div1/clk_out | NONE(cnt0/cnt_0) | 8 |

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-------------------+------------------------+-------+ INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Timing Summary: --------------Speed Grade: -5 Minimum period: 4.259ns (Maximum Frequency: 234.811MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 12.491ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns)

Bc 3: Gn chn sau tng hp Gn cc chn cho thit k, gn ng chn cn xem ph lc I, to mt tp c ui m rng numeric_led.ucf vi ni dung nh sau:
INST "CLK_BUFGP" LOC = BUFGMUX_X2Y1; NET "ANOD[0]" LOC = P78; NET "ANOD[1]" LOC = P82; NET "ANOD[2]" LOC = P84; NET "ANOD[3]" LOC = P83; NET NET NET NET NET NET NET NET NET NET "CLK" LOC = P80; "SEG7[7]" LOC = P116; "SEG7[6]" LOC = P106; "SEG7[5]" LOC = P107; "SEG7[4]" LOC = P108; "SEG7[3]" LOC = P109; "SEG7[2]" LOC = P112; "SEG7[1]" LOC = P113; "SEG7[0]" LOC = P115; "nRESET" LOC = P90;

Bc 4: Hin thc ha thit k Hin thc ha thit k (Implementation) v c kt qu sau qu trnh ny. Kt qu v thi gian tnh sau Place & Route
Data Sheet report: ----------------All values displayed in nanoseconds (ns)

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Clock to Setup on destination clock CLK ------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock|Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ------------+---------+---------+---------+---------+ CLK | 4.641| | | | ------------+---------+---------+---------+---------+

Bc 5: Np cu hnh Np kt file cu hnh numeric_led.bit vo FPGA, Quan st kt qu thu c.

4. Bi tp v cu hi sau thc hnh 1. Trnh by nguyn l s dng Led 7 on v ch qut Led 2. Thay i tc qut v quan st kt qu thu c vi tn s qut 100Hz 3. Sa thit k c th dng Switch iu chnh tc qut led 4. Thay th khi cng NBCD bng khi nhn NBCD trong thit k trn. Np v quan st kt qu.

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Ph lc 5: CC BNG M THNG DNG

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1. M ASCII iu khin H 2 H 10 H 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E Vit tt NUL SOH STX ETX EOT ENQ Biu din Truy nhp Tn/ in c bn phm ting Anh ^@ ^A ^B ^C ^D ^E ^F ^G ^H ^I ^J ^K ^L ^M ^N Null character Start of Header Start of Text End of Text End of Transmission Enquiry Acknowledgement Bell Backspace Horizontal Tab New Line Vertical Tab Form feed Carriage return Shift Out Chung Xo ngc Tab ngang Xung dng Tab dc ngha Tn/ ngha ting Vit K t rng Bt Header u

000 0000 0 000 0001 1 000 0010 2 000 0011 3 000 0100 4 000 0101 5 000 0110 6 000 0111 7 000 1000 8 000 1001 9 000 1010 10 000 1011 11 000 1100 12 000 1101 13 000 1110 14

Bt u vn bn Kt thc vn bn K t truyn Truy vn thc

ACK BEL BS HT LF VT FF CR SO

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000 1111 15 001 0000 16 001 0001 17 001 0010 18 001 0011 19 001 0100 20 001 0101 21 001 0110 22 001 0111 23 001 1000 24 001 1001 25 001 1010 26 001 1011 27 001 1100 28 001 1101 29 001 1110 30 001 1111 31

0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

SI DLE DC1 DC2 DC3 DC4

^O ^P ^Q ^R ^S ^T ^U ^V ^W ^X ^Y ^Z

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NAK SYN ETB

CAN EM SUB ESC FS GS RS US DEL

^[ hay ESC Escape ^\ ^] ^^ ^_ File Separator Group Separator Record Separator Unit Separator

111 1111 127 7F

DEL hay Delete Backspace 409

2. M ASCII hin th H 2 H 10 H 16 ho (Nh phn) (Thp phn) (Thp lc phn) (Hin th ra c) 010 0000 32 010 0001 33 010 0010 34 010 0011 35 010 0100 36 010 0101 37 010 0110 38 010 0111 39 010 1000 40 010 1001 41 010 1010 42 010 1011 43 010 1100 44 010 1101 45 010 1110 46 010 1111 47 011 0000 48 011 0001 49 011 0010 50 011 0011 51 011 0100 52 011 0101 53 011 0110 54 011 0111 55 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 Khong trng () ! " # $ % & ' ( ) * + , . / 0 1 2 3 4 5 6 7 410

011 1000 56 011 1001 57 011 1010 58 011 1011 59 011 1100 60 011 1101 61 011 1110 62 011 1111 63 100 0000 64 100 0001 65 100 0010 66 100 0011 67 100 0100 68 100 0101 69 100 0110 70 100 0111 71 100 1000 72 100 1001 73 100 1010 74 100 1011 75 100 1100 76 100 1101 77 100 1110 78 100 1111 79 101 0000 80 101 0001 81 101 0010 82

38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

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101 0011 83 101 0100 84 101 0101 85 101 0110 86 101 0111 87 101 1000 88 101 1001 89 101 1010 90 101 1011 91 101 1100 92 101 1101 93 101 1110 94 101 1111 95 110 0000 96 110 0001 97 110 0010 98 110 0011 99 110 0100 100 110 0101 101 110 0110 102 110 0111 103 110 1000 104 110 1001 105 110 1010 106 110 1011 107 110 1100 108 110 1101 109

53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D

S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m 412

110 1110 110 110 1111 111 111 0000 112 111 0001 113 111 0010 114 111 0011 115 111 0100 116 111 0101 117 111 0110 118 111 0111 119 111 1000 120 111 1001 121 111 1010 122 111 1011 123 111 1100 124 111 1101 125 111 1110 126

6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E

n o p q r s t u v w x y z { | } ~

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3. Bng m k t cho LCD 1602A

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TI LIU THAM KHO

1- L Xun Bng - K thut s (Tp 1) - NXB Khoa hc k thut Nm 2008 2- Xun Tin - K thut Vi x l v lp trnh Assembly NXB Khoa hc k thut Nm 2002 3- Nguyn Thy Vn - Thit k logic mch s - NXB Khoa hc k thut - Nm 2005 4- Nguyn Linh Giang - Thit k mch bng my tnh NXB Khoa hc k thut - Nm 2005 5- IEEE VHDL Standard reference 2002 Nm 2002. 6- Douglas L Perry - VHDL Programming by Example 4th Edition - 2002 7- S. S. Limaye Digital Design with VHDL 2002 8- Enoch O. Hwang - Microprocessor Design Principles and Practices with VHDL - 2004 9- Mark Balch - Complete digital design - 2003 10- Maxfield, Brawn - The Definitive Guide to How Computers Do Math - Wiley Publisher - 2005 11- Behrooz Parhami - Computer ArithmeticAlgorithms and Hardware Designs Oxford University Press - 2000 12- Mi Lu - Arithmetic and Logic in Computer Systems John Wiley & Sons Inc. Publication - 2004 13- Milos D. Ercegovac and Tomas Lang - Digital Arithmetic - San Francisco Morgan Kaufmann Publishers - 2004 14- IEEE Standard for Binary Floating-Point Arithmetic. ANSI/IEEE Standard No. 754. American National Standards Institute Washington, DC - 1985. 15- Wakerly J.F - Digital design principles and practices - 1999 16- Wai-Kai Chen - The VLSI Handbook, 2nd Edition - University of Illinois 2007 17- Naveed A. Sherwani - Algorithms for VLSI Physical Design Automation, 3rd Edition - Kluwer Academic Publishers - 2002 18- David A. Paterson, John L. Hennessy - Computer Organization and Design,Third Edition - 2005. 19- Uwe Meyer-Baese -Digital Signal Processing with FPGA Springer - 2007 20- Xilinx - Spartan-3 Generation FPGA User Guide (ug331.pdf) 21- Xilinx - Spartan-3E FPGA Family Datasheet (ds312.pdf) 415

22- MIPS Technology - MIPS Instruction Set Reference Vol I - 2003 23- Xilinx - Spartan 3A/3AN Starter Kit User Guide (ug334.pdf) 24- 16COM / 40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (ks0066u.pdf) 25- http://www.csee.umbc.edu/portal/help/VHDL/ 26- http://www.model.com 27- http://www.doulos.com/knowhow/vhdl_designers_guide/ 28- http://www.synopsys.com 29- http://www.xilinx.com 30- http://vlsiip.com/tutorial/ 31- http://www.opencores.org/ 32- http://www.asic-world.com/ 33- http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html 34- http://opencores.org 35- http://en.wikipedia.org/wiki/CORDIC 36- http://en.wikipedia.org/wiki/Advanced_Encryption_Standard 37- http://en.wikipedia.org/wiki/Data_Encryption_Standard 38- http://en.wikipedia.org/wiki/RSA

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