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Fachhochschule Frankfurt am Main

University of Applied Sciences


Faculty of Computer Science and Engineering
Electronics
Academic Year 2011/2012
Prof. Dr.-Ing. G. Zimmer
Contents
1 Semiconductor Basics 2
1.1 Band theory of solids . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Intrinsic conductivity . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Diffusion currents in semiconductors . . . . . . . . . . . . . . . . 10
2 Semiconductor diode and applications 12
2.1 The pn-junction . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 pn-junction with zero bias . . . . . . . . . . . . . . . . . 12
2.1.2 pn-junction with bias . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Small-signal model of a pn-junction . . . . . . . . . . . . 21
2.1.4 Spice model of a semiconductor diode . . . . . . . . . . . 24
2.1.5 Different types of semiconductor diodes . . . . . . . . . . 26
2.2 Diode applications . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.1 Diode as rectier . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 Voltage multiplier . . . . . . . . . . . . . . . . . . . . . . 34
2.2.3 Zener diode as voltage regulator . . . . . . . . . . . . . . 36
3 The bipolar junction transistor and applications 40
3.1 The bipolar junction transistor . . . . . . . . . . . . . . . . . . . 40
3.1.1 Structure and operation principles of a npn BJT . . . . . . 40
3.1.2 Static input and output characteristics of a BJT . . . . . . 43
3.1.3 Simple small signal BJT model . . . . . . . . . . . . . . 46
3.1.4 Advanced small signal BJT model . . . . . . . . . . . . . 49
3.1.5 SPICE model of a BJT . . . . . . . . . . . . . . . . . . . 49
3.2 Small signal amplier . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.1 BJT biasing . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.2 Common-emitter amplier . . . . . . . . . . . . . . . . . 54
3.2.3 Common-collector amplier . . . . . . . . . . . . . . . . 60
3.3 Integrated circuit techniques . . . . . . . . . . . . . . . . . . . . 64
3.3.1 The differential amplier . . . . . . . . . . . . . . . . . . 64
I
3.3.2 Current Sources . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.3 Active Load . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.4 Level-Shifting Circuits . . . . . . . . . . . . . . . . . . . 71
3.3.5 Complementary Output Stage . . . . . . . . . . . . . . . 73
4 Field-Effect Transistors and their Applications 74
4.1 Junction Field-Effect Transistor . . . . . . . . . . . . . . . . . . 74
4.1.1 Cross-Section and Static IU-Characteristic of a JFET . . . 74
4.1.2 Small Signal Equivalent Circuit of a JFET . . . . . . . . . 78
4.1.3 SPICE Model of a JFET . . . . . . . . . . . . . . . . . . 80
4.1.4 Common-Source small Signal Amplier with a JFET . . . 81
4.2 Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) . 86
4.2.1 N-Channel MOSFET . . . . . . . . . . . . . . . . . . . . 86
4.2.2 P-Channel MOSFET . . . . . . . . . . . . . . . . . . . . 87
4.2.3 Static Characteristics of a n-Channel Enhancement MOS-
FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.2.4 Small Signal Equivalent Circuit of a n-Channel MOSFET 90
4.2.5 SPICE Model of a MOSFET . . . . . . . . . . . . . . . . 91
4.2.6 Common-Source Small Signal Amplier with a n-Channel
MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5 Operational Ampliers and their Applications 95
5.1 Basic Linear Model of an Operational Amplier . . . . . . . . . . 95
5.2 Basic Linear Op-Amp Circuits . . . . . . . . . . . . . . . . . . . 97
5.2.1 Inverting Amplier . . . . . . . . . . . . . . . . . . . . . 97
5.2.2 Inverting summing amplier . . . . . . . . . . . . . . . . 98
5.2.3 Non-Inverting Amplier . . . . . . . . . . . . . . . . . . 99
5.2.4 Inverting Integrator . . . . . . . . . . . . . . . . . . . . . 100
5.2.5 Inverting Differentiator . . . . . . . . . . . . . . . . . . . 102
5.2.6 First-Order Low-Pass Filter . . . . . . . . . . . . . . . . 104
5.2.7 Second-Order Low-Pass Filter . . . . . . . . . . . . . . . 105
5.3 Basic Non-Linear Op-Amp Circuits . . . . . . . . . . . . . . . . 109
5.3.1 Op-Amp as Comparator . . . . . . . . . . . . . . . . . . 109
5.3.2 Schmitt Trigger Realised with an Op-Amp . . . . . . . . 110
5.4 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . 113
5.4.1 Op-Amp Summer as DAC . . . . . . . . . . . . . . . . . 114
5.4.2 DAC with R-2R-Ladder Network . . . . . . . . . . . . . 115
5.5 Analog-to-Digital Converter (DAC) . . . . . . . . . . . . . . . . 118
5.5.1 Quantization Error . . . . . . . . . . . . . . . . . . . . . 119
5.5.2 ADC Realizations . . . . . . . . . . . . . . . . . . . . . 121
1
Chapter 1
Semiconductor Basics
Important elements of electric communications systems are devices capable of
amplifying the weak received electrical signals making further signal process-
ing possible. Up to the sixties in most purchasable receivers vacuum tubes were
used for this purpose. In most pratical applications vacuum tubes were replaced
by transistors after the bipolar transistor was invented by Bardeen and Brattain in
1948 and the theoretical prediction of the planar bipolar transistor by Schockley in
1949. Compared to vacuum tubes transistors have an almost innite lifetime and
it is possible to combine a large amount of transistors to form integrated electronic
circuit with a very high functionality. To understand the operation principles of
semiconductor devices, in the rst section their physical basics will be summa-
rized, while in the following sections the devices and their equivalent circuits are
discussed. Today the most important semiconducting material is silicon (Si). In
contrast to metal the conductivity of a semiductor is quite low but raises with in-
creasing temperature. To understand this strange physical behaviour we will rst
discuss the atomic structure of a semiconductor and we will have a look on the
band theory of solids.
1.1 Band theory of solids
In the framework of Maxwells theory the inuence of bodies is described by
scalare values like the conductivity , the permittivity and the permeability .
But they are not subjects of the theory itself. To explain their physical base solid
states physics was introduced, which has its own base in atom physics.
Since the beginning of the nineteenth century most physicists agree that matter
is composed out of atoms, introduced by the greek philosopher Demokrit. Ruther-
ford, an English physicist showed with experiments that an atom consists of a very
small positive nucleus (diameter 10
13
to 10
12
cm) carrying positive charges
2
surrounded by the same amount of negative charges, called electrons, so that the
atom itself is neutral. In this classical picture electrons circle around the positive
nucleus like the planets circle around the sun.
According to Maxwells theory the classical picture of an atom cannot be right,
since an electron moving around the nucleus of an atom would losse its energy by
emitting an electromagnetic wave, thus losing its energy and dropping into the
nucleus. It was Niels Bohr, a Danish physicist, who postulated that an atom does
not behave like a classical object, being able to exchange arbitrary amounts of
electromagnetic energy with its environment, but only in mulitples of an energy
unit W, already introduced by the German physicist Max Planck, to describe the
black-body radiation
W = h f (1.1)
In equation 1.1 h = 6.62410
34
Ws
2
stands for Plancks action quatum or Plancks
constant while f describes the frequency of the radiated electromagnetic wave.
According to Niels Bohr an electron bound to the nucleus of an atom can only
occupy certain levels of total energy, as shown in Fig. 1.1a. If an electron does

W W
x
W
1
W
2
W
3
a)
b)
Figure 1.1: Energy levels of an atom and electronic band structure of a crystal
lattice
not occupy its lowest energy level, it can drop from the energy level W
j
to the
lower energy level W
i
by emitting an electromagnetic wave of frequency
f =
1
h
(W
j
W
i
)
One says the electron changed its quantumstate. If we put a large amount of atoms
together we can in principle form a crystal. Due to the Pauli exclusion principle,
different electrons may not exist in the same quamtum state. That is the reason
why in a crystal the single energy levels of an atomwill split up into closely spaced
energy levels forming a so-called electronic band structure as shown in Fig. 1.1b.
In principle all energy levels within a band may be occupied by electrons, while
no electrons may exist at energy levels between the bands. If we cool down a
3
crystal to an absolute temperature of T 0K, all atoms of the crystal will exist
at their ground states and all energy levels within the electronic band structure
will be occupied up to a certain level. This level is called Fermi level W
F
. If
the temperature is increased, energy levels above the Fermi level may also be
occupied by electrons. The propability p(W) that a certain energy level W is
occupied by an electron is given by the so called Fermi-Dirac distribution [].
p(W) =
1
exp(
W W
F
k
B
T
) +1
(1.2)
with k
B
= 1, 3810
23
J/K (Boltzmanns constant)
Considering the band with the highest energy one can distinguish between two
different cases:
1. Electrons do not occupy all energy levels within the band. As a result there
will exist free energy states slightly above the states already occupied. If an
electric eld is applied, electrons are being accelerated by the eld, enhanc-
ing their kinetic energy and thus reaching higher energy levels. Electrons
will move thru the crystal due to the electric eld, resulting in an electric
current. This scenario describes the situation within metals as shown in Fig.
1.2a.
2. At the absolute temperature T = 0K all lower energy bands are totally oc-
cupied. The occupied band with the highest energy level is called valence
band. Normally there will exist a further energy band above the valence
band, called conduction band. The energy difference between the highest
possible energy state in the valence band and the lowest energy state in the
conduction band is called the band gap W of the crystal. If we have W <
5eV one speaks of a semiconductor while for W > 5eV we speak of an
isolator. In Fig. 1.2 the band structure of the different materials is shown.
Since the band structure shows the energy of the negative electrons inside a crystal
the product of the electrostatic potential function
e
and the elementary charge e
is up to an arbritray constant equal to the band energy. Thus the following relation
holds true:

e
=
1
e
W
L
+C
1
=
1
e
W
V
+C
2
(1.3)
1.2 Intrinsic conductivity
The semiconductor silicon is a group IV element of the periodic table, thus it
possesses four valence electrons and forms a face-centered diamond cubic crystal
4

a) metal b) semiconductor c) isolator
W W W
W
V
W
L
0
W
V
W
L
0
W
V
W
L
0
Figure 1.2: Band structure of a metal, semicondcutor and isolator
structure. In the ideal crystal each atom forms covalent bondings with its four
neighbours, as schematically illustrated in Fig. 1.3a, which shows a plane model
of the crystal. At the absolute temperature T = 0K, all valence electrons are
trapped in covalent bondings. Thus considering the band structure, the valence
band is totally occupied, while the conduction band is totally empty as shown in
Fig. 1.3b. Hence there do not exist free charges inside the crystal and it is an

Si-atom covalent bonding

W
W
C
W
V
a)
b)
Figure 1.3: Plane model of Si-crystal and band structure at T = 0K
isolator. If the temperature is enhanced the atoms of the crystal will perform a
vibration around their mean location. With increasing temperature the thermal
movement of the single atoms can become so strong that single covalent bondings
will break. Now the valence electron will no longer be trapped to the bonding but
can almost freely move within the crystal. This situation is sketched in Fig. 1.4a.
In the picture of the band structure the thermal energy of the atom has moved an
electron from the valence to the conduction band. If an electric eld is applied to
5

Si-atom

W
W
C
W
V
a)
b)






electron hole
Figure 1.4: Plane model of Si-crystal and band structure at T > 0K
the crystal the free electrons will move against the eld direction. But not only
the free electrons will move, the electrons trapped in a bonding will move too.
Since one bonding electron is missing, other valence electrons may replace the
missing electron resulting in a movement of the missing electron in the eld di-
rection. The missing electron thus behaves like a positive charge and is called a
hole. The thermal induced breaking of a bonding thus results in the creation of an
electron-hole pair in the picture of the band structure. Beside the thermal creation
of electron-hole pairs there exists a process called recombination. In this process
a free electron will be trapped again in a covalent bonding, which is equivalent
to the annihilation of an electron-hole pair. In the thermal equilibrium both pro-
cesses are in balance and for a given temperature we will have a certain density of
electrons n and holes p in the crystal.
To calculate their values one not only has to take into account the Fermi-Dirac
distribution, but also the function D(W) which describes the density of states in
the crystal. If one approximates the Fermi-Dirac distribution by the Boltzmann
distribution one nds the following equations describing the electron and hole
density inside a crystal []:
n = N
C
exp(
W
C
W
F
k
B
T
) mit N
C
= 2(
2m

e
k
B
T
h
2
)
3/2
(1.4)
p = N
V
exp(
W
F
W
V
k
B
T
) mit N
V
= 2(
2m

p
k
B
T
h
2
)
3/2
(1.5)
Where m

e
denotes the effective electron mass in the conduction band and m

p
the effective hole mass in the valence band. This correction has to be done to
reect the difference between a free particle and an almost free particle in the
6
periodic potential inside a cyrstal. The values N
C
and N
V
are called effective
density of states in the conduction band respectively valence band. Table 1.1
gives some examples for the effective masses of electrons and holes for different
semiconductors. As already discussed earlier, the electron and hole density are
Semiconductor m

e
/m
e
m

p
/m
e
Si 0,33 0,56
Ge 0,22 0,33
GaAs 0,067 0,48
InP 0,078 0,64
Table 1.1: Effective masses of electrons and holes for different semiconductors []
equal in an ideal semiconductor. This opens the opportunity to dene the so-called
intrinsic charge density n
i
of a semiconductor by:
n
i
=

n p (1.6)
With the help of the equations 1.4 and 1.5 and W =W
C
W
V
we nd:
n
i
=
_
N
L
N
V
exp(
W
2k
B
T
) (1.7)
Example: Intrinsic charge density
Germanium: W =0,63 eV, Silicon: W =1,14 eV, T =300K
n
i Ge
1, 810
13 1
cm
3
n
i Si
2, 610
9 1
cm
3
The examples showthat we have a much lower intrinsic charge density in silicon at
the same temperature, due to its larger band gap. If we expose the semiconductor
to an electric eld the electrons as well as the holes will move with different mean
velocities thru the crystal lattice. This effect is described by the electron mobility

e
and the hole mobility
p
. Table 1.2 gives the mobility of electrons and holes for
different crystals. With the help of the mobility of electrons and holes and their
densities one can formulate the lawdescribing the conductivity of a semiconductor
[].
= e(
n
n +
p
p) (1.8)
Example: Intrinsic conductivity of germanium and silicon at T =300 K
7
Crystal Electron Holes
Si 1300 500
Ge 4500 3500
GaAs 8800 400
InSb 77000 750
InAs 33000 460
InP 4600 150
Table 1.2: Mobility of electrons and holes for different crystals in cm
2
/Vs []

i Ge
2.310
2
S/cm

i Si
7.510
7
S/cm
For example copper at the same temperature has a conductivity of
Cu
5.910
5
S/cm
which is by a factor of 10
7
higher than the conductivity of geramium.
1.3 Doping
The property of semiconductors that makes them most useful for constructing
electronic devices is that their conductivity may easily be modied by introducing
impurities into their crystal lattice. The process of adding controlled impurities to


W
W
C
W
V
a)
b)

donor atom

free electron



donor
level
W
F
Figure 1.5: Plane lattice and band structure of a n-condcutor
a semiconductor is known as doping. The amount of impurity, or dopant, added
to an intrinsic semiconductor can variegate its level of conductivity in a wide
8
range. Most useful doping materials are atoms of group 5 of the periodic table of
elements like phosphor (P), arsenic (As) and antimony (Sb) and atoms of group
3 like boron (B), aluminium (AL) and indium (In). To clearyfy the inuence of
doping we will have a look on Fig.1.5. Again Fig. 1.5 shows a plane model of the
Si lattice. But in contrast to an ideal Si lattice some of the Si atoms are replaced
by atoms having ve valence electrons. To build up the crystal lattice only four
valence electrons are needed, thus the fth electron is only weakly bounded to the
impurity atom. So only very little thermal energy is needed to free the electron. In
the picture of the band structure each impurity atomwill contribute its fth valence
electron to the conduction band. If we use N
D
to denote the volume density of the
donator atoms, this will resut in
n N
D
Hence with the help of the donator atoms, we can inuence the density of the free
electrons in the semiconductor, which is according to equation 1.4 equivalent to a
shift of the Fermi-level
W
F
W
L
k
B
T ln(
N
C
N
D
) (1.9)
Since the product np = n
2
i
only depends on the band gap of the semiconductor we
have,
p =
n
2
i
n

n
2
i
N
D
while the conductivity of the n-conductor is essentially given by
e
n
N
D
(1.10)
In a n-doped semiconductor the elctrons are called majority carrier while the holes
are called minority carrier. If we use doping atoms out of group 3 of the periodic
table of elements, one valence electron is missing. Due to thermal vibrations
this missing bonding can easily move from one atom to the other as shown in
Fig. 1.6. But as already introduced, a missing bonding electron is called a hole in
semiconductor theory. If we use N
A
to denote the volume density of the impurities,
each so-called acceptor atom will contribute a free hole to the valence band and
we have,
p N
A
and with the help of equation 1.5 we can nd the shift of the Fermi-level
W
F
W
V
+k
B
T ln(
N
V
N
A
) (1.11)
In a p-doped semiconductor the holes are the majority carriers while the electrons
are the minority carriers. For the conductivity of a p-type semiconductor we nd:
e
p
N
A
(1.12)
9


W
W
C
a)
b)

acceptor atom

free hole


W
V
acceptor
level
W
F
Figure 1.6: Plane lattice and band structure of a p-condcutor
1.4 Diffusion currents in semiconductors
In contrast to a metal diffusion currents may play an important roll within semi-
conductors, due to the effect that there might exist electrons and holes within the
same volume, forming an electric neutral carrier concentration. To explain the
process of diffusion we have a look at Fig. 1.7. It shows a plane section of a crys-
r
r
r
r
r
r
r
r
r
r r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r r
r
r
r r
r
r
r
r
r r
r
r r
r
r
r
r

x
Figure 1.7: Diffusion process within a crystal lattice
tal lattice in which a uniform concentration drop in the x direction exists, which
is represented by a different amount of particles within a certain region. If we
assume that due to thermal motion one half of the particles moves to the right and
the other half moves to the left, we get a net particle ow in the direction of the
concentration drop. So, diffusion does not need external forces to act on a group
of particles, but is just driven by their thermal energy. If we dene with J
D
p
(x)
the one dimensional diffusion current density of the holes and with J
D
n
(x) the dif-
fusion current density of the electrons, the diffusion current is described by the
following equations:
J
D
p
(x) = eD
p
dp
dx
J
D
n
(x) = eD
n
dn
dx
(1.13)
10
The positive sign in the equation of the electron current density reects the den-
tion of the positive technical current direction, which is contrary to the movement
of the electrons. The constants D
p
and D
n
are called diffusion coefcients and
they are related to the mobility of the carriers by Einsteins relation [?, ]
D
p
=
p
k
B
T
e
D
n
=
n
k
B
T
e
(1.14)
Thus the total current density of the holes J
p
and of the electrons in a semicon-
ductor is composed of the drift current due to an electric eld and the diffusion
current.
J
p
= e
p
pE eD
p
dp
dx
(1.15)
J
n
= e
n
nE + eD
n
dn
dx
(1.16)
11
Chapter 2
Semiconductor diode and
applications
2.1 The pn-junction
The simplest semiconductor component fabricated from both n-type and p-type
material is the semiconductor diode, a two-terminal device which, ideally, permits
conduction with one polarity of applied voltage and completely blocks conduction
when the voltage is reversed. For the mathematical despriction of a pn-junction we
will assume that changes in the crystal structure only occur in the x-direction while
the structure is homogenous in the y- and z-direction. As a result all considered
properties will only be functions of the x-coordinate.
2.1.1 pn-junction with zero bias
To understand the physical behaviour of a pn-junction we will rst consider the
junction being separated by an ideal, ctive, innite thin membrane as shown in
Fig. 2.1. In the n-region will exist a huge amount of free electrons, moving arbi-
trarily thru that region due to their thermal energy. There will also exist the same
amount of positive donator atoms being xed in the crystal lattice. In the adjacend
p-region we formally have the same situation but now the holes play the role of the
electrons and the donators are replaced by xed negative acceptor atoms. If we as-
sume the ctive membrane to be removed, due to the difference in concentration,
the free holes of the p-region will diffuse into the n-region, while the free electrons
of the n-region will diffuse in the p-region and a recombination of electron-hole
pairs will occur. As a result a transition region will be established between the p-
and n-region, were only the xed acceptor and donator atoms exist but essentially
no free carrier. As a further consequence an internal electric eld will be built up,
12

a)
b)
E

free hole
free electron
xed acceptor
xed donator
Figure 2.1: pn-junction with and without a ctive membran
canceling the diffusion process of the free carriers and also resulting in a potential
difference between the end faces of the crystal. This potential difference is called
diffusion or build-in voltage U
D
and is given by the following equation:
U
D
=
e
()
e
() (2.1)
To calculate the hole distribution p(x) we use equation 1.15 and consider the fact
that the diffusion process has stopped (J
P
=0) and that one can deduce the electric
eld by the gradient of the potential function, which is related to the valence band
energy W
V
(x) via equation 1.3:
k
B
T
dp(x)
dx
= p(x)
dW
V
(x)
dx
The last differential equation can be solved by separation of the variables, while
the neccessary constant can be deduced fromthe boundary condition p(x ) =
N
A
. Thus we get for the distribution of the holes:
p(x) = N
A
exp
_

W
V
() W
V
(x)
k
B
T
_
(2.2)
In an analog manner we get for the distribution of the electrons using the boundary
condition n(x ) = N
D
:
n(x) = N
D
exp
_

W
C
(x) W
L
()
k
B
T
_
(2.3)
13
To get a unique relation between the potential function
e
(x) and the band ener-
gies one uses the condition
e
(x ) = 0. As a result we get the following
relation between the potential function and the band energies of the valence and
the conduction band:

e
(x) =
1
e
[W
V
(x) W
V
()] =
1
e
[W
C
(x) W
C
()] (2.4)
With the help of the last equations the hole and the electron distribution may be
expressed by the potential function and the diffusion voltage:
p(x) = N
A
exp
_
e

e
(x)
k
B
T
_
n(x) = N
D
exp
_
e
U
D

e
(x)
k
B
T
_
(2.5)
The last two equations in combination with equation 1.7, may be used to deduce an
expression for the diffusion voltage without knowledge of the potential function

e
(x):
U
D
=
k
B
T
e
ln(
N
A
N
D
n
2
i
) (2.6)
Example: Diffusion voltage of a pn-junction in silicon
N
A
= N
D
= 10
15
cm
3
, T = 300K
U
D
25.9 mV ln
_
(10
15
)
2
(2.610
9
)
2
_
= 660 mV
According to equation 2.2 and 2.3 the decline of the electron and hole distribu-

x
w
n
w
p
(x)
eN
A
eN
D
Figure 2.2: Charge distribution of an abrupt pn-junction
tion follows an exponential function. To calculate the potential function one can
approximate the carrier distributions in the transition region by a step function
14
according Fig. 2.2. This approximation is called abrupt pn-junction [2] and con-
siders a constant negative charge distribution N
A
in the region w
p
< x < 0 and
a constant positive charge distribution N
D
in the region 0 < x < w
n
. Since the
pn-junction is electrically neutral, the following equation must hold true:
N
D
w
n
= N
A
w
p
(2.7)
To calculate the internal electric eld und potential function of an abrupt pn-
junction we use the one-dimensional divergence theorem of the electrical eld,
which results in the following differential equations for the electric eld:
dE
dx
=
e

N
A
for w
p
< x < 0 (2.8)
dE
dx
=
e

N
D
for 0 < x < w
n
(2.9)
The last equations can be integrated easily and one nds the following functional
dependence taking into account that the electric eld may only exist in the region
w
p
< x < w
n
E(x) =
eN
A

(x +w
p
) for w
p
< x < 0 (2.10)
E(x) =
eN
D

(w
n
x) for 0 < x < w
n
(2.11)
According to the above equations the value of the electric eld will rst fall linear
reaching its negative maximum at x = 0 and then will rise also linear to reach zero
again at x = w
n
. The negative sign of the electric eld reects the fact that it is
directed in the negative x-direction, as already shown in Fig. 2.1b. The potential
function can again be evaluated by integration, while the integration constants
must be chosen to reect the following boundary conditions
e
(w
p
) = 0 and

e
(x = 0

) =
e
(x = 0
+
).

e
(x) =
eN
A
2
(x +w
p
)
2
for w
p
x 0 (2.12)

e
(x) =
eN
D
2
(w
n
(w
p
+2x) x
2
) for 0 x w
n
(2.13)
In Fig 2.3 the functional dependence of the electric eld and the potential function
of an abrupt pn-junction is shown. With the help of the last equation and equation
2.7 the values w
p
and w
n
of the depletion zone may be evaluated.
15

w
p
w
n
E(x)
x
E
max

e
(x)
U
D

Figure 2.3: Electric eld and potential function of an abrupt pn-junction without
bias
w
p
=
_
2
e
U
D
N
D
N
A
(N
A
+N
D
)
w
n
=
_
2
e
U
D
N
A
N
D
(N
A
+N
D
)
As a result we get for the total width of the depletion zone:
w =
_
2
e
N
A
+N
D
N
A
N
D
U
D
(2.14)
According to Fig. 2.3 the electric eld reaches its highest absolute value E
max
at
the coordinate x = 0. Since the potential function is in the one-dimensional case
the integral of the electric eld, the easiest way to calculate its value is to evaluate
the area under the graph of the function:
U
D
=
1
2
(w
p
+w
n
)E
max
Using equation 2.14 we nd for the maximum of the electric eld:
E
max
=
2U
D
w
=
_
2eU
D

N
A
N
D
N
A
+N
D
(2.15)
Fig. 2.4 shows the energy band model of a pn-junction at zero bias. Due to the
locally xed acceptor and donator atoms an internal electric eld is created within
the depletion area, which results in a potential difference between the p- and n-
conductor called diffusion voltage or build-in voltage U
D
and in a band bending.
16

x
w
p
w
n
W
W
C
W
F
W
V

eU
D
p-conductor n-conductor





Figure 2.4: Energy band model of a pn-junction at zero bias
The inuence of the electric eld on thermally excited electrons can easily be
illustrated with the help of the band bending. If a thermally excited electron tries
to jump over the potential barrier it behaves like a sphere on a hill, which rolls
to the bottom again. In contrast holes act quite different. They behave more like
balloons in a water basin, they always bob up to the highest energy value in the
valence band, as illustrated in Fig. 2.4.
2.1.2 pn-junction with bias
With the help of the energy band diagrams shown in Fig. 2.5 in a rst step we
now want to discuss qualtively the operation principles of a pn-junction, if a bias
is applied. According to Fig. 2.5 a bias voltage is applied to the pn-junction with
a direction opposed to the internal electric eld. Hence it will lower the potential
barrier between the p- and n-conductor. Due to their thermal energy now electrons
of the n-conductor as well as holes of the p-conductor are able to surmount the
potential barrier and will diffuse into the p- as well as into the n-conductor. Being
minority carrier in these regions they will recombine and as a result a current
will ow in the direction of the applied voltage. If we change the direction of
the applied voltage, the internal electric eld will be enhanced, resulting in an
enhanced potential barrier. As a result the thermal energy neither of the holes nor
of the electrons is high enough to surmount the barrier. So, in principle no carrier
exchange between the two regions of the pn-junction will take place. Only due to
the intrinsic conductivity there will be a small amount of reverse current ow.
Analysis
After the qualitative discussion of the operation principles we will now describe
the process taking place in more mathematical depth. To deduce the mathematical
17
a)

W
C
W
F
W
V
W
x
w
p
w
n

b)

w
p
w
n
x
W
C
W
F
W
V

s s

e(U
D
U)
e(U
D
U)

Figure 2.5: Energy band model a) forward bias b) reverse bias


description we will use the following basic assumptions:
The voltage drop along the regions of the p- and n-conductor is neglected
and it is assumed that it only takes place along the depletion zone of the
pn-junction.
The current due to the minority carrier can solely be described as diffusion
current.
In the depletion zone no recombination takes place. As a result the total
current thru the diode can be described as the diffusion current of the mi-
nority carrier at the boundaries of the depletion zone at each side of the
pn-junction.
We will start our analysis by considering the density of holes p(x) in the n-
conductor. The concentration of the electrons n(x) in the p-conductor can be
18
deduced in an equivalent way. Starting from equation 2.5 we get for the hole
density at x = w
n
in dependence of the applied voltage U:
p(+w
n
) = N
A
exp(
e(U
D
U)
k
B
T
) = p
no
exp(
eU
kT
) (2.16)
In the last expression the constant p
no
denotes the hole density in the undisturbed
n-region (x ). According to equation 2.16 the hole concentration will rise
with U > 0 and decay for U > 0. To calculate the hole distribution in the n-region
we use the rate equation ??, extended by the divergence term of the currents [2]:
p
t
=
1
e
J
p
x

pp
no

In the stationary case (



t
= 0) this expression reduces to:
dJ
p
dx
= e
pp
no

(2.17)
According to our assumption the current J
p
is solely a diffusion current due to the
minority carrier and we get for the region w
n
< x < the following differential
equation:
d
2
p
dx
2
=
1
D
p

(pp
no
) =
1
L
2
p
(pp
no
) (2.18)
In the last term the constant L
p
=
_
D
p
was introduced, it posseses the dimension
of a length and hence denotes the mean length along which a minority carrier can
diffuse in its lifetime before it will recombinate. The solution of the above
differential equation has to reect that for x = w
n
the hole density is given by
equation 2.16 and hence we nd as solution:
p(x) = (p(w
n
) p
no
)exp(
x w
n
L
p
) + p
no
(2.19)
According to equation 2.19 the denisty of the minority carrier in the n-region is
governed by an decaying exponential function. Using equation 1.15 we nd the
following diffusion current density at x = w
n
:
J
p
(w
n
) = e
D
p
L
p
p
no
_
exp(
eU
k
B
T
) 1
_
(2.20)
In an equivalent way one can also deduce an expression for the diffusion current
J
n
(w
p
) and since we assume that there will be no recombination in the depletion
zone we get for the total current thru a pn-junction:
J = J
s
_
exp(
eU
k
B
T
) 1
_
with J
s
= en
2
i
_
D
p
L
p
N
D
+
D
n
L
n
N
A
_
(2.21)
19
According to equation 2.21 the current density thru the pn-junction will rise ex-
ponentially for positive voltages U, while it will decay for negative values. In the
limit it will reach a value of J
s
, hence this value is called reverse biased satura-
tion current density. If we multiply the current density with the area A
pn
of the
pn-junction we get the static I-U characteristic of an ideal pn-junction.
I = I
s
_
exp(
U
U
T
) 1
_
with I
s
= A
pn
J
s
and U
T
=
k
B
T
e
(2.22)
In equation 2.22 the constant U
T
was introduced, which is called thermal voltage.
At room temperature (T = 300 K) it shows a vaule of approximately 26 mV. Since
the voltage drop along the p- and c-conductor was neglected, equation 2.22 is
only valid for small currents. The ohmic behaviour for these regions can in a rst
step be approximated by a resistor R
s
. As a result the ideal pn-junction is only

U
V
I
mA
ideal
R
S
= 1
0
20
40
60
100
0 0.2 0.4 0.6 1
Figure 2.6: Static I-U-characteristic of an ideal pn-junction with I
s
= 10nA
controlled by the reduced voltage U R
s
I. To demonstrate the inuence of this
resistor in Fig. 2.6 the static I-U-characteristic of an ideal pn-junction with I
s
=
10nA and of the same diode with R
s
= 1 is shown.
20
2.1.3 Small-signal model of a pn-junction
The equations deduced in the preceding section describe the behaviour of a pn-
junction only for almost static time functions. To get an idea of its dynamic be-
haviour it is useful to study small signal exitation at a given operation point. In
principle we will study the circuit given in Fig. 2.7, where a DC current source
I is used to setup a certain operation point and a sinusoidal current source i(t) is
used to realize the small signal exitation.

D
r
r
r
r

i(t)

r
r
I

Figure 2.7: Small signal exitation of a pn-junction


Dynamic resistance r
D
According to Fig. 2.7 we assume the pn-junction to be operated in a given op-
eration point (I, U). Due to the sinusoidal current source with amplitude

I there
will also exist a sinusoidal voltage across the pn-junction with amplitude

U. One
speaks of small signal exitation as long as the following relations hold true:

I I and

U U
For a rst order approximation, we will describe the current voltage characteristic
by its slope at the operation point. Hence for the amplitudes of the sinusoidal time
functions the following relation holds true:

U
dU
dI

I =
1
dI
dU

I = r
D

I
In the last equation the dynamic resistance r
D
of a pn-junction was introduced.
Assuming the pn-junction is forward biased, we get the following expression for
the dynamic resistance using equation 2.22:
r
D
=
U
T
I
(2.23)
21
Example: Dynamic resistance of a pn-junction at an operation point of I = 10
mA.
According to equation 2.23 we nd
r
D
=
25, 9 mV
10 mA
2, 6
Diffusion capacitance c
D
As already discussed in section 2.1.2 a forward biased pn-junction will store mi-
nority carrier in the n- as well as in the p-region. So each change in voltage u
at a given operation point will also result in a change for stored minority carrier.
To calculate the stored minority carrier in the n-region we use equation 2.19 and
perform an integration over the n-region:
Q(U) = eA
pn


w
n
_
(p(w
n
) p
no
)exp(
x w
n
L
p
)
_
dx
For a differential change of the applied voltage u we can write:
q
dQ(U)
dU
u =
eA
D
L
p
p
no
U
T
exp(
U
U
T
) u (2.24)
Equation 2.24 can be used to dene the diffusion capacitance c
D
of a pn-junction.
c
D
=
q
u
=
eA
D
L
p
p
no
U
T
exp(
U
U
T
) =

U
T
I =

r
D
(2.25)
Example: Diffusion capacitance of pn-junction at an operation point of I = 1 mA.
In silicon diodes the minority carriers have a lifetime of 2.510
3
s
c
D
=
2, 5 ms
25, 9 mV
1mA 97 F
According to the last example, the diffusion capacitance shows relatively high
values. Since the dynamic resistance and the diffusion capacitance are essentially
connected in parallel, the storage of the minority carrier in the p- and n-regions
inhibits the technical usage of the dynamic resistance at higher frequencies of an
ordinary pn-junction diode, since it is short circuited by the capacitance.
22
Junction capacitance c
J
To deduce an expression for the junction capacitance we have a look at Fig. 2.3,
which shows the electric eld distribution inside the depletion zone of the pn-
junction. If the applied voltage is changed with time also the electric eld will
change, resulting in a displacement current density. To nd an expression of its
value we start with equation 2.15 and assume that the total voltage u
pn
(t) is given
by the sum of a DC voltage U
o
and a time varying voltage u(t). Hence we get
for the electric eld in the pn-junction
E(t, x = 0) =
_
2e

N
A
N
D
N
A
+N
D
(U
D
U
o
)(1
1
2(U
D
U
o
)
u(t)) (2.26)
and for the displacement current density
J
v
=
dE(t, x = 0)
dt
=

e
N
A
N
D
N
A
+N
D
1
2(U
D
U
o
)
du(t)
dt
(2.27)
Since we assume a homogenous distribution across the cross-section of the pn-
junction, the total displacement current can be calculated by multiplication with
the area A
pn
of the pn-junction. According to the denition of a capacitance the
factor in front of the time differential of the voltage must be the expression for the
junction capacitance.
c
J
= A
pn

N
A
N
D
N
A
+N
D
e
2(U
D
U
o
)
(2.28)
To describe the small signal frequency response of a real semiconductor diode in

s
s
r
D
c
J
L
S
s s
s s
C
P
R
S
Figure 2.8: Small signal equivalent circuit of a real semiconductor diode
Fig. 2.8 its equivalent circuit is given. Besides the elements already discussed two
further elements are included. This is a series inductance L
S
accounting for wire
bonds and a parallel capacitance C
P
reecting the inuence of the packaging.
23
2.1.4 Spice model of a semiconductor diode
In the preceding section we discussed the behaviour of an ideal pn-junction. As an
electric two terminal device it is called semiconductor diode. Since all electronic
devices exhibit strong nonlinearities the behaviour of an electronic circuit can only
be analysed by using sophisticated simulation tools. Most of todays commercial
available tools are based on a simulator called SPICE Simulation programm with
Integrated Circuit Emphasis which was developed at the University of Berkley [].
Even though we already discussed several effects and parameters of an ideal pn-
junction a real diode needs even more parameters to describe its real behaviour.
In the following section we will give a short introduction to the equation used
to describe a real diode in the Spice simulation tool, while the denotation of the
parameters a summarised in Table ?? at the end of this section. Fig. 2.9 shows
the equivalent circuit that is used in SPICE. The total time dependent current i
D
(t)

s
s s
s s
s

i
D
u
D
C
D
C
J
R
S

I
D
Figure 2.9: Spice model of a semiconductor diode
thru the diode is calculated using the following equation:
i
D
= I
D
+ C
D
du
D
dt
+ C
J
du
D
dt
(2.29)
Static diode current I
D
Forward biased, the static diode current I
D
is equal to the current of an ideal pn-
junction already given in equation 2.22, but with a further parameter N included,
called emission coefcient.
I
Di
= IS(T)
_
exp
_
u
D
N U
T
_
1
_
(2.30)
24
Here the temperature dependence of the saturation current IS(T) is given by the
following expression:
IS(T) = IS
_
T
T
0
_
(XTI/N)
exp
_
EG(1T
0
/T)
Nk
B
T
0
_
(2.31)
If a diode is reverse biased, experiments showthat the real reverse current is higher
than that predicted by equation 2.30. To account for this effect an additional
current I
Dc
of a so-called correction diode is added:
I
Dc
= ISR
_
exp
_
u
D
NR U
T
_
1
_

_
_
1
u
D
VJ
_
2
+ 0, 005
_
M/2
(2.32)
If the reverse voltage of the diode is further enhanced reverse breakdown occurs
which is modeled by an exponential function:
I
D
= IBV exp
_
u
D
BV
NBV U
T
_
(2.33)
Dynamic diode current
To account for the dynamic behaviour of a real diode expressions for the junc-
tion capacitance and diffusion capacitance have to be considered. According to
equation 2.28 the junction capacitance varies proportional to the square root of the
applied reverse voltage. For a real diode this expression is slightly modied
C
J
= CJO
_
1
u
D
VJ
_
M
(2.34)
If a diode is forward biased the lifetime of the miniority carrier of the junction has
to be considered. In its implementation SPICE uses also equation 2.25 already
discussed earlier.
C
D
= TT
di
D
du
D
=
TT
r
D
(2.35)
In the following table the essential SPICE parameters used to specify a real diode
are summarized
IS saturation current
N emission coefcient
ISR saturation current of correction diode
NR emission coefcient of ISR
BV reverse breakdown voltage
IBV current at break-down voltage
25
NBV coefcient of IBV
RS series resistance
TT minority carrier life time
CJ0 zero-bias junction capacitance
VJ junction potential
M grading coefcient
FC coefcient for forward-bias depletion capacitance formula
EG activation energy
XTI temperature exponent of IS
KF icker noise coefcient
AF icker noise exponent
To include different diodes into SPICE ordinary ASCII-les are used as shown in
the following example.
Example: SPICE diode data sets
*
-----------------------------------------------------------
.MODEL BAT68 D(IS=8N RS=2 N=1.05 XTI=1.8 EG=.68
+ CJO=.77P M=.075 VJ=.1 FC=.5 BV=8 IBV=1U TT=25P)
*
-----------------------------------------------------------
.MODEL BA592 D (IS=185F RS=.15 N=1.305 BV=70 IBV=.1N
+ CJO=1.17P VJ=.12 M=.096 TT=125N)
*
-----------------------------------------------------------
.MODEL BAS116 D(
+ AF= 1.00E+00 BV= 7.50E+01 CJO= 1.83E-12 EG= 1.11E+00
+ FC= 5.00E-01 IBV= 1.00E-04 IS= 1.48E-13 KF= 0.00E+00
+ M= 2.62E-01 N= 1.33E+00 RS= 8.48E-01 TT= 8.66E-09
+ VJ= 3.44E-01 XTI= 3.00E+00)
*
-----------------------------------------------------------
2.1.5 Different types of semiconductor diodes
There were developed different types of junction diodes by emphasizing different
physical aspects for example by geometric scaling, by changing doping levels or
by the use of different semiductor materials. In the following section we will give
a short overview of the diodes most often used in electronics.
26
Zener diodes
The ordinary junction diode will be destroyed, if a reverse voltage is applied, ex-
tending their maximum reverse voltage and breakdown occurs. Zener diodes in
this sense are special diodes that will not be destroyed when the breakdown oc-
curs. Furthermore it is possible to controll the breakdown voltage or Zener voltage
of the diode very precisley. Fig. 2.10 shows the current voltage characteristic of
an ideal Zener diode, which will be conducting as soon as the applied reverse volt-

U
D
I
D
U
Z0
Figure 2.10: I-U characteristic of a ideal Zener diode
age exceeds the Zener voltage U
Z0
. In practical applications these diodes are used
to stabilize a voltage to a certain level.
Schottky diode
From a historical point of view not the pn-junction but the crystal detector was
the rst electronic device already used at the end of the 18th century. In principle
it consists of thin sharpened metal wire pressed against a crystal, thus forming a
metal to semiconductor contact. Today this kind of diode can also be constructed
using semiconductor technology and is called Schottky diode. But in contrast to
a pn-junction no minority carrier is essential for the nonlinear behaviour and they
tend to show a much lower junction capacitance. Thus they can be used up to very
high frequencies as mixers and detectors [].
Varactor diodes
As already discussed in section 2.1.3 if reverse biased, each junction diode shows a
certain capacitive value, that depends on the applied reverse voltage. Furthermore
the value of capacitance and its voltage dependence can be controlled using certain
doping proles. Thus varactor diodes can be used to replace a capacitor, with the
advantage of being adjustable by an applied voltage. One of the main practical
application are their use in voltage controlled oscillators.
27
Photo detector
If a pn-junction is reverse biased only a small reverse current exists, due to thermal
creation of electron hole pairs within the depletion region. But if the pn-junction
is exposed to light and the photon energy is high enough to surmount the band gap
energy of the semiconductor W
g
they can create electron hole pairs. This process
is called absorption. If no external voltage is applied, the photodiode operates in
the mode of a solar cell, converting optical into electrical energy. If the diode is
reverse baised, it operates in the mode of a photo detector and can be used to sense
light. In this case the reverse current, called photo current I
ph
, is proportional to
the incident optical power P
opt
and the proportional constant is called responsivity
R
sp
of the photo detector.
I
ph
= R
sp
P
opt
(2.36)
Light emitting diodes (LEDs)
The fundamental physical principle LEDs are based on is called spontaneous
emission []. If an electron of the conduction band recombines with a hole of
the valence band, the energy may be emitted as photon of a certain wavelength or
frequency, depending on the bandgap W
g
of the semiconductor.
=
C
0
h
W
g
f =
W
g
h
(2.37)
But this process may only take place in certain semiconductors, called direct band-
gap semiconductor. Unfortunatly silicon is no direct-band gap semiconductor.
So more sophisticated materials like GaAs have to be used. All LEDs produce
incoherent, narrow-band light.
Laser diodes
In a crude approximation a laser diode is a LED-like structure with an additional
optical resonator, formed by the endfaces of the semiconductor crystal itself. Due
to this resonator the bandwith of the light due to spontaneous emission is reduced
and stimulated emission takes place resulting in light with a high coherence [].
Laser diodes are commonly used in optical storage devices and for high speed
optical communication.
28
2.2 Diode applications
2.2.1 Diode as rectier
In the previous sections we discussed intensively how to describe and model the
electrical behaviour of a semiconductor diode. For the basic understanding of
diode applications such as a rectier circuit these models are even far to compli-
cated. So here we will introduce the simplest possible model of a diode. From Fig.
2.6 we know that a semiconductor diode has a very strong nonlinear behaviour.
Essentially there will be no current ow, if it is reverse biased, but arbitrarilly
high currents if it is biased in the froward direction. In Fig. 2.11 the static I-U-

U
D
U
th
ideal diode diode with threshold voltage U
th
I
D
Figure 2.11: Diode modeled as a voltage sensitive switch
characteristic of an ideal diode is given. Essentially an ideal diode will behave like
a voltage sensitive switch. If the voltage U
D
across the diode is negative the diode
will show an innite resistance, thus it behaves like an open switch. If on the other
hand the voltage across the diode is positive, it shows a very low resistance or the
switch is closed. Specially for discussion of the following basic diode applica-
tions this model is appropriate for their principle understanding. Especially, when
dealing with small voltages, the model with a certain threshold voltage U
th
can be
used, also shown in Fig. 2.11. For normal silicon diodes the value of the threshold
voltage lies in the range from 0.6 V to 0.7V. The slight differences in behaviour
of real diodes can be examind using simulation tools.
Almost in all electronic equipment DC voltages of different values are needed
for their operation. Since the electric power distribution system uses AC voltages
of 230 V nominal they usually have to be transformed to a lower level and con-
verted to DC. This process is called rectication and in most practical application
this is done with the help of semiconductor diodes. In the following sections we
will discuss different circuits that are used for rectication.
29
Half-wave rectier

r rr
R
L
rr r
r
r


u
D
u
R
u
S
Figure 2.12: Circuit schematic of a half-wave rectier
Fig. 2.12 shows the circuit schematic of a half-wave rectier. It consists of an
alternating source delivering a sinusoidal voltage u
S
(t), a diode and a load resis-
tance R
L
. It should be noted that the nominal output voltage U
N
of a transformer
is the effective value of the sinusoidal time function, so one always has to remem-
ber, that the amplitude

U is by a factor of

2 higher than the nominal value U


N
.
To understand the behaviour of the circuit we introduce the voltage u
D
(t) across
the diode and the voltage u
R
(t) across the load resistance. According to KVL the
following equation holds true:
u
S
(t) + u
D
(t) + u
R
(t) = 0
Since the diode is essential for the operation of the circuit we rst have a look on
the voltage across the diode
u
D
(t) = u
S
(t) u
R
(t) = u
S
(t) R
L
i
D
(t) (2.38)
Starting with a positive half cycle all voltages are zero and so is the diode current
i
D
(t). If now the source voltage becomes positive, the diode voltage becomes
positive too and according to our model the diode will switch into its on state.
As a result the source voltage will drop across the load and the voltage across the
diode will essentially be zero. If now the negative half cycle will start, at rst
again the diode current will be zero and as a result the voltage across the diode
will become negative. According to our model the diode will now switch into
its off state. No current i
D
(t) will exist and thus there will be no voltage drop
across the resistor, but the whole voltage of the source will drop across the diode.
As an example Fig. 2.2.1 shows the time function across the resistor as result
of a simulation with SPICE. The amplitude of the sinusoidal voltage source was
chosen to be 5V, with a load resistance of 500 and the diode BA592. Essentially
it shows the half-wave of the exiting voltage source, but there is a remarkable
30
units <1mm, 1mm>x f rom0.00to80.00, y f rom0.00to68.1511 <1mm>1010 <0pt >
REF : 0 1V/Div[lb]at068.74[lb]at072.590Sec[lb]at 3.852
3.25950mSec[lb]at76.153.259
Figure 2.13: Output voltage of a half-wave rectier
difference. While the model of an ideal diode would propose an amplitude of
5V, the simulation shows that there will be a voltage drop of about 0.8V across
the diode at the peak voltage of the half cycle. For practical applications it is
neccessary to choose an appropriate diode for the application. Thus one has to
consider certain maximum ratings of a diode, which are usally given in their data
sheet. Two crucial parameters are the maximum reverse voltage U
Rmax
and the
maximum forward current I
Fmax
. In case of a half-wave rectier we must fulll
the following conditions:
U
Rmax
>

U =

2U
N
and I
Fmax
>

U
R
L
(2.39)
Of course the voltage shown in Fig. 2.2.1 is not yet a DC voltage but still a
periodic time function, with a DC part given by the following equation.
U
DC
=

U
N
(2.40)
To further smooth the ouput voltage a capacitor may be used as shown in Fig.

r
r
r
r

u
D
u
S
r
r
C
r
r
r
r
R
L

u
R
Figure 2.14: Half-wave rectier with smoothing capacitor
2.14. Fig. 2.15 shows the simulation results of the same half-wave rectier where
according to Fig. 2.14 a capacitor of 100F was included for smoothing, also
shown is the time function without a capacitor. [lb] at 45.00 41.00
Figure 2.15: Ouput voltage of a half-wave rectier with smoothing capacitor
31
units <1mm, 1mm>x f rom0.00to80.00, y f rom0.00to68.1511 <1mm>1010 <0pt >
REF : 0 1V/Div[lb]at068.74[lb]at072.590Sec[lb]at 3.852
3.25950mSec[lb]at76.153.259C = 100F
So even if there seemed to be only a little change in the circuit due to the ca-
pacitor there is an signicant change in the maxium ratings the diode now has to
withstand. At rst we will have a look on the simple equation for the diode voltage
2.38. In the limit of high load resistances R
L
the maximum voltage will become
nearly equal to the amplitude

U of the AC voltage. So, according to equation 2.38
the maximum reverse voltage may reach a value of 2

U, thus the following condi-
tion must be fullled, in case of a half-wave rectier with smoothing capacitor.
U
Rmax
> 2

U (2.41)
But not only the diode must withstand a two times higher reverse voltage, but also
the maximum possible forward current is signicantly changed due to the capac-
itor. This is because at swichting time a capacitor behaves like a short circuit.
Thus, if the rectier is not switched on at a zero crossing, but at a certain positive
voltage value of the alternating source, the maximum forward current is only lim-
ited by internal resistances and can reach fairly hight values. To circumvent this
problem, it is sometimes neccessary to include a resistor in series to the diode to
limit the maximum possible forward current. Even though the circuit of a half-
wave rectier is very simple, it is also very inefcient for power transfer, since
only one half-cycle is used.
Full-wave rectier
The circuit that allows us to use every half-wave of a cycle is called full-wave
rectier. Fig. 2.16 shows its circuit schematic. To realise the two equal voltage
sources, in pratice a transformer is used whose secondary winding is split into two
with a center tap connected to the ground. In principle the upper and lower part
of the circuit each work like a half-wave rectier, but if the anode of diode one is
positive, due to the grounding of the sources, the anode of diode two is negative
and vice versa. Since now each half-wave will be rectied, we get for the DC part
of the voltage:
U
DC
= 2

U

= 2

U
N
(2.42)
while the maximum reverse voltage will reach a value of 2

U and thus the follow-
ing condition must be fulllled.
U
Rmax
> 2

U (2.43)
32
r

r
r
r

rr
R
L

u
S
(t)
u
S
(t)

u
R
(t)

u
D1
(t)
u
D2
(t)
Figure 2.16: Circuit schematic of a full-wave rectier
One disadvantage of this kind of full-wave rectier is the costly transformer, due
to its center tap. To over-come this a so-called bridge rectier as shown in Fig.
2.17 may be used. With the help of this circuit the costly transformer is omitted

D3
r

D4
r

D2
r
r r rrr r
R
L
r

D1
r
r

u
S
(t)

u
R
(t)
Figure 2.17: Circuit schematic of a bridge rectier
by the expense of two further diodes. During the positive half cycle D1 and D4
will be conducting, while diodes D2 and D3 are reverse biased. Thus the current
will ow in the direction of diode D1 thru the resistor R
L
. If the polarity of the
cycle changes, now diodes D3 and D2 are conducting, while diodes D1 and D4
are reverse biased. Now the current will ow in the direction of D3 thru the
resistor, but this direction is identical to that during the positive half cycle. Thus
independent of the polarity of the half cycle, the current will always ow in the
same direction thru the load resistance. [lb] at 45.00 38.00
Figure 2.18: Output voltage of a brigde rectier without and with smoothing ca-
pacitor
Fig. 2.18 shows the simulation results, again using the diode BA592 and a
33
units <1mm, 1mm>x f rom0.00to80.00, y f rom0.00to68.1511 <1mm>1010 <0pt >
REF : 0 1V/Div[lb]at068.74[lb]at072.590Sec[lb]at 3.852
3.25950mSec[lb]at76.153.259C = 100F
500 load resistance. Comparing the maximum amplitude, with the simulation
given in Fig. 2.2.1 shows, that in the case of the bridge recticer the peak volt-
age is further reduced, since in the rectication process two diodes are involved
always. Of course as in the case of the half-wave rectier, also in the case of the
bridge rectier a smoothing capacitor may be connected in parallel to the load
resistance. The result using a cpacitor of 100F parallel to the load resistance is
also shown in Fig. 2.18.
Series and parallel connection of diodes
Under certain circumstances there may exist a neccessity to use diodes that for
example cannot withstand the occuring reverse voltage or forward current. In the
rst case diodes can be connected in series to reach the necessary reverse voltage
capability as shown in Fig. 2.19a, but with the help of two parallel resistors it must
be assured that the voltage will drop equally across the diode to compensate for
differences in their saturation currents. To enhance the forward current capability,

r r

r r
r
R
P
r
R
p
r
r
r r r r r r r rr
R
s
R
s

r r r
a) b)
Figure 2.19: Combined diodes to enhance reverse voltage or forward current ca-
pability
two diodes may be connected in parallel, as shown in Fig.2.19b. But here series
resistors have to be used to compensate for differences in current distribution.
2.2.2 Voltage multiplier
Before we will discuss the circuit of a voltage multiplier according to Greinacher,
we will again have a look on the simple circuit of a half-wave rectier shown in
Fig. 2.20 where the positions of the capacitor and diode are changed with respect
to the ground and compared to the circuit of Fig. 2.14. Using KVL we get for the
34

u
S
(t)
u
C
(t)
u
o
(t)
Figure 2.20: Half-wave rectier with interchanged capacitor and diode
ouput voltage u
o
(t) of the circuit
u
o
(t) = u
S
(t) + u
C
(t)
Fig. 2.2.2 shows the simulation result for the time function u
o
(t) according to
units <1mm, 1mm>x f rom0.00to80.00, y f rom0.00to68.1511 <1mm>1010 <0pt >
REF : 0 2V/Div[lb]at068.74[lb]at072.590Sec[lb]at 3.852
3.259100mSec[lb]at76.153.259
Figure 2.21: Output voltage u
o
(t)
the circuit of Fig. 2.20. As source voltage u
S
(t) a sinusoidal time function with a
5 V amplitude was used. Roughly spoken the output voltage u
o
(t) shows a maxi-
mum amplitude of approximately 10 V, which is two times the source amplitude,
because the capacitor is charged to 5 V. Of course the output voltage may be used
as an input of a further half-wave rectier as shown in Fig. 2.22a. The principle

rr
r

r
r

r rr
r
r
rr r
r r
r r

U
o

u
S
(t)
rr
r r

r
r
r

r r r r
r r

r
r
r r r r
r r

r
r
r r r r
r r

r
r r r
r
U
0

u
S
(t)
Figure 2.22: Voltage doubler and multiplier circuits
of the voltage doubler shown in Fig. 2.22a was extended by Greinacher to reach
even higher voltage levels by adding further stages, as shown in Fig 2.22b. In
principle the voltages of the capacitors in the lower line will add up to the nal
35
REF : 0 2V/Div[lb]at068.74[lb]at072.590Sec[lb]at 3.852
3.259500mSec[lb]at76.153.259
Figure 2.23: Output voltage of a two stage voltage multiplier
voltage level U
0
. The time function of a two stage voltage multiplier ist given
in Fig. 2.2.2. According to our crude approximation, with two stages we should
reach a voltage level of 20 V. As the simulation shows we only reach a value of
approximately 17 V. If we would assume a voltage drop of approximately 0.7V
across each diode, this would sum up to a value of 2.8V, which may essentially
explain the difference.
2.2.3 Zener diode as voltage regulator
In the circuit shown in Fig. 2.24 a zener diode is used to stabilize the output
voltage U
0
to the Zener voltage of the diode. To describe the performance of a
r r
R
s

r
r
r r
r r
r r

U
i
U
o
U
Z
I
o
I
Z

U
Z0
U
Z
I
Z
Figure 2.24: Simple circuit to regulate the ouput voltage
Zener diode usually the current and voltage directions given in Fig. 2.24a are
used. These results in the I-U characteristic of a Zener diode given in Fig. 2.24b.
In contrast to the very sophisticated models that can be used with SPICE, we will
restrict our considerations to idealized Zener diodes. As shown in Fig 2.24b we
will describe the diode by its Zener voltage U
Z0
and a resistance r
Z
, which will
become zero in the limit of an ideal Zener diode. Of course the circuit of Fig.
2.24 is only able to stabilize the output voltage to the Zener voltage as long as
the relation U
i
> U
Z0
holds true. One crucial parameter of a Zener diode is its
maximum possible dissipation power P
max
, which will limit the maximum current
36
I
Zmax
thru the diode and we have:
I
zmax

P
max
U
Z0
(2.44)
But for proper operation at least a certain minimum current I
Zmin
must ow thru
the diode. To deduce an expression for the series resistor we use the loop equation
of the circuit and solve it for the resistor:
R
s
=
U
i
U
o
I
o
+ I
Z
(2.45)
In the practical operation of the circuit there are two extreme cases possible:
The input voltage reaches its minimum value U
imin
while the maximum out-
put current I
omax
is drawn. Under these circumstances it has to be sure that
I
Z
must not fall below I
Zmin
, thus resulting in an upper limit for the series
resistor.
R
s
<
U
imin
U
o
I
omax
+ I
Zmin
(2.46)
The input voltage reaches its maximum value U
imax
while only a minimal
value of output current is drawn I
omin
. Under these circumstances it has to
be sure that I
Z
must not exceed its maximum value I
Zmax
, thus dening a
lower limit for the series resistor.
R
s
>
U
imax
U
o
I
omin
+ I
Zmax
(2.47)
Only if the two inequalities are both fullled, the circuit according to Fig. 2.24 is
realisable with the chosen Zener diode. To compare different circuits to stabilize
the output voltage we dene the following stability factor S
S =
U
i
/U
i
U
o
/U
o

dU
i
/U
i
dU
o
/U
o
(2.48)
In principle the last form of equation 2.48 allows us to deduce expressions for the
stability factor using small signal approximations. Of course, if we would assume
an ideal Zener diode with r
Z
= 0, the stability factor S would become innte since
a variation of the input voltage would not result in a variation of the ouput voltage
at all. If we now, in a rst order approximation consider the Zener diode to have
a non zero r
Z
, a change in the input voltage U
i
will also result in a change of the
output voltage U
o
. According to the circuit schematic of Fig. 2.24a the following
equations are valid:
U
i
= R
s
I + r
Z
I
Z
+ U
Z0
and U
o
= r
Z
I
Z
+ U
Z0
37
If there is a change in the input voltage dU
i
there will also be a change in the
current I and the current I
Z
, so we have,
dU
i
= R
s
dI + r
Z
dI
Z
and there will also be a change in the output voltage
dU
o
= r
Z
dI
Z
So we nd for the ratio dU
i
/dU
o
:
dU
i
dU
o
=
R
s
dI + r
Z
dI
Z
r
z
dI
Z

R
s
r
Z
dI
dI
Z
for R
s
r
Z
In a rst order approximation we can neglect a current change due to the change
of the output voltage and we have dI = dI
z
and we get:
dU
i
dU
o
=
R
s
r
z
So we get as nal result for the stability factor of the circuit according to Fig.
2.24a:
S
R
s
r
z
U
o
U
i
(2.49)
Example: The current thru a load may vary between 0 mA and 100 mA, while
the voltage should be kept stable at 15 V and the input voltage may vary between
27 V and 33 V. A diode with I
Zmax
= 200 mA and I
Zmin
= 20 mA is used. Find the
value of R
s
and the stability factor.
According to the equations 2.46 and 2.47 we get for the series resistance the fol-
lowing relations,
R
s
< 100 and R
s
> 90
so the ratings of the Zener diode are sufcient and the series resistor may be
chosen to be R
S
= 95. From the data sheet of the Zener diode one nds the
maximum dynamic resistance r
Z
to be 7, so we get for the stability factor
S =
95
7
15
30
6.8
38
r r
R
s

r r rr r
r r

U
i

U
o
Figure 2.25: Circuit to stabilize low voltages
Stabilization of low voltages
Usually Zener diodes are built for breakdown voltages above 3 V. So, if one has
to stabilize an output voltage below this value one has to use an other circuit. One
possible simple circuit is shwon in Fig. 2.25. Here the series connection of diodes
is used to stabilize the output voltage. Roughly spoken each diode needs a voltage
of approximately 0.6 V to become conducting. So the output voltage is a multiple
of this value.
39
Chapter 3
The bipolar junction transistor and
applications
3.1 The bipolar junction transistor
We will now discuss the bipolar junction transistor (BJT), which started the age of
electronics. Since its invention in 1948 a lot of different electronic devices have
been realized capable to amplify weak electric signals. Even though today the
most commonly used transistor is the eld effect transistor, we will start our dis-
cussion with the BJT since its operation principles are based on the the behaviour
of a pn-junction, we already discussed.
3.1.1 Structure and operation principles of a npn BJT
Fig. 3.1a shows the simplied physical layout and 3.1b the circuit schematic of
a npn BJT. It consists of a highly n-doped conductor called emitter (E), followed
by a thin p-doped zone, called base. The adjanced zone is called collector, which
is again formed by a n-doped conductor. In Fig. 3.1c an example of a cross
sectional view of a npn-BJT is given, which is realized with the help of SBC-
technique (Standard Buried Collector ) [?], [?] inside an integrated circuit. The
realisation process starts with weak p-conducting silicon crystal. With the help
of gas phase epitaxy a weakly doped n-conductting layer is formed, realizing the
collector (N
DC
10
15
cm
3
). With the help of the p-zones on both sides the
single transistor is isolated to the adjanced ones. With the help of an oxidation
process a silicon oxid layer is formed, in which a window dening the base is
etched. In the following diffusion process the base is formed using Bor atoms
with a concentration of approximately N
AB
10
17
cm
3
. In a further oxidation
and etching process the window for the emitter is formed and nally with the help
40
s s
s
E C
B
N
P
N


s s
s
E C
B
a)
b)
c)


s
s
s
p-Silizium
n
++
p
+
n p n
+
p
+
E
B
C
Figure 3.1: a) simplied physical layout, b) circuit schematic and c) cross sec-
tional view of a npn-BJT
of a diffusion process a donator concentration of approximately N
DE
10
22
cm
3
is realized in the emitter zone, leaving a thin p-conduction layer, which forms the
base of the transistor. To discuss the principle of operation of a BJT we have a
look on Fig. 3.2. In the upper part a simple cross sectional view of the different
layers of the npn BJT ist given. Since the volatge U
BE
> 0 the E-B junction is
forward biased and since the voltage U
BC
< 0 the B-C junction is reverse biased.
Also sketched are widths of the depletion zone of the two junctions. Since the
emitter is highly doped the depletion zone of the E-B junction extends wider into
the base and since the base is normally higher doped than the collector, here the
depletion zone extends wider into the collector. In the lower part of Fig. 3.2 the
energy band diagram under typical basing conditions is shown. Under these con-
ditions the emitter-base-diode is forward biased and thermally excited electrons
are able to surmount the potential barrier to the base, in which they will diffuse.
Since they are minority carriers some of them will recombine and result in a base
current. But if the diffusion length is much longer than the thickness of the base,
the majority of electrons entering the base from the emitter will diffuse thru the
base and enter the depletion zone between base and collector. Since this diode is
based in reverse direction there will exist an electric eld, accelerating the elec-
trons into the collector. Hence creation of an emitter base current will result also
in an emitter collector current. Thus with the current thru the emitter base diode
the current from the emitter to the collector may be controlled. This is essen-
tially the principle of operation of a npn BJT. To reach this state of operation the
following conditions must be met:
The current thru the emitter base diode must be essentially an electron cur-
rent. According to equation 2.21 this is only valid for highly doped emitters.
The majority of electrons entering the base are only capable to reach the
41

x
W
C
W
F
W
V
W
s s
s
E
B
C

U
BE
> 0
U
BC
< 0



Figure 3.2: npn BJT forward baised E-B junction reversed baised B-C junction
collector if the diffusion length L
n
inside the base is longer than the base
thickness d
B
.
The reverse current of the base collector diode has to be negligible small.
In Fig. 3.3 the current distribution inside a BJT is shown qualitatively. The di-
rections of the currents I
E
, I
B
and I
C
where chosen to give the technical current
directions, which is opposed to the movement of the electrons. The thinner arrows
denote the unwanted hole currents between the emitter and the base as well as the
reverse current of the base collector diode. As a result of Fig. 3.3 it is clear that
the collector current is proportional to the emitter current.
I
C
=
0
I
E
(3.1)
The parameter
0
of the last equation is called static current gain in a common
base circuit, despite the fact that due to the recombination of electrons in the base
its value is always lower than one (
o
0,9 0,999). Since the BJT is a node
42
s s
s

E C
B
I
E
I
C

I
B

Figure 3.3: Current distribution in a npn BJT under typical operation conditions
we can apply Kirschhoffs current law:
I
E
= I
B
+ I
C
If we use the last equation to give the collector current as function of the base
current we will get:
I
C
=

0
1
0
I
B
=
0
I
B
(3.2)
The parameter of equation 3.2 is denoted as static current gain in a common emit-
ter circuit. Depending on the transistor
0
can reach values between approxi-
mately 30 and 500.
3.1.2 Static input and output characteristics of a BJT
According to the arragement of the layers a transistor can be represented by two
diodes which are connected at their p-layer. Such a circuit would of course not
act as a transistor because the anode of the emitter base diode is also the anode of
the base collector diode in a physical sense, but not only in an electrcical sense as
modeled by the equivalent circuit. To account for the transistor effect, according
to [?], a current controlled current source has to be included parallel to the base
collector diode, which represent the electron current from the emitter to the col-
lector of a real transistor. As a result we get the equivalent circuit of a transistor
given in Fig. 3.4 under typicall operation condictions, describing its static behav-
iuor. The currents I
SE
and I
CE
representing the saturation currents of the emitter
base and base collector diode, while the resistances of the semiconductor layers
are neglected.
I
E
= I
SE
_
exp(
U
EB
U
T
) 1
_
(3.3)
43


s s s s s
s s s

I
E I
C

o
I
E
U
EB
U
CB
Figure 3.4: Simplied equivalent circuit according to Ebers-Moll under typical
operation conditions
I
C
=
o
I
E
I
SC
_
exp(
U
CB
U
T
) 1
_
(3.4)
As shown in Fig. 3.5 the equivalent circuit of Fig. 3.4 can also be given in a
common emitter conguration. With the help of equations 3.3 and 3.4 we will

s
s s s
s

s s
s s s
s s

U
CE
I
E
I
C
I
B
U
BE
U
CE
U
BE

0
I
E

Figure 3.5: BJT in common emitter conguration at its Ebers-Moll-model


now deduce an expression for the input characteristic I
B
= f (U
BE
,U
CE
) and for
the output characteristic I
C
= f (U
CE
,U
BE
). Staring point is again KCL for the
BJT as a whole:
I
B
= I
E
I
C
= (1
0
)I
E
+I
SC
_
exp(
U
CB
U
T
) 1
_
Accounting the different denitions of the voltages U
EB
= U
BE
and U
CB
=
U
CE
U
BE
we get for the base current:
I
B
= (1
0
)I
SE
_
exp(
U
BE
U
T
) 1
_
+I
SC
_
exp(
U
CE
U
BE
U
T
) 1
_
For typical conditions of operation we have U
CE
U
BE
and the last term may be
neglected, resulting in the following expression for the base current:
I
B
= (1
0
)I
SE
_
exp(
U
BE
U
T
) 1
_
= I
SB
_
exp(
U
BE
U
T
) 1
_
(3.5)
44
The form of the last equation is equivalent to that of a normal pn-junction, which
has a saturation current of I
SB
= (1
0
)I
SE
. Thus the input characteristic of a
transistor is equivalent to that of a pn-junction already shown in Fig. 2.6. With
the help of equation 3.4 we get as expression for the collector current I
C
,
I
C
=
0
I
SE
_
exp(
U
BE
U
T
) 1
_
I
SC
_
exp(
U
CE
U
BE
U
T
) 1
_
(3.6)
or with reference to the saturation current I
SB
I
C
=

0
1
0
I
SB
_
exp(
U
BE
U
T
) 1
_
I
SC
_
exp(
U
CE
U
BE
U
T
) 1
_
(3.7)
Example: Theoretical output characteristic of a BJT
As example Fig. 3.6 shows the output characteristic of a BJT according to equa-

U
CE
V

I
C
mA
0, 64V
0, 66V
0, 68V
0
2
4
6
10
0 1 2 3 5
Figure 3.6: Theoretical output characteristic of a BJT with U
BE
as parameter
tion 3.6, where the following values were used for its calculation: I
SE
= I
SC
=
1 nA, U
T
=43 mV,
0
= 0, 999. Comparing the theoretical predicted output char-
acteristic shown if Fig.3.6 with that of a real BJT shows that the current I
C
of a
real BJT rises with rising voltage U
CE
. Is effect is called Early-effect [?].
The rst term of equation 3.7 can be identied as current gain
0
of the com-
mon emitter conguration:

0
=

0
1
0
(3.8)
45
while the second term describes nothing else but the dependence of the base cur-
rent I
B
on the voltage U
BE
.
I
B
(U
BE
) = I
SB
_
exp(
U
BE
U
T
) 1
_
(3.9)
With the help of the introduced parameters equation 3.7 can be rewritten as
I
C
=
0
I
B
(U
BE
) I
SC
_
exp(
U
CE
U
BE
U
T
) 1
_
(3.10)
Since under normal operation conditions the base collector diode is based in re-
verse direction, the last term of equation 3.10 can be neglected, which reduces this
equation to
I
C

0
I
B
(U
BE
) (3.11)
describing essentially the behaviour of a BJT in a common emitter conguration.
Equation 3.9 and equation 3.11 can be used to setup a large signal model of a BJT
operating in common emitter conguration, as shown in Fig. 3.7 It consists of the

rrr
r
r

0
I
B
r
I
B
C B
E
Figure 3.7: Large signal model of a BJT under normal operation conditions
base emitter diode carrying the current I
B
and an ideal current controlled current
source being responsible for the collector current.
3.1.3 Simple small signal BJT model
One of the applications of transistors is the amplication of small signals. To use
a transistor for amplication one has to operate the transistor under certain DC
conditions U
CE
, I
C
, called biasing. In principle one uses voltage or current sources
to establish the DC conditions under which the transistor shows the described
transistor effect. Fig. 3.8 shows a BJT circuit in common emitter conguration.
The DC voltage sources U
BE
and U
CE
are chosen to establish the typical operation
conditions of the transistor, emitter base diode forward biased and base collector
diode biased in reverse direction. In the input circuit an additional sinusoidal
46
voltage source u
BE
(t) is used, with an amplitude

U
BE
fullling the small signal
condition

U
BE
U
BE
. In the ouput circuit a load resistance R
L
is included to allow
an alternating voltage u
CE
(t) to exist, also fullling the small signal condition

U
CE
U
CE
. A mathematical exact analysis of the circuit shown in Fig. 3.8 is

r r


R
L

U
CE
U
BE
u
BE
(t)
Figure 3.8: Common emitter circuit of a BJT with small signal exitation
very complicated due to the nonlinear behaviour of the equations 3.9 and 3.10
and only possible using advanced simulation tools. Since we are at the moment
only interested in the small signal behaviour we linearize equations 3.9 and 3.11
in the vicinity of the point of operation and thus establish a small signal equivalent
circuit of the BJT at the point of operation. In mathematical sense we will perform
a Taylor approximation at the opertaion point.
I
B
=
I
SB
U
T
exp(
U
BE
U
T
)U
BE

| I
BE
|
U
T
U
BE
(3.12)
In analogy to the pn-junction one can introduce the dynamic resistance r
BE
of the
base emitter diode.
r
BE
=
U
T
| I
B
|
(3.13)
Also linearizing equation 3.11 yields the equivalent circuit shown in Fig. 3.9,
where the resistor r
CE
was additionaly included to account for the Early effect, al-
ready mentioned above. Since the equivalent circuit was deduced from equations
3.9 and 3.11 describing the static behaviour of the transistor, it is only valid for
low frequencies.
h-parameter
To describe the small signal behaviour of BJT at lowfrequency also the h-parameters
are used []. In this case these parameters are real and they describe the inuence
47
r
r
BE
r
r r

r
r r r

r
r r
r
r
CE
r
r r
r
r
R
L

u
BE
(t)
i
B

0
i
B

u
CE
(t)
Figure 3.9: Simple common emitter small signal equivalent circuit of a BJT
of the output voltage u
CE
(t) and input current i
B
(t) on the input voltage u
BE
(t)
and the output current in a more formalized way given by the following equation:
u
BE
= h
ie
i
B
+h
re
u
CE
i
C
=h
f e
i
B
+h
oe
u
CE
(3.14)
From equation 3.14 it becomes clear that the single parameters are dened ac-
cording to the following equations:
h
ie
=
u
BE
i
B
|
u
CE
=0
short circuit input resistance
h
re
=
u
BE
u
CE
|
i
B
=0
open circuit reverse voltage ratio
h
f e
=
i
C
i
B
|
u
CE
=0
short circuit forward current gain
h
oe
=
i
C
u
CE
|
i
B
=0
open circuit output conductance
(3.15)
Since the rst equation of 3.14 denes the small signal voltage u
BE
it may be
interpreted to be the result of Kirchhoffs voltage law at the input of the transistor
while i
C
of the second equation is the result of Kirchhoffs current lawat its output.
Using these interpretations one nds the equivalent circuit shown in Fig. 3.10.
Comparing the equivalent circuit of Fig. 3.10 with that already given in Fig. 3.9

s
s s
s

h
oe
i
C
h
ie
i
B
u
BE
h
re
u
CE
u
CE
h
f e
i
B

s s s
s
Figure 3.10: Small signal equivalent circuit according to the h-parameters
reveals the following equivalences:
h
ie
= r
BE
h
f e
= h
oe
= 1/r
CE
(3.16)
48
On the other hand, the parameter h
re
nds no equivalent element in Fig. 3.9,
because it was deduced from the static behaviour and the parameter h
re
decribes
the feeback of an alternating voltage at the output on the input voltage, which of
course cannot be deduced using static equations. Nevertheless we will use the
parameters given in Fig. 3.9 for a rst order analysis of small signal amplier,
because of their physical signicance. If a more detailed analysis is needed this
can today be done using advanced simulation tools. Nevertheless h-parameters
are often specied in data sheets of single transistors for a certain operation point.
3.1.4 Advanced small signal BJT model
If we want to have a more accurate equivalent circuit describing the behaviour also
up to higher frequencies, we have at least to account for the capacitve behaviour
of all encountered pn-junctions. According to Fig. 3.7 we must consider the
capacitance c
BE
of the base emitter diode, which essentially will reect minority
storing, due to the diffusion process. Even if we neglected the reverse biased base
collector diode, to reach the simplied equivalent circuit of Fig. 3.7, its junction
capacitance c
Bc
has to be considered. A further effect we also did not consider up
r r
r r
r r
I
B

r
r
r
B

E
r r
R
BB

r r

0
I
B

r
r

r
r
c
B

E
r
r
r r
r r
r
r
r
CE
r r
r r
r r
c
B

C
r r

U
BE

U
CE
Figure 3.11: Advanced common emitter small signal equivalent circuit of a BJT
to now is the bulk semiconductor material between the base and the active base
emitter junction, giving rise to the resistor R
BB
. Of course all considered voltages
or currents are now given in phasor notation. The extended equivalent circuit of a
BJT shown in Fig. 3.11 is referred to as full hybrid model.
3.1.5 SPICE model of a BJT
Fig. 3.12 shows the so-called Gummel-Poon-model of a npn BJT as it is imple-
mented in the spice circuit simulator. As in the model already given in Fig. 3.4
also in the Gummel-Poon model a transistor consists essentially of the base emit-
ter diode D
BE
and the base collector diode D
BC
and current controlled current
sources i
F
and i
R
. In contrast to the Ebers-Moll model they are controlled by the
base currents i
BE
and i
BC
. The current voltage characteristic of this diode is de-
scribed by the exponential law already used to describe a real pn-junction (2.30).
49
R
C
r

D
BC
r
r

D
LC
r
r

D
BE
r
r

D
LE
r
r
C
dBC
r
r
C
sBC
r
r
C
dBE
r
r
C
sBE
r
r
R
BB
r r

u
BC

u
BE
R
E
r r
r r

i
F

i
R
r

Kollektor
Emitter
Basis
Figure 3.12: Gummel-Poon-model of a npn BJT
The diodes D
LE
and D
LC
are incorporated to describe leakage currents which have
no inuence on the controlled current sources, and the capacitances C
jBE
, C
dBE
,
C
jBC
, C
dBC
account for the junction und diffusion capacitance of the doides D
BE
and D
BC
. In the following table the SPICE data set of the BJT BFP420 is given:
SPICE data set:
**********************************************************
.MODEL BFP420 NPN(
+ IS = 17.7E-18 RB = 9.47 CJC = 380E-15 BF = 117
+ IRB = 0.5E-3 VJC = 1.0 NF = 0.98 RBM = 5.47
+ MJC = 0.5 VAF = 45 RE = 0.948 XCJC = 0.18
+ IKF = 0.15 RC = 4.4 TR = 5.0E-9 ISE = 4.5E-12
+ CJE = 130E-15 CJS = 0 NE = 2.31 VJE = 1.0
+ VJS = 0.8 BR = 1.0 MJE = 0.5 MJS = 0.33
+ NR = 1.0 TF = 9.6E-12 XTB = 0 VAR = 1000
+ XTF = 0.457 EG = 1.16 IKR = 1000 VTF = 0.413
+ XTI = 3.0 ISC = 0 ITF = 41E-3 FC = 0.78
+ NC = 2.0 PTF = 0 )
50
************************************************************
3.2 Small signal amplier
In order to use a BJT as small signal amplier at rst certain DC values U
CE
and
I
C
have to be established ensuring that the base emitter diode is forward biased,
the base collector diode is reversed biased and the transistor effect can take place.
For single transistors a certain point of operation is often recommended on its data
sheet. Under these circumtances small signals may be applied and the transistor
can be used as an amplier.
3.2.1 BJT biasing
At rst we now want to discuss different possiblities to reach this point of opera-
tion. For calculation we use the equivalent circuit of the BJT shown in Fig. 3.7,
were we assume that the base emitter diode may be modeled by an ideal diode
with a xed threshold voltage U
BE
according to Fig. 2.11 and the BJT has a con-
stant current gain
0
.
Constant base current biasing
One of the simplest possible circuit to reach a certain point of operation is shown
in Fig. 3.13. Since the whole circuit is driven by the DC voltage source U
0
, so we
r
r
R
C
r r
R
B

U
BE
r

U
0
r r
r r


r
r
U
CE
Figure 3.13: Constant base current circuit
get for the collector resistance R
C
:
R
C
=
U
0
U
CE
I
C
(3.17)
51
Due to the given current gain
0
of the transistor the base current I
B
is also known
and we can setup an equation for the resistor R
B
.
R
B
=
U
0
U
BE
I
C

0
(3.18)
Usually the value of the DC voltage U
0
is much higher than the voltage U
BE
and
further-more the base current I
B
is very low, so the value of R
B
becomes very high
and essentially it behaves like a current source. So the base current is essentially
constant and the temperature dependence to the operation points is only due to the
temperature dependence of
0
(T). A very crucial drawback of the circuit is that
the value of R
B
depends directly on the value of
0
, which usually shows a high
variation for single transistors.
A circuit with which one can over-come the considered problems is shown in
Fig. 3.14. For the collector resistor we get:
r
R
B
I
B

U
CE
r
r r r

U
BE
R
C
I
C

U
0
Figure 3.14: Constant base current circuit with feed back
R
C
=
U
0
U
CE
I
C
(1+1/
0
)
(3.19)
And the equation for the resistor R
B
reads:
R
B
=
U
CE
U
BE
I
C

0
(3.20)
Although the equation for R
B
does not exhibit an obvious decrease in
0
depen-
dence, the feedback does tend to stabilize the operation point. For exmaple, if
the transitor has a much higher
0
than the nominal value used to calculate R
B
,
the collector current will be higher and the collector voltage lower than the de-
sign values. With the lower collector voltage there is less voltage across R
B
and
therefore less base current, thus at least partially compensating for the higher
0
.
52
Conversely, if
0
is lower than the nominal value, the collector current is less than
the design value giving a greater voltage across R
B
and hence results in a higher
base current, again partially compensating for the low
0
.
Biasing using a base voltage divider
Fig. 3.15a shows a further possiblity to bias the transistor to a certain operation
point U
CE
and I
C
. In contrast to the preceeding circuit now the voltage U
B
is
I
E


r
R
E
r
I
C
R
C
r
I
B
r
R
1
r
I
T

R
2
rr r
rr r

U
CE
U
0
U
E
U
B
Figure 3.15: Base voltage divider with current feedback
essentially kept constant. Without the resistor R
E
this circuit would be very prob-
lematic, because of the self heating of the transistor. But with the resistor R
E
a
feedback due to the current I
E
is introduced. For example, assume the current
I
E
will increase due to a rise of temperature. Since the voltage U
B
is xed, the
voltage U
BE
driving the base current I
B
will be reduced and hence the current I
E
is reduced again. Typically the voltage U
E
across R
E
is chosen to be in the range
of 1 V to 3 V. For the voltage devider represented by the resistors R
1
and R
2
to act
as a voltage source the transverse current I
T
has to be large compared to the base
current I
B
. Here typically a factor of 10 is chosen. As for the preceeding circuit,
we assume to know the transistor parameter U
BE
and
0
. From the given voltage
U
E
we rst can calculate the value of the resistor R
E
.
R
E

U
E
I
C
(3.21)
With the help of KVL in the output circuit, we nd for the resistor R
C
.
R
C
=
U
0
U
CE
U
E
I
C
(3.22)
53
The voltage U
B
can also be calculated as a result of KVL in the lower base circuit,
U
B
= U
BE
+ U
E
and if we assume the transverse current I
T
to be 10 times the base current, we nd
for the resistor R
2
,
R
2
=
U
B
I
T
=
U
BE
+ U
E
10I
C
/
0
(3.23)
and nally we get for the resistor R
1
R
1
=
U
0
U
B
I
T
+ I
B
=
U
0
U
BE
U
E
11I
C
/
0
(3.24)
Example: Biasing of the transistor BC548C
Data: U
0
= 12V, U
CE
= 5V, I
C
= 2mA,
0
= 400, U
BE
= 0.65V and U
E
= 2V
R
E
=
2
210
3
= 1k
R
C
=
1252
210
3
= 2.5k chosen R
C
= 2.7k
As a result the voltage U
CE
will become:
U
CE
= U
0
R
C
I
C
U
E
= 4.6V
R
2
=
0.65+2
10 510
6
= 53k chosen R
2
= 47k
As a result the transverse current will become I
T
= 56A wich is approximately
11 times the base current, so we get for the resistor R
1
R
1
=
122.65
12 510
6
156k chosen R
1
= 150k
3.2.2 Common-emitter amplier
One of the most commonly used congurations to realize a small signal amplier
using a BJT is the common-emitter amplier shown in Fig. 3.17. It is called
common-emitter conguration, because the emitter of the transistor belongs to
the input as well as to the output of the circuit. In this circuit the operation point
of the transistor is realized using a base voltage divider. The signal of the source
54
r
r
R
2
r
R
1
r
r
C
E
r r r r


r
r
r r
C
1
r rr
R
G

r
r
r
r
R
E
r
r
R
C
r
C
2
r
R
L
r r
r r
r
r
C

r r
r

U
0
Figure 3.16: Common-emitter amplier
is AC coupled with the help of capacitor C
1
to the base to the transistor. This must
be done to not disturb the operation point by the internal resistance of the signal
source. For the same reason the capacitor C
2
is used to AC couple the output
signal to the load resistance R
L
. As already mentioned in section 3.2.1 the resistor
R
E
will result in a current feedback, which will reduce the overall amplication
of the circuit, thus the capacitor C
E
is used to allow the AC current to by pass the
resistor. Even so the DC supply voltage source U
0
has a zero internal resistance
theoretical on a practical circuit board the additional capacitor C

has to be used
to realised the AC short circuit on the circuit board.
AC equivalent circuit
Of course all currents and voltages at the transistors are a superposition of DC and
AC values. Since we already discussed how to realise a certain operation point the
DC values are no longer of interest and the transistor may be replaced by its small
signal equivalent circuit shown in Fig. 3.9. Further-more we want to assume
r r
I
B
r

r
r r
r
r
R
C
r r
r r
r
r
R
L
r
r
BE
r r
rr r
r r
r
r
R
1
r r
r r r
r
R
2
r
R
S
r

U
S

U
BE
I
B

U
CE

r
in

r
out
Figure 3.17: AC equivalent circuit of a common-emitter amplier
55
that the capacitors C
1
, C
2
and C
E
are sufciently high-valued to have negligble
reactance at the frequencies of interest. With the help of these considerations,
we can setup the AC equivalent circuit of the common-emitter amplier shown
in Fig. 3.17, where the small signal output resistance r
CE
of the transistor is also
neglected.
Small signal voltage gain
Normally a small signal amplier is used to amplify weak input signals. Of course
one is interested in the value of the output signal, if a certain input signal is ap-
plied. The ratio of these two voltages is called voltage gain v which usually is
a function of the frequency. Using the circuit shown in Fig. 3.17 we dene the
voltage gain of this stage to be:
v
u
=
U
CE
U
BE
(3.25)
Introducing a resistor R

L
R

L
=
R
C
R
L
R
C
+ R
L
being equal to the parallel connection of R
C
and R
L
, we can write for the output
voltage U
CE
U
CE
= R

L
I
B
According to Fig. 3.17 we have the following relation between the base current
I
B
und the base voltage U
BE
,
I
B
=
U
BE
r
BE
and hence we get for the output voltage,
U
CE
= R

L
U
BE
r
BE
and nally for the voltage gain of the common-emitter stage:
v
u
=
U
CE
U
BE
=
R

L
r
BE
(3.26)
Input and ouput resistance
According to the equivalent circuit shown in Fig. 3.17 the input resistance r
in
of
the stage is given by the parallel connection of R
1
, R
2
and r
BE
,
r
in
=
1
1
R
1
+
1
R
2
+
1
r
BE
(3.27)
56
while the ouput resistance r
out
is equal to the collector resistance R
C
.
r
out
= R
C
(3.28)
Choosing the values of the capacitors
All capacitors included in the common-emitter amplier circuit shown in Fig. 3.17
will contribute to its highpass character. So the amplier will only properly work
above a certain lower frequeny limit we call f
low
. Instead of a rigorous treatment
of the equivalent circuit incorporating all capacitors we will discuss the inuence
of each capacitor separately in a more heuristic manner.
Capacitor C
E
The purpose of this capacitor is to reduce the inuence of the
resistor R
E
on the AC gain of the amplier. Since it is connected in parallel to
the resistor, with increasing frequency the total reactance will become smaller
and smaller and for high frequencies there will exist no current feedback at all.
If already for the lower frequency limit f
low
there shall be no remarkable current
feedback, the following relation must hold true,
1
2f
low
C
E
R
E
which gives a lower limit how to chose the value of C
E
.
C
E

1
2f
low
R
E
(3.29)
Capacitor C
1
If the capacitor C
E
is chosen high enough, the resistors R
S
, r
in
and the capacitor C
1
will form a rst order high-pass lter. Its corner frequency
f
c
being given by:
f
c
=
1
2C
1
(R
S
+r
in
)
Choosing the corner frequency equal to the lower frequency limit f
low
gives a
lower limit for the capacitor C
1
C
1

1
2 f
low
(R
S
+r
in
)
(3.30)
Capacitor C
2
The capacitor C
2
in the ouput circuit is equivalent to the capacitor
C
1
in the input circuit. Thus it will also form a rst order high-pass lter with
57
the resistors R
C
and R
L
, if the capacitor C
E
is chosen high enough. So we get an
equivalent lower limit for its value analog to the limit of capacitor C
1
.
C
2

1
2 f
low
(R
C
+R
L
)
(3.31)
Example: Common-emitter amplier with the transistor BC548C
As an example we will calculate the gain to be expected from a common-emitter
amplier using the transistor BC548C with a biasing according to the last section.
We will choose the load resistance R
L
to be equal to R
C
and we assume a source
with internal resistance R
S
of 50. According to equation 3.13 we get for the
dynamic resistance r
BE
,
r
BE
=
0.026
0.002/400
= 5.2k
and hence for the expected voltage gain
v = 1.35k
400
5.2k
104
and for input resistance:
r
in
=
1
1
47
+
1
150
+
1
5.2
k = 4.54k
If we want the amplier to work above a lower frequency limit of f
low
= 50 Hz
we have to choose the capacitor C
E
according to equation 3.29:
C
E

1
250 10
3
F = 3.18F chosen C
E
= 300F
Using the equations 3.30 and 3.31 we nd for the cpacitors C
1
C
1

1
250 4.5910
3
F = 0.69F chosen C
1
= 1F
and C
2
C
2

1
250 5.410
3
F = 0.59F chosen C
2
= 1F
To verify the prediction above of the gain and the values of the chosen capacitors
Fig. 3.18 shows the simulated frequency response of the common-emitter ampli-
er with the transistor BC548C. The source amplitude was set to be 1mV. With
58
Figure 3.18: Simulated frequency response of the common-emitter small signal
amplier
the help of the marker function we can read out an output amplitude of almost
40dBmV, which corresponds to an absolute value of a small signal gain of 100,
which is very close to the predicted value. The 3 dB cut-off frequency of the high-
pass can be read out to be approximately 110Hz, which is considerably above the
envisaged lower frequency limit of 50 Hz. But the lower frequency limit can now
easily be adjusted by increasing the values of the coupling capacitors C
1
and C
2
. It
is interesting to notice the limitation of the gain at higher frequencies predicted by
the simulation. Of course the SPICE model of the transistor is far more elaborated
than the simple small signal model of Fig. 3.17 and the internal capacitances of
the transistor will limit the frequency range of operation and result in a low-pass
characteristic for high frequencies with a 3 dB cut-off frequency of approximately
14 MHz. If one liked to use the ampier as the input stage of an audio amplier,
one should reduce the cut-off frequency to lower values using additional capaci-
tors in the circuit.
Summarizing the properties we can say that a common-emitter state shows
a high voltage gain
a high current gain
59
a high power gain
a moderate input resistance approximately equal to r
BE
a moderate output resistance approximately equal to R
C
3.2.3 Common-collector amplier
A further possibility to realize a small signal amplier with the help of a BJT is
the common-colllector circuit shown in Fig. 3.19. It is called common-collector
r rr
r
R
2
r r
r r
C
1
r rr
R
S
r

r
R
1
r
r
C


r
r
r r r

r
r r
C
2
r r
r
r
R
L
r
r
R
E

U
0
Figure 3.19: Common-collector amplier
amplier, since the collector of the BJT belongs to the input as well as to the
output circuit of the amplier. Also the term emitter-follower is used. To establish
the operation point again a biasing base voltage divider is used, and established
with the help of the resistors R
1
, R
2
and R
E
. In contrast to the common-emitter
amplier the resistor R
C
is missing. The AC input signal is coupled to the base
using the capacitor C
1
while the capacitor C
2
is used to couple the output signal to
the load resistance R
L
.
AC equivalent circuit
As in the case of the common-emitter amplier we will assume that the capaci-
tors C
1
and C
2
are sufciently high-valued to have negligible reactance at the fre-
quencies of interest. With the help of these considerations, we can setup the AC
equivalent circuit of the common-collector amplier shown in Fig. 3.20, where
the small signal output resistance r
CE
of the transistor is also neglected.
60
r
r
r
r
r r
r r
r
r
R
E
r
R
L
r r
r
BE
r r
r r
r r
r
r
R
1
r r
r r
r
r
R
2
r
R
S
r

U
S

U
BC

I
B
r
r

I
B

U
EC

I
E

r
ini

r
in
Figure 3.20: AC equivalent circuit of a common-collector amplier
Input resistance
We will start our analysis calculating the input resistance r
ini
of the intrinsic com-
mon collector stage rst excluding the contribution of the resistors R
1
and R
2
. As
a rst step we introduce the resistor R

L
which reects the parallel connection of
the resistors R
E
and R
L
.
R

L
=
1
1
R
E
+
1
R
L
Using KVL for the input circuit we nd,
U
BC
= [r
BE
+ (+1)R

L
]I
B
and hence we get for the intrinsic input resistance of a common-collector stage:
r
ini
=
U
BC
I
B
= r
BE
+ (+1)R

L
(3.32)
Comparing r
ini
of a common-collector stage with the intrinsic input resistance r
ini
of the common-emitter stage, which is equal to r
BE
, shows that it is considerable
larger, since the total load resistance R

L
is multiplied by the factor and added to
r
BE
, according to equation 3.32. So the resistors of the base voltage divider may
not be neglected calculating the input resistance of the total stage.
r
in
=
1
1
r
ini
+
1
R
1
+
1
R
2
(3.33)
Small signal voltage and current gain
The voltage gain of the common-collector amplier is dened by:
v
u
=
U
EC
U
BC
61
According to the equivalent circuit shown in Fig. 3.20 we get for the output vol-
tage U
EC
,
U
EC
= R

L
I
E
while we get for the current I
E
and hence for the current gain
I
E
= (+1)I
B
v
i
=
I
E
I
B
= (+1) (3.34)
I
E
= (+1)
U
BC
r
ini
=
+1
(+1)R

L
+r
BE
U
BC
So we nd for the voltage gain of the common-collector amplier
v
u
=
(+1)R

L
(+1)R

L
+ r
BE
1 (3.35)
which is approximately equal to one for transistors with high current gain .
Output resistance
To deduce an expression for the output resistance of the common-collector stage
we again consider Fig. 3.20 and introduce the resistore R

S
which accounts for the
parallel connection of the resistors R
S
, R
1
and R
2
, assuming the voltage source to
be turned off.
R

S
=
1
1
R
S
+
1
R
1
+
1
R
2
According to Fig. 3.20 the ouput resistance r
out
is given by:
r
out
=
U
EC
I
E
A voltage U
EC
applied at the output will result in the following base and emitter
current:
I
B
=
U
EC
R

S
+r
BE
I
E
= (+1)
U
EC
R

S
+r
BE
as a result we get or the ouput resistance:
r
out
=
R

S
+r
BE
+1
(3.36)
62
Chosing the values of the capacitors
All capacitors included in the common-collector amplier circuit shown in Fig.
3.19 will contribute to its highpass character. So the amplier will only work
properly above a certain lower frequeny limit we call f
low
. Instead of a rigor-
ous treatment of the equivalent circuit incorporating all capacitors we again will
discuss the inuence of each capacitor separately in a more heuristic manner.
Capacitor C
1
Again the resistors R
S
, r
in
and the capacitor C
1
will form a rst
order high-pass. Its corner frequency f
c
being given by:
f
c
=
1
2C
1
(R
S
+r
in
)
Chosing the corner frequency equal to the lower frequency limit f
low
gives a lower
limit for the capacitor C
1
C
1

1
2 f
low
(R
S
+r
in
)
(3.37)
Capacitor C
2
The capacitor C
2
in the ouput circuit is equivalent to the capacitor
C
1
in the input circuit. Thus it will also form a rst order high-pass lter with the
resistors r
out
and R
L
. So we get an equivalent lower limit for its value in analogy
to the limit of capacitor C
1
.
C
2

1
2 f
low
(r
out
+R
L
)
(3.38)
Summarizing the properties we can say that a common-collector state shows
a voltage gain of approximately one
a high current gain
a moderate power gain
a high input resistance equal to r
BE
+(+1)R

L
a low output resistance of
R

S
+r
BE
+1
63
3.3 Integrated circuit techniques
In designing integrated circuits the economic rules of discrete component circuit
design are reversed. Active devices are inexpensive since they can be realized
on a much smaller area than resistors or capacitors. Hence, every effort must be
made to minimize the total resistance in a circuit and certainly replace passive
components with transistors or diodes wherever possible. In the following section
we will start with the conventional design of the operational amplier and we will
discuss different possibilities to make it a circuit with almost no passive elements.
3.3.1 The differential amplier
One serve disadvantage of the amplier circuits discussed in the previous section
is that single stages have to be coupled using capacitors which is inpratical for
integrated circuit technology. Another drawback is that also due to the coupling it
is not possible to amplify voltages of very low frequencies down to DC. To over-
come these problems the circuit shown in Fig. 3.21 can be used, which is called
differential amplier. Essentially it consists of two identical transistors coupled


r
r
r rr
r

r
R
C
r
R
C
r r


r
r
r
r
r r

r r r r
r

U
2o
r

U
1o

U
0
U
0
U
n
U
p
U
To

I
E2

I
E1

I
0
Figure 3.21: Differential amplier
by an ideal current source of constant current I
0
. In contrast to conventional am-
pliers a positive as well as a negative supply voltage is used and two voltages
U
p
and U
n
are used as input signal. To get an ouput signal to equal load resistors
R
C
are used in the collector branch of each transistor. Due to the symmetry of the
circuit an output voltage U
To
will only exist, if there is a difference between the
64
input voltages. Thus it is convenient rst to dene the difference voltage U
d
by:
U
d
= U
p
U
n
(3.39)
It is interesting to point out that according to KVL the difference voltage U
d
is
also equal to the difference of the base emitter voltages of the two transistors.
U
d
= U
BE1
U
BE2
(3.40)
To further analyse the behaviour of the circuit especially in dependence of an
applied difference voltage, we start with the node equation at the current source,
which forces the sum of the two currents I
E1
and I
E2
to be constant.
I
E1
+ I
E2
= I
0
(3.41)
Of course the emitter current of each transistor may also be expressed according
to equation 3.3 as a function of its base emitter voltage,
I
E1
= I
S
exp
_
U
BE1
U
T
_
I
E2
= I
S
exp
_
U
BE2
U
T
_
assuming identical transistors at the same temperature. Using equation 3.41 we
get
I
0
= I
S
_
exp
_
U
BE1
U
T
_
+ exp
_
U
BE2
U
T
__
and the last expression can be rearranged to:
I
0
= I
S
exp
_
U
BE1
U
T
__
1 + exp
_
U
BE2
U
BE1
U
T
__
According to 3.3 the rst term of the last equation is equal to the emitter current of
the rst transistor and in the last term, the difference of the base emitter voltages
may be expressed by the difference voltage U
d
. As a result we get for the emitter
current I
E1
:
I
E1
=
I
0
1 + exp
_

U
d
U
T
_
By analogy one can deduce the equivalent equation for the emitter current I
E2
.
I
E2
=
I
0
1 + exp
_
U
d
U
T
_
65
Since we have I
C1
= I
E1
and I
C2
= I
E2
we get for both collector currents:
I
C1
=
I
0
1 + exp
_

U
d
U
T
_ and I
C2
=
I
0
1 + exp
_
U
d
U
T
_ (3.42)
Fig. 3.22 shows the normalised collector currents as a function of the applied
difference voltage U
d
. According to Fig. 3.22 for a zero difference voltage the
5 4 3 2 1 0 1 2 3 4 5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
I
C
/
(


I
0
)



U
d
/U
T

I
C1
I
C2
Figure 3.22: Normalised collector currents as function of the applied difference
voltage
differential amplier is in balance and the total current I
0
is equally distributed
on both transistors. For a positive difference voltage transistor 1 becomes more
conductive carrying more current, while the conduction of transistor 2 is reduced.
Similarly for a negative difference voltage the current I
0
is steered more towards
transistor 2 while now the conduction of transistor 1 is reduced.
To deduce an expression for the voltage U
To
we use KVL and apply it to the
top mesh of the circuit shown Fig. 3.21:
U
To
= R
C
(I
C1
I
C2
)
66
With the help of equation 3.42 we can rewrite the equation above as:
U
To
= R
C
I
0
_

_
1
1 + exp
_

U
d
U
T
_
1
1 + exp
_
U
d
U
T
_
_

_
Using the denitions of the functions cosh(x) and sinh(x), the last expression can
be manipulated to:
U
To
= R
C
I
0
sinh
_
U
d
U
T
_
1 + cosh
_
U
d
U
T
_ (3.43)
Fig. 3.23 shows the normalised output voltage as function of the difference volt-
age U
d
. For a difference input voltage U
d
< 2U
T
50mV we have an almost
8 6 4 2 0 2 4 6 8
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
U
o
u
t
/
(
R
C


I
0
)



U
d
/U
T

Figure 3.23: Normalised output voltage as function of the difference voltage
linear dependence of the output voltage on U
d
. But as the difference voltage in-
creases the ouput voltage will reach a saturation value of R
C
I
0
. Of course this
value may not become larger than the supply voltage U
0
, which can be used to get
a relation between the current I
0
and the value of R
C
.
R
C
I
0
< U
0
R
C
<
U
0
I
0
67
Small Signal Gain
As already mentioned above, for low values of the difference input voltage U
d
the differential amplier behaves linear and can be described by the differential
voltage gain v
d
. Approximation of equation 3.43 yields:
U
To

R
C
I
0
2U
T
U
d
v
d
=
R
C
I
0
2U
T

R
C
I
0
2U
T
(3.44)
Using the deduced relation above for R
C
we nd
v
d
<
U
0
2U
T
(3.45)
With the last equation we found an upper limit for the attainable differential volt-
age gain of a single stage BJT differential amplier with a resistive load. It is
interesting to notice that this limit is essentially independent of the used BJT as
long as its current gain is sufciently high and that it depends strongly on the
used level of supply voltage.
Realizing a Simple Current Source
The simplest way to realize the current source of the differential amplier is shown
in Fig. 3.24. Here the ideal current source is just replaced by the resistor R
0
. To


r
r
r rr
r
R
0
r
R
C
r
R
C
r r


r
r
r
r
r r

r r r r
r

U
2o
r

U
1o

U
0
U
0
U
n
U
p
U
To

I
E2

I
E1

I
0
Figure 3.24: Differential amplier with a resitor used as current source
understand why this resistor acts like a current source, one should again consider
68
Fig. 3.23 which showed that already a very small differential voltage U
d
is suf-
cient to drive the output voltage into the region of saturation. On the other hand
this implies that the voltage level of the base of the transistors is very close to
the ground level and as a result the voltage drop across the current source will
be equal to the supply voltage U
0
. Applying these considerations to the circuit
shown in Fig. 3.24 gives the following approximation between the current I
0
and
the resistor R
0
.
I
0

U
0
R
0
(3.46)
Common Mode Rejection
A differential amplier should only respond to the difference between the input
signals U
d
. But of course the input signal U
p
and U
n
can also show a common
mode voltage U
c
, dened as:
U
c
=
1
2
(U
p
+ U
n
) (3.47)
As a consequence there may also exist a common mode gain v
cm
, dened by
v
cm
=
U
out
U
c
(3.48)
Considering the circuit according to Fig. 3.24 an increase in common mode volt-
age U
c
will result in a change of the current thru the resistor R
0
:
I
0
=
U
c
R
0
Assuming an operation near the balance point of the amplier, both collector cur-
rents will increase
I
c
=
I
0
2
=
U
c
2R
0
Now one must distinguish between two cases:
1. In a double-ended output dened by the voltage U
To
, given that the circuit
is truly symmetrical, both collector currents will alter by the same amount
and the differential ouput voltage will still be zero and no common-mode
gain will occur.
2. In a single-ended mode, dened by the output voltages U
1o
or U
2o
there is
an ouput response and for the common-mode gain we will get:
|v
cm
| =
U
1o
U
c
=
R
c
2R
0
(3.49)
69
A useful gure of merit for the differencing performance of the differential am-
plier may be dened as the ratio of differential voltage gain v
d
to common-mode
gain v
cm
. This is called the common-mode rejection ratio (CMRR). With the help
of equations 3.44 and 3.49.
CMRR =
v
cm
v
d
=
2U
T
R
0
I
0
(3.50)
3.3.2 Current Sources
Current sources are very important electronic circuits providing for example bi-
asing functions such as the current source of a differential amplier. According
to the simple large signal equivalent circuit shown in Fig. 3.7 a BJT essentially
acts like a current source, with the advantage of the current being adjustable by
the base current. Thus in principle the constant base voltage circuit with current
feedback shown in Fig. 3.15 can also be used to realise the current source of a
differential amplier as shown in Fig. 3.25a, which can be used to replace the
resistor. Of course the voltage U
CE
of the BJT may not drop below approximately
R
E
rr
R
1
r
R
2
r r

-U
0
I
0

U
CE
r
r


r
r
r
r


r
rr
r
r
R
r
r
rr r

I
0

I
1
-U
0

2I
B
Figure 3.25: Single BJT as current source and current mirror
0.7 V, which is the onset of saturation. The advantage of the BJT as current source,
is its higher ouput resistance, when compared to the single resistor. But with the
expense of using three additional resistors, which will be a severe drawback for
the realisation as integrated circuit. A circuit to overcome these problems is shown
in Fig. 3.25b. It is called current mirror. In contrast to the previous circuit here
only one resistor is needed to dene the current I
0
. A further advantage of the
integrated version of the circuit is that both BJTs may be realised in close vicinity,
so that process variations will not cause severe differences between the transistors
and on the other hand they will be closely related in temperature so that thermal
70
tracking will take place. If we assume strictly equal transistors with a static cur-
rent gain
0
, we will have the following relation between the currents I
0
and I
1
,
which shows that for high static current gain both currents are almost identical.
I
0
=

0

0
+ 2
I
1
(3.51)
3.3.3 Active Load
A further step in reducing the number of passive components in a differential

T 3
r
r

T 4
r
r
r
rr r
r
r


T 1
r
r


T 2
r
r r
rrr
r

U
0
Figure 3.26: Differential amplier with current mirror as active load
amplier is to replace the resistors R
C
by a pnp current mirror as shown in Fig.
3.26, which is called active load. This load circuit is very economical in area
since T1 provides the current I
1
for the current mirror and no resistors are used.
By using an active load, a high-impedance ouput load can be realized without
excessively large resitors and hence large power-supply voltage. As a result, for a
given power-supply voltage, a larger voltage gain can be achieved using an active
load than would be possible, if a resistor would be used as load. For example, if a
50 k load would be used with a bias current of 1 mA, a resistive-load approach
would require a power-supply voltage of at least 50 V. An active load makes use
of the possibilities of a transitor to create simultaneously a large bias current and
a large small-signal output resistance r
CE
.
3.3.4 Level-Shifting Circuits
Despite using circuit techniques which avoid the use of high-valued decoupling
capacitors, there still remains the problem of coupling one circuit to another. Of
71
course direct coupling between amplier stages removes the requirement for cou-
pling capacitors but it is difcult because of the different DC-levels. So DC level-
shifting circuits must be introduced. In principle the DC level may be shifted by
using an ideal voltage source and due to its zero internal resistance no AC-signal
attentuation would occur. In section 2.2 we already studied how to use normal
diodes to stabilize an ouput voltage. Figure 3.27a shows the principle layout of

r
r
r
n

r
r
r
r

r r r r
r r


r
rr
r

R
2
r
R
1
r rr
r
r r r r
r r

u
in
u
out
u
in
u
out
Figure 3.27: Level-shifting circuit with diodes and an amplied diode
a circuit to shift the DC level by an integer number times the threshold voltage
U
th
0.7 V of a diode. Using KVL we nd for the ouput voltage of the rst
circuit:
u
out
(t) u
in
(t) nU
th
To deduce an expression for the second circuit we must rst consider the circuit
consisting of the two resistors and the transistor. Assuming a transistor with a high
current gain
0
the current I
T
thru the voltage divider R
1
and R
2
will not change
and we will have:
U
R2
= U
BE
= R
2
I
T
U
R1
= R
1
I
T
=
R
1
R
2
U
BE
So, we get for the total voltage across the voltage divider and hence across the
transistor U
CE
U
CE
=
_
1 +
R
1
R
2
_
U
BE
(3.52)
Which can be adjusted to be a non-integer fraction of the diode voltage U
BE
and
is thus called amplied diode. With the help of the last equation we nd for the
output voltage of the circuit with amplied diode:
u
out
(t) = u
in
(t)
_
1 +
R
1
R
2
_
U
BE
(3.53)
72
3.3.5 Complementary Output Stage
In Fig. 3.28 the circuit schematic of a complementary emitter-follower output
stage is shown. In contrast to the input stages of an operational amplier the output


R
L
U
0
U
0
U
in

U
out
r
r
r
r r
Figure 3.28: Complementary emitter-follower output stage
stage must be able to drive other circuits and so the main emphasis does not lie on
the voltage gain of the stage but on the current the stage is able to deliver to the
circuits to be driven. As already discussed in section 3.2.2 an emitter follower has
a voltage gain of nearly one but a high current gain and provides a small output
resistance. In contrast to the conventional emitter-follower, the transistors shown
in Fig. 3.28 will only amplify on half of the sine wave. So the npn transistor will
only conduct for a positive signal, while the pnp transistor will only contact for a
negative signal.
73
Chapter 4
Field-Effect Transistors and their
Applications
4.1 Junction Field-Effect Transistor
Today eld-effect transistors (FET, Field Effect Transistor) of different construc-
tion are used. In principle in all FETs the resistance of a channel between the
contacts Source and Drain is inuenced by the potential between the Gate
and Source electrode. The working principles were already proposed by Julius
Lilienfeld in 1926, but not until the late fties, the rst working devices could
be produced. At that time the material processing technology had evolved and
the treatment of the semiconductor surface was by then so well-understood to cir-
cumvent its realisation difculties. In contrast to the bipolar junction transistor
the operation principle of a FET is based only on the carriers dening the con-
ductivity of the channel. Thus the FET is called to be an unipolar device and its
operation does not depend on the recombination of electrons and holes, making it
a fast device especially suited also for rf- and microwave applications.
4.1.1 Cross-Section and Static IU-Characteristic of a JFET
Fig.4.1 shows a cross-sectional view of a JFET, which is realised using metalor-
ganic vapour epitaxy. First on an almost non-conducting substrate a 1 2 m
thick buffer-layer is grown being sligthly p-conducting. It is followed by the n-
conducting channel with a thickness of 100 nm and a donator concentration of
approximately N
D
= 5 10
17
cm
3
. The top layer used for contacting shows a
thickness of 30 nm and a donator concentration of N
D
= 2 10
18
cm
3
. The con-
tacts of the Source and the Drain to the semiconductor material must show ohmic
behaviour, while the Gate electrode forms a Schottky-contact with the top layer.
74

s
s
s

cover layer 30nm


channel layer 100nm
buffer layer
12m
GaAs substrate
500m
U
GS
U
DS
S
G
D
Figure 4.1: Cross-sectional view of JFET
As a result, a depletion-layer is formed beneath the gate-electrode while its width
may be changed by applying a negative Gate-Source-voltage (U
GS
< 0). Under
normal operation condition a positive voltage between drain and source is applied
(U
DS
>0) resulting in a constant current for a xed gate-source-voltage. Using the
gate-source voltage to change the effective channel width will result in a change
of current form the drain to the source. In contrast to the BJT, the drain-source
current may be changed only by the applied gate voltage, while essentially no
gate currents are present and thus the JFET current may be controlled without
power. After discussing the behaviour of the JFET on a more qualitative base we
s
s s

U
GS
U
DS

I
D

x
y

w(y)

U
x
(y)

U
y
(y)


d
L
Figure 4.2: JFET-model to deduce the static IU-characteristic
will now follow [?], [?] and use Fig. 4.2 to deduce a quantitative model of its
behaviour. Again Fig. 4.2 shows a cross-sectional view of the controlable section
of the channel. It has a total thickness d, which is assumed to be much smaller
75
than the channel length L, which possesses a width b perpendicular to the shown
cross-section. Due to the applied gate voltage the depletion-layer will show a
width w(y), which will seperate the channel into two sections. In the lower re-
gion the applied voltage U
DS
will result in a channel current, while in the upper
region the depletion-layer exists. To proceed in our considerations we will make
the following assumptions:
In the current carrying part of the channel an electric eld in the y-direction
will essentially exist, resulting in a voltage U
y
(y).
In the depletion layer an electric eld in x-direction will exist, described by
a voltage U
x
(y), which will essentially determine the width of the depletion
layer w(y).
The electrons carrying the current in the channel will not reach their satura-
tion drift velocity.
To start with our considerations, we again have a look at Fig. 4.2 which shows
the cross-section of cuboid of length dy at an arbitrary point y inside the channel.
Using Ohms law one can determine the voltage drop dU
y
due to the drain current
I
D
and the resistance of that small part of the channel dR.
dU
y
= dRI
D
=
I
D
b[d w(y)]
dy (4.1)
According to section ?? the depletion width of a Schottky-contact behaves like
pn-junction (equ. 2.14). Thus we get for the width of the depletion layer w(y).
w(y) =
_
2
eN
D
(U
D
U
x
(y)) = d

2
eN
D
d
2
[U
D
U
GS
+U
y
(y)] (4.2)
In the last equation KVL was used to give the voltage U
x
(y) in dependence of the
voltage U
GS
and U
y
(y).
U
x
(y) =U
GS
U
y
(y)
According to equation 4.2 the factor 2/(eN
D
d
2
) possesses the dimension of a
reciprocal voltage. If this value is reached, the width of the depletion layer w(y)
is equal to the thickness of the total channel. One says that the channel is pinched
off and one can introduce the so-called pinch-off voltage U
p
by:
U
p
=
eN
D
d
2
2
(4.3)
76
Example: Pinch-off voltage of the channel according to Fig. 4.1
N
D
= 510
17
cm
3
, d =100 nm,
r
= 10, 9
U
p
= 4, 14 V
Using the expression for the width of the depletion-layer in equation 4.1 we will
nd the following differential form
dU
y
=
I
D
dy
bd
_
1

U
D
U
GS
+U
y
(y)
U
p
_
which may be integrated by separation of variables:

U
DS
0
_
1

U
D
U
GS
+U
y
U
p
_
dU
y
=

L
0
I
D
bd
dy
As a result of the integration one gets the static current characteristic of the drain-
current as function of the gate-source-voltage U
GS
and the drain-source-voltage
U
DS
I
D
= G
o
_
U
DS

2
3
U
p
_
(
U
D
U
GS
+U
DS
U
p
)
3/2
(
U
D
U
GS
U
p
)
3/2
__
(4.4)
In equation 4.4 the conductance G
o
of the open channel was introduced.
G
o
=
bd
L
=
e
n
N
D
bd
L
(4.5)
Example: Conductance of the open channel
N
D
= 510
17
cm
3
, d =100 nm,
n
= 3, 500 cm
2
/Vs, b = 240 m, L = 1, 0 m
G
o
= 0, 67 S
According to equation 4.2 the width of the depletion-layer will increase with in-
creasing voltage U
y
(y). As a result the cross-section of the channel will become
narrower approching the drain contact. But since the current thru the channel re-
mains constant, the velocity of the electrons must increase inside the channel next
to the drain contact. At the end they may not exceed the saturation drift velocity,
which is a constant of the used material. As a result the drain current essentially
will be independed form the drain source voltage. According to [] in this satura-
tion region we will have the following dependence of the drain current I
D
on the
gate voltage U
GS
.
I
D
= I
Ds
_
1
U
GS
U
P
_
2
(4.6)
77
The constant I
Ds
is called drain saturation current. For a real JFET one will notice
that the drain current will not be totaly independent on the drain source voltage,
but will slightly increase. To describe this effect the last equation must be modied
to:
I
D
= I
Ds
_
1
U
GS
U
P
_
2
(1 + U
DS
) (4.7)
where a further parameter is introduced called channel length modulation pa-
rameter.
4.1.2 Small Signal Equivalent Circuit of a JFET
To use a JFET as active device to amplify sinusoidal signals one has to establish
a point of operation, analogous to a BJT. Fig. 4.3 shows a possible circuit and
the output characteristic of the JFET. With the help of the voltage source U
GS
a
certain IU-characteristic of the JFET can be chosen, while in the ouput circuit the
following equation must hold true.
U
DS
=U
o
R
L
I
D
Since the static IU-characteristic as well as the last equation must be fullled the
operation point denoted with OP will be established with a certain drain current I
D
and a certain drain source voltage U
DS
. For the following considerations we want
to assume that the amplitudes of the time functions u
GS
(t), u
DS
(t) and i
D
(t) are
small compared to the point of operation. To calculate the small signal amplitude

U
GS
u
GS
(t)
R
L
U
o

U
DS
I
D
U
o
U
o
/R
L
s
s
OP

U
GS
>

I
D
Figure 4.3: Principle circuit to establish an operation point

i
D
of the drain current we develop the output characteristic of the JFET with the
help of a Taylor series:

i
D

I
D
U
GS
|
OP

U
GS
+
I
D
U
DS
|
OP

U
DS
(4.8)
78
The change of drain current I
D
due to a change in gate voltage U
GS
in the point of
operation is called transconductance g
0
of the transistor.
g
0
=
I
D
U
GS
|
U
DS
=konst.
According to equation 4.6 we nd
g
0
=
2
|U
P
|

I
Ds
I
D
(4.9)
The change of drain current I
D
due to a change in drain source voltage U
DS
is
called output conductance of the transistor at the given operation point.
g
DS
=
I
D
U
DS
|
U
GS
=konst.
Using equation 4.7 we nd
g
DS
= I
Ds
_
1
U
GS
U
P
_
2
I
D
(4.10)
Fig. 4.4 shows the small signal equivalent circuit of the JFET in a common source
conguration. Since the pn-junction of the transistor is reverse biased it possesses
essentially no input conductance.

s
s s s
s s
s

u
GS
(t) g
DS
R
L

g
o
u
GS
(t)

u
DS
(t)
s
JFET
Figure 4.4: Low-frequency small signal equivalent circuit of a JFET
Example: Comparing the transconductance of a BJT and a JFET
Values: g
0
=80 mS, g
DS
=8 mS, R
L
= 125

U
DS
=
g
o

U
GS
(g
DS
+1/R
L
)

v =

U
DS

U
GS
=
g
o
(g
DS
+1/R
L
)
=5
79
4.1.3 SPICE Model of a JFET
Fig. 4.5 shows the large-signal SPICE model of a n-channel JFET [3]. The dy-
namic behaviour of a JFET is modeled by two depletion capacitances C
GS
and
C
GD
of the two reverse-biased pn-junctions. Additionally the resistors R
D
and R
S
are included to describe the ohmic character of the contacts and the semiconduc-
tor resistance. The current of the current source is given by equation 4.7, where
r r
R
S
r
C
GS
r

r
rr r

r r

r
rr r
I
D
r
C
GD
rr r
R
D
r r r r r r
r
r
S D
G
Figure 4.5: SPICE model of a n-channel JFET
instead of I
Ds
the transconductance parameter is used.
=
I
Ds
U
2
p
(4.11)
In the following table the model parameters of a JFET are summarised.
Name Parameter def. Value Unit
VTO pinch-off voltage -2.0 V
BETA Transconductance parameter 10
4
AV
2
LAMBDA Channel length modulation parameter 0.0 V

1
RD Drain ohmic resistance 0.0
RS Source ohmic resistance 0.0
CGS Zero-bias GS junction capacitance 0.0 F
CGD Zero-bias GD junction capacitance 0.0 F
PB Gate junction potential 1.0 V
IS Gate junction saturation current 10
14
A
Table 4.1: SPICE JFET model parameters
80
SPICE data set:
************************************************************
.MODEL BF245A NJF(
+ VTO = -1.7372E+000 BETA = 1.16621E-003 LAMBDA = 1.77211E-002
+ RD = 9.01678E+000 RS = 9.01678E+000 IS = 2.91797E-016
+ CGS = 2.20000E-012 CGD = 2.20000E-012 PB = 7.80988E-001
+ FC = 5.00000E-001)
************************************************************
4.1.4 Common-Source small Signal Amplier with a JFET
In contrast to the circuit shown in Fig. 4.4 the circuit schematic given in Fig.
4.6 shows a common-source amplier where the DC voltage U
GS
is realised by a
source resistance R
S
. To discuss the operation principle of this circuit we apply
r
r
rr
r
R
S
r r r
r
R
1
r
r
C
S
r
r r
C
1
r r
r r r rr r
r
R
D
r
r r
C
2
r rr
r
R
L
r

U
in

U
out
U
0
Figure 4.6: Common-source amplier with a JFET
KVL to the DC input circuit.
U
R
1
+ U
GS
+ R
S
I
D
= 0
Of course the last equation may be resolved for the gate-source voltage U
GS
.
U
GS
= R
S
I
D
+ U
R
1
According to the last equation, switching on the circuit will result in a drain cur-
rent I
D
and as a result in a negative gate-source voltage U
GS
. Thus the gate-source
diode will be reverse biased and essentially no gate-source current will exist. So,
81
even for very high values of the resistance R
1
the voltage U
R
1
will be zero and the
gate-source voltage will be given by:
U
GS
= R
S
I
D
(4.12)
Using high frequencies all capacitors may be considered to be a short circuit
and we reach the small-signal equivalnet circuit of the common-source amplier
shown in Fig. 4.7
r r r

g
0
U
GS
r
r r
r
r
r
DS
r r
r r
r
r
R
D
r r
r r r
R
L
r r
r r r r
r r r
r
R
1

U
in
U
GS
U
out
Figure 4.7: Small signal equivalent circuit of a common-source amplier
Input Resistance r
in
From Fig. 4.7 it is obvious that the input resistance is given by:
r
in
= R
1
(4.13)
Comparing this with the input resistance of a common-emitter BJT amplier this
value is considerabl higher, because one can choose the resistance R
1
in the M
range.
Output Resistance r
out
According to Fig.4.7 the output resistance is given by the parallel connection of
r
DS
and R
D
, and thus essentially dependend on the point of operation.
r
out
=
r
DS
R
D
r
DS
+ R
D
(4.14)
Voltage Gain v
u
The voltage gain of the common-source circuit is dened by the ratio of the output
voltage U
out
to the input voltage U
in
. With the help of Fig. 4.7 we nd:
v
u
=
r
out
R
L
r
out
+ R
L
g
0
(4.15)
82
Choosing the Values of the Capacitors
All capacitors included in the common-source amplier given in Fig. 4.6 will con-
tribute to its highpass character as already discussed in the case of the common-
emitter amplier. We will now introduce a lower cut-off frequency f
low
again
againabove which the amplier should work. Again, instead of a rigorous treat-
ment we will discuss the inuence of each capacitor separately in a more heuristic
manner.
Capacitor C
S
The purpose of this capacitor is to reduce the inuence of the
resistor R
S
on the AC gain of the amplier. Since it is connected in parallel to the
resistor, with increasing frequency the total reactance will become smaller and
smaller and for high frequencies there will exist no current feedback at all. So the
following relation must hold true
1
2f
low
C
S
R
S
which gives a lower limit how to chose the value of C
S
.
C
S

1
2f
low
R
S
(4.16)
Capacitor C
1
If the capacitor C
S
is chosen high enough, the resistors R
G
of the
generator, r
in
of the amplier and the capacitor C
1
will form a rst order high-pass
lter. Its corner frequency f
c
being given by:
f
c
=
1
2C
1
(R
G
+r
in
)
Since in the case of the JFET amplier the input resistance will be very high,
usually the resistance of the generator may be neglected. Choosing the corner fre-
quency equal to the lower frequency limit f
low
gives a lower limit for the capacitor
C
1
C
1

1
2 f
low
R
1
(4.17)
Capacitor C
2
The capacitor C
2
in the ouput circuit is equivalent to the capacitor
C
1
in the input circuit. Thus it will also form a rst order high-pass lter with the
resistors r
out
and R
L
. So we get an equivalent lower limit for its value in analogy
to the limit of capacitor C
1
.
C
2

1
2 f
low
(r
out
+R
L
)
(4.18)
83
Example: Common-source amplier with the JFET BF245A
Data: U
0
= 12V, U
DS
= 5V, I
D
= 2mA, R
1
= 1M
From equation 4.11 we nd the drain saturation current I
Ds
I
Ds
= U
2
p
= 3.5mA
and with the help of equation 4.6 we can approximately calculate the necessary
gate source voltage to reach a DC drain current of 2mA.
U
GS
= U
p
_
1
_
I
D
I
Ds
_
= 0.43V
Using 4.12 we now can determine the resistance of R
S
,
R
S
=
U
GS
I
D
200
and with the help of a voltage loop we can set up an equation to nd the value of
R
D
R
D
=
U
0
U
DS
U
Rs
I
D
3.3k
Now all resistors to establish the chosen point of operation are determined and we
can calculate the transconductance g
0
according to equation 4.9
g
0
=
2
1.74V

3.5 2.0 mA = 3.04 mS


Assuming the load resistance R
L
to be equal to the resistance of R
D
and neglecting
g
DS
we now can also calculate the expected voltage gain of the amplier.
v
u
=1.65k3.04mS = 4.95
Comparing the result above the voltage gain of the common-emitter stage con-
sidered in section ?? shows that the amplier using a BJT has a 20 times higher
voltage gain under almost the same conditions of operation. Of course the input
resistance of the JFET-stage is much higher. Using the equations 4.16 to 4.34 and
f
low
= 50 Hz, we nd for the capacitors
C
S
15.9F C
S
= 1.6mF
C
1
3.18nF C
1
= 5nF
C
2
0.48F C
2
= 1F
84
Figure 4.8: Simulated frequency response of the common-source small signal
amplier
To verify the prediction above of the gain and the values of the chosen capacitors
Fig. 4.8 shows the simulated frequency response of the common-source amplier
with the JFET BF254A. The source amplitude was set to be 1mV. With the help
of the marker function we can read out an output amplitude of 13.8dBmV, which
corresponds to an absolute value of a voltage gain of 4.89, which is very close to
the predicted value. The 3 dB cut-off frequency of the highpass can be read out
to be approximately 50Hz, which is equal to the envisaged lower frequency limit.
It is interesting to notice the limitation of the gain at higher frequencies predicted
by the simulation. Of course the SPICE model of the JFET is far more elaborated
than the simple small signal model of Fig. 4.4 and the internal capacitances of
the transistor will limit the frequency range of operation and result in a low-pass
characteristic for high frequencies. If one would like to use the ampier as the in-
put stage of an audio amplier, one should reduce the cut-off frequency to lower
values using additional capacitors in the circuit.
85
4.2 Metal-Oxide Semiconductor Field-Effect Tran-
sistor (MOSFET)
Today MOSFETs are the dominant type of transistor and they are currently used
to make most electronic integrated circuits (ICs). The structure of this class of
transistors is based on three layers: metal, oxide, and a semiconductor.
4.2.1 N-Channel MOSFET
Fig. 4.9 shows a cross-sectional viewof a so-called n-channel enhancement MOS-
FET. As in the case of a JFET the terminals of the MOSFET are called source,
source drain
gate
p-substrate
n
+
n
+
Figure 4.9: Cross-section of a n-channel MOSFET
gate and drain. In this structure the gate electrode is not connected to the semi-
conductor, but the metal of the eletrode is isolated by a thin layer of SiO
2
with
a typical thickness of 0.01 m to 0.03 m. Today instead of metal electrodes,
polysilicon gates are used because polysilicon allows the dimensions of the tran-
sistor to be realized much more accurately during the patterning of the transistor.
In contrast the source and drain electrodes form ohmic contacts to the two n
+
-type
semiconductor islands in the p-substrate. If one would apply a voltage between
the drain and source electrode no current would result. This is because in principle
the structure is equivalent to two pn-junctions connceted in series which work in
opposite directions. This situation may be changed, if a positive voltage is applied
to the gate with respect to the source. If the voltage is high enough, the free elec-
trons, which even exist in a p-conductor, are attracted and may form a thin layer
next to the surface of the p-conducting substrate. This thin n-conducting layer
is called channel and will connect the island of the drain contact to the source
contact. As a result an applied voltage between drain und source will result in
a current thru the induced channel. This kind of transistor is called n-channel
enhancement MOSFET, because the channel has to be created by a positive gate-
source voltage. The minimum voltage necessary to create the connecting channel
is called threshold voltage U
th
. So, if a positive voltage U
DS
is applied between
source and drain, with the help of the gate-source voltage U
GS
the drain source
86
current I
D
may be controlled. For voltages U
GS
< U
th
there will exist essentially
no drain current I
D
while the drain current will increase for voltages U
GS
>U
th
. It
is also possible to build a n-channel transistor where the channel already exists for
a zero gate-source voltage. This type is called depletion n-channel MOSFET. To
stop the current ow between drain and source the gate-source voltage has to be-
come negative. Fig. 4.10 shows different symbols commonly used to represent n-
Figure 4.10: Symbols of n-channel MOSFETs
G
S
D
a)
G
S
B
D
b)
G
S
D
c)
G
S
B
D
d)
channel MOSFETs. Both Fig. 4.10a and 4.10b represent n-channel enhancement
transistors. The transistor shown in 4.10b possesses an additional terminal called
substrate or bulk. For single transistors this terminal is connected to the source
contact. In digital integrated circuits it is normally connected to the ground. The
symbols shown in Fig 4.10c and 4.10d are used to represent n-channel depletion
MOSFETs.
4.2.2 P-Channel MOSFET
If one uses a n-type subtrate with p-type islands for the source and drain contact,
as shown in Fig. 4.11 one has again realized a transistor, but now a p-channel en-
hancement MOSFET. Again, if no voltage is applied between the gate and source
source drain
gate
n-substrate
p
+
p
+
Figure 4.11: Cross section of a p-channel enhancement MOSFET
contact, the structure behaves like two back-to-back connected diodes. Despite
the polarity of the applied voltage between the drain and source contact no drain
current will ow. To change the situation, a negative gate source voltage must
87
be applied. If this voltage is high enough a conducting p-type channel may be
induced next to the surface of the substrate. In most cases there is no physical
difference between the drain and the source. In a p-channel transistor the source
terminal will always be the terminal with the higher potential. Also in case of a
p-channel transistor it is possible to build transistors where a p-channel already ex-
ists for a zero gate source voltage. These transistors are of the deleption type and
a positive gate-source voltage has to be applied to turn off the conducting chan-
nel. Fig. 4.12 shows the different symbols commonly used to represent p-channel
Figure 4.12: Symbols of p-channel MOSFETs
G
S
D
a)
G
S
B
D
b)
G
S
D
c)
G
S
B
D
d)
MOSFETs of the enhancement type (a,b) and the depletion type (c,d).
4.2.3 Static Characteristics of a n-Channel Enhancement MOS-
FET
In the following section we will discuss the basic operation with respect to a n-
channel MOSFET. To dene important MOSFET parameters Fig. 4.13 gives the
dimensions normally used to specify a MOS transistor. As was already discussed
L
Gate
tox
W
Figure 4.13: Basic parameters of a MOS transistor
in the previous section, the positive gate source voltage is used to induce a n-
conducting channel next to the surface of the semiconductor, with free electrons.
88
According to [2] we will assume that the density of electrons Q
n
will be propor-
tional to the difference between the gate-source voltage U
GS
and the threshold
voltage U
th
Q
n
= C
ox
(U
GS
U
th
) (4.19)
The introduced constant C
ox
is the gate capacitance per unit area and is given by:
C
ox
=

rox

0
t
ox
(4.20)
If we use a parallel plate capacitor as approximation. In this equation
rox
denotes
the relative permittivity of SiO
2
while t
ox
is the thickness of the the oxide sepa-
rating the gate from the substrate. An applied a drain-source voltage U
DS
across
the channel will now result in a drain current I
D
, which will be proportional to the
electric eld inside the channel U
DS
/L, the charge density Q
n
, the width W of the
channel, and the electron mobility
n
near the silicon surface.
I
D
=
n
Q
n
W
U
DS
L
(4.21)
With the help of equation 4.19 we can rewrite the last equation as:
I
D
=
n
C
ox
W
L
(U
GS
U
th
)U
DS
(4.22)
It should be emphasized that equation 4.22 is only valid for small drain source
voltages as long as there exists an almost homogenous channel. With increasing
drain-source voltage, the gate-to-channel voltage at the drain end will decrease
resulting in a smaller charge density. As a result the current will no longer be
proportional to U
DS
but will atten for larger U
DS
values. According to [2] this
will result in the following equation:
I
D
=
n
C
ox
W
L
_
(U
GS
U
th
)U
DS

U
2
DS
2
_
(4.23)
This part of the I
D
-characteristic is called Triode region. As already mentioned
above for high drain-source voltages U
DS
the charge density on the drain side of
the transistor becomes smaller and smaller. Thus to hold the current I
D
constant
the velocity of the carriers must increase at the drain end, reaching the drift ve-
locity saturation. Even a further increase in drain-source voltage will no longer
result in a higher drain current. Now the saturation region is reached and the
drain current will no longer be a function of the drain-source voltage. According
to equation 4.23 saturation will occur for U
DS
= U
GS
U
th
and in the region of
saturation the drain current will be given by:
I
D
=

n
C
ox
2
W
L
(U
GS
U
th
)
2
(4.24)
89
Comparing experimental results with equation 4.24 shows that even in the satu-
ration region there is a slight increase of drain current when increasing the drain-
source voltage. This phenomenon is called channel-length modulation [2] and can
be described by introducing an addional term to equation 4.24.
I
D
=

n
C
ox
2
W
L
(U
GS
U
th
)
2
(1 + U
DS
) (4.25)
The parameter is called channel-lentgh modulation parameter.
4.2.4 Small Signal Equivalent Circuit of a n-Channel MOS-
FET
To use a MOSFET as an active device to amplify sinusoidal signals one has to
establish a point of operation in the saturation region, analogous to the circuit
with a JFET already shown in Fig. 4.3. Again a DC voltage source U
GS
may be
used to select a certain I
D
of the output characteristic. To allow voltage changes
U
DS
in the ouput circuit a load resistance R
L
has to be used in series with the
DC power supply U
0
. As result a DC operation point OP will be established
with a quiescent drain current I
D
and a certain drain source voltage U
DS
. For
the following considerations we want to assume that the amplitudes of the time
functions u
GS
(t), u
DS
(t) and i
D
(t) are small compared to the values in the point
of operation. To calculate the small signal amplitude

i
D
of the drain current we
develop the output characteristic of the MOSFET with the help of a Taylor series:

i
D

I
D
U
GS
|
OP

U
GS
+
I
D
U
DS
|
OP

U
DS
(4.26)
The change of drain current I
D
due to a change in gate voltage U
GS
in the point of
operation is called transconductance g
0
of the transistor.
g
0
=
I
D
U
GS
|
U
DS
=konst.
According to equation 4.25 we nd
g
0
=
n
C
ox
W
L
(U
GS
U
TH
) (4.27)
The change of drain current I
D
due to a change in drain source voltage U
DS
is
called ouput conductance of the transistor at a given operation point:
g
DS
=
I
D
U
DS
|
U
GS
=konst.
90
Again using equation 4.25 we nd
g
DS
=

n
C
ox
2
W
L
(U
GS
U
th
)
2
I
D
(4.28)
Fig. 4.14 shows the low-frequency small signal equivalent circuit of the MOSFET
in a common source conguration.

s
s s s
s s
s

u
GS
(t) g
DS

g
o
u
GS
(t)
u
DS
(t)
s
Figure 4.14: Low-frequency small signal equivalent circuit of a MOSFET
4.2.5 SPICE Model of a MOSFET
Fig. 4.15 shows the large-signal SPICE model of a MOSFET [3]. The dynamic
behaviour of a MOSFET is modeled by the two ordinary capacitances C
GS
and
r
C
GS

r
C
GD

r
r
r
r
r
r rr rr
r r
I
D

rr rr rr r r
r
C
BS
C
BD

r
r
C
GB
r r
R
D
r r
R
S
G
D S
B
Figure 4.15: SPICE model of MOSFET
C
GD
between the gate, the inner source and the drain contact. Further the two nor-
mally reverse biased pn-junctions between the inner source or drain are included
91
to the bulk contact as well as the assoiciated depletion capacitances C
BS
and C
BD
.
Additionally the resistors R
D
and R
S
are included to describe the ohmic character
of the contacts and semiconductor materials and a capacitance between the gate
and bulk contact. The current of the current source is given by equation 4.25,
where depending on the used model level [3]. The transconductance parameter
is alos introduced.
=
n
C
ox
W
L
(4.29)
In the following table important model parameters of a MOSFET are summarised.
Name Parameter def. Value Unit
VTO Threshold voltage 0.0 V
KP Transconductance parameter 2.0 10
5
AV
2
LAMBDA Channel length modulation parameter 0.0 V

1
GAMMA Bulk threshold parameter 0.0 V
0.5
PHI Surface potential 0.6 V
RD Drain ohmic resistance 0.0
RS Source ohmic resistance 0.0
RSH D and S diffusion sheet resistance 0.0 /sq
CGS Zero-bias GS junction capacitance 0.0 F
CGD Zero-bias GD junction capacitance 0.0 F
CJ Zero-bias bulk junction bottom capacitance 0.0 F
PB Gate junction potential 1.0 V
IS Gate junction saturation current 10
14
A
Table 4.2: SPICE MOSFET model parameters
4.2.6 Common-Source Small Signal Amplier with a n-Channel
MOSFET
The circuit schematic given in Fig. 4.16 shows a common-source amplier with
a n-channel MOSFET where the DC voltage U
GS
is realized using a gate voltage
divider. Due to the threshold voltage U
th
a positive U
GS
>U
th
has to be realized.
Of course in contrast to a BJT a MOSFET has an almost innite input resistance
and under these circumtances resistances in the M-range may be used to set up
the appropriate voltage divider with resistors R
1
and R
2
. Using high frequencies
all capacitors may be considered to be a short circuit and we reach the small-signal
equivalent circuit of the common-source MOS amplier shown in Fig. 4.17
92
Figure 4.16: Common-source amplier with a n-channel MOSFET
r r r

g
0
U
GS
r
r r
r
r
r
DS
r r
r r
r
r
R
D
r r
r r r
R
L
r r
r r r r
r r r
r
R
1

U
in
U
GS
U
out
Figure 4.17: Small signal equivalent circuit of a common-source MOS amplier
Input Resistance r
in
From Fig. 4.17 it is obvious that the input resistance is given by:
r
in
=
R
1
R
2
R
1
+ R
2
(4.30)
Comparing this with the input resistance of a common-emitter BJT amplier this
value is considerabl higher, because the resistances R
1
and R
2
may be chosen in
the M range.
Output Resistance r
out
According to Fig.4.17 the output resistance is given by the parallel connection of
r
DS
and R
D
, and thus essentially depends on the point of operation due to R
D
and
U
0
.
r
out
=
r
DS
R
D
r
DS
+ R
D
(4.31)
93
Voltage Gain v
u
The voltage gain of the common-source circuit is dened by the ratio of the output
voltage U
out
to the input voltage U
in
. With the help of Fig. 4.17 we nd:
v
u
=
r
out
R
L
r
out
+ R
L
g
0
(4.32)
Choosing the Values of the Capacitors
All capacitors included in the common-source amplier given in Fig. 4.16 will
contribute to its highpass character as already discussed in case of the common-
emitter amplier. We will now introduce a lower cut-off frequency f
low
again
above which the amplier should work. Again, instead of a rigorous treatment we
will discuss the inuence of each capacitor separately in a more heuristic manner.
Capacitor C
1
The resistors R
G
of the generator, r
in
of the amplier and the
capacitor C
1
will form a rst order high-pass lter. Its corner frequency f
c
being
given by:
f
c
=
1
2C
1
(R
G
+r
in
)
Since in case of the MOS amplier the input resistance will be very high, usually
the resistance of the generator may be neglected. Choosing the corner frequency
equal to the lower frequency limit f
low
gives a lower limit for the capacitor C
1
C
1

1
2 f
low
r
in
(4.33)
Capacitor C
2
The capacitor C
2
in the ouput circuit is equivalent to the capacitor
C
1
in the input circuit. Thus it will also form a rst order high-pass lter with the
resistors r
out
and R
L
. So we get an equivalent lower limit for its value in analogy
to the limit of capacitor C
1
.
C
2

1
2 f
low
(r
out
+R
L
)
(4.34)
94
Chapter 5
Operational Ampliers and their
Applications
The operational amplier is one of the basic elements used in analog and mixed
signal circuits. As we already saw in section 3.3 an operational amplier consists
of stages with different purpose which are DC coupled, but it is rather complex.
So it is normally described by so-called macro modells instead of considering its
real internal circuitry.
5.1 Basic Linear Model of an Operational Amplier
In Fig. 5.1 a simple basic linear model is shown to be capable of approximating
its electric behaviour for a lot of applications. As a differential amplier it has two

R
D
+

R
out

U
P
U
D
U
N
V U
D
U
out
r
r
r r
r

r
Figure 5.1: Basic linear macro model of an operational amplier
inputs. An inverting input with the applied voltage U
N
and a non-inverting input,
95
to witch the voltage U
P
is applied. The voltage between the non-inverting and
inverting input is called difference voltage U
D
. In the simple model the resistor R
D
describes the load seen by the difference voltage and hence is called differential
input resistance. The capability of the op-amp to amplify signals is described by
a voltage controlled voltage source to which a frequency dependend differential
voltage gain V( j) is assigned. In the basic model the frequency dependence is
described by a rst-order lowpass transfer function,
V( j) =
V
0
1+ j( f /f
c
)
(5.1)
in which V
0
denotes the open loop voltage gain at DC and f
c
denes the cut-off
frequency of the transfer function. The parameter R
out
approximates the output
resistance of the op-amp. In table 5.1 ranges for the parameter values of a real
real op-amp ideal op-amp
R
D
2 ... 10 M
R
out
100...500 0
V
0
10
4
...10
6

f
g
10Hz...100Hz
Table 5.1: Parameter values of a real and ideal op-amp
op-amp are given. For comparsion the equivalent values for an ideal op-amp are
given in the second row. If we have a look at the parameters of table 5.1 it is quite
obvious, that especially the cut-off frequency f
g
is far below its ideal value. This
is because manufactures introduce a dominate pole into the transfer function of
a real op-amp with the help of a capacitor. If they would not do this, the cut-off
frequency would be determined by all transistors of the circuit leading to a higher
order transfer function and also being the cause for instabilities for a wired op-
amp. Often in the data sheet not the cut-off frequency of the op-amp is given but
its gain-bandwidth product (GBP). It describes the gain behaviour of the op-amp
with frequency. Due to the introduced dominant pole the gain-bandwith product
of an op-amp is constant [] and if we assume a certain gain G of a wired op-amp,
we will get for its cut-off frequency f

g
.
f

g
=
GBP
G
(5.2)
96
5.2 Basic Linear Op-Amp Circuits
To deduce the electric behaviour of the following circuits we will always assume
to use an ideal op-amp which is described by the parameters already given in table
5.1.
5.2.1 Inverting Amplier
Fig. 5.2 shows the circuit schematic of an inverting amplier, which we now will
analyse using direct voltages and currents. It consists of an op-amp and a two

I
f
R
f

I
1
R
1

U
1
U
out
r
r r
r
r r
Figure 5.2: Circuit schematic of an inverting amplier
resistor network. With the help of resistor R
f
a fraction of the output voltage U
out
is fed back to the inverting input thus realizing a negative feedback. The resistor
R
1
must be used to decouple the input voltage U
1
from the inverting input. The
non-inverting input is directly connected to the ground. Assuming an ideal op-
amp we can conclude that for a nite output voltage U
out
the difference voltage
U
D
at the input must approach zero since we have an innite voltage gain V
0
.
U
D
=
1
V
0
U
out
0
Sometimes it is said that the inverting input of the op-amp is a virtual ground.
Furthermore the input current into the op-amp must also approach zero, since we
assume an innte input resistance R
D
, leading to the following node equation at
the input of the op-amp:
I
1
+ I
f
= 0
Applying KVL to the input and the output mesh yields,
U
1
R
1
+
U
out
R
f
= 0
97
and we nd for the voltage gain v of the inverting amplier:
v =
U
out
U
1
=
R
f
R
1
(5.3)
It is interesting to notice that the closed loop gain of a wired ideal op-amp only
depends on the external elements.
Phasor Analysis
Instead of using direct voltages and currents we can also use sinusoidal voltages
which are described by phasors, and instead of assuming the resistors to be real,
they may be replaced by impedances with complex values. So we can use the
following correspondence between real and complex values:
U
1
U
1
U
out
U
out
R
f
Z
f
R
1
Z
1
Using phasors we nd for the transfer function of an inverting amplier, which
will now be of course a function of the frequency:
v( j) =
Z
f
( j)
Z
1
( j)
(5.4)
5.2.2 Inverting summing amplier
The circuit of 5.2 can easily be extended to an inverting summing amplier as
shown in Fig. 5.3 Instead of only using one input, now inputs U
1
to U
N
are used
R
f

R
1
R
2
R
N
U
1
U
2
U
N
U
out
r
r r
r r
r
r
r
r
r
r
Figure 5.3: Circuit schematic of a summing amplier
with the resistors R
1
to R
N
. Again assuming an ideal op-amp, with virtual ground
at the inverting input, will lead to the following equation:
I
1
+ I
2
+ . . . + I
N
= 0
98
Using KVL we nd:
U
1
R
1
+
U
2
R
2
+ . . . +
U
out
R
f
= 0
Finally we get for the ouput voltage U
out
in dependence of the input voltages U
i
:
U
out
=
_
R
f
R
1
U
1
+
R
f
R
2
U
2
+ . . . +
R
f
R
N
U
N
_
(5.5)
5.2.3 Non-Inverting Amplier
One disadvantage of the inverting amplier shown in Fig. 5.2 is its low input
resistance when compared to that of a real op-amp. Since the inverting input is
virtually connected to the ground the input resistance of the inverting amplier is
equal to R
1
, which is usually considerabl lower than R
D
of a real op-amp. A circuit
which overcomes this disadvantage is shown if Fig. 5.6. The input voltage U
1
of

R
f
R
1

U
1
U
out
r
r
r
r
r r
Figure 5.4: Circuit schematic of a non-inverting amplier
this circuit is connected to the non-inverting input, while the negative feedback is
realized by the resistors R
f
and R
1
. Assuming an ideal op-amp, the voltage across
the resistor R
1
will be equal to the input voltage U
1
, while the output voltage U
out
drops across the series connection of the resistors R
f
and R
1
. Since no current will
ow into the op-amp, we have:
U
1
R
1
=
U
out
R
f
+ R
1
Hence we get for the overall voltage gain v of the non-inverting amplier:
v = 1 +
R
f
R
1
(5.6)
99
Since in this circuit the voltage U
1
is directly applied to the non-inverting input,
the input resistance R
in
is essentially given by the differential input resistance of
the used op-amp.
R
in
R
D
(5.7)
A special realisation of the non-inverting amplier with R
f
= 0 and R
1
is
shown in Fig. 5.5. It is called voltage follower because according to equation 5.6


U
1
U
out
r r
r
r r
Figure 5.5: Circuit schematic of a voltage follower
the ouput voltage will be equal to the input voltage. This circuit can be used as
buffer amplier to eliminate loading effects and hence can be used to connect a
device with high output impedance to a device with low input impedance.
5.2.4 Inverting Integrator
Fig. 5.6 shows the Circuit schematic of an inverting integrator. To understand its
behaviour we will rst study it in the time domain, assuming an ideal op-amp.

i
C
R

i
R

u
1
(t)
u
out
(t)
r
r r
r
r r
Figure 5.6: Circuit schematic of an inverting integrator
Due to the negative feed back we again assume the difference voltage u
D
to be
zero and the current thru the resistor and capacitor must be equal since no current
will ow into the op-amp.
i
R
(t) + i
C
(t) = 0
100
In dependence of the voltages the last equation reads,
u
1
(t)
R
+ C
du
out
(t)
dt
= 0
and solving for the time function of the output voltage u
out
(t) yields:
u
out
(t) =
1
RC

t
0
u
1
(t)dt with u
out
(t = 0) = 0 (5.8)
To reach equation 5.8 we assumed the integration to start at t = 0 and the voltage
of the capacitor to be zero at the starting point.
Phasor Analysis
With the help of equation 5.8 one can determine the output voltage u
out
for arbi-
trary time functions of input voltages u
1
(t). In electrical engineering one often
deals with sinusoidal time functions which are represented by phasors. So, in the
following section we will discuss the inverting integrator and its transfer function
in the frequency domain. Of course the equations discussed in the previous sec-
tion also hold true for phasors and we can setup the node equation at the inverting
input of the op-amp.
I
R
+ I
C
= 0
Using phasor notation, the differentiation in time domain changes into a multipli-
cation with j in the frequency domain, thus we get as equation for the phasors
of the voltage,
U
1
R
+ jCU
out
= 0
which results in the following transfer function of the inverting integrator:
v( j) =
U
out
U
1
=
1
jRC
(5.9)
If we introduce

0
= 1/RC (5.10)
we can rewrite the equation above in the following form:
v( j) = j

0

(5.11)
Example: Inverting integrator with the following values R= 1 kund C= 159 nF.
According to equation 5.10 we get for the characteristic frequency of the integra-
tor:

0
=
1
1 10
3
159 10
6
s
= 6.28 10
3
1
s
101
Figure 5.7: Transfer function the integrator
According to transfer function given in equation 5.11 it will show a value of zero
dB at its characteristic frequency ( f
0
= 1 kHz), which is conrmed by the tranfer
function shown in Fig. 5.7.
5.2.5 Inverting Differentiator
The circuit schematic of an inverting differentiator is shown in Fig. 5.8. Again

i
C
R
i
R

u
1
u
out
r
r
r
r
r
r
Figure 5.8: Circuit schematic of an inverting differentiator
we rst want to study its electric behaviour in the time domain and start with the
102
node equation at the inverting input of the op-amp:
i
C
(t) + i
R
(t) = 0
In dependence of the input voltage u
1
(t) and the output voltage u
out
(t) the last
equation reads:
C
d u
1
dt
+
u
out
R
= 0
Rearranging the last equation yields for the output voltage u
out
of the inverting
integrator:
u
out
= RC
d u
1
dt
(5.12)
Phasor Analysis
We will now perform the phasor analysis of the inverting integrator, replacing the
arbitrary time functions by sinusoidal time function, represented by their pahsors.
Starting again with the node equation yields,
I
C
+ I
R
= 0
or expressed with phasors of the voltages,
jCU
1
+
U
out
R
= 0
which results in the following transfer function for the inverting differentiator:
v( j) =
U
out
U
1
= jRC (5.13)
If we again introduce
0
to be equal to 1/RC, we can rewrite the transfer function
in the following form:
v( j) = j

0
(5.14)
In contrast to the transfer function of the inverting integrator (equ. 5.11) the trans-
fer function of the inverting differentiator formed with an ideal op-amp predicts
according to equation 5.14, an increasing voltage gain |v( j)| with increasing fre-
quency. If we consider to have a real op-amp this is not possible due to its nte
GBP.
Example Inverting differentiator with the following values:
103
5.2.6 First-Order Low-Pass Filter
Fig. 5.9 shows a further circuit with an op-amp, which forms an active rst-order
low-pass lter. To calculate its transfer function and hence its frequency response,

R
1
R
2
C

U
1
U
out
r
r
r
r r
r
r r
Figure 5.9: Circuit schematic of a rst-order low-pass lter
we use equation 5.4 for the inverting ampier wired with complex impedances.
According to Fig. 5.9 the impedances Z
1
and Z
f
are given by the following equa-
tions:
Z
1
= R
1
and Z
f
=
1
1
R
2
+ jC
This results in the following transfer function:
v( j) =
R
2
R
1
1
1 + jR
2
C
(5.15)
104
Comparing the last equation to the normalised transfer function of a rst-oder low
pass lter,
v( j) =
v
0
1 + j

0
(5.16)
we nd for the parameters:
v
0
=
R
2
R
1
and
0
=
1
R
2
C
(5.17)
Example: Active rst-order low-pass lter
|v
0
| = 10 and f
0
= 3.4kHz
According to equation 5.17 we have to determine three values but only two equa-
tions. This opens us the possibility to choose one element free. If we for exmaple
choose R
1
to be 1 k, which would determine the input resistance of the low-pass
lter, we get for the remaining elements:
R
2
= 10 k and C = 4.7 nF
Fig. 5.10 shows the Bode plot of the transfer function. For low frequency the
transfer function shows a gain of 20dB, which corresponds to its linear value of
10. With the help of the marker one reads out a value of approximately 17.1dB at a
frequency of 3.3kHz, which is slightly lower than the proposed cut-off frequency
of 3.4kHz
5.2.7 Second-Order Low-Pass Filter
Fig. 5.11 shows a possible circuit to realise a second-order low-pass lter using
only a single op-amp but multiple feedback. Analysing the network using the
approximation of an ideal op-amp will result in the following transfer function.
v( j) =
R
4
R
1
1 + j
C
5
(G
1
+G
3
+G
4
)
G
4
+G
3

2
C
5
C
2
R
3
R
4
(5.18)
If we compare the last equation with the normalised transfer function of a second-
order low-pass lter,
v( j) =
v
0
1 + j2tan()

0
_
2
(5.19)
105
Figure 5.10: Transfer function a rst-order low-pass lter
we nd the folowing values for the parameters of the second-order low-pass:
v
0
=
R
4
R
1

0
=
1
_
C
2
C
5
R
3
R
4
tan() =
1
2
_
C
5
C
2
_
(v
0
+ 1)
_
R
3
R
4
+
_
R
4
R
3
_
The normalised transfer function of the second-order low-pass lter can be speci-
ed by three independent parameters. On the other hand, the circuit shown in Fig.
5.11 needs ve component values to be specied, which offers us a certain degree
of exiblity. In a rst step it appears to be useful to dene the capacitance C
2
in
dependence of the capacitance C
5
, by introducing a new parameter k,
C
2
= k C
5
which will lead to the fowolling equation:
_
R
4
R
3
=
0
C
5

kR
4
With the help of the last equation we nd for resistor R
4
:
R
4
=
tan()

0
C
5
_
1

1
v
0
+1
ktan()
_
(5.20)
106
C
5
R
3
R
4
R
1

C
2

U
1
U
out
r
r r r
r r
r r
Figure 5.11: Circuit schematic of a second-order low-pass lter
Equation 5.20 can only give a valid value of the resistance of R
4
as long as the
term unter the square root is positive, leading to an additional requirement:
k
v
0
+1
tan()
(5.21)
Choosing an appropriate value for k opens the possibility to determine the resistors
R
3
and R
1
.
R
3
=
1
k(
0
C
5
)
2
R
4
R
1
=
R
4
v
0
(5.22)
Example: Active second-order low-pass lter with the following parameters:
f
0
= 3.4 kHz, tan() =0.707 and v
0
= 10.
According to equation 5.21 k must fulll the following relation:
k
11
0.707
= 15.6
Of course there is still a high degree of freedom to choose the value of C
5
, but
according to equation 5.20 the resistance of R
4
and the impedance of C
5
will
range in the same order of magnitude. Choosing C
5
to be 4nF and the k factor to
be 20 ( C
2
= 80nF) yields for the resistance of R
4
R
4
=
0.707
23.510
3
410
9

_
1 +
_
1
11
20 0.707
_
= 11.8k
As a consequence we get for the resistors R
3
and R
1
:
R
3
=
1
20(23, 510
3
410
9
)
2
11, 810
3
= 548
107
R
1
=
11.8
10
k = 1.18k
108
5.3 Basic Non-Linear Op-Amp Circuits
So far we studied op-amp circuits with negative feedback ensuring to operate the
amplier in the linear part of its transfer function. As a result the difference volt-
age U
D
of the op-amp always approaches zero. In the follwing circuits we will
also use the non-linear part of the transfer function of an op-amp as shown in Fig.
5.12. The output voltages of the op-amp in the saturation regions we will denote
0
U_oL

0

U_oH
U
o
u
t


U
D

real
ideal
Figure 5.12: Non-linear transfer function of an ideal and real op-amp
by the voltages U
oH
and U
oL
as also shown in Fig. 5.12. In case of an ideal op-amp
its transfer function may be described by the following equation:
U
out
=
_
U
oH
for U
D
> 0
U
oL
for U
D
< 0
(5.23)
5.3.1 Op-Amp as Comparator
Fig. 5.13 shows a basic circuit where an op-amp is used to compare the input
voltage U
in
with a reference voltage U
re f
. According to KVL we nd for the
difference voltage of the op-amp,
U
D
= U
re f
U
in
and hence for the non-linear transfer function of the comparator:
U
out
=
_
U
oH
for U
in
< U
re f
U
oL
for U
in
> U
re f
(5.24)
109

U
in
U
re f
U
D
U
out

r
r
r r
Figure 5.13: Comparator realized with an op-amp
Fig. 5.14 shows the static non-linear transfer function according to equation 5.24
assuming an ideal op-amp. Of course in practice the op-amp will not have an

U
in
U
out
U
oH
U
re f
U
0L
Figure 5.14: Nonlinear tranfer function of the comparator
innite voltage gain and thus the change from one state to the other will depend
on the time dependence of the input signal. The situation may be even worse if
a noise signal is super impossed upon the input signal causing multiple switching
of the comparator between the output stages.
5.3.2 Schmitt Trigger Realised with an Op-Amp
A circuit to circumvent drawbacks of a comparator is shown in Fig. 5.15. It is
called Schmitt trigger. Again two resistors R
2
and R
1
are used to realize a feeback
from the ouput to the input. But in contrast to the inverting amplier shown in
Fig. 5.2, in case of a Schmitt trigger, a part of the ouput signal is fed to the non-
inverting input, resulting in a positive feedback. To discuss the consequence of a
positive fed back, we rst consider the input signal U
in
to be zero. Hence we have
the following relation between the ouput voltage U
out
and the difference voltage
110
R
2
R
1

U
in
U
out
U
D
r
r r
r
r r
Figure 5.15: Schmitt trigger realized using an op-amp
U
D
.
U
D
=
R
1
R
2
+ R
1
U
out
Hence, a positive output voltage will result in a nite positive difference voltage
and a negative output voltage will result in a nite negative difference voltage U
D
.
According to the non-linear transfer function given in Fig. 5.12 the ouput voltage
U
out
will either show the value U
oH
or U
oL
depending on the history of the circuit.
But due to the positive feeback this value will be stable, as long as the difference
voltage does not change. To deduce the transfer characteristic of a Schmitt trigger,
we now again set up the equation for the difference voltage, assuming a non-zero
input voltage U
in
:
U
D
=
R
1
R
2
+ R
1
U
out
U
in
(5.25)
As already discussed in the preceeding section, the ouput voltage will either show
the value U
oH
or U
oL
depending on the history of the circuit. As a result we have
to consider two different cases:
1. U
out
= U
oH
The transition to the state U
out
= U
oL
will only occur for U
D
<0. According
to equation 5.25 we have:
U
D
< 0 U
1
>
R
1
R
2
+ R
1
U
oH
(5.26)
2. U
out
= U
oL
The transition to the state U
out
= U
oH
will only occur for U
D
> 0. Accord-
ing to equation 5.25 we have:
U
D
< 0 U
1
<
R
1
R
2
+ R
1
U
oL
(5.27)
111
The transfer function according to equations 5.26 and 5.27 is shown in Fig. 5.16.
First we a assume the Schmitt trigger to be in the state U
out
=U
oH
and the input

U
in
U
out

U
oH
U
0L
Figure 5.16: Transfer function of an inerting Schmitt trigger
voltage to show a large negative value. According to equation 5.25 the difference
voltage will be positive and the Schmitt trigger remains in this state. If the input
voltage is increased, the Schmitt trigger will remain in its state as long as equation
5.26 is not fullled. But as soon as the voltage U
1
exceeds the value
R
1
R
2
+R
1
U
oH
the
Schmitt trigger will switch to the state U
out
=U
oL
and remain in this state while
U
1
is further increased. Decreasing the input voltage from large positive values
will at rst not change its stage. But the transition to the state U
out
= U
oH
will
occur when equation 5.27 is fullled resulting in the shown hysteresis loop of the
transfer function. The width U
in
of the hysteresis loop is given by the following
equation:
U
in
=
R
1
R
2
+ R
1
(U
oH
U
oL
) (5.28)
Schmitt Trigger with Shifted Hysteresis Loop
If the values U
oH
and U
oL
show the same absolute values, the hysteresis loop
of the realized Schmitt trigger will be symmetrically placed to the origin of the
coordinate system as shown in Fig. 5.16. But sometimes it is desirable to shift the
center of the hysteresis loop by a certain amount. A circuit capable to do this is
shown in Fig. 5.17. The only difference to the circuit shown in Fig. 5.15 is the
additional included source U
s
. So equation 5.25 will change to:
U
D
=
R
1
R
2
+ R
1
U
out
+
R
2
R
2
+ R
1
U
s
U
in
(5.29)
Again we have to consider two different cases:
112
R
2
R
1

U
in
U
out
U
s

U
D
r
r

r
r
r
r
Figure 5.17: Schmitt trigger with shifet hysteresis loop
1. U
out
= U
oH
The transition to the state U
out
= U
oL
will only occur for U
D
<0. According
to equation ?? we have:
U
D
< 0 U
1
>
R
1
R
2
+ R
1
U
oH
+
R
2
R
2
+ R
1
U
s
(5.30)
2. U
out
= U
oL
The transition to the state U
out
= U
oH
will only occur for U
D
> 0. Accord-
ing to equation 5.25 we have:
U
D
< 0 U
1
<
R
1
R
2
+ R
1
U
oL
+
R
2
R
2
+ R
1
U
s
(5.31)
Comparing equations 5.30 and 5.31 with equations 5.26 and 5.27 shows that both
transition points are shifted by the voltage
R
2
R
2
+R
1
U
s
resulting in a total shift of the
transfer function, while the width of the hysteresis loop is still given by equation
5.28.
5.4 Digital-to-Analog Converter (DAC)
Today most of our information is stored as combination of digital numbers. Es-
pecially in case of a signal its amplitude can be given by a number represented as
a binary word of nte length. To make it easier we will start our considerations
with a binary word of length four, which we use to represent a number z:
z = a
3
2
3
+ a
2
2
2
+ a
1
2
1
+ a
0
2
0
with a
n
[0, 1]
The coefcients a
n
are called the bits of the binary word, which can only have
the values 0 or 1. In our simple case the element a
0
is called Least Signicant Bit
113
(LSB) while the element a
3
is called Most Sigincant Bit (MSB). So with the help
of a four bit word we can reperesent the numbers z = 0 (0000) to z = 15 (1111).
Extending the representation given above to an arbitrary number N of bits yields
for the represented number:
z =
N1

i=0
a
i
2
i
(5.32)
So, with a binary word of length N the numbers 0 to 2
N
1 may be represented.
After digital signal processing the binary word must be again converted to voltage
amplitude in most cases . In the following subsections we will discuss different
circuit capable to solve this task.
5.4.1 Op-Amp Summer as DAC
Fig. 5.18 shows a DAC circuit for a four bit word realized using essentially an
op-amp summer circuit. For the node equation at the inverting input we nd:
R/2
2
1
R
2
0
R
2
2
R
2
3
R


U
re f
U
out
r r
r r
r
r
r
r
r
r
a
3
r

a
2
r

r
a
1
r

r
a
0
r

r
Figure 5.18: DAC realized with an op-amp summer circuit
_
a
3
2
0
R
+
a
2
2
1
R
+
a
1
2
2
R
+
a
0
2
3
R
_
U
re f
+
2U
out
R
= 0
Which yields the following equation for the output voltage U
out
in dependence of
the digital number z and the reference voltage:
U
out
=
1
2
4
_
2
3
a
3
+ 2
2
a
2
+ 2
1
a
1
+ 2
0
a
0
_
U
re f
U
out
=
z
2
4
U
re f
(5.33)
114
Equation 5.33 describes the electric behaviour of the circuit shown in Fig. 5.18,
which results in a certain mapping of a four bit binary number z to an output volt-
age U
out
. One essential drawback of the circuit is the wide variation of resistors to
be realized, which restricts its application to DAC with only few binary digits.
5.4.2 DAC with R-2R-Ladder Network
Fig. 5.19 shows a so-called R-2R-ladder network. The ladder portrayal comes
from the ladder-like topology of the network. To understand its electrical charac-
R
2R
r

U
1

2R
R
2R
r

U
2

R
2R
r

U
3

2R

U
0

U
oc
r r
r
Figure 5.19: R-2R-ladder network
teristic we rst calculate the equivalent circuit seen into the rst stage. According
to the theorem of Thevenin it shows the following values of an open circuit voltage
U
oc
and an input resistance R
i
:
U
oc
=
1
2
U
0
R
i
= R
If we now add the second stage and calculate again the open circuit voltage and
input resistance we get:
U
oc
=
1
2
U
1
+
1
4
U
0
R
i
= R
According to the last equation the input resitance of an N-stage R-2R-ladder net-
work will always be equal to R while we get for the open circuit voltage:
U
oc
=
1
2
U
N1
+
1
2
N1
U
1
+
1
2
N
U
0
(5.34)
Assuming each voltage source to show the same value U
re f
and to be switched on
or off by a bit a
n
we get for the source voltage n:
U
n
= a
n
U
re f
115
The equation for the open circuit voltage of the R-2R-Ladder network can be
rewriten as:
U
oc
=
1
2
N
_
2
N1
a
n1
+ 2
1
a
1
+ 2
0
a
0
_
U
re f
=
z
2
N
U
re f
(5.35)
Voltage-Switched R-2R DAC
2R

a
0
R
2R

a
1
R
2R

a
2
R
2R

a
3

U
out

U
re f
r
r
r
r
r
r
r
r
r r
r r r r r r
r
r
r
r
r
r
Figure 5.20: DAC using a R-2R- ladder network and a voltage follower
Fig. 5.20 shows the circuit schematic of a four bit DAC using a R-2R-ladder
network and a voltage follower to decouple the ladder network and realize a low
output resistance. In contrast to the circuit with an op-amp summer, only two
different values of resistors have to be realized, which simplies its realisation.
On the other hand, due to the switching process the reference voltage has differ-
ent loads depening on the digital word to be converted and the single nodes of
the network must change their potential resulting in a certain cut-off frequency
depending on the parasetic capacitances of the network.
Current-Switched R-2R DAC
To discuss the current-switched R-2R DAC we again consider a R-2R-ladder net-
work this time driven by a current source as shown in Fig. 5.21. Due to the fact
that the input resistance of each single stage of the ladder network will be 2R the
current at the input of the stage will always split into two equal parts and with
reference to Fig. 5.21 the following relations will hold true:
I
0
=
1
2
I
1
I
1
=
1
2
I
2
I
n1
=
1
2
I
n
(5.36)
116
R
2R
R
2R
2R
2R
R
2R
I
0

I
1

I
2

I
3

I
4
r r r r

Figure 5.21: R-2R-ladder network driven by a current source


2R

a
1
R
2R

a
2
R
2R

a
3
2R

2R

a
0
R
R

U
re f
I
0
I
1
I
2
I
3
U
out
r
r
r
r
r
r
r r r r r r
r
r
r
r
r r
r
r
r
r
r
Figure 5.22: R-2R-ladder network driven by a current source
The circuit shown in Fig.5.22 uses this behaviour to set up a different kind of
DAC. In contrast to the previous one the currents are switched between the virtual
ground of the op-amp and the real ground. The current source of Fig. 5.21 is
replaced by a voltage source. Independend on the stage of the applied binary
word the current I
4
fed into the ladder network will be equal to:
I
4
=
U
re f
R
According to KCL applied to the node at the inverting input of the op-amp we get:
a
0
I
0
+ a
1
I
1
+ a
2
I
2
+ a
3
I
3
+
U
out
R
= 0
I
4
_
1
2
4
a
0
+
1
2
3
a
1
+
1
2
2
a
2
+
1
2
1
a
3
_
+
U
out
R
= 0
U
re f
2
4
R
_
2
0
a
0
+ 2
1
a
1
+ 2
2
a
2
+ 2
3
a
3
_
+
U
out
R
= 0
117
Using the last result we get for the output voltage of a current-switched DAC of
N stages with the binary digit z as input:
U
out
=
z
2
N
U
re f
(5.37)
5.5 Analog-to-Digital Converter (DAC)
Today communication systems in most cases use digital signal processing to per-
form certain operations on the signal e.g. to lter it. But in most cases the original
signal is an analog amplitude and time continuous signal normally represented by
a voltage u
in
(t), which has to be converted to an amplitude and time discrete sig-
nal x
q
(nT
s
). As is shown in the block diagram of Fig. 5.23 this is essentially done
by a three step process. In a rst step, the analog input signal is lowpass ltered to
u
in
(t)

u
SH
(nT
s
)

x
q
(nT
s
)
LPF
f
c
S/H Quantizer

f
s
=
1
T
s
2f
c
Figure 5.23: Block diagram of a DAC
limit its bandwidth according to Nyquists theorem []. In the second step samples
are taken at certain time instants with a sample and hold circuit (S/H). After this
process we still have an amplitude continuous but time discrete voltage u
SH
(nT
s
).
In the last step a quantizer maps the sample value to the nearest discrete value in a
u
in
(t)
u
SH
(nT
s
)
x
q
(nT
s
)
t
Figure 5.24: Time functions and quatum levels of a ADC
118
set of quantum levels. Fig 5.24 shows an example of the different time functions
and quantum levels involved in the analog-to-digital conversion. Of course this
is only possible if the amplitude of the input signal u
in
(t) is restricted to a certain
interval [U
min
,U
max
]. Its absolute range is called full scale range (FSR).
FSR = |U
max
U
min
| (5.38)
If the quantizer has a resolution of N bit we get for a single quantum step:
U
q
=
FSR
2
N
(5.39)
5.5.1 Quantization Error
To discuss the quantisation error its is convenient to introduce a normalised input
signal x
in
, which is restricted to the interval [0,1]. If we assume an input volt-
age u
in
out of the interval [U
min
,U
max
], the normalised input signal x
in
may be
calculated by:
x
in
=
u
in
U
min
FSR
(5.40)
If we now assume the quantizer has a to have a resolution of N bit a single nor-
malised quantum step has a height of:
q =
1
2
N
(5.41)
Fig. 5.25 shows the ideal transfer function of a 3bit ADC (step function) com-
0 1/4 1/2 3/4 1
001
011
101
111
x
in

Figure 5.25: Transfer function of a 3bit ADC
pared to the transfer function of an ADC with innite resolution (straight line).
The quantization error is now dened as the difference between the two transfer
functions. According to Fig. 5.25 we have:

1
2
q
1
2
q (5.42)
119
Quantization noise
To deduce an expression for the signal-to-noise ratio of an ADC we will make the
following assumptions:
The quantization errors
k
of all samples are uncorrelated
The quantization error is equally distributed in the interval given in equation
5.42.
With the assumptions above and the common property of an arbitrary propability
density function p()

p()d =

1/2q
1/2q
p()d = 1
we nd for the propability density function (PDF) of an ADC:
p() =
1
q
for
1
2
q
1
2
q (5.43)
Using the PDF dened above we nd for the mean square value of the quantization
error:
<
2
> =

1/2q
1/2q
1
q
d =
q
2
12
(5.44)
In principle <
2
> is equivalent to the noise power in a communication system.
If we assume to feed a sinusoidal time function into the ADC, the normalised
amplitude

X
in
may in maximum be equal to 0.5. Thus we get for the equivalent
signal power S:
S =
1
2

X
2
in
=
1
8
As a result we get for the Signal-to-Noise ratio (SNR)
S
<
2
>
=
3
2q
2
=
3
2
2
2N
and for its value in dB:
SNR
dB
= 20log(
3
2
2
2N
) = 6.02 N + 1.76 (5.45)
According to equation 5.45 an ideal ADC with a resolution of N-bit shows a max-
imum SNR of approximately 6NdB.
Example: Which resolution is need to reach the SNR of a CD ( 95dB ).
N
95
6
16
120
5.5.2 ADC Realizations
Flash ADC
Fig. 5.26 shows the circuit of a 2 bit ash ADC. With a 2 bit word one can

R/2

R
R
R
Encoder
U
re f
U
in
a
1
a
0
r
r
r r
r
r r
r
r
Figure 5.26: Circuit schematic of a 2 bit ash ADC
distinguish between four different voltages. This is done with the three op-amps
which are connected to three different voltage levels, established with the help of
the resistors connected in series. As soon as the difference voltage at the input
of the op-amp becomes positive its output voltage swings to the high state. So
with increasing input voltage the number of comparators showing a high level
output signal increases. This is called thermometer code and an encoder must be
used to create the appropriate two bit combination a
1
, a
0
at the output . Due to its
hardware structure a ash ADC is very fast, but also very hardware expensive. For
a N bit conversion a ash ADC needs 2
N
1 op-amps and 2
N
resistors. The size
and the cost of the op-amps make a ash ADC impractical for precisions greater
than 8 bits.
Pipeline ADC
To circumvent the problems occuring with ash ADC with high bit resolution one
can cascade ADCs as shown in Fig. 5.27. The shown circuit consists of two 3 bit
ADCs and one DAC. With the help of the rst ADC the 3 highest bit values are
121
ADC
DAC
MSB
ADC
LSB
U
in
2
3
Stage
Figure 5.27: Principle circuit of two cascaded ash ADCs
extracted and the DAC is used to realize a corresponding analog signal, which is
substracted from the orginal input signal. Now a gain stage is used to amplify the
reduced input signal by a factor of 2
3
and the second ADC is used to extract the
remaining 3 Bits. In Fig. 5.27 the shadowed area denes one stage of 3-Bit ADC.
In principle stages of this kind may be cascaded to form for example a 12-bit
pipeline ADC as shown in Fig. 5.28.
1.Stage 2.Stage 3.Stage 4.Stage
MSB
LSB
U
in
Figure 5.28: Principle circuit of a 12-bit pipeline ADC
122
Bibliography
[1] Jackson J.D.: Classical Electrodynamics, John Wiley & Sons, New York,
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