A 4bit * 4bits booth-encoded Wallace tree multiplier are implemented in verilog to demonstrate the proposed multiplier.

The figure below is the wallace tree part of the multiplier.

According to the figure above, the wallace tree only need 18 adders (15 Fulladders and 3 Half-adders). The typical array multiplier might need 64 Adders for signed multiplication. This is can have substantially area-saving.

Booth_encoder Verilog_code Partial product generator Verilog_code Wallace tree Verilog_code 4*4 multiplier Verilog_code simulation