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I HC QUC GIA THNH PH H CH MINH

TRNG I HC BCH KHOA


KHOA KHOA HC V K THUT MY TNH
------oOo-----

THC HNH
THIT K MCH S VI HDL

TP.HCM, 9-2009

Gii thiu
B ti liu thc hnh thit kt mch s vi HDL c son tho nhm mc ch h
tr cc bn sinh vin trong vic tip xc vi ngn ng c t phn cng. M c th l h
tr cho mn hc thit kt mch s vi HDL.
Ti liu ny bao gm 9 bi, tng ng vi 9 bui. Ni dung chu yu hng n
vic hc t duy thit kt phn cng. Gip sinh vin luyn tp cc k nng lp trnh vi
Verilog, m phng trn Model Sim hay trc tip trn board DE2.
Mc d rt c gng nhng cng khng th trnh khi nhng sai st. V vy rt
mong nhn c kin ng gp t pha bn c hoc cc bn sinh vin.
Chn thnh cm n!
TP.HCM, ngy 27thng 9 nm 2009

Mc lc

Bui 1.
Tng quan v cc phn mm thit k trn FPGA ....................................... 7
I. Gii thiu Board DE2 ca Altera ............................................................................. 7
1.
Gii thiu .......................................................................................................... 7
2.
Thnh phn ....................................................................................................... 7
3.
Mt vi ng dng ca board DE2 .................................................................... 8
II. Cch ci t Quartus II 8.0 v Nios II ..................................................................... 9
1.
Gii thiu .......................................................................................................... 9
2.
Ci t ............................................................................................................. 10
III. Cch np chng trnh cho Quartus II 8.0: ............................................................ 13
1.
To 1 project: .................................................................................................. 13
2.
Vit chng trnh v bin dch: ...................................................................... 17
3.
To file m phng (simulate) v bt u simulate ......................................... 22
4.
Cu hnh chn v np ln board...................................................................... 30
Bui 2.
Mch t hp v mch tun t...................................................................... 40
I. Gii thiu ............................................................................................................... 40
1.
Gii thiu ........................................................................................................ 40
2.
Hng dn thit k FPGA thng qua s khi/Schematic .......................... 40
II. Bi tp .................................................................................................................... 46
Bui 3.
Lp trnh Verilog vi m hnh cu trc ..................................................... 48
I. Gii thiu ModelSim ............................................................................................. 48
1.
Gii thiu ........................................................................................................ 48
2.
Ci t ............................................................................................................. 48
3.
Hng dn ...................................................................................................... 58
II. Bi tp .................................................................................................................... 65
Bui 4.
M hnh hnh vi ............................................................................................ 67
I. Bi tp .................................................................................................................... 67
Bui 5.
M hnh hnh vi (tt)...................................................................................... 71
I. Bi tp .................................................................................................................... 71
Bui 6.
My trng thi .............................................................................................. 75
I. Gii thiu ............................................................................................................... 75
1.
Gii thiu ........................................................................................................ 75
2.
Hng dn ...................................................................................................... 75
II. Bi tp .................................................................................................................... 83

Mc lc hnh

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1.Board DE2 ............................................................................................................. 7


2. TV Box.................................................................................................................. 8
3. Chng trnh v (paintbrush) ................................................................................ 9
4. My ht Karaoke v my chi nhc t card SD ................................................... 9
5. Thng bo cha ci dirver .................................................................................. 10
6. Chn cch thc ci t driver ............................................................................. 11
7. Chn th mc tm kim driver ............................................................................ 11
8. Chn th mc cha dirver .................................................................................. 12
9. Thng bo li ...................................................................................................... 12
10. Thng bo ci t hon tt ................................................................................ 13
11. To mi mt project .......................................................................................... 14
12. Hp hi thoi to mi project ........................................................................... 15
13. Hp thoi la chn chip .................................................................................... 16
14. Hp thoi tng hp cc thng tin ca project ................................................... 17
15. To mi file....................................................................................................... 18
16. La chn loi file cn to .................................................................................. 19
17. Ca s vit code ................................................................................................ 19
18. Ca s lp trnh ................................................................................................. 20
19. Hp thoi lu file .............................................................................................. 20
20. La chn lop-level cho file ............................................................................... 21
21. Bin dch chng trnh ..................................................................................... 21
22. Thng bo vic bin dch thnh cng ............................................................... 22
23. To mi file testbench....................................................................................... 23
24. Chn tn hiu s c test ................................................................................. 23
25. Hp thoi la chn tn hiu ............................................................................... 24
26. Ca s la chn tn hiu ................................................................................... 24
27. Xc nhn li vic la chn tn hiu ................................................................... 25
28. Thit lp gi tr cho cc tn hiu........................................................................ 25
29. Ca s Save As ................................................................................................. 26
30. La chn ch simulate ................................................................................. 26
31. Ca s thit lp cc thng s ca qu trnh simulate ........................................ 27
32. Thc hin chc nng tng hp v phn tch chng trnh ............................... 27
33. Thng bo thnh cng ....................................................................................... 28
34. Thit lp file testbench cho chng trnh ......................................................... 28
35. La chn ng dn lu tr file testbench ....................................................... 28
36. Ch nh v tr lu tr file testbench .................................................................. 29
37. Tin hnh qu trnh simulation ......................................................................... 29
38. Thng bo simulate thnh cng ........................................................................ 30
39. Kt qu qu trnh m phng (simulation) ......................................................... 30
40. Ca s gn chn ................................................................................................ 31
41. Cc tn hiu cn gn chn ................................................................................. 31
42. Danh sch cc chn c th c gn ................................................................ 32
43. Qu trnh gn chn hon tt .............................................................................. 32
44. Lu li file cu hnh chn ................................................................................. 33

Hnh
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45. Hp thoi load file cu hnh chn ..................................................................... 33


46. Ca s lp trnh (np) ....................................................................................... 34
47. Ca s Hardware Setup .................................................................................... 35
48. Ca s lp trnh ................................................................................................. 35
49. Ca s thit b ................................................................................................... 36
50. Ca s Device & Pin Options ........................................................................... 37
51. Thng bo thay i ch lp trnh ................................................................. 37
52. Ca s lp trnh trong ch AS ...................................................................... 38
53. La chn file cu hnh ...................................................................................... 38
54. Qu trnh lp trnh hon tt ............................................................................... 39
55. Ca s la chn loi file ................................................................................... 41
56. Ca s lm vic ca Quartus ............................................................................ 42
57. Hp thoi la chn linh kin c trong th vin ................................................ 43
58. c linh kin ln ca s lm vic ..................................................................... 44
59. Ca s gn chn cho tn hiu xut nhp ........................................................... 45
60. Hon tt vic v mch ....................................................................................... 45
61. La chn file cu hnh cho project ................................................................... 46
62. Ca s ci t ModelSim .................................................................................. 49
63. Ca s ci t ModelSim .................................................................................. 50
64. Ca s la chn th mc ci t ....................................................................... 51
65. La chn tn th mc cho chng trnh ........................................................... 52
66. Tng hp thng tin ci t ................................................................................ 53
67. Thanh process ci t ........................................................................................ 53
68. Ca s thng bo license ca phn mm .......................................................... 54
69. ng k thng tin.............................................................................................. 55
70. Xem thng tin card mng ca my ................................................................... 56
71. Ca s thuc tn ca h thng ........................................................................... 57
72. Ca s bin mi trng..................................................................................... 58
73. Hp thoi to mi mt bin mi trng ........................................................... 58
74. Ca s lm vic ca ModelSim ........................................................................ 59
75. To mi project ................................................................................................. 59
76. Thng tin ca project mi ................................................................................. 60
77. Thm cc file vo project .................................................................................. 60
78. Hp thoi to mi file ....................................................................................... 60
79. Ca s son tho ............................................................................................... 61
80. To mi file....................................................................................................... 61
81. Thm file vo project ........................................................................................ 62
82. Code verilog file testbench ............................................................................... 62
83. Th vin word ................................................................................................... 63
84. Thc hin simulate ............................................................................................ 63
85. Chn tn hiu s c v dng sng (gin ) .................................................. 64
86. Ca s lnh ....................................................................................................... 64
87. Gin thi gian ca cc tn hiu..................................................................... 65
88. Kt thc qu trnh simulate ............................................................................... 65
89. S kt ni mch ........................................................................................... 66
90. Kt ni mch ..................................................................................................... 68

Hnh
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91. Bng thc tr v s mch ............................................................................. 68


92. S mch........................................................................................................ 69
93. Bng thc tr v s kt ni ........................................................................... 69
94. S kt ni ..................................................................................................... 70
95. Bng thc tr ..................................................................................................... 70
96. Bng thc tr ..................................................................................................... 71
97. S kt ni mch ........................................................................................... 72
98. Bng thc tr v s kt ni mch ................................................................. 73
99. Mch cng 4-bit Full-Adder ............................................................................. 73
100. To file my trng thi .................................................................................... 76
101. Ca s lm vic ............................................................................................... 77
102. To cc trng thi ............................................................................................ 78
103. To cc ng chuyn trng thi .................................................................... 78
104. Thit lp biu thc chuyn trng thi ............................................................. 79
105. Thit lp tn hiu xut v action ca mi trng thi ........................................ 80
106. My trng thi ................................................................................................. 80
107. Chuyn my trng thi sang nh dng ca ngn ng thit kt phn cn ...... 81
108. Code verilog c to ra t my trng thi .................................................... 82
109. Chng trnh chnh ......................................................................................... 83
110. Thit lp top-level ........................................................................................... 83
111. Lu trng thi ............................................................................................. 84

H. Bch Khoa TP.HCM

Bui 1.

Khoa KH&KTMT

Tng quan v cc phn mm thit k trn FPGA

Mc tiu
Nm c cng ngh FPGA
Lm quen board thc hnh DE2
Ci t, v lm quen vi cc phn mm: Quartus II, Nios II

I. Gii thiu Board DE2 ca Altera


1. Gii thiu
Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc
lnh vc lun l s hc (digital logic), t chc my tnh (computer organization)
v FPGA.

Hnh 1.Board DE2

2. Thnh phn
Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht
trin, di y l thng tin chi tit ca mt board DE2:
FPGA:
-

Vi mch FPGA Altera Cyclone II 2C35.


Vi mch Altera Serial Configuration EPCS16.

Thc hnh thit kt mch s vi HDL

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Cc thit b xut nhp:


-

USB Blaster cho lp trnh v iu khin API ca ngi dung; h tr c 2 ch


lp trnh JTAG v AS.
B iu khin Cng 10/100 Ethernet.
Cng VGA-out.
B gii m TV v cng ni TV-in.
B iu khin USB Host/Slave vi cng USB kiu A v kiu B.
Cng ni PS/2 chut/bn phm.
B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in,
line-out, v microphone.
2 Header m rng 40-pin vi lp bo v diode.
Cng giao tip RS-232 v cng ni 9-pin.
Cng giao tip hng ngoi.

B nh:
-

SRAM 512-Kbyte.
SDRAM 8-Mbyte.
B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte).
Khe SD card.

Switch, cc n led, LCD, xung clock


-

4 nt nhn, 18 nt gt.
18 LED , 9 LED xanh, 8 Led 7 on
LCD 16x2
B dao ng 50-MHz v 27-MHz cho ng h ngun.

3. Mt vi ng dng ca board DE2


ng dng lm TV box

Hnh 2. TV Box

Thc hnh thit kt mch s vi HDL

KTMT

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Khoa KH&KTMT

Chng trnh v bng chut USB (paintbrush)

Hnh 3. Chng trnh v (paintbrush)

My ht Karaoke v my chi nhc SD

Hnh 4. My ht Karaoke v my chi nhc t card SD

II. Cch ci t Quartus II 8.0 v Nios II


1. Gii thiu
B phn mm thit k i km vi board DE2 bao gm 2 da: Quartus 2 v
Nios 2 Integrated Development Environment (IDE)
Quartus II l phn mm h tr tt c mi qu trnh thit k mt mch logic,
bao gm qu trnh thit k, tng hp, placement v routing (sp xp v chy dy),
m phng (simulation), v lp trnh ln thit b (DE2).
Nios II, mi trng pht trin tch hp ca h Nios II (IDE), n l cng c
pht trin ch yu ca h vi x l Nios II. Phn mm s l mi trng cung cp
kh nng chnh sa, xy dng, debug v m t s lc v chng trnh. IDE cn
cho php to cc chng trnh t n nhim (single-threaded) n cc chng

Thc hnh thit kt mch s vi HDL

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

trnh phc tp da trn mt h iu hnh thi gian thc v cc th vin


middleware.

2. Ci t
Ci t Quartus II v Nios II
Qu trnh ci t Quartus II v Nios n gin ch cn a a vo my v thc
hin theo hng dn ca chng trnh ci t

Ci t phn mm USB blaster driver


V Board DE2 c lp trnh bng cch s dng phn mm USB Blaster
(USB Blaster mechanism). Nn nu USB Blaster driver cha c ci t th qu
trnh lp trnh xung board DE2 s khng thnh cng.
Sau khi gn board DE2 vo my tnh thng qua cng USB, nu USB Blaster
driver cha c ci t th hp thoi sau s xut hin, Chn No, not this time sau
nhn Next

Hnh 5. Thng bo cha ci dirver

Chn Install from a specific location v chn Next

Thc hnh thit kt mch s vi HDL

10

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hnh 6. Chn cch thc ci t driver

Kt tip bn chn Search for the best driver in these location v sau nhn
Browse.

Hnh 7. Chn th mc tm kim driver

Thc hnh thit kt mch s vi HDL

11

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hp
thoi
mi
s
xut
hin
bn
tm
n
v
altera\quartus60\drivers\usbblaster, sau nhn OK v tip tc nhn Next

tr

Hnh 8. Chn th mc cha dirver

Ca s thng bo vic kim tra logo window khng thnh cng, tuy nhin
vic ny s khng b nh hng n vic kt ni ca chng trnh sau ny. Bn
tip tc nhn Continue Anyway

Hnh 9. Thng bo li

Nhn Finish hon tt vic ci t

Thc hnh thit kt mch s vi HDL

12

KTMT

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Khoa KH&KTMT

Hnh 10. Thng bo ci t hon tt

III. Cch np chng trnh cho Quartus II 8.0:


1. To 1 project:
Bc 1.

Vo Menu > file chn New Project Wizard

Thc hnh thit kt mch s vi HDL

13

KTMT

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Khoa KH&KTMT

Hnh 11. To mi mt project

Bc 2.
Ta chn th mc cha project v t tn cho project, xem hnh
bn di

Thc hnh thit kt mch s vi HDL

14

KTMT

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Khoa KH&KTMT

Hnh 12. Hp hi thoi to mi project

Bc 3.

Sau ta chn hng sn xut chip v tn loi chip trn mch

Thc hnh thit kt mch s vi HDL

15

KTMT

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Khoa KH&KTMT

Hnh 13. Hp thoi la chn chip

Bc 4.

Cui cng chn Finish hon tt

Thc hnh thit kt mch s vi HDL

16

KTMT

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Khoa KH&KTMT

Hnh 14. Hp thoi tng hp cc thng tin ca project

2. Vit chng trnh v bin dch:


Bc 1.

Vo Menu > file chn New

Thc hnh thit kt mch s vi HDL

17

KTMT

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Khoa KH&KTMT

Hnh 15. To mi file

Bc 2.
Sau chn loi file m chng ta mun vit chng trnh. y ta
chn loai file Verilog HDL

Thc hnh thit kt mch s vi HDL

18

KTMT

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Khoa KH&KTMT

Hnh 16. La chn loi file cn to

Bc 3.
x2

Di y l mt on chng trnh demo: tnh hm f = x1 EX-OR

Hnh 17. Ca s vit code

Bc 4.
Sau khi vit xong th ta phi lu tn file trng vi tn module ca
chng trnh

Thc hnh thit kt mch s vi HDL

19

KTMT

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Khoa KH&KTMT

Hnh 18. Ca s lp trnh

Hnh 19. Hp thoi lu file

Ch : Chn Add file to current project


Bc 5.
Sau khi lu file xong phi thit lp cho file l top-level th mi
bin dch c

Thc hnh thit kt mch s vi HDL

20

KTMT

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Khoa KH&KTMT

Hnh 20. La chn lop-level cho file

Bc 6.

Bin dch chng trnh:

Hnh 21. Bin dch chng trnh

Thc hnh thit kt mch s vi HDL

21

KTMT

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Khoa KH&KTMT

Hnh 22. Thng bo vic bin dch thnh cng

Ch : n y th c th np trc tip ln board DE2 kim th hoc s dng chng


trnh m phng c trn Quartus II. Phn 3 s trnh by cc bc cn thit to file m
phng v tin hnh m phng gin thi gian. Phn 4 s trnh by cc bc cn thit
np ln board DE2 kim th trc tip trn board ny.

3. To file m phng (simulate) v bt u simulate


Bc 1.

Vo Menu > file chn New, sau chn Vector Waveform File

Thc hnh thit kt mch s vi HDL

22

KTMT

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Khoa KH&KTMT

Hnh 23. To mi file testbench

Bc 2.

Sau nhp chut phi chn Insert, chn Insert Node or bus

Bc 3.

Chn Node Finder

Hnh 24. Chn tn hiu s c test

Thc hnh thit kt mch s vi HDL

23

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hnh 25. Hp thoi la chn tn hiu

Bc 4.
Ca s la chn tn hiu s xut hin (xem hnh 26).
hin th ra tt c cc chn :
Chn Pins: all.
Sau chn nt List hin tt c cc chn.

Nt

: Chn tng tn hiu

Nt

: Chn tt c cc tn hiu

Nt

: B tng tn hiu

Nt
: B tt c cc tn hiu
V d mun chn 3 tn hiu f, x1, x2 ta c 2 cch:

Chn tng tn hiu theo nt

Nhn nt
chn tt c c tn hiu
Nhn OK hon tt vic chn tn hiu

Hnh 26. Ca s la chn tn hiu

Thc hnh thit kt mch s vi HDL

24

KTMT

H. Bch Khoa TP.HCM


Bc 5.

Khoa KH&KTMT

Nhn OK n nh cc tn hiu cn chn

Hnh 27. Xc nhn li vic la chn tn hiu

Bc 6.
Thit lp gi tr cc tn hiu:
Ta r chut t khi chng li
Sau s dng cc nt 0, 1 thit lp gi tr cho chng (xem hnh 28)

Hnh 28. Thit lp gi tr cho cc tn hiu

Bc 7.

Sau khi thit lp gi tr ca cc chn xong ta Save li.

Thc hnh thit kt mch s vi HDL

25

KTMT

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Khoa KH&KTMT

Hnh 29. Ca s Save As

Bc 8.

Nhp vo nt

la chn ch simulate (xem hnh 30).

Bc 9.

Trong khung Simulate mode chn chc nng Functional

Hnh 30. La chn ch simulate

Thc hnh thit kt mch s vi HDL

26

KTMT

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Khoa KH&KTMT

Hnh 31. Ca s thit lp cc thng s ca qu trnh simulate

Bc 10.
Vo Processing > Generate Functional Simulation Netlist tin
hnh qu trnh phn tch v tng hp

Hnh 32. Thc hin chc nng tng hp v phn tch chng trnh

Bc 11.
Hp thoi thng bo qu trnh phn tch v tng hp thnh cng,
chn OK n nh

Thc hnh thit kt mch s vi HDL

27

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hnh 33. Thng bo thnh cng

Bc 12.

La chn file testbench cho chng trnh cn m phng

Hnh 34. Thit lp file testbench cho chng trnh

Bc 13.

Nhn vo nt

la chn ng dn lu tr file testbench.

Hnh 35. La chn ng dn lu tr file testbench

Bc 14.

La chn v tr lu tr file testbench trong hp thoi Select File

Thc hnh thit kt mch s vi HDL

28

KTMT

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Khoa KH&KTMT

Hnh 36. Ch nh v tr lu tr file testbench

Bc 15.
Chn Processing > Start Simulation hoc nhp vo nt
tin
hnh qu trnh simulation. Nu thnh cng th s c thng bo nh hnh 38, v
kt qu qu trnh m phng s c hin th nh hnh 39.

Hnh 37. Tin hnh qu trnh simulation

Thc hnh thit kt mch s vi HDL

29

KTMT

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Khoa KH&KTMT

Hnh 38. Thng bo simulate thnh cng

Hnh 39. Kt qu qu trnh m phng (simulation)

4. Cu hnh chn v np ln board


Cu hnh chn
cu hnh chn bn tin hnh ln lt theo cc bc sau:
Bc 1.
Chn Assignments-> Pins ca s la chn chn s xut hin nh
hnh:

Thc hnh thit kt mch s vi HDL

30

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hnh 40. Ca s gn chn

Bc 2.
Nhp p vo <<new>> ct To nh trn hnh. Mt menu cha
danh sch cc chn cn gn s c hin ra. Bn chn chn cn gn (v d
y chn tn hiu cn gn x1).

Hnh 41. Cc tn hiu cn gn chn

Bc 3.
Tip theo nhn vo <<new>> ct Location. Mt menu cha
danh sch cc chn trong FPGA s c hin ra bn chn chn ca FPGA s
ni vi tn hiu (v d y chn chn PIN_N25).

Thc hnh thit kt mch s vi HDL

31

KTMT

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Khoa KH&KTMT

Hnh 42. Danh sch cc chn c th c gn

Bc 4.

Lp li qu trnh ny cho n khi gn ht cc chn linh kin.

Hnh 43. Qu trnh gn chn hon tt

Bc 5.
lu li file cu hnh chn bn chn File -> Export, sau nhp
tn file cn lu.

Thc hnh thit kt mch s vi HDL

32

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

Hnh 44. Lu li file cu hnh chn

Bc 6.
nhng ln cu hnh sau ta c th load file cu hnh bng cch
(nu ln cu hnh chn ny l hon ton ging vi ln cu hnh trc). Bn
chn. Assignment -> Import Assignments, tip theo bn chn file cu hnh
chn ri nhn OK.

Hnh 45. Hp thoi load file cu hnh chn

Ch : DE2 cung cp mt file cu hnh chun, file ny c tn DE2_pin_assigments.csv


trong th mc. File cu hnh chun ny s kt ni tt c cc chn ca DE2. Khi bn
ch cn t tn tn hiu trng tn vi tn hiu m DE2 quy c. V d: cc nt nhn s c
tn l SW, cc n led s c tn l LEDG hay LEDR,

Np ln board

Thc hnh thit kt mch s vi HDL

33

KTMT

H. Bch Khoa TP.HCM

Khoa KH&KTMT

DE2 h tr 2 cch np ln board. l ch np l JTAG v AS. Trong ch


JTAG (Joint Test Action Group) th d liu cu hnh s c np trc tip ln
FPGA. Trong ch ny th thng tin cu hnh s b mt khi tt ngun. ch AS
(Active Serial), th d liu cu hnh s c np ln b nh flash. Mi khi m ngun
(reset) th thng tin cu hnh y s c load ln FPGA, do thng tin cu hnh
FPGA s khng b mt mi khi tt ngun. chuyn i gia 2 ch np ny th
trn board DE2 cung cp nt RUN/PROG. RUN tng ng vi ch np JTAG,
trong khi PROG l ch AS.

Lp trnh theo ch JTAG


Tin hnh theo cc bc:
Bc 1.
Gt nt RUN/PROG trn board DE2 sang RUN, sau chn
Tools->Programmer, ca s lp trnh cho board DE2 s xut hin nh hnh
v.

Hnh 46. Ca s lp trnh (np)

Bc 2.
Trn ca s lp trnh, ch la chn JTAG trong khung ch lp
trnh (Mode). Tip o nu USB-Blaster khng c chn nh trn hnh, th
bn nhn Hardware Setup, ca s Hardware Setup s xut hin khi bn
chn USB-Blaster la chn cng kt ni vi board DE2.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 47. Ca s Hardware Setup

Bc 3.
Tr li ca s lp trnh bn chn vo file lp trnh (light.sof). Nu
file ny cha c th bn c th nhn nt Add File thm file ny vo. Tip
bn nhp vo la chn Program/configure

Hnh 48. Ca s lp trnh

Bc 4.
Nhn nt Start bt u vic lp trnh. Trong khi lp trnh th cc
n led trn board DE2 s sng m i. Trn ca s lp trnh, thanh Progess s
cho thy tin trnh np ln board DE2.

Lp trnh theo ch AS
Bc 1.
Gt nt RUN/PROG trn board DE2 sang PROG.
Bc 2.
Vo Assignment -> Device, chn Device v sau chn thit b l
EP2C35F672C6. Tip nhp vo Device & Pin Options, ca s Device &
Pin Opions s xut hin, bn chn tab Configuration, trong khung

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Configuration device chn EPCS16. Nhn OK n nh sau dch li


chng trnh.

Hnh 49. Ca s thit b

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 50. Ca s Device & Pin Options

Bc 3.
Tools->Programmer, ca s lp trnh s xut hin (nh hnh ca
s lp trnh). Tip trong khung Mode bn chn Active Serial
Programming. Mt thng bo s hin ln bn chn Yes.

Hnh 51. Thng bo thay i ch lp trnh

Bc 4.
Ca s lp trnh ch AS s hin ra nh hnh bn di. Bn
chn nt Add File thm file cn np vo chng trnh (light.pof, file
cu hnh cho ch AS s c dng *.pof v file cu hnh cho ch JTAG s
c dng *.sof).

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 52. Ca s lp trnh trong ch AS

Hnh 53. La chn file cu hnh

Bc 5.
Nhp vo la chn Program/Configure. Tip bn nhn nt
Start np chng trnh cu hnh ln board DE2

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 54. Qu trnh lp trnh hon tt

Thc hnh thit kt mch s vi HDL

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H. Bch Khoa TP.HCM

Bui 2.

Khoa KH&KTMT

Mch t hp v mch tun t

Mc ch: Nm vng cc kin thc


Thit k FPGA thng qua s khi/Schematic
Mch tun t v mch t hp
o Rt gn biu thc i s Boole bng phng php ba Karnaugh
o Gii thut rt gn Quine McCluskey
o Thit k mch tun t
o Thit k mch t hp

I. Gii thiu
1. Gii thiu
Ngoi vic vit chng trnh cu hnh FPGA thng qua code verilog nh
trnh by chng trc th Quartus II cn h tr nhiu cch thit k FPGA khc:
s dng AHDL, EDIF file, SystemVerilog HDL file, Tcl Script file trong th
cch thit k s dng s khi, s dng trc tip cc khi lun l l mt trong
nhng cch kh thng dng. Di y s trnh by mt v d thit k FPGA thng
qua m hnh s khi.

2. Hng dn thit k FPGA thng qua s khi/Schematic


hiu r qu trnh thit k ny, chng ti s trnh by mt v d n gin s
dng s khi/schematic. Chng trnh s hin thc php nor trn 2 tn hiu
SW[0] v SW[1] sau xut tn hiu ra LEDR[0]. to mt s mch v cu
hnh v d ny ln FPGA bn ln lt thc hin cc bc sau:
Bc 1. M Quartus II v to mt project mi (thc hin nh bi trc
trnh by)
Bc 2. Vo File -> New hoc nhp vo biu tng
trn thanh cng c.
Ca s la chn loi file s xut hin bn chn Block
Diagram/Schematic File sau nhn OK.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 55. Ca s la chn loi file

Bc 3.

Ca s son tho s hin ra nh hnh bn di.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Ca s lm vic

Thanh cng c
Ca s project

Hnh 56. Ca s lm vic ca Quartus

Bc 4. thun tin cho vic son tho ca bn, th y ti s gii thiu


chc nng ca mt vi nt trn thanh cng c:
a.

(Select tool): con tr l cng c gip chn la cc thnh phn trn


ca s lm vic
b. Nt
(Text tool) : cng c to cc ra cc dng vn bn trn ca s
lm vic
c.
(Symbol tool): cha linh kin s dng cho qu trnh son tho (cc
cng lun l, cc megafunction, v cc cha nng khc)
d.

(Block tool): cng c h tr vic to ra cc khi chc nng. Gip


cho vic thit k nhiu cp chc nng.
e.
(orthogonal node tool): ni dy tn hiu
f.
(orthogonal bus tool): ni bus cho cc tn hiu
g.
h.

(Zoom tool): phng to, thu nh


(Full Screen): La chn ch ca s lm vic l Full Screen hay
khng.
i.
(Find): cng c tm kim trn ca s lm vic
Bc 5. Tip n bn chn nt
(Symbol tool) ca s xut hin

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 57. Hp thoi la chn linh kin c trong th vin

Bc 6. Trn ca s la chn linh kin bn chn primitives -> logic ->


nor2 sau nhn OK. Tip bn nhn chut tri ln ca s lm vic
thc hin vic c mt linh kin cng nor (2 ng nhp). kt thc vic
chn cng nor2, bn nhp chut phi vo ca s lm vic v chn Cancel

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 58. c linh kin ln ca s lm vic

Bc 7. Tip tc chn
(Symbol tool), trong ca s la chn linh kin
bn chn ng dn primitives -> pin -> input, sau bn c 2 tn hiu
ng nhp. Lp li qu trnh ny c thm mt tn hiu output nh hnh
bn di

Bc 8. Bc k tip l kt ni chn cc linh kin. Bn nhp vo biu


tng
(orthogonal node tool) trn thanh cng c, sau drag chut t
v tr mun ni n v tr ch
Bc 9. Nhp p vo tn hiu nhp gn chn cho mch thit k. Nhp
gi tr SW[0] vo pin name sau nhn OK.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 59. Ca s gn chn cho tn hiu xut nhp

Bc 10. Tng t nh vy bn thit lp cho tn hiu nhp cn li l SW[1]


v tn hiu output l LEDR[0].

Hnh 60. Hon tt vic v mch

Bc 11. Chn Assignments -> Import Assignments, ca s la chn file


cu hnh chn cho FPGA xut hin, bn chn ng dn cho file
DE2_pin_assignments.csv ri nhn OK

Thc hnh thit kt mch s vi HDL

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Hnh 61. La chn file cu hnh cho project

Bc 12. Nhn Ctrl + S hoc nhp vo biu tng


trn thanh cng c.
Khi hp thoi Save As xut hin bn chn ng th mc cha project hin
ti ca mnh v lu vi tn trng vi tn project ca mnh, ng thi chn
Add file to current project sau nhn OK
Bc 13. Nhp nt
trn thanh cng c hoc chn Processing -> Start
Complilation bin dch chng trnh
Bc 14. Sau khi qu trnh compile hon tt bn tin hnh np ln board
DE2. Quy trnh np ny hon ton ging vi quy trnh np ln board DE2
phn trc.

II. Bi tp
Bi 1. Hy hin thc hm F (khng rt gn) ln FPGA bng phng php thit
k s khi, tn hiu nhp c a vo t cc SW, v tn hiu xut l cc
LEDR. Rt gn hm F, v m hnh transitor v kim tra li kt qu hm rt
gn vi kt qu chng trnh chy trn FPGA. Vi hm F nh sau:
a. F a(b c d )(a bc)
b. F a(c b) ad bcd
Bi 2. Ch s dng tnh cht ca hm Boole bin i biu thc F thnh dng
tng cc tch (SOP) v tch cc tng (POS), vi F
a. F a(b c)(a c)
b. F a(b c) d bc
Bi 3. S dng phng php Ba Karnaugh
a. Rt gn hm F (a, b, c, d ) m(0,1, 4, 7, 8,11,15) d (2,13) v dng tng
cc tch (SOP)

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

b. rt gn hm F (a, b, c, d ) M (0, 2, 4, 6, 7,10,15) d (8,11) v dng


tch cc tng (POS)
Bi 4. S dng gii thut Quine McCluskey rt gn biu thc sau
a. F (a, b, c, d ) m(0, 2, 4, 6, 7,10,15) d (8,11)
b. F (a, b, c, d ) m(0,1, 4, 7, 8,11,15) d (2,13)
Bi 5. Hy thit k mt SR-Latch s dng D-Latch v cc cng lun l v hin
thc n ln FPGA.
Bi 6. Hy thit k mt D-Latch s dng RS-Latch v cc cng lun l v hin
thc n ln FPGA kim th.
Bi 7. Mt mch tun t c 2 D-FlipFlop A v B, cc tn hiu nhp ca mch
tun t l X, Y. Tn hiu xut l Z. S kt ni ca mch c biu din
thng qua cc cng thc sau:

DA ( X Y )(QB QA Y ), DB X (QA QB ), Z X QAQB


Hy hin thc mch tun t ny ln FPGA.

Thc hnh thit kt mch s vi HDL

47

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H. Bch Khoa TP.HCM

Bui 3.

Khoa KH&KTMT

Lp trnh Verilog vi m hnh cu trc

Mc ch: Nm vng cc kin thc


Gii thiu cng c son tho v m phng ModelSim
HDLs v Verilog
Hin thc cc mch t hp v tun t bng verilog
Hin thc cc testbench kim th
M phng v kim chng thit k trn ModelSim

I. Gii thiu ModelSim


1. Gii thiu
ModelSim l mi trng m phng v kim th (debug) phn cng rt thng
dng hin nay. y chng ti s dng phin bn ModelSim web 6.1g
(ModelSim-Altera 6.1g web edition).

2. Ci t
tin hnh ci t bn ln lt thc hin cc bc sau:
Bc 1. Nu bn cha c file ci t th c th down load file ci t ti
https://www.altera.com/support/software/download/eda_software/modelsim/msmindex.jsp. Bn chn phin bn web 6.1g
Bc 2. Sau khi c file ci t bn nhp p chut vo file ny. Ca s ci t
s xut hin.

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Hnh 62. Ca s ci t ModelSim

Bc 3.

Bn nhn Next tip sang bc k tip.

Thc hnh thit kt mch s vi HDL

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Hnh 63. Ca s ci t ModelSim

Bc 4.

Bn nhn Yes chp nhn cc yu cu v license ca Altera

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 64. Ca s la chn th mc ci t

Bc 5. Tip theo bn nhn Browse la chn ng dn ci t mi hoc c th


th mc mc nh. Sau nhn Next

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 65. La chn tn th mc cho chng trnh

Bc 6.

Tip tc bn nhn Next, hoc nhp tn th mc mi vo.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 66. Tng hp thng tin ci t

Bc 7. Trong ca s hin th thng tin th mc ci t bn chn Next thc


hin qu trnh ci t. Thanh process s xut hin cho bit tin trnh ci t
phn mm.

Hnh 67. Thanh process ci t

Bc 8. Sau khi qu trnh ci t kt thc mt bn thng bo s xut hin. Nu


bn c file license.dat th chn Yes v b qua quy trnh download file license
t trang web altera. Ngc li nu cha c file ny th bn chn No v sau tin
hnh download file license t altera, theo hng dn sau

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 68. Ca s thng bo license ca phn mm

Bc 9. download file license, trc tin bn vo trang ch


https://www.altera.com ng k account, sau bn vo trang web sau:
Bc 10. https://www.altera.com/support/software/download/eda_software/modelsi
m/dnl-msim-61g.jsp tin hnh download. Trong trang web ny bn chn phin
bn Windows (ModelSim-Altera Web Edition) v nhp vo link requires a
license. Trang web s yu cu bn login vo h thng, bn login vo account
to ra (nu cha c th ng k mi mt account) sau vo li trang ny
down. Trng hp login thnh cng th bn s thy trang web nh sau:

Thc hnh thit kt mch s vi HDL

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a ch card mng

Hnh 69. ng k thng tin

Bc 11. trang web ny bn nhp a ch card mng ca my mnh vo khung


NIC number. ng thi la chn option Yes, include a free ModelSim-Altera
Web Edition License v Academic: Only for academic/education/hobby purposes.
Sau nhn Continue n nh. Mt email t server s c gi vo email ca
bn, vo mail v download file license.
Bc 12. Sau khi download file license bn sa tn file li thnh license.dat v lu
trong th mc C:\ModelSim.
Bc 13. bit c a ch card mng ca mnh th bn vo Start-> Run, g vo
cmd v nhn enter. Trong ca s mi xut hin bn g lnh ipconfig /all a ch
card mng ca my s c hin th nh hnh v:

Thc hnh thit kt mch s vi HDL

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Hnh 70. Xem thng tin card mng ca my

Bc 14. Sau khi c file license bn tip tc to 2 bin mi trng ch n v


tr ca file license. u tin bn nhp chut phi vo Mycomputer (trn desktop)
chn Properties. Trong ca s properties bn chn tab advanced

Thc hnh thit kt mch s vi HDL

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Hnh 71. Ca s thuc tn ca h thng

Bc 15. Tip tc bn nhp nt vo nt Environment Variables, ca s cha cc


bin mi trng s c hin th nh hnh v

Thc hnh thit kt mch s vi HDL

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Hnh 72. Ca s bin mi trng

Bc 16. Trong ca s user variables bn chn nt New to mt bin mi trng


mi. Ca s to mi s xut hin

Hnh 73. Hp thoi to mi mt bin mi trng

Bc 17. Tip bn nhp tn bin l LM_LICENSE_FILE v gi tr bin l


C:\ModelSim\license.dat, sau nhn OK n nh. Tng t bn to thm mt
bin khc c tn l MGLS_LICENSE_FILE v gi tr l C:\ModelSim\license.dat.
n y th vic ci c hon tt, chy chng trnh bn ch cn nhp p
vo icon ca ModelSim trn desktop.

3. Hng dn
Di y s l quy trnh son tho mt project vi ModelSim.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Bc 1. Nhp p vo icon ca ModelSim trn mn hnh desktop. Ca s lm vic


ca ModelSim s xut hin nh hnh v.

Hnh 74. Ca s lm vic ca ModelSim

Bc 2. to mi mt project bn vo File -> New -> Project (xem hnh).

Hnh 75. To mi project

Bc 3. Trong ca s to mi project bn nhp tn ca project, la chn ni lu


tr project sau nhn OK to mi project.

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 76. Thng tin ca project mi

Bc 4. K , mt ca s cho php to thm cc file vo project xut hin

Hnh 77. Thm cc file vo project

Bc 5. Bn chn Create New File, hp thoi to mi mt file s xut hin

Hnh 78. Hp thoi to mi file

Bc 6. Tip theo bn nhp tn file, chn Browse chn ni lu tr file nyv


chn kiu file s to ra (chn Verilog, nh trn hnh v). Sau khi to xong bn
chn close ng ca s thm file vo project.
Bc 7. Nhp p vo file mi to tin hnh son tho.

Thc hnh thit kt mch s vi HDL

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Hnh 79. Ca s son tho

Bc 8. Hnh v trn cha code verilog hin thc mt cng AND 2 ng nhp. Sau
khi g xong code verilog bn nhp vo nt
trn thanh cng c bin dch
chng trnh. Ca s lnh s cho bit chng trnh bin dch c thnh cng hay
khng (xem hnh).
Bc 9. Tip theo kim th ta phi hin thc thm file testbench. File
TestBench ny s s dng chng trnh chnh (cng AND) nh l mt linh kin
th vin, v nhim v chnh ca file testbench l lm sao to ra y cc kh
nng c th kim tra tnh ng n ca linh kin test. Cc bc tip theo y
s l quy trnh to ra file testbench.
Bc 10.To mi mt file bn vo File->New->Source->Verilog to mi file
verilog (xem hnh).

Hnh 80. To mi file

Bc 11.Ca s ca file mi to s xut hin, bn nhn Ctrl + S hoc nhp vo biu


tng
trn thanh cng c lu li file mi ny. Khi ca s Save As xut
hin bn nhp tn file vo sau nhn Save lu tr file
Bc 12.K tip bn thm file mi to ny vo project ca mnh bng cch chn
File->Add to Project->Existing File.

Thc hnh thit kt mch s vi HDL

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Hnh 81. Thm file vo project

Bc 13.Trong ca s thm file vo project, bn chn Browse tm v tr ca file


cn thm vo. Trong khung ca s kiu file (add file as type) bn chn loi file
cn thm vo (verilog), nhn OK n nh
Bc 14.Tip theo bn nhp p vo file va mi thm vo bn ca s project, v
nhp hin thc code cho file ny.

Hnh 82. Code verilog file testbench

Bc 15.Bin dch file testbench sau nhp vo tab Library. Ton b file trong
project s c bin dch vo th vin word. Bn m th vin ny s thy cc
file va mi to (xem hnh).

Thc hnh thit kt mch s vi HDL

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Hnh 83. Th vin word

Bc 16.Nhp chut phi vo file Testbench v chn Simulate thc hin qu


trnh simulate (m phng) file testbench.

Hnh 84. Thc hin simulate

Bc 17.Ca s Object s xut hin, trong ca s ny bn gi phm Ctrl v nhp


chut tri chn nhng tn hiu s c v trn gin thi gian.

Thc hnh thit kt mch s vi HDL

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Hnh 85. Chn tn hiu s c v dng sng (gin )

Bc 18.Tip theo trong ca s lnh bn g ln run 199 (nh hn thi gian


simulate 1 n v chng trnh vn cha dng li).

Hnh 86. Ca s lnh

Bc 19.Ca s v gin thi gian s xut hin

Thc hnh thit kt mch s vi HDL

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Hnh 87. Gin thi gian ca cc tn hiu

Bc 20. kt thc qu trnh simulate bn c th vo Simulate -> End Simulate

Hnh 88. Kt thc qu trnh simulate

II. Bi tp
Bi 1. Hin thc b cng Half-adder bng Verilog
Bi 2. Hin thc b cng Full-adder t cc b cng Half-adder s dng Verilog.
Bi 3. Hin thc cc testbench kim th b cng Half-adder
Bi 4. Hin thc testbench kim th cho b cng Full-adder
Bi 5. S dng cc cng primitive thit k mch sau

Thc hnh thit kt mch s vi HDL

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Hnh 89. S kt ni mch


Vit testbench kim th chng trnh thit k trn.
Bi 6. Pht trin v kim th bng Verilog mch chuyn i mt m BCD sang
m Excess-3 nh chng 3.

Thc hnh thit kt mch s vi HDL

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Bui 4.

Khoa KH&KTMT

M hnh hnh vi

Mc ch:
Cng c kin thc v HDL v Verilog
Thc hin vic np v kim th trc tip trn FPGA
Nm vng quy trnh thit k FPGA
Lm quen vi DE2
S dng Quartus II

I. Bi tp
Bi 1. Board DE2 cung cp 18 nt gt (SW0-SW17) v 18 n led (LEDR0LEDR17). Hin thc mt module, v np ln board DE2 cho php s dng
cc nt gt iu khin m hoc tt cc n led ny.
Hng dn: thc hin lnh gn:
assign LEDR[17] = SW[17]
assign LEDR[16] = SW[16]

assign LEDR[0] = SW[0]


Bi 2. Hin thc mt b mch chn (Multiplexer), gm 3 tn hiu ng nhp X (8
bit), Y (8 bit), s (1 bit) v 1 tn hiu ng xut 8 bit M. Nu s = 0 th tn hiu
ng xut M = X, ngc li (s = 1) th M = Y.
Hng dn: hin thc mt mch chn 2-to-1, ngha l X (1 bit), Y(1 bit), M(1
bit). Nu s = 0 th M = X, ngc li M = Y. S mch kt ni nh sau:

Thc hnh thit kt mch s vi HDL

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Khoa KH&KTMT

Hnh 90. Kt ni mch

Verilog Code: assign m = (~s & x) | (s & y)


Bi 3. Hin thc mt b chn 5-to-1 (Multiplexer) t 4 b chn 2-to-1 cho php
chn tn hiu ra m t 5 tn hiu nhp u, v, w, x, y v 3 tn hiu iu khin s0,
s1 v s2 (m, u, v, w, x, v y u l cc tn hiu 1 bit). B chn hot ng theo
ng bng thc tr sau:

Hnh 91. Bng thc tr v s mch

Hng dn:
-

Hin thc b chn 2-to-1 tng t nh bi 2 (xy dng chng trnh con).

Thc hnh thit kt mch s vi HDL

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-

Khoa KH&KTMT

Hin thc b chn 5-to-1 bng cch s dng 4 b chn 2-to-1, c kt ni


nh hnh v:

Hnh 92. S mch

Bi 4. Hin thc mch decode led 7 on vi tn hiu nhp l c2c1c0 v tn hiu


xut l mt led7 hot ng nh bn thc tr sau:

Hnh 93. Bng thc tr v s kt ni

Hng dn:
-

Ni c2c1c0 vo cc SW[2:0]

Ni tn hiu xut vo led 7 HEX0[0:6]

Bi 5. Hin thc chng trnh verilog thc hin cc chc nng sau:

Thc hnh thit kt mch s vi HDL

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Hnh 94. S kt ni

Tn hiu nhp bao gm cc b 3 bit ln lt l SW[0:2], SW[3:5], SW[6:8],


SW[9:11], SW[12:14], cc tp bit ny s ln lt cha d liu 100, 011, 010,
001, 000 tng ng vi cc k t blank (tt ht), O, L, E hoc H. Cc tn hiu
SW[15:17] cho php s chn d liu no s c hin th ln led 7 on

Bi 6. M rng bi tp s 5 s dng c 8 led 7 on hin th chui nh sau:

Hnh 95. Bng thc tr

Thc hnh thit kt mch s vi HDL

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Bui 5.

M hnh hnh vi (tt)

Mc ch: Nm vng cc kin thc


HDLs v Verilog
Quartus II
Vit chng trnh v kim th trc tip trn board DE2

I. Bi tp
Bi 1. Hin thc mt chng trnh verilog thc hin cc chc nng sau:
-

Hin th gi tr ca cc switch SW[0:3], SW[4:7], SW[8:11], SW[12:15] ln


cc led 7 on 0, 1, 2, 3.

Chuyn nhng gi tr t cc switch ra gi tr trn cc led 7. Nu gi tr ca


cc switch l t 10 n 15 th khng cn quan tm

Bi 2. Hin thc b gii m 4 bit thp lc phn thnh 2 s thp phn hin th trn
led 7:
-

Tn hiu nhp l cc switch SW[0:3]

Tn hiu xut l cc led 7 HEX0, HEX1

Hot ng theo bng thc tr sau:

Hnh 96. Bng thc tr

Thc hnh thit kt mch s vi HDL

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Hnh 97. S kt ni mch

Hng dn:
-

Thit k b so snh: Comparator, s dng kim tra liu tn hiu nhp


v3v2v1v0 c ln hn 9 hay khng. Nu gi tr nhp ln hn 9 th tn hiu
output ca b so snh ny, z, c tn hiu l 1 v trc tip iu khin cc b
chn 2-to-1 (Multiplexer) v iu khin led7 th 2.

Thit k mch A, nhn tn hiu nhp v2v1v0 v tn hiu xut l bng tn hiu
nhp tr i 2.

Thit k b decode7 nhn tn hiu l m3m2m1m0 v gii m ra led7

Thit k b mch B mch ny iu khin led7 th 2, nu tn hiu nhp l 1 th


tn hiu xut l gi tr 1 trn led7. Ngc li hin th gi tr 0 trn led7

Bi 3. Hin thc b cng 4 bit (4bit-Full-Adder) t cc b cng 2 bit (2bit-FullAdder)


-

Tn hiu nhp l cc switch SW[0:3], SW[4:7], v tn hiu carry-in l SW[8]

Tn hiu xut l cc led n LEDR[0:3], carry-out l LEDR[4]

Hng dn:
Thc hnh thit kt mch s vi HDL

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Hin thc cc mch cng 2bit-Full-Adder theo mch sau

Hnh 98. Bng thc tr v s kt ni mch

Kt ni 4 mch cng 2bit-Full-Adder thnh mch cng 4bit-FullAdder theo s


sau

Hnh 99. Mch cng 4-bit Full-Adder

Bi 4. Hin thc b cng y 4 bit BCD (t 0 n 9) vi c t sau:


-

Tn hiu nhp l SW[0:3] (A) v SW[4:7] (B), carry-in SW[8] (C), cc tn


hiu nhp A, B c ni vi cc led n LEDR[0:3], LEDR[4:7] ng thi
c hin th gi tr ln led 7 on l HEX6 v HEX4. C c ni vi
LEDR[8].

Tn hiu xut (kt qu php cng) c ni vi LEDG[0:3] (S) ng thi


c hin th ln 2 led7 l HEX1 v HEX0, v carry-out(Co) c ni vi
LEDG[4].

Bi 5. Hin thc b chuyn i 6-bit nh phn sang 2 s thp phn v hin th


trn 2 led7 on
Bi 6. Hin thc mt chng trnh verilog thc hin cc chc nng sau:
-

Cho php nhp vo 2 s 16 bit, v sau hin th gi tr (thp lc phn) ca 2


s ny ln led 7 on

Thc hnh thit kt mch s vi HDL

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Tn hiu nhp l SW[0:15], SW[16] cho php quyt nh nhp s no (s th


nht hay s th 2). Sau hin th 2 s ny ln led 7, s u tin ln HEX0,
HEX1, HEX2, HEX3. S th 2 ln 4 led 7 cn li.

Bi 7. Hin thc b m BCD, cho php tng gi tr ni dung bin m c mi


giy mt ln
-

Tn hiu KEY0 l tn hiu reset (xa gi tr m xung 0)

Cc s BCD s c hin th ln 3 led 7 HEX2-0

Bi 8. Hin thc mch trn board DE2, hin th thng tin ngy thng nm
-

Tn hiu KEY0 l tn hiu reset (xa tt c gi tr xung 0)

Hin th thng tin ln cc led7 on.


o Gi: (gi tr t 0 n 23) hin th HEX7-6
o Pht: (gi tr t 0 n 59) hin th HEX5-4
o Giy: (gi tr t 0 n 59) hin th HEX3-2

o Sao: (= 1/100 giy, gi tr t 0 n 99) hin th HEX1-0

Thc hnh thit kt mch s vi HDL

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Bui 6.

My trng thi

Mc ch:
Thit k s dng m hnh my trng thi
Cng c kin thc l thuyt v cc my trng thi Moore v Mealy
Bit cch xy dng mch t cc my trng thi
Nm vng k thut rt gn mt my trng thi

I. Gii thiu
1. Gii thiu
Quy trnh thit k FPGA thng thng kh phc tp i hi ngi thit k
phi thng qua kh nhiu bc phc tp. My trng thi l mt trong nhng bc
trung gian gip cho qu trnh thit k v hin thc code verilog tr nn d dng
hn i vi ngi lp trnh. Thng thng c 2 dng my trng thi: Moore v
Mealy. Tuy nhin trong Quartus ch h tr my trng thi Moore. Bi thc hnh
ny s gip cc bn sinh vin tip cn vi cch thit k HDL theo cch thc ny.

2. Hng dn
to mt my trng thi cc bn thc hin cc bc sau:
Bc 1. M Quartus v to mi mt project (cch to nh trnh by trong bui
u tin)
Bc 2. K tip bn vo File -> New hoc nhp vo biu tng trn thanh cng
c, to mi mt file

Thc hnh thit kt mch s vi HDL

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Hnh 100. To file my trng thi

Bc 3. Trong ca s to mi file bn chn loi State Machine file, sau nhn


OK. Ca s son tho s xut hin nh hnh v

Thc hnh thit kt mch s vi HDL

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Thanh cng c
Ca s project
Ca s lm vic

Hnh 101. Ca s lm vic

Bc 4. Di y l mt vi cng c h tr cho vic thit k mt my trng thi c


trn thanh cng c
a.
(Selection tool): Cng c la chn cc thnh phn trong my trng thi
b.
c.
d.

(Zoom tool): Cng c phng to hay thu nh.


(State tool): Cng c v trng thi
(Transition tool): Cng c v ng chuyn trng thi

e.

(State table): Cng c n/hin bng trng thi

f.
g.
h.

(State machine wizard): Cng c to my trng thi bng ca s wizard


(Insert input port): cng c thm cng nhp
(Insert output port): cng c thm cng xut

i.

(Generate HDL file): Cng c chuyn my trng thi thnh code verilog,
HDL,
j.
(Transition Equation): Cng c n/hin biu thc trn cc cnh chuyn trng
thi
Cc bc tip theo s l quy trnh to ra mt my trng thi c kh nng nhn
din chui 2 bit 1 lin tip. Sau chuyn file ny thnh code verilog.
Bc 5. Bn nhp vo cng c
(State tool) sau v 3 trng thi nh hnh v

Thc hnh thit kt mch s vi HDL

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Hnh 102. To cc trng thi

Bc 6. Tip theo bn nhp vo cng c (Transition tool) v drag chut t trng


thi ny n trng thi state1 n trng thi state2 hnh thnh ng chuyn
trng thi t trng thi state1 sang trng thi state2. Tng t ta v c my
trng thi nh hnh v (trng hp nu v ng chuyn trng thi vo chnh n
th ch cn chn cng c transition tool, sau nhp chut tri vo trng thi ).

Hnh 103. To cc ng chuyn trng thi

Thc hnh thit kt mch s vi HDL

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Bc 7. Tip theo bn nhp vo biu tng


(Insert input port) thm mt tn
hiu nhp v click vo biu tng
(Insert output port) thm mt tn hiu
xut
Bc 8. Nhp vo biu tng (State table) hin th bng trng thi (nu bng
ny b n i). Trong ca s trng thi ny chn tab Transition (xem hnh)

Hnh 104. Thit lp biu thc chuyn trng thi

Bc 9. Nhp tn hiu tn tn hiu nhp vo (input1). Trng hp nu ng


chuyn trng thi ny ch b nh hng bi duy nht mt tn hiu nhp (input1)
th:
a. Nu chuyn trng thi xy ra khi gp mt tn hiu 0 th nhp tn tn hiu vo
(input1)
b. Nu chuyn trng thi xy ra khi gp tn hiu nhp l 1 th nhp tn tn hiu v
pha trc c du ~ (~input1, o tn hiu input1)
Trng hp ng chuyn trng thi b nh hng bi nhiu tn hiu th thm
du & gia cc tn hiu (v d: input1 & input2).
Bc 10. Tng t nh vy i vi cc ng chuyn trng thi khc.
Bc 11. K tip bn chn trng thi state1 sau nhp chut phi chn properties.
Ca s properties s xut hin, bn chn tab Action (xem hnh)

Thc hnh thit kt mch s vi HDL

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Hnh 105. Thit lp tn hiu xut v action ca mi trng thi

Bc 12. Trong ct Output Port bn chn tn hiu xut, ct Output Value bn thit
lp gi tr xut ra cho trng thi . Sau nhn OK
Bc 13. Lp li thao tc ny cho 2 trng thi cn li.
a. State1: Output Port l output1, v Output Value l 0
b. State2: Output Port l ouput1, v Output Value l 0
c. State3: Output Port l output1, v Output Value l 1
Bc 14. Cui cng bn s c my trng thi nh hnh v:

Hnh 106. My trng thi

Thc hnh thit kt mch s vi HDL

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Bc 15. Nhn Ctrl + S, hoc nhp vo biu tng


trn thanh cng c lu li
my trng thi ny vi tn l Machine11.smf. Tip theo bn nhn vo biu tng
(Generate HDL file) trn thanh cng c. Khi bn thng bo sinh file HDL xut
hin bn nhp vo la chn Verilog HDL sau nhn OK, Quartus s sinh ra mt
file Verilog (Machine11.v) t s my trng thi ny.

Hnh 107. Chuyn my trng thi sang nh dng ca ngn ng thit kt phn cn

Thc hnh thit kt mch s vi HDL

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Hnh 108. Code verilog c to ra t my trng thi

Bc 16. K tip bn to mt file mi bng cch nhp vo biu tng


to ra
mt file verilog mi. File ny s l file chnh ca project n s s dng linh kin
Machine11 tao ra nh l mt thit b bnh thng.
Bc 17. Hon tt code cho file verilog mi to ra ny (xem code).

Thc hnh thit kt mch s vi HDL

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Hnh 109. Chng trnh chnh

Bc 18. Lu li file ny vi tn trng vi tn ca project, ng thi nhp chut


phi vo file v chn la chn Set as Top-Level Entity.

Hnh 110. Thit lp top-level

Bc 19. Import file cu hnh chn DE2_pin_assignment.csv cho project nh


hng dn nhng phn trc. Sau bin dch v np xung board DE2
kim th.

II. Bi tp
Bi 1. Cho s my trng thi sau:

Thc hnh thit kt mch s vi HDL

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Hnh 111. Lu trng thi

a. Hy hin thc my chuyn trng thi ny ln DE2


b. Hy v bng trng thi v s d mch ca my trng thi trn.
Bi 2. Thit k mt mch tun t cho php kim tra chui 1001. V hin thc
n ln board DE2 kim th.

Thc hnh thit kt mch s vi HDL

84

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