Professional Documents
Culture Documents
Chng 1.
Chng 2.
Chng 3.
Hng dn ci t v s dng phn mm Control Panel iu
khin kit DE2 ....................................................................................... 89
3.1 Hng dn ci t Control Panel iu khin Kit DE2................... 89
3.2 Tng quan v cu trc v hot ng ca Control Panel ................ 92
3.3 Hng dn s dng Control Panel ................................................ 95
3.3.1 iu khin LEDs, LEDs by on, LCD ............................ 95
3.3.2 Truy xut b nh SDRAM/SRAM ..................................... 96
3.3.3 Truy xut b nh Flash (Flash memory)............................. 99
3.3.4 TOOLS Multi-Port SRAM/SDRAM/Flash Controller ... 102
3.3.5 VGA Display Control....................................................... 103
Chng 4.
Hng dn thit k v thc hnh mn hc H thng s trn Kit
DE2 ........................................................................................ 109
4.1 Hng dn thc hnh ................................................................. 109
4.1.1 To mt project trn Quartus II ........................................ 109
4.1.2 Thit k mt mch in n gin ( cng XOR ) dng Schematic trn
Quartus II: ........................................................................ 115
4.1.3 Gn pin............................................................................. 121
4.1.4 M phng mch thit k : ............................................ 126
4.1.5 Programming mch thit k ln FPGA : ...................... 131
4.2 Ni dung thc hnh mn H thng s ........................................ 135
4.2.1 Bi thc hnh s 1 Switchs, Lights, Multiplexers .......... 135
4.2.2 Bi thc hnh s 2 S v cch hin th .......................... 142
4.2.3 Bi thc hnh s 3 Latch, Flip-flop, Register ................ 150
4.2.4 Bi thc hnh s 4 B m (Counters) .......................... 157
4.2.5 Bi thc hnh s 5 Adder, Subtractor, Multiplier of two signed
numbers in 2s- complement form .................................... 161
Chng 5.
Hng dn thit k v thc hnh mn Thit k mch dng Verilog
HDL trn Kit DE2 .............................................................................. 168
5.1 Hng dn thc hnh ................................................................. 168
5.1.1 To mt project trn Quartus II ........................................ 168
5.1.2 Thit k mt mch in n gin (cng XOR) dng Verilog trn
Quartus II: ........................................................................ 174
5.1.3 Gn pin............................................................................. 180
5.1.4 M phng mch thit k : ............................................ 185
5.1.5 Programming mch thit k ln FPGA : ...................... 190
5.2 Ni dung thc hnh mn Thit k mch vi Verilog HDL ......... 194
3
Chng 6.
Hng dn thit k v thc hnh mn Kin trc my tnh nng
cao. ......................................................................................... 227
6.1 Kin thc tng qut v vi x l Nios II ....................................... 227
6.1.1 Gii thiu tng quan Nios II ............................................. 227
6.1.2 Kin trc b x l Nios II................................................. 233
6.1.3 M hnh lp trnh.............................................................. 240
6.2 Hng dn thc hnh trn vi x l Nios II .................................. 273
6.2.1 Nios II System :................................................................ 273
6.2.2 M mt project mi.......................................................... 274
6.3 Ni dung thc hnh mn Kin trc my tnh nng cao ............... 296
6.3.1 Bi thc hnh s 1 Thit k v s dng mt h thng my tnh n
gin .................................................................................. 296
6.3.2 Bi thc hnh s 2 iu khin nhp xut d liu t Vi x
l...301
6.3.3 Bi thc hnh s 3 Tm hiu cch thc hot ng v s dng
Subroutine v Stack ca Vi x l NiosII ........................... 313
4
Chng 7.
MC LC HNH
Hnh 1.1 Board mch DE2 ................................................................................... 20
Hnh 1.2 S khi board mch DE2.................................................................. 22
Hnh 1.3 ng dng trong x l nh v truyn hnh ............................................... 28
Hnh 1.4 ng dng giao tip USB ....................................................................... 29
Hnh 1.5 ng dng trong x l m thanh.............................................................. 29
Hnh 2.1 Mn hnh VGA mc nh ...................................................................... 32
Hnh 2.2 Ch v tr driver cho hardware................................................................ 33
Hnh 2.3 Ch ng dn cho driver ...................................................................... 34
Hnh 2.4 Ch ng dn cho driver ...................................................................... 34
Hnh 2.5 Ch ng dn cho driver ...................................................................... 35
Hnh 2.6 Khng cn kim tra driver ..................................................................... 36
Hnh 2.7 Driver c ci t thnh cng ......................................................... 36
Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode ............................ 38
Hnh 2.9 Thit lp cu hnh cho FPGA thng qua AS mode ................................ 39
Hnh 2.10 Chc nng chng ny cho Push button ................................................ 40
Hnh 2.11 Mch thit k ca switches v push button .......................................... 41
Hnh 2.12 Mapped pins gia switches v FPGA .................................................. 42
Hnh 2.13 Mapped pins gia Push button v FPGA ............................................. 42
Hnh 2.14 Mch thit k ca Leds ........................................................................ 43
Hnh 2.15 Mapped pins gia LEDs v FPGA ...................................................... 44
Hnh 2.16 Led 7 on .......................................................................................... 45
Hnh 2.17 Mch thit k ca LEDs 7 on ........................................................... 46
Hnh 2.18 Mapped pins gia LEDs 7 on v FPGA ........................................... 48
6
Hnh 3.1 Giao din cho vic cu hnh thit k ln FPGA ..................................... 90
Hnh 3.2 Giao din Control Panel ........................................................................ 91
Hnh 3.3 Giao tip gia Control Panel v cc thit b ngoi vi trn FPGA ........... 92
Hnh 3.4 S khi giao tip gia Control Panel v cc thit b ngoi vi ............ 94
Hnh 3.5 Giao din Control Panel iu khin LEDs 7 on ................................. 95
Hnh 3.6 Giao din Control Panel iu khin LEDs n ...................................... 96
Hnh 3.7 Giao din Control Panel iu khin SDRAM ........................................ 97
Hnh 3.8 Giao din Control Panel iu khin FLASH .........................................100
Hnh 3.9 Giao din Control Panel iu khin Multi-Ports ...................................102
Hnh 3.10 Giao din Control Panel iu khin VGA...........................................103
Hnh 3.11 Giao din Control Panel iu khin Multi-ports .................................105
8
18
MC LC BNG
Bng 6.1 Thao tc h tr bi Nios II ALU ..........................................................235
Bng 6.2 Cc thanh ghi a dng ca NIOS II......................................................242
Bng 6.3 Cc bit v tn ca thanh ghi iu khin ................................................244
Bng 6.4 Cho bit chi tit cc trng c nh ngha trong thanh ghi status .....245
Bng 6.5 Cc trng ca thanh ghi iu khin estatus ........................................247
Bng 6.6 Cc trng ca thanh ghi iu khin bstatus ........................................247
Bng 6.7 Nhm lnh chuyn d liu ...................................................................256
Bng 6.8 Lnh logic v s hc ............................................................................257
Bng 6.9 Cc lnh di chuyn...............................................................................259
Bng 6.10 Cc lnh so snh ................................................................................260
Bng 6.11 Lnh dch v xoay ..............................................................................261
Bng 6.12 Nhm lnh nhy v gi hm khng iu kin ....................................262
Bng 6.13 Nhm lnh nhy c iu kin .............................................................263
Bng 6.14 Nhm lnh iu khin khc................................................................264
Bng 6.15 Cc kiu d liu Nios II .....................................................................264
Bng 6.16 M ha trng OP ca cc t lnh .....................................................269
Bng 6.17 M ha trng OPX ca cc t lnh loi R ........................................270
Bng 6.18 Danh sch cc lnh v lnh tng ng ...........................................271
Bng 6.19 Danh sch cc macro hin hnh .........................................................272
19
Chng 1.
35 embedded multipliers
4 PLLs
475 I/O pins
FineLine BGA 672-pin package.
Serial Configuration device v USB Blaster circuit
Rom EPCS16 Serial Configuration device
USB Blaster for programing v user API control
JTAG v AS programming modes
SRAM:
512- Kbyte SRAM memory chip
c t chc nh l 256K x 16 bits
C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
SDRAM:
8-Mbyte Single Data Rate Synchronous Dynamic RAM.
c t chc nh l 1M x 16 bits x 4 banks
C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
Flash memory:
4-Mbyte NOR Flash memory
8-bit data bus
C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
Khe cm th nh SD card:
Truy xut SD card bng mode SPI
23
25
1.3 Ti liu h tr
Phn mm i km vi Kit DE2 bao gm Quartus II Web Edition CAD v
Nios II Embedded Processor. Ngoi ra mt s hng dn v ng dng n gin
gip sinh vin v gio vin hiu r v ng dng ca Kit trong ging dy v nghin
cu.
Thng thng nhng Kit FPGA c sn xut cho mc ch gio dc s
cung cp nhiu c tnh v phn cng cng nh cng c CAD c th to ra
26
27
28
30
Chng 2.
ii.
iii.
iv.
v.
vi.
31
33
By gi, ta chn Search for the best driver in these locations v nhn
Browse xut hin hp thoi nh trong Hnh 2.5. Tm trnh iu khin mong
mun nm trong th mc C:\altera\90\quartus\drivers\usb-blaster\x32. Nhn OK,
sau mn hnh s chuyn v nh trong Hnh 2.4, nhn Next. Lc ny th vic ci
t c bt u, nhng s c mt hp thoi nh trong Hnh 2.6 s xut hin
thng bo rng trnh iu khin cha hon thnh kim tra Window Logo. Nhn
Continue Anyway.
35
dn ny trc v tham kho nhanh nhng thng tin di y hiu r qui trnh s
dng Kit.
Trn kit DE2 c mt b nh EEPROM hot ng ni tip, b nh ny cha
d liu khi to cu hnh ban u cho Cyclon II FPGA. D liu ny s t ng
c ti ln FPGA t EEPROM mi khi ngun in ca Kit DE2 c cung cp.
Sau khi ngun in c cung cp, FPGA s iu khin cc thit b trn Kit DE2
(leds, switchs,) hot ng vi d liu khi to. Sau , ta hon ton c th thay
i cu hnh khi to trn bng vic ti trc tip ln FPGA mt d liu, mt
chng trnh do ta thit k bng phn mm Quartus II. Bn cnh ta cng c th
thay i cu hnh khi to bng vic thay i d liu trn b nh EEPROM. Hai
phng php trn s c lit k di y:
JTAG ( Joint Test Action Group) programming: Trong phng php
ti chng trnh ny, chui bit cu hnh d liu s c ti trc tip
ln Cyclone II FPGA. FPGA s gi cu hnh ny cho n khi ngun
in khng cn c cung cp ln Kit DE2 na.
AS ( Active Serial) Programming: Trong phng php ti chng
trnh ny, chui bit cu hnh s c ti ln b nh EEPROM
EPCS16 hot ng ni tip. D liu lu tr trn b nh ny c nh
khng b mt hoc xa khi khng cn ngun in cung cp. Mi khi
ngun in c cung cp ln Kit DE2, d liu t b nh EEPROM
ny s t ng c ti ln Cyclone II FPGA.
Tng bc ca qu trnh thc thi vic ti chng trnh bng JTAG v AS s
c m t di. c hai phng php trn, Kit DE2 c kt ni vi my tnh
ch thng qua cap USB. Vi kt ni ny, Kit DE2 s c nhn dng bi my tnh
ch nh l mt thit b USB Blaster. Trnh iu khin (driver) dng nhn dng
v giao tip gia my tnh ch vi thit b USB Blaster cn c ci t trn my
37
tnh ch ( trnh by trong phn 2.2). Thit lp cu hnh mi cho FPGA t phn
mm QuartusII trn my tnh thng qua JTAG mode:
Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode
ti mt chui bit d liu cu hnh ln FPGA, ta cn thc thi nhng bc
sau:
1- Cung cp ngun cho Kit DE2.
2- Kt ni cp USB n cng USB Blaster trn Kit DE2.
3- Bt switch RUN/PROG v v tr RUN (pha tri ca Kit).
4- S dng cng c Programmer trn phn mm Quartus II ti file
cha chui bit d liu cu hnh c nh dng .sof ln FPGA.
38
2.3.1
Thit lp cu hnh ban u cho FPGA thng qua vic np cu hnh cho b nh
EPPROM EPCS16 bng AS mode:
39
41
42
2.4.2
Leds
43
2.4.3
LED hin th by on
Kit DE2 cung cp 8 LED hin th by on. LED sng khi tn hiu vo mc
thp v LED tt khi tn hiu vo mc cao. By on hin th trn LED c nh
s t 0 n 6, vi v tr c th hin nh hnh di, ch l du chm (.) trn mi
LED khng c kt ni nn khng th s dng.
45
46
47
49
50
Hnh 2.23 B m a ch
53
Hnh 2.25 B nh lu gi mu k t
Di y l b mu k t c nh sn xut to sn trong ROM ca khi
iu khin v 8 bits d liu m ha ( ta dng ghi vo b nh DDRAM) tng
ng cho tng mu k t. ( 8 bits d liu ny cng chnh l A[11:4] ca a ch m
mu k t c lu trong ROM).
54
Hnh 2.26 B nh lu gi tt c cc mu k t
55
Hnh 2.27 B to mu k t
56
57
58
59
60
2.4.5
Ng vo xung Clock
Kit DE2 cung cp hai ngun tn hiu xung Clock 27 MHz v 50 MHz. Ngoi
ra ta cng c th cung cp ngun xung Clock t bn ngoi thng qua cng ng vo
SMA. S mch kt ni ngun xung Clock v danh sch lit k nhng tn hiu
ngun xung Clock kt ni n nhng Pin tng ng ca Cyclone II FPGA.
61
62
63
64
65
2.4.7
VGA
thi gian (b) ny l khong thi gian hin th (c). Trong sut khong thi gian hin
th, tn hiu RGB iu khin mi pixel hin th dc theo hng. Cui cng, trong
mt khong thi gian gi l front porch (d) nhng tn hiu RGB phi tt i ln
na trc khi tn hiu xung ng vo ng b hng (hsync) k tip xut hin bt
u mt hng mi. c t v thi gian cho tn hiu ng b ct (vsync) c trnh
by tng t trong Hnh 2.34, n ch khc l xung tn hiu vsync cho bit du
hiu kt thc mt khung (frame) mn hnh v bt u mt khung mn hnh k tip.
Hnh 2.35 v Hnh 2.36 m t nhng khong thi gian ng b hng v ct a, b, c
v d ng vi nhng phn gii khc nhau.
Thng tin chi tit v vic s dng chip Video DAC ADV7123 c m t r
trong datasheet ca n m ta c th tm thy trn website ca nh sn xut. Vic
gn pin gia FPGA Cyclone II v chip ADV7123 c lit k trong Hnh 2.37.
68
69
70
2.4.8
Bo mch DE2 cung cp vic x l m thanh cht lng cao 24 bit thng qua
mt chip Wolfson WM8731 audio CODEC (encoder/DECcoder). Con chip ny h
tr ng vo microphone, ng vo v ng ra c kh nng iu chnh tc ly mu
t 8 kHz n 96 kHz. Chip WM8731 c kt ni vi cc pin trn FPGA Cyclone
II thng qua giao thc giao tip bus ni tip I2C. S mch x l m thanh c
th hin trn Hnh 2.38, v vic gn pin trn FPGA c lit k trong bng Hnh
2.39. Thng tin chi tit v cch thc s dng chip WM8731 CODEC c trnh
by trn datasheet ca n v ta cng c th tm thy trn website ca nh sn xut.
71
Bo mch DE2 s dng chip truyn nhn d liu MAX232 v cng giao tip
D-SUB 9 pin cho vic giao tip RS-232. Thng tin chi tit v cch thc s dng
72
chip MAX232 cng nh cng giao tip D-SUB c trnh by trn datasheet ca
n v ta cng c th tm thy trn website ca nh sn xut. Hnh 2.40 m t mch
kt ni cng ni tip RS-232, v vic gn pin cho FPGA Cyclone II c lit k
trong Hnh 2.41
73
Hnh 2.42 Mch thit k giao tip gia cng PS/2 v FPGA
74
75
76
77
2.4.13 TV Encoder
78
Bo mch DE2 cung cp ng thi hai giao tip USB host v device bng
vic s dng mt chip iu khin USB ISP1362 ca Philips. B iu khin host v
device tng thch vi chun giao tip USB 2.0, h tr vic truyn d liu vi tc
cao (12 Mbit/s) v tc thp (1.5 Mbit/s). Hnh 2.49 m t s mch kt ni
USB. Hnh 2.50 lit k vic gn pin kt ni t chip ISP1362 n FPGA Cyclone II.
Thng tin chi tit v cch thc s dng chip ISP1362 c trnh by trn
datasheet ca n v ta cng c th tm thy trn website ca nh sn xut. Phn
thch thc nht ca mt ng dng USB l lun cn mt phn mm iu khin.
79
Hnh 2.49 Mch thit k giao tip USB gia chip ISP1362 v FPGA
80
81
Hnh 2.51 Mch giao tip gia cng hng ngoi v FPGA
82
83
84
85
86
87
88
Chng 3.
DE2_USB_API.sof
ii.
DE2_control_panel.exe
kch hot trnh ng dng Control Panel, ta cn thc hin nhng bc sau:
1- Kt ni cp USB n cng USB Blaster. Cung cp ngun 9V. Bt
ngun ln v tr ON.
2- Chuyn switch RUN/PROG v tr RUN.
3- M phn mm Quartus II .
4- Chn Tools Programmer, ta s c hnh sau:
89
90
91
Hnh 3.3 Giao tip gia Control Panel v cc thit b ngoi vi trn FPGA
Trong IP thc thi chc nng iu khin. IP ny c thit k trn FPGA.
N lin lc vi trnh ng dng DE2 Control Panel trn computer thng qua cng
USB Blaster. Giao din ha c s dng truyn lnh xung mch iu
khin. Cng vic ca IP l qun l tt c nhng yu cu v thc thi vic truyn d
liu gia my tnh v Kit DE2.
Trnh ng dng DE2 Control Panel c th c dng thay i gi tr hin
th trn LEDs by on, bt LEDs, giao tip vi bn phm PS/2, c v ghi SRAM,
Flash Memory v SDRAM, ti hnh nh ln mn hnh VGA, ti nhc vo b nh
v nghe nhc qua audio DAC. c tnh c v ghi mt byte hay ton b file t hay
n Flash Memory cho php ngi s dng pht trin nhiu ng dng multimedia (
Flash Audio Player, Flash Picture Viewer) m khng cn quan tm n cch to ra
mt Flash Memory Programmer.
92
93
Hnh 3.4 S khi giao tip gia Control Panel v cc thit b ngoi vi
Ta c th kt ni nhng module ca mnh n mt trong nhng User
Ports ca trnh iu khin SRAM/SDRAM/Flash memory, sau ta c th ti d
liu nh phn vo trong SRAM/SDRAM/Flash memory. Khi d liu c ti
vo trong SRAM/SDRAM/Flash memory, ta c th thit lp li cu hnh cho cc
khi trnh iu khin SRAM/SDRAM/Flash memory nhng khi ny c th
c/ghi d liu ca SRAM/SDRAM/Flash memory thng qua User Ports (
thit lp li cu hnh cho nhng khi ny i hi ta phi c kin thc v Verilog).
94
95
97
98
3.3.3
101
3.3.4
Chn Tab TOOLS trn ca s Control Panel s cho php ta chn User
Ports. Chng ta s mt v d c th bng vic thc thi mt Flash Music Player. Ta
ti mt file nhc vo trong Flash memory. User Port 1 ca trnh iu khin Flash
memory c dng truyn file nhc n trnh iu khin Audio DAC v xut ra
output.
thc hin v d trn ta thc thi theo cc bc sau:
1. Xa b nh Flash . Sau ghi file nhc (music.wav) ln b nh
Flash (Trnh by trong phn 3.3.3 )
2. Trn Control Panel, chn Tab TOOLS, mt ca s nh hnh di
s xut hin.
3.3.5
103
104
105
106
108
Chng 4.
Bc 1.
Bc 2.
109
Bc 3.
Nhn Next
110
Bc 5.
cha to s c t ng to).
Bc 6.
Nhp tn ca project.
Bc 7.
project).
Bc 8.
Nhn Next
Bc 9.
Bc 10.
Nhn Yes
111
Bc 11.
Nhn Next
Bc 12.
112
Bc 13.
Nhn Next
Bc 15.
Nhn Next
113
(H ca Chip
Bc 16.
4.1.2
Thit k mt mch in n gin ( cng XOR ) dng Schematic trn Quartus II:
Bc 1.
M File New
Bc 2.
115
Bc 3.
Bc 1.
116
Bc 3.
Kt ni linh kin
Nhng linh kin trong mch phi c kt ni bng dy in. Nhn chn
biu tng
mt bng bo co c to ra nh hnh di
Bc 2.
Gn pin
V ta cha thc hin gn pin trn FPGA cho linh kin trong mch in
thit k trn nn khi thc hin bin dch th trnh bin dch Quartus II gn
chn ca linh kin vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gi s trong
thit k cng XOR n gin trn, sau khi thit k c bin dch v np ln
FPGA, ta mun hai ng vo x1, x2 c iu khin bi hai switch SW0 v SW1
cn kt qu ng ra f s c th hin trn led LEDG0 (SW0, SW1, LEDG0 c
ghi trn Kit). Mt khc ta bit switch SW0 c kt ni c nh vi pin N25 ca
FPGA, tng t vy switch SW1 c kt ni c nh vi pin N25 ca FPGA v
led LEDG0 c kt ni c nh vi pin AE22 ca FPGA. thc hin c iu
ta phi gn chn linh kin trn mch (x1, x2, f) vi pin tng ng trn FPGA
(N25, N26, AE22). gn pin ta thc hin cc bc sau
Bc 1.
hin
121
Bc 2.
122
Bc 4.
Bc 5.
Bc 6.
Bc 7.
To, Location
x1, PIN_N25
x2, PIN_N26
f, PIN_AE22
Nu ta dng Microsoft Excel, th ta s c format nh sau:
sau
Bc 1.
Bc 2.
nhn OK.
thun tin cho ngi s dng Altera cung cp mt file CSV c tn
DE2_pin_assignments, file ny lit k tt c cc pin ca FPGA, c format nh sau:
125
Bc 1.
Waveform File
126
Bc 2.
Nhn OK
Bc 3.
Bc 4.
Bc 5.
Bc 6.
127
Bc 8.
Bc 9.
Bc 10.
Selected Nodes
Bc 11.
Nhn OK
128
Bc 12.
Bc 13.
Bc 14.
Bc 15.
(gi s ta mun trong khong thi gian t 40ns -> 60 ns , SW0 signal c
gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns ->
60ns.
Bc 16.
129
Bc 19.
Bc 20.
Bc 21.
Bc 22.
Bc 23.
Nhn OK
130
Bc 24.
Simulation Netlist
Bc 25.
Bc 26.
4.1.5
Bc 1.
t driver trc ).
Bc 2.
Bc 4.
131
Bc 5.
Hnh 4.37 Thit lp cng giao tip gia kit DE2 v Computer
Bc 6.
Nhn Close
Bc 7.
Bc 8.
chy Compilation).
Bc 9.
132
Bc 10.
Nhn Start.
Bc 11.
Bc 13.
Bc 14.
Bc 15.
Bc 16.
Bc 17.
Bc 19.
Bc 20.
Bc 21.
Bc 22.
Bc 23.
134
Bc 25.
Bc 26.
Bc 27.
Bc 2.
Bc 3.
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
4.2.1.2 Phn 2
Bc 2.
Bc 3.
To
mt
project
user_dir/lab1/lab1_part2
Bc 4.
137
Quartus
mi,
tn:
Bc 6.
hot ng ca mch.
Bc 7.
4.2.1.3 Phn 3
138
Bc 2.
To
mt
project
Quartus
mi,
tn:
user_dir/lab1/lab1_part3
Bc 3.
Bc 5.
hot ng ca mch.
139
Bc 6.
4.2.1.4 Phn 4
Bc 1.
tch cc mc thp).
Bc 2.
trn.
Bc 3.
To
mt
project
Quartus
mi,
tn:
user_dir/lab1/lab1_part4
Bc 4.
Bc 5.
Bc 6.
hot ng ca mch.
Bc 7.
4.2.1.5 Phn 5
141
4.2.2
Bc 2.
142
Bc 3.
Symbol Tool
143
Bc 2.
Bc 3.
Bc 4.
144
Bc 5.
hot ng ca mch.
Bc 6.
Ch : Sinh vin chun b trc nhng cng vic sau (Khng c bi chun
b khng c vo lp lm th nghim tnh vng bui )
c v thc hin cc bc t 1 n 5 nh
4.2.2.2 Phn 2
145
Bc 2.
Bc 3.
Bc 4.
Bc 5.
Bc 6.
Bc 7.
hot ng ca mch.
Bc 8.
Ch : Sinh vin chun b trc nhng cng vic sau (Khng c bi chun
b khng c vo lp lm th nghim Tnh vng bui )
c v thc hin cc bc t 1 n 7
4.2.2.3 Phn 3
Bc 1.
Bc 3.
Bc 4.
Gn pin
Input a3a2a1a0 c gn ti SW[3:0], input b3b2b1b0 c gn
ti SW[7:4], input cin c gn ti SW[8].
Output s3s2s1s0 v cout ln lt c gn ti LEDG[3:0] v
LEDG[4].
Kt ni cc SW ra LEDR kim tra gi tr nhp vo.
Bc 6.
Bc 7.
hot ng ca mch.
Bc 8.
Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim Tnh vng bui )
147
Thc hin cc bc t 1 n 6
4.2.2.4 Phn 4
Bc 2.
mt ch s A, B v 1 bit cin.
Bc 3.
Gn pin
S dng SW[3:0] cho A, SW[7:4] cho B va SW[8] cho cin. Kt
ni cc SW ny ra LEDR kim tra kt qu. Gi tr BCD ca A
c hin th trn HEX6, ca B hin th trn HEX4.
Output l s BCD 2 ch s S1S0.
S dng cc LEDG hin th kt qu ca 4 bit tng v s d.
Gi tr BCD ca S1S0 c hin th trn HEX1 v HEX0
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim tnh vng bui )
Thc hin cc bc t 1 n 5
4.2.2.5 Phn 5
148
Bc 2.
Gn pin
S dng SW[15:8] cho A1A0, SW[7:0] cho B1B0. Kt ni cc
SW ny ra LEDR kim tra kt qu. Gi tr BCD ca A1A0
c hin th trn HEX7 v HEX6, ca B1B0 hin th trn
HEX5 v HEX4.
Output l s BCD 3 ch s S1S0 S2.
Gi tr BCD ca S1S0 S2 c hin th trn HEX2, HEX1 v
HEX0
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim Tnh vng bui )
Thc hin cc bc t 1 n 5
149
4.2.3
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tn:
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Bc 2.
Bc 3.
150
Bc 5.
hot ng ca mch.
Bc 6.
4.2.3.2 Phn 2
151
Bc 1.
To
mt
project
Quartus
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tn:
user_dir/lab3/lab3_part2
Bc 2.
Bc 4.
hot ng ca mch.
Bc 5.
4.2.3.3 Phn 3
Bc 1.
To
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project
Quartus
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tn:
user_dir/lab3/lab3_part3
Bc 2.
Bc 4.
hot ng ca mch.
Bc 5.
153
4.2.3.4 Phn 4
Cho mch sau vi mt D-FF tch cc mc cao, mt D-FF tch cc cnh ln,
mt D-FF tch cc cnh xung v mt D-FF tch cc mc thp. Thit k mch to
D-FF tch cc cnh ln v D-FF tch cc cnh xung v D-FF tch cc mc thp (
c th tham kho trn Internet), sau thit k mch nh hnh di:
154
To
mt
project
Quartus
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tn:
user_dir/lab3/lab3_part4
Bc 2.
Bc 4.
hot ng ca mch.
Bc 5.
155
4.2.3.5 Phn 5
4.2.4
To
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project
user_dir/lab4/lab4_part1
157
Quartus
mi,
tn:
Bc 2.
Thit k 3 b m vi yu cu nh sau:
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
Sinh vin thc hin trc cc cng vic sau (khng bi chun b khng c
vo lp lm th nghim Tnh vng bui )
T bc 1 n bc 5
4.2.4.2 Phn 2
To
mt
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user_dir/lab4/lab4_part2
Bc 2.
Thit k cc b m vi yu cu nh sau:
158
tn:
Bc 5.
hot ng ca mch.
Bc 6.
Sinh vin thc hin trc cc cng vic sau (khng bi chun b khng c
vo lp lm th nghim Tnh vng bui )
Thc hin cc cng vic t bc 1 n bc 5
Nu nhn xt u khuyt im ca b m tun t v b m song
song
4.2.4.3 Phn 3
159
160
4.2.5
Bi thc hnh s 5 Adder, Subtractor, Multiplier of two signed numbers in 2scomplement form
To
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tn:
user_dir/lab5/lab5_part1
Bc 2.
dng b -2.
161
Bc 3.
Bc 4.
162
Bc 5.
hot ng ca mch.
Bc 6.
4.2.5.2 Phn 2
Bc 2.
dng b -2.
163
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
4.2.5.3 Phn 3
To
mt
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tn:
user_dir/lab5/lab5_part3
Bc 2.
dng b -2.
Bc 3.
Bc 5.
hot ng ca mch.
Bc 6.
166
167
Chng 5.
Bc 1.
Bc 2.
168
Bc 3.
Bc 4.
Nhn Next
169
Bc 5.
nu cha to s c t ng to ).
Bc 6.
Nhp tn ca project.
Bc 7.
project ).
Bc 8.
Nhn Next
Bc 9.
Bc 10.
Nhn Yes
Bc 11.
Nhn Next
171
Bc 12.
Bc 13.
Nhn Next
Bc 15.
Nhn Next
172
(H ca Chip
Bc 16.
5.1.2
Thit k mt mch in n gin (cng XOR) dng Verilog trn Quartus II:
M File New
Bc 2.
174
Bc 4.
175
Bc 5.
Assignments Settings
Bc 2.
Bc 3.
Nhn vo button
177
Hnh 5.18 Ch ng dn
Bc 4.
.
5.1.2.1 Trnh bin dch
mt bng bo co c to ra nh hnh di
178
Bc 2.
c.
5.1.2.2 Message window
179
th tm hiu thm thng tin v li cng nh cnh bo bng cch nhn chn vo
thng bo ri nhn phm F1 trn bn phm.
5.1.3
Gn pin
V ta cha thc hin gn pin trn FPGA cho linh kin trong mch in
thit k trn nn khi thc hin bin dch th trnh bin dch Quartus II gn
chn ca linh kin vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gi s trong
thit k cng XOR n gin trn, sau khi thit k c bin dch v np ln
FPGA, ta mun hai ng vo x1, x2 c iu khin bi hai switch SW0 v SW1
cn kt qu ng ra f s c th hin trn led LEDG0 (SW0, SW1, LEDG0 c
ghi trn Kit). Mt khc ta bit switch SW0 c kt ni c nh vi pin N25 ca
FPGA, tng t vy switch SW1 c kt ni c nh vi pin N25 ca FPGA v
led LEDG0 c kt ni c nh vi pin AE22 ca FPGA. thc hin c iu
ta phi gn chn linh kin trn mch (x1, x2, f) vi pin tng ng trn FPGA
(N25, N26, AE22). gn pin ta thc hin cc bc sau
Bc 1.
hin
180
Bc 2.
181
Bc 4.
Bc 5.
Bc 6.
Bc 7.
To, Location
x1, PIN_N25
x2, PIN_N26
f, PIN_AE22
Nu ta dng Microsoft Excel, th ta s c format nh sau:
sau
Bc 8.
Bc 9.
nhn OK.
thun tin cho ngi s dng Altera cung cp mt file CSV c tn
DE2_pin_assignments, file ny lit k tt c cc pin ca FPGA, c format nh sau:
184
Bc 1.
Waveform File
185
Bc 2.
Nhn OK
Bc 3.
Bc 4.
Bc 5.
Bc 6.
186
Bc 8.
Bc 9.
Bc 10.
Selected Nodes
Bc 11.
Nhn OK
187
Bc 12.
Bc 13.
Bc 14.
Bc 15.
(gi s ta mun trong khong thi gian t 40ns -> 60 ns , SW0 signal c
gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns ->
60ns.
Bc 16.
188
Bc 19.
Bc 20.
Bc 21.
Bc 22.
Bc 23.
Nhn OK
189
Bc 24.
Simulation Netlist
Bc 25.
Bc 26.
5.1.5
Bc 1.
t driver trc ).
Bc 2.
Bc 4.
190
Bc 5.
Hnh 5.37 Thit lp cng giao tip gia kit DE2 v Computer
Bc 6.
Nhn Close
Bc 7.
Bc 8.
chy Compilation).
Bc 9.
191
Bc 10.
Nhn Start.
Bc 11.
Bc 4.
Bc 5.
Bc 6.
Bc 7.
Bc 8.
Bc 10.
Bc 11.
Bc 12.
Bc 13.
Bc 14.
193
Bc 16.
Bc 17.
Bc 18.
Mc ch:
Thc hnh thit k mch t hp dng nhn hai s khng du 4 bits.
Thc hnh thit k mch tun t dng thanh ghi v b m.
5.2.1.1 Phn 1
To
mt
project
user_dir/lab1/lab1_part1
194
Quartus
mi,
tn:
Bc 2.
Verilog.
Bc 3.
Gn pin nh sau
Dng switches SW11- 8 nhp s A v switches SW3-0
nhp s B. Gi tr ca A v B c hin th trn Led 7 on
HEX6 v HEX4 di dng s Hexa. Kt qu php nhn C=A*B
c hin th trn HEX1 v HEX0 cng di dng Hexa.
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
M rng mch nhn sang 4 bit sang mch nhn 8 bit. Dng SW15-8 nhp
s A v switches SW7-0 nhp s B. . Gi tr ca A v B c hin th tng
ng trn cc Led 7 on HEX7-6 v HEX5-4 di dng s Hexa. Kt qu php
nhn C=A*B c hin th trn HEX3-0 cng di dng Hexa.
Cc bc thc hin
Bc 1.
To
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tn:
user_dir/lab1/lab1_part2
Bc 2.
Verilog.
Bc 3.
Gn pin nh sau
195
Bc 5.
hot ng ca mch.
Bc 6.
Part III
Ta mun hin th mt gi tr hexadecimal ca mt s A 16 bit trn bn Led 7
on HEX7-4 v hin th s B 16 bit trn bn Led 7 on HEX3-0. Gi tr ca A
v B u c cung cp bi SW15-0. Mun lm c iu ny th trc ht ta
phi nhp gi tr A t SW15-0 v phi lu tr gi tr ny vo thanh ghi trc khi
nhp gi tr mi cho B.
Cc bc thc hin
Bc 1.
To
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Bc 2.
Gn pin nh sau
196
Bc 5.
hot ng ca mch.
Bc 6.
To
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Bc 2.
Gn pin nh sau
S dng Led 7 on HEX0 hin th s.
CLK_50 gn cho xung clock ca counter.
Bc 4.
Bc 5.
hot ng ca mch.
197
Bc 6.
5.2.2
Mc ch:
Thc hnh v tm hiu phng php thit k latches, flip-flops v
counter.
5.2.2.1 Phn 1
Trong Hnh 5.42 m t mt mch latch RS. Pha di Hnh 5.42 th hin hai
phong cch code Verilog c th dng m t mch latch RS trn. Phn a m t
198
199
// RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /*synthesis keep */;
assign R_g = R & Clk;
assign S_g = S & Clk;
assign Qa = !(R_g | Qb);
assign Qb = !(S_g | Qa);
assign Q = Qa;
endmodule
b. Dng cc biu thc logic m t mch latch RS.
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Bc 2.
Bc 4.
hot ng ca mch.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
201
5.2.2.2 Phn 2
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Bc 2.
Gn pin nh sau
Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Q.
Bc 4.
Bc 5.
Technology Viewer.
Bc 6.
hot ng ca mch.
Bc 7.
5.2.2.3 Phn 3
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user_dir/lab2/lab2_part3
Bc 2.
flop trn, gi (instantiate) module D latch trn phn 2 thc thi D flipflop ny.
Bc 3.
Gn pin nh sau
Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Q.
Bc 4.
Bc 5.
Technology Viewer.
203
Bc 6.
hot ng ca mch.
Bc 7.
To
mt
project
user_dir/lab2/lab2_part4
204
Quartus
mi,
tn:
Bc 2.
Gn pin nh sau
Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Qa, LEDR1
c gn n Qb, LEDR2 c gn n Qc.
Bc 4.
Bc 5.
Technology Viewer.
Bc 6.
hot ng ca mch.
Bc 7.
5.2.2.5 Phn 5
To
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tn:
user_dir/lab3/lab3_part5
Bc 2.
Gn pin nh sau
Dng switches SW0 iu khin tn hiu Enable v switches
SW1 lm tn hiu xung Reset.
KEY0 lm tn hiu xung Clock.
Bn led 7 on HEX3-0 hin th gi tr m theo m hexa.
Bc 4.
206
Bc 5.
hot ng ca mch.
Bc 7.
207
5.2.3
Bi thc hnh s 3 Thit k h thng s dng xung Clock thi gian thc
Mc ch:
Thc hnh thit k v s dng xung Clock thi gian thc
5.2.3.1 Phn 1
To
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tn:
user_dir/lab3/lab3_part1
Bc 2.
Verilog
Bc 3.
Gn pin nh sau
Ng ra b m BCD ni n 3 led 7 on HEX2-0
Chn Reset_n ni n KEY0
Bc 4.
Bc 5.
hot ng ca mch.
208
Bc 6.
To
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tn:
user_dir/lab3/lab3_part2
Bc 2.
Verilog
Bc 3.
Gn pin nh sau
Ng ra ch gi ni n 2 led 7 on HEX7-6
Ng ra ch pht ni n 2 led 7 on HEX5-4
Ng ra ch giy ni n 2 led 7 on HEX3-2
SW15-0 ni n chn thit lp gi tr gi, pht cho ng h.
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
5.2.4
Mc ch:
Thc hnh v tm hiu thit k h thng s dng State machines.
5.2.4.1 Phn 1
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tn:
user_dir/lab4/lab4_part1
Bc 2.
Gn pin
SW0 gn n chn input w.
LEDG0 gn n chn output z
KEY0 gn n chn xung Clock
Bc 4.
Bc 5.
Technology Viewer.
Bc 6.
hot ng ca mch.
210
To
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tn:
user_dir/lab4/lab4_part2
Bc 2.
Gn pin nh sau
Dng switches SW0, SW1 iu khin tn hiu w0, w1.
KEY0 iu khin xung Clock.
Ng ra b m c hin th trn Led 7 on HEX0 di dng
s HEX.
Bc 4.
Bc 5.
Technology Viewer.
Bc 6.
hot ng ca mch.
Bc 7.
5.2.4.3 Phn 3
To
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tn:
user_dir/lab3/lab3_part3
Bc 2.
Gn pin nh sau
Dng HEX0-HEX7 hin k t.
Dng KEY2, KEY3 lm chn input iu khin tc dch.
Dng xung Clock_50 to cc khong delay.
Bc 4.
212
Bc 5.
Technology Viewer.
Bc 6.
hot ng ca mch.
Bc 7.
213
5.2.5
Bi thc hnh s 5 Thc hnh tm hiu phng php thit k onchip Memory trn
FPGA v phng php s dng offchip Memory
Mc ch:
Trong nhng h thng my tnh, lu tr chng trnh v lu tr d
liu n lun cn mt b nh vi dung lng lu tr. Nu mt h
thng c thc thi trn FPGA, th n c th s dng b nh c sn
trn FPGA (onchip memory) do nh sn xut h tr sn hoc ta cng
c th thit k b nh ngay trn FPGA (onchip memory). Tuy nhin,
nu dung lng b nh trn FPGA khng th mt b nh bn ngoi
FPGA (offchip memory) s cn c s dng. Do , trong phn thc
hnh ny ta s tm hiu ba vn sau:
Tm hiu cch thc hin thc mt memory trn FPGA (onchip
memory)
Tm hiu cch thc s dng mt offchip memory (SRAM chip trn
kit DE2).
Chy m phng trn ModelSim
5.2.5.1 Phn 1
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Bc 2.
to ra RAM nh yu cu.
Tools MegaWizard Plug-in Manager
216
217
218
220
221
222
Bc 4.
To
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user_dir/lab5/lab5_part2
Bc 2.
Gn pin nh sau
Dng switches SW[7:0] lm tn hiu d liu ng vo.
Dng switches SW[15:11] lm tn hiu a ch.
Dng HEX0, HEX1 hin th tn hiu d liu ng vo.
Dng HEX2, HEX3 hin th tn hiu a ch.
Dng HEX4, HEX5 hin th tn hiu ng ra.
Dng SW[17] lm tn hiu WREN (khi WREN = 1, cho php
ghi, WREN = 0, cho php c)
Dng KEY0 lm xung CLK.
Bc 4.
Bc 5.
hot ng ca mch.
223
Bc 6.
To
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user_dir/lab5/lab5_part3
Bc 2.
Bc 3.
Gn pin nh sau
Dng switches SW[7:0] lm tn hiu d liu ng vo.
Dng switches SW[15:11] lm tn hiu a ch.
Dng HEX0, HEX1 hin th tn hiu d liu ng vo.
Dng HEX2, HEX3 hin th tn hiu a ch.
Dng HEX4, HEX5 hin th tn hiu ng ra.
Dng SW[17] lm tn hiu WREN (khi WREN = 1, cho php
ghi, WREN = 0, cho php c)
Dng KEY0 lm xung CLK.
Bc 4.
Bc 5.
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Bc 2.
Bc 3.
Gn pin nh sau
Dng switches SW[7:0] lm tn hiu d liu ng vo
DATA[15:0] = {8h00,SW[7:0]}.
Dng switches SW[15:8] lm tn hiu a ch (vi 8 a ch ny
s gii m ra mt phn dung lng ca SRAM, ADDR[17:0] =
{10h000,SW[15:8]}.
Dng HEX0-HEX3 hin th tn hiu ng ra.
Dng KEY[0] lm tn hiu /OE.
Dng KEY[1] lm tn hiu /WE
Ni mc logic 0 cho c /LB v /UB.
Bc 4.
Bc 5.
hot ng ca mch.
Bc 6.
END
226
Chng 6.
- n v bo v b nh (MPU) ty chn.
- Mi trng pht trin phn mm da trn chui cng c GNU C/C++
v Eclipse IDE.
- Tch hp vi Altera's SignalTap II Embedded Logic Analyzer, cho
php phn tch thi gian thc cc lnh v d liu cng vi cc tn hiu
khc trong thit k FPGA.
227
6.1.1.2
Phn ny gii thiu nhng khi nim ring ca Nios II nhm cung cp nn
tng cc nh thit k phn cng c th iu chnh h thng mt cch linh hot.
6.1.1.2.1 B x l nhn mm kh cu hnh
230
232
6.1.2
- B nh m (d liu v lnh)
- Interface cho b nh tightly-coupled cho lnh v d liu
- JTAG debug module
Kin trc Nios II h tr mt tp tin thanh ghi phng, cha 32 thanh ghi a
dng 32-bit, v ln n 32 thanh ghi iu khin 32-bit. Kin trc ny h tr ch
gim st (supervisor mode) v ch ngi dng (user mode), cho php bo v
234
cc thanh ghi iu khin t cc ng dng sai. Trong tng lai, kin trc Nios II cho
php b sung nhng thanh ghi chm ng.
6.1.2.3
n v lun l s hc (ALU)
Kin trc ca Nios II h tr cc bus d liu v lnh ring bit, nh kin trc
Harvard. Bus d liu thng qua cng d liu chnh kt ni vi c b nh v ngoi
vi, trong khi bus lnh thng qua cng lnh chnh ch kt ni vi b nh.
Cu trc Nios II truy xut I/O v b nh theo dng: c hai b nh d liu v
thit b ngoi vi u c nh x vo khng gian a ch ca cng d liu chnh.
Kin trc lu tr ca Nios II theo dng little endian, cc t v na t c lu tr
trong b nh vi bytes cao th lu tr a ch cao.
236
6.1.2.6 B nh m (cache)
6.1.2.7 B nh tightly-coupled
238
6.1.2.9
n v bo v b nh (MPU)
239
6.1.3
M hnh lp trnh
User mode:
User mode sn sng ch khi trong thit k ca b x l Nios II c MMU
hoc MPU. User mode thng thng ch h tr cc h iu hnh v cc h iu
hnh u chy cc ng dng user mode. Cc kh nng ca b x l trong user
mode l tp con trong supervisor mode, tc ch mt tp con cc lnh trong tp lnh
ca Nios II c th s dng trong user mode.
H iu hnh quyt nh vng b nh no c th truy cp bi cc ng dng
trong user mode. Vic c gng truy cp vo cc v tr nh m cc ng dng trong
user mode khng c php s gy ra mt ngoi l. Code chy trong user mode s
dng li gi h thng yu cu h iu hnh thc hin cc hot ng I/O, qun l
b nh, hay truy cp n cc chc nng h thng khc trong supervisor mode
241
242
243
Bng 6.4 Cho bit chi tit cc trng c nh ngha trong thanh ghi status
245
Ghi ch:
(1) EH v U cng l bit 1 th khng c php v c th s cho ra kt qu
sai.
Thanh ghi estatus
Thanh ghi estatus lm nhim v lu gi mt bn sao ca thanh ghi status
trong sut qu trnh x l ngoi l dng non-break. Bng 6.5 cho thy cch b tr
ca thanh ghi estatus.
246
247
Ngoi l l qu trnh chuyn quyn iu khin ra khi lung thc thi bnh
thng ca chng trnh, c to ra bi mt s kin no , bn trong hay bn
ngoi b x l m i hi phi c ch ngay lp tc. X l ngoi l l ng ph
vi mt ngoi l v sau a h thng tr li trng thi trc khi ngoi l xy ra.
Cc ngoi l trong Nios II thuc mt trong cc loi sau:
- Ngoi l khi ng li (Reset exceptions)
- Ngoi l break (Break exceptions)
- Ngoi l ngt (Interrupt exceptions)
- Ngoi l lin quan n lnh (Instruction-related exceptions)
248
- Mt u vo interrupt c tc ng ln 1 (irqn)
- Bit th n tng ng ca thanh ghi ienable bng 1.
Trong thi gian x l ngt cng, b x l xa bit PIE v 0, khng cho php
thm cc interrupt, sau thc hin cc bc khc x l ngt.
Gi tr ca thanh ghi iu khin ipending ch ra interrupt no ang ch gii
quyt. Hnh 3-1 cho thy mi quan h gia ipending, ienable, PIE, v s pht sinh
ca mt interrupt.
Nios II c mt on chng trnh con dng xc nh xem trong s nhng
ngt ang ch gii quyt, ngt no c u tin cao nht, v sau chuyn quyn
iu khin cho on chng trnh x l ngt (cn gi l ISR _ interrupt service
routine).
251
Phn ny gii thiu cc lnh ca Nios II, c phn nhm theo tng dng
hot ng ca chng
6.1.3.6.1 Nhm lnh chuyn d liu
Kin trc Nios II l kin trc load-store. Lnh load (ly d liu) v store (lu
tr d liu) nm gi tt c cc hot ng di chuyn d liu gia cc thanh ghi, b
nh v cc thit b ngoi vi. Bng 6.7 lit k cc lnh dng load v store (32 bit)
255
Nhm lnh logic h tr cho cc hot ng: and, or, xor, v nor. Nhm lnh s
hc h tr thao tc: cng, tr, nhn, chia. Tham kho
256
Bng 6.8.
257
258
Nhm lnh ny thc hin vic so snh hai thanh ghi hoc thanh ghi vi mt
gi tr tc thi; kt qu l 1(nu ng) hoc 0 (nu sai) c ghi ra thanh ghi kt
qu. Tham kho Bng 6.10
259
Nhm lnh ny thc hin cc php ton dch v xoay. S bit xoay hoc
dch c ch r trong mt thanh ghi hoc mt s tc thi. Tham kho Bng 6.11
260
261
262
263
Kin trc stack trong Nios II pht trin theo hng xung, hai con tr cn
quan tm khi lm vic vi stack l con tr stack (stack pointer) v con tr khung
(frame pointer). Stack pointer ch ti khe (slot) c dng cui cng. Frame
pointer tr n frame pointer c lu gn nh ca stack.
Frame pointer c cung cp h tr cho cng vic debug. Nu khng cn
debug, frame pointer c th b ra khi code. Dng ty chn fomit-frame-pointer
cho trnh bin dch, thanh ghi fp s c xem nh thanh ghi tm.
Trnh bin dch chu trch nhim lu tr nhng thanh ghi m cn c lu
trong mt hm. Nu c nhng thanh ghi nh vy, chng s c lu trong stack, t
265
a ch cao n thp theo th t sau: ra, fp, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12,
r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, gp, v sp. Khng gian
stack khng c cp cho cc thanh ghi m khng c lu. Hnh 6.4 trnh by
mt v d hm a() gi hm b(), v stack c th hin trc li gi v sau dn
nhp ca cu trc khung hin ti. Trong trng hp ny, hm a() gi hm b(), v
stack c th hin trc v ngay sau li gi hm.
266
267
268
269
6.1.3.10 Lnh gi
270
6.1.3.11 Cc Macros
272
Nios II System :
M mt project mi
Bc 2.
Bc 3.
Nhn OK
275
Bc 5.
Bc 6.
Bc 7.
Nhn Add
276
Bc 8.
Bc 9.
Nhn Finish
Bc 10.
Nhn Add
277
Bc 12.
Bc 13.
Nhn Finish
278
Bc 14.
Bc 15.
Bc 16.
Bc 17.
Nhn Finish
Bc 18.
Bc 20.
Bc 21.
Nhn Finish
Bc 22.
Bc 23.
Nhn Finish.
Bc 24.
282
Bc 27.
Bc 29.
Bc 30.
Nhn Generate
Bc 31.
Bc 35.
Tools Programmer
Bc 40.
Nhn OK
285
Bc 41.
Bc 42.
Nhn Start
Bc 2.
287
Bc 4.
Bc 5.
Bc 6.
Bc 7.
Nhn OK
Bc 8.
Bc 9.
Nhn OK
Bc 12.
Bc 13.
289
Bc 14.
290
Cng thc hin tng t nhng bc trn , ch khc o ch khi chn Program
Type thay v chn Assembly thi ta chn C
Quan st kt qu, ta thy n cng cho kt qu tng t .
Chng ta c th dng Altera Monitor Program debug chng trnh:
Ta c th thc thi chng trnh tng bng vic thc thi tng lnh
mt theo tun t.
Ta c th dng vic thc thi mt chng trnh ti mt v tr lnh
no bng vic to ra mt breakpoint.
Ta c th thay i gi tr ca Register.
Ta c th thay i gi tr ca memory.
Thc thi chng trnh tng bng vic thc thi tng lnh mt theo
tun t:
Action Restart
Action Single step
291
292
Bc 2.
chng trnh.
Bc 3.
Bc 4.
Bc 5.
Bc 2.
trong processor).
293
Thc thi li chng trnh kim tra xem chng trnh c thc
294
Bc 2.
i.
Bc 3.
Nhp gi tr cn thay i.
Bc 4.
295
Mc ch:
Xy dng mt h thng vi x l n gin
Lm quen cch s dng cng c debug Altera Monitor Program.
6.3.1.1 Phn 1
Bc 2.
Bc 3.
Generate system.
Bc 5.
Bc 6.
Compile project
Bc 8.
Program
configure
nios
system
ln
Cyclone
II
.include "nios_macros.s"
.text
.equ TEST_NUM, 0x90abcdef
297
.global _start
_start:
movia r7, TEST_NUM
mov r4, r7
STRING_COUNTER:
mov r2, r0
STRING_COUNTER_LOOP:
beq r4, r0, END_STRING_COUNTER
srli r5, r4, 1
and r4, r4, r5
addi r2, r2, 1
br STRING_COUNTER_LOOP
END_STRING_COUNTER:
mov r16, r2
END:
br END
.end
Bc 2.
Bc 3.
Bc 4.
Bc 5.
Bc 7.
ca register pc, zero, r2, r4, r5, r7, r16 qua tng bc thc thi.
Bc 8.
Bc 9.
Thay i gi tr register :
6.3.1.3 Phn 3
Bc 2.
Bc 3.
Stop).
Bc 4.
lnh : orhi r7, zero, 0x90ab) v 8004 (a ch cha lnh : ori r7, r7,
0xcdef) bi hai gi tr m my trn.
Bc 6.
Bc 7.
6.3.1.4 Phn 4
300
6.3.2
Mc ch:
Tm hiu cch to Processor vi kh nng Input/Output v cch s dng
nhng SWs/KEYs/LEDs nhp xut d liu vi Processor.
6.3.2.1 Phn 1
To
mt
project
Quartus
mi,
tn:
/lab2/nios_system_lab2
Bc 2.
theo yu cu:
Nios II/s processor vi JTAG Debug Module Level 1, la chn
nhng option sau:
Embedded Multipliers for Hardware Multiply
Hardware Divide
On-chip memory RAM mode v size l 32 Kbytes
Mt PIO input 8 bits (t tn cho module ny l : new_number,
tng ng vi SW [7:0])
Mt PIO output 8 bits (t tn cho module ny l : green_LEDs,
tng ng vi LEDG [7:0])
Mt PIO output 16 bits (t tn cho module ny l : red_LEDs,
tng ng vi LEDR [15:0])
301
Ch :
SOPC Builder s t ng t tn 3 PIO va to ra l pio_0, pio_1, pio_2. Ta
nn i tn cho d hiu v gn vi ngha ca chng, nh new_number,
green_LEDs v red_LEDs.
Bc 3.
nios_system_lab2.ptf
Bc 5.
Np xung FPGA
6.3.2.2 Phn 2
302
.include "nios_macros.s"
.equ
NEW_NUMBER, 0x11000
.equ
GREEN_LEDS,
0x11010
.equ
RED_LEDS ,
0x11020
.text
.global _start
_start:
add
r17, r0, r0
movia r8,
NEW_NUMBER
movia r9,
GREEN_LEDS
r16, 0(r8)
stwio
r16, 0(r9)
add
stwio
r17, 0(r10)
303
br
MAIN_LOOP
.end
Bc 1.
Bc 2.
thc thi tng bc. Quan st v ghi li hin tng trn LEDG[7:0] v
LEDR[15:0]. Cho chng trnh thc thi n khi gi tr ca LEDR bng 5
th bt tip SW[1] ln 1 (khng restart li chng trnh), tip tc cho
thc thi tng bc n khi gi tr LEDR bng 14 th dng. Quan st v
ghi li hin tng trn LEDG[7:0] v LEDR[15:0]. Gii thch hin tng.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Nu ngha tng instruction ca chng trnh trn.
Nu ngha ca chng trnh trn.
Nu gii thut ca chng trnh trn.
6.3.2.3 Phn 3
Bc 1.
Click Add.
Bc 4.
Bc 5.
Bc 6.
305
Bc 7.
Bc 8.
Finish
Bc 9.
Bc 10.
Connect flag
Bc 11.
Chn clk
Bc 12.
Bc 13.
Quay v QuartusII
Bc 14.
module nios_system_lab2 (
// Inputs
306
CLOCK_50,
KEY,
SW,
// Outputs
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3
);
// Inputs
input
CLOCK_50;
input
[3:0] KEY;
input
[17:0]
SW;
output
[17:0]
LEDR;
output
[8:0] LEDG;
output
[6:0] HEX0;
output
[6:0] HEX1;
output
[6:0] HEX2;
output
[6:0] HEX3;
// Outputs
******************************************************
*
307
wire
[15:0]
SUM;
// Output Assignments
assign LEDR[15:0] = SUM;
******************************************************
*
nios_system the_nios_system (
// Inputs
.clk
(CLOCK_50),
.reset_n
(KEY[0]),
.in_port_to_the_new_number
.in_port_to_the_flag
(SW[7:0]),
(KEY[1]),
// Outputs
.out_port_from_the_green_LEDs
(LEDG[7:0]),
.out_port_from_the_red_LEDs
(SUM)
);
Hexadecimal_To_Seven_Segment Digit0 (
// Inputs
.hex_number
(SUM[3:0]),
// Outputs
.seven_seg_display(HEX0)
);
Hexadecimal_To_Seven_Segment Digit1 (
// Inputs
308
.hex_number
(SUM[7:4]),
// Outputs
.seven_seg_display(HEX1)
);
Hexadecimal_To_Seven_Segment Digit2 (
// Inputs
.hex_number
(SUM[11:8]),
// Outputs
.seven_seg_display(HEX2)
);
Hexadecimal_To_Seven_Segment Digit3 (
// Inputs
.hex_number
(SUM[15:12]),
// Outputs
.seven_seg_display(HEX3)
);
endmodule
******* Module:
Hexadecimal_To_Seven_Segment
module Hexadecimal_To_Seven_Segment (
// Inputs
hex_number,
// Outputs
seven_seg_display
);
309
// Inputs
input
[3:0] hex_number;
// Outputs
output
[6:0] seven_seg_display;
assign seven_seg_display =
({7{(hex_number == 4'h0)}} & 7'b1000000) |
({7{(hex_number == 4'h1)}} & 7'b1111001) |
({7{(hex_number == 4'h2)}} & 7'b0100100) |
({7{(hex_number == 4'h3)}} & 7'b0110000) |
({7{(hex_number == 4'h4)}} & 7'b0011001) |
({7{(hex_number == 4'h5)}} & 7'b0010010) |
({7{(hex_number == 4'h6)}} & 7'b0000010) |
({7{(hex_number == 4'h7)}} & 7'b1111000) |
({7{(hex_number == 4'h8)}} & 7'b0000000) |
({7{(hex_number == 4'h9)}} & 7'b0010000) |
({7{(hex_number == 4'hA)}} & 7'b0001000) |
({7{(hex_number == 4'hB)}} & 7'b0000011) |
({7{(hex_number == 4'hC)}} & 7'b1000110) |
({7{(hex_number == 4'hD)}} & 7'b0100001) |
({7{(hex_number == 4'hE)}} & 7'b0000110) |
({7{(hex_number == 4'hF)}} & 7'b0001110);
endmodule
310
Bc 15.
nios_system_lab2.ptf
Bc 17.
Np xung FPGA
6.3.2.4 Phn 4
Hnh 6.44 Mapping gia Based address trn SOPC vi address trong program
.include "nios_macros.s"
311
.equ NEW_NUMBER,
0x11000
.equ GREEN_LEDS,
0x11010
.equ RED_LEDS,
0x11020
.equ STATUS_FLAG,
0x11030
.text
.global _start
_start:
add
r17, r0, r0
MAIN_LOOP:
ldwio r16, 0(r8)
stwio r16, 0(r9)
ldwio r18, 12(r11)
beq
MAIN_LOOP
.end
312
Bc 1.
thc thi tng bc. Quan st v ghi li hin tng trn LEDG [7:0] v
LEDR[15:0] v 7 segment LEDs.
Bc 3.
Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st
tip tc cho thc thi tng bc, quan st v ghi li hin tng trn
LEDG[7:0] v LEDR[15:0] v 7 segment LEDs.
Bc 5.
Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st
Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st
6.3.3
Mc ch:
313
To
mt
project
Quartus
mi,
tn:
/lab3/nios_system_lab3
Bc 2.
theo yu cu:
Nios II/s processor vi JTAG Debug Module Level 1.
On-chip memory RAM mode v size l 32 Kbytes.
Bc 3.
to v gi tt c cc module.v ca nios_system c to ra bi
SOPC_Builder.
nios_system NiosII (CLK, RESET);
Bc 4.
Assign pin :
CLK PIN_N2
RESET PIN_G26.
Bc 5.
nios_system_lab3.ptf
Bc 6.
Np xung FPGA
6.3.3.2 Phn 2
.include "nios_macros.s"
.text
.global _start
315
_start:
movia r8, SIZE
movia r9, LIST
BEGIN_SORT:
ldwio r20, 0(r8)
RESTART_SORT:
mov r18, r0
movi r19, 1
mov r10, r9
SORT_LOOP:
ldwio r16, 0(r10)
ldwio r17, 4(r10)
blt
SWAP:
stwio r17, 0(r10)
stwio r16, 4(r10)
movi r18, 1
SKIP_SWAP:
addi r19, r19, 1
addi r10, r10, 4
bne
bne
br
END
END:
.org 0x01000
LIST_FILE:
SIZE:
.word 0
LIST:
.end
Load
file
cha
gi
tr
cn
sort,
ni
dung
file:
phi:
Bc 4.
Bc 5.
Bc 6.
Dilimiter character : ,
Bc 7.
Bc 9.
chng trnh.
Note : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Nu ngha tng instruction ca chng trnh trn.
318
6.3.3.3 Phn 3
.include "nios_macros.s"
.equ STACK,
0xa000
.text
/* Main Program */
.global _start
_start:
movia
sp, STACK
mov
fp, sp
movia
r8, SIZE
319
movia
r9, LIST
ldwio
r2, 0(r8)
mov
r3, r9
call
SORT
br
END
END:
/* SORT - Subroutine */
SORT:
subi
sp, sp, 28
stw
ra, 0(sp)
stw
fp, 4(sp)
stw
r8, 8(sp)
stw
r16, 12(sp)
stw
r17, 16(sp)
stw
r18, 20(sp)
stw
r19, 24(sp)
addi
fp, sp, 28
BEGIN_SORT:
RESTART_SORT:
mov
r18, r0
movi
r19, 1
mov
r8, r3
SORT_LOOP:
ldwio
r16, 0(r8)
320
ldwio
r17, 4(r8)
blt
stwio
r17, 0(r8)
stwio
r16, 4(r8)
movi
r18, 1
SWAP:
SKIP_SWAP:
addi
r19, r19, 1
addi
r8, r8, 4
bne
bne
END_SORT:
ldw
ra, 0(sp)
ldw
fp, 4(sp)
ldw
r8, 8(sp)
ldw
r16, 12(sp)
ldw
r17, 16(sp)
ldw
r18, 20(sp)
ldw
r19, 24(sp)
addi
sp, sp, 28
ret
.org 0x01000
321
LIST_FILE:
SIZE:
.word 0
LIST:
.end
Bc 1.
Bc 3.
Bc 4.
Bc 6.
chng trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Nu cu trc ca mt subroutine cng nh cch gi subroutine t
chng trnh chnh (C th tham kho t NiosII processor Reference
Handbook).
Nu ngha ca stack, stack pointer register, frame pointer register
(Tham kho NiosII processor Reference Handbook).
Nu ngha tng instruction ca chng trnh trn.
Nu gii thut ca chng trnh trn.
6.3.3.4 Phn 4
322
Bc 1.
Bc 2.
323
Bc 2.
0x11000
.equ OUTPUT_NUM,
0x11010
.equ GREEN_LEDS,
0x11020
.equ STACK,
0xa000
.text
/* Main Program */
.global _start
_start:
add
r4, r0, r0
fp, sp
r2, 0(sp)
FACTOR
END:
br
END
/* FACTOR - Subroutine */
FACTOR:
subi sp, sp, 12
stw
ra, 0(sp)
stw
fp, 4(sp)
stw
r17, 8(sp)
r17, 0(fp)
bne
movi r4, 1
br
END_FACTOR
NON_ZERO:
subi r17, r17, 1
subi sp, sp, 4
stw
call
r17, 0(sp)
FACTOR
325
ra, 0(sp)
ldw
fp, 4(sp)
ldw
r17, 8(sp)
Chy thc thi tng bc, quan st v gii thch gii thut
chng trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Chun b bc 2 nh.
Tm hiu gii thut chng trnh assemble trn.
326
6.3.4
Mc ch:
Tm hiu cch gi v nhn data ti/t thit b xut nhp.
C 2 phng thc c s dng bit trng thi data:
Pooling: Processor truy xut nhng thit b lin tc xem trng thi
ca data.
327
328
6.3.4.1 Phn 1
To
mt
project
Quartus
mi,
tn:
./lab4/nios_system_lab4
Bc 2.
329
330
Lu li nh hnh sau:
Edit
thnh 1
Error
Bc 3.
Generate nios_system.
331
Bc 4.
to
Bc 5.
Assign pin
CLK PIN_N2
RESET PIN_G26.
Bc 6.
nios_system_lab4.ptf
Bc 7.
Np xung FPGA
6.3.4.2 Phn 2
332
Cc bc thc hin
Bc 1.
.global _start
_start:
movia r4, UART
movi r3, 'Z'
CHECK:
ldwio r2, 4(r4)
srli r2, r2, 16
beq r2, r0, CHECK
stbio r3, 0(r4)
br CHECK
END:
br END
.end
Bc 2.
trn.
Bc 3.
Bc 4.
Bc 5.
335
336
337
6.3.4.3 Phn 3
.include "nios_macros.s"
.equ UART_BASE,
0x8820
.equ TIMER,
0x8800
.global _start
_start:
movia r8, UART_BASE
GET_CHAR_LOOP:
ldwio r17, 0(r8)
338
andi
beq
andi
PUT_CHAR_LOOP:
ldwio r17, 4(r8)
andhi r17, r17, 0xffff
beq
br
GET_CHAR_LOOP
br
END
END:
.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Gii thch ngha cho on code mu trn
Compile, load v chy chng trnh trn.
Quan st v gii thch ngha gii thut, v lu gii thut.
6.3.4.4 Phn 4
Exception
Vector
located
0x20
ISR:
rdctl et, ctl4
/* Check if an external */
/* If yes, decrement ea to
execute */
/* interrupted instruction */
SKIP EA DEC:
... the interrupt-service routine
END ISR:
eret
.global start
_start:
LOOP:
br LOOP
/* Endless loop */
.end
Ch ti ngha nhng thanh ghi iu khin: (xem Nios II Processor
Reference Handbook)
Thanh ghi ctl3: Trong Part I, JTAG UART c t ti interrupt
level 0. iu ny c ngha l bit 0 ca ctl3 phi c gn gi tr 1
interrupt ca JTAG UART hot ng.
Thanh ghi ctl0: Bit 0 ca thanh ghi ctl0 c gn gi tr 1 cho php
external interrupt.
341
Yu cu Phn 4:
To 1 interrupt-service routine c 1 k t t JTAG UART.
Trong interrupt-service routine, s dng dng polling hin th k
t nhn c t host computer.
Code tham kho:
.include "nios_macros.s"
.equ UART_BASE,
0x9020
.equ TIMER,
0x9000
.equ STACK,
0x8000
.text
/********************************************
.global _start
_start:
br
PROGRAM_START
/********************************************
.org 0x0020
ISR:
subi sp, sp, 24
stw
et, 20(sp)
342
ea, 0(sp)
stw
ra, 4(sp)
stw
fp, 8(sp)
stw
r21, 12(sp)
stw
r22, 16(sp)
NOT_EI:
br
END_ISR
CHECK_LEVEL_0:
movi r21, 1
and
beq
call
JTAG_UART_ISR
br
END_ISR
CHECK_LEVEL_1:
br
END_ISR
END_ISR:
ldw
ea, 0(sp)
ldw
ra, 4(sp)
ldw
fp, 8(sp)
343
ldw
r21, 12(sp)
ldw
r22, 16(sp)
ldw
et, 20(sp)
eret
/*******************************************
PROGRAM_START:
movia sp, STACK
mov fp, sp
movia r8, UART_BASE
movi r23, 1
stw
r23, 4(r8)
END
.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Vit
sub_routine:
JTAG_UART_ISR
JTAG_UART_PUT_CHAR
JTAG_UART_ISR kim tra nu UART c data mi v lu data
mi vo memory, sau gi JTAG_UART_PUT_CHAR.
344
6.3.4.5 Phn 5
Cho
Hnh 6.60 Thanh ghi ca Timer
php
Interrupt
345
.include "nios_macros.s"
.equ UART_BASE,
0x9020
.equ TIMER,
0x9000
.equ STACK,
0x8000
.text
.global _start
_start:
br
PROGRAM_START
/********************************************************
*/
.org 0x0020
ISR:
subi sp, sp, 24
stw
et, 20(sp)
rdctl et, ctl4
beq
SKIP_EA_DEC:
stw
ea, 0(sp)
stw
ra, 4(sp)
stw
fp, 8(sp)
stw
r21, 12(sp)
stw
r22, 16(sp)
346
br
END_ISR
NOT_EI:
CHECK_LEVEL_0:
movi r21, 1
and
beq
call
JTAG_UART_ISR
br
END_ISR
CHECK_LEVEL_1:
slli
r21, r21, 1
and
beq
call
INTERVAL_TIMER_ISR
br
END_ISR
CHECK_LEVEL_2:
br
END_ISR
ldw
ea, 0(sp)
END_ISR:
ldw
ra, 4(sp)
347
ldw
fp, 8(sp)
ldw
r21, 12(sp)
ldw
r22, 16(sp)
ldw
et, 20(sp)
eret
/*********************************/
/* INTERVAL_TIMER_ISR sub routine */
/********************************/
INTERVAL_TIMER_ISR:
subi sp, sp, 12
stw
ra, 0(sp)
stw
fp, 4(sp)
stw
r10, 8(sp)
r0, 0(r10)
call
JTAG_UART_PUT_CHAR
END_INTERVAL_TIMER_ISR:
ldw
ra, 0(sp)
ldw
fp, 4(sp)
ldw
r10, 8(sp)
/****************************/
PROGRAM_START:
movia sp, STACK
mov fp, sp
movia r8, UART_BASE
movia r10, TIMER
movi r18, 1
stwio r18, 4(r8)
sthio r18, 4(r10)
movi r18, 3
wrctl ctl3, r18
movi r18, 1
wrctl ctl0, r18
END:
br
END
THE_CHAR:
.ascii
"Z"
.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Nu ngha on code trn.
Ch : sinh vin vit cc sub_routine sau:
JTAG_UART_ISR: kim tra nu UART c data mi v lu data
mi vo memory.
JTAG_UART_PUT_CHAR: ly k t t memory v hin th ln
terminal window ca Altera Debug Client.
349
6.3.5
Mc ch
Tm hiu v cch thc giao tip thng qua bus. Trong nhng thit k c
to bi SOPC-Builder, cc thit b ngoi vi giao tip vi Nios processor thng qua
nhng Peripheral Interface Module ( c to ra bi SOPC-Builder ) v Avalon
Switch Fabric. Tuy nhin, ta c th s dng bus truyn/nhn d liu gia cc thit
b ngoi vi vi Nios processor m khng cn dng nhng Peripheral Interface
Module c to bi SPOC-Builder. thc hin c iu ny, ta s s dng
mt module Avalon to External Bus Bridge. Vi vic s dng module ny, giao
tip gia Nios processor vi mt External Slave Interface ta ch cn to mt
Peripheral Interface Module (by manual) n gin thc hin vic kt ni.
c th to c mt Peripheral Interface Module (by manual), trc ht
ta phi hiu ngha ca nhng tn hiu connect gia Avalon to External Bus
Bridge vi External Slave Peripheral.
350
Hnh 6.61 M hnh Nios System dng Avalon to External Bus Bridge
Address : a ch ca Data c c ra hoc a ch m Data cn
ghi vo trong Virtual Memory of Avalon to External Bus Bridge.
WriteData : Data bus c ghi vo External Slave Peripheral t
Memory of Avalon to External Bus Bridge khi WR\ = 0. Ta c
th chn rng ca Data bus : 8bits , 16 bits, 32 bits, 64 bits,
128bits.
BusEnable : y l c bo hiu khi tt c nhng signals khc
valid, Data c th c Read or Write.
ByteEnable : Cho php users chn Bytes khi truy xut Data.
RW\ : Khi c ny ln 1, n cho php Read Data t External Slave
Peripheral vo Virtual Memory
351
352
Bc 2.
/lab5/Lab5_Part1
theo yu cu:
Nios II/s processor vi JTAG Debug Module Level 1.
On-chip memory RAM mode v size l 32 Kbytes.
JTAG_UART- use default setting.
Avalon to External Bus Bridge, thm module ny cn thc
hin cc bc sau:
i.
ii.
iii.
iv.
353
v.
Bc 3.
Bc 4.
Generate System.
Bc 5.
Assign pins.
Bc 7.
Compile system.
Bc 8.
Bc 9.
Bc 10.
trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui )
Tm hiu v gii thch hot ng ca 3 modules (gi km theo file ni
dung bi thc hnh 5 ny).
Chun b trc nh chng trnh assemble thc hin vic ghi 4 gi
tr : 0x0123; 0x4567; 0x89ab ; 0xcdef vo Virtual Memory of
Avalon to External Bus Bridge vi a ch u tin l 0x0000.
6.3.5.2 Phn 2:
Bc 2.
Lm ging Phn 1
355
/lab5/Lab5_Part2
Bc 3.
trnh.
Note : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui )
Tm hiu v gii thch hot ng ca 2 modules Lab5_Part2,
SRAM_Controller (gi km theo ni dung bi thc hnh 5 ny).
Chun b trc nh chng trnh assemble thc hin vic ghi 4 gi
tr : 0x0123; 0x4567; 0x89ab ; 0xcdef vo SRAM vi a ch u tin
l 0x0000 , sau c ngc tr li 4 gi tr vo nhng thanh ghi
ca processor.
6.3.5.3 Phn 3:
356
Bc 1.
Bc 2.
Lm ging Phn 1
Bc 3.
/lab5/Lab5_Part3
trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui )
357
358
Chng 7.
359
M phn mm ModelSim
Bc 2.
Bc 4.
362
v d l m t thit k mt D-Flipflop
363
Bc 10.
Bc 12.
Ch ng dn n file Testbench
366
367
368
Ca s dng sng c m ra
369
370
Chn No, dng sng sau khi m phng xut hin, nhn nt
Bc 25.
371
Bc 1.
Bc 3.
372
373
Bin
dch
(compilation)
thit
k,
mt
th
mc
374
7.3.2
Bc 1.
M phn mm ModelSim
375
376
Bc 3.
Nhn OK
377
Bc 7.
379
380
Ca s thit lp c m ra
381
382
383
Bc 16.
384
Ca s chy m phng c to ra
items in region
385
Bc 19.
Ca s dng sng c m ra
386
387
Chn No, dng sng sau khi m phng xut hin, nhn nt
hiu ng vo. Delay timing ny do file SDF .sdo to ra. M timing trong
file SDF c to ra da trn cng ngh thit k ca FPGA CycloneII.
Bc 25.
388
7.3.3
M li project
389
Ch ng dn project cn m
390
391
392