Giáo trình Vi điều khiển - Ths.Phạm Hùng Kim Khánh

B GIO DC & O TO TRNG I HC K THUT CNG NGH THNH PH H CH MINH KHOA IN IN T --- oOo ---
GIO TRNH
VI IU KHIN
Tc gi: ThS. PHM HNG KIM KHNH
03/2008
Su tm bi: www.daihoc.com.vn
Gio trnh vi x l
LI NI U
Gio trnh Vi iu khin c bin son nhm cung cp cho sinh vin kin thc v h vi iu khin MCS-51, cch thc lp trnh iu khin, np chng trnh v thit k phn cng iu khin thit b. Gio trnh c s dng cho kha hc 45 tit dnh cho sinh vin h i hc Khoa in in t trng i hc K thut Cng ngh TPHCM. B cc gio trnh gm 4 chng da theo cng mn hc K thut Vi iu khin dnh cho sinh vin ngnh in T Vin Thng: Chng 1. Tng quan v h vi iu khin MCS-51 Chng 2. Lp trnh hp ng Chng 3. Cc hot ng ca h vi iu khin MCS-51 Chng 4. Cc ng dng Ph lc 1: Tm tt tp lnh Ph lc 2: M t tp lnh PHM HNG KIM KHNH
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MC LC
Chng 1: Tng quan v h MCS-51 .......................................................................... 1 1. Gii thiu ..................................................................................................................... 1 2. Vi iu khin AT89C51 .............................................................................................. 1 2.1. S .............................................................................................................. 2 2.2. nh th chu k my ...................................................................................... 6 2.3. T chc b nh .............................................................................................. 8 2.4. Cc thanh ghi chc nng c bit (SFR Special Function Registers) ...... 17 2.5. Cu trc port ................................................................................................ 21 2.6. Hot ng Reset .......................................................................................... 22 2.7. Cc vn khc ........................................................................................... 23 Bi tp chng 1 ............................................................................................................ 34 Chng 2: Lp trnh hp ng .................................................................................... 35 1. Cc phng php nh a ch ................................................................................... 35 2. Cc vn lin quan khi lp trnh hp ng ............................................................... 36 2.1. C php lnh ................................................................................................ 36 2.2. Khai bo d liu .......................................................................................... 37 2.3. Cc ton t ................................................................................................... 38 2.4. Cu trc chng trnh .................................................................................. 39 3. Tp lnh ..................................................................................................................... 41 3.1. Nhm lnh chuyn d liu .......................................................................... 41 3.2. Nhm lnh x l bit..................................................................................... 46 3.3. Nhm lnh chuyn iu khin ..................................................................... 47 3.4. Nhm lnh logic .......................................................................................... 51 3.5. Nhm lnh s hc ........................................................................................ 53 Bi tp chng 2 ............................................................................................................ 56 Chng 3: Cc hot ng ........................................................................................... 57 1. Hot ng nh thi (Timer / Counter) ..................................................................... 57 1.1. Gii thiu ..................................................................................................... 57 1.2. Hot ng Timer / Counter ......................................................................... 57 1.3. Cc thanh ghi iu khin hot ng ............................................................ 58 1.3.1. Thanh ghi iu khin timer (Timer/Counter Control Register)...... 58 1.3.2. Thanh ghi ch timer (TMOD Timer/Counter Mode) ............. 59
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1.4. Cc ch hot ng .................................................................................. 59 1.4.1. Ch 0 .......................................................................................... 60 1.4.2. Ch 1 .......................................................................................... 60 1.4.3. Ch 2 .......................................................................................... 61 1.4.4. Ch 3 .......................................................................................... 61 1.5. Timer 2 ........................................................................................................ 62 1.5.1. Cc thanh ghi iu khin Timer 2 .................................................. 62 1.5.2. Ch capture ................................................................................ 64 1.5.3. Ch t ng np li .................................................................... 64 1.5.4. Ch to xung clock .................................................................... 65 1.5.5. Ch to tc baud ................................................................... 66 1.6. Cc v d ...................................................................................................... 67 2. Cng ni tip (Serial port) ......................................................................................... 71 2.1. Cc thanh ghi iu khin hot ng ............................................................ 72 2.1.1. Thanh ghi SCON (Serial port controller) ....................................... 72 2.1.2. Thanh ghi BDRCON (Baud Rate Control Register) ...................... 73 2.2. To tc baud ........................................................................................... 73 2.2.1. To tc baud bng Timer 1 ........................................................ 74 2.2.2. To tc baud bng Timer 2 ........................................................ 76 2.2.3. B to tc baud ni (Internal Baud Rate Generator) ................. 77 2.3. Truyn thng a x l ................................................................................. 77 2.4. Nhn dng a ch t ng .......................................................................... 78 2.5. Kim tra li khung ....................................................................................... 79 2.6. Cc v d ...................................................................................................... 79 3. Ngt (Interrupt) .......................................................................................................... 81 3.1. Cc thanh ghi iu khin hot ng ............................................................ 82 3.1.1. Thanh ghi IE (Interrupt Enable) ..................................................... 82 3.1.2. Thanh ghi IP (Interrupt Priority) .................................................... 82 3.1.3. Thanh ghi TCON (Timer/Counter Control) ................................... 83 3.2. X l ngt .................................................................................................... 84 3.3. Ngt do b nh thi .................................................................................... 86 3.4. Ngt do cng ni tip .................................................................................. 89 3.5. Ngt ngoi ................................................................................................... 91 Bi tp chng 3 ............................................................................................................ 94
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Chng 4: Cc ng dng da trn h vi iu khin MCS-51................................. 95 1. iu khin Led n ................................................................................................... 95 2. iu khin Led 7 on .............................................................................................. 98 2.1. Cu trc v bng m hin th d liu trn Led 7 on ................................ 98 2.2. Cc phng php hin th d liu ............................................................. 100 2.2.1. Phng php qut ......................................................................... 100 2.2.2. Phng php cht ......................................................................... 104 3. iu khin ma trn Led ........................................................................................... 107 4. iu khin ng c bc......................................................................................... 112 5. iu khin LCD (Liquid Crystal Display) .............................................................. 115 6. Giao tip vi PPI8255 ............................................................................................. 129 Bi tp chng 4 .......................................................................................................... 135 Ph lc 1: Son tho v np chng trnh .............................................................. 136 Ph lc 2: M phng bng Proteus .......................................................................... 181 Ph lc 3: Tm tt tp lnh ...................................................................................... 191 Ph lc 4: M t tp lnh .......................................................................................... 195
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Gio trnh Vi iu khin
Tng quan v vi iu khin MCS-51
Chng 1: TNG
QUAN V VI IU KHIN MCS-51
Chng ny gii thiu tng quan v h vi iu khin MCS-51(ch yu trn AT89C51): cu trc phn cng, s chn, cc thanh ghi, c tnh lp trnh v cc c tnh v in.
1. Gii thiu
H vi iu khin MCS-51 do Intel sn xut u tin vo nm 1980 l cc IC thit k cho cc ng dng hng iu khin. Cc IC ny chnh l mt h thng vi x l hon chnh bao gm cc cc thnh phn ca h vi x l: CPU, b nh, cc mch giao tip, iu khin ngt. MCS-51 l h vi iu khin s dng c ch CISC (Complex Instruction Set Computer), c di v thi gian thc thi ca cc lnh khc nhau. Tp lnh cung cp cho MCS-51 c cc lnh dng cho iu khin xut / nhp tc ng n tng bit. MCS-51 bao gm nhiu vi iu khin khc nhau, b vi iu khin u tin l 8051 c 4KB ROM, 128 byte RAM v 8031, khng c ROM ni, phi s dng b nh ngoi. Sau ny, cc nh sn xut khc nh Siemens, Fujitsu, cng c cp php lm nh cung cp th hai. MCS-51 bao gm nhiu phin bn khc nhau, mi phin bn sau tng thm mt s thanh ghi iu khin hot ng ca MCS-51.
2. Vi iu khin AT89C51
AT89C51 l vi iu khin do Atmel sn xut, ch to theo cng ngh CMOS c cc c tnh nh sau: 4 KB PEROM (Flash Programmable and Erasable Read Only Memory), c kh nng ti 1000 chu k ghi xo Tn s hot ng t: 0Hz n 24 MHz 3 mc kha b nh lp trnh 128 Byte RAM ni. 4 Port xut /nhp I/O 8 bit. 2 b Timer/counter 16 Bit. 6 ngun ngt. Giao tip ni tip iu khin bng phn cng. 64 KB vng nh m ngoi 64 KB vng nh d liu ngoi. Cho php x l bit. 210 v tr nh c th nh v bit. 4 chu k my (4 s i vi thch anh 12MHz) cho hot ng nhn hoc chia.
Phm Hng Kim Khnh
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C cc ch ngh (Low-power Idle) v ch ngun gim (Power-down).
Ngoi ra, mt s IC khc ca h MCS-51 c thm b nh thi th 3 v 256 byte RAM ni.
2.1.
S
P0.0 P0.7 P2.0 P2.7
VCC VSS
PORT0DRIVERS
PORT2DRIVERS
RAMADDR REGISTER
RAM
PORTO LATCH
PORT2 LATCH
ROM
PROGRAM ADDRREGISTER STACK POINTER PCON SCON TMOD TL0 TL2* IE TCON TH1 RCAP2H* IP PROGRAM COUNTER PC INCREAMENTER
ACC
BUFFER
T2CON* TH0 TMP2 B REGISTER ALU TMP1 TL1 TH2*
RCAP2L* SBUF
IINTERRUPTSERIALPORTAND TIMERBLOCKS
PSW PSEN ALE EA RST INSTRUCTION REGISTER TIMINGAND CONTROL
DPTR
PORT1LATCH
PORT3LATCH
OSC PORT1 DRIVER PORT3 DRIVER
XTAL1
XTAL2
P1.0 P1.7
P3.0 P3.7
Note: * for Timer 2 only
Hnh 1.1 S khi ca AT89C51

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AT89C51 gm c 40 chn, m t nh sau:

40 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 AT89C51 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST
Hnh 1.2 S chn ca AT89C51 Port 0: Port 0 l port c 2 chc nng cc chn 32 39 ca AT89C51: Chc nng IO (xut / nhp): dng cho cc thit k nh. Tuy nhin, khi dng chc nng ny th Port 0 phi dng thm cc in tr ko ln (pull-up), gi tr ca in tr ph thuc vo thnh phn kt ni vi Port. Khi dng lm ng ra, Port 0 c th ko c 8 ng TTL. Khi dng lm ng vo, Port 0 phi c set mc logic 1 trc . Chc nng a ch / d liu a hp: khi dng cc thit k ln, i hi phi s dng b nh ngoi th Port 0 va l bus d liu (8 bit) va l bus a ch (8 bit thp).
Ngoi ra khi lp trnh cho AT89C51, Port 0 cn dng nhn m khi lp trnh v xut m khi kim tra (qu trnh kim tra i hi phi c in tr ko ln).
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20
GND
VCC
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN
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Port 1: Port1 (chn 1 8) ch c mt chc nng l IO, khng dng cho mc ch khc (ch trong 8032/8052/8952 th dng thm P1.0 v P1.1 cho b nh thi th 3). Ti Port 1 c in tr ko ln nn khng cn thm in tr ngoi. Port 1 c kh nng ko c 4 ng TTL v cn dng lm 8 bit a ch thp trong qu trnh lp trnh hay kim tra. Khi dng lm ng vo, Port 1 phi c set mc logic 1 trc . Port 2: Port 2 (chn 21 28) l port c 2 chc nng: Chc nng IO (xut / nhp): c kh nng ko c 4 ng TTL. Chc nng a ch: dng lm 8 bit a ch cao khi cn b nh ngoi c a ch 16 bit. Khi , Port 2 khng c dng cho mc ch IO. Khi dng lm ng vo, Port 2 phi c set mc logic 1 trc . Khi lp trnh, Port 2 dng lm 8 bit a ch cao hay mt s tn hiu iu khin. Port 3: Port 3 (chn 10 17) l port c 2 chc nng: Chc nng IO: c kh nng ko c 4 ng TTL. Khi dng lm ng vo, Port 3 phi c set mc logic 1 trc . Chc nng khc: m t nh bng 1.1 Bng 1.1: Chc nng cc chn ca Port 3 Bit Tn P3.0 RxD P3.1 TxD P3.3 INT1 P3.4 T0 P3.5 T1 P3.6 WR P3.7 RD Chc nng Ng vo port ni tip Ng ra port ni tip Ngt ngoi 1 Ng vo ca b nh thi 0 Ng vo ca b nh thi 1 Tn hiu iu khin ghi d liu ln b nh ngoi. Tn hiu iu khin c t b nh d liu ngoi.
P3.2 INT0 Ngt ngoi 0
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Ngun: Chn 40: VCC = 5V 20% Chn 20: GND PSEN (Program Store Enable):
PSEN (chn 29) cho php c b nh chng trnh m rng i vi cc ng dng s dng ROM ngoi, thng c ni n chn OC (Output Control) ca ROM c cc byte m lnh. PSEN s mc logic 0 trong thi gian AT89C51 ly lnh.Trong qu trnh ny, PSEN s tch cc 2 ln trong 1 chu k my.
M lnh ca chng trnh c c t ROM thng qua bus d liu (Port0) v bus a ch (Port0 + Port2). Khi 8951 thi hnh chng trnh trong ROM ni, PSEN s mc logic 1. ALE/ PROG (Address Latch Enable / Program): ALE/ PROG (chn 30) cho php tch cc ng a ch v d liu ti Port 0 khi truy xut b nh ngoi. ALE thng ni vi chn Clock ca IC cht (74373, 74573). Cc xung tn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th c dng lm tn hiu clock cho cc phn khc ca h thng. Xung ny c th cm bng cch set bit 0 ca SFR ti a ch 8Eh ln 1. Khi , ALE ch c tc dng khi dng lnh MOVX hay MOVC. Ngoi ra, chn ny cn c dng lm ng vo xung lp trnh cho ROM ni ( PROG ). EA /VPP (External Access) :
EA (chn 31) dng cho php thc thi chng trnh t ROM ngoi. Khi ni chn 31 vi Vcc, AT89C51 s thc thi chng trnh t ROM ni (ti a 8KB), ngc li th thc thi t ROM ngoi (ti a 64KB).
Ngoi ra, chn EA c ly lm chn cp ngun 12V khi lp trnh cho ROM. RST (Reset): RST (chn 9) cho php reset AT89C51 khi ng vo tn hiu a ln mc 1 trong t nht l 2 chu k my. X1,X2: Ng vo v ng ra b dao ng, khi s dng c th ch cn kt ni thm thch anh v cc t nh hnh v trong s . Tn s thch anh thng s dng cho AT89C51 l 12Mhz.
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Gi tr C1, C2 = 30 pF 10 pF Hnh 1.3 S kt ni thch anh 2.2. nh th chu k my
Mt chu k my bao gm 6 trng thi (12 xung clock). Mt trng thi bao gm 2 phn ng vi 12 xung clock : Phase 1 v Phase 2. Nh vy, mt chu k my bao gm 12 xung clock c biu din t S1P1 n S6P2 (State 1, Phase 1 State 6, Phase 2). Chu k ly lnh v thc thi lnh m t nh hnh 1.4. Tn hiu cht a ch ALE tch cc 2 ln trong mt chu k my (trong khong thi gian S1P2 n S2P1 v t S4P2 n S5P1). T tn s xung ti chn ALE bng 1/6 tn s thch anh. i vi cc lnh thc thi trong 1 chu k: Lnh 1 byte: c thc thi ti thi im S1P2 sau khi m lnh c cht vo thanh ghi lnh ti S1P1. Lnh 2 byte: byte th 2 c c ti thi im S4 v s c thc thi ti thi im S4. i vi cc lnh thc thi trong 2 chu k: Qu trnh ly lnh thc hin ti thi im S1 ca chu k u tin (byte m lnh 1). Nu lnh c nhiu hn 1 byte th s c ly cc thi im tip theo ging nh cc lnh thc thi trong 1 chu k.
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Hnh 1.4 Chu k lnh
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2.3.
T chc b nh
B nh trong
B nh ngoi B nh chng trnh 64 KB 0000h FFFFh iu khin bng PSEN B nh d liu 64 KB 0000h FFFFh iu khin bng RD v WR
ROM4KB 0000h0FFFh RAM128byte 00h7Fh SFR 80h0FFh
Hnh 1.5 - Cc vng nh trong AT89C51 B nh ca h MCS-51 c th chia thnh 2 phn: b nh trong v b nh ngoi. B nh trong bao gm 4 KB ROM v 128 byte RAM (256 byte trong 8052). Cc byte RAM c a ch t 00h 7Fh v cc thanh ghi chc nng c bit (SFR) c a ch t 80h 0FFh c th truy xut trc tip. i vi 8052, 128 byte RAM cao (a ch t 80h 0FFh) khng th truy xut trc tip m ch c th truy xut gin tip (xem thm trong phn tp lnh). B nh ngoi bao gm b nh chng trnh (iu khin c bng tn hiu PSEN ) v b nh d liu (iu khin bng tn hiu RD hay WR cho php c hay ghi d liu). Do s ng a ch ca MCS-51 l 16 bit (Port 0 cha 8 bit thp v Port 2 cha 8 bit cao) nn b nh ngoi c th gii m ti a l 64KB. 2.3.1. T chc b nh trong B nh trong ca MCS-51 gm ROM v RAM. RAM bao gm nhiu vng c mc ch khc nhau: vng RAM a dng (a ch byte t 30h 7Fh v c thm vng 80h 0FFh ng vi 8052), vng c th a ch ha tng bit (a ch byte t 20h 2Fh, gm 128 bit c nh a ch bit t 00h 7Fh), cc bank thanh ghi (t 00h 1Fh) v cc thanh ghi chc nng c bit (t 80h 0FFh).
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Cc thanh ghi chc nng c bit (SFR Special Function Registers): Bng 1.2 Cc thanh ghi chc nng c bit a ch byte F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h
IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TH0 DPH TL1 TH1 AUXR CKCON PCON SBUF BRL BDRCON SADDR SADEN PSW (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2) ACC B
C th nh a ch bit
Khng nh a ch bit
Cc thanh ghi c th nh a ch bit s c a ch bit bt u v a ch byte trng nhau. V d nh: thanh ghi P0 c a ch byte l 80h v c a ch bit bt u t 80h (ng vi P0.0) n 87h (ng vi P0.7). Chc nng cc thanh ghi ny s m t trong phn sau.
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RAM ni: chia thnh cc vng phn bit: vng RAM a dng (30h 7Fh), vng RAM c th nh a ch bit (20h 2Fh) v cc bank thanh ghi (00h 1Fh).
a ch byte 7F 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 1F 08 07 00 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 Vng RAM a dng a ch bit Chc nng
Vng c th nh a ch bit
Bank 3 Bank 2 Cc bank thanh ghi Bank 1 Bank thanh ghi 0 ( mc nh cho R0-R7)
Hnh 1.6 S phn b RAM ni RAM a dng: RAM a dng c 80 byte t a ch 30h 7Fh c th truy xut mi ln 8 bit bng cch dng ch a ch trc tip hay gin tip. Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ich nh trn ngoi cc chc nng cp nh phn sau. RAM c th nh a ch bit: Vng a ch t 20h 2Fh gm 16 byte (= 128 bit) c th thc hin ging nh vng RAM a dng (mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh
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x l bit. Vng RAM ny c cc a ch bit bt u ti gi tr 00h v kt thc ti 7Fh. Nh vy, a ch bt u 20h (gm 8 bit) c a ch bit t 00h 07h; a ch kt thc 2Fh c a ch bit t 78h Fh. Cc bank thanh ghi: Vng a ch t 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h 07h, bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank thanh ghi ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng h thng th bank thanh ghi c s dng l bank 0. Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi c truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c th thc hin thng qua thanh ghi t trng thi chng trnh (PSW). Cc bank thanh ghi ny cng c th truy xut bnh thng nh vng RAM a dng ni trn. 2.3.2. T chc b nh ngoi MCS-51 c b nh theo cu trc Harvard: phn bit b nh chng trnh v d liu. Chng trnh v d liu c th cha bn trong nhng vn c th kt ni vi 64KB chng trnh v 64KB d liu. B nh chng trnh c truy xut thng qua chn PSEN cn b nh d liu c truy xut thng qua chn WR hay RD . Lu rng vic truy xut b nh chng trnh lun lun s dng a ch 16 bit cn b nh d liu c th l 8 bit hay 16 bit tu theo cu lnh s dng. Khi dng b nh d liu 8 bit th c th dng Port 2 nh l Port I/O thng thng cn khi dng ch 16 bit th Port 2 ch dng lm cc bit a ch cao. Port 0 c dng lm a ch thp/ d liu a hp. Tn hiu ALE tch byte a ch v a vo b cht ngoi. Trong chu k ghi, byte d liu s tn ti Port 0 va trc khi WR tch cc v c gi cho n khi WR khng tch cc.Trong chu k c, byte nhn c chp nhn va trc khi RD khng tch cc. B nh chng trnh ngoi c x l 1 trong 2 iu kin sau: Tn hiu EA tch cc ( = 0). Gi tr ca b m chng trnh (PC Program Counter) ln hn kch thc b nh.
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PCH: Program Counter High PCL: Program Counter Low DPH: Data Pointer High DPL: Data Pointer Low Hnh 1.7 Thc thi b nh chng trnh ngoi
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Kt ni phn cng khi thit k b nh ngoi m t nh sau:

ADDRESS BUS DATA BUS
U1 A8 A9 A10 A11 A12 A13 A14 A15 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 11 1 U8 D0 D1 D2 D3 D4 D5 D6 D7 LE OE 74HC573 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 22 20 28 U3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE/VPP CE VCC O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7
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ROM 27512
Hnh 1.8 Giao tip b nh chng trnh ngoi
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U4 A8 A9 A10 A11 A12 A13 A14 A15 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 11 1 U7 D0 D1 D2 D3 D4 D5 D6 D7 LE OE 74HC573 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 24 29 22 30 U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE WE CE1 CE2 RAM 62512 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7
Hnh 1.9 Giao tip b nh d liu ngoi
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U5 A8 A9 A10 A11 A12 A13 A14 A15 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 U11A 1 2 7408 3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 11 1 U10 D0 D1 D2 D3 D4 D5 D6 D7 LE OE 74HC573 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 24 29 22 30 U9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE WE CE1 CE2 RAM 62512 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7
Hnh 1.10 Giao tip b nh chng trnh v d liu ngoi dng chung
Gio trnh Vi iu khin
B nh chng trnh ngoi: Qu trnh thc thi lnh khi dng b nh chng trnh ngoi c th m t nh hnh 1.7. Trong qu trnh ny, Port 0 v Port 2 khng cn l cc Port xut nhp m cha a ch v d liu. S kt ni vi b nh chng trnh ngoi m t nh hnh 1.8. Trong mt chu k my, tn hiu ALE tch cc 2 ln. Ln th nht cho php 74HC573 m cng cht a ch byte thp, khi ALE xung 0 th byte thp v byte cao ca b m chng trnh u c nhng ROM cha xut v PSEN cha tch cc, khi tn hiu ALE ln 1 tr li th Port 0 c d liu l m lnh. ALE tch cc ln th hai c gii thch tng t v byte 2 c c t b nh chng trnh. Nu lnh ang thc thi l lnh 1 byte th CPU ch c Opcode, cn byte th hai b qua. B nh d liu ngoi: B nh d liu ngoi c truy xut bng lnh MOVX thng qua cc thanh ghi xc nh a ch DPTR (16 bit) hay R0, R1 (8 bit). S kt ni vi b nh d liu ngoi m t nh hnh 1.9. Qu trnh thc hin c hay ghi d liu c cho php bng tn hiu RD hay
WR (chn P3.7 v P3.6).

B nh chng trnh v d liu dng chung: Trong cc ng dng pht trin phn mm xy dng da trn AT89C51, ROM s c lp trnh nhiu ln nn d lm h hng ROM. Mt gii php t ra l s dng RAM cha cc chng trnh tm thi. Khi , RAM va l b nh chng trnh va l b nh d liu. Yu cu ny c th thc hin bng cch kt hp chn RD v chn PSEN thng qua cng AND. Khi thc hin c m lnh, chn PSEN tch cc cho php c t RAM v khi c d liu, chn RD s tch cc. S kt ni m t nh hnh 1.10. 2.3.3. Gii m a ch Trong cc ng dng da trn AT89C51, ngoi giao tip b nh d liu, vi iu khin cn thc hin giao tip vi cc thit b khc nh bn phm, led, ng c, Cc thit b ny c th giao tip trc tip thng qua cc Port. Tuy nhin, khi s lng cc thit b ln, cc Port s khng thc hin iu khin. Gii php a ra l xem cc thit b ny ging nh b nh d liu. Khi , cn phi thc hin qu trnh gii m a ch phn bit cc thit b ngoi vi khc nhau. Qu trnh gii m a ch thng c thc hin thng qua cc IC gii m nh 74139 (2 -> 4), 74138 ( 3 -> 8), 74154 (4 -> 16). Ng ra ca cc IC gii m s c a ti chn chn chip ca RAM hay b m khi iu khin ngoi vi.
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2.4.
Cc thanh ghi chc nng c bit (SFR Special Function Registers)
2.4.1. Thanh ghi tch lu (Accumulator) Thanh ghi tch lu l thanh ghi s dng nhiu nht trong AT89C51, c k hiu trong cu lnh l A. Ngoi ra, trong cc lnh x l bit, thanh ghi tch lu c k hiu l ACC. Thanh ghi tch lu c th truy xut trc tip thng qua a ch E0h (byte) hay truy xut tng bit thng qua a ch bit t E0h n E7h. VD: Cu lnh: MOV A,#1 MOV 0E0h,#1 c cng kt qu. Hay: SETB ACC.4 SETB 0E4h cng tng t. 2.4.2. Thanh ghi B Thanh ghi B dng cho cc php ton nhn, chia v c th dng nh mt thanh ghi tm, cha cc kt qu trung gian. Thanh ghi B c a ch byte F0h v a ch bit t F0h F7h c th truy xut ging nh thanh ghi A. 2.4.3. Thanh ghi t trng thi chng trnh (PSW - Program Status Word) Thanh ghi t trng thi chng trnh PSW nm ti a ch D0h v c cc a ch bit t D0h D7h, bao gm 7 bit (1 bit khng s dng) c cc chc nng nh sau: Bng 1.3 Chc nng cc bit trong thanh ghi PSW Bit 7 6 5 4 3 Chc CY AC F0 RS1 RS0 nng 2 OV 1 0 P
CY (Carry): c nh, thng c dng cho cc lnh ton hc (C = 1 khi c nh trong php cng hay mn trong php tr) AC (Auxiliary Carry): c nh ph (thng dng cho cc php ton BCD). F0 (Flag 0): c s dng tu theo yu cu ca ngi s dng.
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RS1, RS0: dng chn bank thanh ghi s dng. Khi reset h thng, bank 0 s c s dng. Bng 1.4 Chn bank thanh ghi RS1 RS0 Bank thanh ghi 0 0 Bank 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 OV (Overflow): c trn. C OV = 1 khi c hin tng trn s hc xy ra (dng cho s nguyn c du). P (Parity): kim tra parity (chn). C P = 1 khi tng s bit 1 trong thanh ghi A l s l (ngha l tng s bit 1 ca thanh ghi A cng thm c P l s chn). V d nh: A = 10101010b c tng cng 4 bit 1 nn P = 0. C P thng c dng kim tra li truyn d liu. 2.4.4. Thanh ghi con tr stack (SP Stack Pointer) Con tr stack SP nm ti a ch 81h v khng cho php nh a ch bit. SP dng ch n nh ca stack. Stack l mt dng b nh lu tr dng LIFO (Last In First Out) thng dng lu tr a ch tr v khi gi mt chng trnh con. Ngoi ra, stack cn dng nh b nh tm lu li v khi phc cc gi tr cn thit. i vi AT89C51, stack c cha trong RAM ni (128 byte i vi 8031/8051 hay 256 byte i vi 8032/8052). Mc nh khi khi ng, gi tr ca SP l 07h, ngha l stack bt u t a ch 08h (do hot ng lu gi tr vo stack yu cu phi tng ni dung thanh ghi SP trc khi lu). Nh vy, nu khng gn gi tr cho thanh ghi SP th khng c s dng cc bank thanh ghi 1, 2, 3 v c th lm sai d liu. i vi cc ng dng thng thng khng cn dng nhiu n stack, c th khng cn khi ng SP m dng gi tr mc nh l 07h. Tuy nhin, nu cn, ta c th xc nh li vng stack cho MCS-51. 2.4.5. Con tr d liu DPTR (Data Pointer) Con tr d liu DPTR l thanh ghi 16 bit bao gm 2 thanh ghi 8 bit: DPH (High) nm ti a ch 83h v DPL (Low) nm ti a ch 82h. Cc thanh ghi ny khng cho php nh a ch bit. DPTR c dng khi truy xut n b nh c a ch 16 bit. 2.4.6. Cc thanh ghi port Cc thanh ghi P0 ti a ch 80h, P1 ti a ch 90h, P2, ti a ch A0h, P3 ti a ch B0h l cc thanh ghi cht cho 4 port xut / nhp (Port 0, 1, 2, 3). Tt c cc thanh ghi ny u cho php nh a ch bit trong a ch bit ca P0 t 80h 87h, P1 t 90h 97h, P2 t A0h A7h, P3 t B0h B7h. Cc a ch bit ny c th thay th bng ton t . V d nh: 2 lnh sau l tng ng:
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SETB P0.0 SETB 80h 2.4.7. Thanh ghi port ni tip (SBUF - Serial Data Buffer) Thanh ghi port ni tip ti a ch 99h thc cht bao gm 2 thanh ghi: thanh ghi nhn v thanh ghi truyn. Nu d liu a ti SBUF th l thanh ghi truyn, nu d liu c c t SBUF th l thanh ghi nhn. Cc thanh ghi ny khng cho php nh a ch bit. 2.4.8. Cc thanh ghi nh thi (Timer Register) Cc cp thanh ghi (TH0, TL0), (TH1, TL1) v (TH2, TL2) l cc thanh ghi dng cho cc b nh thi 0, 1 v 2 trong b nh thi 2 ch c trong 8032/8052. Ngoi ra, i vi h 8032/8052 cn c thm cp thanh ghi (RCAP2L, RCAP2H) s dng cho b nh thi 2 (s tho lun trong phn hot ng nh thi). 2.4.9. Cc thanh ghi iu khin Bao gm cc thanh ghi IP (Interrupt Priority), IE (Interrupt Enable), TMOD (Timer Mode), TCON (Timer Control), T2CON (Timer 2 Control), SCON (Serial port control) v PCON (Power control). Thanh ghi IP ti a ch B8h cho php chn mc u tin ngt khi c 2 ngt xy ra ng thi. IP cho php nh a ch bit t B8h BFh. Thanh ghi IE ti a ch A8h cho php hay cm cc ngt. IE c a ch bit t A8h AFh. Thanh ghi TMOD ti a ch 89h dng chn ch hot ng cho cc b nh thi (0, 1) v khng cho php nh a ch bit. Thanh ghi TCON ti a ch 88h iu khin hot ng ca b nh thi v ngt. TCON c a ch bit t 88h 8Fh. Thanh ghi T2CON ti a ch C8h iu khin hot ng ca b nh thi 2. T2CON c a ch bit t C8h CFh. Thanh ghi SCON ti a ch 98h iu khin hot ng ca port ni tip. SCON c a ch bit t 98h 9Fh. Cc thanh ghi ni trn s c tho lun thm cc phn sau.
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Thanh ghi iu khin ngun PCON Thanh ghi PCON ti a ch 87h khng cho php nh a ch bit bao gm cc bit nh sau: Bit Chc nng Bng 1.5 Chc nng cc bit trong thanh ghi PCON 7 6 5 4 3 SMOD1 SMOD0 POF GF1 2 GF0 1 PD 0 IDL
SMOD1 (Serial Mode 1): = 1 cho php tng gp i tc port ni tip trong ch 1, 2 v 3. SMOD0 (Serial Mode 0): cho php chn bit SM0 hay FE trong thanh ghi SCON ( = 1 chn bit FE). POF (Power-off Flag): dng nhn dng loi reset. POF = 1 khi m ngun. Do , xc nh loi reset, cn phi xo bit POF trc . GF1, GF0 (General purpose Flag): cc bit c dnh cho ngi s dng. PD (Power Down): c xo bng phn cng khi hot ng reset xy ra. Khi bit PD = 1 th vi iu khin s chuyn sang ch ngun gim. Trong ch ny: Ch c th thot khi ch ngun gim bng cch reset. Ni dung RAM v mc logic trn cc port c duy tr. Mch dao ng bn trong v cc chc nng khc ngng hot ng. Chn ALE v PSEN mc thp. Yu cu Vcc phi c in p t nht l 2V v phc hi Vcc = 5V t nht 10 chu k trc khi chn RESET xung mc thp ln na.
IDL (Idle): c xo bng phn cng khi hot ng reset hay c ngt xy ra. Khi bit IDL = 1 th vi iu khin s chuyn sang ch ngh. Trong ch ny: Ch c th thot khi ch ngun gim bng cch reset hay c ngt xy ra. Trng thi hin hnh ca vi iu khin c duy tr v ni dung cc thanh ghi khng i. Mch dao ng bn trong khng gi c tn hiu n CPU. Chn ALE v PSEN mc cao.
Lu rng cc bit iu khin PD v IDL c tc dng chnh trong tt c cc IC h MSC-51 nhng ch c th thc hin c trong cc phin bn CMOS.
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2.5.
Cu trc port
a. Cu trc Port 0
b. Cu trc Port 1
c. Cu trc Port 2
d. Cu trc Port 3
Hnh 1.11 Cu trc cc Port ca AT89C51 Cu trc cc Port m t nh hnh v, mi port c mt b cht (SFR t P0 n P3), mt b m vo v b li ng ra. Port 0: Khi dng ch IO: FET ko ln tt (do khng c cc tn hiu ADDR v CONTROL) nn ng ra Port 0 h mch. Nh vy, khi thit k Port 0 lm vic ch IO, cn phi c cc in tr ko ln. Trong ch ny, mi chn ca Port 0 khi dng lm ng ra c th ko ti a 8 ng TTL (xem thm phn sink / source trong 2.7).
Khi ghi mc logic 1 ra Port 0, ng ra Q ca b cht (latch) mc 0 nn FET tt, ng ra Port 0 ni ln Vcc thng qua FET v c th ko xung mc 0 khi kt ni vi tn hiu ngoi. Khi ghi mc logic 0 ra Port 0, ng ra Q ca b cht mc 1 nn FET dn, ng ra Port 0 c ni vi GND nn lun mc 0 bt k ng vo. Do , c d liu ti Port 0 th cn phi set bit tng ng.
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Khi dng ch a ch / d liu: FET ng vai tr nh in tr ko ln nn khng cn thit k thm cc in tr ngoi.
Port 1, 2, 3: Khng dng FET m dng in tr ko ln nn khi thit k khng cn thit phi thm cc in tr ngoi. Khi dng ch IO, cch thc hot ng ging nh Port 0 (ngha l trc khi c d liu th cn phi set bit tng ng). Port 1, 2, 3 c kh nng sink / source dng cho 4 ng TTL.
2.6.
Hot ng Reset
thc hin reset, cn phi tc ng mc cao ti chn RST (chn 9) ca AT89C51 t nht 2 chu k my. S mch reset c th m t nh sau:
VCC R28 100 C20 0.1uF
RST RESET R27 8.2K
Hnh 1.12 S mch reset ca AT89C51 Sau khi reset, ni dung ca RAM ni khng thay i v cc thanh ghi thay i v gi tr mc nh nh sau: Bng 1.6 - Gi tr mc nh ca cc thanh ghi khi reset Thanh ghi Ni dung m chng trnh PC 0000h A, B, PSW, SCON, SBUF 00h SP 07h DPTR 0000h Port 0 n port 3 FFh IP XXX0 0000b IE 0X0X 0000b Cc thanh ghi nh thi 00h PCON (HMOS) 0XXX XXXXb PCON (CMOS) 0XXX 0000b
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2.7.
Cc vn khc
2.7.1. Dng g sink v so ource D Dng in si ink v sour rce l mt p phn quan tr rng khi thi it k cc mch in t. S khc nhau ca chng c c m t nh hnh 1.13.
n gia dng d sink v v source Hnh 1.13 Khc nhau T Trong AT89 9C51, Port 0 c dng g sink ca mi chn t ng ng n vi 8 ng g TTL cn n cc Port khc k c dn ng sink /sour rce tng ng vi 4 ng TTL. 2.7.2. Lp trnh t cho AT89C51 A 2.7.2. .1. Cc ch kho b nh ch hng trnh
Bng 1.7 Cc C ch kho chn ng trnh Ch Lp trnh h cc bit M t kho o LB1 LB2 2 LB3 1 U U U Khng kho o 2 P U U Khng cho php lnh MOVC ti b nh ch ng trnh n EA c ly mu v cht khi re eset, khng g ngoi, chn cho php lp trnh. 3 4 P P P P U P Ging ch 2 v kh ng cho ph p kim tra. Ging ch 3 v kh ng cho ph p thc thi ngoi. n
Trong AT89 T 9C51, c 3 bit kho (LB lock k bit) c th h c lp trnh (P program mmed) hay khng k (U unprogram mmed) cho php chn cc ch kho kh c nhau (bng 1.7).
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2.7.2.2.
Lp trnh
Khi AT89C51 trng thi xo, tt c cc nh thng l 0FFh v c th c lp trnh. in p lp trnh c th l 5V hay 12V tu theo loi IC. in p lp trnh xc nh bng k hiu trn chip hay cc byte nhn dng khi xo chip (xem bng 1.8). Bng 1.8 Nhn dng in p lp trnh Vpp = 12V K hiu AT89C51 xxxx yyww Byte nhn dng (30h) = 1Eh (31h) = 51h (32h) = 0FFh Vpp = 5V AT89C51 xxxx-5 yyww (30h) = 1Eh (31h) = 51h (32h) = 05h
Lu rng AT89C51 c lp trnh theo tng byte nn phi thc hin xo tt c chip trc khi lp trnh. Qu trnh lp trnh cho AT89C51 c thc hin theo cc bc sau: Bc 1: t gi tr a ch ln ng a ch. Bc 2: t d liu ln ng d liu. Bc 3: t cc tn hiu iu khin tng ng (xem bng 1.9). Bc 4: t chn EA /VPP ln in p 12V (nu s dng in p lp trnh 12V). Bc 5: To mt xung ti chn ALE/ PROG (xem bng 1.9). Thng chu k ghi 1 byte khng vt qu 1.5 ms. Sau thay i a ch v lp li bc 1 cho n khi kt thc d liu cn lp trnh.
Bng 1.9 Cc tn hiu iu khin lp trnh Vpp P2.6 P2.7 P3.6 P3.7 Ch RST PSEN PROG Ghi m H L H/12V L H H H c m H L H H L L H H Ghi lock bit LB1 H L H/12V H H H H LB2 H L H/12V H H L L LB3 H L H/12V H L H L Xo chip H L H/12V H L L L c byte nhn dng H L H H L L L L Lu rng cc xung PROG i hi thi gian khng vt qu 1.5 ms, ch c ch xo chip cn xung 10ms. S mch lp trnh v kim tra cho AT89C51 m t nh hnh 1.14 v 1.15.
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Address 0000h 0FFFh
Xem bng 1.9
Hnh 1.14 S mch lp trnh cho AT89C51
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Address 0000h 0FFFh
Xem bng 1.9
Hnh 1.15 S mch kim tra cho AT89C51
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Cc dng tn hiu dng lp trnh cho AT89C51 c m t nh hnh 1.16 v 1.17.
Hnh 1.16 Dng sng lp trnh in p 12V
Hnh 1.17 - Dng sng lp trnh in p 5V
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Khi lp trnh, cc thng s v thi gian v in p c m t nh bng 1.10. Bng 1.10 Cc c tnh lp trnh v kim tra T = 0 700C, VCC = 5V 10% K M t hiu VPP (1) in p lp trnh IPP (1) Dng in lp trnh 1/tCLCL Tn s thch anh Khong thi gian t lc a ch n nh cho n tAVGL khi c th to xung PROG (xung mc thp) Khong thi gian gi li a ch sau khi chn tGHAX PROG ln mc cao Khong thi gian t lc d liu n nh cho n tDVGL khi c th to xung PROG (xung mc thp) Khong thi gian gi li d liu sau khi chn tGHDX PROG ln mc cao Khong thi gian t lc P2.7 (ENABLE) ln mc tEHSH cao n khi Vpp chuyn n gi tr in p lp trnh (5V/12V) Khong thi gian t lc Vpp chuyn ln gi tr tSHGL in p lp trnh n khi chn PROG xung mc thp tGHSL Khong thi gian t lc chn PROG ln mc cao (1) n khi Vpp chuyn xung gi tr in p thp tGLGH rng xung lp trnh tAVQV Khong thi gian t lc a a ch cho n lc (2) c th c d liu tELQV Khong thi gian t lc chn P2.7 (ENABLE) (2) xung mc thp n khi c th c d liu tEHQZ Khong thi gian t lc chn P2.7 (ENABLE) ln (2) mc cao n khi th ni ng d liu Khong thi gian t lc chn PROG ln mc cao tGHBL n khi chn P3.4 (BUSY) xung mc thp Chu k ghi byte tWC (1) Ch dng cho in p lp trnh 12V (2) Dng cho ch kim tra (Tham kho thm mt mch lp trnh cho AT89C51 ti Ph lc 3)
Min 11.5 3 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10
Max 12.5 1.0 24
n v V mA MHz
s 10 1 110 48tCLCL 48tCLCL 0 48tCLCL 1.0 2.0 s ms s s
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2.7.3. Cc c tnh ca AT89C51 2.7.3.1. c tnh DC
Bng 1.11 c tnh DC ca AT89C51 T = - 40 850C; VCC = 5V 20% K M t iu kin hiu VIL in p ng vo mc thp Tr EA VIL1 in p ng vo mc thp EA Tr XTAL1, VIH in p ng vo mc cao RST VIH1 in p ng vo mc cao XTAL1, RST in p ng ra mc thp VOL IOL = 1.6 mA (1) (Port 1,2,3) in p ng ra mc thp VOL1 IOL = 3.2 mA (1) (Port 0,ALE, PSEN ) VOH in p ng ra mc cao (Ports 1,2,3, ALE, PSEN ) in p ng ra mc cao (Port 0 trong ch a ch d liu a hp) Dng ng vo mc 0 (Port 1,2,3) Dng in xy ra khi chuyn mc logic t 1 xung 0 (P1, 2, 3) Dng in ng vo in tr ko xung ti ng Reset in dung ti cc chn Dng ti thiu ca ngun cung cp Ch ngun gim (2)
IOH = -60 A VCC = 5V 10%
Min -0.5 -0.5

0.2 VCC + 0.9
Max
0.2 VCC - 0.1 0.2 VCC - 0.3
n v V V V V V V V V V V V V
VCC + 0.5 VCC + 0.5 0.45 0.45
0.7 VCC
2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650 10 50 300 10 20 5 100 40
VOH1
IOH = -800 A VCC = 5V 10%
IOH = -25 A IOH = -10 A
IOH = -300 A IOH = -80 A VIN = 0.45V VIN = 2V, VCC = 5V 10% 0.45 < VIN < VCC
Tn s = 1 MHz TA = 25C
IIL ITL ILI RRST CIO
A A A K pF mA mA A A
ICC
Ch thng 12 MHz Ch ngh 12 MHz VCC = 6V VCC = 3V
(1) ch thng, IOL xc nh nh sau: IOLmax ti mi chn l 10 mA.
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IOLmax ti mi port 8 bit: 26 mA cho Port 0 v 15 mA cho Port 1,2,3. IOLmax ti tt c cc ng vo: 71 mA. Nu IOL khng tho mn cc iu kin trn, in p VOL c th s ln hn gi tr trong bng 1.11 (2) in p Vcc ti thiu trong ch ngun gim l 2V. 2.7.3.2. c tnh AC
Thch anh 16 - 24 MHz
Bng 1.12 c tnh AC ca AT89C51 Thch anh 12 K MHz M t hiu Min Max 1/tCLCL Tn s thch anh tLHLL rng xung ALE 127 Khong thi gian t lc a ch n nh tAVLL 43 n khi ALE xung mc thp Khong thi gian gi tLLAX li a ch sau khi 48 ALE xung mc thp Khong thi gian t lc ALE xung mc tLLIV 233 thp n khi m lnh vo hp l Khong thi gian t lc ALE xung mc 43 tLLPL thp n khi PSEN xung mc thp 205 tPLPH rng xung PSEN Khong thi gian t lc PSEN xung tPLIV 145 mc thp n khi m lnh vo hp l Khong thi gian gi li m lnh sau tn tPXIX 0 hiu PSEN Khong thi gian t tAVIV lc t a ch n khi 312 m lnh vo hp l Khong thi gian th ni ng vo m lnh tPXIZ sau tn hiu PSEN
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n v MHz ns ns
Min 0
2tCLCL-40
Max 24
tCLCL-13
tCLCL-20
ns
4tCLCL-65
ns
tCLCL-13
3tCLCL-20
ns ns 3tCLCL-45 ns
ns
5tCLCL-55
ns
tCLCL-10
ns
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tPXAV
tPLAZ tRLRH tWLWH tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH tWHQX
Khong thi gian t tn hiu PSEN n khi a ch hp l Khong thi gian t lc PSEN xung mc thp n khi th ni a ch rng xung RD rng xung WR Khong thi gian t lc RD xung mc thp n khi d liu vo hp l Khong thi gian gi li d liu sau tn hiu RD Khong thi gian th ni d liu sau tn hiu RD Khong thi gian t lc ALE xung mc thp n khi d liu hp l Khong thi gian t lc t a ch n khi d liu hp l Khong thi gian t lc ALE xung mc thp n khi RD hay WR xung mc thp Khong thi gian t lc t a ch n khi RD hay WR xung mc thp Khong thi gian t lc d liu hp l n khi WR chuyn mc logic Khong thi gian t lc d liu hp l n khi WR ln mc cao Khong thi gian gi
75
tCLCL-8
ns
10 400 400 252

6tCLCL-100 6tCLCL-100
10
ns ns ns
5tCLCL-90
ns
97
2tCLCL-28
ns
517
8tCLCL-150
ns
585
9tCLCL-165
ns
200
300
3tCLCL-50
3tCLCL+50
ns
203
4tCLCL-75
ns
23
tCLCL-20
ns
433 33
7tCLCL-120
ns ns
tCLCL-20
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tRLAZ
tWHLH
li d liu sau tn hiu WR Khong thi gian t lc RD xung mc thp n khi th ni a ch Khong thi gian t lc RD hay WR ln mc cao n khi ALE ln mc cao
ns ns ns ns ns ns ns ns
43
123
tCLCL-20
tCLCL+25
Cc c tnh AC c m t trong cc hnh v sau:
Hnh 1.18 Chu k c b nh chng trnh ngoi
Hnh 1.19 Chu k c b nh d liu ngoi
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Hnh 1.20 Chu k ghi d liu b nh ngoi
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BI TP CHNG 1
1. Gii thch ti sao thng phi c in tr ko ln (pull-up) ti Port 0? Trng hp no khng cn s dng in tr ny? 2. Thit k mch gii m a ch dng 74LS138 cho 1 RAM 8 KB, 1 RAM 4KB v 1 ROM 16 KB. 3. Cho bn b nh sau:
B nh a ch RAM1 1000h 1FFFh RAM2 3800h 3FFFh ROM 8000h 9FFFh
Lp bn b nh y v thit k mch gii m a ch theo bn trn. 4. Cho mch nh hnh v. Xc nh a ch cc chn CS. Cho bit chn no dng c, chn no dng ghi.
DATA BUS
U14 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ALE 3 4 7 8 13 14 17 18 11 1 U16 D0 D1 D2 D3 D4 D5 D6 D7 LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 RD WR A0 A1 A2 A3 A4 A5 A6 A7
1 2 4 5 9
CS1
CS3
U15 74LS373 A5 A6 A7 VCC 1 2 3 6 4 5 A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7
10 CS2 12 13 CS6 CS7 CS8
CS4
WR RD ALE
11
CS5
74LS138
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Lp trnh hp ng trn vi iu khin MCS-51
Chng 2: LP
TRNH HP NG TRN VI IU KHIN MCS-51
Chng ny gii thiu cch thc lp trnh trn MCS-51 cng nh gii thch hot ng ca cc lnh s dng cho h MCS-51. Cc k hiu cn ch : Rn : cc thanh ghi t R0 R7 (bank thanh ghi hin hnh) Ri : cc thanh ghi t R0 R1 (bank thanh ghi hin hnh) @Rn : nh a ch gin tip 8 bit dng thanh ghi Rn @DPTR : nh a ch gin tip 16 bit dng thanh ghi DPTR direct : nh a ch trc tip RAM ni (00h 7Fh) hay SFR (80h FFh) (direct) : ni dung ca b nh ti a ch direct #data8 : gi tr tc thi 8 bit #data16 : gi tr tc thi 16 bit bit : a ch bit ca cc nh c th nh a ch bit (00h 7Fh i vi a ch bit v 20h 2Fh i vi a ch byte)
1. Cc phng php nh a ch
nh a ch trc tip nh a ch trc tip ch dng cho cc thanh ghi chc nng c bit v RAM ni ca 8951. Gi tr a ch trc tip 8 bit c thm vo pha sau m lnh. Nu a ch trc tip t 00h 7Fh th l RAM ni ca 8951 (128 byte), cn a ch t 80h FFh l a ch cc thanh ghi chc nng c bit (xem bng 1.2, chng 1). Cc lnh sau c kiu nh a ch trc tip: MOV A, P0 MOV A, 30h Lnh u tin chuyn ni dung t Port 0 vo thanh ghi A. Khi bin dch, chng trnh s thay th t gi nh P0 bng a ch trc tip ca Port 0 (80h) v a vo byte 2 ca m lnh. Lnh th hai chuyn ni dung ca RAM ni c a ch 30h vo thanh ghi A. nh a ch gin tip nh a ch gin tip c th dng cho c RAM ni v RAM ngoi. Trong ch ny, a ch ca RAM xc nh thng qua mt thanh ghi (R0, R1, SP cho a ch 8 bit v DPTR cho a ch 16 bit). Cc lnh sau c kiu a ch gin tip: MOV A, @R0
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MOVX A, @DPTR Lnh u tin chuyn ni dung ca RAM ni c a ch cha trong thanh ghi R0 vo thanh ghi A (gi s R0 = 30h th chuyn ni dung ca nh 30h). Lnh th hai chuyn ni dung RAM ngoi vo thanh ghi A (a ch RAM cha trong DPTR). nh a ch thanh ghi Cc thanh ghi t R0 R7 c th truy xut bng cch nh a ch trc tip hay gin tip nh trn. Ngoi ra, cc thanh ghi ny cn c th truy xut bng cch dng 3 bit trong m lnh chn 1 trong 8 thanh ghi (8 thanh ghi ny c a ch trc tip thay i tu theo bank thanh ghi ang s dng). nh a ch tc thi Gi tr ca mt hng s c th a trc tip vo m lnh ca chng trnh. Trong hp ng, hng s c xc nh bng cch s dng du #. Lnh: MOV A, #10h c ch a ch tc thi. nh a ch ch s Qu trnh nh a ch ch s ch c th dng cho b nh chng trnh, c dng c d liu trong cc bng tm kim. Ch ny thng dng mt thanh ghi nn 16 bit (PC hay DPTR) ch v tr ca bng v thanh ghi A ch v tr ca cc phn t trong bng.
2. Cc vn lin quan khi lp trnh hp ng

2.1.
Nhn A: LED On_Led
C php lnh
Lnh MOV EQU BIT Ton hng A, #10h 30h 00h Ch thch ; a gi tr 10h vo thanh ghi A ; nh ngha nh cha m led ; C trng thi led
Mt lnh trong chng trnh hp ng c dng nh sau:
Trng nhn nh ngha cc k hiu (c th l a ch trong chng trnh, cc hng d liu, tn on hay cc cu trc lp trnh). Trng nhn khng bt u bng s v khng trng vi cc t kho c sn. Trng lnh cha cc t gi nh cho cc lnh ca MCS-51 hay cc lnh gi dng cho chng trnh dch.
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Trng ton hng cha cc thng s lin quan n lnh ang s dng. Trng ch thch dng ghi ch trong chng trnh hp ng. Trng ny phi c bt u bng du ; v chng trnh dch s b qua cc t t sau du ;. Lu rng cc chng trnh dch khng phn bit ch hoa v ch thng.
2.2.
-
Khai bo d liu
Khi khai bo hng s, ch h cui cng xc nh hng s l s thp lc phn; ch b cui cng xc nh s nh phn v ch d cui (hay khng c) xc nh s thp phn. Lu rng i vi s thp lc phn, khi bt u bng ch A F th phi thm s 0 vo pha trc.
V d: 1010b ; S nh phn 1010h ; S thp lc phn 1010 ; S thp phn 0F0h ; S thp lc phn nhng bt u bng ch F nn phi thm vo pha trc s 0. Khi dng du # pha trc mt con s, chnh l d liu tc thi cn nu khng dng du # th l a ch ca nh. Lu rng khi dng RAM ni th ch dng a ch t 00 7Fh cn vng a ch t 80h 0FFh dng cho cc thanh ghi chc nng c bit. i vi h 89x52, RAM ni c 256 byte th cc byte a ch cao (t 80h 0FFh) khng th truy xut trc tip m phi truy xut gin tip.
V d: MOV A,30h MOV A,#30h MOV A,80h MOV R0,#80h MOV A,@R0 ; ; ; ; ; ; Chuyn ni dung nh 30h vo A Chuyn gi tr 30h vo A Chuyn ni dung Port 0 vo A (80h l a ch Port 0 Chuyn ni dung nh 80h vo A (ch dng cho h 89x52)
nh ngha trc mt vng nh trong b nh chng trnh, c th dng cc ch dn DB (define byte nh ngha 1 byte) hay DW (define word nh ngha 2 byte).
V d: nh ngha trc d liu cho led nh sau:
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Led: DB
01h,02h,04h,08h,10h,20h,40h,80h
on chng trnh ny xc nh ti nhn Led c cha cc gi tr ln lt t 01h n 80h. Nu nhn Led t ti a ch 100h th gi tr tng ng nh sau: a ch 100h 101h 102h 103h 104h 105h 106h 107h Gi tr 01h 02h 04h 08h 10h 20h 40h 80h
d nh v d hiu khi lp trnh, cc chng trnh dch cho php dng cc k t thay th cho cc nh bng cc lnh gi EQU, BIT.
V d: LED EQU 30h ON_LED BIT 00h Gi s chng trnh hp ng c cc lnh sau: MOV A,LED SETB ON_LED Khi bin dch, chng trnh dch s t ng chuyn thnh dng lnh sau: MOV A,30h SETB 00h
2.3.
Cc ton t
Cc ton t s hc: Bao gm cc ton t +, -, *, /, mod. V d: Cc lnh sau tng ng: MOV A,#12h MOV A,#21 mod 2 MOV A,#12/4 MOV A,#10h + 2h MOV A,#1 MOV A,#3
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Cc ton t logic: Bao gm cc ton t: OR, AND, NOT, XOR. V d: Cc lnh sau tng ng: MOV A,#01h MOV A,#-5 MOV A,#24h MOV A,#03h AND 91h MOV A,#NOT 5 MOV A,#20h OR 04h
Cc ton t quan h: Bao gm cc ton t: EQ (=), NE (<>), LT ( <), LE (<=), GT (>), GE (>=). Lu rng kh s dng cc ton t quan h, ch c 2 kt qu: sai (= 0) hay ng (= FFh hay FFFFh tu theo kt qu l 8 bit hay 16 bit). V d: Cc lnh sau tng ng: MOV A,#00h MOV A,#0FFh MOV DPTR,#0FFFFh Cc ton t khc: Bao gm cc ton t: SHR (dch phi), SHL (dch tri), HIGH (byte cao), LOW (byte thp), (, ). V d: Cc lnh sau tng ng: MOV A,#06h MOV A,#01h MOV A,#02h MOV A,#03h SHL 1 MOV A,#HIGH 0123h MOV A,#LOW 0102h MOV A,#5 EQ 6 MOV A,#7 < 9 MOV DPTR,#5 NE 6
2.4.
-
Cu trc chng trnh

; t lnh LJMP main ti a ch ; 0000h (a ch bt u khi ; reset AT89C51)
Cu trc chng trnh hp ng c bn m t nh sau: ORG 0000h LJMP main
ORG 0030h Main:
; Vng a ch 0003h 002Fh ; dng cha cc chng trnh ; phc v ngt
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CALL Subname ;-------------Subname: RET END ; kt thc chng trnh
Cc lnh gi ORG cho bit lnh pha sau t ti v tr no trong chng trnh. Lu rng khi khi ng, chng trnh trong AT89C51 s c thc thi ti a ch 0000h nn thng thng ti a ch ny s c lnh LJMP main xc nh chng trnh chnh s bt u ti nhn main. Cc du ; xc nh y l mt ch thch, chng trnh dch s b qua tt c cc phn nm sau du ;. Cc a ch t 0003h 002Fh phc v cho mc ch x l ngt nn khng s dng. Tuy nhin, nu chng trnh khng cn x l ngt th cng c th s dng lun vng a ch ny. Khi thc hin son tho chng trnh hp ng, c th dng bt k chng trnh son tho khng nh dng (nh NotePad, Norton Commander, ) v thng lu file vi phn m rng .asm, .a51 (tu theo chng trnh dch). Sau khi son tho, dng mt chng trnh dch chuyn t file vn bn thnh file .hex (c th dng sim51.exe, oh.exe). Ngoi ra, c nhiu chng trnh son tho bao gm c chng trnh dch bn trong (xem thm phn ph lc). Khi dch ra file .hex, dng mt mch np np file .hex vo AT89C51 (xem thm ph lc).
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3. Tp lnh
3.1. Nhm lnh chuyn d liu
3.1.1. RAM ni Cc lnh trong nhm lnh chuyn d liu trong RAM ni m t nh bng sau: Bng 2.1 Cc lnh chuyn d liu trong RAM ni Lnh MOV A,(byte) MOV (byte),A MOV (byte1),(byte2) MOV DPTR,#data16 PUSH (byte) POP (byte) XCH A,(byte) Hot ng A = (byte) (byte) = A (byte1) = (byte2) DPTR = data16 SP = SP + 1 [SP] = (byte) (byte) = [SP] SP = SP 1 Chuyn i d liu gia ACC v (byte) Chuyn i 4 bit thp gia ACC v @Ri Tc thi x x x x x x x x Ch a ch Trc tip Gin tip x x x x x x Thanh ghi x x x Chu k thc thi 1 1 2 2 2 2 1
XCHD A,@Ri
Lnh MOV (Move): Di chuyn d liu gia cc thanh ghi v b nh trong 128 byte RAM c a ch t 80h FFh (ch c trong 8x52) ch c th truy xut bng cch nh a ch gin tip. Cc dng ca lnh MOV nh sau: MOV A, Rn MOV Rn, A MOV A, direct MOV direct, A MOV A,@Ri MOV @Ri,A
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; Chuyn ni dung thanh ghi Rn vo thanh ghi A ; Chuyn ni dung thanh ghi A vo thanh ghi Rn ; Chuyn ni dung nh trc tip vo thanh ghi A ; Chuyn ni dung thanh ghi A vo nh trc tip ; Chuyn ni dung ca nh c a ch cha trong Ri vo A ; Chuyn ni dung caA vo nh c a ch cha trong Ri
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MOV A, #data8 ; Chuyn gi tr 8 bit vo A MOV Rn, direct; Chuyn ni dung nh trc tip vo thanh ghi Rn MOV direct, Rn ; Chuyn ni dung thanh ghi Rn vo nh trc tip MOV Rn, #data8; Chuyn gi tr 8 bit vo Rn MOV direct, direct; Chuyn ni dung gia 2 nh trc tip MOV direct, @Ri; Chuyn ni dung ca nh c a ch cha trong Ri vo nh trc tip MOV @Ri, direct; Chuyn ni dung ca nh trc tip vo nh c a ch cha trong Ri MOV direct, #data8; Chuyn gi tr 8 bit vo nh trc tip MOV @Ri, #data8; Chuyn gi tr 8 bit vo nh c a ch cha trong Ri MOV C, bit ; Chuyn gi tr 1 bit vo c C MOV bit, C ; Chuyn gi tr c C vo 1 bit MOV DPTR, #data16 ; Chuyn gi tr tc thi 16 bit vo thanh ghi DPTR Trong lnh MOV, khi s dng a ch trc tip t 80h FFh th c th thay bng cc t gi nh ca cc thanh ghi chc nng c bit. V d: lnh MOV A, 80h c th thay th bng lnh MOV A, P0 (xem thm bng 1.2, chng 1). Khi lnh MOV thc hin truy xut bit, cc bit c th l a ch trc tip (t 00h 7Fh) hay cc t gi nh c nh ngha. Cc bit c nh ngha trc m t nh sau: Bng 2.2 Cc bit c nh ngha trc trong 8951 Thanh ghi A T gi nh ACC.0 ACC.7 CY hay C AC F0 RS1 RS0 OV P P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.7 a ch bit E0h E7h D7h D6h D5h D4h D3h D2h D0h 80h 87h 90h 97h A0h A7h B0h B7h Thanh ghi B T gi nh B.0 B.7 SM0 SM1 SM2 REN TB8 RB8 TI RI PS PX1 PT1 PX0 PT0 a ch bit F0h F7h 9Fh 9Eh 9Dh 9Ch 9Bh 9Ah 99h 98h BCh BBh BAh B9h B8h
PSW
SCON
Cc thanh ghi Port
IP
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TF1 TR0 TF0 TR0 IE TCON IE1 IT1 IE0 IT0 V d: Lnh MOV C, P0.0 c th thay bng lnh MOV C, 80h. Lnh PUSH / POP:
EA ES EX1 ET1 EX0 ET0
AFh ACh ABh AAh A9h A8h
8Fh 8Eh 8Dh 8Ch 8Bh 8Ah 89h 88h
Cc lnh ny cho php ct hay ly ni dung ca stack. Khi thc hin lnh PUSH, ni dung thanh ghi SP tng ln 1 v ct byte vo stack. Khi thc hin lnh POP, byte c ly ra t stack v sau gim SP 1 gi tr. Lu rng khi s dng 8951, do b nh ni ch c 128 byte (00h 7Fh) nn gi tr ca SP khng c vt qu 7Fh (nu vt qua th d liu s b mt khi dng lnh PUSH v d liu khng xc nh khi dng lnh POP). Cn i vi 8x52, do RAM ni l 256 byte nn khng c hin tng ny. Cc dng ca lnh PUSH / POP: PUSH direct POP direct ; Ct vo stack ; Ly d liu t stack
Lu rng lnh PUSH v POP ch dng cho a ch trc tip nn khng th thc hin lnh PUSH Rn do thanh ghi Rn c 4 a ch khc nhau tu theo bank thanh ghi s dng. Xt thanh ghi R0: 4 a ch ca R0 ng vi 4 bank l 00h, 08h, 10h, 18h. Mc nh khi reset, bank 0 c s dng nn cc thanh ghi Rn c a ch t 00h 07h. Khi thay v dng lnh PUSH R0, ta c th thay bng lnh PUSH 00h. Lnh XCH / XCHD (Exchange / Exchange Digit): Lnh XCH / XCHD dng hon chuyn 8 bit / 4 bit thp ca thanh ghi A vi cc thanh ghi khc hay b nh (lnh XCHD ch dng cho b nh ni nh a ch gin tip). Cc dng lnh nh sau: XCH A,(byte) ; Hon chuyn 8 bit XCHD A,@Ri ; Hon chuyn 4 bit thp V d: Xt on lnh: MOV A, #30h
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; A = 30h
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MOV R0, #54h ; R0 = 54h MOV 30h, #20h ; nh 30h cha gi tr 20h hay ;(30h) = 20h XCH A, R0 ; Hon chuyn gia A v R0 A = 54h ; v R0 = 30h XCHD A, @R0 ; Chuyn 4 bit thp gia A v nh ; R0 = 30h @R0: ni dung nh 30h 20h ;Chuyn 4 bit thp A = 50h v (30h) = 24h 3.1.2. RAM ngoi Cc lnh trong nhm lnh chuyn d liu trong RAM ngoi m t nh sau: Bng 2.3 Cc lnh chuyn d liu trong RAM ngoi Lnh Hot ng Chu k thc thi MOVX A, @Ri c ni dung t RAM ngoi ti a ch Ri 2 MOVX @Ri, A Ghi vo RAM ngoi ti a ch Ri 2 MOVX A, @DPTR c ni dung t RAM ngoi ti a ch DPTR 2 MOVX @DPTR, A Ghi vo RAM ngoi ti a ch DPTR 2 (MOVX : Move eXternal) i vi cc lnh c / ghi d liu ca RAM ngoi, ch cho php thc hin nh a ch gin tip. Khi a ch RAM l 8 bit th dng thanh ghi R0 hay R1 cn nu l a ch 16 bit th phi dng thanh ghi DPTR. Lu rng khi dng a ch 8 bit th cc bit a ch cao khng s dng nn Port 2 c th s dng cho mc ch khc nhng nu dng a ch 16 bit th Port 2 ch c nhim v l xut 8 bit a ch cao. Khi thc hin lnh c t RAM ngoi, chn RD s xung mc thp cn khi thc hin lnh ghi, chn WR xung mc thp. 3.1.3. Bng tm kim Cc lnh trong nhm lnh tm kim d liu trong bng m t nh sau: Bng 2.4 Cc lnh tm kim d liu Lnh MOVC A, @A + DPTR Hot ng Chu k thc thi 2 2
c ni dung b nh chng trnh ti a ch A + DPTR c ni dung b nh chng trnh ti a MOVC A, @A +PC ch A + PC (MOVC: Move Code)
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Cc lnh ny cho php tm kim d liu nh ngha sn trong b nh chng trnh (nu b nh chng trnh l ROM ngoi th tn hiu c l PSEN ). Cc thanh ghi DPTR hay PC (Program Counter: b m chng trnh xc nh a ch ca lnh k tip s thc hin) cha v tr nn ca cc bng tm kim cn thanh ghi A cha v tr ca phn t (thng thng kch thc 1 phn t trong bng tm kim l 1 byte). V d: Ly phn t th 2 trong bng LED_7S: MOV A, #2 ; Phn t th 2 MOV DPTR, #LED_7S ; a ch nn ca bng tm kim MOVC A, @A + DPTR ; c ni dung phn t LED_7S: DB data8, data8, data8, data8, ; Ni dung bng tm kim c th t tu trong b nh chng trnh s dng thanh ghi PC tm kim d liu, qu trinh tm kim phi thc hin thng qua chng trnh con v bng phi c t ngay sau chng trnh con. V d: Ly phn t th 2 trong bng LED_7S: MOV A, #2 ; Phn t th 2 CALL Read_Led7s Read_Led7s: MOVC A, @A+PC RET LED_7S: DB 0, data8, data8, data8, data8, ; Ni dung bng tm kim Lu rng trong on lnh trn, khi thc hin lnh MOVC, thanh ghi PC s ch n lnh k tip l lnh RET ch khng phi bng LED_7S. Do , bng tm kim trong trng hp ny s khng c phn t 0 m bt u ti phn t 1. chng trnh ging nh cch thc hin dng DPTR, cn phi thay i chng trnh con nh sau: V d: Ly phn t th 2 trong bng LED_7S: MOV A, #2 ; Phn t th 2 CALL Read_Led7s Read_Led7s: INC A ; Tng ni dung A ln 1 hiu chnh v tr bng MOVC A, @A+PC RET
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LED_7S: DB data8, data8, data8, data8, ; Ni dung bng tm kim
3.2.
Nhm lnh x l bit
H MCS-51 cha mt b x l bit hon chnh. RAM ni c 128 bit c th x l bit v cc thanh ghi chc nng c bit c th h tr ln ti 128 bit (cc bit trong SFR xem ti bng 2.2). Cc a ch bit t 00h 7Fh nm trong RAM ni cn cc a ch t 80h FFh nm trong SFR. Cc lnh trong nhm lnh logic m t nh trong bng sau: Bng 2.5 Cc lnh logic Lnh Hot ng Chu k thc thi ANL C,bit C = C AND bit 2 ANL C,/bit C = C AND (NOT bit) 2 ORL C,bit C = C OR bit 2 ORL C,/bit C = C OR (NOT bit) 2 MOV C,bit C = bit 1 MOV bit,C Bit = C 2 CLR C C=0 1 CLR bit Bit = 0 1 SETB C C=1 1 SETB bit Bit = 1 1 CPL C C = NOT C 1 CPL bit Bit = NOT bit 1 JC rel Nhy n nhn rel nu C = 1 2 JNC rel Nhy n nhn rel nu C = 0 2 JB bit,rel Nhy n nhn rel nu bit = 1 2 JNB bit,rel Nhy n nhn rel nu bit = 0 2 JBC bit,rel Nhy n nhn rel nu bit = 1 v sau xo bit 2 ANL: And logic; ORL: Or logic; CLR: Clear; CPL: Complement Bit: cc bit trong RAM ni t 00h 7Fh hay trong SFR theo bng 2.2 Rel: a ch tng i (cho php trong vng t -128 127 byte trong b nh chng trnh) V d: Chuyn t bit 00h vo P1.0 MOV C, 00h ; Chuyn bit 00h vo c Carry MOV P1.0, C ; Chuyn c Carry vo P1.0 Lu rng trong tp lnh logic khng c lnh XOR m phi thc hin bng phn mm, c th nh sau: Thc hin lnh C = C XRL bit:
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Gio trnh Vi iu khin
JNB bit, next CPL C Next: Ngoi ra, cc lnh nhy trn u dng a ch tng i, ngha l ch cho php trong vng t -128 127 byte. Nu cn nhy n da ch xa hn th phi dng cc lnh nhy khc, nh m t trong phn sau.
3.3.
Nhm lnh chuyn iu khin
Nhm lnh chuyn iu khin bao gm cc lnh nhy, cc lnh lin quan n chng trnh con, m t nh sau: Bng 2.6 Cc lnh chuyn iu khin Lnh Hot ng JMP addr Nhy ti nhn addr JMP @A+DPTR Nhy ti a ch A + DPTR CALL addr Gi chng trnh con ti a ch addr RET Tr v t chng trnh con RETI Tr v t chng trnh con phc v ngt NOP Khng lm g c JMP: Jump RET: Return RETI: Return from Interrupt NOP: No Operation Lnh Hot ng Tc thi JZ rel Chu k thc thi 2 2 2 2 2 1
Ch a ch Trc tip Gin tip Thanh ghi
Chu k thc thi
Nhy n nhn rel Ch dng cho thanh ghi A nu A = 0 Nhy n nhn rel JNZ rel Ch dng cho thanh ghi A nu A 0 (byte) = (byte) - 1 DJNZ Nu (byte) 0 th x x (byte),rel nhy n nhn rel CJNE Nhy n nhn rel x x A,(byte),rel nu A (byte) CJNE (byte), Nhy n nhn rel x x #data8,rel nu (byte) data8 JZ: Jump if Zero; JNZ: Jump if Not Zero DJNZ: Decrement and Jump if Not Zero
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2 2 2 2 2
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Gio trnh Vi iu khin
CJNE: Compare and Jump if Not Equal Lnh JMP (Jump): Lnh JMP bao gm 3 lnh: LJMP (Long jump), AJMP (Absolute jump) v SJMP (Short jump) cho php nhy n mt v tr bt k trong chng trnh. Lnh LJMP c kch thc 3 byte trong 1 byte m lnh v 2 byte cha a ch nhn nn phm vi biu din a ch l 64K (2 byte = 16 bit phm vi biu din 216 = 26 x 210 = 64K). Do lnh LJMP c th thc hin nhy n bt k v tr no trong chng trnh v a ch s dng trong lnh LJMP l a ch tuyt i. Lnh SJMP c kch thc 2 byte trong c 1 byte m lnh v 1 byte a ch nn phm vi biu din a ch l 256 byte. Trong lnh ny, a ch s dng khng phi l a ch tuyt i m l a ch tng i (khong nhy tnh t v tr bt u lnh). Do byte a ch s dng phng php b 2 nn phm vi biu din t -128 + 127, ngha l phm vi nhy ca lnh SJMP ch trong phm vi t - 128 n 127 byte. Phm vi thc hin m t nh hnh v.
128 byte SJMP rel
127 byte
Hnh 2.1 Phm vi thc hin ca lnh SJMP Lnh AJMP c kch thc 2 byte trong a ch cha trong 11 bit nn phm vi biu din a ch l 211 (2K). Trong khi , vng a ch ti a ca MCS-51 l 64K nn khi thc hin lnh AJMP, 64K chng trnh phi chia thnh tng vng 2K (tng cng 32 vng) v lnh AJMP ch c th thc hin trong mt vng. Tuy nhin, khi lp trnh cho MCS-51, thng thng cc chng trnh dch u cho php s dng lnh JMP thay th cho 3 lnh trn. Khi bin dch, chng trnh dch s t ng thay th bng cc lnh thch hp.
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Gio trnh Vi iu khin 0000h 2K AJMP rel 07FFh
Phm vi thc hin
F800h 2K AJMP rel FFFFh Phm vi thc hin
Hnh 2.2 Phm vi thc hin ca lnh AJMP Lnh JMP @A + DPTR cho php chn cc v tr nhy khc nhau tu theo gi tr trong thanh ghi A. a ch nhy n chnh l tng gi tr ca thanh ghi A v DPTR. V d: MOV DPTR, # JUMP_TABLE MOV A, INDEX_NUMBER MOV B, #3 MUL AB JMP @ A + DPTR JUMP_TABLE: LJMP LABEL0 LJMP LABEL1 LJMP LABEL2 LJMP LABEL3 LJMP LABEL4 ; ; ; ; a ch bng nhy V tr nhy x3 do lnh LJMP c kch thc 3
; ; ; ; ;
V V V V V
tr tr tr tr tr
nhy nhy nhy nhy nhy
0 1 2 3 4
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Gio trnh Vi iu khin
Lnh CALL, RET, RETI: Lnh CALL dng gi chng trnh con, bao gm 2 lnh: ACALL (Absolute Call) v LCALL (Long Call). V tr c th gi lnh CALL ging nh xt trong lnh JMP. Khi lp trnh, thng thng cc chng trnh dch cng cho php thay th duy nht bng lnh CALL v khi bin dch, lnh CALL s c thay th bng lnh ACALL hay LCALL tu theo v tr gi lnh. Lu rng khi thc hin lnh CALL th trong chng trnh con phi kt thc bng lnh RET. Ngoi ra, khi s dng cc chng trnh con phc v ngt, khi kt thc phi dng lnh RETI. Lnh RETI v lnh RET ch khc nhau ch lnh RETI bo cho h thng iu khin ngt bit rng qu trnh x l ngt thc hin xong. Lnh JZ, JNZ: Lnh JZ v JNZ dng kim tra ni dung ca thanh ghi A. Lnh JZ nhy khi A = 0 v JNZ nhy khi A 0. Lu rng phm vi nhy ch cho php trong khong t -128 127 byte (ging nh khi s dng lnh SJMP). Lnh DJNZ: Lnh DJNZ thng c dng to vng lp. S ln lp c chuyn vo thanh ghi m u vng lp (thanh ghi m c th dng bt k thanh ghi no hay l b nh). V d: MOV R7, #10 ; Lp 10 ln LOOP: DJNZ R7, LOOP Lnh CJNE: Lnh CJNE dng so snh 2 gi tr vi nhau, khi 2 gi tr ny khc nhau th s thc hin lnh nhy. Lu rng trong tp lnh ca MCS-51 khng c lnh ln hn hay nh hn nn ch c th thc hin cc lnh ny bng cch kt hp lnh CJNE v ni dung ca c Carry. Trong lnh CJNE, nu byte u tin nh hn byte th hai th CF = 1. Ngc li (byte u tin ln hn hay bng byte th hai) th CF = 0. V d: Kim tra ni dung ca thanh ghi A, nu A nh hn 10 th xut gi tr trong thanh ghi A ra Port 1. Ngc li th xut gi tr 10 ra Port 1.
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Gio trnh Vi iu khin
CJNE A,#10,Khacnhau; JMP Xuat10 ; Khacnhau: JC XuatA ; Xuat10: ; MOV P1,#10 SJMP Tiep XuatA: MOV P1,A Tiep:
So snh A vi 10 Nu A = 10 th xut gi tr 10 Nu CF = 1 (A < 10) th xut ni dung trong A ra P1
3.4.
Nhm lnh logic
Nhm lnh logic bao gm cc lnh lin quan n x l logic theo tng byte, m t nh sau: Bng 2.7 Cc lnh logic Lnh Hot ng Tc thi x Ch a ch Trc tip x x x x x x x x x x x Ch dng cho thanh ghi A Ch dng cho thanh ghi A Ch dng cho thanh ghi A Ch dng cho thanh ghi A Ch dng cho thanh ghi A x x x x Gin tip x Thanh ghi x Chu k thc thi
ANL A,(byte) ANL (byte),A ANL (byte),#data8 ORL A,(byte) ORL (byte),A ORL (byte),#data8 XRL A,(byte) XRL (byte),A XRL (byte),#data8 CLR A CPL A RR A RLC A RL A
A = A AND (byte) (byte)=(byte) AND A (byte)=(byte)AND data8 A = A OR (byte) (byte)=(byte) OR A (byte)=(byte) OR data8 A = A XOR (byte) (byte)=(byte) XOR A (byte)=(byte) XOR data8 A=0 A = NOT A Quay phi thanh ghi A 1 bit Quay phi thanh ghi A v CF 1 bit Quay tri thanh ghi A 1 bit
1 1 2 1 1 2 1 1 2 1 1 1 1 1
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Gio trnh Vi iu khin
Quay tri thanh ghi A Ch dng cho thanh ghi A v CF 1 bit i v tr nibble cao SWAP A Ch dng cho thanh ghi A v thp ca ACC RL: Rotate Left, RLC: Rotate Left through Carry RR: Rotate Right; RRC: Rotate Right through Carry RLC A Lnh ANL, ORL, XRL:
1 1
Cc lnh logic ny thc hin ging nh trong cc lnh x l bit nhng thc hin trn 8 bit ca cc thanh ghi hay b nh. Lnh XRL cn c dng o tt c cc bit nh sau: XRL P0, #0FFh Lnh RR, RRC, RL, RLC: Cc lnh ny dng quay phi hay quay tri thanh ghi A 1 bit. V d: Gi s thanh ghi A = 39h (0011 1001b), CF = 1. Ni dung thanh ghi A sau khi thc hin cc lnh quay tng ng nh sau: RR A: Trc khi quay: 0 0 1 1 1 0 0 1
Sau khi quay: 0 0 RL A: A = 0111 0010b (72h) RRC A: Trc khi quay:
ACC 0 0 1 1 1 0 0 1
CF 1
Sau khi quay: ACC 1 0 0 1 1 1 0 0 CF 1
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Gio trnh Vi iu khin
RLC A: A = 0111 0011b (73h); CF = 0 Lnh SWAP: Lnh SWAP A dng hon chuyn ni dung 2 nibble trong thanh ghi A. V D: Nu ni dung thanh ghi A = 39h th sau khi thc hin lnh SWAP A, ni dung thanh ghi A l 93h.
3.5.
Nhm lnh s hc
Cc lnh trong nhm lnh s hc m t nh trong bng sau: Bng 2.8 Cc lnh s hc Lnh ADD A,(byte) ADDC A,(byte) SUBB A,(byte) INC A INC (byte) INC DPTR DEC A DEC (byte) MUL AB DIV AB DA A Hot ng Tc thi A=A+ (byte) A=A+ (byte) + C A=A(byte) - C A=A+1 (byte) = (byte) + 1 DPTR = DPTR + 1 A=A-1 (byte) = (byte) - 1 B_A = B x A A = A div B B = A mod B Hiu chnh trn s BCD Lnh ADD: Thc hin cng gia thanh ghi tch lu A v mt ton hng khc. Lnh ADD nh hng n cc c Carry (C), Overflow (OV) v Auxiliary (AC).
Ch a ch Trc tip x x x Gin tip Thanh ghi x x x x x x
Chu k thc thi 1 1 1 1 1 2 1 1 4 4 1
x x x
Ch dng cho thanh ghi tch lu ACC x x x
Ch dng cho thanh ghi con tr lnh DPTR Ch dng cho thanh ghi tch lu ACC x x x
Ch dng cho thanh ghi tch lu ACC v thanh ghi B Ch dng cho thanh ghi tch lu ACC v thanh ghi B Ch dng cho thanh ghi tch lu ACC
Gio trnh Vi iu khin
Lnh ADD c 4 ch a ch khc nhau: ADD A, #30h ; nh a ch tc thi (A = A + 30h)
ADD A, 30h ; nh a ch trc tip (A = A + [30h] trong [30h] l gi tr ca RAM ni c a ch 30h) ADD A, @R0 ; nh a ch gin tip (A = A + [R0] trong [30h] l gi tr ca RAM ni c a ch cha trong thanh ghi R0) ; R0 = 30h
MOV R0,#30h
ADD A,@R0 ; A = A + [R0] = A + [30h] (cng ni dung ca thanh ghi ACC vi RAM ni c a ch 30h) ADD A,R0 ; nh a ch thanh ghi (A = A + R0)
Lnh ADDC, SUBB: Thc hin cng hay tr ni dung ca thanh ghi A vi mt ton hng khc trong c dng thm c Carry. Lnh ADDC v SUBB nh hng n cc c C, OV v AC. Lnh MUL: Nhn ni dung ca thanh ghi A vi thanh ghi B. Lnh MUL nh hng n c OV v xo c C (C = 0). V d: MOV MOV MUL A,#50 ; 50 x 25 = 1250 04E2h B,#25 ; byte cao = 04h, byte thp = E2h AB ; B = 04h, A = E2h Lnh DIV:
Chia ni dung ca thanh ghi A cho thanh ghi B. Lnh DIV nh hng n c OV v xo c C (C = 0). V d: MOV MOV DIV A,#250 ; 250 / 40 = 6 d 10 B,#40 ; AB ; B = 0Ah (10), A = 06h Lnh DA A:
Hiu chnh ni dung thanh ghi A sau khi thc hin cc php ton lin quan n s BCD. Qu trnh thc hin lnh DA A m t nh sau:
Gio trnh Vi iu khin
Nu A[3-0] > 9 hay AC = 1 th A[3-0] = A[3-0] + 6 Nu A[7-4] > 9 hay C = 1 th A[7-4] = A[7-4] + 6
Lnh DA A cng nh hng n c C.
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Gio trnh Vi iu khin
BI TP CHNG 2
1. Xc nh gi tr ca cc biu thc sau: a. (10 SHL 2) OR ( 1000 1000b) b. (5*2 10 SHR 1) AND (11h) c. HIGH(10000) d. LOW(-30000) 2. Vit on chng trnh c ni dung ca nh 30h. Nu gi tr c ln hn hay bng 10 th xut 10 ra P0, ngc li th xut gi tr va c ra P0. 3. Vit on chng trnh xut cc gi tr trong nh 30h 3Fh ra P1 (gia cc ln xut c thi gian tr hon). 4. Vit on chng trnh theo yu cu sau: c d liu t P1 (10 ln) v lu gi tr c mi ln vo nh 30h 39h (mi ln c c tr hon mt khong thi gian). Tm gi tr ln nht trong cc nh 30h 39h, lu vo nh 3Ah v xut gi tr ny ra P2. Kim tra ni dung nh 3Ah, nu = 0 th quay li u chng trnh, ngc li th xut gi tr ny ra P3.
5. Vit on chng trnh theo yu cu: B1: Kim tra bit P3.0: P3.0 Thc hin = 0 n bc 2 = 1 n bc 3 B2: c d liu t P2, o tt c cc bit v xut ra P0. Sau quay li bc 1. B3: xut ni dung ti nh 30h ra P1 v quay li bc 1
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Gio trnh Vi iu khin
Cc hot ng ca vi iu khin MCS-51
Chng 3: CC
HOT NG CA VI IU KHIN MCS-51
Chng ny gii thiu v cc hot ng c trng ca h vi iu khin MCS51: nh thi, cng ni tip, ngt v cc cch thc iu khin cc hot ng ny.
1. Hot ng nh thi (Timer / Counter)

1.1. Gii thiu
AT89C51 c 2 b nh thi 16 bit c th hot ng cc ch khc nhau v c kh nng nh thi hay m s kin (Timer 0 v Timer 1). Khi hot ng nh thi (timer), b Timer / Counter s nhn xung m t dao ng ni cn khi m s kin (counter), b Timer / Counter nhn xung m t bn ngoi. B Timer / Counter bn trong AT89C51 l cc b m ln 8 bit hay 16 bit tu theo ch hot ng. Mi b Timer / Counter c 4 ch hot ng khc nhau v c dng : m s kin ti cc chn T0 (chn 14) hay T1 (chn 15). Ch mt khong thi gian. To tc cho port ni tip.
Qu trnh iu khin hot ng ca Timer / Counter c thc hin thng qua cc thanh ghi sau: Bng 3.1 Cc thanh ghi iu khin hot ng Timer / Counter Thanh ghi TCON TMOD TL0 TL1 TH0 TH1 a ch byte 88h 89h 90h 91h 92h 93h a ch bit 88h 8Fh Khng Khng Khng Khng Khng
Ngoi ra, trong h 8x52 cn c thm b nh thi th 3 (Timer 2).
1.2.
Hot ng Timer / Counter
Hot ng c bn ca Timer / Counter gm c cc thanh ghi timer THx v TLx (x = 0, 1) mc lin tng to thnh dng thanh ghi 16 bit. Khi set bit TRx trong thanh ghi TCON (xem thm phn 1.3), timer tng ng s hot ng v gi tr trong thanh ghi TLx tng ln 1 sau mi xung m. Khi TLx trn (thay i t 255 0), gi tr ca THx tng ln 1. Khi THx trn, c trn tng ng TFx (trong thanh ghi TCON) s c a ln mc 1.
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Gio trnh Vi iu khin
Tu theo ni dung ca bit C/ T (xem thm thanh ghi TMOD, phn 1.3), xung m c th ly t dao ng ni (C/ T = 0) hay t cc chn Tx bn ngoi (C/ T = 1). Lu rng phi xo bit TRx khi thay i ch hot ng ca Timer. Khi xung m ly t dao ng ni, tc m = fOSC/12 hay fOSC/2 trong ch X2(ngha l nu fOSC = 12 MHz th tc xung m l 1 MHz hay c 1 s th c 1 xung m trong ch d chun) hay tc m = fPER/6 (fPER: tn s xung ngoi vi peripheral clock). Khi ly xung m t bn ngoi (cc chn Tx),b m s tng ln 1 khi ng vo Tx mc 1 trong 1 chu k v xung mc 0 trong chu k k tip. Do , tn s xung ti a ti cc chn Tx l fOSC/24 trong ch thng hay fOSC/12 trong ch X2 (=fPER/12). 1.3. Cc thanh ghi iu khin hot ng
1.3.1. Thanh ghi iu khin timer (TCON Timer/Counter Control Register) TCON cha cc bit trng thi v cc bit iu khin cho Timer 1, Timer 0. Bng 3.2 Ni dung thanh ghi TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 K hiu TCON.7 TF1 Bit a ch 8Fh M t C bo trn timer 1 (Timer 1 overflow Flag). c xo bi phn cng khi chuyn n chng trnh con x l ngt hay xo bng phn mm. t bng phn cng khi Timer 1 trn iu khin Timer 1 chy (Timer 1 Run Control Bit). Cho php Timer 1 hot ng (= 1) hay ngng (= 0). Timer 0 overflow Flag Timer 0 Run Control Bit Dng cho ngt ngoi 0 v 1 (s xt trong phn 3 x l ngt)
TCON.6 TR1 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 TF0 TR0 IE1 IT1 IE0 IT0
8Eh 8Dh 8Ch 8Bh 8Ah 89h 88h
Gi tr khi reset: TCON = 00h
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Gio trnh Vi iu khin
1.3.2. Thanh ghi ch timer (TMOD Timer/Counter Mode) Thanh ghi TMOD cha hai nhm 4 bit dng t ch lm vic cho Timer 0, v Timer 1. Lu rng khi lp trnh cho AT89C51, thng thng thanh ghi TMOD ch c gn mt ln u chng trnh. Bng 3.3 Ni dung thanh ghi TMOD GATE1 C/ T 1 M11 M01 GATE0 C/ T 0 M10 M00 Bit Tn Timer M t 7 GATE1 1 Timer 1 Gating Control Bit GATE = 0: timer hot ng bnh thng GATE = 1: timer ch hot ng khi chn INT1 = 1 Timer 1 Timer/Counter Select Bit = 1: m bng xung ngoi ti chn T1 (chn 15) = 0: m bng xung dao ng bn trong Timer 1 Mode Select Bit M11 M01 Ch 0 0 13 bit 0 1 8 bit t ng np li 1 0 16 bit 1 1 Khng dng Timer 1 Timer 0 Gating Control Bit Timer 0 Timer/Counter Select Bit Timer 0 Mode Select Bit Cc ch ging nh timer 1 trong ch 3 dng TH0 v TL0 lm 2 gi tr m ca timer 0 v timer 1 (xem thm phn 1.4) Timer
C/T1
M11
Dng cho Timer 1
4 3 2 1 0
M01 GATE0 C/T0 M10 M00
1 0 0 0 0
Dng cho Timer 0
Gi tr khi reset: TMOD = 00h Ngoi ra, Timer cn cc thanh ghi cha gi tr m: TH0, TL0 (Timer 0) v TH1, TL1 (Timer 1), mi thanh ghi c kch thc 8 bit. Gi tr cc thanh ghi ny khi reset cng l 00h. 1.4. Cc ch hot ng Cc ch ca timer c xc nh bng 4 bit trong thanh ghi TMOD, trong 4 bit thp iu khin timer 0 v 4 bit cao iu khin timer 1, m t nh sau:
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Gio trnh Vi iu khin
1.4.1. Ch 0 Ch 0 l ch 13 bit bao gm 8 bit ca thanh ghi THx v 5 bit ca thanh ghi TLx cn 3 bit cao ca thanh ghi TLx khng s dng. Mi ln c xung m, gi tr trong thanh ghi 13 bit tng ln 1. Khi gi tr ny thay i t 1 1111 1111 1111b n 0 th b m trn lm cho TFx c t ln mc 1. Do ch 0 s dng 13 bit nn gi tr m ti a l 213 = 8192. Ch ny c cung cp nhm mc ch to kh nng tng thch vi 8048 v thng khng c s dng hin nay.
Hnh 3.1 Ch 0 ca Timer/Counter 1.4.2. Ch 1 Ch 1 ging nh ch 0 nhng s dng 16 bit bao gm 8 bit ca THx v 8 bit ca TLx nn gi tr m ti a l 216 = 65536. Nh vy, ch 0 v ch 1 ging nhau nhng ch khc s bit m nn thng thng ch 0 khng s dng m ch dng ch 1. Khi b m trn (gi tr trong cp thanh ghi THx_TLx thay i t 1111 1111 1111 1111b n 0), c trn TFx c set ln mc 1. Lu rng, khi timer trn, gi tr ca cc thanh ghi m l 0 (THx = 0 v TLx = 0) nn nu mun timer hot ng tip th phi np li gi tr cho cc thanh ghi THx v TLx.
Hnh 3.2 Ch 1 ca Timer/Counter
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Gio trnh Vi iu khin
1.4.3. Ch 2 Ch 2 l ch 8 bit trong s dng thanh ghi TLx cha gi tr m cn thanh ghi THx cha gi tr np li (do ch ny c gi l ch t ng np li autoreload). Trong ch 2, mi khi gi tr trong thanh ghi TLx thay i t 1111 1111b n 0 th c TFx c set ln mc 1 ng thi gi tr trong thanh ghi THx c chuyn vo thanh ghi TLx. Nh vy, gi tr m trong TLx v THx ch c np mt ln khi khi ng timer (c th khng cn np cho TLx nhng khi chu k hot ng u tin ca timer s sai). Ch 2 s dng 8 bit m trong thanh ghi TLx nn gi tr m ti a l 28 = 256.
Hnh 3.3 Ch 2 ca Timer/Counter 1.4.4. Ch 3
Hnh 3.4 Ch 3 ca Timer/Counter Ch 3 s dng cc thanh ghi TL0 v TH0 nh cc b nh thi c lp trong TL0 iu khin bng cc thanh ghi ca timer 0 v TH0 iu khin bng cc thanh ghi ca tmer 1. Khi TL0 chuyn t gi tr 1111 1111b n 0 th TF0 c t ln mc 1 cn TH0 chuyn t 1111 1111b n 0 th TF1 c t ln mc 1. Lu rng trong ch 3 (ch c trong Timer 0), Timer 1 khng tc ng n c TF1 nn thng c
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Gio trnh Vi iu khin
dng to tc baud cho port ni tip (xem thm phn 2 cng ni tip) hay dng cho mc ch khc. Ch ny ch cho php tc ng n c trn TF1 thng qua xung m ca dao ng ni m khng m bng dao ng ngoi ti chn T1 ng thi bit GATE1 (TMOD.7) khng tc ng n qu trnh m ti TH0. 1.5. Timer 2 Timer 2 l b nh thi 16 bit (ch c trong h 8x52). Gi tr m ca timer 2 cha trong cc thanh ghi TH2 v TL2. Ging nh timer 0 v timer1, timer 2 cng hot ng nh b nh thi (timer) hay m s kin (counter). Ch nh thi m bng dao ng ni, ch m s kin m bng xung ngoi ti chn T2 (P1.0) v chn ch bng bit C/ T 2 ca thanh ghi T2CON. Cc thanh ghi iu khin timer 2 bao gm: T2CON, T2MOD, RCAP2H, RCAP2L, TH2 v TL2. Timer 2 c 3 ch hot ng: capture (gi), autoreload (t ng np li) v to tc baud (chn ch trong thanh ghi T2CON). Cc bit chn ch c m t nh bng 3.4. Bng 3.4 Chn ch trong Timer 2 Ch RCLK TCLK CP/ RL 2 TR2 0 0 0 1 T ng np li 16 bit 0 0 1 1 Gi 16 bit X 1 X 1 To tc baud 1 X X 1 X X X 0 Ngng 1.5.1. Cc thanh ghi iu khin Timer 2 Thanh ghi T2CON: Bng 3.5 Ni dung thanh ghi T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T 2 CP/ RL 2 Bit Tn 7 TF2 M t Timer 2 overflow Flag TF2 khng c tc ng khi RCLK hay TCLK = 1. TF2 phi c xo bng phn mm v c t bng phn cng khi Timer trn Timer 2 External Flag c t khi EXEN2 = 1 v xy ra ch np li hay gi do c cnh m ti chn T2EX (P1.1) (chuyn t 1 xung 0). Khi EXF2 = 1 v cho php ngt ti Timer 2 th chng trnh s chuyn n chng trnh phc v ngt ca Timer 2. EXF2 phi c xo bng phn mm
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EXF2
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Gio trnh Vi iu khin
RCLK
4 3
TCLK EXEN2
Receive Clock Bit (ch dng cho port ni tip ch 1 v 3) RCLK = 0: dng timer 1 lm xung clock thu cho port ni tip RCLK = 1: dng timer 2 lm xung clock thu cho port ni tip Transmit Clock Bit Ging nh RCLK nhng dng cho xung clock pht
Timer 2 External Enable Bit = 0: b qua tc ng ti chn T2EX (P1.1) = 1: xy ra ch np li hay gi do c cnh m ti chn T2EX (P1.1) (chuyn t 1 xung 0) TR2 Timer 2 Run Control Bit = 0: cm timer 2 = 1: chy timer 2 C/ T 2 Timer / Counter 2 Select Bit = 0: nh thi (m bng dao ng ni) = 1: m s kin (m bng xung ti T2 (P1.0)) CP/ RL Timer 2 Capture / Reload Bit Nu RCLK = 1 hay TCLK = 1: b qua 2 Nu RCLK = 0 v TCLK = 0: chn ch gi ( = 1) hay np li (= 0) khi xut hin xung m ti T2EX (P1.1) v EXEN2 = 1 Gi tr khi reset: T2CON = 00h, T2CON cho php nh v bit Thanh ghi T2MOD: Bng 3.6 Ni dung thanh ghi T2MOD
- - - - - - T2OE DCEN
Bit 7 6 5 4 3 2 1 Tn M t
T2OE Timer 2 Output Enable Bit = 0: T2 (P1.0) l ng vo clock hay I/O port = 1: T2 l ng ra clock DCEN Down Counter Enable Bit = 0: cm timer 2 l b m ln / xung = 1: cho php timer 2 l b m ln / xung
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Gi tr khi reset: T2MOD = xxxx xx00b, MOD khng cho php nh v bit Cc thanh ghi TH2, TL2, RCAP2H v RCAP2L khng cho php nh v bit v gi tr khi reset l 00h. Cc ch hot ng ca Timer 2 m t trong phn sau.
1.5.2. Ch capture
Hnh 3.5 Ch gi ca Timer 2
Ch gi ca Timer 2 c 2 trng hp xy ra: Nu EXEN2 = 0: Timer 2 hot ng ging nh Timer 0 v 1, ngha l khi gi tr m trn (TH2_TL2 thay i t FFFFh n 0) th c trn TF2 c t ln mc 1 v to ngt ti Timer 2 (nu cho php ngt). Nu EXEN2 = 1: vn hot ng nh trn nhng thm mt tnh cht na l: khi xut hin cnh m ti chn T2EX (P1.1), gi tr hin ti ca TH2 v TL2 c chuyn vo cp thanh ghi RCAP2H, RCAP2L (qu trnh gi (capture) xy ra); ng thi, bit EXF2 = 1 (s to ngt nu cho php ngt ti Timer 2).
1.5.3. Ch t ng np li
Ch t ng np li cng c 2 trng hp ging nh ch gi: Nu EXEN2 = 0: khi Timer trn, c trn TF2 c t ln 1 v np li gi tr cho TH2, TL2 (t cp thanh ghi RCAP2H, RCAP2L) ng thi to ngt ti timer 2 nu cho php ngt. Nu EXEN2 = 1: hot ng ging nh trn nhng khi c xung m ti chn T2EX th cng np li gi tr cho TH2, TL2 v t c EXF2 ln 1.
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Ch t ng np li cng cho php thc hin m ln hay xung (iu khin bng bit DCEN trong thanh ghi T2MOD). Khi DCEN c t ln 1 v chn T2EX mc cao th timer 2 s m ln; cn nu T2EX mc thp th timer 2 m xung. Khi m ln, tmer trn ti gi tr m 0FFFFh. Khi trn, c TF2 c t ln mc 1 v gi tr trong cp thanh ghi RCAP2H, RCAP2L chuyn vo cp thanh ghi TH2, TL2. Khi m xung, timer trn khi gi tr trong cp thanh ghi TH2, TL2 bng gi tr trong cp thanh ghi RCAP2H, RCAP2L. Khi trn, c TF2 c t ln 1 v gi tr 0FFFFh c np vo cp thanh ghi TH2, TL2. Trong ch ny, khi timer trn, gi tr trong c EXF2 s chuyn mc v khng to ngt (c th dng thm EXF2 to gi tr m 17 bit).
Hnh 3.6 Ch t ng np li 1.5.4. Ch to xung clock
Trong ch ny, timer to ra mt xung clock c chu k bn phn (duty cycle) 50%. Khi timer trn, ni dung ca thanh ghi RCAP2H, RCAP2L c np vo cp thanh ghi TH2, TL2 v timer tip tc m. Tn s xung clock ti chn T2 c xc nh theo cng thc sau:
f= f OSC x 2 X 2 RCAP2H 2 65536 RCAP2L
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X2: bit nm trong thanh ghi CKCON. Trong ch X2: fOSC = fthch anh, ngc li th fOSC = fthch anh/2. timer 2 hot ng ch to xung clock, cn thc hin cc bc sau: t bit T2OE trong thanh ghi T2MOD = 1. Xo bit C/ T 2 trong thanh ghi T2CON = 0 (do ch ny khng cho php m bng dao ng ngoi m ch m bng dao ng ni). Xc nh gi tr ca cp thanh ghi RCAP2H v RCAP2L theo tn s xung clock cn to. Khi ng gi tr cho cp thanh ghi TH2, TL2 (c th khng cn thit tu theo ng dng). t bit TR2 trong thanh ghi T2CON = 1 cho php timer chy.
Hnh 3.7 Ch to xung clock 1.5.5. Ch to tc baud
Khi cc bit TCLK v RCLK trong thanh ghi T2CON c t ln mc 1, timer 2 s dng to tc baud cho cng ni tip. Ch ny cng hot ng nh timer 0 v timer 1 (s kho st c th ti phn 2 cng ni tip).
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1.6.
Cc v d
iu khin hot ng ca timer, cn thc hin: Np gi tr cho thanh ghi TMOD xc nh ch hot ng (thng thng ch dng ch 1 16 bit v ch 2 8 bit t ng np li). Np gi tr m trong cc thanh ghi THx, TLx (thng thng s dng timer 0 v timer 1 nn qu trnh m l m ln). t cc bit TR0, TR1 = 1 (cho php timer hot ng) hay xo cc bit ny v 0 (cm timer). Trong qu trnh timer chy, thc hin kim tra cc bit TF0, TF1 xc nh timer trn hay cha. Sau khi timer trn, nu thc hin kim tra trn bng phn mm (khng dng ngt) th phi thc hin xo TF0 hay TF1 c th tip tc hot ng.
V d 1: Vit chng trnh to sng vung tn s 10 KHz ti chn P1.0 dng timer 0 (tn s thch anh l fOSC = 12MHz). Gii
Do fOSC = 12MHz nn chu k my = 1 s. f = 10 KHz T = 1/f = 0.1 ms = 100 s mt chu k sng vung chim khong thi gian 100 chu k my thi gian tr hon cn thit l 50 chu k my. Tr hon 50 chu k my
T = 100 chu k my Do gi tr m l 50 (ng vi 50 chu k my) nn ch cn dng ch 8 bit (c th m t 1 n 256) cho timer 0 (ch 2). Ni dung thanh ghi TMOD:
GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 0 0 0 0 1 0 Timer 1 khng dng Khng dng m bng dao ng Ch 8 bit INT0 ni TMOD = 0000 0010b (02h)
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Gi tr m l 50 v do timer 0 m ln nn gi tr cn np cho TH0 l -50 (c th khng cn np cho TL0 nhng lc chu k u tin ca xung s sai).
Chng trnh thc hin nh sau:

MOV TMOD,#02h MOV TH0,#(-50) MOV TL0,#(-50) SETB TR0 ; Cho php timer 0 chy JNB TF0,Lap CLR TF0 CPL P1.0 SJMP Lap END ; Nu Timer cha trn th ch ; o bit P1.0 to xung vung
Lap:
V d 2: Vit chng trnh to xung vung tn s f = 1 KHz ti P1.1 dng timer 1(tn s thch anh l fOSC = 12MHz). Gii
Do fOSC = 12MHz nn chu k my = 1 s. f = 1 KHz T = 1/f = 1 ms = 1000 s mt chu k sng vung chim khong thi gian 1000 chu k my thi gian tr hon cn thit l 500 chu k my. Gi tr m l 500 vt qu phm vi ca ch 8 bit nn phi s dng timer 1 ch 16 bit (ch 1). i vi ch 16 bit, do khng c gi tr np li nn mi khi timer trn, cn phi np li gi tr cho thanh ghi TH1 v TL1. Ni dung thanh ghi TMOD:
GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 0 1 0 0 0 0 Khng dng m bng dao ng Ch 16 Timer 0 khng dng bit INT1 ni TMOD = 0001 0000b (10h) Gi tr m l 500 nn gi tr cn np cho cp thanh ghi TH0_TL0 l -500 (dng cc lnh gi HIGH v LOW).
Chng trnh thc hin nh sau:

MOV TMOD,#10h Batdau: MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) SETB TR1 ; Cho php timer 1 chy
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JNB TF1,Lap ; Nu Timer cha trn th ch CLR TF1 CPL P1.1 ; o bit P1.1 to xung vung CLR TR1 SJMP Batdau ; Quay li np gi tr cho TH0_TL0 END V d 3: Vit chng trnh to xung vung tn s f = 10KHz ti P1.0 dng timer 0 v xung vung tn s f = 1 KHz ti P1.1 dng timer 1. Gii
Lap:
Phn tch cho cc thanh ghi ging nh phn v d 1 v 2 nhng lu rng qu trnh kim tra timer trn s khc: thc hin kim tra timer 0, nu cha trn th kim tra timer 1 v kim tra tng t cho timer 1. Chng trnh thc hin nh sau:
MOV TMOD,#12h MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) MOV TH0,#(-50) MOV TL0,#(-50) SETB TR0 SETB TR1 KtrT0: JNB TF0,KtrT1 CLR TF0 CPL P1.0 KtrT1: JNB TF1,KtrT0 CLR TF1 CPL P1.1 MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) SJMP KtrT0 END
Lu rng, xung vung to bng cch nh trn c th khng chnh xc khi 2 timer trn cng lc.
V d 4: Vit chng trnh to xung vung tn s f = 1 Hz ti P1.2 dng timer1. Gii
f = 1 Hz T = 1/f = 1 s = 1 000 000 s mt chu k sng vung chim khong thi gian 500 000 chu k my thi gian tr hon cn thit l 500 000 chu k my.
Gio trnh Vi iu khin
Gi tr m l 500 000, vt qu kh nng ca timer (ti a ch m c 65536 chu k) nn phi thc hin to vng lp m nhiu ln cho n khi t n gi tr 500 000 (c th m mi ln 50 000 v thc hin vng lp 10 ln). Chng trnh thc hin nh sau:
MOV TMOD,#10h Batdau: MOV R7,#10 ; Lp 10 ln Lap: MOV TH1,#HIGH(-50000) MOV TL1,#LOW(-50000) SETB TR1 KtrT1: JNB TF1,KtrT1 CLR TF1 CLR TR0 DJNZ R7,Lap ; Nu R7 0 th lp li CPL P1.2 SJMP Batdau END V d 5: Vit chng trnh con to thi gian tr hon 1s dng timer 0. Gii ; o bit to xung
Do chng trnh yu cu to thi gian tr hon nn s chu k m l 1 000 000. Chng trnh nh sau:
MOV TMOD,#01h ;--- CHNG TRNH CHNH ;--Delay1s: MOV R7,#20 ; Lp 20 ln Lap: MOV TH0,#HIGH(-50000) ; Mi ln tr hon 50 000 s MOV TL0,#LOW(-50000) SETB TR0 Lap1: JNB TF0,Lap1 CLR TF0 CLR TR0 DJNZ R7,Lap ; Lp 20 ln th thot RET
Gio trnh Vi iu khin
Lu rng khi vit chng trnh tr hon nh trn th chng trnh ca AT89C51 xem nh dng li, khng lm g c (c th gii quyt bng cch s dng ngt xem thm phn 3).
2. Cng ni tip (Serial port)

Cng ni tip trong 89C51 c kh nng hot ng ch ng b v bt ng b dng 2 chn TxD (P3.1) v RxD (P3.0). Chc nng ca port ni tip l thc hin chuyn i song song sang ni tip i vi d liu xut, v chuyn i ni tip sang song song i vi d liu nhp. Khi hot ng ch truyn / nhn bt ng b (UART Universal Asynchronous Receiver / Transmitter), cng ni tip c 3 ch song cng (1, 2 v 3). Qu trnh c / ghi cng ni tip dng thanh ghi SBUF (Serial Buffer), thc cht l 2 thanh ghi khc nhau: mt thanh ghi truyn v mt thanh ghi nhn. Cng ni tip c tt c 4 ch khc nhau:
Ch 0: d liu truyn / nhn thng qua chn RxD v xung clock dch bit thng qua TxD vi tc baud bng fthch anh/12. Ch 1: truyn / nhn 10 bit: 1 bit start (lun = 1), 8 bit d liu v 1 bit stop (lun = 0), tc baud c th thay i c v khi nhn, bit stop a vo RB8 ca thanh ghi SCON. Ch 2: truyn / nhn 11 bit: 1 bit start, 8 bit d liu, bit th 9 v 1 bit stop. Khi truyn, bit 9 l bit TB8 v khi nhn, bit 9 l bit RB8 trong thanh ghi SCON. Tc baud c nh l 1/32 hay 1/64 tn s thch anh. Ch 3: ging ch 2 nhng tc baud c th thay i c.
Trong 4 ch trn, thng s dng ch 1 hay 3 truyn d liu. Trong trng hp truyn d liu gia cc vi iu khin AT89C51 vi nhau, c th dng ch 2. Ngoi ra, cng ni tip cn c cc ch nng cao: kim tra li khung v nhn dng a ch t ng.
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2.1.
Cc thanh ghi iu khin hot ng
2.1.1. Thanh ghi SCON (Serial port controller) Bng 3.7 Ni dung thanh ghi SCON
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit K a M t hiu ch SCON.7 FE Framing Error kim tra li khung c t ln 1 khi pht hin li ti bit stop v phi xo bng phn mm. Bit FE ch truy xut c khi bit SMOD0 9Fh = 1 (trong thanh ghi PCON). SM0 SCON.6 SM1 9Eh Serial port Mode bit 0 - Xc nh ch cho cng ni tip Serial port Mode bit 1 SM0 SM1 M t Tc baud 0 0 Thanh ghi dch fOSC/12 0 1 UART 8 bit Thay i 1 0 UART 9 bit fOSC/32 hay fOSC/64 1 1 UART 9 bit Thay i Serial port Mode bit 2 Ch a x l = 0: bnh thng = 1: cho php truyn thng a x l trong ch 2 v 3 Reception Enable bit Cho php thu = 0: cm thu = 1: cho php thu ti cng ni tip Transmitter Bit Bit truyn th 9 trong ch 2 v 3 Receiver Bit Bit nhn th 9 trong ch 2 v 3. Trong ch 1, nu SM2 = 0 th RB8 = stop bit.
SCON.5 SM2
9Dh
SCON.4 REN
9Ch
SCON.3 TB8 SCON.2 RB8 SCON.1 TI
9Bh 9Ah 99h
Transmit Interrupt flag C ngt pht c t bng 1 khi kt thc qu trnh truyn v xo bng phn mm. SCON.0 RI 99h Receive Interrupt flag C ngt thu c t bng 1 khi nhn xong d liu v xo bng phn mm. Gi tr khi reset: 00h, cho php nh a ch bit
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2.1.2. Thanh ghi BDRCON (Baud Rate Control Register) Bng 3.8 Ni dung thanh ghi BDRCON Bit K hiu
- - - BRR TBCK RBCK SPD SRC M t
7 6 5 4
BRR
3 2 1
TBCK RBCK SPD
Baud Rate Run control bit Cho php hot ng = 0: cm b to tc baud ni (internal baud rate generator) hot ng = 1: cho php Transmission Baud rate generator selection bit for UART Chn b to tc baud truyn l b to tc ni (= 1) hay bng timer (= 0) Reception Baud rate generator selection bit for UART Chn b to tc baud nhn l b to tc ni (= 1) hay bng timer (= 0)
Baud Rate Speed control bit for UART Chn tc baud l nhanh (= 1) hay chm (= 0) 0 SRC Baud Rate Source select bit in Mode 0 for UART Chn tc baud trong ch 0 t dao ng thch anh (= 0) hay t b to tc baud ni (= 1) Gi tr khi reset: 00h, khng cho php nh a ch bit Ngoi ra cn c cc thanh ghi SBUF (Serial Buffer), BRL (Baud Rate Reload), SADEN (Slave Address Mark), SADDR (Slave Address). Lu rng cc thanh ghi BDRCON, BRL, SADEN v SADDR ch c trong cc phin bn mi ca MCS-51.
2.2.
-
To tc baud
Ch 0: tc baud c nh = 1/12 tn s thch anh. Ch 2: tc baud = 1/32 tn s thch anh khi SMOD = 1 hay 1/64 khi SMOD = 0 (SMOD: nm trong thanh ghi PCON). Ch 1 v 3: tc baud xc nh bng tc trn ca timer 1. Trong h 89x52, c th dng timer 2 to tc baud cn trong cc phin bn mi, c th dng b to tc ni (INT_BRG Internal Baud Rate Generator). Vic xc nh ngun to tc baud m t nh hnh 3.8 v bng 3.9.
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Hnh 3.8 La chn tc baud Bng 3.9 La chn tc baud TCLK RCLK TBCK RBCK Clock pht 0 0 0 0 Timer 1 1 0 0 0 Timer 2 0 1 0 0 Timer 1 1 1 0 0 Timer 2 X 0 1 0 INT_BRG X 1 1 0 INT_BRG 0 X 0 1 Timer 1 1 X 0 1 Timer 2 X X 1 1 INT_BRG 2.2.1. To tc baud bng Timer 1 Clock thu Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG INT_BRG
Khi dng timer 1 to tc baud, thng thng cn thit lp timer 1 hot ng ch 8 bit t np li v gi tr np ban u ca timer 1 (cha trong thanh ghi TH1) ph thuc vo tc baud cn to theo cng thc sau:
f OSC 2 SMOD Gi tr np = 12 32 baud _ rate
V d: Gi s tn s thch anh l fOSC = 11.0592 MHz, gi tr np khi to tc baud 4800 bps l:
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11.0592 10 6 2 0 Nu SMOD = 0: gi tr np = = 6 TH1 = -6 hay TH1 12 32 4800
= FAh
11.0592 10 6 21 Nu SMOD = 1: gi tr np = = 12 TH1 = -12 hay 12 32 4800 TH1 = F4h
V d: Gi s tn s thch anh l fOSC = 12 MHz, gi tr np khi to tc baud 4800 bps l:

12 10 6 2 0 = 6.51 chn gi tr np l -6 12 32 4800 hay -7. Nu chn gi tr np = -6 th tc baud = 5208 bps cn nu chn -7 th tc baud l 4464 bps.
Nu SMOD = 0: gi tr np =
11.0592 10 6 21 Nu SMOD = 1: gi tr np = = 13.02 chn gi tr np 12 32 4800 l -13 tc baud l 4807 bps. Nh vy, khi dng tn s thch anh l 12 MHz th tc baud s c sai s ch dng khi kt ni nhiu vi iu khin MCS-51 vi nhau cn khi kt ni vi cc thit b khc (nh my tnh chng hn) th nn s dng tn s thch anh 11.0592 MHz.
Cc gi tr np thng dng cho MCS-51 m t nh sau:
Bng 3.10 Cc gi tr np thng dng Tc [bps] fOSC[MHz] SMOD Gi tr np Tc thc [bps] Sai s 1200 11.059 0 -12 1200 0 4800 11.059 0 -6 4800 0 9600 11.059 0 -3 9600 0 1200 11.059 1 -24 1200 0 19200 11.059 1 -3 19200 0 1200 12 0 -26 1201.9 2.17% 2400 12 0 -13 2403.8 0.16% 4800 12 0 -6 5208.3 8.5% 9600 12 0 -3 10416.7 8.5%
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2.2.2. To tc baud bng Timer 2
Hnh 3.9 To tc baud bng timer 2

Timer 2 c dng to tc baud khi t cc bit TCLK, RCLK ln 1 (trong thanh ghi T2CON). Cng thc lin quan gia tc baud v gi tr np nh sau (lu rng gi tr np cha trong cp thanh ghi RCAP2H_RCAP2L): Gi tr np =
f OSC 2 16 baud _ rate
Khi dng Timer 2 to tc baud, xung clock thu v pht c th tch ring bng cch ch dng TCLK hay RCLK. Lc , xung clock cn li c xc nh theo Timer 1. Ngoi ra, cng c th to ngt cho Timer 2 bng cch t bit EXEN2 = 1 v ngt to ra khi xut hin cnh m ti chn T2EX.
V d: Gi s tn s thch anh l fOSC = 11.0592 MHz, gi tr np khi to tc baud 4800 bps l:

11.0592 10 6 = 72 FFB8h Gi tr np = 2 16 4800
RCAP2H = FFh, RCAP2L = B8h
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2.2.3. B to tc baud ni (INT_BRG Internal Baud Rate Generator)
Hnh 3.10 B to tc baud ni

Gi tr np trong b to tc ni cha trong thanh ghi BRL v c xc nh theo cng thc sau: Gi tr np =
f OSC 2 SMOD1 2 32 61SPD baud _ rate
Trong SMOD1 nm trong thanh ghi PCON v SPD nm trong thanh ghi BDRCON.
2.3.
Truyn thng a x l
Ch 2 v 3 ca MCS-51 cho php thc hin kt ni nhiu vi iu khin ch master slave. M hnh thc hin ca qu trnh truyn thng m t nh hnh v sau: Master
RxD TxD RxD
Slave 1
TxD RxD
Slave 2
TxD
RxD
TxD
RxD
TxD
RxD
TxD
Slave 3
Slave 4
Slave 5
Hnh 3.11 Truyn thng a x l

Qu trnh truyn d liu m t nh sau: Khi khi ng, cc vi iu khin slave c bit SM2 = 1 (trong thanh ghi SCON) v hot ng ch UART 9 bit. Nh vy, slave ch nhn c d liu khi bit truyn th 9 (TB8 ca master) l 1.
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Mi slave c gn trc mt a ch. Khi cn trao i thng tin vi slave no, master s gi d liu 9 bit gm 8 bit a ch ca slave v bit 9 = 1. D liu ny s c tt c cc slave nhn v (do bit 9 = 1). Chng trnh trong slave s kim tra gi tr a ch tng ng, nu trng vi a ch ci t sn th o bit SM2 (= 0), nu khc th b qua. Tip tc, master s gi d liu n slave nhng lc ny bit 9 = 0. Khi , ch c slave no c bit SM2 = 0 mi nhn c d liu. Sau khi truyn xong d liu, master gi li 8 bit a ch v bit 9 = 1. Slave nhn c s o bit SM2 ln na khi phc trng thi ban u.
Nh vy, trong qu trnh truyn thng a x l, c 2 loi thng tin gi: byte a ch nu bit 9 = 1 v byte d liu nu bit 9 = 0.
2.4.
Nhn dng a ch t ng
Trong cc phin bn mi ca MCS-51, a ch ca cc slave c th nhn dng bng cc thanh ghi SADDR v thanh ghi mt n SADEN (cc bit khng quan tm trong thanh ghi a ch SADDR s tng ng vi cc bit 0 trong thanh ghi SADEN). Xt h thng c 1 master v 3 slave: Slave 1: SADDR = 1111 0001b, SADEN = 1111 1010b 1111 0001b 1111 1010b 1111 0x0xb Slave 2: SADDR = 1111 0011b, SADEN = 1111 1001b 1111 0011b 1111 1001b 1111 0xx1b Slave 3: SADDR = 1111 0001b, SADEN = 1111 1010b 1111 1011b 1111 0101b 1111 x0x1b
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Nu ch cn gi d liu cho slave 1, a ch cn s dng c bit 0 = 0 (do a ch ca slave 2 v slave 3 c bit 0 = 1 cn a ch ca slave 1 c bit 0 tu ), gi s l 1111 0000b. Nu cn gi cho slave 2 v slave 3 m khng gi cho slave 1 th a ch cn dng c bit 1 = 1 (do a ch ca slave 1 c bit 1 = 0 cn slave 2 v 3 th tu ), gi s nh 1111 0011b.
a ch broadcast
a ch broadcast to thnh t php ton OR gia cc thanh ghi SADDR v SADEN trong cc bit 0 xc nh l cc bit khng quan tm. Gi s SADDR = 0101 0000b v SADEN = 1111 1101b th 0101 0000b OR 1111 1101b 1111 1101b a ch broadcast l 1111 11x1b.
2.5.
Kim tra li khung
Ch kim tra li khung ch c trong cc ch 1, 2 v 3 c thc hin bng cch t bit SMOD0 ln 1 (trong thanh ghi PCON). Khi SMOD0 = 1, b thu s kim tra bit stop mi khi c d liu n. Nu bit stop khng hp l, bit FE s c t ln 1 (trong thanh ghi SCON). Phn mm sau khi c byte d liu s kim tra bit FE xc nh c li ng truyn hay khng. Lu rng bit FE ch xo bng phn mm hay khi reset h thng m khng b xo khi nhn bit stop hp l.
2.6.
-
Cc v d
iu khin hot ng ca cng ni tip, cn thc hin cc bc sau: Khi ng gi tr ca thanh ghi SCON xc nh ch hot ng. Chn b to tc baud (mc nh l timer 1) v xc nh cc thng s cn thit theo tc baud yu cu. Kim tra cc bit TI v RI xc nh cho php truyn hay nhn d liu khng. Nu cn truyn d liu th kim tra TI v chuyn ni dung truyn vo thanh ghi SBUF.
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Nu cn nhn d liu th kim tra RI v c ni dung t SBUF vo thanh ghi A.
V d 1: Khi ng cng ni tip ch UART 8 bit vi tc baud 9600 bps, dng timer 1 l b to tc baud (gi s tn s thch anh l 11.0592 MHz). Gii
Ni dung thanh ghi SCON: REN 1 Cho php thu TB8 RB8 0 0 TI 1 Cho php truyn RI 0
SM0 SM1 SM2 0 1 0 UART 8 Khng ch a x bit l SCON = 0101 0010b (52h) Ni dung thanh ghi TMOD:
GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 1 0 0 0 0 0 Khng dng m bng dao ng Ch 8 Timer 0 khng dng INT1 ni bit TMOD = 0010 0000b (20h) Gi tr m (theo bng 3.10): TH1 = -3
on chng trnh khi ng nh sau:
MOV SCON,#52h MOV TMOD, #20h MOV TH1,#-3 SETB TR1 V d 2: Vit chng trnh xut lin tc cc k t t A n Z ra cng ni tip vi tc baud 4800 bps (gi s tn s thch anh l 11.0592 MHz). Gii
Tc = 4800 bps gi tr m: TH1 = -6 Chng trnh thc hin nh sau:
MOV SCON,#52h MOV TMOD,#20h MOV TH1,#-6 SETB TR1 Batdau: MOV A,#A
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Truyen: JNB TI,$ ; Nu cha cho php truyn th ch CLR TI ; Xo TI khng cho php truyn, sau khi ; truyn xong th mi c th truyn tip MOV SBUF,A ; Truyn d liu INC A ; Qua k t k CJNE A,#Z+1,Truyen; Nu truyn xong t A SJMP Batdau ; n Z th lp li qu trnh V d 3: Vit chng trnh nhn k t t cng ni tip vi tc baud 19200bps (gi s tn s thch anh l 11.0592 MHz). Gii
Tc = 1900 bps gi tr m: TH1 = -3 v SMOD = 1 Chng trnh thc hin nh sau:
MOV SCON,#52h MOV TMOD,#20h MOV A,PCON ; Gn bit SMOD = 1 (do PCON khng cho SETB ACC.7 ; php nh a ch bit nn phi thc MOV PCON,A ; hin thng qua thanh ghi A) MOV TH1,#-3 SETB TR1 Nhan: JNB RI,$ ; Nu cha c k t n th ch CLR RI ; Xo RI khng cho php nhn, sau khi ; c k t tip theo th mi nhn MOV A,SBUF ; Nhn d liu SJMP Nhan
Lu rng, i vi cc v d trn, khi truyn hay nhn d liu th MCS-51 phi ch, khng c thc hin cng vic khc. Vn ny c th gii quyt bng cch s dng ngt (xem thm phn 3).
3. Ngt (Interrupt)
Ngt l qu trnh dng chng trnh ang thc thi phc v cho mt chng trnh khc khi xy ra mt s kin. Chng trnh x l s kin ngt gi l chng trnh phc v ngt (ISR Interrupt Service Routine).
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H MCS-51 c tng cng 5 ngun ngt khc nhau (khng k reset cng c th xem nh l mt ngt): ngt ngoi 0, 1 (ti cc chn INT0 , INT1 ), timer 0, 1 (khi timer tng ng trn), cng ni tip (khi c k t n hay khi truyn k t i). i vi h 89x52 s c thm ngt timer 2.
3.1.
Cc thanh ghi iu khin hot ng
3.1.1. Thanh ghi IE (Interrupt Enable) Bng 3.11 Ni dung thanh ghi IE
EA - ET2 ES ET1 EX1 ET0 EX0 Bit K hiu a ch M t IE.7 EA AFh Enable All Cm tt c (= 0) hay cho php ngt IE.6 IE.5 ET2 ADh Enable Timer 2 Cho php ngt ti timer 2 (= 1) IE.4 ES ACh Enable serial port Cho php ngt ti cng ni tip (= 1) IE.3 ET1 ABh Enable Timer 1 Cho php ngt ti timer 1 (= 1) IE.2 EX1 AAh Enable External interrupt 1 Cho php ngt ti ngt ngoi 1 (= 1) IE.1 ET0 A9h Enable Timer 0 Cho php ngt ti timer 0 (= 1) IE.0 EX0 A8h Enable External interrupt 0 Cho php ngt ti ngt ngoi 0 (= 1) Gi tr khi reset: 00h, cho php nh a ch bit Thanh ghi IE cho php mt ngt c xy ra hay cm ngt ( cho php cn dng 2 bit: bit EA = 1 v bit cho php tng ng tng ngt).
3.1.2. Thanh ghi IP (Interrupt Priority) Bng 3.12 Ni dung thanh ghi IP Bit IP.7 IP.6 IP.5 IP.4
- - PT2 PS PT1 PX1 PT0 PX0 K hiu a ch M t PT2 BDh Chn mc u tin cao (= 1) hay thp (= 0) ti timer 2 PS BCh Chn mc u tin cao (= 1) hay thp (= 0) ti cng ni tip
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IP.3 PT1 BBh Chn mc u tin cao (= 1) hay thp (= 0) ti timer 1 IP.2 PX1 BAh Chn mc u tin cao (= 1) hay thp (= 0) ti ngt ngoi 1 IP.1 PT0 B9h Chn mc u tin cao (= 1) hay thp (= 0) ti timer 0 IP.0 PX0 B8h Chn mc u tin cao (= 1) hay thp (= 0) ti ngt ngoi 0 Gi tr khi reset: 00h, cho php nh a ch bit Thanh ghi IP cho php chn mc u tin cho cc ngt. H MCS-51 c 2 mc u tin: mc cao v mc thp. Qu trnh x l u tin ngt m t nh sau: Nu 2 ngt xy ra ng thi th ngt no c mc u tin cao hn s c phc v trc. Nu 2 ngt xy ra ng thi c cng mc u tin th th t u tin thc hin t cao n thp nh sau: ngt ngoi 0 timer 0 ngt ngoi 1 timer 1 cng ni tip timer 2. Nu ISR ca mt ngt c mc u tin thp ang chy m c ngt khc xy ra vi mc u tin cao th ISR ny s tm dng chy ISR c mc u tin cao (cng c ngha l khng th dng ISR c mc u tin cao).
3.1.3. Thanh ghi TCON (Timer/Counter Control) Bng 3.13 Ni dung thanh ghi TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit
TCON.7 TCON.6 TCON.5 TCON.4 TCON.3
K hiu TF1 TR1 TF0 TR0 IE1
a ch 8Fh 8Eh 8Dh 8Ch 8Bh
M t
Xem phn timer C ngt ngoi 1 t bng 1 khi pht hin tc ng ngt ti INT1 Xo bng phn mm hay bng phn cng khi chuyn iu khin n ISR Interrupt 1 Type control bit = 0: ngt ngoi 1 c tc ng bng mc logic 0 = 1: ngt ngoi 1 c tc ng bng cnh m Dng cho ngt ngoi 0
TCON.2 IT1
8Ah
TCON.1 IE0 TCON.0 IT0
89h 88h
Gi tr khi reset: TCON = 00h

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3.2.
X l ngt
kim tra khi no ngt xy ra, cc c ngt c ly mu thi gian S5P2 ca mi chu k my. Cc iu kin ngt c hi vng cho n chu k my k tip xc nh xem c ngt xy ra hay khng. Khi c iu kin ngt, h thng ngt s to ra lnh LCALL gi ISR tng ng nhng lnh ny s khng c thc hin khi tn ti mt trong cc iu kin sau: C mt ngt c mc u tin bng hay cao hn ang c phc v. Chu k hi vng hin ti khng phi l chu k cui ca mt lnh. ang thc thi lnh RETI hay bt k lnh no c nh hng n thanh ghi IE v IP.
Khi c ngt xy ra, cc thao tc thc hin ln lt l: Hon tt lnh hin hnh. Ct ni dung ca thanh ghi PC vo stack. Lu trng thi ca ngt hin hnh. a vo thanh ghi PC a ch ca ISR tng ng.
Sau khi thc hin xong ISR (kt thc bng lnh RETI), thc hin qu trnh: khi phc trng thi ban u ca ngt v ly a ch t stack a vo PC.
Bng vector ngt

Khi xy ra ngt, thanh ghi PC s c np gi tr tng ng vi cc ngt. Cc gi tr ny c gi l vector ngt, m t nh sau:
Bng 3.14 Bng vector ngt Nguyn nhn ngt Reset Ngt ngoi 0 Timer 0 Ngt ngoi 1 Timer 1 Cng ni tip Timer 2
a ch 0000h 0003h 000Bh 0013h 001Bh 0023h 002Bh
Trong cc nguyn nhn ny, reset c th c xem nh mt ngt c vector ngt l 0000h nhng cch x l khi reset khng ging nh ngt: khi ng tt c cc thanh ghi v gi tr mc nh v khng lu ni dung ca PC vo stack.
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Theo bng vector ngt, ISR ca ngt ngoi 0 nm t a ch 0003h n 000Ah (chim tng cng 8 byte) nn khi s dng ISR c kch thc thp hn 9 byte th c th dng trc tip ti a ch 0003h (xem thm phn sau). Tuy nhin, nu kch thc ISR ln hn th phi dng cc lnh nhy ti cc vector ngt. Khi chng trnh s c cu trc nh sau (tn ca cc ISR c th thay i):
ORG 0000h LJMP main ORG 0003h LJMP Int0_ISR ORG 000Bh LJMP Timer0_ISR ORG 0013h LJMP Int1_ISR ORG 001Bh LJMP Timer1_ISR ORG 0023h LJMP Serial_ISR Main: Int0_ISR: RETI Timer0_ISR: RETI Int1_ISR: RETI Timer1_ISR: RETI Serial_ISR: RETI END
Lu rng nu khng s dng ngt no th khng cn phi khai bo ISR cho ngt .
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3.3.
Ngt do b nh thi
MCS-51 c 2 ngun ngt t timer: timer 0 v timer 1 (i vi h 89x52 cn c thm timer 2). Khi timer hot ng ch ngt, chng trnh vn hot ng bnh thng cho n khi timer trn th mi chuyn n v tr ca ISR (trong khi , khi timer hot ng khng s dng ngt th chng trnh s dng li xem thm phn v d trong hot ng nh thi). Cc ngun ngt ny cho php hay cm bng cc bit trong thanh ghi IE: EA, ET0, ET1 v chn ch u tin bng cc bit trong thanh ghi IP: PT0, PT1. Khi timer trn, c TFx s chuyn ln mc 1. H thng ngt khi pht hin c TFx ln 1 s chuyn n ISR tng ng v t ng xo c TFx. Qu trnh iu khin hot ng bng b nh thi c s dng ngt thc hin nh sau: Xc nh ch hot ng ca b nh thi. Np gi tr cho cc thanh ghi THx, TLx. Cho php ngt ti cc b nh thi tng ng (thanh ghi IE). Xc nh mc u tin (thanh ghi IP). Cho php timer chy bng cc bit TRx. Vit ISR cho timer tng ng.
V d 1: Vit chng trnh to sng vung tn s f = 5 KHz ti P1.0 dng ngt timer 1 (gi s tn s thch anh l 12 MHz). Gii
f = 5 KHz T = 200 s (200 chu k) thi gian tr hon: 100 chu k Gi tr m = 100 dng ch 8 bit TMOD = 0010 0000b (20h) Ni dung thanh ghi IE:
EA - ET2 ES ET1 EX1 ET0 EX0 1 0 0 0 1 0 0 0 IE = 1000 1000b (88h) Chng trnh thc hin nh sau:
ORG 0000h
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LJMP main ORG 001Bh CPL P1.0 ; o bit RETI ; tr v chng trnh chnh t ISR Main: MOV TMOD,#20h MOV IE,#88h ; C th thay th bng 2 lnh sau: ; SETB EA ; SETB ET1 MOV TH1,#(-100) MOV TL1,#(-100) SETB TR1 SJMP $ ; Lp ti ch, ngha l chng trnh ; khng lm g c, ch timer trn (cc ; ng dng thc t c th x l cc ; cng vic khc) END
Lu rng lnh CPL P1.0 chim 2 byte, lnh RETI chim 1 byte, tng cng ISR cho timer 1 l 3 byte khng vt qu 8 byte nn c th t trc tip ti a ch 001Bh.
V d 2: Vit chng trnh to xung vung tn s f = 10KHz ti P1.0 dng ngt timer 0 v xung vung tn s f = 1 KHz ti P1.1 dng ngt timer 1. Gii
Gi tr m cho timer 0: 50. Gi tr m cho timer 1: 500. timer 0: 8 bit, timer 1: 16 bit TMOD = 0001 0010b (12h) Ni dung thanh ghi IE:
EA - ET2 ES ET1 EX1 ET0 EX0 1 0 0 0 1 0 1 0 IE = 1000 1010b (8Ah) Chng trnh thc hin nh sau:
ORG 0000h LJMP main
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ORG 000Bh CPL P1.0 RETI ORG 001Bh MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) CPL P1.1 RETI Main: MOV TMOD,#12h MOV IE,#8Ah SETB TR0 SETB TR1 MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) MOV TH0,#(-50) MOV TL0,#(-50) SJMP $ END
; ; ; ;
2 2 2 1
byte byte byte byte
Trong v d ny, do timer 1 hot ng ch 16 bit nn mi ln timer trn phi thc hin np li gi tr cho timer 1.
V d 3: Vit chng trnh dng ngt timer 0 sao cho c 1s th tng ni dung ca cc nh 30h, 31h, 32h theo quy lut ng h (30h cha gi, 31h cha pht, 32h cha giy). Gii
Yu cu chng trnh tr hon l 1s trong khi timer 0 cho php tr hon ti a l 65536 s chn gi tr m l 50000 v thc hin lp li 20 ln (20 x 50000 = 1000000 s = 1s). TMOD = 0000 0001b (01h) IE = 1000 0010b (82h) Chng trnh thc hin nh sau:
Hour EQU 30h Minute EQU 31h Second EQU 32h ORG 0000h LJMP main
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; nh ngha trc cc nh
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ORG 0003h LJMP Timer0_ISR Main: MOV TMOD,#01h MOV IE,#82h MOV TH0,#HIGH(-50000) MOV TL0,#LOW(-50000) MOV R7,#20 SETB TR0 SJMP $ Timer0_ISR: MOV TH0,#HIGH(-50000) MOV TL0,#LOW(-50000) DJNZ R7,exitTimer0 CALL Inc_clock MOV R7,#20 exitTimer0: RETI Inc_clock: INC Second MOV A,Second CJNE A,#60,exitInc MOV Second,#0 INC Minute MOV A,Minute CJNE A,#60,exitInc MOV Minute,#0 INC Hour MOV A,Hour CJNE A,#24,exitInc MOV Hour,#0 exitInc: RET END
; Lp 20 ln
; Nu cha 20 ln th thot ; Tng theo quy lut ng h
; Tng giy ; Nu giy < 60 th thot ; Ngc li th gn giy = 0 ; v tng pht ; Nu pht < 60 thi thot ; Ngc li th gn pht = 0 ; v tng gi ; Nu gi < 24 th thot ; Ngc li th gn gi = 0
3.4.
Ngt do cng ni tip
MCS-51 c 2 ngun ngt do cng ni tip: ngt pht v ngt thu. Hai ngun ngt ny xc nh bng cc bit RI, TI v dng chung mt a ch ISR nn khi chuyn n ISR, cc c ngt khng t ng xo bng phn cng m phi thc hin bng phn mm: kim tra nguyn nhn ngt (RI hay TI) v xo bit c tng ng.
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V d: Vit chng trnh khi ng cng ni tip ch UART 8 bit vi tc truyn 4800 bps. Vit ISR cho cng ni tip theo yu cu: truyn tun t cc k t t A n Z ra cng ni tip ng thi mi ln c k t n cng ni tip th nhn v v xut k t nhn ra P0 (gi s tn s thch anh l 11.0592 MHz). Gii
Ni dung thanh ghi SCON: REN 1 Cho php thu TB8 RB8 0 0 TI 0 Khng cho php truyn RI 0
SM0 SM1 SM2 0 1 0 UART 8 Khng ch a bit x l SCON = 50h -
Ni dung thanh ghi TMOD:
GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 1 0 0 0 0 0 Khng dng m bng dao ng Ch 8 Timer 0 khng dng INT1 ni bit TMOD = 0010 0000b (20h) Gi tr m (theo bng 3.10): TH1 = -6 Ni dung thanh ghi IE:
EA - ET2 ES ET1 EX1 ET0 EX0 1 0 0 1 0 0 0 0 IE = 1001 0000b (90h) Chng trnh thc hin nh sau:
ORG 0000h LJMP main ORG 0023h ; a ch ISR ca cng ni tip LJMP Serial_ISR Main: MOV TMOD,#20h MOV TH1,#(-6) MOV TL1,#(-6) ; Tc 4800 bps SETB TR1 MOV R7,#A ; K t truyn u tin MOV IE,#90h ; Cho php ngt ti cng ni tip SETB TI ;Cho php truyn SJMP $
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Serial_ISR: JNB RI,Transmit
; Nu khng phi ngt do nhn ; k t th truyn
CLR RI MOV A,SBUF ; Nhn k t MOV P0,A ; Xut ra Port 0 SJMP exitSerial Transmit: ; Truyn k t CLR TI MOV A,R7 MOV SBUF,A ; Truyn k t INC R7 ; Qua k t k CJNE R7,#Z+1,exitSerial ; Nu cha truynZ th ; tip tc truyn, ngc li th MOV R7,#A ; bt u truyn t k t A exitSerial: RETI END
3.5.
Ngt ngoi
MCS-51 c 2 ngun ngt ngoi khc nhau: ngt ngoi 0 v ngt ngoi 1. Ngt ngoi xy ra khi bit IEx chuyn ln mc 1, qu trnh chuyn mc ca bit IEx xy ra khi: Bit ITx = 0 v xut hin mc logic 0 ti chn INTx tng ng (P3.2 cho ngt ngoi 0 hay P3.3 cho ngt ngoi 1). Bit ITx = 1 v xut hin cnh m ti chn INTx.
Khi c ngt xy ra v cho php ngt (dng thanh ghi IE), chng trnh s c chuyn n a ch ca ISR tng ng (0003h cho ngt ngoi 0 v 0013h cho ngt ngoi 1) v xo c ngt TFx. Lu rng cc c ngt c ly mu trong mi chu k nn pht hin ngt, yu cu phi: mc thp ti thiu 1 chu k nu tc ng bng mc logic (ITx = 0). mc cao ti thiu 1 chu k trc khi chuyn xung mc thp v mc thp cng phi tn ti ti thiu 1 chu k (ITx = 1).
Qu trnh iu khin ngt ngoi m t nh sau: Xc nh yu cu ngt bng cnh m hay bng mc logic.
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Cho php ngt ti ngt ngoi tng ng (dng thanh ghi IE). Xc nh mc u tin (thanh ghi IP). Vit ISR cho cc ngt.
V d: Vit chng trnh sao cho mi khi c mc logic 0 xut hin ti P3.2 (ngt ngoi 0) th to xung 1 KHz ti P1.0. Qu trnh to xung ch dng khi c mc logic 0 xut hin ti P3.3 (ngt ngoi 1). Gii
Chng trnh thc hin c 3 ngt xy ra: ngt ngoi 0 cho php timer chy to xung ti P1.0, ngt ngoi 1 cm timer ngng qu trnh to xung v ngt timrer to xung. f = 1 KHz T = 1ms (1000 chu k): gi tr m l 500 (ch 16 bit) - Ni dung thanh ghi TMOD: GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 0 1 0 0 0 0 Khng dng m bng dao ng Ch 16 Timer 0 khng dng INT1 ni bit TMOD = 0001 0000b (10h) Ni dung thanh ghi IE:
EA - ET2 ES ET1 EX1 ET0 EX0 1 0 0 0 1 1 0 1 IE = 1000 1101b (8Dh) Chng trnh thc hin nh sau:
ORG 0000h LJMP main ORG 0003h SETB TR1 RETI ORG 0013h CLR TR1 RETI ; a ch ISR ngt ngoi 0 ; Timer 1 chy ; a ch ISR ca ngt ngoi 1 ; Cm timer 1
ORG 001Bh ; a ch ISR timer 1 MOV TH1,#HIGH(-500); Ch 16 bit nn mi ln trn MOV TL1,#LOW(-500); phi np li gi tr CPL P1.0 ; o bit P1.0 to xung RETI
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Main: MOV TMOD,#10h MOV TH1,#HIGH(-500) MOV TL1,#LOW(-500) MOV IE,#8Dh ; Cho php ngt ti ngt ngoi 0, 1 v SJMP $ ; timer 1 END
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BI TP CHNG 3
1. Vit on chng trnh theo yu cu: Khi ng cng ni tip ch UART 8 bit vi tc truyn 4800 bps. nh thi 1s th c d liu t P1, lu vo nh 30h v xut d liu va c ra cng ni tip.
2. Vit on chng trnh theo yu cu: Khi ng cng ni tip ch UART 9 bit vi tc truyn 9600 bps. Khi c ngt xy ra ti ngt ngoi 0 th xut d liu ti nh 30h ra cng ni tip trong bit truyn th 9 l bit parity. Khi c ngt ti ngt ngoi 1 th c d liu t P0 v lu kt qu vo nh 30h.
3. Vit on chng trnh theo yu cu: Khi c ngt ti ngt ngoi 0 (tc ng bng cnh) th c d liu ti P2 v lu vo nh 30h ng thi tng gi tr trong nh ln 1. Dng ngt timer 0 nh thi 30s th c gi tr trong nh 30h, xo ni dung trong nh 31h v kim tra gi tr theo yu cu:
Gi tr Thc hin > 200 t bit P1.0 = 1, xo bit P1.1 = 0 v P1.2 = 0 To xung f = 1KHz ti P1.3 dng ngt timer 1 < 100 t bit P1.1 = 1, xo bit P1.0 = 0 v P1.2 = 0 Ngng to xung ti P1.3 Khc t bit P1.2 = 1, xo bit P1.0 = 0 v P1.1 = 0
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Cc ng dng da trn vi iu khin MCS-51
Chng 4: CC
NG DNG DA TRN VI IU KHIN MCS-51
Chng ny gii thiu v mt s ng dng ca MCS-51 trong thc t: iu khin Led n, Led 7 on, ma trn Led, LCD, ng c bc, giao tip 8255.
1. iu khin Led n
VCC
D1 IN LED
R1
IN
D1
R1
RESISTOR
LED
RESISTOR
Hnh a
Hnh b
Hnh 4.1 S kt ni Led n Mch iu khin led n m t nh hnh 4.1. Lu rng cc port ca AT89C51 c dng ti a l 10 mA (xem thm chng 1, phn c tnh DC) nn khi cn iu khin nhiu Led cn mc thm mch khuch i.
VCC D2 R1
IN
2 D1 74LS04 R2
VCC D4 R3
D3
R4
IN
Q1
Hnh 4.2 S kt ni dng mch khuch i
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VCC
Phm Hng Kim Khnh

U2 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9
1 R5 D5 LED D6 LED D7 LED D8 LED D9 LED D10 LED D11 LED D12 LED 9 8 7 6 5 4 3 2
RN1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
Hnh 4.3 Kt ni Led n vi AT89C51
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V d: Xt s kt ni Led nh hnh 4.3. Vit chng trnh iu khin Led sng tun t t tri sang phi, mi ln 1 Led. Gii Cc Led ni vi Port 0 ca AT89C51 (P0 khi dng nh cc cng nhp / xut th cn phi c in tr ko ln ngun) nn mun Led sang th phi gi d liu ra P0. Theo s mch, Led sang khi cc bit tng ng ti P0 l 0. Yu cu iu khin Led sang t tri sang phi (theo th t ln lt t P0.0 n P0.7) nn d liu gi ra l: Ln 1: 1111 1110b (0FEh) sng 1 Led tri Ln 2: 1111 1101b (0FDh) Ln 3: 1111 1011b (0FBh) Ln 4: 1111 0111b (0F7h) Ln 5: 1110 1111b (0EFh) Ln 6: 1101 1111b (0DFh) Ln 7: 1011 1111b (0BFh) Ln 8: 0111 1111b (7Fh) Ln 9: quay li ging nh ln 1
Chng trnh thc hin nh sau: MOV DPTR,#MaLed ; DPTR cha v tr bng m Led Main: MOV R7,#0 ; Phn t u tin ca bng m Loop: MOV A,R7 MOVC A,@A+DPTR ; c bng m MOV P0,A ; Chuyn vo P0 sng Led CALL Delay ; Ch mt ngi c th thy INC R7 ; Chuyn qua trng thi k CJNE R7,#8,Loop ; ht bng m th lp li SJMP main MaLed: DB 0FEh,0FDh,0FBh,0F7h,0EFh,0DFh,0BFh,7Fh Delay: MOV TMOD,#01h MOV TH0,#HIGH(-50000) ; Ch 50 ms MOV TL0,#LOW(-50000) SETB TR0 JNB TF0,$ CLR TF0
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CLR TR0 RET END
2. iu khin Led 7 on
2.1.
-
Cu trc v bng m hin th d liu trn Led 7 on

a f g e d c dp b
Dng Led:
Hnh 4.4 Hnh dng ca Led 7 on Led Anode chung:

COM
D1 a D2 b D3 c D4 d D5 e D6 f D7 g D8 dp
dp
Hnh 4.5 Led 7 on dng anode chung i vi dng Led anode chung, chn COM phi c mc logic 1 v mun sng Led th tng ng cc chn a f, dp s mc logic 0. Bng 4.1 - Bng m cho Led Anode chung (a l MSB, dp l LSB): S 0 1 2 3 4 5 6 a 0 1 0 0 1 0 0 b 0 0 0 0 0 1 1 c 0 0 1 0 0 0 0 d 0 1 0 0 1 0 0 e 0 1 0 1 1 1 0 f 0 1 1 1 0 0 0 g dp M hex 1 1 03h 1 1 9Fh 0 1 25h 0 1 0Dh 0 1 99h 0 1 49h 0 1 41h
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7 8 9
0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 1 1
1Fh 01h 09h
Bng 4.2 - Bng m cho Led Anode chung (a l LSB, dp l MSB): S dp g f e d c b a M hex 0 1 1 0 0 0 0 0 0 0C0h 1 1 1 1 1 1 0 0 1 0F9h 2 1 0 1 0 0 1 0 0 0A4h 3 1 0 1 1 0 0 0 0 0B0h 4 1 0 0 1 1 0 0 1 99h 5 1 0 0 1 0 0 1 0 92h 6 1 0 0 0 0 0 1 0 82h 7 1 1 1 1 1 0 0 0 0F8h 8 1 0 0 0 0 0 0 0 80h 9 1 0 0 1 0 0 0 0 90h Led Cathode chung
a
D1 a
b
D2 b
c
D3 c
d
D4 d
e
D5 e
g
D6 f
f
D7 g
dp
D8 dp
COM
Hnh 4.6 Led 7 on dng cathode chung i vi dng Led Cathode chung, chn COM phi c mc logic 0 v mun sng Led th tng ng cc chn a f, dp s mc logic 1. Bng 4.3 - Bng m cho Led Cathode chung (a l MSB, dp l LSB): S 0 1 2 3 4 5 6 7
Phm Hng Kim Khnh
a 1 0 1 1 0 1 1 1
b 1 1 1 1 1 0 0 1
c 1 1 0 1 1 1 1 1
d 1 0 1 1 0 1 1 0
e 1 0 1 0 0 0 1 0
f 1 0 0 0 1 1 1 0
g dp M hex 0 0 0FCh 0 0 60h 1 0 0DAh 1 0 0F2h 1 0 66h 1 0 0B6h 1 0 0BEh 0 0 0E0h

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8 9
1 1 1 1 1 1 1 1 1 1 1 0 1 1
0 0
0FEh 0F6h
Bng 4.4 - Bng m cho Led Anode chung (a l LSB, dp l MSB): S dp g f e d c b a M hex 0 0 0 1 1 1 1 1 1 3Fh 1 0 0 0 0 0 1 1 0 06h 2 0 1 0 1 1 0 1 1 5Bh 3 0 1 0 0 1 1 1 1 4Fh 4 0 1 1 0 0 1 1 0 66h 5 0 1 1 0 1 1 0 1 6Dh 6 0 1 1 1 1 1 0 1 7Dh 7 0 0 0 0 0 1 1 1 07h 8 0 1 1 1 1 1 1 1 7Fh 9 0 1 1 0 1 1 1 1 6Fh
2.2.
Cc phng php hin th d liu
2.2.1. Phng php qut Khi kt ni chung cc ng d liu ca Led 7 on, cc Led khng th sng ng thi (do nh hng ln nhau gia cc Led) m phi thc hin qut Led, ngha l ti mi thi im ch sng mt Led v tt cc Led cn li. Do hin tng lu nh ca mt, ta s thy cc Led sng ng thi. V d 1: Xt s kt ni nh hnh 4.7. Vit chng trnh hin th s 0 ra Led1 v s 1 ra Led2. Gii Led c chn COM ni vi Vcc (thng qua Q2, Q3) nn Led l loi anode chung v Q2, Q3 l transistor PNP nn Led sng th d liu tng ng ti cc chn iu khin (P1.0, P1.1) phi l 1. Theo s kt ni, chn g ca Led ni vi P0.6, chn a ni vi P0.0 nn bng m Led l bng 4.2, d liu cho s 0 v 1 ln lt l 0C0h v 0F9h. Phng php s dng l phng php qut nn cn phi c thi gian tr hon gia 2 ln qut, thi gian ny c thc hin thng qua timer (thi gian tr hon khong 200 s).
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Chng trnh thc hin nh sau: MOV P1,#0 ; Xo P1 tt Led Main: MOV P0,#0C0h ; M s 0 SETB P1.0 ; Sng Led1 CALL Delay ; Thi gian tr hon thy Led sng CLR P1.0 ; Tt Led1 MOV P0,#0F9h ; M s 1 SETB P1.1 ; Sng Led2 CALL Delay CLR P1.1 ; Tt Led2 SJMP main ;-------------------Delay: MOV TMOD,#01h MOV TH0,#(-200) MOV TL0,#(-200) SETB TR0 JNB TF0,$ CLR TF0 CLR TR0 RET END V d 2: Vit li chng trnh trn nhng s dng ngt ca timer. Gii i vi chng trnh trong v d 1, khi ang thc hin qut led th chng trnh khng lm g c trong khi , cc ng dng thc t thng x l cc cng vic khc ng thi vi qu trnh qut. Vn ny c th gii quyt bng cch s dng ngt ca timer: mi khi timer trn th thc hin hin th trn 1 Led. Chng trnh thc hin nh sau: Led1 EQU 30h Led2 EQU 31h Led_Pos EQU 32h ORG 0000h LJMP main ORG 000Bh LJMP Timer0_ISR ; a ch cha d liu ca Led1 ; a ch cha d liu ca Led2 ; V tr Led hin hnh
; a ch ISR ca timer 0
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Main: SETB EA ; Cho php ngt ti timer 0 SETB ET0 MOV Led1,#0C0h ; S 0 MOV Led2,#0F9h ; S 1 MOV Led_Pos,#01h ; V tr sng u tin l Led1 MOV R0,#Led1 ; D liu gi ra u tin l Led1 MOV TMOD,#01h MOV TH0,#(-200) MOV TL0,#(-200) SETB TR0 SJMP $ ; Khng lm g c, cc ng dng thc t ; c th thm chng trnh vo ;---------------------Timer0_ISR: MOV A,Led_Pos ; Xc nh v tr Led hin hnh MOV P1,A ; Sng Led hin hnh RL A ; Dch tri chuyn qua Led k MOV Led_Pos,A ; trong qua trnh trn tip theo MOV A,@R0 ; c d liu hin hnh MOV P0,A INC R0 ; Chuyn qua d liu k CJNE R0,#Led_Pos,exitTimer0 ; Nu qut ht ton b MOV Led_Pos,#01h ; Led th bt u li t Led1 MOV R0,#Led1 exitTimer0: RETI END V d 2 c th m rng thm cho 8 Led trong cc bit iu khin t P1.0 n P1.7 bng cch khai bo thm cc nh cho cc Led nh sau: Led1 EQU 30h Led2 EQU 31h Led3 EQU 32h Led4 EQU 33h Led5 EQU 34h Led6 EQU 35h Led7 EQU 36h Led8 EQU 37h Led_Pos EQU 38h ; a ch cha d liu ca Led1 ; a ch cha d liu ca Led2
; V tr Led hin hnh
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V d 3: Vit chng trnh hin th ni dung trong nh 30h ra 2 Led trong Led1 cha s hng chc v Led2 cha s hng n v (gi s gi tr trong nh 30h ti a l 99). Gii xut ni dung trong nh 30h ra Led 7 on cn thc hin: Chuyn ni dung trong nh 30h thnh s hng chc v hng n v (thc hin chia cho 10). Chuyn gi tr s thnh m Led 7 on (bng cch tra bng).
Chng trnh thc hin nh sau: Led1 EQU 30h ; a ch cha d liu ca Led1 Led2 EQU 31h ; a ch cha d liu ca Led2 Led_Pos EQU 32h ; V tr Led hin hnh ORG 0000h LJMP main ORG 000Bh ; a ch ISR ca timer 0 LJMP Timer0_ISR Main: SETB EA ; Cho php ngt ti timer 0 SETB ET0 MOV Led_Pos,#01h ; V tr sng u tin l Led1 MOV R0,#Led1 ; D liu gi ra u tin l Led1 MOV TMOD,#01h MOV TH0,#(-200) MOV TL0,#(-200) SETB TR0 Begin: MOV A,30h CALL Chuyenma SJMP Begin ;---------------------Chuyenma: MOV B,#10 ; Chia cho 10: A cha s hng chc, DIV AB ; B cha s hng n v CALL BCDtoLed7 ; Chuyn sang m Led 7 on MOV Led1,A ; a vo nh 31h (Led1) MOV A,B ; Chuyn sang m Led 7 on ca CALL BCDtoLed7; s hng n v MOV Led2,A
Gio trnh Vi iu khin
RET ;---------------------BCDtoLed7: MOV DPTR,#MaLed7 MOVC A,@A+DPTR RET MaLed7: DB 0C0h,0F9h,0A4h,0B0h,99h,92h,82h,0F8h,80h,90h ;---------------------Timer0_ISR: PUSH ACC MOV A,Led_Pos ; Xc nh v tr Led hin hnh MOV P1,A ; Sng Led hin hnh RL A ; Dch tri chuyn qua Led k MOV Led_Pos,A ; trong qua trnh trn tip theo MOV A,@R0 ; c d liu hin hnh MOV P0,A INC R0 ; Chuyn qua d liu k CJNE R0,#Led_Pos,exitTimer0 ; Nu qut ht ton b MOV Led_Pos,#01h ; Led th bt u li t Led1 MOV R0,#Led1 exitTimer0: POP ACC RETI END 2.2.2. Phng php cht Khi thc hin tch ring cc ng d liu ca Led, ta c th cho php cc Led sng ng thi m s khng c hin tng nh hng gia cc Led. IC cht cho php lu tr d liu cho cc Led c th s dng l 74LS373, 74LS374. Khi thc hin bng phng php cht, khi no cn xut d liu ra Led th gi d liu v to xung cht. V d: Xt s mch kt ni nh hnh 4.8. Vit chng trnh xut s 2 ra Led3 v s 3 ra Led4. Gii Do Led3 ni vi 74LS374 (U5) iu khin bng chn P1.0 nn hin th trn Led3, cn phi: Xut d liu ra P0. Kch xung ti chn P1.0 cht d liu
Phm Hng Kim Khnh
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Gio trnh vi iu khin Phm Hng Kim Khnh

U3 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 1 2 3 4 5 6 7 220
+5V LED1 a b c d e f g 7 6 4 2 1 9 10 5 a b c d e f g p a b c d e f g C1 C2 7 6 4 2 1 9 10 5 LED2 a b c d e f g p
1 R6 10k
C1 3
9 8 7 6 5 4 3 2
RN2 14 13 12 11 10 9 8 a b c d e f g
+5V
C2
R7 Q2 C828 10K
R8 Q3 C828 10K
Hnh 4.7 Kt ni Led 7 on dng phng php qut
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U4 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 3 4 7 8 13 14 17 18 11 1
+5V
1 R9 10k 9 8 7 6 5 4 3 2
U5 D0 D1 D2 D3 D4 D5 D6 D7 CLK OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 1 2 3 4 5 6 7
RN3 14 13 12 11 10 9 8 220 7 6 4 2 1 9 10 5
LED3 a b c d e f g p
C1 3
C2
74LS374 U6 3 4 7 8 13 14 17 18 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CLK OE 74LS374 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 1 2 3 4 5 6 7
RN4 14 13 12 11 10 9 8 220 7 6 4 2 1 9 10 5
LED4 a b c d e f g p
+5V
C1 3
Hnh 4.8 Kt ni Led 7 on dng phng php cht
C2
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Chng trnh thc hin nh sau: MOV P0,#0B0h CLR P1.0 SETB P1.0 MOV P0,#99h CLR P1.1 SETB P1.1 END
3. iu khin ma trn Led

Ma trn LED bao gm nhiu LED cng nm trong mt v chia thnh nhiu ct v hng, mi giao im gia hng v ct c th c 1 LED (ma trn LED mt mu) hay nhiu LED (2 LED ti mt v tr to thnh ma trn LED 3 mu). LED ti mt v tr no sng th phi cp hiu in th dng gia Anode v Cathode. Trn c s cu trc nh vy, ta c th m rng hng v ct ca ma trn LED to thnh cc bng quang bo.
Hnh 4.9 Hnh dng ma trn Led Kt ni ca ma trn Led c 2 cch: anode ni vi hng, cathode ni vi ct hay ngc li. S kt ni m t nh hnh 4.10. Theo cu trc kt ni nh hnh v, 2 Led trn 2 ct khng th sng ng thi. Xt s kt ni nh mch hnh b, mt Led sng khi tng ng hng ca Led = 0 v ct = 1. Gi s ta cn sng Led ng thi ti hng 1, ct 1 v hng 2, ct 2. Nh vy, ta phi c hng 1 = 0, ct 1 = 1 (sng Led ti hng 1, ct 1) v hng 2 = 0, ct 2 = 1 (sng Led ti hng 2, ct 2). T , do hng 1 = 0, ct 2 = 1 v hng 2 = 0, ct 2 = 1 nn ta cng c cc Led ti hng 1, ct 2 v hng 2, ct 1 cng sng. Ngha l, khi ta cho 2 Led ti hng 1, ct 1 v hng 2, ct 2 sng ng thi th s dn n cc Led ti hng 1, ct 2 v hng 2, ct 1 cng sng. Do , thc hin sng mt k t trn ma trn Led, ta phi dng c ch qut, ti mi thi im ch sng 1 ct, cc ct cn li tt i nhng nu cho thi gian qut nhanh th ta vn thy ging nh cc ct sng ng thi.
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Hnh a
Hnh b
Hnh 4.10 S kt ni ma trn Led
Phm Hng Kim Khnh
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D liu cho s 0: X X X X X X X X X X X X X X X X
sng s 0 trn ma trn Led, ta thc hin qu trnh qut nh sau: Ln 1: Hng = 0100 0001b, ct = 0001 0000b Ln 2: Hng = 0011 1110b, ct = 0000 1000b Ln 3: Hng = 0011 1110b, ct = 0000 0100b Ln 4: Hng = 0011 1110b, ct = 0000 0010b Ln 5: Hng = 0100 0001b, ct = 0000 0001b V d: Xt s kt ni ma trn Led nh hnh 4.11. Vit chng trnh sng s 0 trn ma trn Led. Gii main: MOV R0,#0 lap: MOV A,R0 MOV DPTR,#cot MOVC A,@A+DPTR MOV P1,A MOV A,R0 MOV DPTR,#hang MOVC A,@A+DPTR MOV P0,A CALL delay INC R0 CJNE R0,#5,lap
Phm Hng Kim Khnh
; Xut ct
; ; ; ;
Xut hng To thi gian tr hon thy Chuyn sang ct k Nu qut 5 ct th lp li

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SJMP main ;-------------------delay: MOV TMOD,#01h MOV TL0,#LOW(-500) MOV TH0,#HIGH(-500) SETB TR0 JNB TF0,$ CLR TF0 CLR TR0 RET ;-------------------cot: DB 01h,02h,04h,08h,10h hang: DB 41h,3Eh,3Eh,3Eh,41h END V d 2: Vit chng trnh cho chui KTCN di chuyn t tri sang phi trn ma trn Led. Gii Gii thut Led di chuyn t tri sang phi tham kho thm ti Ti liu Th nghim Vi x l Bi 3 (ma trn Led v bn phm) (download ti Website http://eed.hutech.edu.vn). main2: MOV R2,#0 main1: MOV R1,#20 ; Mt k t qut 20 ln main: MOV R0,#0 lap: MOV A,R0 MOV DPTR,#cot MOVC A,@A+DPTR MOV P1,A MOV A,R0 ADD A,R2 MOV DPTR,#hang MOVC A,@A+DPTR MOV P0,A
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VCC 1 R10
Hnh 4.11 S kt ni ma trn Led vi AT89C51
U7 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 VCC R15 Q8 R16 Q9 R17 1 2 3 4 5 6 7 8
9 8 7 6 5 4 3 2
RN5 16 15 14 13 12 11 10 9
Q10 R18 Q11 R19 Q12
Gio trnh Vi iu khin
CALL delay INC R0 CJNE R0,#5,lap DJNZ R1,main INC R2 CJNE R2,#31,main1 ; Nu qut ht chui th lp li SJMP main2 ;----------delay: MOV TMOD,#01h MOV TL0,#LOW(-500) MOV TH0,#HIGH(-500) SETB TR0 JNB TF0,$ CLR TF0 CLR TR0 RET cot: DB 01h,02h,04h,08h,10h hang: DB 00h,77h,6Bh,5Dh,3Eh,7Fh ;M ch K DB 7Eh,7Eh,00h,7Eh,7Eh,7Fh ;M ch T DB 41h,3Eh,3Eh,3Eh,5Dh,7Fh ;M ch C DB 00h,7Dh,7Bh,77h,00h,7Fh ;M ch N DB 7Fh,7Fh,7Fh,7Fh,7Fh ; Cc ct trng END
4. iu khin ng c bc
ng c bc l ng c cho php dch chuyn mi ln mt bc hay na bc tu theo xung iu khin. Gc quay ca mi bc tu theo loi ng c, thng l 1.80/bc hay 7.20/bc. ng c bc gm 4 cun dy: 1-2, 2-3, 4-5 v 5-6 nh s sau:
MG1 1 2 3
STEPPER MOTOR
Hnh 4.12 ng c bc
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Mch iu khin ng c nh sau:

VCC
R1 Q1
D1 1 2 3
MG1
R2 Q2 D2
MOTOR STEPPER
R3 Q3 D3
R4 Q4 D4
Hnh 4.13 S iu khin ng c bc Xung iu khin ng c nh sau: Bng 4.5 - iu khin mt bc Ngc 1 2 3 4 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 Thun 1 1 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 1 0 0 0 4
1 1 1 1 0 0
Bng 4.6 - iu khin na bc Ngc 2 3 4 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0
Thun 2 0 0 0 0 1 0 0 1 1 1 3 1 1 1 0 0 4
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0 0 0 1
0 0 0 0
1 1 0 0
0 1 1 1
0 1 1 1
1 1 0 0
0 0 0 0
0 0 0 1
V d: Xt s kt ni ng c nh hnh 4.14. Vit chng trnh iu khin ng c quay thun mi ln mt bc vi tc 50 vng/pht (gi s ng c c gc quay l 7.20/bc).
VCC
R11 Q4 U8 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29
D13 1 2 3
MG1
R12 Q5 D14
MOTOR STEPPER
R13 Q6 D15
R14 Q7 D16
Hnh 4.14 S kt ni AT89C51 vi ng c bc Gii Gc quay 7.20/bc 1 vng quay cn 3600/7.20 = 50 bc 50 vng quay cn thc hin 2500 bc. Tc 50 vng / pht 1 pht (60s) thc hin 2500 bc mi bc cn 60/2500 = 0.024s = 24,,000 s. Th t kch xung nh bng 4.5. Chng trnh thc hin nh sau: main: MOV R0,#0 MOV DPTR,#thuan1buoc
Gio trnh Vi iu khin
begin: MOV A,R0 MOVC A,@A+DPTR MOV P2,A ; Xut ra P2 iu khin ng c CALL Delay INC R0 CJNE R0,#4,begin SJMP main ;----------------Delay: MOV TMOD,#01h MOV TH0,#HIGH(-24000) MOV TL0,#LOW(-24000) SETB TR0 JNB TF0,$ CLR TF0 CLR TR0 RET thuan1buoc: DB 08h,04h,02h,01h END
5. iu khin LCD (Liquid Crystal Display)

S ca LCD1602A:
1602 LCD
THIS IS THE LCD 2 LINES x 16 CHARACTERS

CONST GND VCC R/W RS EN D0 D1 D2 D3 D4 D5 D6 D7
7 8 9 10 11 12 13 14
Hnh 4.15 LCD 1602A CONST (contrast): chnh tng phn ( sng ca hnh nh trn LCD). EN (Enable): cho php c/ghi d liu. Trong ch c, EN tc ng bng xung dng (cnh ln) v trong ch ghi, EN tc ng bng xung m (cnh xung).
Phm Hng Kim Khnh
15 16
A K
LAMP
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RS (register selection): chn thanh ghi lnh (RS = 0) hoc thanh ghi d liu (RS = 1) R/W: c (R/W = 1) hay ghi (R/W = 0) D7 D4: bus d liu (ch 8 bit: 4 bit cao, ch 4 bit: dng cho truyn 4 bit cao v 4 bit thp). Ngoi ra, bit D7 cn dng lm ng ra cho c Busy. D3 D0: 4 bit thp trong ch 8 bit hay b trng trong ch 4 bit. A, K: anode v cathode n nn ca LCD. Cc thnh phn chc nng ca LCD1602A:
C Busy (BF Busy flag): Nu BF = 1, LCD ang trong qu trnh thc thi mt lnh. Khi , cc lnh gi tip theo s b b qua. BF c c ti chn D7 khi RS = 0 v R/W = 1. Do , trc khi thc hin mt lnh, cn kim tra BF trc, nu BF = 0 th mi gi lnh. DDRAM (Display Data RAM): cha cc k t s hin th trn LCD, ti a l 80x8 bit (80 k t). Khi hin th ch 1 dng, a ch ca DDRAM c phm vi t 00h 4Fh cn khi ch 2 dng, a ch DDRAM t 00h 27h cho dng 1 v 40h 67h cho dng 2. B m a ch (AC - Address Counter): dng lu a ch hin hnh ca DDRAM v CGRAM, c th thc hin c AC khi RS = 0 v R/W = 1. CGROM (Character Genaration ROM): cha cc m hnh k t s hin th trn LCD, bao gm 192 k t 5x7 theo bng m ASCII (ngha l khi DDRAM cha gi tr 41h tng ng vi m ASCII ca k t A th trn LCD s hin A), trong ch c cc m t 00h 0Fh s khng ly theo m ASCII m ly theo cc k t nh ngha trong CGRAM. CGRAM (Character Genaration RAM): cha cc m hnh k t do ngi s dng nh ngha hin th cc k t khng c sn trong CGROM. CGRAM cho php to ti a 8 k t 5x8 (xem bng 4.7).
Bng 4.7 Cc k t nh ngha trong CGRAM DDRAM a ch CGRAM D liu CGRAM K t 00h hay 08h 000 000 xxx ????? 1 000 001 xxx ????? 000 010 xxx ????? 000 011 xxx ????? 000 100 xxx ????? 000 101 xxx ????? 000 110 xxx ????? 000 111 xxx ?????
Gio trnh Vi iu khin
01h hay 09h
02h hay 0Ah
03h hay 0Bh
04h hay 0Ch
05h hay 0Dh
001 000 001 001 001 010 001 011 001 100 001 101 001 110 001 111 010 000 010 001 010 010 010 011 010 100 010 101 010 110 010 111 011 000 011 001 011 010 011 011 011 100 011 101 011 110 011 111 100 000 100 001 100 010 100 011 100 100 100 101 100 110 100 111 101 000 101 001 101 010 101 011 101 100 101 101 101 110 101 111
xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ????? xxx ?????
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06h hay 0Eh 110 000 xxx ????? 7 110 001 xxx ????? 110 010 xxx ????? 110 011 xxx ????? 110 100 xxx ????? 110 101 xxx ????? 110 110 xxx ????? 110 111 xxx ????? 07h hay 0Fh 111 000 xxx ????? 8 111 001 xxx ????? 111 010 xxx ????? 111 011 xxx ????? 111 100 xxx ????? 111 101 xxx ????? 111 110 xxx ????? 111 111 xxx ????? nh ngha mt k t, thc hin thay th du ? bng cc gi tr 0 hay 1 tng ng v gi vo CGRAM. V d: nh ngha ch ti v tr 1 trong CGRAM, a ch v d liu tng ng l: a ch 00h 01h 02h 03h 04h 05h 06h 07h 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 D liu 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1Eh 09h 09h 1Dh 09h 09h 1Eh 00h
Ngha l ti a ch 00h ca CGRAM cha gi tr l 1Eh v tng t cho n a ch 07h. Cc ch truyn d liu: LCD1602A c 2 ch truyn d liu: ch 8 bit (dng c D0 D7) v ch 4 bit (khng dng D3 D0, ch dng D7 D4). Trong trng hp dng ch 4 bit, d liu 8 bit s c truyn 2 ln: truyn 4 bit cao ri tip tc truyn 4 bit thp.
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Sau khi thc hin truyn xong 8 bit, BF mi chuyn ln 1. Hai ch truyn ny m t nh hnh 4.16 v 4.17.
Hnh 4.16 nh thi giao tip ch 8 bit
Hnh 4.17 nh thi giao tip ch 4 bit

Gio trnh Vi iu khin
Tp lnh: Bng 4.8 - Tp lnh ca LCD1602A

M lnh Lnh RS R/W D7 D6 D5 D4 D3 D2 D1 D0 Ghi 20h (khong trng) vo DDRAM v t a ch DDRAM l 00h t a ch DDRAM l 00h v tr con tr v v tr u (ni dung DDRAM khng i) - Chiu di chuyn con tr I/D = 1: tng I/D = 0: gim - Dch ton mn hnh khi ghi DDRAM: S = 1: cho php dch S = 0: cm D = 1: hin mn hnh D = 0: cm C = 1: hin con tr C = 0: cm B = 1: nhp nhy B = 0: cm S/C = 1: dch mn hnh S/C = 0: dch con tr R/L = 1: dch phi R/L = 0: dch tri DL = 1: 8 bit DL = 0: 4 bit N = 1: 2 dng N = 0: 1 dng M t Thi gian thc thi (fOSC = 270 KHz)
Xo mn hnh
1.53ms
V u chui
1.53ms
nh ch
I/D
39s
iu khin hin th
39s
Dch con tr hay mn hnh
S/C
R/L
39s
Chc nng
DL
39s
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F = 0: k t 5x7 F = 1: k t 5x10 Xc nh a ch ca CGRAM Xc nh a ch ca DDRAM Xc nh a ch hin hnh v kim tra xem c th gi lnh tip hay khng BF = 1: khng BF = 0: c th Ghi d liu vo DDRAM hay CGRAM c d liu t DDRAM hay CGRAM
nh a ch CGRAM nh a ch DDRAM
AC5
AC4
AC3
AC2
AC1
AC0
39s
AC6
AC5
AC4
AC3
AC2
AC1
AC0
39s
c BF v a ch hin hnh
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Ghi d liu c d liu
D7
D6
D5
D4
D3
D2
D1
D0
43s
D7
D6
D5
D4
D3
D2
D1
D0
43s
I/D: Increment/Decrement R/L: Right/Left F: Font type
S: Screen S/C: Screen/Cursor DL: Data Length N: Line number AC: Address Counter
Cc gi tr thng dng m t nh sau: Bng 4.9 Cc lnh thng dng Lnh M t Xa mn hnh mn hnh Tr v u chui Dch con tr sang tri Dch con tr sang phi Dch mn hnh sang phi Dch mn hnh sang tri Tt con tr, tt hin th Tt hin th, bt con tr Bt hin th, tt con tr Bt hin th, nhp nhy con tr Tt hin th, nhp nhy con tr Dch v tr con tr sang tri Dch v tr con tr sang phi Dch ton b mn hnh sang tri
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01H 02H 04H 06H 05H 07H 08H 0AH 0CH 0EH 0FH 10H 14H 18H
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1CH 80H C0H 38H
Dch ton b mn hnh sang phi a con tr v u dng 1 a con tr v u dng 2 Xc lp ch 2 dng v phn gii ch 5x7
V d 1: Cho s kt ni LCD 1602A vi AT89C51 nh hnh v. Vit chng trnh hin th chui KHOA DIEN DIEN TU trn dng 1 v BO MON DIEN TU VIEN THONG trn dng 2.
1602
CONST
GND
VCC
R/W
RS
EN
D0 D1 D2 D3 D4 D5 D6 D7
7 8 9 10 11 12 13 14
VCC U9 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9
Hnh 4.18 Kt ni LCD v 89C51 Gii 8 bit d liu ca LCD ni vi P1 ch 8 bit. Yu cu hin trn 2 dng ch 2 dng. Chng trnh thc hin nh sau: EN RS BIT BIT P2.2 P2.0
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15 16
A K
LAMP
THIS IS THE LCD 2 LINES x 16 CHARACTERS
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RW BIT P2.1 LCD_DATA EQU P1 ;---------------------------------------------------main: MOV LCD_DATA,#38h ; t ch 2 dng CALL write_command MOV LCD_DATA,#0Ch ; bt hin th CALL write_command MOV LCD_DATA,#01h CALL write_command ;xo mn hnh
MOV LCD_DATA,#80h ; Chuyn v a ch 00h (dng 1) CALL write_command MOV DPTR,#Line1 CALL write ; Ghi vao DDRAM MOV LCD_DATA,#0C0h ; Chuyn v a ch 40h (dng 2) CALL write_command MOV DPTR,#Line2 CALL write ; Ghi vao DDRAM SJMP $ ;-------------------------------------------------------write: CLR A MOVC A,@A+DPTR CJNE A,#0FFh,write1;Nu gi tr l 0FFh th ht chui RET write1: MOV LCD_DATA,A call write_data INC DPTR SJMP write ;-------------------------------------------------write_command: CLR RS CLR RW CLR EN NOP
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SETB EN NOP CLR EN CALL Delay RET ;-------------------------------------------------write_data: SETB RS CLR RW CLR EN NOP SETB EN NOP CLR EN CALL Delay RET ;-------------------------------------------------Delay: PUSH 07h PUSH 06h MOV R6,#50 MOV R7,#255 DJNZ R7,$ DJNZ R6,$-4 POP 06h POP 07h RET ;-------------------------------------------------Line1: DB 'KHOA DIEN DIEN TU', 0FFh Line2: DB 'BO MON DIEN TU VIEN THONG', 0FFH END V d 2: Yu cu ging nh v d 1 nhng c mi 1s th dch chui sang tri mt k t. Gii Chng trnh thc hin nh trn nhng thm phn x l ngt cho timer 0: c nh thi 1s th dch chui sang tri (ngha l dch ton b mn hnh sang phi). Theo bng 4.9, lnh cn gi ra LCD c m lnh l 1Ch. Chng trnh thc hin nh sau:
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ORG 0000h LJMP main ORG 000Bh LJMP Timer0_ISR Main: MOV IE,#82h ; Cho php ngt ti Timer 0 MOV TMOD,#01h MOV TH0,#HIGH(-50000) MOV TL0,#LOW(-50000) MOV R7,#20 SETB TR0 Timer0_ISR: MOV TH0,#HIGH(-50000) MOV TL0,#LOW(-50000) DJNZ R7,exitTimer0 MOV R7,#20 MOV LCD_DATA,#1Ch ;Dch ton mn hnh sang phi CALL write_command exitTimer0: RETI END V d 3: Cho mch kt ni LCD nh hnh 4.18, vit chng trnh xut chui Khoa in in t trn dng 1 v B mn in t - Vin thng trn dng 2. Gii V d ny yu cu cc k t khng c trong bng m nn phi nh ngha thm trong CGRAM. Cc k t cn nh ngha l: , , , , , , tng cng l 6 k t (c th thc hin c do LCD 1602A cho php nh ngha ti a 8 k t).
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a ch v d liu tng ng l: a ch 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0
1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0
D liu 1 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0
K t M DDRAM 1Eh 09h 09h 1Dh 09h 09h 1Eh 00h 04h 0Eh 11h 1Eh 10h 0Fh 04h 00h 08h 05h 09h 12h 12h 12h 0Ch 00h 04h 0Ah 0Eh 11h 11h 0Eh 04h 00h
00h
01h
02h
03h
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a ch 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
0 0 0 1 1 0 0 0
1 1 1 0
04h 0Ah 0Eh 11h 11h 0Eh 00h 00h 05h 1 0Eh 1 0Ah 1 1Fh 1 1Fh 10h 1 1 1 1 0Fh 0 0 0 0 00h
0 1 1 0 0 1 0 0
D liu 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
K t M DDRAM
04h
05h
Chng trnh thc hin nh sau: EN BIT P2.2 RS BIT P2.0 RW BIT P2.1 LCD_DATA EQU P1 ;---------------------------------------------------org 0 ljmp main main: MOV LCD_DATA,#38h CALL write_command MOV LCD_DATA,#0Ch CALL write_command MOV LCD_DATA,#01h CALL write_command MOV LCD_DATA,#40h call write_command MOV DPTR,#cgram_data CALL write
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;xo mn hnh
; a ch u ca CGRAM ; l 00h
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MOV LCD_DATA,#80h CALL write_command MOV DPTR,#Line1 CALL write MOV LCD_DATA,#0C0h CALL write_command MOV DPTR,#Line2 CALL write here:SJMP here ;-------------------------------------------------------write: CLR A MOVC A,@A+DPTR CJNE A,#0FFh,write1 RET write1: MOV LCD_DATA,A call write_data INC DPTR SJMP write ;-------------------------------------------------------Delay: PUSH 07h PUSH 06h MOV R6,#50 MOV R7,#255 DJNZ R7,$ DJNZ R6,$-4 POP 06h POP 07h RET ;-------------------------------------------------write_command: CLR RS CLR RW CLR EN NOP SETB EN NOP
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CLR EN SJMP wait ;-------------------------------------------------write_data: SETB RS CLR RW CLR EN NOP SETB EN NOP CLR EN wait: call delay ret ;------------------------------------------------Line1: DB 'Khoa ',00h,'i',01h,'n - ',00h,'i',01h,'n t',02h,0FFh ; Chui Khoa in in t Line2: DB 'B',03h,' m',04h,'n ',00h,'i',01h,'n t',02h,' vi',05h,'n th',04h,'ng', 0FFH ; Chui B mn in t Vin thng ;------------------------------------------------cgram_data: DB 1Eh,09h,09h,1Dh,09h,09h,1Eh,00h ; Ch DB 04h,0Eh,11h,1Eh,10h,0Fh,04h,00h ; Ch DB 08h,05h,09h,12h,12h,12h,0Ch,00h ; Ch DB 04h,0Ah,0Eh,11h,11h,0Eh,04h,00h ; Ch DB 04h,0Ah,0Eh,11h,11h,0Eh,00h,00h ; Ch DB 05h,0Eh,0Ah,1Fh,1Fh,10h,0Fh,00h ; Ch DB 0FFh END
6. Giao tip vi PPI8255

PPI8255 l IC giao tip lp trnh c, cho php m rng port trong trng hp cc port ca 89C51 khng dng. Cc ch hot ng ca 8255 c th tham kho thm ti Gio trnh Vi x l (cng tc gi). 8255 c tng cng 2 ch : BSR (Bit Set/Reset) v I/O (Input/Output) trong I/O chia thnh 3 ch khc nhau, tron ti liu ny ch xt ch 0 (xut/nhp c bn). 8255 c tng cng 3 port, mi port 8 bit trong port C c th chia thnh 4 bit cao v 4 bit thp to thnh 2 nhm: nhm A (PA + PCH) v nhm B (PB v PCL).
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Cc ng dng da trn vi iu khin MCS-51 D7 D0: bus d liu PA7 PA0: Port A PB7 PB0: Port B PC7 PC0: Port C A1, A0: gii m RESET: ng vo Reset
34 33 32 31 30 29 28 27 5 36 9 8 35 6
D0 D1 D2 D3 D4 D5 D6 D7 RD WR A0 A1 RESET CS
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
4 3 2 1 40 39 38 37 18 19 20 21 22 23 24 25 14 15 16 17 13 12 11 10
8255
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
CS : Chip Select
RD : Read
Hnh 4.19 S chn ca 8255 iu khin 8255, bn trong c mt thanh ghi iu khin (CR Control Register) cho php chn ch hot ng. Ni dung ca CR nh sau:
1 D6 D5 D4 D3 D2 D1 D0
Nhm A
Nhm B
PCH (PC7 PC4) 1: Input 0: Output
PCL (PC3 PC0) 1: Input 0: Output
PA 1: Input 0: Output
PB 1: Input
Hnh 4.20 Dng t iu khin cho 8255A ch I/O
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D7 0 Mode BSR
D6 x
D5 x
D4 X
D3
D2
D1
D0 S/R
Khng s dng
Chn bit 000: PC0 001: PC1 010: PC2 011: PC3 100: PC4 101: PC5 110: PC6 111: PC7
0: Xo (Reset) 1: t (Set)
Hnh 4.21 - Dng t iu khin cho 8255A ch BSR Lu rng khi cn Set/Reset bit th phi gi d liu ra CR ch khng gi ra PC. Nh vy, xc lp iu khin lm vic cho 8255, cn thc hin nh cu hnh cho 8255 (chn cc ch hot ng cho PA, PB v PC). thc hin qu trnh ny, cn tc ng n CR ca 8255. Logic chn cc port cho 8255 m t nh sau: Bng 4.10 Logic chn cc port ca 8255
CS
0 0 0 0 1 A1 0 0 1 1 x A0 0 1 0 1 x Port A Port B Port C Thanh ghi iu khin 8255A khng hot ng Chn
V d: Cho mch kt ni gia AT89C51 v 8255 nh hnh 4.22. Vit chng trnh iu khin theo yu cu: Nhn SW1: sng 4 Led tri v sng Lamp. Nhn SW2: sng 4 Led phi v tt Lamp.
Gii
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21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN WR RD ALE VCC
VCC
DATA BUS ADDRESS BUS

U10 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST AT89C51 1 2 3 6 4 5 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9 U11 A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 8255 3 D79 VCC 1 2 4 1 2 LAMP D0 D1 D2 D3 D4 D5 D6 D7 ALE D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 11 1 U12 D0 D1 D2 D3 D4 D5 D6 D7 LE OE 74LS373 RD WR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 34 33 32 31 30 29 28 27 9 8 35 5 36 6 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 RESET RD WR CS U13 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 4 3 2 1 40 39 38 37 18 19 20 21 22 23 24 25 14 15 16 17 13 12 11 10 RL1 5 1 2 3 4 5 6 7 8 RN6 16 15 14 13 12 11 10 9 220 VCC D71 D72
...
D78
R20 10K
R21 10K SW1
SW2
220V
74LS138
Hnh 4.22 S kt ni 89C51 vi 8255
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Do PA iu khin Led, PCL iu khin cng tc nhn, PCH iu khin RL1 nn PA xut, PCL nhp v PCH xut (cn PB tu ). Ni dung thanh ghi iu khin nh sau: 1 0 0 0 0 0 0 1 81h I/O Ch 0 PA xut PCH xut Ch 0 PB xut PCL nhp Led n ni vi cc bit ca PA ti cathode v anode ni vi Vcc nn Led sng th d liu ti PA l 0 v Led tt khi d liu l 1. n LAMP c iu khin bng RL1: khi RL1 ng (ng vi PC7 = 0) th LAMP sng v ngc li, khi RL1 ngt (ng vi PC7 = 1) th LAMP tt. Ni dung thanh ghi iu khin khi iu khin PC7 nh sau: PC7 = 0 0 0 0 0 1 1 1 0 0Eh BSR Khng dng PC7 =0 PC7 = 1 0 0 0 0 1 1 1 1 0Fh BSR Khng dng PC7 =1 Cng tc SW1, SW2 ni vi PC0 v PC1: khi nhn cng tc th chn tng ng ti PC = 0 v khi khng nhn th = 1. Do , kim tra cng tc c nhn hay khng th c d liu t PCL v kim tra tng ng cc bit PC0, PC1. a ch cc port ca 8255:
CS = 0 (Y6 = 0)
A15 A14 A13 A12 A11 A10 A9 A8
Tu
A7 A6 A5 A4 A3 A2
A1
A1
A0
A0
Port A B C CR
a hex
ch
0 0 1 1
0 1 0 1
C000h C001h C002h C003h
Chng trnh thc hin nh sau: MOV DPTR,#0C003h ; a ch CR MOV A,#81h; PA: xut, PB: xut, PCH: xut, PCL: nhp MOVX @DPTR,A ; Xut ra CR Begin: MOV DPTR,#0C002h ; a ch PC
Gio trnh Vi iu khin
MOVX A,@DPTR JNB ACC.0,SW1 JNB ACC.1,SW2 SJMP begin SW1: CALL Delay MOV A,11110000b MOV DPTR,#0C000h MOVX @DPTR,A MOV A,0Eh MOV DPTR,#0C003h MOVX @DPTR,A SJMP begin SW2: CALL Delay MOV A,00001111b MOV DPTR,#0C000h MOVX @DPTR,A
; c vo ; Nu PC0 = 0 th n SW1 ; Nu PC1 = 0 th n SW2
; Trnh rung phm ; Sng 4 Led tri ; a ch PA (do PA ni vi Led)
; PC7 = 0 ng RL1 sng LAMP ; a ch CR (do dng ch BSR)
; Sng 4 Led phi ; a ch PA (do PA ni vi Led)
MOV A,0Fh ; PC7 = 1 ng RL1 sng LAMP MOV DPTR,#0C003h ; a ch CR (do dng ch BSR) MOVX @DPTR,A SJMP begin ;---------------------------Delay: MOV TMOD,#02h MOV TH0,#HIGH(-50000) MOV TL0,#LOW(-50000) SETB TR0 JNB TF0,$ CLR TF0 CLR TR0 RET END
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BI TP CHNG 4
1. Cho s kt ni nh hnh 4.3. Vit chng trnh sng Led theo yu cu: sng ln lt 1 Led t phi sang tri v thc hin 4 ln; nhp nhy 8 Led 5 ln; sng Led t ngoi vo trong, mi ln 2 Led v thc hin 3 ln (thi gian tr hon gia 2 ln sng l 300ms, dng timer 1). 2. Cho s kt ni nh hnh 4.7. Vit chng trnh tng ni dung ca nh 30h t 00 99 v hin th gi tr trn 2 Led 7 on (hin th Led bng ngt timer 1 v thi gian tr hon khi tng ni dung ca nh 30h l 1s dng ngt timer 0). 3. Cho s kt ni nh hnh 4.7 trong kt ni thm 4 Led (Led2 6) c iu khin bng cc bit ca P1: P1.2 P1.5. Vit chng trnh hin th gi, pht giy trn 6 Led (Led1,2: gi; Led3,4: pht; Led5,6: giy) trong gi cha trong nh 30h, pht trong nh 31h, giy trong nh 32h (thi gian tr hon 1s dng ngt timer 0, qut Led dng ngt timer 1). 4. Cho s kt ni nh hnh 4.11. Vit chng trnh cho chui DAI HOC KY THUAT CONG NGHE TPHCM di chuyn t tri sang phi trn ma trn Led. 5. Cho s kt ni nh hnh 4.14. Vit chng trnh iu khin ng c quay thun 100 vng vi tc 10 vng/pht (gi s mi bc c gc quay l 7.20). 6. Cho s kt ni nh hnh 4.18. Vit chng trnh cho chui i hc K thut Cng ngh trn dng 1 v Khoa in in t trn dng 2 di chuyn t tri sang phi (thi gian dch chuyn l 300ms dng ngt timer 1).
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Ph lc 2 M phng bng Proteus
Ph lc 2: M PHNG BNG PROTEUS

1. Gii thiu
Phn mm Proteus l phn mm cho php m phng hot ng ca mch in t bao gm phn thit k mch v vit chng trnh iu khin cho cc h vi iu khin nh MCS-51, PIC, AVR, Phn mm bao gm 2 chng trnh: ISIS cho php m phng mch v ARES dng v mch in. Khi ng chng trnh Start > All Program > Proteus 6 Professional > ISIS 6 Professional
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Ca s chng trnh sau khi khi ng: Thanh cng c chun Vng khng gian dng v mch in
Thanh cng c chn linh kin
Cc nt chn cho php bt u, tm dng hay kt thc qu trnh m phng
Cc thao tc c bn S dng thanh cng c chun:
New: to mch in mi Open: m mch in c sn
Save: lu tr mch in Zoom In: phng to mch
Zoom Out: thu nh mch in Zoom All: hin ton b mch
Zoom to Area: phng to mt vng mch in
Cc thao tc trn thanh cng c chun cng c th thc hin thng qua menu File v menu Edit.
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S dng thanh linh kin: Linh kin c chn
Nhm cc linh kin va s t tn cho dy dn Ni dy dng bus Ngun v GND Cc thit b to tn hiu sin, vung, Cc thit b o dng sng
Cc linh kin trong nhm
Cho php quay linh kin
a linh kin vo vng thit k, ta thc hin chn linh kin ri nhn chut tri trn vng lm vic. thc hin chn linh kin, ta thc hin nhn chut phi trn linh kin, n s chuyn sang mu cho bit trng thi ang chn.
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Sau khi chn linh kin, ta c th di chuyn linh kin bng cch thc hin thao tc drag-and-drop (nhn chut tri v gi ri di chuyn chut n v tr k). xo linh kin, ta chn linh kin ri nhn chut phi ln na xo. Thm linh kin mi: Nu linh kin khng tn ti trong thanh linh kin, ta phi thc hin thm mi t cc th vin c sn bng cch chn menu Library > Pick hay nhn P.
Ca s ly linh kin:
Tn linh kin Tm kim linh kin Cc th vin cha linh kin Cc th vin con Hnh nh linh kin
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V d nh tm linh kin in tr: G Resistor trong vng Keywords. Chn Category l Resistors. Chn Sub-category l Generic.
Ni dy: Chuyn con tr chut n v tr cn ni dy, trn con tr chut s xut hin du X
Di chuyn chut v nhn chut tri khi cn thit xc nh v tr dy dn
Khi ko dy n v tr cn thit th nhn chut tri ni dy.
2. M phng 89C51
thc hin qu trnh m phng 89C51 trong Proteus, ta cn thc hin cc bc sau: Bc 1: V mch nguyn l. Bc 2: nh ngha chng trnh dch
Chn menu Source > Define Code Generation Tools
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Sau thc hin chn chng trnh dch mong mun. y ta thc hin m phng cho 89C51 nn chn chng trnh ASEM51.
Phn Tools: chn ASEM51, phn Command Line: g vo %1. Bc 3: nh ngha file chng trnh cho 89C51.
Chn menu Source > Add/Remove Source File
Chn phn Code Generation Tool l ASEM51.
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To file mi
Do cha c chng trnh cho 89C51, ta nhn vo nt New to file. Trong phn File name, ta g vo tn chng trnh (gi s g vo bai2).
Nu cha c file bai2.ASM, Proteus s xut hin thng bo yu cu to file, nhn Yes to:
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Sao khi to file thnh cng, trn menu Source s xut hin thm file bai2.ASM.
Bc 4: nh ngha file thc thi cho 89C51
Chn file bai2.ASM son tho chng trnh ngun, nhp vo END v nhn nt Save.
Nhn Save lu
Sau khi lu file ngun, ta thc hin dch chng trnh ngun.
Khi bin dch, nu c li, chng trnh dch s thng bo li, nu khng th s to ra file bai2.HEX.
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Thng bo chng trnh khng c li
Thc hin gn file thc thi cho 89C51 bng cch nhn chut phi ln 89C51 chn (89C51 s chuyn sang mu ) ri nhn chut tri m ca s thuc tnh ca 89C51.
Nt Browse: M chng trnh thc thi
Nhn vo nt Browse (hnh v trn) m chng trnh thc thi, chn chng trnh l bai2.HEX
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Nhn nt Open m file, khi trong thuc tnh Program File ca 89C51 s c tn chng trnh l bai2.HEX.
Sau khi gn file thc thi cho 89C51, ta ch cn thc hin sa chng trnh ngun v bin dch li m khng cn gn li file thc thi. C th tham kho thm phn hng dn s dng ca Proteus ng dng tong m phng 89C51 ti Website: http://eed.hutech.edu.vn, phn H tr hc tp
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Ph lc 3 Tm tt tp lnh
Ph lc 3: TM TT TP LNH
Mnemonic Description Byte Oscillator Period 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 2 2 1 1 1 1 1 1 2 1 2 2 3 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 24 48 48 12 12 12 12 12 12 24
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ARITHMETIC OPERATIONS ADD A,Rn Add register to Accumulator ADD A,direct Add direct byte to Accumulator ADD A,@Ri Add indirect RAM to Accumulator ADD A,#data Add immediate data to Accumulator ADDC A,Rn Add register to Accumulator with Carry ADDC A,direct Add direct byte to Accumulator with Carry ADDC A,@Ri Add indirect RAM to Accumulator with Carry ADDC A,#data Add immediate data to Acc with Carry SUBB A,Rn Subtract Register from Acc with Borrow SUBB A,direct Subtract direct byte from Acc with Borrow SUBB A,@Ri Subtract indirect RAM from ACC with Borrow SUBB A,#data Subtract immediate data from Acc with borrow INC A Increment Accumulator INC Rn Increment register INC direct Increment direct byte INC @Ri Increment direct RAM DEC A Decrement Accumulator DEC Rn Decrement Register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A & B DIV AB Divide A by B DA A Decimal Adjust Accumulator LOGICAL OPERATIONS ANL A,Rn AND Register to Accumulator ANL A,direct AND direct byte to Accumulator ANL A,@Ri AND indirect RAM to Accumulator ANL A,#data AND immediate data to Accumulator ANL direct,A AND Accumulator to direct byte ANL direct,#data AND immediate data to direct byte
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ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A DATA TRANSFER MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct,direct MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV DPTR,#data16
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OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct Byte Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumulator Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit Constant
1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3
12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 12 12 12 12 12 12 12 24 12 12 24 24 24 24 12 24 12 24
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MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A
Move Code byte relative to DPTR to Acc
1 1 1 1 1 1 2 2 1 2 2 1
24 24 24 24 24 24 24 24 12 12 12 12
Move Code byte relative to PC to Acc Move External RAM (8-bit addr) to Acc Move Exernal RAM (16-bit addr) to Acc Move Acc to External RAM (8-bit address) Move Acc to External RAM (16-bit address) PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A,Rn Exchange register with Accumulator XCH A,direct Exchange direct byte with Accumulator XCH A,@Ri Exchange indirect RAM with Accumulator XCHD A,@Ri Exchange low-order Digit indirect RAM with Acc BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C,bit AND direct bit to Carry ANL C,/bit AND complement of direct bit to Carry ORL C,bit OR direct bit to Carry ORL C,/bit OR complement of direct bit to Carry MOV C,bit Move direct bit to Carry MOV bit,C Move Carry to direct bit JC rel Jump if Carry is set JNC rel Jump if Carry not set JB bit,rel Jump if direct Bit is set JNB bit,rel Jump if direct Bit is Not set JBC bit,rel Jump if direct Bit is set & clear bit PROGRAM BRANCHING ACALL addr11 Absolute Subroutine Call LCALL addr16 Long Subroutine Call RET Return from Subroutine RETI Return from interrupt AJMP addr11 Absolute Jump LJMP addr16 Long Jump SJMP rel Short Jump (relative address) JMP @A+DPTR Jump indirect relative to the DPTR JZ rel Jump if Accumulator is Zero JNZ rel Jump if Accumulator is Not Zero
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1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2
12 12 12 12 12 12 24 24 24 24 12 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
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CJNE A,direct,rel
Compare direct byte to Acc and Jump if Not Equal CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal DJNZ Rn,rel Decrement register and Jump if Not Zero DJNZ direct,rel Decrement direct byte and Jump if Not Zero NOP No Operation
3 3 3 3 2 3 1
24 24 24 24 24 24 12
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Ph lc 4 M t tp lnh
Ph lc 4: M T TP LNH
1. ACALL addr11
Function: Absolute Call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected. Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following instruction, ACALL SUBRTN at location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC contains 0345H. Bytes: 2 Cycles: 2 Encoding: A10 A9 A8 1 0 0 0 1 A7 A6 A5 A4 A3 A2 A1 A0 Operation: ACALL (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC10-0) page address
2. ADD A,<src-byte>
Function: Add Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
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Example: The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH (10101010B). The following instruction, ADD A,R0 leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1. 2.1. ADD A,Rn
Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 1 r r r Operation: ADD (A) (A) + (Rn) 2.2. ADD A,direct
Bytes: 2 Cycles: 1 Encoding: 0 0 1 0 0 1 0 1 direct address Operation: ADD (A) (A) + (direct) 2.3. ADD A,@Ri
Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 1 1 i Operation: ADD (A) (A) + ((Ri)) 2.4. ADD A,#data
Bytes: 2 Cycles: 1 Encoding: 0 0 1 0 0 1 0 0 immediate data Operation: ADD (A) (A) + #data
3. ADDC A, <src-byte>
Function: Add with Carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and
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cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The following instruction, ADDC A,R0 leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1. 3.1. ADDC A,Rn
Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 1 r r r Operation: ADDC (A) (A) + (C) + (Rn) 3.2. ADDC A,direct
Bytes: 2 Cycles: 1 Encoding: 0 0 1 1 0 1 0 1 direct address Operation: ADDC (A) (A) + (C) + (direct) 3.3. ADDC A,@Ri
Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 1 1 i Operation: ADDC (A) (A) + (C) + ((Ri)) 3.4. ADDC A,#data
Bytes: 2 Cycles: 1 Encoding: 0 0 1 1 0 1 0 0 immediate data
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Operation: ADDC (A) (A) + (C) + #data
4. AJMP addr11
Function: Absolute Jump Description: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP. Example: The label JMPADR is at program memory location 0123H. The following instruction, AJMP JMPADR is at location 0345H and loads the PC with 0123H. Bytes: 2 Cycles: 2 Encoding: A10 A9 A8 0 0 0 0 1 A7 A6 A5 A4 A3 A2 A1 A0 Operation: AJMP (PC) (PC) + 2 (PC10-0) page address
5. ANL<dest-byte>,<src-byte>
Function: Logical-AND for byte variables Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following instruction, ANL A,R0 leaves 41H (01000001B) in the Accumulator. When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The following instruction, ANL P1,#01110011B clears bits 7, 3, and 2 of output port 1. 5.1. ANL A,Rn
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Bytes: 1 Cycles: 1 Encoding: 0 1 0 1 1 r r r Operation: ANL (A) (A) (Rn) 5.2. ANL A,direct
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 1 0 1 direct address Operation: ANL (A) (A) (direct) 5.3. ANL A,@Ri
Bytes: 1 Cycles: 1 Encoding: 0 1 0 1 0 1 1 i Operation: ANL (A) (A) ((Ri)) 5.4. ANL A,#data
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 1 0 0 immediate data Operation: ANL (A) (A) #data 5.5. ANL direct,A
Bytes: 2 Cycles: 1 Encoding: 0 1 0 1 0 0 1 0 direct address Operation: ANL (direct) (direct) (A) 5.6. ANL direct,#data
Bytes: 3 Cycles: 2 Encoding:

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0 1 0 1 0 0 1 1 direct address immediate data Operation: ANL (direct) (direct) #data
6. ANL C,<src-bit>
Function: Logical-AND for bit variables Description: If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0: MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN STATE ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7 ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG 6.1. ANL C,bit
Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 1 0 bit address Operation: ANL (C) (C) (bit) 6.2. ANL C,/bit
Bytes: 2 Cycles: 2 Encoding: 1 0 1 1 0 0 0 0 bit address Operation: ANL (C) (C) NOT (bit)
7. CJNE <destbyte>,<src-byte>, rel

Function: Compare and Jump if Not Equal. Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.
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The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant. Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence, CJNE R7, # 60H, NOT_EQ ; . . . . . . . . ;R7 = 60H. NOT_EQ: JC REQ_LOW ;IF R7 < 60H. ; . . . . . . . . ;R7 > 60H. sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to Port 1 is also 34H, then the following instruction, WAIT: CJNE A, P1,WAIT clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data changes to 34H.) 7.1. CJNE A,direct,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 0 1 direct address relative address Operation: (PC) (PC) + 3 IF (A) < > (direct) THEN (PC) (PC) + relative offset IF (A) < (direct) THEN (C) 1 ELSE (C) 0 7.2. CJNE A,#data,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 0 0 immediate data relative address Operation: (PC) (PC) + 3 IF (A) < > data THEN (PC) (PC) + relative offset IF (A) < data THEN (C) 1 ELSE (C) 0 7.3. CJNE Rn,#data,rel
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Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 1 r r r immediate data relative address Operation: (PC) (PC) + 3 IF (Rn) < > data THEN (PC) (PC) + relative offset IF (Rn) < data THEN (C) 1 ELSE (C) 0 7.4. CJNE @Ri,data,rel
Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 1 i immediate data relative address Operation: (PC) (PC) + 3 IF ((Ri)) < > data THEN (PC) (PC) + relative offset IF ((Ri)) < data THEN (C) 1 ELSE (C) 0
8. CLR A
Function: Clear Accumulator Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected Example: The Accumulator contains 5CH (01011100B). The following instruction, CLR A leaves the Accumulator set to 00H (00000000B). Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 0 0 Operation: CLR (A) 0
9. CLR bit
Function: Clear bit Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.
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Example: Port 1 has previously been written with 5DH (01011101B). The following instruction, CLR P1.2 leaves the port set to 59H (01011001B). 9.1. CLR C
Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 0 1 1 Operation: CLR (C) 0 9.2. CLR bit
Bytes: 2 Cycles: 1 Encoding: 1 1 0 0 0 0 1 0 bit address Operation: CLR (bit) 0
10.
CPL A
Function: Complement Accumulator Description: CPLA logically complements each bit of the Accumulator (ones complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected. Example: The Accumulator contains 5CH (01011100B). The following instruction, CPL A leaves the Accumulator set to 0A3H (10100011B). Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 0 1 0 0 Operation: CPL (A) NOT (A)
11.
CPL bit
Function: Complement bit Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.
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Example: Port 1 has previously been written with 5BH (01011101B). The following instruction sequence, CPL P1.1 CPL P1.2 leaves the port set to 5BH (01011011B). 11.1. CPL C Bytes: 1 Cycles: 1 Encoding: 1 0 1 1 0 0 1 1 10110011 Operation: CPL (C) NOT (C) 11.2. CPL bit Bytes: 2 Cycles: 1 Encoding: 1 0 1 1 0 0 1 0 bit address Operation: CPL (bit) NOT (bit)
12.
DA A
Function: Decimal-adjust Accumulator for Addition Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the loworder four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.
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Example: The Accumulator holds the value 56H (01010110B), representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B), representing the packed BCD digits of the decimal number 67. The carry flag is set. The following instruction sequence ADDC A,R3 DA A first performs a standard twos-complement binary addition, resulting in the value 0BEH (10111110) in the Accumulator. The carry and auxiliary carry flags are cleared. The Decimal Adjust instruction then alters the Accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the loworder two digits of the decimal sum of 56, 67, and the carry-in. The carry flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of 56, 67, and 1 is 124. BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the following instruction sequence, ADD A, # 99H DA A leaves the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the sum can be interpreted to mean 30 - 1 = 29. Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 1 0 0 Operation: DA -contents of Accumulator are BCD IF [[(A3-0) > 9] [(AC) = 1]] THEN (A3-0) (A3-0) + 6 AND IF [[(A7-4) > 9] [(C) = 1]] THEN (A7-4) (A7-4) + 6
13.
DEC byte
Function: Decrement Description: DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The following instruction sequence, DEC @R0 DEC R0 DEC @R0 leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.
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13.1. DEC A Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 1 0 0 Operation: DEC (A) (A) - 1 13.2. DEC Rn Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 1 r r r Operation: DEC (Rn) (Rn) - 1 13.3. DEC direct Bytes: 2 Cycles: 1 Encoding: 0 0 0 1 0 1 0 1 direct address Operation: DEC (direct) (direct) - 1 13.4. DEC @Ri Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 1 1 i Operation: DEC ((Ri)) ((Ri)) - 1
14.
DIV AB
Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case. Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The following instruction,
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DIV AB leaves 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV are both cleared. Bytes: 1 Cycles: 4 Encoding: 1 0 0 0 0 1 0 0 Operation: DIV (A)15-8 (A)/(B) (B)7-0
15.
DJNZ <byte>,<rel addr>
Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence, DJNZ 40H,LABEL_1 DJNZ 50H,LABEL_2 DJNZ 60H,LABEL_3 causes a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence, MOV R2, # 8 TOGGLE: CPL P1.7 DJNZ R2,TOGGLE toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin. 15.1. DJNZ Rn,rel Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 1 r r r relative address Operation: DJNZ
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(PC) (PC) + 2 (Rn) (Rn) - 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) (PC) + rel 15.2. DJNZ direct,rel Bytes: 3 Cycles: 2 Encoding: 1 1 0 1 0 1 0 1 direct address relative address Operation: DJNZ (PC) (PC) + 2 (direct) (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) (PC) + rel
16.
INC <byte>
Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The following instruction sequence, INC @R0 INC R0 INC @R0 leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively. 16.1. INC A Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 0 0 Operation: INC (A) (A) + 1 16.2. INC Rn Bytes: 1 Cycles: 1 Encoding:
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0 0 0 0 1 r r r Operation: INC (Rn) (Rn) + 1 16.3. INC direct Bytes: 2 Cycles: 1 Encoding: 0 0 0 0 0 1 0 1 direct address Operation: INC (direct) (direct) + 1 16.4. INC @Ri Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 1 i Operation: INC ((Ri)) ((Ri)) + 1
17.
INC DPTR
Function: Increment Data Pointer Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence, INC DPTR INC DPTR INC DPTR changes DPH and DPL to 13H and 01H. Bytes: 1 Cycles: 2 Encoding: 1 0 1 0 0 0 1 1 Operation: INC (DPTR) (DPTR) + 1
18.
JB bit,rel
Function: Jump if Bit set Description: If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding
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the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The following instruction sequence, JB P1.2,LABEL1 JB ACC. 2,LABEL2 causes program execution to branch to the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 0 0 0 0 0 bit address relative address Operation: JB (PC) (PC) + 3 IF (bit) = 1 THEN (PC) (PC) + rel
19.
JBC bit,rel
Function: Jump if Bit is set and Clear bit Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relativedisplacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. Example: The Accumulator holds 56H (01010110B). The following instruction sequence, JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (01010010B). Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 0 0 bit address relative address Operation: JBC (PC) (PC) + 3 IF (bit) = 1 THEN (bit) 0 (PC) (PC) +rel
20.
JC rel
Function: Jump if Carry is set

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Description: If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. Example: The carry flag is cleared. The following instruction sequence, JC LABEL1 CPL C JC LABEL 2 sets the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 0 0 0 0 0 relative address Operation: JC (PC) (PC) + 2 IF (C) = 1 THEN (PC) (PC) + rel
21.
JMP @A+DPTR
Function: Jump indirect Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected. Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL. MOV DPTR, # JMP_TBL JMP @A + DPTR JMP_TBL: AJMP LABEL0 AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 1 Cycles: 2 Encoding: 0 1 1 1 0 0 1 1 Operation: JMP
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(PC) (A) + (DPTR)
22.
JNB bit,rel
Function: Jump if Bit Not set Description: If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The following instruction sequence, JNB P1.3,LABEL1 JNB ACC.3,LABEL2 causes program execution to continue at the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 1 0 0 0 0 bit address relative address Operation: JNB (PC) (PC) + 3 IF (bit) = 0 THEN (PC) (PC) + rel
23.
JNC rel
Function: Jump if Carry not set Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set. The following instruction sequence, JNC LABEL1 CPL C JNC LABEL2 clears the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 1 0 0 0 0 relative address Operation: JNC (PC) (PC) + 2 IF (C) = 0 THEN (PC) (PC) + rel
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24.
JNZ rel
Function: Jump if Accumulator Not Zero Description: If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally holds 00H. The following instruction sequence, JNZ LABEL1 INC A JNZ LABEL2 sets the Accumulator to 01H and continues at label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 0 0 0 relative address Operation: JNZ (PC) (PC) + 2 IF (A) 0 THEN (PC) (PC) + rel
25.
JZ rel
Function: Jump if Accumulator Zero Description: If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally contains 01H. The following instruction sequence, JZ LABEL1 DEC A JZ LABEL2 changes the Accumulator to 00H and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 0 0 0 0 0 relative address Operation: JZ (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + rel
26.
LCALL addr16
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Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memory address space. No flags are affected. Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. After executing the instruction, LCALL SUBRTN at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0 Operation: LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC) addr15-0
27.
LJMP addr16
Function: Long Jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. Example: The label JMPADR is assigned to the instruction at program memory location 1234H. The instruction, LJMP JMPADR at location 0123H will load the program counter with 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 Operation: LJMP (PC) addr15-0
28.
MOV <destbyte>, <src-byte>

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Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed. Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). MOV R0,#30H ;R0 30H MOV A,@R0 ;A 40H MOV R1,A ;R1 40H MOV B,@R1 ;B 10H MOV @R1,P1 ;RAM (40H) 0CAH MOV P2,P1 ;P2 0CAH leaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2. 28.1. MOV A,Rn Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 1 r r r Operation: MOV (A) (Rn) 28.2. *MOV A,direct Bytes: 2 Cycles: 1 Encoding: 1 1 1 0 0 1 0 1 direct address Operation: MOV (A) (direct) * MOV A,ACC is not a valid Instruction. 28.3. MOV A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 1 i Operation: MOV (A) ((Ri)) 28.4. MOV A,#data
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Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 0 0 immediate data Operation: MOV (A) #data 28.5. MOV Rn,A Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 1 r r r Operation: MOV (Rn) (A) 28.6. MOV Rn,direct Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 1 r r r direct address Operation: MOV (Rn) (direct) 28.7. MOV Rn,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 1 r r r immediate data Operation: MOV (Rn) #data 28.8. MOV direct,A Bytes: 2 Cycles: 1 Encoding: 1 1 1 1 0 1 0 1 direct address Operation: MOV (direct) (A) 28.9. MOV direct,Rn Bytes: 2 Cycles: 2 Encoding:
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1 0 0 0 1 r r r direct address Operation: MOV (direct) (Rn) 28.10. MOV direct,direct Bytes: 3 Cycles: 2 Encoding: 1 0 0 0 0 1 0 1 direct address (source) direct address (destination) Operation: MOV (direct) (direct) 28.11. MOV direct,@Ri Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 1 1 i direct address Operation: MOV (direct) ((Ri)) 28.12. MOV direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 1 1 0 1 0 1 direct address immediate data Operation: MOV (direct) #data 28.13. MOV @Ri,A Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 0 1 1 i Operation: MOV ((Ri)) (A) 28.14. MOV @Ri,direct Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 1 1 i direct address Operation: MOV ((Ri)) (direct)
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28.15. MOV @Ri,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 1 i immediate data Operation: MOV ((Ri)) #data
29.
MOV <destbit>, <src-bit>
Function: Move bit data Description: MOV <dest-bit>,<src-bit> copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. Example: The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B). MOV P1.3,C MOV C,P3.3 MOV P1.2,C leaves the carry cleared and changes Port 1 to 39H (00111001B). 29.1. MOV C,bit Bytes: 2 Cycles: 1 Encoding: 1 0 1 0 0 0 1 0 bit address Operation: MOV (C) (bit) 29.2. MOV bit,C Bytes: 2 Cycles: 2 Encoding: 1 0 0 1 0 0 1 0 bit address Operation: MOV (bit) (C)
30.
MOV DPTR,#data16
Function: Load Data Pointer with a 16-bit constant Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte
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(DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Example: The instruction, MOV DPTR, # 1234H loads the value 1234H into the Data Pointer: DPH holds 12H, and DPL holds 34H. Bytes: 3 Cycles: 2 Encoding: 1 0 0 1 0 0 0 0 immed. data15-8 immed. data7-0 Operation: MOV (DPTR) #data15-0 DPH #data15-8 DPL #data7-0
31.
MOVC A,@A+<base-reg>
Function: Move Code byte Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higherorder bits. No flags are affected. Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive. REL_PC: INC A MOVC A,@A+PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. The INC A before the MOVC instruction is needed to get around the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead. 31.1. MOVC A,@A+DPTR Bytes: 1 Cycles: 2 Encoding: 1 0 0 1 0 0 1 1
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Operation: MOVC (A) ((A) + (DPTR)) 31.2. MOVC A,@A+PC Bytes: 1 Cycles: 2 Encoding: 1 0 0 0 0 0 1 1 Operation: MOVC (PC) (PC) + 1 (A) ((A) + (PC))
32.
MOVX <destbyte>,<src-byte>
Function: Move External Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why X is appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using R0 or R1. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence, MOVX A,@R1 MOVX @R0,A copies the value 56H into both the Accumulator and external RAM location 12H. 32.1. MOVX A,@Ri Bytes: 1
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Cycles: 2 Encoding: 1 1 1 0 0 0 1 i Operation: MOVX (A) ((Ri)) 32.2. MOVX A,@DPTR Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 0 0 Operation: MOVX (A) ((DPTR)) 32.3. MOVX @Ri,A Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 1 i Operation: MOVX ((Ri)) (A) 32.4. MOVX @DPTR,A Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 0 0 Operation: MOVX (DPTR) (A)
33.
MUL AB
Function: Multiply Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction, MUL AB will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared. Bytes: 1 Cycles: 4
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Encoding: 1 0 1 0 0 1 0 0 Operation: MUL (A)7-0 (A) X (B) (B)15-8
34.
NOP
Function: No Operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence, CLR P2.7 NOP NOP NOP NOP SETB P2.7 Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 0 0 Operation: NOP (PC) (PC) + 1
35.
ORL<dest-byte>,<src-byte>
Function: Logical-OR for byte variables Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the following instruction, ORL A,R0 leaves the Accumulator holding the value 0D7H (1101011lB).When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable
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computed in the Accumulator at run-time. The instruction, ORL P1,#00110010B sets bits 5, 4, and 1 of output Port 1. 35.1. ORL A,Rn Bytes: 1 Cycles: 1 Encoding: 0 1 0 0 1 r r r Operation: ORL (A) (A) (Rn) 35.2. ORL A,direct Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 1 direct address Operation: ORL (A) (A) (direct) 35.3. ORL A,@Ri Bytes: 1 Cycles: 1 Encoding: 0 1 0 0 0 1 1 i Operation: ORL (A) (A) ((Ri)) 35.4. ORL A,#data Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 0 immediate data Operation: ORL (A) (A) #data 35.5. ORL direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 0 1 0 direct address Operation: ORL (direct) (direct) (A)
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35.6. ORL direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 0 0 0 0 1 1 direct address immediate data Operation: ORL (direct) (direct) #data
36.
ORL C,<src-bit>
Function: Logical-OR for bit variables Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN P10 ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7 ORL C,/OV ;OR CARRY WITH THE INVERSE OF OV. 36.1. ORL C,bit Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 0 1 0 bit address Operation: ORL (C) (C) (bit) 36.2. ORL C,/bit Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 0 0 0 bit address Operation: ORL (C) (C) (bit)
37.
POP direct
Function: Pop from stack. Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.
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Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction sequence, POP DPH POP DPL leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H. At this point, the following instruction, POP SP leaves the Stack Pointer set to 20H. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 0 0 0 0 direct address Operation: POP (direct) ((SP)) (SP) (SP) - 1
38.
PUSH direct
Function: Push onto stack Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The following instruction sequence, PUSH DPL PUSH DPH leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Bytes: 2 Cycles: 2 Encoding: 1 1 0 0 0 0 0 0 direct address Operation: PUSH (SP) (SP) + 1 ((SP)) (direct)
39.
RET
Function: Return from subroutine Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.
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Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RET leaves the Stack Pointer equal to the value 09H. Program execution continues at location 0123H. Bytes: 1 Cycles: 2 Encoding: 0 0 1 0 0 0 1 0 Operation: RET (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1
40.
RETI
Function: Return from interrupt Description: RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its preinterrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. Example: The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RETI leaves the Stack Pointer equal to 09H and returns program execution to location 0123H. Bytes: 1 Cycles: 2 Encoding: 0 0 1 1 0 0 1 0 Operation: RETI (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1
41.
RL A
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Function: Rotate Accumulator Left Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RL A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 0 1 1 Operation: RL (An + 1) (An) n = 0 - 6 (A0) (A7)
42.
RLC A
Function: Rotate Accumulator Left through the Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. Example: The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The following instruction, RLC A leaves the Accumulator holding the value 8BH (10001010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 0 1 1 Operation: RLC (An + 1) (An) n = 0 - 6 (A0) (C) (C) (A7)
43.
RR A
Function: Rotate Accumulator Right Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RR A leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. Bytes: 1
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Cycles: 1 Encoding: 0 0 0 0 0 0 1 1 Operation: RR (An) (An + 1) n = 0 - 6 (A7) (A0)
44.
RRC A
Function: Rotate Accumulator Right through Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The following instruction, RRC A leaves the Accumulator holding the value 62 (01100010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 0 1 1 Operation: RRC (An) (An + 1) n = 0 - 6 (A7) (C) (C) (A0)
45.
SETB <bit>
Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions, SETB C SETB P1.0 sets the carry flag to 1 and changes the data output on Port 1 to 35H (00110101B). 45.1. SETB C Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 0 1 1 Operation: SETB (C) 1 45.2. SETB bit
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Bytes: 2 Cycles: 1 Encoding: 1 1 0 1 0 0 1 0 bit address Operation: SETB (bit) 1
46.
SJMP rel
Function: Short Jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it. Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction, SJMP RELADR assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H. Note: Under the above conditions the instruction following SJMP is at 102H. Therefore, the displacement byte of the instruction is the relative offset (0123H0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH is a oneinstruction infinite loop. Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 0 0 relative address Operation: SJMP (PC) (PC) + 2 (PC) (PC) + rel
47.
SUBB A,<src-byte>
Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The
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source operand allows four addressing modes: register, direct, register-indirect, or immediate. Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction, SUBB A,R2 will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by CLR C instruction. 47.1. SUBB A,Rn Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 1 r r r Operation: SUBB (A) (A) - (C) - (Rn) 47.2. SUBB A,direct Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 1 direct address Operation: SUBB (A) (A) - (C) - (direct) 47.3. SUBB A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 0 1 1 i Operation: SUBB (A) (A) - (C) - ((Ri)) 47.4. SUBB A,#data Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 0 immediate data Operation: SUBB (A) (A) - (C) - #data
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48.
SWAP A
Function: Swap nibbles within the Accumulator Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A leaves the Accumulator holding the value 5CH (01011100B). Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 0 0 Operation: SWAP (A3-0) (A7-4)
49.
XCH A,<byte>
Function: Exchange Accumulator with byte variable Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCH A,@R0 leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator. 49.1. XCH A,Rn Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 1 r r r Operation: XCH (A) ((Rn) 49.2. XCH A,direct Bytes: 2 Cycles: 1 Encoding: 1 1 0 0 0 1 0 1 direct address Operation: XCH (A) (direct)
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49.3. XCH A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 1 i Operation: XCH (A) ((Ri))
50.
XCHD A,@Ri
Function: Exchange Digit Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. Example: R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCHD A,@R0 leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 1 1 i Operation: XCHD (A3-0) ((Ri3-0))
51.
XRL <destbyte>,<src-byte>
Function: Logical Exclusive-OR for byte variables Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the instruction, XRL A,R0 leaves the Accumulator holding the value 69H (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to
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be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL P1,#00110001B complements bits 5, 4, and 0 of output Port 1. 51.1. XRL A,Rn Bytes: 1 Cycles: 1 Encoding: 0 1 1 0 1 r r r Operation: XRL (A) (A) XOR (Rn) 51.2. XRL A,direct Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 1 0 1 direct address Operation: XRL (A) (A) XOR (direct) 51.3. XRL A,@Ri Bytes: 1 Cycles: 1 Encoding: 0 1 1 0 0 1 1 i Operation: XRL (A) (A) XOR (Ri) 51.4. XRL A,@#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 1 0 0 immediate data Operation: XRL (A) (A) XOR #data 51.5. XRL direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 0 1 0 direct address
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Operation: XRL (direct) (direct) XOR (A) 51.6. XRL direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 1 0 0 0 1 1 direct address immediate data Operation: XRL (direct) (direct) XOR #data
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Giáo trình Vi điều khiển - Ths.Phạm Hùng Kim Khánh

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Giáo trình Vi điều khiển - Ths.Phạm Hùng Kim Khánh

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B GIO DC & O TO TRNG I HC K THUT CNG NGH THNH PH H CH MINH KHOA IN IN T --- oOo ---

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Tng quan v vi iu khin MCS-51

QUAN V VI IU KHIN MCS-51

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C cc ch ngh (Low-power Idle) v ch ngun gim (Power-down).

T2CON* TH0 TMP2 B REGISTER ALU TMP1 TL1 TH2*

PSW PSEN ALE EA RST INSTRUCTION REGISTER TIMINGAND CONTROL

OSC PORT1 DRIVER PORT3 DRIVER

Note: * for Timer 2 only

Hnh 1.1 S khi ca AT89C51

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AT89C51 gm c 40 chn, m t nh sau:

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P3.2 INT0 Ngt ngoi 0

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Gi tr C1, C2 = 30 pF 10 pF Hnh 1.3 S kt ni thch anh 2.2. nh th chu k my

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Hnh 1.4 Chu k lnh

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ROM4KB 0000h0FFFh RAM128byte 00h7Fh SFR 80h0FFh

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Kt ni phn cng khi thit k b nh ngoi m t nh sau:

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Hnh 1.8 Giao tip b nh chng trnh ngoi

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ADDRESS BUS DATA BUS

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Hnh 1.9 Giao tip b nh d liu ngoi

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ADDRESS BUS DATA BUS

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Tng quan v vi iu khin MCS-51

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WR (chn P3.7 v P3.6).