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Tn thnh vin
Nguyn Vn Cng
ng Ngc Hong
L Hu Vit
Cng vic
+ Tm hiu li LAB 1: Thit k
RegisterFile 32 by 32
+Tm hiu hot ng v thit k :
Khi Control, Khi dch tri, Khi
m rng
+ Slide: phn I.
+ Tm hiu li LAB2: Thit k b
tnh ton ALU.
+Tm hiu hot ng v thit k:
Thanh ghi PC, Khi JR_Control,
Cc khi Multiplexor
+ Slide: phn II 1,2.
+ Tm hiu li chng 4 sch COD
Tm hiu hot ng v thit k:
ALUControl, MIPS, Khi m
phng Stimulate
+ Slide: phn II3,III.
+ Bo co.
+ M phng lnh trn Quartus
ng gp
30%
30%
40%
NHM 28
Page 1
I.
1. Yu cu chung:
- Thit k b x l trung tm MIPS chu k n 32-bit thc hin cc lnh:
ADD, SUB, SLT, JR, LW, SW, BNE, XORI, J
- Cc cng logic khng c qu 4 ng vo, vi delay 50ps.
- Cc khi iu khin logic c th dng cu trc lnh behavioral.
2. Tp lnh:
-
Lnh loi R:
JR rs:
PC = Reg[rs].
NHM 28
Page 2
Lnh loi I:
Lnh JUMP:
NHM 28
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II.
NHM 28
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1. Program Counter:
- Thanh ghi thc hin nhim v tr ti lnh tip theo c thc hin.
- Cu to gm 32 D-FlipFlop
Code:
module PC_Register(PCout,PCin,reset,clk);
output [31:0] PCout;
input [31:0] PCin;
input reset,clk;
D_FF dff0(PCout[0],PCin[0],reset,clk);
D_FF dff2(PCout[2],PCin[2],reset,clk);
D_FF dff4(PCout[4],PCin[4],reset,clk);
D_FF dff6(PCout[6],PCin[6],reset,clk);
D_FF dff8(PCout[8],PCin[8],reset,clk);
D_FF dff10(PCout[10],PCin[10],reset,clk);
D_FF dff12(PCout[12],PCin[12],reset,clk);
D_FF dff14(PCout[14],PCin[14],reset,clk);
D_FF dff16(PCout[16],PCin[16],reset,clk);
D_FF dff18(PCout[18],PCin[18],reset,clk);
D_FF dff20(PCout[20],PCin[20],reset,clk);
D_FF dff22(PCout[22],PCin[22],reset,clk);
D_FF dff24(PCout[24],PCin[24],reset,clk);
D_FF dff26(PCout[26],PCin[26],reset,clk);
D_FF dff28(PCout[28],PCin[28],reset,clk);
D_FF dff30(PCout[30],PCin[30],reset,clk);
Endmodule
D_FF dff1(PCout[1],PCin[1],reset,clk);
D_FF dff3(PCout[3],PCin[3],reset,clk);
D_FF dff5(PCout[5],PCin[5],reset,clk);
D_FF dff7(PCout[7],PCin[7],reset,clk);
D_FF dff9(PCout[9],PCin[9],reset,clk);
D_FF dff11(PCout[11],PCin[11],reset,clk);
D_FF dff13(PCout[13],PCin[13],reset,clk);
D_FF dff15(PCout[15],PCin[15],reset,clk);
D_FF dff17(PCout[17],PCin[17],reset,clk);
D_FF dff19(PCout[19],PCin[19],reset,clk);
D_FF dff21(PCout[21],PCin[21],reset,clk);
D_FF dff23(PCout[23],PCin[23],reset,clk);
D_FF dff25(PCout[25],PCin[25],reset,clk);
D_FF dff27(PCout[27],PCin[27],reset,clk);
D_FF dff29(PCout[29],PCin[29],reset,clk);
D_FF dff31(PCout[31],PCin[31],reset,clk);
2. B nh lnh:
- B nh lnh nhn ng ra ca PC lm a ch ca lnh tip theo c
thc hin.
NHM 28
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3. Register File:
+ 32 thanh ghi 32 bit, ring thanh ghi u tin( R0) th lun mang gi tr 0.
+ C 2 ng vo chn thanh ghi c (Read Register 1 v Read Register 2) v 2
ng ra d liu (Read Data 1 v Dead Data 2)
+ C 1 ng vo chn thanh ghi ghi d liu (Write register) , 1 ng vo cho
php ghi (RegWrite) v1 ng vo d liu (Write Data) khi ghi vo file thanh
ghi.
S khi:
NHM 28
Page 7
Code:
module RegisterFile(RD1,RD2,WD,RR1,RR2,WR,RW,reset,clk); // RR : Read Register
input [4:0]RR1,RR2,WR;
// WR : Write Register
input [31:0]WD ;
// WD : Write Data
input RW,clk,reset;
// RW : RegWrite
output [31:0]RD1,RD2;
// RD : Read Data
wire [31:0]x;
// x : ng ra cua bo decoder5_32
wire[31:0]R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,R20,R21,
R22,R23,R24,R25,R26,R27,R28,R29,R30,R31;
decoder5_32 d(WR,x[31:0],RW);
// chn thanh ghi ch
mux32x32_32
m1(RD1,RR1,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18,R17,R16,R15,R14,R13,R1
2,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0);
// chn thanh ghi ngun Rs
mux32x32_32
m2(RD2,RR2,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18,R17,R16,R15,R14,R13,R1
2,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0);
// chn thah ghi ngun Rt
reg32bit r0(32'b0,R0[31:0],clk,reset,x[0]);
reg32bit r16(WD,R16[31:0],clk,reset,x[16]);
reg32bit r1(WD,R1[31:0],clk,reset,x[1]);
reg32bit r17(WD,R17[31:0],clk,reset,x[17]);
reg32bit r2(WD,R2[31:0],clk,reset,x[2]);
reg32bit r18(WD,R18[31:0],clk,reset,x[18]);
reg32bit r3(WD,R3[31:0],clk,reset,x[3]);
reg32bit r19(WD,R19[31:0],clk,reset,x[19]);
reg32bit r4(WD,R4[31:0],clk,reset,x[4]);
reg32bit r20(WD,R20[31:0],clk,reset,x[20]);
reg32bit r5(WD,R5[31:0],clk,reset,x[5]);
reg32bit r21(WD,R21[31:0],clk,reset,x[21]);
reg32bit r6(WD,R6[31:0],clk,reset,x[6]);
reg32bit r22(WD,R22[31:0],clk,reset,x[22]);
reg32bit r7(WD,R7[31:0],clk,reset,x[7]);
reg32bit r23(WD,R23[31:0],clk,reset,x[23]);
reg32bit r8(WD,R8[31:0],clk,reset,x[8]);
reg32bit r24(WD,R24[31:0],clk,reset,x[24]);
reg32bit r9(WD,R9[31:0],clk,reset,x[9]);
reg32bit r25(WD,R25[31:0],clk,reset,x[25]);
reg32bit r10(WD,R10[31:0],clk,reset,x[10]);
reg32bit r26(WD,R26[31:0],clk,reset,x[26]);
reg32bit r11(WD,R11[31:0],clk,reset,x[11]);
reg32bit r27(WD,R27[31:0],clk,reset,x[27]);
reg32bit r12(WD,R12[31:0],clk,reset,x[12]);
reg32bit r28(WD,R28[31:0],clk,reset,x[28]);
reg32bit r13(WD,R13[31:0],clk,reset,x[13]);
reg32bit r29(WD,R29[31:0],clk,reset,x[29]);
reg32bit r14(WD,R14[31:0],clk,reset,x[14]);
reg32bit r30(WD,R30[31:0],clk,reset,x[30]);
reg32bit r15(WD,R15[31:0],clk,reset,x[15]);
reg32bit r31(WD,R31[31:0],clk,reset,x[31]);
Cu to MIPS ALU:
+ 2 ng vo BusA v BusB 32
bit
+ 1 ng ra Output 32 bit
+ Cc c ng ra: zero,
overflow, carryout, negative
C zero: c set khi kt qu
bng 0
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#50 or03(x[2],out[8],out[9],out[10],out[11]);
#50 or04(x[3],out[12],out[13],out[14],out[15]);
#50 or05(x[4],out[16],out[17],out[18],out[19]);
#50 or06(x[5],out[20],out[21],out[22],out[23]);
#50 or07(x[6],out[24],out[25],out[26],out[27]);
#50 or08(x[7],out[28],out[29],out[30],out[31]);
or
or
nor
//Co carry
wire [2:0]y;
and #50 and3(y[0],(~AluControl[1]),cadd);
and #50and4(y[1],AluControl[1],csub);
or #50 or11(y[2],y[0],y[1]);
and
#50 and5(carry,y[2],(~AluControl[0]));
endmodule
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end
6'b001110 :
begin
NHM 28
1'bx;
1'b0;
1'bx;
1'b0;
=
1'b0;
1'b0;
1'b1; // cho phep thuc hien lenh branch
2'b01;
1'b0;
1'b0; // sign extend
1'b0;
1'b1; // Chon zero_extend 32 bit dua vao ALU
1'b0;
1'b1; // Cho phep ghi du lieu vao thanh ghi dich
=
1'b0;
1'b0;
1'b0;
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2'b11;
1'b0;
1'b1; // zero extend
// j - Jump
RegDst =
ALUSrc =
MemtoReg =
RegWrite =
MemRead
MemWrite =
Branch =
ALUop =
Jump
=
SignZero =
1'bx;
1'bx;
1'bx;
1'b0;
=
1'b0;
1'b0;
1'bx;
2'bxx;
1'b1;
1'bx;
RegDst =
ALUSrc =
MemtoReg =
RegWrite =
MemRead
MemWrite =
Branch =
ALUop =
Jump
=
SignZero =
1'b0;
1'b0;
1'b0;
1'b0;
=
1'b0;
1'b0;
1'b0;
2'b10;
1'b0;
1'b0;
end
default :
begin
end
endcase
endmodule
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7. ALU_Control_Unit :
-
Kt hp gi tr ca tn hiu iu khin ALUop t b iu khin trung tm v 6bit Function gii m t lnh to ra tn hiu iu khin ALUControl cho b
tnh ton ALU
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Code:
module ALU_Control_Unit(ALUControl,ALUop,Funct);
input [1:0]ALUop;
input [5:0]Funct;
output [1:0]ALUControl;
reg [1:0] ALUControl;
wire [7:0] ALUCtrl;
assign ALUCtrl = {ALUop,Funct};
always @(ALUCtrl)
casex (ALUCtrl)
8'b00xxxxxx: ALUControl = 2'b00;
// LW & SW
// BNE
// XORI
// ADD
// SUB
// SLT
default: ALUControl=2'b00;
endcase
endmodule
8. JR_Control_Unit:
-
Kt hp gi tr ca tn hiu iu khin ALUop t b iu khin trung tm v 6bit Function gii m t lnh to ra tn hiu JR_Control cho php thc hin
lnh JUMP REGISTER.
a ch ca lnh JumpRegister chnh l d liu trong thanh ghi Rs.
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Code:
module JR_Control_Unit(ALUop,Funct,JRControl);
input [5:0]Funct; // 6 bit function cua lenh
input [1:0] ALUop; // 2 bit ALU Opcode tu khoi dieu khien ALU
output JRControl; // dieu khien chon dia chi cho PC
reg JRControl;
wire [7:0]x;
assign x = {ALUop,Funct};
/* ALUop = 10 va function = 01000 => JRControl = 1
cac truong hop khac JRControl = 0 */
always @(x)
case (x)
8'b10001000: JRControl = 1'b1;
default: JRControl = 1'b0;
endcase
endmodule
9. B m rng du Extender:
-
Page 18
Dch tn hiu 32-bit qua tri 2 bit thc hin php nhn vi 4.
Code:
module Shiftleft2(out,in);
input [31:0]in;
output [31:0]out;
assign out = { in[29:0], 2'b0 };
endmodule
11. B Multiplexor:
-
Code:
module Mux_2to1(out,in1,in2,en); // en = 0: out = in1
input in1,in2,en;
output out;
module Mux_2x32to32(out,in1,in2,Sel);
wire a1,a2;
input [31:0]in1,in2;
and #50 and1(a1,nen,in1);
input Sel;
and #50 and2(a2,en,in2);
output [31:0]out;
not #50 not1(nen,en);
or #50 or1(out,a1,a2);
Mux_2to1 mux0(out[0],in1[0],in2[0],Sel);
endmodule
Mux_2to1 mux1(out[1],in1[1],in2[1],Sel);
Mux_2to1 mux2(out[2],in1[2],in2[2],Sel);
module Mux_2x5to5(out,in1,in2,en);
Mux_2to1 mux3(out[3],in1[3],in2[3],Sel);
input [4:0] in1,in2; // 2 ng vo 5 bit
Mux_2to1 mux4(out[4],in1[4],in2[4],Sel);
input en;
Mux_2to1 mux5(out[5],in1[5],in2[5],Sel);
output [4:0]out; // Ng ra 5 bit
Mux_2to1 mux6(out[6],in1[6],in2[6],Sel);
Mux_2to1 m4(out[4],in1[4],in2[4],en);
Mux_2to1 mux7(out[7],in1[7],in2[7],Sel);
Mux_2to1 m3(out[3],in1[3],in2[3],en);
Mux_2to1 mux8(out[8],in1[8],in2[8],Sel);
Mux_2to1 m2(out[2],in1[2],in2[2],en);
Mux_2to1 mux9(out[9],in1[9],in2[9],Sel);
Mux_2to1 m1(out[1],in1[1],in2[1],en);
Mux_2to1 mux10(out[10],in1[10],in2[10],Sel);
Mux_2to1 m0(out[0],in1[0],in2[0],en);
Mux_2to1 mux11(out[11],in1[11],in2[11],Sel);
endmodule
Mux_2to1 mux12(out[12],in1[12],in2[12],Sel);
NHM 28
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Mux_2to1 mux23(out[23],in1[23],in2[23],Sel);
Mux_2to1 mux24(out[24],in1[24],in2[24],Sel);
Mux_2to1 mux25(out[25],in1[25],in2[25],Sel);
Mux_2to1 mux26(out[26],in1[26],in2[26],Sel);
Mux_2to1 mux27(out[27],in1[27],in2[27],Sel);
Mux_2to1 mux28(out[28],in1[28],in2[28],Sel);
Mux_2to1 mux29(out[29],in1[29],in2[29],Sel);
Mux_2to1 mux30(out[30],in1[30],in2[30],Sel);
Mux_2to1 mux31(out[31],in1[31],in2[31],Sel);
endmodule
/************************************
************* KHAI BAO *************
************************************/
// KHAI BAO DIA CHI
wire [31:0] PCin,PC;
Page 20
wire JR_Control;
wire Bne_Control;
wire [1:0] ALU_Control;
/************************************
********* CAU TRUC MIPS ************
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/* BNE CONTROL */
assign Bne_shift_in = Extend;
Shiftleft2 Shift_bne( Bne_shift_out, Bne_shift_in);
Add_32bit Adder_bne( PC_4,
Bne_shift_out,,,
Bne_Address);
not #(50) notBNE(NotZero,Zero);
and #(50) andBNE(Bne_Control,Branch,NotZero);
Mux_2x32to32 Mux_BNE( PC_Bne,
PC_4,
Bne_Address,
Bne_Control);
/* JUMP CONTROL */
assign Jump_shift_in = {6'b0,Instruction[25:0]};
assign Jump_Address = {PC_4[31:28],Jump_shift_out[27:0]};
Shiftleft2 Shift_jump(Jump_shift_out,Jump_shift_in);
NHM 28
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III. M phng:
1. Tp lnh m phng:
a ch
( thp phn)
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
Lnh
M my
Lw $12,0x00($0)
Lw $5 , 0x00($0)
Lw $6 , 0x04($0)
Slt $7, $1, $2
Jr $0
.............
NHM 28
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NHM 28
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