( (DOC) Hu - NG D - N TH - C Hành MPLAB 8 Và MPLAB C18 Trên BKIT PIC - BKIT Hardwareclub)

[DOC] Hng dn thc hnh MPLAB 8 v MPLAB C18 trn BKIT PIC -...
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[DOC] Hng dn thc hnh MPLAB 8 v MPLAB C18 trn BKIT PIC
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Trang 1/2 1 2 > LinkBack 08-01-2013, 08:23 PM iu Chnh Xp Bi
#1 (permalink) Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
bs135
Administrator [DOC] Hng dn thc hnh MPLAB 8 v MPLAB C18 trn BKIT PIC
MC LC Phn 1 : Ci t v cu hnh software Bi 1 : Ci t MPLAB IDE 8.36 Bi 2 : Ci t compiler MPLAB C18 Bi 3 : To project trn MPLAB 8.36 v C18 3.01 Phn 2 : Lp trnh C vi PIC 18F4520 Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi 4 : Kho st cc ch dao ng 5 : Interrupt v ngt Timer 6 : Ma trn phm 7 : Chng rung cho ma trn phm 8 : LCD 16x2 v bn phm in thoi 9 : Qut led 7 on v led ma trn 10 : Giao tip ni tip SPI 11 : iu khin led 7 on v m trn bng SPI 12 : Qut 2 led ma trn bng SPI 13 : Giao tip ni tip I2C v DS1307 14 : Analog to Digital Converter ADC 15 : iu ch xung PWM 16 : Giao tip UART RS232 17 : Giao tip vi bn phm PS2 18 : Graphics LCD 128x64 19 : Giao tip SD Card bng SPI
__________________ BS
thay i ni dung bi: bs135, 15-02-2013 lc 07:29 PM
The Following 4 Users Say Thank You to bs135 For This Useful Post: InterMilan (12-01-2013), matxac_vtv (04-05-2013), thanh_nhan93 (28-01-2013), vipboy (01-02-2013)
08-01-2013, 08:37 PM #2 (permalink) Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
bs135
Administrator Bi 1 : Ci t MPLAB IDE 8.36
Bi 1 : Ci t MPLAB IDE 8.36

1.1 Gii thiu MPLAB IDE l phn mm c h tr bi Microchip, dng son tho code cho cc ng dng ca PIC. Hin ti, thng 8/2010 MPLAB IDE c phin bn 8.51. Trong ti liu ny ti chn phin bn 8.36 v n c kh nhiu li v cu hnh . Cc phin bn khc nh 8.43, bn c th khng chn cu hnh ban u nhng bn thn n c th t ng tm kim cc th vin cn
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thit trong qu trnh bin dch. Vi phin bn 8.36 chng ta phi cu hnh ton b cho IDE. 1.2 Ci t MPLAB IDE 8.36 Bc 1 : Double Click vo file setup trong th mc MPLAB IDE 8.36. Mn hnh Welcome s hin ra nh sau. Bn chn Next tip tc.
Hnh 1.1 : Welcome to MPLAB IDE 8.36 Bc 2 : Chn I accept the term of the license agreement v chn Next.
Hnh 1.2 : License Agreement Bc 3 : ch mc nh l ci t Complete v chn Next tip tc.
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Hnh 1.3 : Chn ci t complete Bc 4 : Chn ng dn ci t, ta nn mc nh l C:\Program Files\Microchip\
Hnh 1.4 : Chn ng dn ci t Bc 5 : Tip tc chn I accept cho Maestro License v C32 License.
Hnh 1.5 : Maestro License
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Hnh 1.6 : C32 License Bc 6 : Giao din sau tng kt li cc la chn ca bn, nhn Next tin hnh ci t. Nu mun hiu chnh bn nhn Back.
Hnh 1.7 : Bt u ci t
Hnh 1.8 : Ch ci t xong Bc 7 : Khi ci t xong MPLAB IDE s hi bn c cn ci Hi Tech khng. y l compiler C h tr cho MPLAB IDE, tuy nhin ta s khng dng compiler ny m s dng MPLAB C18. Bn chn No nhn Finish hon tt vic ci t MPLAB IDE.
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Hnh 1.9 : Ci t hon tt Thng bo di u xut hin, thng k cc ti liu hng dn i km. Cc ti liu ny u nm trong th mc ci t C:\Program Files\Microchip\
Hnh 1.10 : Cc ti liu hng dn __________________ BS

thay i ni dung bi: bs135, 10-01-2013 lc 05:42 AM
The Following 2 Users Say Thank You to bs135 For This Useful Post: InterMilan (12-01-2013), xuanbach05 (11-01-2013)
bs135
Administrator Bi 2 : Ci t compiler MPLAB C18
Bi 2 : Ci t compiler MPLAB C18

2.1 Gii thiu Khi ci t xong MPLAB IDE, compiler mc nh cho n l MPASM, dng dch project vit bng ASM sang file HEX. Mun vit chng trnh bng C, ta cn phi ci t thm 1 compiler khc c h tr cho chip PIC ang dng. Trong phn ny, ti th nghim trn vi iu khin PIC18F4520 v chn compiler C18 h tr cho lp trnh C chun. 2.2 Cc bc ci t Bc 1 : Double Click vo file MPLAB C18 V1.0.exe tin hnh ci t, mn hnh welcome ca MPLAB C18 s hin ra nh sau :
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Hnh 2.1 : Welcome MPLAB C18 Bc 2 : Chn ni lu tr cho cc file bin dch ca MPLAB C18, ta c th mc nh l C:\mcc18 .
Hnh 2.2 : Chn ng dn lu tr Bc 3 : Chn la cc thnh phn ca gi MCC18, thng thng ta s chn ht tt c cc gi trong compier C18.
Hnh 2.3 : Chn cc gi ci t Bc 4 : Nhn Next tin hnh ci t
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Hnh 2.4 : Ci t C18 Ch cho n khi ci t xong.
Hnh 2.5 : Ch ci t C18 Bc 5 : Nhn Finish kt thc ci t MPLAB C18.
Hnh 2.6 : Kt thc ci t C18 2.3 Cp nht ln C18 version 3.01 Phin bn m ta va ci t l C18 v1.0. cp nht ln v3.01, ta s double click v file MPLAB-C18-pgrade-doc-v3_01.exe. Mn hnh welcome s hin ra nh sau:
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Hnh 2.7 : Welcome C18 update Chn I Accept v nhn Next tip tc ci t.
Hnh 2.8 : License Agreement Cc ti liu h tr lp trnh cho compiler C18 i km.
Hnh 2.9 : Cc ti liu hng dn Chn th mc mc nh cho vic update (ging vi th mc ci t C18)
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mc nh cc thnh phn s c ci t, khng cn phi check thm.
Hnh 2.10 : Cc gi ci t C18 v3.01 Check chn thm cc option di y MPLAB IDE t ng cu hnh cc thng s tng thch vi phin bn C18 v3.01
Hnh 2.11 : Chn cu hnh update cho MPLAB IDE Chn Next tin hnh Update
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Hnh 2.12 : Tin hnh ci t Ch cho n khi hon tt.
Hnh 2.13 : Ch cho n khi hon tt Nhn Finish kt thc.
Hnh 2.14 : Ci t hon tt __________________ BS

The Following User Says Thank You to bs135 For This Useful Post: InterMilan (12-01-2013)
09-01-2013, 12:29 AM #4
bs135
Administrator Bi 3 : To project trn MPLAB 8.36 v C18 3.01
Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Pos
Bi 3 : To project trn MPLAB 8.36 v C18 3.01
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To 1 project ln u trn MPLAB kh phc tp. Ngi s dng cn phi cu hnh cho MPLAB kh nhiu. Tuy nhin hu ht cc thng s cu hnh ny s c lu li cho ln sau, chng ta ch cn phi thit lp 1 ln. Phn ny hng dn cch to 1 project n gin trn MPLAB cho chip 18F4520 v mch np PICKit2 trn board BKIT PIC. 3.1 To mi project Kch hot chng trnh MPLAB IDE 8.36 t biu tng Microchip trn mn hnh Desktop, ca s sau y s hin ra.
Hnh 3.1 : Mn hnh khi ng ca MPLAB IDE 8.36 Chn menu Project v chn New
Hnh 3.2 : To mi project Ca s sau y hin ra, bn t tn cho project khung Project Name v chn ng dn cho n khung Project Directory.
Hnh 3.3 : t tn v chn th mc lu tr Ca s lm vic ca project s hin ra bn tri nh hnh di y. Nu ca s project khng hin ra bn s chn menu View v chn Project.
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Hnh 3.4 : Ca s project Chn compile C18 cho project ny bng cch chn vo menu Project v chn Select Language Toolsuite.
Hnh 3.5 : Chn Language ToolSuite (Compiler) Chn Active Toolsuite l Microchip C18 Toolsuite. Cc ng dn ca cc chng trnh trong gi compiler cho C18 c cu hnh trong lc ci t C18 upgrade, bn khng cn phi chnh li. Cc gi ny u nm trong th mc C:\mcc18.
Hnh 3.6 : Chn compiler C18 3.2 Cu hnh cho chip Phn ny c nh hng i vi qu trnh dch v np cho chip. Chn menu Configure v chn Select Device chn chip.
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Hnh 3.7 : Select Device Giao din di y hin ra v bn chn cho ng chip m mnh ang dng. y ti chn chip PIC18F4520.
Nhn OK ng ca s ny li. Tip theo l vic la chn cu hnh thch anh v 1 s cu hnh khc. Bn vo li menu Configure v chn Configuration Bits
Hnh 3.8 : Configuration Bits Mn hnh bn cu hnh cho ch hot ng ca chip di y hin ra. Check b du chn Configuration Bits set in code bn c th thay i cc thng s. Thng s u tin l ch thch anh, ty vo mi loi chip v thch anh m chn la khc nhau. y ti s dng thch anh ngoi 12MHz nn s chn ch thch anh l HS (High Speed). Cc ch thch anh ca PIC18F4520 s c cp cc bi sau. PORTB bit 4-0 ch mt nh l cc chn analog. Khi khng s dng analog bn cn phi chnh sang ch Digital khi reset. Disable chc nng Low Voltage Programming (LVP - Np in p thp), mch PICKit2 khng h tr chc nng ny. Sau khi hon thnh bn check li Configuration Bits set in code v ng ca s ny li.
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Hnh 3.9 : Thit lp thch anh, PortB, LVP 3.3 To mi file v add th vin cho project Bc tip theo l to file source vit code. T toolbar bn c th chn New File hoc v menu File v chn New.
Hnh 3.10 : To mi source file Mt file mi c to ra vi tn mc nh l Untitled nh hnh di y.
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Hnh 3.11 : File mi c to ra Bn nhn v menu File v chn Save As lu li file ny. Ca s di y hin ra v bn chn ng dn lu cho chnh xc. Thng thng ta s lu trong th mc cha project hin ti cho d qun l.
Hnh 3.12 : Lu file trong th mc cha project Nhn Save lu file vi tn mi l main.c v ng ca s trn li. Bc tip theo l add file va mi lu (main.c) v th mc Source File ca project. Click chut phi vo Source File v chn Add Files
Hnh 3.13 : Add file vo Source Files Chn ng dn n file main.c v nhn Open.
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Hnh 3.14 : Browse ng dn n main.c File main.c s c add vo mc Source File ca project nh hnh bn di.
Hnh 3.15 : Add xong main.c cho Source Files Tip theo ta s add cc th vin cho project. u tin l Header Files. Cng tng t nh khi add file vo Source File, click chut phi v chn Add Files. Browse ng dn n C:\mcc18\h v chn file p18f4520.h hoc g tn file ny vo mc File name ri nhn Open.
Hnh 3.16 : Add Header File Add file vo mc Linker Script, browse ng dn n C:\mcc18\lkr v chn file 18f4520.lkr.
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Hnh 3.17 : Add file Linker Script Add file lib vo mc Library Files, 18f4520.lib ti th mc C:\mcc18\lib
Hnh 3.18 : Add Library File 3.4 Cu hnh cho qu trnh dch project Khi dch project, compiler cn 1 s file object ca n (chng hn nh c018i.o), ta cn phi ch ng dn tm kim cc file object ny cho compiler. i vi 1 s phin bn MPLAB, n t ng tm ng cc file ny. Tuy nhin i vi phin bn 8.36 ta cn phi ch nh ng dn tm kim. T menu Project, chn Build Option v chn Project.
Giao din Build Option hin ra, ti mc Show Directories for bn chn Include Search Path, chn New v Browse ng dn n C:\mcc18\h. Sau chnh sang Library Search Path v to mi 1 ng dn C:\mcc18\lib
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Hnh 3.19 : To ng dn cho include file
Hnh 3.20 : To ng dn cho Library File Nhn OK hon tt vic cu hnh ca qu trnh dch. 3.5 Vit code cho project Double Click vo file main.c v bt u vit code cho project. Ta vit 1 on code nh lm cho cc led ni vi PORTB ca vi iu khin sng xen k (PORTB = 0xAA)
Code:
#include <p18f4520.h> void main() { TRISB = 0x00; PORTB = 0xAA; while(1); }
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Hnh 3.21 : Double Click v main.c v vit code kim tra code vit c li hay khng bn vo menu Project v chn Build All hoc nhn t hp phm nng Ctrl F10. Nu khng c li thng bo BUILD SUCCEEDED s xut hin.
Hnh 3.22 : Bin dch thnh cng 3.6 Kt ni vi board Sau khi bin dch thnh cng, bn kt ni my tnh vi board np v chy th chng trnh. Vi mch BKIT PIC bn cm dy USB vo chn mch np, bt cng tt ngun v gt tt c cc switch ca SW2 ln ON kt ni mch np PICKit2.
Hnh 3.23 : Kt ni vi PICKit2 trn BKIT PIC Gt tt c cc switch ca SW1 ln ON enable nt Reset, Led PortB v chn thch anh ngoi.
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Hnh 3.24 : Enable Reset, Led v XTAL ngoi 3.7 Cu hnh mch np T menu Programmer chn Select Programmer v chn mch np tng ng l PICKit2. Mun chn mch np khc hoc kt ni vi mch np li bn phi chn li None ri sau mi chn li mch np.
Hnh 3.25 : Chn mch np thun tin cho qu trnh lp trnh, ta nn thit lp thm 1 s thng s cho mch np c th t ng np v chy chng trnh khi bin dch khng c li. lm c iu ny ta s chn Programmer v chn Settings.
Hnh 3.26 : Setting cho mch np Giao din sau hin ra v bn check chn Program after successful build (Np chng trnh khi bin dch thnh cng) v Run after a successful program (Chy chng trnh khi np thnh cng). Nhn OK kt thc.
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Hnh 3.27 : Cu hnh np v chy chng trnh By gi bn nhn li t hp phm Ctrl F10 (Build All), MPLAB s lm 1 lot cc thao tc nu khng c li : Dch chng trnh Np chng trnh Ko chn VDD ln mc cao th chn Reset v chng trnh bt u chy trn board.
Hnh 3.28 : Dch - Np - Chy chng trnh Hnh nh chng trnh chy trn board BKIT PIC nh sau :
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Hnh 3.29 : Chng trnh chy trn BKIT PIC __________________ BS

The Following 3 Users Say Thank You to bs135 For This Useful Post: InterMilan (12-01-2013), ninzaij (18-01-2013), xuanbach05 (11-01-2013)
10-01-2013, 04:38 AM #5 (permalink) Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
bs135
Administrator Bi 4 : Kho st cc ch dao ng
Bi 4 : Kho st cc ch dao ng
1.1 Gii thiu Dng PIC18F c 10 ch dao ng khc nhau, k hiu v tn gi ca chng nh sau: LP : Low Power Crystal , thch anh c tn s dao ng thp (khong vi chc kHz). XT : Crystal/ Resonator, thch anh/resonator c tn s trung bnh (di 4MHz). HS : High Speed Crystal/Resonator, thch anh/resonator c tn s cao (trn 4Mhz). HSPLL : High Speed Crystal/Resonator with Phase Locked Loop enabled, thch anh tn s cao vi b khuyt i PLL. RC : External Resistor/Capacitor with Fosc/4 output on RA6, dao ng RC ngoi,output vi tn s chia 4 chn RA6. RCIO : External Resistor/Capacitor with I/O on RA6, chn RA6 l I/O. INTIO1 : Internal Oscillator with Fosc/4 output on RA6 and I/O on RA7, dao ng ni, output chn RA6, input/output chn RA7 vi tn s Fosc/4 . 8. INTIO2 : Internal Oscillator with I/O on RA6 and RA7, dao ng ni vi RA6, RA7 l I/O. 9. EC : External Clock with Fosc/4 output, clock ngoi, RA6 l output tn s Fosc/4. 10. ECIO : External Clock with I/O on RA6, clock ngoi, RA6 l chn I/O. 1.2 Crystal v Resonator y l loi dao ng n gin nht. Resonator cn c tn gi khc l Ceramic Resonator. Hnh nh ca Crystal v Resonator nh hnh bn di. Cc loi dao ng LP, XT, HS, HSPLL s dng Crystal hoc Resonator. 1. 2. 3. 4. 5. 6. 7.
ch hot ng ny, Crystal/Resonator s c kt ni vi 2 chn OSC1 v OSC2 ca vi iu khin nh hnh di y. Khi dng Crystal, gi tr ca t in ph thuc vo tn s ca Crystal nh bng di y
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Bng 2 1 : Gi tr Capacitor cho Crystal Gi tr ca t in cng cao th dao ng cng n nh, nhng b li thi giai khi ng s lu hn. Khi dng Resonator, gi tr ca t in nh sau:
Bng 2 2 : Gi tr Capacitor cho Resonator Khi tn s resonator ln hn 3.5 MHz ta nn cu hnh l HS thay v XT. 1.3 External Clock Ngun dao ng clock ngoi c ni vo chn OSC1. c im ca loi dao ng ny l vi iu khin hot ng ngay khi c ngun cp (hoc thc dy t ch sleep) m khng cn tn thi gian khi ng (start-up time). i vi chip PIC18F th dao ng ny c 2 loi : EC : chn RA6 output vi tn s Fosc/4 (Fosc l tn s clock a vo chn OSC1). Chn output ny c th dng kim tra hoc lm chn clock cho 1 s ng dng (nh 1 tn hiu ng b). Trong ca s Configuration Bits, tn gi ca ch ny l EC-CLKOUT on RA6.
ECIO : chn RA6 truy xut nh 1 I/O bnh thng. Trong ca s Configuration Bits, tn gi ca ch ny l EC-Port on RA6.
1.4 Dao ng RC i vi 1 vi ng dng khng i hi chnh xc v nh thi cao th dao ng RC l 1 la chn tit kim. Do tn s dao ng ti chn OSC1 ph thuc vo in p cp, in tr, t in, nhit v thm ch l hng sn xut chip, nn tn s dao ng RC khng c chnh xc. Ch ny cng c 2 loi l RC (RC-CLKOUT on RA6, Port on RA7) : Clock out vi tn s chia 4 chn RA6 v RCIO (RC-Port on RA6, Port on RA7) : RA6, RA7 s dng nh I/O. 1.5 B khuch i tn s PLL PLL l 1 mch tch hp bn trong chip, c tc dng nng tn s input ln nhiu ln, nng cao tc thc thi chng trnh ca vi iu khin. B PLL c th c dng kt hp vi nhiu ch hot ng thch anh ca vi iu khin PIC. HSPLL : PLL khi dng vi ch HS c th nhn gp 4 ln tn s input. Khi tn s input ti a l 10Mhz, tn s khuch i t 40MHz. Trong ca s Configuration Bits tn gi ca ch ny l HS-PLL enabled freq = 4xFosc1. Trong
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ch ny bit PLLEN khng c tc dng. PLL v INTOSC : PLL cng c th c dng kt hp vi b dao ng ni, khi tn s khuch i c th t 32Mhz. Ch ny phi c thit lp bng phn mm, khng c option chn la trong ca s Configuration Bits. PLLEN bit dng kch hot ch ny. 1.6 B dao ng ni Gn tng t vi b dao ng External Clock, b dao ng ni (Internal Oscillator Block) cng c 2 ch , output tn s Fosc/4 chn RA6 v ch I/O chn ny. Tn s ca b dao ng ni c lp trnh software. Cc thanh ghi nh hng n tn s ny l OSCCON v OSCTUNE. b dao ng ni c 2 ngun clock, ngun clock 8MHz v ngun clock RC 31kHz. B ngun clock 8MHz s i qua 1 b chia (Prescaller) v cp clock cho thit b hot ng. Gi tr ca b chia ny c xc nh bi 3 bit IRCF2:IRCF0 trong thanh ghi OSCCON. Khi gi tr cc bit u l 0 th vic chn clock source da vo bit INTRC trong thanh ghi OSCTUN. Nu INTRC = 0 th tn s ly t clock source th 2, 31kHz. Ngc li tn s s l 8MHz/256 = 31.5kHz (b chia l 256 cho clock 8MHz). Khi tn s ca b dao ng ni l 4MHz hoc 8MHz (OSCCON<6:4> = 110 hoc 111) th n c th c s dng kt hp vi b PLL. kch hot b PLL ta phi set bit PLLEN thanh ghi OSCTUNE ln 1. 1.7 Demo Kit BKIT PIC c thit k dng switch gt kt ni vi thch anh (crystal) 20MHz, nn ta c th s dng ch thch anh ngoi khng PLL (PLL ch dng c vi thch anh nh hn 10MHz) hoc dng thch anh ni kt hp vi PLL. demo tn s cung cp cho chip, ta s vit chng trnh c 1s tng gi tr ca PORTB ln 1 n v. Mt cu lnh trong PIC chim 4 chu k dao ng. 1.7.1 Thch anh ngoi 20MHz Ta s dng 2 vng lp for to hiu ng delay. Vi chu k 20MHz ta phi m 5 000 000 chu k lnh (do 1 chu k lnh chim 4 chu k dao ng). Khi mun tnh ton chnh xc thi gian, ta phi dng cc cu lnh ASM. Khi vit bng ngn ng C, ta ch c th c lng gn ng. Cu lnh (for i=0 ; I < MAX_I ; i++) tn khong 4 chu k lnh : i++ tn 2 chu k lnh, i< MAX_I tn 2 chu k lnh, lnh gn i =0 ch thc hin 1 ln nn ta c th b qua. Vy hm to hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau:
Code:
void delay1s_20MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } } }
Nh cp trn, 1 vng for thc hin khong 4 chu k lnh nn tng s chu k lnh ca 2 vng for trn l (250 * 4) * (1250 *4) = 5 000 000. Hm main ta c th vit nh sau:
Code:
void main() { TRISB = 0x00; PORTB = 0x00; while(1) {
//setup PORTB is output //init value
PORTB++; Delay1s_20MHz(); } }
//increase PORTB //call delay 1s
Chnh ch thch anh trong ca s Configuration Bits l HS, PORTB l Digital (mc nh l analog), Disable chc nng np in p thp (LVP), dch v np chng trnh ta s thy gi tr PORTB tng dn sau 1s. Chnh ch thch anh sang ch LP hoc XT, dch v np li chng trnh bn s thy chng trnh khng chy hoc chy sai. Do vi thch anh 20MHz ta phi chn l HS nh datasheet ca PIC18F4520. 1.7.2 Thch anh ni 8MHz Cng tng t nh trn, ch thch anh ni 8MHz ta phi thc hin 2 000 000 chu k lnh. Hm to hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau:
Code:
void delay1s_8MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } }
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s dng c thch anh ni 8MHz, trc tin ta phi cu hnh l dng thch anh ni trong ca s Configuration Bits (chn INT RC Port on RA6, Port on RA7), sau vit code trong hm main la chn b Prescaller cho ngun clock 8MHz. Ta s set 3 bit <6:4> ca thanh ghi OSCCON ln 1. Hm main s vit nh sau:
Code:
void main() { TRISB = 0x00; PORTB = 0x00; OSCCON |= 0x70 while(1) {
//setup PORTB is output //init value //set bit <6:4> -> freq = 8MHz
PORTB++; Delay1s_8MHz(); } }
//increase PORTB //call delay 1s
1.7.3 Thch anh ni 8MHz v PLL Khi s dng thch anh ni 8MHz v b PLL nhn 4, tn s dao ng cp cho chip s l 32MHz, vy ta phi m 8 000 000 chu k lnh. Hm to hiu ng delay s nh sau:
Code:
void delay1s_8MHzPLL() { int i,j; for(i=0;i<500;i++) { for(j=0;j<1000;j++) { } } }
Hm main ngoi vic chn Prescaller cho clock ni ta phi set thm bit PLLEN (bit 6) trong thanh ghi OSCTUNE:
Code:
void main() { TRISB = 0x00; //setup PORTB is output PORTB = 0x00; //init value OSCCON |= 0x70 //set bit <6:4> -> freq = 8MHz OSCTUNE |= 0x40 //enable PLL while(1) { PORTB++; //increase PORTB Delay1s_8MHzPLL(); //call delay 1s } }
__________________ BS
The Following 2 Users Say Thank You to bs135 For This Useful Post: InterMilan (12-01-2013), xuanbach05 (11-01-2013)
bs135
Administrator Bi 5 : Interrupt v ngt Timer
Bi 5 : Interrupt v ngt Timer

2.1 Interrupt trong PIC Dng PIC18F4520 (2420, 2520, 4420) c nhiu ngun ngt (interrupt source) v 2 mc u tin ngt (high priority interrupt v low priority interrupt). Vector ngt c mc u tin cao c a ch 0x08 cn ngt c mc u tin thp c a ch 0x18. Khi hm phc v ngt qung cho ngt u tin thp ang xy ra, ngt u tin cao xy ra s tm dng ngt u tin thp v phc v cho ngt u tin cao.
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i vi 1 ngt, thng thng c 3 bit iu khin n: Flag bit : C bo hiu interrupt, khi flag bit c set, ngt s xy ra. Enable bit : Cho php ngt i vi cc ngt c mt n (maskabled interrupt) Priority bit : Thit lp u tin ngt, khi c set ngt s c mc u tin cao. c th thit lp mc u tin cho cc ngun ngt, ta phi enable chc nng u tin ngt bng cch set IPEN bit (Interrupt Priority Enable bit : RCON<7>). Khi IPEN = 1 : GIEH bit (INTCON<7>) s enable cc ngt c mc u tin cao, GIEL bit (INTCON<6>) s enable cc ngt c mc u tin thp. Khi ngt ton cc, Flag bit, Enable bit c set, ngt s c kch hot, con tr chng trnh s nhy ti a ch 0x08 hoc 0x18 ty theo ngt c thip lp l u tin cao (Priority bit l 1) hay u tin thp (Priority bit l 0). Khi IPEN = 0 : y l trng hp mc nh, disable chc nng u tin ngt (gi l ch compatibility mode). INTCON<6> lc ny l PEIE bit, enable hay disable cc ngt ngoi vi (peripheral interrupt). INTCON<7> lc ny l GIE bit, enable hay disable tt c cc ngun ngt. ch compatibility ny, tt c cc ngt s nhy n a ch 0x08. Khi cc ngun ngt c cng u tin, chng s cng nhy n 1 a ch ngt. Hm phc v ngt qung cn phi kim tra tt c cc c xc nh ngun ngt no ang gy ra ngt. C ngt cn c xa trnh hin tng ngt quy (recursive interrupt), vi iu khin s lp v tn trong hm ngt cho n khi trn stack. im ch quan trng trong thanh ghi INTCON l khi IPEN = 1 : INTCON<7> = 1 s enable tt c cc ngt c u tin cao nhng khi INTCON<7> = 0 n li disable tt c cc ngt, bao gm c ngt u tin thp. Mt ngt u tin thp ngoi vic thit lp GIEL (INTCON<6>) cn phi set lun c bit GIEH (INTCON<7>). 2.2 Gii thiu Timer0 Timer0 c 2 ch 16 bit hoc 8 bit. Clock cp cho timer 0 c th l clock ni hoc clock ngoi (ly t chn T0CKI). Ngoi ra Timer0 cn c b Prescaller chia tn s clock.
Hnh 2.1 : Thanh ghi iu khin T0CON Timer0 c iu khin bi thanh ghi T0CON. ngha cc bit trong thanh ghi ny nh sau: Bit 7 TMR0ON : Bt tt Timer 0. 1 : Bt Timer 0 . 0 : Tt Timer 0. Bit 6 T08BIT : Chn cu hnh cho Timer 0. 1 : Timer 16 bit. 0 : Timer 8 bit. Khi hot ng ch 16 bit, gi tr ca b nh thi (counter)/ b m Timer 0 c ghi vo 2 thanh ghi TMR0H v TMR0L. Ngc li, ch 8 bit, gi tr m c lu trong thanh ghi TMR0L. Bit 5 T0CS : Chn ngun clock cho Timer 0. 1 : Clock ngoi t chn T0CKI. 0 : Clock ni (Fosc/4). Bit 4 T0SE : Chn ch kch Timer 0 khi dng ngun ngoi. 1 : Timer 0 m ln khi c tn hiu t High sang Low chn T0CKI. 0 : Timer 0 m ln khi c tn hiu t Low sang High chn T0CKI. Bit 3 PSA : Bt/ Tt ch Prescaller cho Timer 0. 1 : Tt Prescaller. 0 : Cho php Prescaller. Bit 2 : 0 T0PS2 :T0PS0 : Chn gi tr Prescaller. 111 110 101 100 : : : : 1:256 011 : 1:16 1:128 010 : 1:8 1:64 001 : 1:4 1:32 000 : 1:2
Khi chn b Prescaller, tn s ca Timer 0 s b chia xung. V d thch anh dng cho mch l 20MHz, th tn s ca clock ni l Fosc/4 = 5MHz. Nu ta chn Prescaller l 1:2 th tn s m ca timer 0 l 2.5MHz. Khi Timer 0 m trn t FF :FF (ch 16 bit) hoc FF (ch 8 bit) ln 0, c TMR0IF s c bt ln 1 v gy ra ngt nu cc bit cho php ngt (ngt ton cc, ngt timer0) c set ln 1.
2.3 Lp trnh module Timer0 2.3.1 Hm init_timer0
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Trong phn ny, chng ta s khi to timer0 ch 16 bit, s dng clock ni v prescaller 1:2, ngt timer0 s c cu hnh l ngt u tin thp v sau mi 1ms s xy ra ngt 1 ln. Timer0 s m ln sau mi ln tch cc ca clock. Trong ch 16 bit, khi gi tr trong 2 thanh ghi TMR0H:TMR0L chuyn t FFFF sang 0000 s xy ra ngt, c TMR0IF s c bt ln 1. Mch BKIT PIC s dng thch anh 20MHz, nn clock ni cho timer0 s l 5MHz (timer0 s m 5 000 000 n v trong 1 giy). c c ngt 1ms ta s np cho thanh ghi TMR0H:TMR0L gi tr thp hn FFFF 5000 n v. V Timer0 c cu hnh s dng prescaller 1:2, nn con s ny s thp hn FFFF 2500 n v : 65535 2500 = 63035 = F63B. Vic np gi tr ny cho thanh ghi TMR0 s c thc hin trong hm phc v ngt qung timer0_isr. enable ngt timer 0, ta cn set bit ngt ton cc GIE, set bit ngt thp GIEL, set bit enable timer 0 TMR0IE v c ngt timer 0 TMR0IF trong thanh ghi INTCON. Cu hnh u tin ngt timer 0 l ngt thp bng cch clear bit TMR0IP trong thanh ghi INTCON2. Hm ngt timer0 s c khi to nh sau:
Code:
void init_timer0() { counter0 = 0;//counter for virtual timer timer0_flag = 0;//flag for virtual timer T0CON = 0x00;//timer0 16bit mode, internal RCONbits.IPEN = 1;//enable interrupt priority INTCON2bits.TMR0IP = 0;//low interrupt priority INTCONbits.GIE = 1;//enable global interrupt INTCONbits.GIEL =1;//enable low priority interrupt INTCONbits.TMR0IE = 1;//enable timer0 interrupt INTCONbits.TMR0IF = 1;//force timer0 interrupt } clock,
2.3.2 Hm timer0_isr Hm ny c gi khi ngt Timer0 xy ra. i vi tt c cc ngt ca PIC, ta cn phi xa c ngt trc tin v n khng c t ng xa bng phn cng. Trong hm phc v ngt qung Timer0 ny ta nn tt n i bng cch xa bit TMR0ON, np li gi tr cho 2 thanh ghi m Timer0. cui hm phc v ngt qung ta s bt cho Timer0 m ln (set bit TMR0ON). Gi tr trong 2 thanh ghi m Timer0 s tng dn theo mi xung nhp ca clock, v khi t gi tr FFFF n s xy ra ngt ln tip theo.
Code:
void timer0_isr() { INTCONbits.TMR0IF = 0; T0CONbits.TMR0ON = 0; TMR0H = 0xF6; TMR0L = 0x3B; //CODE HERE virtual_timer(); //END CODE T0CONbits.TMR0ON = 1; }
//clear interrupt flag //stop timer 0 //reconfig timer 0 //1ms interrupt
//start timer 0
gi c hm ny, ta phi dng thm ch th pragma dch 1 hm ti a ch nht nh v ch th pragma interrupt dch hm ny l dng hm interrupt. Timer0 c cu hnh l ngt u tin mc thp (low priority interrupt), nn khi ngt xy ra, con tr chng trnh s nhy ti a ch 0x18. Chng trnh hin thc lnh gi hm timer0_isr c hin thc cui file main.c
Code:
#pragma code #pragma interrupt low_interrupt_isr void low_interrupt_isr() { if(INTCONbits.TMR0IF == 1) timer0_isr(); } #pragma code _vector_low = 0x18 void _vector_low(void) { low_interrupt_isr();
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} #pragma code void main() { while(1) { } }
Vi ch th u tin, hm vecter_low s c dch ti a ch 0x18, l a ch vector ngt thp. Do 2 a ch ngt ca PIC l 0x08 cho ngt cao v 0x18 cho ngt thp cch gn nhau, nn ta s ch t tht t lnh ti 2 a ch ny. Trn y ch t 1 lnh gi hm low_interrupt_isr ti a ch 0x18. Trong hm ny ta s kim tra ngt ang xy ra c phi l Timer0 hay khng bng cch xt bit th 2 ca thanh ghi INTCON (bit TMR0IF) trc khi gi hm timer0_isr. Hm main() by gi phi thm ch th #pragma code compiler dch hm ny 1 vng nh khc trong vng code memory. Ngoi Timer0, PIC cn c thm 3 Timer na. V cc chc nng c bn nh Timer0, chng cn c thm 1 vi chc nng c bit khc.
2.4 Gii thiu Timer 1 Khc vi Timer0 l 1 interrupt, Timer1 l 1 Peripheral Interrupt. V vy c th enable cho ngt Timer1, ta phi set bit PEIE. Tng t vi Timer0, Timer1 cng c chc nng counter t clock ngoi ( chn T13CKI) v tng gi tr ln 1 mi khi c clock cnh ln chn T13CKI. Khi chn clock ngoi, T1SYNC bit dng chn ch cho counter, l Ansynchronous Counter hoc Synchronous Counter. Hai loi counter ny u tng gi tr m ln 1 sau mi ln tch cc ca clock, im khc bit ca chng nm kt ni phn cng. Synchronous Counter cp clock cho tt c cc flip flop trong khi Ansynchronous Counter ch cp clock cho flip flop u tin.
Hnh 2.2: Synchronous Counter
Hnh 2.3 : Ansynchronous Counter Bn cnh , Timer1 cn c th m ln nh dao ng ngoi 2 chn T1OSI v T1OSO. Ngi ta thng dng thch anh 32,768kHz v bin Timer1 thnh 1 b Real Time Clock (ng h thi gian thc) . S kt ni nh sau:
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Hnh 2.4 : Timer1 Osillator s dng c chc nng ny ta cn phi set bit T1OSCEN. Chc nng c bit cui, Timer1 l ngn clock cho module CCP. Chi tit v module ny s c trnh by Bi 16. Hai timer cn li thng c dng tch hp vi cc module khc, Timer2 (c thm b Post Scaller) s c dng cho module PWM Bi 14 v Timer3 s c dng cho module Capture Bi 16. 2.5. Ngt Timer1 v Timer2 Timer 1: Khi khng c interrupt priority : GIE enable all interrupts, PEIE/GIEL enable all peripheral interrupt. Khi c interrupt priority : GIE enable all high interrupt, nhng nu bng 0 s disable all interrupts. Nn nu set timer 1 l interrupt mc thp th phi set GIEH ln enable, sau set tip GIEL enable interrupt u tin thp. Nu timer1 mc cao th phi set GIEH enable high interrupt v set PEIE v timer1 l peripheral interrupt. Timer 2: Timer 8 bit, gi tr trong thanh ghi TMR2 khi bng vi PR2 s set c TMR2IF v gy ra ngt. Prescaller l b chia tn s input. (1,4,16) PostScaller l b chia tn s output. (1-16) Timer 2 l peripheral interrupt.
Code:
void init_timer2() { T2CON = 0x00; //postscaller 1 T2CONbits.T2OUTPS0 = 1; T2CONbits.T2OUTPS1 = 0; T2CONbits.T2OUTPS2 = 0; T2CONbits.T2OUTPS3 = 0; //prescaller 4 T2CONbits.T2CKPS0 = 1; T2CONbits.T2CKPS1 = 0; } void init_timer2_interrupt() { //enable timer 2 interrupt PIE1bits.TMR2IE = 1; //enable interrupt priority RCONbits.IPEN = 1; //enable timer1 low priority interrupt IPR1bits.TMR2IP = 0; INTCONbits.GIEH = 1; INTCONbits.GIEL = 1; //force into interrupt TMR2 = 0x00; PR2 = 200; PIR1bits.TMR2IF = 1; } #pragma code vector_high = 0x08 void _vector_high(void) { _asm goto timer1_isr_high _endasm 2.6. Code mu
Download ti y __________________ BS
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15-01-2013, 08:13 PM
#7 (permalink) Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
bs135
Administrator Bi 6 : Ma trn phm
Bi 6 : Ma trn phm
3.1 Khi nim Ma trn phm l cch kt ni cc phm theo hng v ct. Cch kt ni nh vy s tit kim c ti nguyn ca vi iu khin. V d di y l cch mc ma trn phm 4x4 :
Hnh 3.1 : Ma trn phm 4x4 Ta c 16 phm v 8 tn hiu iu khin. Nu mc 16 phm ny nh cc phm n, ta phi cn n 16 tn hiu iu khin. 3.2 Gii m ma trn phm Ta xt 1 ma trn phm 2x2 nh hnh di y:
Hnh 3.2 : Ma trn 2x2 Khi phm A c nhn th in p ti C1 s bng R1. Nh vy nu ban u ti C1 v C2 l mc cao, R1 l mc thp v R2 l mc cao, th khi phm A c nhn, in p ti C1 (ban u l mc cao) s b ko xung mc thp.
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Hnh 3.3 : Phm A c nhn Tng t nu phm B c nhn th C2 s b ko xung mc thp. xc nh 2 phm C v D c c nhn hay khng, ta s nng in p ti R1 ln mc cao, ko in p ti R2 ln mc cao (chuyn hng tch cc).
Hnh 3.4 : Phm D c nhn Nh vy, xc nh v tr ca phm no c nhn, ta s duyt qua tt c cc hng v xt cc phm hng . Quy c tn hin DEACTIVE l mc 1 v tn hin ACTIVE l mc 0, tng bc gii m ma trn phm nh sau: Cho tn hiu cc ct l DEACTIVE Ci t tn hin ti cc ct l INPUT Cho tn hin cc hng l DEACTIVE Ci t tn hiu cc hng l OUTPUT Lp qua cc hng Cho tn hiu hng ang xt l ACTIVE. Xt cc ct trong hng ang cho ACTIVE, ct no c tn hiu ACTIVE l phm tng ng c nhn. Kt thc vng lp 3.3 Vit chng trnh Chng trnh dnh cho gii m ma trn gm 2 phn : phn u dng khi to cc chn vi iu khin, phn 2 l duyt qua cc hng v ct xc nh phm no c nhn. File key_matrix.h nh ngha cc hng s v 2 hm dng trong ma trn phm:
Code:
#define TRIS_BUTTON TRISC #define PORT_BUTTON PORTC #define MAX_COL 4 #define MAX_ROW 4 extern char key_data[]; extern char key_code[]; void init_key_matrix(); void scan_key_matrix();
key_code l 1 mng 16 phn t tng ng vi 16 phm, nu phm c nhn th phn t tng ng c gi tr l 1.
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key_data cng l 1 mng 16 phn t, ta c th dng lu thng tin cho phm v tr th nht, chng hn nh data hin th s 0 (0x3F) trn led 7 on. 3.3.1 Khi to ma trn phm Theo nh s kt ni ma trn phm hnh 4.1, ta s khi to cc hng l output v cc ct l input. Quy nh DEACTIVE l mc 1 nn ta s gn gi tr ban u ca PORTC l 0xFF.
Code:
void init_key_matrix() { TRIS_BUTTON = 0x0F; //C3-C0:input C7-C4:output PORT_BUTTON = 0xFF; }
3.3.2 Qut ma trn phm Nh cp gii thut trn, ta s ln lt duyt qua tt c cc hng bng cch xut tn hiu ca hng l ACTIVE (mc 0) ri xt tng ct.
Code:
void scan_key_matrix() { int i,j; //loop all rows for(i=0;i<MAX_ROW;i++) { //pull down row i PORT_BUTTON &= ~(1<<(7-i)); //loop all cols for(j=0;j<MAX_COL;j++){ //reset key code key_code[i*MAX_ROW+j] = 0; //when col j is activated if((PORT_BUTTON & (1<<j)) == 0){ //set key code key_code[i*MAX_ROW+j] = 1; } } //pull up row i PORT_BUTTON |= (1<<(7-i)); } }
3.3.3 Hm main file main.c, ta s include file key_matrix.h c th gi c cc hm ca n. Bin key_code c extern file key_matrix.h nn ta cng c th truy xut file main.c.
Code:
#include "KEY_MATRIX\\key_matrix.h" void main() { int i; TRISB = 0x00; //init PORTB for output PORTB = 0x00; //initial value init_key_matrix(); while(1) { scan_key_matrix(); for(i=0;i<16;i++) { if(key_code[i] != 0) { PORTB = i; break; } } } }
Code chi tit ca ma trn phm cc bn c th tham kho Bai7. __________________ BS

thay i ni dung bi: bs135, 16-01-2013 lc 06:08 PM
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bs135
Administrator Bi 7 : Chng rung cho ma trn phm
Bi 7 : Chng rung cho ma trn phm

4.1 Nguyn l chng rung
Hnh 4.1 : Hin tng rung phm Hnh trn minh ho mc in p ca 1 phm nhn tch cc mc 0, trng thi bnh thng, in p vi iu khin nhn vo l 5V cn khi nhn l 0V. Tuy nhin, do rung c hc ca phm, ti thi im va nhn xung, in p s khng n nh trong 1 khong thi gian, trc khi n nh mc 0V. Hiu tng ny gi l rung phm. Mc d khong thi gian in p mc 0 trong giai on rung phm l nh nhng cng vi iu khin nhn c. V vy khi ta xt nu in p l 0 th gi hm func() th hm ny s c gi rt nhiu ln, l iu m ta khng mong mun. khc phc hin tng rung phm, c 2 hng gii quyt : dng phn cng v phn mm. V gii php phn cng : thay v mc n gin nh kit th nghim ny (xem li s ), ta c th dng thm t in hn ch vic thay i in p t ngt, s nguyn l nh sau:
Hnh 4.2 : Chng rung bng phn cng s trn, khi khng nhn l mc 1, khi nhn l mc 0. Phm nhn trn tch cc mc 0. Mch trn cn gi l mch RC. Nu nt nhn c 2 cc (3 chn), ta c th chn gii php dng mch RS flip flop, y l mch phn cng chng rung tt nht, s nguyn l nh sau:
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Hnh 4.3 : Chng rung bng phn cng (tt) V gii php phn mm : Ta s nh k c tn hiu t nt nhn, cho n khi no chng trng nhau n ln th mi x l. Hnh di y minh ho trong trng hp 2 ln l 0 th mi xc nhn l phm c nhn v mi x l tc v m ta mong mun.
Hnh 4.4 : Chng rung bng phn mm Khong thi gian gia 2 ln c l khong 10ms, ta s hin thc hm c ny v gi n trong timer. Gii thut n gin x l chng rung c th hin thc nh sau:
Code:
previous_key = current_key; current_key = Port_key; If(previous_key == current_key) effective_key = current_key;
Trong : previous_key : bin lu gi tr phm trc . current_key : bin lu gi tr phm hin ti. Port_key : Port ca vi iu khin kt ni vi phm. y chng ta gi hm c ma trn phm tr v gi tr ca phm c nhn. effective_key : gi tr phm hp l (gi tr trong giai on n nh) tng tnh chnh xc, ta c th dng nhiu bin previous_key lu li cc gi tr v so snh nhiu ln. on code trn ch so snh trng nhau 2 ln. 4.2 Kt ni phn cng S nguyn l ca phm trong kit ny nh sau :
Hnh 4.5 : S kt ni nt nhn Phm nhn ny tnh cc mc 0, c kt ni kh n gin, nn ta s dng phn mm chng rung. Ta s dng 3 bin so snh 2 ln trng nhau, 2 ln lin tip cch nhau 10ms. Trong trng hp nhn 1 phm, ta s dng bin TimeOutForKeyPress xc nh thi gian tch cc tip theo. Bin ny s quan trng trong trng hp ta vit 1 ng dng chng hn nh son tho vn bn. Nu khng c bin ny qun l, nu ta th trong 1s c ti 100 ln tch cc.
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4.3 Vit chng trnh Module ny c 2 hm nh sau : void initKey() : Khi ng cc thng s ban u void getKey() : Hm ny c gi trong timer0, dng qut phm. void SubKeyProcess() : Hm ny hin thc tc v bn cn thc hin khi nhn phm. kit th nghim ny, cc nt nhn c ni thnh dng ma trn v c ni vi PORTC nn ta nh ngha thm u file Key.c :
Code:
#define KEY_PORT
PORTC
4.3.1 Hm initkey()
Code:
void initKey() { KeyReg0 = 0x00; KeyReg1 = 0x00; KeyReg2 = 0x00; KeyReg3 = 0x00; }
Trong KeyReg0, KeyReg1, KeyReg2 dng lu 3 ln lin tip. Khi 3 bin ny bng nhau, bin KeyReg3 mi c cp nht. Bin KeyReg3 l gi tr hp l ca phm nhn. 4.3.2 Hm getKey() Hm ny c chia lm 2 phn, phn u l chng rung phm dng 2 ln so snh trng nhau. Phn th 2 x l khi 1 phm c , phi sau 1 khong thi gian TimeOutForKeyPress mi c tch cc.
Code:
void getKey(){ KeyReg2 = KeyReg1; KeyReg1 = KeyReg0; KeyReg0 = read_matrix_key();// Cho phep nut nhan nao duoc tich cuc. if ((KeyReg1 == KeyReg0) && (KeyReg1 == KeyReg2)) { TimeOutForKeyPress --; if (TimeOutForKeyPress == 0) { KeyReg3 = 0x00; } if (KeyReg2 != KeyReg3) { KeyReg3 = KeyReg2; if (FlagFirstTimeKeyPress == 1)// Day la lan dau phim duoc nhan. { TimeOutForKeyPress = 100; SubKeyProcess(); FlagFirstTimeKeyPress = 0; } else { if (KeyReg2 == 0x00) FlagFirstTimeKeyPress = 1; else { TimeOutForKeyPress = 100; SubKeyProcess(); } } } } }
4.4. Code mu Download code mu ti y __________________ BS
18-01-2013, 07:31 PM #9 (permalink)
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bs135
Administrator Bi 8 : LCD 16x2 v bn phm in thoi
Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
Bi 8 : LCD 16x2 v bn phm in thoi

5.1 Chc nng cc chn ca LCD
Hnh 5.1 : LCD 16x2 LCD thng s dng 14 chn, ch 16 chn khi cn iu khin n nn. Chc nng ca cc chn nh sau:
5.2 Kt ni mn hnh LCD
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Hnh 5.2 : Kt ni mn hnh LCD Hnh trn m t kt ni LCD vi ch 16 chn, 2 chn K v A dng kt ni vi n nn.
5.3 Cc vng nh ca LCD 5.3.1 Display Data Ram (DDRAM) Lu tr m k t hin th ra mn hnh. M ny ging vi m ASCII. C tt c 80 nh DDRAM. Vng hin th tng ng vi ca s gm 16 nh hng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch ch bng cch s dng lnh dch , khi ca s hin th s dch em li hiu ng dch ch.
Hnh 5.3 : Vng nh DDRAM 5.3.2 Character Generator Ram (CGRAM) Lu tr tm mu k t do ngi dng nh ngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* mang gi tr ty nh 0 hay 1).
Hnh 5.4 : Vng nh CGRAM 5.3.3 B nh CGROM B nh dng lu tr cc k t hin th trn LCD. Cc gi tr lu trong b nh ny nh sau:
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Hnh 5.5 : Vng nh CGROM Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin th ang bt u t v tr u tin (hng th nht hin th d liu ca nh t 0x00 n 0x0f, hng th hai hin th d liu ca nh t 0x40 n 0x4f, y l v tr home). Gi tr ca nh 0x07 l 0x43 (k t C), ca nh 0x08 l 0x45 (k t E). Chng ta mun hin th ch gi hng th hai, gi s c s hin th ang v tr home. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta phi nh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k t CGRAM th nht. Lc ny gi tr ca nh 0x47 l 0x00 hoc 0x08 (v tr ca mu k t CGRAM th nht ). 5.4 Cc lnh c bn ca LCD truyn lnh cho LCD th chn RS = 0, khi cc tn hin trn D0-D7 c xem l lnh. ngha ca cc lnh iu khin LCD nh sau:
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I/D 1 = Increment (by 1) 0 = Decrement (by 1) RL 1 = Shift right 0 = Shift left S 1 = Display shift on 0 = Display shift off DL 1 = 8-bit interface 0 = 4-bit interface D 1 = Display on 0 = Display off N 1 = Display in two lines 0 = Display in one line U 1 = Cursor on 0 = Cursor off F 1 = Character format 5x10 dots 0 = Character format 5x7 dots B 1 = Cursor blink on 0 = Cursor blink off D/C
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1 = Display shift 0 = Cursor shift
5.5 Kt ni LCD vi vi iu khin LCD c 2 ch 8 bit v 4 bit. ch 8 bit, ta dng ton b 8 chn D0-D7 giao tip. ch 4 bit, ta ch dng 4 bit cao D4-D7 giao tip vi LCD. D liu gi cho LCD ch ny bao gm 4bit cao gi trc, sau s n 4bit thp. S kt ni 2 ch nh sau:
Hnh 5.6 : Kt ni LCD vi vi iu khin Nu mun tit kim chn, R/W c th ni xung GND. ch 4bit th 4 bit thp ca LCD c th ni xung GND. 5.6 Khi to LCD Qu trnh khi to LCD ch 8 bit nh sau:
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Hnh 5.7 : Khi to LCD 8 bit Qu trnh khi to ch 4 bit nh sau:
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Hnh 5.8 : Khi to LCD 4 bit 5.7 Kt ni phn cng LCD c kt ni vi Port B ca vi iu khin PIC nh sau:
Trch:
LED_BACKLIGHT = PortB.0 PIN_RS : PortB.1 PIN_RW : PortB.2 PIN_EN : PortB.3 D4 : PortB.4 D5 : PortB.5 D6 : PortB.6 D7 : PortB.7 5.8 Vit chng trnh & 5.9 Cc hm c bn qu trnh iu khin LCD hiu qu, ta nh ngha 1 s hm c bn nh sau: Hm delay: trung bnh PIC thc hin 5 lnh mt 1us vi thch anh 20Mhz.
Code:
void lcd_delay(int time) { while(--time); }
Hm ghi d liu ra LCD:

Code:
//Ghi 4 bit void lcd_write_4bits(unsigned char dat) {
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RW(WRITE); //ko chn RW xung 0 EN(SET); //set chn Enable ln 1 LCD_DATA_OUT(dat & 0xF0); //Gi data ra lcd_delay(10); EN(CLR); //ko chn Enable xung 0 lcd_delay(10); } //Ghi 1 byte : ghi 4 bit 2 ln void lcd_write_cmd(unsigned char cmd){ lcd_wait_busy(); RS(CMD); lcd_write_4bits(cmd); lcd_write_4bits(cmd << 4); }
Mt s macro trong file lcd.h, v d nh:

Code:
#define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) ) //Nu x = 1 th thc hin lnh LCD_PORT |=0x02, x=0 th thc hin LCD_PORT &=0xFD.
5.10 Khi to LCD ch 4 bit

Code:
void init_lcd() { lcd_delay(15000); RS(CMD); lcd_write_4bits(0x03 lcd_delay(4100); lcd_write_4bits(0x03 lcd_delay(100); lcd_write_4bits(0x03 lcd_write_4bits(0x02 lcd_write_cmd(0x28) lcd_write_cmd(0x0C); lcd_write_cmd(0x06); }
//1 //2 << 4); << 4); << 4); << 4); ; //3 //4 //5 //6 //7 //8 //9 //10 //11
ngha cc lnh trn nh sau: Lnh 1 : gi hm lcd_delay(15000) delay 15ms. Lnh 2 : ko chn RS (ni vi LCD_PORT ti bit 1) xung 0. Lnh ny c nh ngha l 1 macro trong file lcd.h: #define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) ) CMD c define l 0 nn lnh RS(CMD) s c iu kin (x) l false v s thc hin phn th 2 ca lnh trn : LCD_PORT & 0xFD (ko bit 1 xung 0 : 1111 1101). Lnh 3 : thc hin trng thi u tin sau khi ch 15ms, ghi D7 D6 D5 D4 = 0011. Cc chn ny c ni vi 4 bit cao ca vi iu khin nn ta phi dch tri gi tr 0x03 4 bit. Lnh 4 : delay khong 41ms. Lnh 5,6,7,8 : Thc hin cc trng thi 2,3 v 4. Sau lnh 7 th LCD chuyn sang ch 4 bit, v gi 1 byte, ta s gi 2 ln 4 bit cao trc ri ti 4 bit thp. Lnh 9 : gi hm lcd_write_cmd ghi 4 bit 2 ln, gi tr 0x28 tng ng vi N = 1 (hin th trn 2 hng ca LCD) v B = 0 (font nh dng 5x7 im). Lnh 10 : thc hin lnh display on (xem thm trong bng lnh), D = 1. Lnh 11 : thc hin lnh entry set mode, 0x06 tng ng vi ch dch phi tng dn. 5.11 Xo mn hnh Hm ny ch n gin l gi lnh clear mn hnh lcd (xem thm trong bng lnh ca LCD).
Code:
void lcd_clear() { lcd_write_cmd(0x01); lcd_goto_xy(0, 0); }
5.12 Thit lp v tr con tr Hm ny thit lp v tr bt u xut d liu trn mn hnh LCD 2 hng 16 ct. hin thc hm ny ta phi tnh c a ch tng ng vi to (row,col) v dng lnh SET DDRAM ADDRESS (bit 7 ca lnh ny bng 1).
Code:
char lcd_goto_xy(unsigned char row, unsigned char col) { unsigned char addr = 0x00; if(col >= 20 || row >= 4)
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return FALSE; if(row < 2) { addr = (row * addr = 0x80 | } else { addr = (row * addr = 0x94 | } lcd_write_cmd(addr); current_row = row; current_col = col; return TRUE; }
0x40) + col; (addr & 0x7F);
0x40) + col; (addr & 0x7F);
5.13 In k t ra mn hnh Hm ny nhn thng s l 1 k t v hin th k t ra mn hnh LCD. Vic hin thc hm ny kh n gin, ta ch cn ko chn RS xung 0 l LCD s hiu cc bit D7-D4 l d liu.
Code:
void lcd_print_char(unsigned char dat) { lcd_wait_busy(); //find next position if(current_row == 0 && current_col == 16) lcd_goto_xy(1,0); if(current_row == 1 && current_col ==16) lcd_goto_xy(0,0); RS(DAT); //RS = 0 lcd_write_4bits(dat); lcd_write_4bits(dat << 4); current_col ++; //update new position }
T nhng hm c bn ny, bn c th hin thc thm cc hm xut 1 string hay 1 gi tr s ra mn hnh LCD. Code chi tit c th xem thm file nh km. 5.14 Thit lp bn phm in thoi Tm tt : bn phm 4x4 c nh cc k t s (0-9) v ch (A,B,C,D,*,#) s l cc phm chc nng m phng theo bn phm in thoi. Cc trng thi cng nh thng tin s c hin th trn mn hnh LCD. lm c bi ny cc bn cn c nhng hm v qut ma trn phm (trong th mc button_matrix) cng nh xut ra LCD (trong th mc lcd). Trc ht bn cn phi bit qua bi qut ma trn phm. Trong Button.c chng ta c hm button_process(void); Hm ny c gi nh k trong timer kim tra xem c nt no c nhn khng.Hm read_matrix_key(void) khi khng c nt no c nhn, n s tr v gi tr 0. Khi c nt nhn n s tr v gi tr t 1-16 ty theo v tr ca nt nhn. Vic kim tra ny c thc hin nhiu ln v chng ta s ch x l n khi c t nht 3 ln c gi tr ging nhau (theo nguyn l chng rung, c thm bi chng rung cho phm). Bi th 2 cn bit l bi v xut lcd. Trong lcd.c h tr cho bn sn cc hm ghi ln lcd (Tham kho thm trong lcd.h). Chng ta bt u bng vic to mt project mi vi nhng thit lp ph hp. copy th mc button_matrix, lcd, timer, interrupt vo ni cha chng trnh hon chnh project mi. Thm nhng file .h trong cc th mc ny vo main.c. To th mc Phone v cha cc file phone.c, phone.h . add vo project. Cc s kin v trng thi ca chic in thoi ca chng ta s c x l chnh trong file phone.c ny. Include file .h ca button_matrix v lcd. nh hnh: trc ht chng ta nh hnh li v tr v chc nng ca tng nt. V thc hin c chc nng nhn tin cng nh gi in nn mi nt t 0-9 c thm cc chc nng ring. Ta khai bo mt mng lu gi nhng gi tr m ta mun nt nhn c th thc hin.
Code:
unsigned char key[16][5] = {
'0',' ',0,0,0, '1','.',',',0,0, '2','a','b','c',0, '3','d','e','f',0, '4','g','h','i',0, '5','j','k','l',0, '6','m','n','o',0, '7','p','q','r','s', '8','t','u','v',0, '9','w','x','y','z', '*',0,0,0,0, '#',0,0,0,0, 'A',0,0,0,0, 'B',0,0,0,0, 'C',0,0,0,0,
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'D',0,0,0,0};
y c cc nt c nhiu k t (7-p-q-r-s) cng c nt c t k t (1-.) nn thun tin ta to thm mt mng cha gi tr l s k t c s dng ca nt :
Code:
unsigned char limit_key[16]={2,3,4,4,4,4,4,5,4,5,1,1,1,1,1,1};
By gi coi li trong button.c c hm qut ma trn phm. Tuy nhin, gi tr tr v ca hm ny l v tr ca cc nt trn bn phm (vd:1=1,2=2,3=3,A=4). Ta s cn phi chuyn i sang mt h khc thun tin trong vic lp trnh thng qua mt mng sau:
Code:
unsigned char convert_key[16]={ 1,2,3,12,4,5,6,13,7,8,9,14,10,0,11,15};
Chng trnh chnh ca chng ta l hm Phone() c gi lin tc trong hm main(). Hm ny u tin s xt bin ActiveKey xem c nt nhn no c nhn khng . Khi c nt nhn th s c mt chuyn i nh
Code:
KeyPress = convert_key[ActiveKey-1];
V bin KeyPress ny chnh l gi tr chng ta x l chnh. Bin PhoneStatus cha gi tr ca ca cc trng thi ca in thoi. Cc trng thi chnh l i (WAIT_STATUS), gi in (ENTERING_NUMBER_STATUS, CALLING_STATUS, ENDCALL_STATUS), nhn tin (MESS_STATUS, TYPING_MESS_STATUS, SENDING_STATUS, ENDSEND_STATUS). Vi mi trng thi ta x l nt C l quay li, D l xa k t, A l enter ty theo quy nh mi ngi. Tip theo chng ta x l nt nhn ti mi trng thi. Ti trng thi i, nu nhp vo l s th s ch hin s key[KeyPress][0]. Cn nu trong ch nhn tin th nu nh phm c nhn lp li trong khong thi gian timeout th coi nh s chuyn k t ngay ti nt :
Code:
KeyMessIndex = (KeyMessIndex +1)%(limit_key[KeyPress]); lcd_putChar(key[KeyPress][KeyMessIndex]);
, nu khng th in k t mi.:
Code:
KeyMessIndex = 1; lcd_putChar(key[KeyPress][KeyMessIndex]);
Download code mu Ti y __________________ BS
21-01-2013, 08:55 PM #10 ( permalink) Tham gia ngy: Sep 2008 Bi gi: 336 Thanks: 151 Thanked 363 Times in 160 Posts
bs135
Administrator Bi 9 : Qut led 7 on v led ma trn
Bi 9 : Qut led 7 on v led ma trn

6.1 iu khin led 7 on v led ma trn. 6.1.1 Cu to Led 7 on LED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp. Mi on l mt led, kt hp tt/sng ca cc led ny hin th s m chng ta hiu c.
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Hnh 6 1 Led 7 on LED 7 on c hai loi l Common Anode v Common Cathode, tng ng cc LED ni chung Anode hay ni chung Cathode. Mch th nghim BKIT PIC s dng loi Common Anode.
Hnh 6.1 : S nguyn l led 7 on 6.1.2 Cu to led ma trn LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct.
Hnh 6 3. Led ma trn Mi im c hai LED tng ng vi hai mu. Cc LED trn cng mt hng ni chung Anode, cc LED cng mu trn cng mt ct ni chung Cathode.
Hnh 6 4 S nguyn l led ma trn 6.1.3 Nguyn l qut LED hin th 1 led 7 on, ta cn 8 ng tn hiu gi d liu cho n. Nh vy, vi 8 led 7 on, theo kt ni bnh thng, ta cn tng cng 64 ng tn hiu thp sng 8 led cng lc. Vic ny rt tn ti nguyn v phn cng. khc phc, ngi ta dng k thut qut led. Cc ng d liu ca cc led s c ni vi nhau.
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Hnh 6 5 Kt ni khi qut led 7 on Vi k thut qut led ny, ti 1 thi im, ch c 1 led sng. Ti thi im t1 ch c led 1 sng, ti thi im t2 = t1 + t0 ch c led 2 sng, khi t0 rt nh, mt ngi khng th nhn bit c nhp nhy gia 2 ln lun chuyn, v s c cm gic l 2 n sng cng lc. Thng th t0 ny phi nh hn 1/24 giy, tc l trong mt giy s c nhiu hn 24 ln lun chuyn gia cc led. Bng m t qu trnh qut Led 7 on:
Tng t i vi led ma trn, ta dng 16 ng tn hiu iu khin hai mu led v 8 ng tn hiu tch cc dng (ROW). Ti mi thi im ch c mt dng led ma trn c hin th d liu.
Hnh 6 6 Nguyn l qut led ma trn 6.2 S kt ni mch
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Hnh 6-7 S kt ni led 7 on v led ma trn Mc ch ca bi ny l mi ngi lm quen vi led 7 on v led ma trn cho nn cc led 7 on v led ma trn c kt ni theo kiu song song, cc chn d liu v iu khin led c gn trc tip vi chn vi iu khin PIC, v vy chng trnh s n gin v d thc hin hn.
6.3 Xy dng chng trnh 6.3.1 tng hin thc c th hin thc gii thut qut led chng ta cn s dng ti b inh thi(timer) v ngt qung thit lp thi gian qut. V d chng ta qut 1 led vi tn s 50Hz(ngha l led sng 50 ln/giy) nh vy ta cn cu hnh cho timer l c sau 1000ms/50 = 20ms th ngt 1 ln v trong hm x l ngt ta s a d liu ra cho led. Nu s led nhiu hn th ta ch cn ly tn s chun cho mi led nhn vi s lng led. V d nu qut cng luc 8 led 7 on vi tn s mi led l 50Hz th tn s ngt ca timer l 8*50 = 400Hz. 6.3.2 Cc hm phc v qut led 2.6.3.1 Hm qut led 7 on
Code:
void display_led7(void) { PORTE = 0; PORTD = led7_buffer[index_led7]; PORTE = 1 << index_led7; index_led7 = (index_led7 + 1) % 3; }
Theo s nguyn l PORTD l port a d liu ra led 7 on v PORTE l port chn led( y chng ta c 3 led 7 on).Trc mi ln xut led, ta cn phi tt tt c cc led trnh trng hp d liu c c a vo led c chn tip theo,hay ngc li d liu mi c a vo led trc . 2.6.3.2 Hm qut led ma trn
Code:
void display_ledmatrix(void) { PORTA = 0; PORTB = green_buffer[index_matrix]; PORTC = red_buffer[index_matrix]; PORTA = 1 << index_matrix; index_matrix = (index_matrix + 1) % 8; }
Theo s nguyn l, PORTA l port la chn led, PORTB v PORTC tng ng l cc d liu xanh v ca led ma trn, cch qut vn ging vi vic qut led 7 on.
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i vi vic qut led ta nn to ra nhng mng buffer tin cho vic xut d liu v cp nhp chng, cng vi vic hin thc 1 s hm cp nhp buffer nh update_led7_buffer(), update_green_bugffer(), update_red_buffer() chng trnh ca chng ta tr nn thn thin, trong sng, n gin hn rt nhiu v ph hp vi vic pht trin ln thnh nhng bi kh hn nh chy ch hay cc hiu ng led river. __________________ BS
Trang 1/2 1 2 > Ti Trc | Ti K Quyn vit bi Bn Bn Bn Bn khng khng khng khng th th th th gi ch mi gi tr li gi file nh km sa bi vit ca mnh
BB code is M Mt ci ang M [IMG] ang M HTML ang Tt Trackbacks are M Pingbacks are M Refbacks are M Forum Rules
Mi gi GMT. Hin ti l 03:18 PM Lin h - Lu Tr - Ln trn BKIT Hardware Club forum Powered by: vBulletin Copyright 2000-2013, Jelsoft Enterprises Ltd.
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( (DOC) Hu - NG D - N TH - C Hành MPLAB 8 Và MPLAB C18 Trên BKIT PIC - BKIT Hardwareclub)

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( (DOC) Hu - NG D - N TH - C Hành MPLAB 8 Và MPLAB C18 Trên BKIT PIC - BKIT Hardwareclub)

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[DOC] Hng dn thc hnh MPLAB 8 v MPLAB C18 trn BKIT PIC -...

BKIT Hardwareclub > Document - Study > PIC

Tn ti khon Mt khu Lch Bi gi hm nay

Trang 1/2 1 2 > LinkBack 08-01-2013, 08:23 PM iu Chnh Xp Bi

Bi 1 : Ci t MPLAB IDE 8.36

Hnh 1.2 : License Agreement Bc 3 : ch mc nh l ci t Complete v chn Next tip tc.

Hnh 1.3 : Chn ci t complete Bc 4 : Chn ng dn ci t, ta nn mc nh l C:\Program Files\Microchip\

Hnh 1.5 : Maestro License

Hnh 1.10 : Cc ti liu hng dn __________________ BS

Bi 2 : Ci t compiler MPLAB C18

Hnh 2.3 : Chn cc gi ci t Bc 4 : Nhn Next tin hnh ci t

Hnh 2.4 : Ci t C18 Ch cho n khi ci t xong.

Hnh 2.5 : Ch ci t C18 Bc 5 : Nhn Finish kt thc ci t MPLAB C18.

mc nh cc thnh phn s c ci t, khng cn phi check thm.

Hnh 2.12 : Tin hnh ci t Ch cho n khi hon tt.

Hnh 2.13 : Ch cho n khi hon tt Nhn Finish kt thc.

Hnh 2.14 : Ci t hon tt __________________ BS

Bi 3 : To project trn MPLAB 8.36 v C18 3.01

Hnh 3.10 : To mi source file Mt file mi c to ra vi tn mc nh l Untitled nh hnh di y.

Hnh 3.19 : To ng dn cho include file

#include <p18f4520.h> void main() { TRISB = 0x00; PORTB = 0xAA; while(1); }

Hnh 3.29 : Chng trnh chy trn BKIT PIC __________________ BS

void delay1s_20MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } } }

void main() { TRISB = 0x00; PORTB = 0x00; while(1) {

//setup PORTB is output //init value

//increase PORTB //call delay 1s

void delay1s_8MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } }

void main() { TRISB = 0x00; PORTB = 0x00; OSCCON |= 0x70 while(1) {

//increase PORTB //call delay 1s

void delay1s_8MHzPLL() { int i,j; for(i=0;i<500;i++) { for(j=0;j<1000;j++) { } } }

Bi 5 : Interrupt v ngt Timer

2.3 Lp trnh module Timer0 2.3.1 Hm init_timer0

//clear interrupt flag //stop timer 0 //reconfig timer 0 //1ms interrupt

} #pragma code void main() { while(1) { } }

Hnh 2.2: Synchronous Counter

key_code l 1 mng 16 phn t tng ng vi 16 phm, nu phm c nhn th phn t tng ng c gi tr l 1.

void init_key_matrix() { TRIS_BUTTON = 0x0F; //C3-C0:input C7-C4:output PORT_BUTTON = 0xFF; }

Code chi tit ca ma trn phm cc bn c th tham kho Bai7. __________________ BS

Bi 7 : Chng rung cho ma trn phm

previous_key = current_key; current_key = Port_key; If(previous_key == current_key) effective_key = current_key;

4.4. Code mu Download code mu ti y __________________ BS

Bi 8 : LCD 16x2 v bn phm in thoi

5.2 Kt ni mn hnh LCD

1 = Display shift 0 = Cursor shift

Hnh 5.7 : Khi to LCD 8 bit Qu trnh khi to ch 4 bit nh sau:

void lcd_delay(int time) { while(--time); }

Hm ghi d liu ra LCD:

//Ghi 4 bit void lcd_write_4bits(unsigned char dat) {

Mt s macro trong file lcd.h, v d nh:

5.10 Khi to LCD ch 4 bit

void lcd_clear() { lcd_write_cmd(0x01); lcd_goto_xy(0, 0); }

0x40) + col; (addr & 0x7F);

0x40) + col; (addr & 0x7F);

unsigned char key[16][5] = {

unsigned char limit_key[16]={2,3,4,4,4,4,4,5,4,5,1,1,1,1,1,1};

unsigned char convert_key[16]={ 1,2,3,12,4,5,6,13,7,8,9,14,10,0,11,15};

KeyMessIndex = (KeyMessIndex +1)%(limit_key[KeyPress]); lcd_putChar(key[KeyPress][KeyMessIndex]);

Download code mu Ti y __________________ BS

Bi 9 : Qut led 7 on v led ma trn

Hnh 6 6 Nguyn l qut led ma trn 6.2 S kt ni mch

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