Khoa CNTT

Bo mon Ky thuat May tnh

Pham Tng Hai oan Minh Vng Phan nh The Duy

Ti liu tham kho

) Digital Logic Design Principles, N. Balabanian & B. Carlson John Wiley & Sons Inc., 2004 ) Digital Design, 3rd Edition, J.F. Wakerly, Prentice Hall, 2001 ) Digital Systems, 5th Edition, R.J. Tocci, Prentice Hall, 1991

Logic Design 1 - Chapter 5

Chng 5.

Logic Design 1 - Chapter 5

Dn nhp
) i vi mch t hp, cc tn hiu ng ra ti 1 thi im nht nh ch ph thuc vo cc tn hiu ng vo ti thi im m khng ph thuc vo lch s ca cc tn hiu ng vo trong qu kh ) C nhng trng hp ngi ta mong mun ng ra ca mch s khng ch ph thuc vo cc tn hiu ng vo hin hnh m cn ph thuc vo trng thi ca mch ti thi im cc tn hiu ng vo c gi n ) Trng thi ca mch ti 1 thi im nht nh th li ph thuc vo lch s ca cc tn hiu ng vo trong qu kh ) Cn phi c c ch cho php lu tr thng tin truyn ti bi chui cc tn hiu ng vo trong qu kh
Logic Design 1 - Chapter 5 4

Cc nh ngha & khi nim c bn

) Mt mch s c gi l mch tun t (sequential circuit) nu cc ng ra ca n ti 1 thi im nht nh l hm ca c gi tr cc ng vo ti thi im hin hnh v ca chui gi tr cc ng vo trong qu kh ) Cn c b nh (memory) lu tr qu kh ca cc ng vo ) Cn n cc mch c bit c th s dng nh cc cell (thng gi l primitive cell) lu tr qu kh gn ca 1 ng vo ) Bng cch kt ni cc memory cell ni trn kt hp vi vic s dng cc mch t hp c th gii quyt bi ton t ra cho mt mch tun t
Logic Design 1 - Chapter 5

) M hnh Mealy

) M hnh Moore

Cc nh ngha
) Vn thc o cho qu kh ? ) Cc kh khn do tn hiu xut hin khng ng thi, thi gian tr ca cng khc nhau, v.v ) Cn n mt h thng nh thi (timing) cho cc mch tun t ) Ngi ta s dng xung ng h (clock) nh thi ) Clock l tn hiu c dng 1 chui xung tun hon ) Cc thuc tnh quan trng ca tn hiu clock
Duty cycle Tn s/chu k clock Thi im tch cc dc cnh n nh tn s v dng sng
6

Logic Design 1 - Chapter 5

Mch ci (Latch) & Flip-flop

) Phn tch hot ng ca mch sau:

) Ng ra cc mch trn lun n nh trng thi Q = 0 hay Q = 1 ) Mch nh n (bistable device), l mch tn ti 1 trong 2 trng thi n nh, c th c s dng cha 1 bit thng tin ) i vi mch s, phn t linh kin thng dng nht c s dng lm b nh cho cc tn hiu l 1 thit b in t nh n c tn l flip-flop
Logic Design 1 - Chapter 5 7

Mch ci SR (SR Latch)

) Mch nh n xt c th v li nh sau ) Gii quyt c s u nhau gia cc tn hiu vo ) Mch ci SR c s khi v c th v li nh sau

) Mch c xem c 2 tn hiu ng vo l I (tn hiu bn ngoi) v Q (tn hiu hi tip) u nhau quyt nh gi tr Q ca memory cell ) Chng ta xt 1 mch bistable khc c tn l mch ci SR (SR Latch)
S : set R : reset
Logic Design 1 - Chapter 5

) Xc nh bng s tht ca mch mch ci SR ? ) Trng thi ?

Trng thi hin hnh Q(tn ) | Qn | Trng thi k tip Q(tn+1 ) | Qn+1 Q

Q+
8

Mch ci SR ...
) Bng chuyn trng thi (transition table) ca mch ci SR
S 0 0 0 0 R 0 0 1 1 Q 0 1 0 1 Q+ 0 1 0 0 S 1 1 1 1 R 0 0 1 1 Q 0 1 0 1 Q+ 1 1 S 0 0 1 1 R 0 1 0 1 Q+ Q 0 1

) Mch ci SR s dng cng NOR

) Phng trnh chuyn trng thi ca mch ci SR: Q+ = S + R.Q ,iu kin S.R = 0
Logic Design 1 - Chapter 5 9

nh thi v Clocked RS Latch

) Mch ci SR xt cha c s tham gia ca xung clock ) Xung clock gip cho vic chuyn trng thi c xy ra ng thi v n nh hn ) Clocked SR Latch s dng cng NAND ) S khi

) Bng chuyn trng thi

C 0 1 1 1 1 S 0 0 1 1 R 0 1 0 1 Q+ Q Q 0 1

) Phng trnh chuyn trng thi Q+ = C Q + C S + R Q

Logic Design 1 - Chapter 5 10

JK Latch
) mch ci SR
C 2 ng vo khng c ng thi mang gi tr 1 Khng ph hp vi thc t, cn phi c s ci tin

) Mch ci JK (JK Latch)

) Phng trnh chuyn trng thi Q+ = C.Q + C(J.Q) + (K.Q).Q = C.Q + C.J.Q + K.Q + Q.Q = C.Q + C.J.Q + K.Q = J.Q + K.Q ; vi C = 1 ) Kim tra iu kin ? S.R = (J.Q).(K.Q) = J.K.Q.Q = 0 ) Bng chuyn trng thi
C 0 1 J 0 0 1 1 K 0 1 0 1 Q+ Q Q 0 1 Q
11

) Nhn xt
S = J.Q R = K.Q
Logic Design 1 - Chapter 5

1 1 1

Master-Slave Latch
) mch ci JK, iu g s xy ra khi J = K = 1 ?
Trng hp mch ci JK Trng hp clocked JK Latch

) Gii php

) Kch cnh (Edge-Triggering)

C ch Master-Slave Mch JK Master-Slave Latch K hiu

) Mt s s mch ca JK Master-Slave Latch

Logic Design 1 - Chapter 5

Flip-flop

12

(Delay) D Flip-flop
) Mt gii php khc cho mch ci SR l gn R = S ) Mch ci D (D latch) ) D flip-flop

Phng trnh chuyn trng thi Q+ = D Bng chuyn trng thi

C 0 1 1 D 0 1 Q+ Q 0 1

) Xy dng D flip-flop t JK flip-flop ? ) Gin xung (timing waveform)

D data hoc delay

Logic Design 1 - Chapter 5 13

(Toggle) T flip-flop
) Flip-flop c ng ra bt-tt (toggle) ) Xy dng t JK flip-flop
S mch Phng trnh Q+ = T.Q + T.Q = T Q

toggle xy ra khi T = 1

) Mt s mch T flip-flop

) Xy dng T flip-flop t D flip-flop ?

Logic Design 1 - Chapter 5 14

Kch thch cc flip-flop

) Bng trng thi / phng trnh chuyn trng thi cho php xc nh trng thi (ng ra Q) ca flip-flop theo cc tn hiu ng vo ) Cn xc nh iu kin kch thch flip-flop chuyn t trng thi xc nh ny sang trng thi xc nh khc ) Cc iu kin kch thch flip-flop
SR flip-flop
Q Q+ 0 0 1 1 0 1 0 1 S R 0 1 0 0 1 0 0 0 1 1

JK flip-flop
Q Q+ 0 1 0 1 J K 0 1 1 0

D flip-flop
Q Q+ 0 0 1 1 0 1 0 1 D 0 1 0 1

T flip-flop
Q Q+ 0 0 1 1 0 1 0 1 T 0 1 1 0

Logic Design 1 - Chapter 5

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Thanh ghi (Register)

) Khc bit ca mch tun t so vi mch t hp
C kh nng cha vo b nh cc thng tin v trng thi ca mch, h qu ca tn hiu ng vo trong qu kh S dng thng tin trong b nh to tn hiu ng ra theo tn hiu ng vo hin hnh Thanh ghi n-bit l mt tp hp ca n flip-flop (thng l D flipflop) Cc flip-flop ny dng chung xung clock v p ng cng thi im ca xung clock C th cha c n bit thng tin

) n v c bn cha 1 bit thng tin l flip-flop hoc l mch ci ) Cc flip-flop c th nhm li to thnh thanh ghi (register)

) Chuyn thng tin vo thanh ghi c gi l np (load) thanh ghi ) Tham kho thng tin t thanh ghi c gi l c (read) ni dung thanh ghi

Logic Design 1 - Chapter 5

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Serial-Load Shift Register

) Thanh ghi dch np tun t 4 bit

) Phn tch mch lm r cc tnh nng sau

Thanh ghi dch (shift register) Xut song song (parallel-out) Xut tun t (serial-out) Np tun t (serial-in)

) Thm vo cc tn hiu iu khin

iu khin xung clock iu khin d liu vo

Logic Design 1 - Chapter 5

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Parallel-Load Shift Register

) Thanh ghi np song song 4 bit s dng JK flip-flop
m xung clock m tn hiu iu khin np (load) Tn hiu iu khin xa (CLR)

) Thanh ghi thng mi ha di dng MSI

74 273 74 373 74 374

) Xy dng thanh ghi dch np song song ?

Logic Design 1 - Chapter 5

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Chuyn i song song ni tip

) Thanh ghi dch 4 bit lm nhim v chuyn i song song ni tip

) Phn tch mch ) Hot ng

Logic Design 1 - Chapter 5

19

Thanh ghi a nng

) tng v thanh ghi a nng

) Mt ng dng minh ha 000 001 100

Logic Design 1 - Chapter 5

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Bi tp
) ) ) ) ) Problem Problem Problem Problem Problem 5.1 5.4 5.5 5.7 5.11

Thy

Phan nh Th Duy
duypdt@cse.hcmut.edu.vn

Logic Design 1 - Chapter 5

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