Kien Truc Co Ban Cua STM32-ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3
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Kin trc c bn ca STM32_ARM Cortex M3

ARM Vietnam 3/18/2010
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Mc Lc
Mc Lc ....................................................................................................................... 1 Chng 1...................................................................................................................... 6 GII THIU ............................................................................................................... 6 1.1 Cortex l g?....................................................................................................... 6 1.2 Mt vi c im ni bt ca STM32 ............................................................. 9 1.2.1 S tinh vi .................................................................................................. 10 1.2.2 S an ton ................................................................................................ 11 1.2.3 Tnh bo mt ........................................................................................... 11 1.2.4 Pht trin phn mm .............................................................................. 12 1.2.5 Dng Performance v Access ca STM32 ............................................ 12 Chng 2.................................................................................................................... 14 TNG QUAN V CORTEX ................................................................................... 14 2.1 Cc phin bn kin trc ARM ....................................................................... 14 2.2 B x l Cortex v n v x l trung tm Cortex ........................................ 15 2.3 n v x l trung tm Cortex (Cortex CPU) ............................................... 15 2.3.1 Kin trc ng ng (Pipline) ................................................................ 15 2.3.2 M hnh lp trnh (Programmers model) ............................................ 16 2.3.2.1 Thanh ghi XPSR .............................................................................. 18 2.3.3 Cc ch hot ng ca CPU .............................................................. 19 2.3.4 Tp lnh Thumb-2 .................................................................................. 21 2.3.5 Bn b nh (Memory Map) .............................................................. 22 2.3.6 Truy cp b nh khng xp hng (Unaligned Memory Accesses) ..... 24 2.3.7 Di Bit (Bit Banding) .............................................................................. 25 2.4 B x l Cortex ............................................................................................... 28 2.4.1 Bus ............................................................................................................ 28 2.4.2 Ma trn Bus ............................................................................................. 29 2.4.3 Timer h thng (System timer) .............................................................. 29 2.4.4 X l ngt (Interrupt Handling)............................................................. 30 2.4.5 B iu khin vector ngt lng nhau (Nested Vector Interrupt Controller) ......................................................................................................... 30 2.4.5.1 Phng php nhp v thot khi mt ngoi l ca NVIC (NVIC Operation Exception Entry And Exit) ........................................................ 32 2.4.5.2 Cc ch x l ngt cao cp (Advanced Interrupt Handling Modes) ............................................................................................................ 33 2.4.5.2.1 Quyn u tin ngt (Interrupt Pre-emption) ......................... 33 2.4.5.2.2 K thut Tail Chaining trong NVIC ....................................... 34 2.4.5.3 Cu hnh v s dng NVIC ............................................................. 35 2.4.5.3.1 Bng vector ngt (Exception Vector Table) ........................... 35 2.5 Cc ch nng lng .................................................................................. 40 2.5.1 Cch i vo ch nng lng thp ca CPU Cortex ........................ 40
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2.5.2 Khi h tr g li CoreSight .................................................................. 42 Chng 3.................................................................................................................... 45 PHN CNG C BN CHO MT THIT K THC T ............................... 45 3.1 Kiu ng gi chip v kiu chn linh kin .................................................... 45 3.3.1 S mch phn cng c bn ................................................................ 47 Chng 4.................................................................................................................... 48 KIN TRC H THNG CA ARM CORTEX ................................................. 48 4.1 Cu trc b nh .............................................................................................. 49 4.2 Ti a hiu nng .............................................................................................. 50 4.2.1 Vng Kha Pha(Phase Lock Loop) ............................................................ 51 4.2.1.1 Cu hnh cho bus....................................................................................... 53 4.2.2 Flash Buffer .................................................................................................. 54 4.2.3 Direct Memory Access ................................................................................. 55 Chng 5.................................................................................................................... 61 NGOI VI.................................................................................................................. 61 5.1 Ngoi vi a dng.............................................................................................. 61 5.1.1 Cc cng I/O a dng .............................................................................. 61 5.1.1.1 Chc nng thay th(Alternate Function) ........................................ 63 5.1.1.2 Event Out ........................................................................................... 64 5.1.2. Ngt ngoi(EXTI).................................................................................... 64 5.1.3 ADC ........................................................................................................... 66 5.1.3.1 Thi gian chuyn i v nhm chuyn i ..................................... 66 5.1.3.2 Analogue WatchDog ......................................................................... 69 5.1.3.3 Cu hnh ADC ................................................................................... 69 5.1.3.4. Dual mode ......................................................................................... 71 5.3.1.4.1. C hai khi ADC cng hot ng cng ch Regular hoc Injected....................................................................................................... 71 5.3.1.4.2. C hai khi cng hot ng 2 ch Regular v Injected xen k.......................................................................................................... 72 5.3.1.4.3. Hot ng xen k nhanh v chm Regular............................. 72 5.3.1.4.4. Ch kch hot thay th......................................................... 73 5.3.1.4.5. Kt hp ng b ha Regular v kch hot thay th ............. 73 5.3.1.4.6. Kt hp ng b ha Injected v xen k Regular .................. 73 5.1.4. B nh thi a nhim v nng cao ....................................................... 74 5.1.4.1. B nh thi a nhim ..................................................................... 74 5.1.4.1.1 Khi Capture/Compare ............................................................. 75 5.1.4.1.2 Khi Capture .............................................................................. 75 5.1.4.1.3 Ch PWM Input.................................................................... 76 5.1.4.1.5 Ch One Pulse ....................................................................... 78 5.1.4.3 ng b ho cc b nh thi........................................................... 78 5.1.5 RTC v cc thanh ghi Backup ................................................................ 79 5.2 Kt ni vi cc giao tip khc ........................................................................ 80
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5.2.1 SPI ............................................................................................................. 80 5.2.2 I2C ............................................................................................................. 82 5.2.3 USART ...................................................................................................... 83 5.2.4 CAN ........................................................................................................... 85 5.2.5 USB ............................................................................................................ 88 Chng 6.................................................................................................................... 89 CH TIU TH NNG LNG THP........................................................ 89 6.1 Ch bnh thng - RUN mode .................................................................. 89 6.1.1 Ch Half-cycle v Prefetch-buffer..................................................... 90 6.2. Cc ch s dng cng sut tiu th thp ................................................ 91 6.2.1. SLEEP ...................................................................................................... 91 6.2.2 STOP Mode .............................................................................................. 92 6.3 Standby ............................................................................................................ 94 6.4. S tiu th cng sut ca ngun d phng (Backup Region Power Consumption) ........................................................................................................ 96 6.5 H tr Debug (Debug Support) ..................................................................... 96 Chng 7.................................................................................................................... 97 TNH AN TON ....................................................................................................... 97 7.1 Reset Control ................................................................................................... 97 7.2 Kim tra in p ngun .................................................................................. 99 7.3 H thng an ton xung nhp (Clock Security System - CSS) ...................... 99 7.4 Watchdogs ..................................................................................................... 100 7.4.1 Windowed Watchdog ............................................................................ 101 7.4.2 Independent Watchdog ......................................................................... 102 7.5 Tnh nng ngoi vi ........................................................................................ 104 7.5.1 GPIO Port Locking (kha port GPIO) ................................................ 104 7.5.2 Analog Watchdog ................................................................................... 104 7.5.3 Break Input............................................................................................. 104 Chng 8: ................................................................................................................ 105 FLASH ..................................................................................................................... 105 8.1 Lp trnh v m bo an ton cho FLASH ni .......................................... 105 8.2 Hot ng xa v ghi .................................................................................... 106 8.3 Cc byte Option (Option Bytes)................................................................... 107 8.3.1 Bo v ghi ................................................................................................ 107 8.3.2 Bo v c ............................................................................................... 107 8.3.3 Byte Cu hnh ......................................................................................... 108 Chng 9: ................................................................................................................ 109 CNG C PHT TRIN ...................................................................................... 109 9.1 Evaluation Tools............................................................................................ 110
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9.2 Cc th vin v giao thc ............................................................................. 110 9.3 H iu hnh thi gian thc ......................................................................... 111
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Chng 1 GII THIU

Trong vi nm tr li y, mt trong nhng xu hng ch yu trong cc thit k vi vi iu khin l s dng cc chip ARM7 v ARM9 nh mt vi iu khin a dng. Ngy nay cc nh sn xut IC a ra th trng hn 240 dng vi iu khin s dng li ARM. Tp on ST Microelectronic va cho ra mt dng STM32, vi iu khin u tin da trn nn li ARM Cortex-M3 th h mi do hng ARM thit k, li ARM Cortex-M3 l s ci tin ca li ARM7 truyn thng, tng mang li s thnh cng vang di cho cng ty ARM. Dng STM32 thit lp cc tiu chun mi v hiu sut, chi ph, cng nh kh nng p ng cc ng dng tiu th nng lng thp v tnh iu khin thi gian thc khc khe.
1.1 Cortex l g?
Dng ARM Cortex l mt b x l th h mi a ra mt kin trc chun cho nhu cu a dng v cng ngh. Khng ging nh cc chip ARM khc, dng Cortexk l mt li x l hon thin, a ra mt chun CPU v kin trc h thng chung. Dng Cortex gm c 3 phn nhnh chnh: dng A dnh cho cc ng dng cao cp, dng R dnh cho cc ng dng thi gian thc nh cc u c v dng M dnh cho cc ng dng vi iu khin v chi ph thp. STM32 c thit k da trn dng Cortex-M3, dng Cortex-M3 c thit k c bit nng cao hiu sut h thng, kt hp vi tiu th nng lng thp, CortexM3 c thit k trn nn kin trc mi, do chi ph sn xut thp cnh tranh vi cc dng vi iu khin 8 v 16-bit truyn thng. Cc chip ARM7 v ARM9 c cc nh sn xut bn dn thit k vi gii php ring ca mnh, c bit l phn x l cc cc ngt c bit (exception) v cc ngt thng thng (interrupt). Cortex-M3 a ra mt li vi iu khin chun nhm cung cp phn tng qut, quan trng nht ca mt vi iu khin,
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bao gm h thng ngt (interrupt system), SysTick timer (c thit k cho h iu hnh thi gian thc), h thng kim li (debug system) v memory map. Khng gian a ch 4Gbyte ca Cortex-M3 c chia thnh cc vng cho m chng trnh, SRAM, ngoi vi v ngoi vi h thng. Khng ging vi ARM7 c thit k theo kin trc Von Neumann (b nh chng trnh v b nh d liu chung vi nhau), Cortex-M3 c thit k da theo kin trc Harvard (b nh chng trnh v b nh d liu tch bit vi nhau), v c nhiu bus cho php thc hin cc thao tc song song vi nhau, do lm tng hiu sut ca chip. Khng ging vi cc kin trc ARM trc , dng Cortex cho php truy cp d liu khng xp hng (unaligned data, v chip ARM l kin trc 32bit, do tt c cc d liu hoc m chng trnh u c sp sp kht vi vng b nh l bi s ca 4byte). c im ny cho php s dng hiu qu SRAM ni. Dng Cortex cn h tr vic t v xo cc bit bn trong hai vng 1Mbyte ca b nh bng phng php gi l bit banding. c im ny cho php truy cp hiu qu ti cc thanh ghi ngoi vi v cc c c dng trn b nh SRAM m khng cn mt b x l lun l (Boolean processor).
Hnh 1.1. Kin trc vi x l ARM Cortex-M3
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Khi trung tm ca STM32 l b x l Cortex-M3. B x l Cortex-M3 l mt vi iu khin c tiu chun ho gm mt CPU 32bit, cu trc bus (bus structure), n v x l ngt c h tr tnh nng lng ngt vo nhau (nested interrupt unit), h thng kim li (debug system) v tiu chun b tr b nh (standard memory layout). Mt trong nhng thnh phn chnh ca li Cortex-M3 l NVIC (Nested Vector Interrupt Controller). NVIC cung cp mt cu trc ngt chun cho tt c cc vi iu khin c thit k da trn li Cortex v cch x l cc ngt c bit (exceptional interrupt). NVIC cung cp cc vector ngt chuyn dng ln ti 240 ngun ngt t ngoi vi, mi ngun ngt c th c u tin ho vi cc mc ring bit. NVIC c thit k x l cc ngt i hi thi gian p ng cc k nhanh (extremely fast interrupt). Thi gian t lc nhn mt tn hiu ngt cho ti khi thc thi dng lnh u tin trong trnh phc v ngt ch l 12 chu k xung nhp. Cng vic ny c thc hin t ng bi mt vi chuong trnh (microcode) c ci sn trong CPU. Trong trng hp xut hin cc interrupt lng nhau (tc l xy ra ngt khi ang x l ngt trc ), NVIC s dng mt phng thc gi l tail chain cho php ngt lin tip c phc v vi tr ch c 6 chu k xung nhp. Trong sut giai on lu tr d liu ln vng nh stack bt u thc thi chng trnh phc v ngt, mt ngt c mc u tin cao hn ngt hin ti c th cnh tranh vi (pre-empt) ngt hin ti m khng chu bt k tr hon no. Cu trc ngt cng i km vi ch tit kim nng lng ca trong li Cortex-M3. CPU c th c cu hnh t ng vo ch tit kim nng lng sau khi thot khi ngt. Sau li tip tc ng cho n khi mt exception (ngt c bit) xut hin. Mc d Cortex-M3 c thit k nh l mt li chi ph thp (low cost core), nhng n vn l mt CPU 32-bit v vn h tr hai ch hot ng: Thread v Handler, mi ch c th c cu hnh vi mi vng stack ring bit ca n, iu ny cho php thit k cc phn mm phc tp v h tr cc h diu
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hnh thi gian thc. Li Cortex c h tr mt timer 24-bit t ng np li gi tr, n s cung cp mt ngt timer u n cho mt nhn RTOS (Real Time Operating System). Cc chip ARM7 v ARM9 c hai tp lnh (tp lnh ARM 32-bit v tp lnh Thumb 16-bit), trong khi dng Cortex c thit k h tr tp lnh ARM Thumb-2, tp lnh ny c pha trn gia tp lnh 16 v 32bit, nhm t c hiu sut cao ca ca tp lnh ARM 32-bit vi mt m chng trnh ti u ca tp lnh Thumb 16-bit. Tp lnh Thumb-2 c thit k c bit dnh cho trnh bin dch C/C++, tc l cc ng dng da trn nn Cortex hon ton c th c vit bng ngn ng C m khng cn n chng trnh khi ng vit bng assembler nh ARM7 v ARM9.
1.2 Mt vi c im ni bt ca STM32
ST a ra th trng 4 dng vi iu khin da trn ARM7 v ARM9, nhng STM32 l mt bc tin quan trng trn ng cong chi ph v hiu sut (price/performance), gi ch gn 1 Euro vi s lng ln, STM32 l s thch thc tht s vi cc vi iu khin 8 v 16-bit truyn thng. STM32 u tin gm 14 bin th khc nhau, c phn thnh hai nhm: dng Performance c tn s hot ng ca CPU ln ti 72Mhz v dng Access c tn s hot ng ln ti 36Mhz. Cc bin th STM32 trong hai nhm ny tng thch hon ton v cch b tr chn (pin) v phn mm, ng thi kch thc b nh FLASH ROM c th ln ti 128K v 20K SRAM.
Hnh 1.2. Kin trc ca STM32 nhnh Performance v Access
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Dng STM32 c hai nhnh, nhnh Performance hot ng vi xung nhp ln n 72Mhz v c y cc ngoi vi, nhnh Access hot ng vi xung nhp ti a 36Mhz v c t ngoi vi hn so vi nhnh Performance.
1.2.1 S tinh vi
Thot nhn th cc ngoi vi ca STM32 cng ging nh nhng vi iu khin khc, nh hai b chuyn i ADC, timer, I2C, SPI, CAN, USB v RTC. Tuy nhin mi ngoi vi trn u c rt nhiu c im th v. V d nh b ADC 12-bit c tch hp mt cm bin nhit t ng hiu chnh khi nhit thay i v h tr nhiu mode chuyn i. Mi b timer c 4 khi capture compare, mi khi timer c th lin kt vi cc khi timer khc to ra mt mng cc timer tinh vi. Mt timer cao cp chuyn h tr iu khin ng c, vi 6 u ra PWM vi dead time lp trnh c v mt ng break input s buc tn hiu PWM sang mt trng thi an ton c ci sn. Ngoi vi ni tip SPI c mt khi kim tng CRC bng phn cng cho 8 v 16 word h tr tch cc cho giao tip th nh SD hoc MMC. STM32 c h tr thm 7 knh DMA (Direct Memory Access). Mi knh c th c dng truyn d liu n cc thanh ghi ngoi vi hoc t cc thanh ghi ngoi vi i vi kch thc t (word) d liu truyn i c th l 8/16 hoc 32-bit. Mi ngoi vi c th c mt b iu khin DMA (DMA controller) i km dng gi hoc i hi d liu nh yu cu. Mt b phn x bus ni (bus arbiter) v ma trn bus (bus matrix) ti thiu ho s tranh chp bus gia truy cp d liu thng qua CPU (CPU data access) v cc knh DMA. iu cho php cc n v DMA hot ng linh hot, d dng v t ng iu khin cc lung d liu bn trong vi iu khin. STM32 l mt vi iu khin tiu th nng lng thp v t hiu sut cao. N c th hot ng in p 2V, chy tn s 72MHz v dng tiu th ch c 36mA vi tt c cc khi bn trong vi iu khin u c hot ng. Kt hp vi cc ch tit kim nng lng ca Cortex, STM32 ch tiu th 2A khi
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ch standby. Mt b dao ng ni RC 8MHz cho php chip nhanh chng thot khi ch tit kim nng lng trong khi b dao ng ngoi ang khi ng. Kh nng nhanh i vo v thot khi cc ch tit kim nng lng lm gim nhiu s tiu th nng lng tng th.
1.2.2 S an ton
Ngy nay cc ng dng hin i thng phi hot ng trong mi trng khc khe, i hi tnh an ton cao, cng nh i hi sc mnh x l v cng nhiu thit b ngoi vi tinh vi. p ng cc yu cu khc khe , STM32 cung cp mt s tnh nng phn cng h tr cc ng dng mt cch tt nht. Chng bao gm mt b pht hin in p thp, mt h thng bo v xung clock v hai b watchdogs. B u tin l mt watchdog ca s. Watchdog ny phi c lm ti trong mt khung thi gian xc nh. Nu nhn n qu sm, hoc qu mun, th watchdog s kch hot. B th hai l mt watchdog c lp, c b dao ng bn ngoi tch bit vi xung nhp h thng chnh. H thng bo v xung nhp c th pht hin li ca b dao ng chnh bn ngoi (thng l thch anh) v t ng chuyn sang dng b dao ng ni RC 8MHz.
1.2.3 Tnh bo mt
Mt trong nhng yu cu khc khe khc ca thit k hin i l nhu cu bo mt m chng trnh ngn chn sao chp tri php phn mm. B nh Flash ca STM32 c th c kha chng truy cp c Flash thng qua cng debug. Khi tnh nng bo v c c kch hot, b nh Flash cng c bo v chng ghi ngn chn m khng tin cy c chn vo bng vector ngt. Hn na bo v ghi c th c cho php trong phn cn li ca b nh Flash. STM32 cng c mt ng h thi gian thc v mt khu vc nh d liu trn SRAM c nui nh ngun pin. Khu vc ny c mt u vo chng gi mo, c th kch hot mt s kin ngt khi c s thay i trng thi u vo ny. Ngoi ra mt s kin chng gi mo s t ng xa d liu c lu tr trn SRAM c nui bng ngun pin.
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1.2.4 Pht trin phn mm

Nu bn s dng mt vi iu khin da trn li ARM, cc cng c pht trin c h tr tp lnh Thumb-2 v dng Cortex. Ngoi ra ST cng cung cp mt th vin iu khin thit b ngoi vi, mt b th vin pht trin USB nh l mt th vin ANSI C v m ngun l tng thch vi cc th vin trc c cng b cho vi iu khin STR7 v STR9. C rt nhiu RTOS m ngun m v thng mi v middleware (TCP/IP, h thng tp tin, v.v.) h tr cho h Cortex. Dng Cortex-M3 cng i km vi mt h thng g li hon ton mi gi l CoreSight. Truy cp vo h thng CoreSight thng qua cng truy cp Debug (Debug Access Port), cng ny h tr kt ni chun JTAG hoc giao din 2 dy (serial wire-2 Pin), cng nh cung cp trnh iu khin chy g li, h thng CoreSight trn STM32 cung cp mt data watchpoint v mt cng c theo di (instrumentation trace). Cng c ny c th gi thng tin v ng dng c la chn n cng c g li. iu ny c th cung cp thm cc thng tin g li v cng c th c s dng trong qu trnh th nghim phn mm.
1.2.5 Dng Performance v Access ca STM32

H STM32 c hai nhnh u tin ring bit: dng Performance v dng Access. Dng Performance tp hp y cc thit b ngoi vi v chy vi xung nhp ti a 72MHz. Dng Access c cc thit b ngoi vi t hn v chy ti a 32MHz. Quan trng hn l cch b tr chn (pins layout) v cc kiu ng gi chip (package type) l nh nhau gia dng Access v dng Performance. iu ny cho php cc phin bn khc nhau ca STM32 c hon v m khng cn phi sa i sp sp li footprint (m hnh chn ca chip trong cng c layout bo mch) trn PCB (Printed Circuit Board). Ngoi hai dng Performance v Access u tin, hin nay ST a ra th trng thm hai dng USB Access v Connectivity nh hnh bn di.
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Hnh 1.3. c im ca bn nhnh trong h STM32
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Chng 2 TNG QUAN V CORTEX

Nh chng ta thy trong phn gii thiu, b x l Cortex l th h li nhng k tip t ARM. Cortex tha k cc u im t cc b x l ARM trc , n l mt li x l hon chnh, bao gm b x l trung tm Cortex v mt h thng cc thit b ngoi vi xung quanh, Cortex cung cp phn x l trung tm ca mt h thng nhng. p ng yu cu khc khe v a dng ca cc h thng nhng, b x l Cortex gm c 3 nhnh, c biu hin bng cc k t sau tn Cortex nh sau: Cortex-A : b vi x l dnh cho h iu hnh v cc ng dng ca ngi dng phc tp. H tr cc tp lnh ARM, Thumb v Thumb-2. Cortex-R : b x l dnh cho cc h thng i hi khc khe v tnh thi gian thc. H tr cc tp lnh ARM, Thumb, v Thumb-2. Cortex-M : b x l dnh cho dng vi iu khin, c ti u ha cho cc ng dng nhy cm v chi ph. Ch h tr tp lnh Thumb-2. Con s nm cui tn Cortex cho bit mc hiu sut tng i, vi 1 l thp nht v 8 l cao nht. Hin nay dng Cortex-M c mc hiu sut cao nht l mc 3. STM32 da trn b x l Cortex-M3.
2.1 Cc phin bn kin trc ARM

Tnh n thi im hin ti th phin bn kin trc mi nht ca li ARM l ARMv7 (Trc c ARMv4, ARMv5, ARMv6). B x l Cortex-M3 da trn kin trc ARMv7 M v c kh nng thc hin tp lnh Thumb-2.
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Hnh 2.1. Cc phin bn kin trc ca li ARM
Cc ti liu hng dn k thut cho Cortex-M3 v kin trc ARMv7-M c th c ti v t website ca ARM ti www.arm.com.
2.2 B x l Cortex v n v x l trung tm Cortex

Trong sut phn cn li ca ti liu ny, cc thut ng b x l Cortex (Cortex processor) v n v x l trung tm Cortex (Cortex CPU) s c s dng phn bit gia nhng li Cortex hon chnh v b x l trung tm RISC ni (internal RISC CPU). Trong phn tip theo chng ta s xem xt cc c im chnh ca n v x l trung tm Cortex, tip theo l h thng thit b ngoi vi bn trong b x l Cortex.
2.3 n v x l trung tm Cortex (Cortex CPU)

Trung tm ca b x l Cortex l mt CPU RISC 32-bit. CPU ny c mt phin bn c n gin ha t m hnh lp trnh (programmers model) ca ARM7/9 , nhng c mt tp lnh phong ph hn vi s h tr tt cho cc php ton s nguyn, kh nng thao tc vi bit tt hn v kh nng p ng thi gian thc tt hn.
2.3.1 Kin trc ng ng (Pipline)
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CPU Cortex c th thc thi hu ht cc lnh trong mt chu k n. Ging nh CPU ca ARM7 v ARM9, vic thc thi ny t c vi mt ng ng ba tng. Tuy nhin Cortex-M3 kh nng d on vic r nhnh gim thiu s ln lm rng (flush) ng ng.
Hnh 2.2. Kin trc ng ng ca ARM Cortex-M3
Trong khi mt lnh ang c thc thi, th lnh tip theo s c gii m v lnh tip theo na s c ly v t b nh. Phng thc hot ng ny s pht huy hiu qu ti a cho m tuyn tnh (linear code), nhng khi gp phi mt r nhnh (v d cu trc lnh ifelse) th cc ng ng phi c lm rng (flush) v lm y (refill) trc khi m c th tip tc thc thi. Vi CPU ARM7 v ARM9, vic r nhnh l rt tn km v mt hiu sut m (code performance). Trong CPU Cortex c ng ng ba tng c tng cng kh nng d on r nhnh, c ngha rng khi mt lnh r nhnh c iu kin xut hin, mt thao tc ly lnh da trn suy on c thc hin, do lnh r nhnh c iu kin sn sng thc hin m khng cn chu thm mt thao tc no. Trng hp xu nht khi gp phi mt r nhnh gin tip, khi khng th thc hin vic ly lnh da trn vic suy on, do phi lm rng ng ng dn. Kin trc ng ng l cha kha dn n hiu sut tng th ca CPU Cortex, v vy khng cn bt k cn nhc, xem xt c bit no c thc hin trong m ng dng.
2.3.2 M hnh lp trnh (Programmers model)

CPU Cortex l b x l da trn kin trc RISC, do h tr kin trc np v lu tr (load and store architecture). thc hin lnh x l d liu, cc ton
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hng phi c np vo mt tp thanh ghi trung tm, cc php tnh d liu phi c thc hin trn cc thanh ghi ny v kt qu sau c lu li trong b nh.
Hnh 2.3. Kin trc load v store ca ARM Cortex-M3
Do vy tt c cc hot ng ca chng trnh tp trung xung quanh tp thanh ghi ca CPU. Tp thanh ghi ny bao gm mi su thanh ghi 32-bit. Cc thanh ghi R0-R12 l cc thanh ghi n gin, c th c dng cha cc bin ca chng trnh. Cc thanh ghi R13-R15 c chc nng c bit trong CPU Cortex. Thanh ghi R13 c dng nh l con tr ngn xp (stack pointer). Thanh ghi ny c chia thnh nhm (banked), cho php CPU Cortex c hai ch hot ng, mi ch c khng gian ngn xp ring bit. c im ny thng c h iu hnh thi gian thc (Real Time Operating System) s dng c th chy m h thng ca mnh trong mt ch bo v. Trong CPU Cortex c hai ngn xp c gi l main stack v process stack. Thanh ghi R14 tip theo c gi l thanh ghi lin kt (link register). Thanh ghi ny c s dng lu tr cc a ch tr v khi mt cuc gi th tc (call a procedure) c thc hin. iu ny cho php CPU Cortex thc hin rt nhanh vic nhp v thot khi mt th tc (fast entry and exit to a procedure). Nu chng trnh ca bn gi su vo nhiu lp chng trnh con, trnh bin dch s t ng lu R14 trn ngn xp (stack). Thanh ghi cui cng R15 l b m chng trnh (Program Counter); n l mt phn ca tp thanh ghi trung tm, n c th c c v thao tc ging nh bt k thanh ghi khc.
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Hnh 2.3. M hnh lp trnh ca ARM Cortex-M3
2.3.2.1 Thanh ghi XPSR

Ngoi tp thanh ghi trung tm cn c mt thanh ghi ring bit c gi l thanh ghi trng thi chng trnh (Program Status Register). N khng phi l mt phn ca tp thanh ghi chnh v ch c th truy cp thng qua hai lnh chuyn dng. XPSR cha mt s cc vng chc nng quan trng nh hng n vic thc thi ca CPU Cortex.
Hnh 2.4. Thanh ghi trng thi chng trnh ca CPU Cortex
Thanh ghi xPSR cng c th c truy cp thng qua ba bit hiu c bit (special alias names) cho php truy cp vo cc bit trong xPSR. Nm bit u l nhng c m iu kin v c gn bit hiu (aliased) nh thanh ghi trng thi chng trnh ng dng. Bn c N, Z, C, V (Negative, Zero, Carry v Overflow) s c thit lp v xa ty thuc vo kt qu ca mt lnh x l d liu. Bit Q l c s dng bi cc lnh ton hc DPS ch ra rng mt bin t gi tr ti a hoc gi tr ti thiu ca n. Ging nh tp lnh ARM 32bit, cc lnh Thumb-2 ch c thc hin nu m iu kin ca lnh ph hp vi trng thi ca cc c trong thanh ghi trng thi chng trnh ng dng (Application Program Status Register). Nu m iu kin ca lnh khng ph hp, th lnh i ngang qua ng ng nh l mt lnh NOP (lnh ny khng
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Author: ARMVN
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lm g c). iu ny m bo rng cc lnh i qua ng ng mt cch trn tru v gim thiu lm rng ng ng. Trong CPU Cortex, k thut ny c m rng vi thanh ghi trng thi chng trnh thc thi. y l mt bit hiu ca bit cc bit t 8-26 ca xPSR. N gm ba trng: trng "If then", trng "interrupt continuable instruction"v trng lnh Thumb. Lnh Thumb-2 c mt phng php hiu qu khi thc hin cc khi lnh nh 'if then'. Khi mt kim tra iu kin l ng, n c th thit lp mt gi tr trong vng IT, bo cho CPU thc thi ln bn lnh. Nu vic kim tra iu kin l sai, cc lnh ny s i ngang qua ng ng nh l mt lnh NOP. V vy, mt dng lnh C in hnh s c m ho nh sau:
If (r0 ==0) CMP r0,#0 ITTEE EQ Then r0 = *r1 +2; LDR r0,[r1] ADDr0,#2 ;compare r0 to 0 ;if true execute the next two instructions ;load contents of memory location into r0 ;add 2
Hu ht cc lnh Thumb-2 thc thi trong mt chu k n, mt s khc (nh lnh load v store) cn nhiu chu k. V vy, CPU Cortex c th c mt thi gian p ng ngt xc nh, cc lnh cn nhiu chu k thc thi phi c ngt. Khi mt lnh c chm dt sm, vng ICI (Interrupt Continuable
Instruction) trong thanh ghi xPSR s lu li s cc thanh ghi tip theo c dng trong lnh load hoc store nhiu d liu cng lc. V vy, mt khi ngt c phc v, lnh load/store b ngt trc c th tip tc c thc hin. Trng Thumb cui cng c tha hng t phin bn CPU ARM trc . Trng ny ch ra nu tp lnh ARM hoc Thumb ang c thc hin bi CPU. Trong Cortex-M3 bit ny lun lun c thit lp mc 1 (tc l tp lnh ang c thc thi l tp lnh Thumb). Cui cng, trng trng thi ngt cha thng tin v yu cu ngt c u tin trc (pre-empted).
2.3.3 Cc ch hot ng ca CPU

B vi x l Cortex c thit k vi mc tiu gim s bng bn dn, nhanh chng v d s dng li vi iu khin, n c c thit k h tr vic s
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dng h iu hnh thc hnh thi gian. B x l Cortex c hai ch hot ng: ch Thread v ch Handler. CPU s chy ch Thread trong khi n ang thc thi ch nn khng c ngt xy ra v s chuyn sang ch Handler khi n ang thc thi cc ngt c bit (exceptions). Ngoi ra, CPU Cortex c th thc thi m trong ch c quyn hoc khng c quyn (privileged or non-privileged mode). Trong ch c quyn, CPU c quyn truy cp tt c cc lnh. Trong ch khng co c quyn, mt s lnh b cm truy cp (nh lnh MRS v MSR cho php truy cp vo xPSR v cc trng ca n). Ngoi ra, vic cp cc thanh ghi iu khin h thng trong b vi x l Cortex cng b cm. Cch s dng ngn xp (stack) cng c th c cu hnh. Ngn xp chnh (main stack-R13) c th c s dng bi c hai ch Thread v Handler. Ch Handler c th c cu hnh s dng ngn xp qu trnh (process stack-R13 banked register).
Hnh 2.5. M hnh hot ng ca ch Thread v Handler
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Sau khi reset, b x l Cortex s chy trong cu hnh phng (flat configuration). C hai ch Thread v Handler c thc thi trong ch c quyn (privileged mode), do , khng c s gii hn no v quyn truy cp vo bt k ti nguyn ca b x l. C hai ch Thread v Handler u s dng ngn xp chnh. bt u thc hin, b x l Cortex n gin ch cn vector reset v a ch bt u ca ngn xp c cu hnh trc khi bn c th bt u thc thi chng trnh ng dng C ca bn. Tuy nhin, nu bn ang s dng mt h iu hnh thi gian thc (RTOS) hoc ang pht trin mt ng dng i hi khc khe v an ton, chip c th c s dng trong ch cu hnh nng cao, ni ch Handler (exceptions v RTOS) chy trong ch c quyn v s dng ngn xp chnh (main stack), trong khi m ng dng chy trong ch Thread v khng c c quyn truy cp v s dng ngn xp qu trnh (process stack). Bng cch ny m h thng v m ng dng c phn vng v cc li trong m ng dng s khng lm cho RTOS sp . 2.3.4 Tp lnh Thumb-2 Cc CPU ARM7 v ARM9 c th thc thi hai tp lnh: ARM 32-bit v Thumb 16-bit. iu ny cho php ngi pht trin ti u ho chng trnh ca mnh bng cch la chn tp lnh no c s dng cho th tc khc nhau: lnh 32-bit tng tc x l v lnh 16-bit nn m chng trnh. CPU Cortex c thit k thc thi tp lnh Thumb-2, l mt s pha trn ca lnh 16-bit v 32-bit. Tp lnh thumb-2 ci tin 26% mt m so vi tp lnh ARM 32-bit v 25% hiu sut so vi tp lnh Thumb 16-bit. Tp lnh Thumb2 c mt s lnh nhn c ci tin, c th thc hin trong mt chu k n v kh nng thc hin php chia bng phn cng v ch mt t 2-7 chu k.
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Author: ARMVN
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Hnh 2.6. th biu din hiu nng ca b x l Cortex
im chun b x l Cortex (Cortex processor benchmark) cho mt mc thc hin l 1,25 DMIPS/MHz, cao hn so vi ARM7 (0.95 DMIPS/MHz vi
tp lnh ARM v 0.74 DMIPS/MHz vi tp lnh Thumb) v ARM9 ().
Tp lnh Thumb-2 c: cc lnh r nhnh c ci tin bao gm vic kim tra v so snh, cc khi thc thi c iu kin if/then, th t byte thao tc d liu, cc lnh trch byte v half word. CPU Cortex c mt tp lnh phong ph c thit k c bit cho trnh bin dch C. Mt chng trnh Cortex-M3 in hnh s c vit hon ton bng ANSI C, vi ti thiu cc t kho non-ANSI v ch c bng vc t ngt c vit bng Assembler. 2.3.5 Bn b nh (Memory Map) B x l Cortex-M3 l mt li vi iu khin c tiu chun ha, nh vy n c mt bn b nh cng c xc nh. Mc d c nhiu bus ni, bn b nh ny l mt khng gian a ch 4 Gbyte tuyn tnh. Bn b nh ny l chung cho tt c cc thit b da trn li Cortex.
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Hnh 2.6. Bn b nh tuyn tnh 4Gbyte ca b x l Cortex-M3
Mt Gbyte b nh u tin c chia u cho mt vng m (code region) v mt vng SRAM (SRAM region). Khng gian m c ti u ha thc thi t bus I-Code. Tng t, SRAM c ni n bus D-Code. Mc d m c th c np v thc thi t SRAM, cc lnh s c ly bng cch s dng bus h thng, v vy phi chu thm mt trng thi ch (an extra wait state). Tc l m chy trn SRAM s chm hn so vi t b nh Flash trn chip (on-chip) nm trong vng m. Vng 0,5 Gbyte tip theo ca b nh l vng ngoi vi trn chip, tt c thit b ngoi vi c cung cp bi nh sn xut vi iu khin s c t ti vng ny. Vng 1 Mbyte u tin gm c SRAM (mu vng nht) v vng ngoi vi (mu hng nht) c nh a ch theo bit, s dng mt k thut c gi l di bit (bit banding). T tt c SRAM v cc thit b ngoi vi ngi dng (user peripherals) trn STM32 c t ti vng ny, v tt c cc v tr b nh ca nhng vng ny trn STM32 u c th c thao tc theo word-wide hoc bitwise. Khng gian a ch 2 Gbyte tip theo c phn
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cho b nh ngoi - nh x SRAM v thit b ngoi vi (external RAM v external Device). Vng 0,5 Gbyte cui cng c phn cho cc thit b ngoi vi bn trong ca b x l Cortex v mt khu vc dnh cho cc ci tin trong tng lai ca nh sn xut chip cho b x l Cortex. Tt c cc thanh ghi ca b x l Cortex c t v tr c nh cho tt c vi iu khin da trn li Cortex. iu ny cho php m chng trnh d dng c chuyn gia cc bin th STM32 khc nhau v cc vi iu khin da trn li Cortex ca cc nh sn xut chip khc. 2.3.6 Truy cp b nh khng xp hng (Unaligned Memory Accesses) Tp lnh ARM7 v ARM9 c kh nng truy cp cc bin c du v khng du c kch thc byte, half word (thng l 2byte) v word (thng l 4byte). iu ny cho php CPU h tr cc bin s nguyn m khng cn n th vin phn mm h tr, thng c yu cu i vi vi iu khin 8 v 16-bit. Tuy nhin, cc phin bn CPU ARM trc gp bt li ch, n ch c th truy cp d liu kch thc l word hoc half word. iu ny hn ch kh nng ca trnh lin kt ca trnh bin dch (compiler linker) trong vic ng gi d liu vo SRAM v nh vy mt s SRAM s b lng ph (Vic lng ph ny c th ln n 25% ty thuc vo s kt hp ca cc bin c s dng).
Hnh 2.7. Kh nng truy cp b nh khng xp hng ca b x l Cortex-M3 so vi cc phin bn CPU ARM trc
B x l Cortex-M3 c th truy cp b nh khng xp hng, vic m bo rng SRAM c s dng mt cch hiu qu.
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CPU Cortex c cc ch nh a ch cho word, half word v byte, nhng c th truy cp b nh khng xp hng (unaligned memory). iu ny cho php trnh lin kt ca trnh bin dch t do sp xp d liu chng trnh trong b nh. Vic b sung h tr tnh nng di bit (bit banding) vo CPU Cortex cho php cc c chng trnh c ng gi vo mt bin word hoc half-word hn l s dng mt byte cho mi c. 2.3.7 Di Bit (Bit Banding) Cc phin bn CPU ARM7 v ARM9 trc ch c th thc hin thao tc bit trn b nh SRAM v vng nh thit b ngoi vi bng cch dng cc php ton AND v OR. iu ny i hi thao tc c sa i ghi (READ MODIFY WRITE operation), thao tc ny s tn nhiu chu k thc hin thit lp v xo cc bit ring bit v cn nhiu khng gian m cho mi bit.
Hnh 2.8. Thao tc c sa i ghi ca CPU ARM7 v ARM9 v k thut di Bit ca b x l Cortex-M3
K thut di Bit cho php b x l Cortex-M3 thao tc cc bit trong khi vn gi c s lng bng bn dn mc ti thiu. khc phc nhng hn ch trong cc thao tc bit CPU ARM7 v ARM9, c th a ra cc lnh chuyn dng thit lp hoc xo bit, hoc mt b x l Boolean y , nhng iu ny s lm tng kch thc v s phc tp ca CPU Cortex. Thay vo , mt k thut gi l di bit cho php thao tc bit trc tip trn cc phn khng gian b nh ca cc thit b ngoi vi v SRAM, m
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khng s cn bt k lnh c bit no. Cc khu vc nh a ch bit ca bn b nh Cortex bao gm vng bit band (ln n 1Mbyte b nh thc hoc cc thanh ghi ngoi vi) v vng bit hiu bit band (bit band Alias region) chim n 32Mbyte ca bn b nh. Di Bit hot ng bng cch nh x mi bit trong vng bit band ti mt a ch word trong vng Alias. V vy, bng cch thit lp v xo a ch word c t bit hiu (aliased word address) chng ta c th thit lp v xo cc bit trong b nh thc.
Hnh 2.9. Di Bit ca vng b nh SRAM v cc ngoi vi
Di Bit c h tr trn 1Mb u tin ca khu vc SRAM v ngoi vi . N bao gm tt c cc ti nguyn ca STM32. K thut Bit Banding cho php thc hin thao tc bit ring l m khng cn bt k lnh c bit no, iu ny gi cho kch thc tng th ca li Cortex nh nht c th. Trong thc t, chng ta cn phi tnh ton a ch ca cc word nm trong vng Bit Band Alias cho mt v tr b nh nht nh trong khng gian b nh ca thit b ngoi vi hoc SRAM. Cng thc tnh ton alias address nh sau: a ch trong khu vc Bit Band Alias = Bit band alias base address + bit word offset bit word offset = Byte offset from bit band base x 0x20 + bit number x 4
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Cho mt v d thc t, thanh ghi d liu u ra GPIO (General Purpose I/O) c ghi vo thit lp v xo cc ng I/O ring bit. a ch vt l ca thanh ghi u ra ca port B l 0x40010C0C. Trong v d ny, chng ta mun c th thit lp v xo 8 bit ca word ny bng cch s dng cng thc trn. Word address Peripheral bit band base Peripheral bit band Alias base Byte offset from bit band base Bit word offset Bit Alias address cc dng lnh C nh sau : #define PB8 (*((volatile unsigned long*)0x422181A0)) // Port B bit 8 = 0x40010C0C = 0x40000000 = 0x42000000 = 0x40010c0c 0x40000000 = 10c0c = (0x10c0c x 0x20) +(8x4) = 0x2181A0 = 0x42000000 + 0x2181A0 = 0x422181A0
By gi chng ta c th to ra mt con tr n a ch ny bng cch s dng
Con tr ny c th c s dng thit lp v xo cc bit ca cng I/O ny: PB8 = 1; // led on
M trn c bin dch ra ngn ng assembly nh sau: MOVS LDR STR Tt LED: PB8 = 0; // led off r0,#0x01 r1,[pc,#104] r0,[r1,#0x00]
To ra m assembly sau y: MOVS LDR STR r0,#0x00 r1,[pc,#88] r0,[r1,#0x00]
C hai thao tc thit lp v xo mt ba lnh 16-bit v vi STM32 chy tn s 72 MHz cc lnh ny c thc hin trong 80nsec. Bt k mt word trong khu vc bit band ca thit b ngoi vi v SRAM c th c nh a ch trc tip ton word (word-wide), v vy c th thc hin vic thit lp v xo bng cch s dng phng php truyn thng vi cc lnh AND v OR:
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GPIOBODR |= 0x00000100; //LED on LDR r0,[pc,#68] ADDS r0,r0,#0x08 LDR r0,[r0,#0x00] ORR r0,r0,#0x100 LDR r1,[pc,#64] STR r0,[r1,#0xC0C] GPIOBODR &= !0x00000100; LDR r0,[pc,#40] ADDS r0,r0,#0x08 LDR r0,[r0,#0x00] MOVS r0,#0x00 LDR r1,[pc,#40] STR r0,[r1,#0xC0C] //LED off
Trng hp ny mi thao tc thit lp v xo s ly cc php ton hn hp gia 16 v 32-bit, iu ny phi mt ti thiu 14 byte cho tng php ton v cng mt tn s 72MHz s mt ti thiu l 180 nSec. Nu xem xt tc ng ca di bit trn mt ng dng nhng in hnh th vic thit lp v xa nhiu bit trong cc thanh ghi ngoi vi v s dng semaphores (mt dng nh c dng lp trnh trong mi trng h iu hnh) v c trong SRAM, r rng k thut bit band s tit kim ng k kch thc m v thi gian thc hin.
2.4 B x l Cortex
B x l Cortex c to thnh t CPU Cortex kt hp vi nhiu thit b ngoi vi nh Bus, system timer 2.4.1 Bus B vi x l Cortex-M3 c thit k da trn kin trc Harvard vi bus m v bus d liu ring bit . Chng c gi l cc bus Icode v Dcode. C hai bus u c th truy cp m v d liu trong phm vi b nh t 0x00000000 0x1FFFFFFF. Mt bus h thng b sung c s dng truy cp vo khng gian iu khin h thng Cortex trong phm vi 0x20000000 0xDFFFFFFF v 0xE0100000 0xFFFFFFFF. H thng g li trn chip ca Cortex c thm mt cu trc bus c gi l bus ngoi vi ring.
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2.4.2 Ma trn Bus Bus h thng v bus d liu c kt ni vi vi iu khin bn ngoi thng qua mt tp cc bus tc cao c sp xp nh mt ma trn bus. N cho php mt s ng dn song song gia bus Cortex v cc bus ch (bus master) khc bn ngoi nh DMA n cc ngun ti nguyn trn chip nh SRAM v cc thit b ngoi vi. Nu hai bus ch (v d CPU Cortex v mt knh DMA) c gng truy cp vo cng mt thit b ngoi vi, mt b phn x ni s gii quyt xung t v cho truy cp bus vo ngoi vi c mc u tin cao nht. Tuy nhin, trong STM32 khi DMA c thit k lm vic ha hp vi CPU Cortex. 2.4.3 Timer h thng (System timer) Li Cortex c mt b m xung 24-bit, vi tnh nng t ng np li (auto reload) gi tr b m v to s kin ngt khi m xung zero. N c to ra vi dng cung cp mt b m thi gian chun cho tt c vi iu khin da trn Cortex. ng h SysTick c s dng cung cp mt nhp p h thng cho mt RTOS, hoc to ra mt ngt c tnh chu k phc v cho cc tc v c lp lch. Thanh ghi trng thi v iu khin ca SysTick trong n v khng gian iu khin h thng Cortex-M3 cho php chn cc ngun xung clock cho SysTick. Bng cch thit lp bit CLKSOURCE, ng h SysTick s chy tn s ng bng tn s hot ng ca CPU. Khi bit ny c xa, SysTick s chy tn s bng 1/8 CPU.
Hnh 2.10. Cc thanh ghi trng thi v iu khin ca SysTick
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ng h SysTick c ba thanh ghi. Gi tr hin ti v gi tr ti (current value v reload value) nn c khi to vi chu k m. Thanh ghi trng thi v iu khin c mt bit cho php (ENABLE bit) bt u chy b m thi gian v mt bit TICKINT cho php tn hiu ngt. Trong phn tip theo chng ta s xem xt c cu ngt ca Cortex v s dng SysTick to ra mt ngt ngoi l (exception) u tin trn STM32. 2.4.4 X l ngt (Interrupt Handling) Mt trong nhng ci tin quan trng ca li Cortex so vi cc CPU ARM trc l cu trc ngt ca n v x l cc ngt ngoi l (exception handling). CPU ARM7 v ARM9 c hai ng ngt: ngt nhanh (fast interrupt-FIQ) v ngt a dng (general purpose interrupt hay cn gi l interrupt request-RIQ). Hai ng tn hiu ngt ny phc v tt c cc ngun ngt bn trong mt vi iu khin, trong khi k thut c s dng l nh nhau, nhng vic thc hin li khc bit gia cc nh sn xut chip. C cu ngt ca ARM7 v ARM9 gp phi hai vn . Trc ht n khng phi l xc nh; thi gian thc hin vic chm dt hay hy b mt lnh ang thc thi khi xy ra ngt l khng xc nh. iu ny c th khng l vn tr ngi cho nhiu ng dng, nhng n l mt vn ln trong iu khin thi gian thc. Th hai, c cu ngt ca ARM7 v ARM9 khng h tr ngt lng nhau (nested interrupts); cn c s h tr ca phn mm: s dng macro Assembler hoc mt RTOS. Mt trong nhng tiu ch quan trng ca li Cortex l khc phc nhng hn ch ny v cung cp mt cu trc ngt chun cc k nhanh chng v xc nh (extremely fast and deterministic). 2.4.5 B iu khin vector ngt lng nhau (Nested Vector Interrupt Controller) NVIC (Nested Vector Interrupt Controller) l mt n v tiu chun bn trong li Cortex. iu ny c ngha l tt c cc vi iu khin da trn li Cortex s c cng mt cu trc ngt, bt k nh sn xut chip l ST, Atmel, Luminary
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hoc NXP... V vy, m ng dng v h iu hnh c th d dng c chuyn t vi iu khin ny sang vi iu khin khc v lp trnh vin khc khng cn phi tm hiu mt tp cc thanh ghi hon ton mi. NVIC cng c thit k c mt tr khi p ng ngt rt thp. y l mt c im ca chnh bn thn b NVIC v ca tp lnh Thumb-2, n cho php thc thi cc lnh nhiu chu k (multi-cycle instructions) nh lnh ti v lu tr nhiu d liu ( load and store multiple instruction) c th c ngt khi ang thc thi. Do tr khi p ng ngt l xc nh, vi nhiu c im x l ngt tin tin, n h tr rt tt cho cc ng dng thi gian thc. Nh tn gi ca n, NVIC c thit k h tr cc ngt lng nhau (nested interrupts) v trn STM32 c 16 cp u tin ngt. Cu trc ngt NVIC c thit k hon ton lp trnh bng ANSI C v khng cn bt k macro Assembler hoc cc ch dn (directives) nonANSI.
Hnh 2.11. Cu trc ca NVIC trong b x l Cortex
Mc d NVIC l mt n v t chun bn trong li Cortex, gi cho s bng bn dn mc ti thiu, s ng tn hiu ngt i vo NVIC c th cu hnh khi vi iu khin c thit k. NVIC c mt ngt khng che mt n (nonmaskable interrupt) v hn 240 ng tn hiu ngt bn ngoi v c th c kt ni vi ngoi vi ngi dng. Ngoi ra cn c thm 15 ngun ngt bn trong li Cortex, c s dng x l cc ngt ni ngoi l trong li Cortex. B
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NVIC ca STM32 c tng hp vi ti a l 43 ng ngt che mt n (maskable interrupt lines). 2.4.5.1 Phng php nhp v thot khi mt ngoi l ca NVIC (NVIC Operation Exception Entry And Exit) Khi mt ngt c sinh ra bi mt thit b ngoi vi, NVIC s kch khi CPU Cortex phc v ngt. Khi CPU Cortex i vo ch ngt ca n, n s y mt tp cc thanh ghi vo vng ngn xp (stack). Thao tc ny c thc hin trong vi chng trnh (microcode), v vy khng cn vit thm bt k lnh no trong m ng dng. Trong khi khung ngn xp (stack frame) ang c lu tr, a ch bt u ca trnh dch v ngt c ly v trn bus Icode (instruction bus). V vy, thi gian t lc ngt c sinh ra cho ti khi lnh u tin ca trnh dch v ngt c thc thi ch c 12 chu k.
Hnh 2.12. Stack frame trong ch ngt
Stack frame bao gm thanh ghi trng thi chng trnh (Program Status Register), thanh ghi b m chng trnh (program counter) v thanh ghi lin kt (link register). Stack frame dng lu ng cnh m CPU Cortex ang chy. Cc thanh ghi t R0 - R3 cng c lu. Trong chun giao din nh phn ARM (ARM binary interface standard) cc thanh ghi ny c s dng truyn tham s, do thao tc lu tr cc thanh ghi ny s cung cp cho chng ta mt b thanh ghi sn sng c s dng bi trnh phc v ngt (Interrupt
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Service Routine-ISR). Thanh ghi cui cng cng c lu l R12; thanh ghi ny c s dng bi bt k m chng trnh no ang chy khi mt cuc gi hm c thc hin. V d, nu bn cho php tnh nng kim tra ngn xp (stack) trong trnh bin dch, m chng trnh c thm vo khi bin dch ra s s dng R12 nu n cn mt thanh ghi CPU. Khi kt thc qu trnh phc v ngt, khung ngn xp c khi phc t ng bi vi chng trnh (microcode), song song vi thao tc th a ch tr v c ly v, chng trnh nn c th tip tc thc hin ch sau 12 chu k.
Hnh 2.13. p ng thi gian khi mt ngt bt k xy ra ca Cortex-M3
2.4.5.2 Cc ch x l ngt cao cp (Advanced Interrupt Handling Modes) Vi kh nng x l mt ngt n rt nhanh, NVIC c thit k x l hiu qu nhiu ngt trong mt ng dng i hi khc khe tnh thi gian thc. NVIC c mt s phng php x l thng minh nhiu ngun ngt, sao cho tr gia cc ngt l ti thiu v m bo rng cc ngt c mc u tin cao nht s c phc v u tin. 2.4.5.2.1 Quyn u tin ngt (Interrupt Pre-emption) NVIC c thit k cho php cc ngt c mc u tin cao s dnh quyn u (pre-empt) so vi mt ngt c mc u tin thp hn ang chy. Trong trng hp ny ngt ang chy s b dng v mt khung ngn xp mi (new stack frame) c lu li, thao tc ny ch mt 12 chu k sau ngt c mc u tin cao hn s chy. Khi ngt c mc u tin cao thc hin xong, d liu lu trn
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ngn xp trc s c t ng ly ra (automatically POPed) v ngt u tin thp hn c th tip tc thc hin. 2.4.5.2.2 K thut Tail Chaining trong NVIC Nu mt ngt c mc u tin cao ang chy v ng thi mt ngt c mc u tin thp hn cgn c kch hot, NVIC s dng mt phng php gi l Tail Chaining m bo thi gian tr l ti thiu gia cc ln phc v ngt. Nu hai ngt c nng ln, ngt c mc u tin cao nht s c phc trc v s bt u thc hin ch sau 12 chu k xung nhp k t lc xut hin ngt. Tuy nhin, khi n cui trnh phc v ngt CPU Cortex khng tr v chng trnh ng dng nn, v vy m stack frame ca ngt ny khng c khi phc, thay vo ch c a ch ca hm phc v ngt c mc u tin cao nht k tip c ly v.
Hnh 2.14. p ng thi gian khi hai ngt xy ra ng thi ca Cortex-M3
iu ny ch mt 6 chu k xung nhp v sau trnh phc v ngt k tip c th bt u c thc thi. Vo cui cc ngt ang ch, ngn xp c khi phc v a ch tr v c ly, tip chng trnh ng dng nn c th bt u thc thi ch trong 12 chu k xung nhp. Nu mt ngt c mc u tin thp xut hin trong khi mt ngt khc ang thc thi chun b thot khi trnh phc v ngt, thao tc POP (ly d liu t ngn xp) s b b qua v con tr stack s c cun v gi tr ban u c th tip tc lu tr stack frame ca ngt mi xut hin, s c mt tr 6 chu k xung nhp cho ti khi a ch ca ISR mi c ly v. iu ny to ra mt tr t 7-18 chu k xung nhp trc khi trnh phc v ngt mi c th bt u c thc hin.
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Hnh 2.15. p ng thi gian khi hai ngt xy ra ln lt ca Cortex-M3
Trong mt h thng thi gian thc thng xut hin tnh hung, trong khi mt ngt c mc u tin thp ang c phc v, th ch c mt ngt c mc u tin cao hn xut hin. Nu tnh hung ny xy ra trong qu trnh PUSH d liu ln ngn xp, NVIC s chuyn sang phc v ngt u tin cao hn. Vic PUSH d liu ln ngn xp c tip tc v s c ti thiu 6 chu k xung nhp ti thi im ngt u tin cao hn xut hin, cho ti khi a ch ca ISR mi c ly v.
Hnh 2.16. p ng thi gian khi ngt u tin cao n sau ca Cortex-M3
Sau khi ngt u tin cao hn thc hin xong, ngt u tin thp ban u s c ni ui (tail chain) v bt u thc hin sau 6 chu k xung nhp. 2.4.5.3 Cu hnh v s dng NVIC s dng NVIC cn phi qua ba bc cu hnh. u tin cu hnh bng vector cho cc ngun ngt m bn mun s dng. Tip theo cu hnh cc thanh ghi NVIC cho php v thit lp cc mc u tin ca cc ngt trong NVIC v cui cng cn phi cu hnh cc thit b ngoi vi v cho php ngt tng ng. 2.4.5.3.1 Bng vector ngt (Exception Vector Table) Bng vector ngt ca Cortex bt u di cng ca bng a ch. Tuy nhin bng vector bt u ti a ch 0x00000004 thay v l 0x00000000 nh ARM7
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v ARM9, bn byte u tin c s dng lu tr a ch bt u ca con tr ngn xp (stack pointer).
Hnh 2.17. Bng vector ngt ca Cortex-M3
Mi vector ngt c rng l bn byte v gi a ch bt u ca trnh phc v ngt tng ng, 15 vector ngt u tin l cc ngt c bit ch xy ra trong li Cortex, bao gm reset vector, non-maskable interrupt, qun l fault v error, debug exceptions v ngt timer ca SysTick. Tp lnh Thumb-2 cng bao gm lnh gi dch v h thng (system service call), khi c gi, n s to ra mt ngt c bit. Cc ngt ngoi vi ngi dng bt u t vector 16, c nh ngha bi nh sn xut v c lin kt n thit b ngoi vi. Trong phn mm, bng vector thng c gi trong chng trnh khi ng bng cch nh v cc a ch trnh phc v ngt ti a ch nn ca b nh.
AREA EXPORT __Vectors DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD RESET, DATA, READONLY __Vectors
__initial_sp ; Top of Stack Reset_Handler ; Reset Handler NMI_Handler ; NMI Handler HardFault_Handler ; Hard Fault Handler MemManage_Handler ; MPU Fault Handler BusFault_Handler ; Bus Fault Handler UsageFault_Handler ; Usage Fault Handler 0 ; Reserved 0 ; Reserved 0 ; Reserved 0 ; Reserved
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DCD DCD DCD DCD DCD
SVC_Handler DebugMon_Handler 0 PendSV_Handler SysTick_Handler
; SVCall Handler ;Debug Monitor Handler ; Reserved ; PendSV Handler ; SysTick Handler
Trong trng hp ca b m thi gian SysTick, chng ta c th to ra mt trnh phc v ngt bng cch khai bo mt hm C vi tn ph hp:
void SysTick_Handler (void) { . }
Sau khi cu hnh xong bng vector ngt v nh ngha cc ISR (Interrupt Service Routine), chng ta c th cu hnh NVIC x l ngt ca timer SysTick qua hai bc: thit lp mc u tin ngt v sau cho php ngt ngun. Cc thanh ghi NVIC nm trong vng iu khin h thng ca CortexM3 v ch c th truy cp khi CPU ang chy ch c quyn (privileged mode).
Hnh 2.18. Cc thanh ghi trng thi v iu khin ca NVIC
Cc ngt c bit bn trong Cortex c cu hnh thng qua cc thanh ghi iu khin v thanh ghi cu hnh mc u tin ca h thng, trong khi cc thit b ngoi vi ngi dng c cu hnh bng cch s dng cc thanh ghi IRQ (Interrupt Request). Ngt ca SysTick l mt ngt c bit bn trong Cortex v c x l thng qua cc thanh ghi h thng. Mt s ngt c bit khc bn trong li Cortex lun trng thi cho php, bao gm cc ngt reset v NMI (Non-Maskable Interrupt), tuy nhin ngt ca timer h thng-SysTick li
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khng c kch hot bn trong NVIC. cu hnh ngt cho SysTick, chng ta cn phi cu hnh cho SysTick chy v cho php ngt bn trong SysTick:
SysTickCurrent = 0x9000; SysTickReload = 0x9000; SysTickControl = 0x07; //Start value for the sys Tick counter //Reload value //Start and enable interrupt
Mc u tin ca mi exception (ngt c bit) bn trong Cortex c th c ci t thng qua cc thanh ghi cu hnh mc u tin trong h thng. Mc u tin ca cc exception nh Reset, NMI v hard fault c c nh m bo rng li Cortex s lun lun sn sng cho mt exception c bit trc. Mi exception c mt trng 8-bit nm trong ba thanh ghi v mc u tin ca h thng. Tuy nhin STM32 ch thc hin 16 mc u tin, nh vy ch c bn bit ca trng ny c dng. Mt iu quan trng cn lu l mc u tin c thit lp bi bn bit c trng s cao nht. Mi thit b ngoi vi c iu khin bi cc khi thanh ghi IRQ. Mi ngoi vi c mt bit cho php ngt. Nhng bit nm trn hai thanh ghi cho php ngt c chiu di l 32-bit. Bn cnh cng c cc thanh ghi tng ng cm bt k mt ngun ngt. Ngoi ra NVIC cng bao gm cc thanh ghi bo ch (pending) v kch hot (active) cho php xc nh tnh trng hin ti ca mt ngun ngt.
Hnh 2.19. Cu hnh ngt cho thit b ngoi vi
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Ch : Mi ngun ngt c mt bit cho php bn trong NVIC v khi ngoi vi tng ng. C 16 thanh ghi ci t mc u tin ngt. Mi thanh ghi c chia thnh bn trng c rng l 8-bit cu hnh mc u tin, mi trng c ch nh cho mt vector ngt nht nh. STM32 ch s dng mt na ca trng ny (4-bit c trng s cao nht) thc hin 16 mc u tin ngt. Mc nh cc trng ny xc nh 16 mc u tin vi mc 0 l cao nht v 15 l thp nht. Ngoi ra c th sp sp cc trng u tin thnh cc nhm (group) v nhm con (subgroup). iu ny khng to thm bt k mc u tin no, nhng gip chng ta d qun l cc mc u tin khi chng trnh ng dng c mt s lng ln cc ngt bng cch lp trnh trng PRIGROUP trong thanh ghi iu khin reset v ngt mc ng dng.
Hnh 2.20. Thanh ghi iu khin reset v ngt mc ng dng
Hnh 2.21. Cu hnh mc u tin thnh cc group v subgroup
Trng PRIGROUP gm 3-bit cho php chia trng 4-bit trong cc thanh ghi ci t mc u tin thnh cc nhm v nhm con. V d, tr gi ca PRIGROUP l 5 s to ra hai nhm, mi nhm vi 4 mc u tin. Trong chng trnh ng dng , chng ta c th xc nh mt nhm cc ngt c mc u tin cao v mt nhm c mc u tin thp. Bn trong mi nhm chng ta
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c th xc nh cc mc cho nhm con nh mc thp, trung bnh, cao v rt cao. Nh cp trn vic phn nhm s khng to ra thm mc u tin no nhng cung cp mt ci nhn tru tng v cu trc ngt, iu ny hu ch cho ngi lp trnh khi qun l mt s lng ln cc ngt. Vic cu hnh ngt cho mt thit b ngoi vi cng ging vi cu hnh mt exception bn trong Cortex. Trong trng hp ngt ca ADC, trc tin chng ta phi thit lp vector ngt v cung cp hm phc v ngt-ISR:
DCD ADC_IRQHandler ; void ADC_Handler(void) { }
Sau , ADC phi c khi to v cc ngt phi c cho php trong cc thit b ngoi vi v cc NVIC:
ADC1CR2 = ADC_CR2; //Switch on the ADC and continuous conversion ADC1SQR1 = sequence1; //Select number of channels in sequence conversion ADC1SQR2 = sequence2; //and select channels to convert ADC1SQR3 = sequence3; ADC1CR2 |= ADC_CR2; //Rewrite on bit ADC1CR1 = ADC_CR1; //Start regular channel group, enable ADC interrupt GPIOBCRH = 0x33333333; //Set LED pins to output NVICEnable[0] = 0x00040000; //Enable ADC interrupt NVICEnable[1] = 0x00000000;
2.5 Cc ch nng lng

Trong phn ny, chng ta s xem xt cc ch qun l nng lng bn trong li Cortex. Cc ty chn y v qun l nng lng ca STM32 s c xem xt phn sau. CPU Cortex c mt ch ng (sleep mode), s t li Cortex vo ch nng lng thp ca n v ngng thc thi cc lnh bn trong ca CPU Cortex. Mt phn nh ca NVIC vn c hot ng bnh thng, do ngt to ra t cc thit b ngoi vi ca STM32 c th nh thc li Cortex. 2.5.1 Cch i vo ch nng lng thp ca CPU Cortex Li Cortex c th c t vo ch sleep ca mnh bng cch thc hin lnh WFI (Wait For Interrupt) hoc WFE (Wait For S kin). Trong trng hp
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thc thi lnh WFI, li Cortex s tip tc thc hin v phc v ngt ang ch x l. Khi trnh phc v ngt-ISR kt thc, s c hai kh nng xy ra. Trc tin, CPU Cortex c th tr v t ISR ny v tip tc thc hin chng trnh ng dng nn nh bnh thng. Bng cch t bit SLEEPON EXIT trong thanh ghi iu khin h thng, li Cortex s t ng i vo ch ng mt khi ISR ny kt thc. iu ny cho php mt ng dng nng lng thp (trng thi h thng lun ch sleep khi khng c s kin no xy ra) s hon ton c iu khin bng ngt, li Cortex s c nh thc bi mt s kin (t ngt bn trong hoc bn ngoi CPU Cortex), ch cn thc thi mt on m thch hp v sau li i vo ch sleep, nh vy vi mt m chng trnh ti thiu chng ta c th qun l hiu qu nng lng ca h thng. Ngt WFE cho php li Cortex tip tc thc hin chng trnh t im m n c t vo ch sleep. N s khng nhy n v thc thi mt trnh phc v no. Mt s kin nh thc (wake-up) ch n gin n t mt thit b ngoi vi d cho n khng c kch hot nh l mt ngt bn trong NVIC. iu ny cho php mt thit b ngoi vi c th bo ng thc li Cortex v tip tc thc thi chng trnh ng dng m khng cn mt trnh phc v ngt no. Cc lnh WFI v WFE khng th gi trc tip t ngn ng C, tuy nhin thun li l trnh bin dch cho tp lnh Thumb-2 cung cp sn cc macro c th c s dng nh mt lnh C chun (inline C command): __WFI __WFE Ngoi cc ch nng lng thp SLEEPNOW v SLEEPONEXIT, li Cortex c th pht ra mt tn hiu SLEEPDEEP cho phn cn li ca h thng vi iu khin.
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Hnh 2.22. Thanh ghi iu khin h thng dng cu hnh cc ch ng ca vi x l Cortex
iu ny cho php cc khi chc nng nh PLL (Phase Loop Lock) v thit b ngoi vi c th ngng hot ng, STM32 c th i vo ch nng lng thp nht ca n. 2.5.2 Khi h tr g li CoreSight Tt c cc CPU ARM u trang b h thng g li ring ca n ngay trn chip. CPU ARM7 v ARM9 CPU c ti thiu mt cng JTAG cho php mt cng c g li chun kt ni vi CPU v ti chng trnh vo b nh RAM ni hoc b nh Flash. Cng JTAG cng h tr iu khin ng c bn (thit lp chy tng bc v cc breakpoint v.v) cng nh c th xem ni dung ca cc v tr trong b nh. Ngoi ra CPU ARM7 v ARM9 cn c th cung cp mt b theo di thi gian thc (real-time trace) thng qua mt thit b ngoi vi g li c gi l ETM (embedded trace macro cell). Trong khi h thng g li ny hot ng tt, th n bc l mt s hn ch. JTAG ch c th cung cp thng tin g li cho cng c pht trin (nh Keil, IAR) khi CPU ARM dng li, do khng c kh nng cp nht thi gian thc. Ngoi ra, s lng ca breakpoints phn cng c gii hn ti hai im, mc d tp lnh ARM7 v ARM9 h tr mt lnh breakpoint, c th c chn vo m chng trnh bng cng c pht trin (gi l soft breakpoints). Tng t vi JTAG, b theo di thi gian thcETM phi c trang b bi cc nh sn xut vi chi ph b sung. Do vy ETM khng phi lc no cng c h tr. Vi li Cortex mi, ton b h thng g li gi l CoreSight c gii thiu.
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Hnh 2.23. H thng g li CoreSight bn trong Cortex
H thng g li Cortex CoreSight s dng giao din JTAG hoc SWD (Serial Wire Debug). CoreSight cung cp chc nng chy kim sot v theo di. N c th chy khi STM32 ang mt ch nng lng thp. y l mt bc ci tin ln v chun g li JTAG. H thng g li CoreSight c mt cng truy cp g li cho php kt ni vi vi iu khin bng cng c JTAG. Cng c g li c th kt ni bng cch s dng chun giao din JTAG 5 chn hoc giao din 2 dy ni tip. Ngoi cc tnh nng g li ca JTAG, CoreSight c cha mt theo di d liu v mt ETM. Trong thc t, c cu g li CoreSight trn STM32 cung cp mt phin bn thi gian thc c ci tin ca chun g li JTAG. H thng g li STM32 CoreSight cung cp 8 breakpoints phn cng c th c t v xa trong khi CPU Cortex ang chy. Ngoi ra b theo di Data Watch cho php bn xem cc ni dung ca cc v tr nh trong khi CPU Cortex ang chy. H thng CoreSight c th duy tr trng thi hot ng khi li Cortex i vo ch ng. Ngoi ra cc timer ca STM32 c th c tm dng khi h thng CoreSight tm dng CPU. iu ny cho php chng ta thc thi tng bc m chng trnh v gi cho timer ng b vi h thng. Vi cc lnh thc thi trn
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CPU Cortex, CoreSight ci thin ng k kh nng g li thi gian thc ca STM32 so vi CPU ARM7 v ARM9 trc kia, trong khi vn s dng cng mt phn cng chi ph thp.
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Chng 3 PHN CNG C BN CHO MT THIT K THC T

Mt thit k c bn vi STM32 cn rt t cc ph kin bn ngoi. STM32 c th hot ng ch cn mt khi cp ngun. STM32 c sn mt b dao ng ni RC v mt mch reset ni. Phn ny s xem xt cc phn cng chnh cn xy dng mt thit k thc t.
3.1 Kiu ng gi chip v kiu chn linh kin

Cc bin th ca dng Access, USB, Performance v Connectivity ca STM32 c thit k ph hp vi nhiu kiu ng gi, cho php nng cp phn cng mt d dng m khng cn phi thit k li PCB (Printed Circuit Board). Tt c cc vi iu khin STM32 u c sn dng ng gi LQFP, t 48 chn n 144 chn.
3.2 Ngun cp in
STM32 i hi mt ngun cung cp trong khong 2.0V n 3.6V. Mt b n p ni c s dng to ra ngun cung cp 1.8V cho li Cortex. STM32 c hai ngun cung cp nng lng ty chn khc. B RTC (Real Time Clock) v mt vi thanh ghi c t trong mt min nng lng ring bit, n c th c nui bi pin duy tr d liu trong khi phn cn li ca STM32 ang trong trng thi ng su (deep sleep mode). Nu thit k khng c s dng pin sao lu, th chn VBAT phi c kt ni vi VDD.
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Hnh 3.1. Cc min nng lng bn trong STM32
Ty chn cung cp nng lng th hai c s dng cung cp cho ADC. Nu ADC c s dng, ngun in chnh VDD c gii hn trong phm vi 2.4V n 3.6V. i vi chip ng gi 100 chn, khi ADC c thm chn in p tham kho VREF+ v VREF-. Chn VREF- phi c kt ni vi VDDA v VREF+ c th thay i t 2,4V n VDDA. Tt c cc kiu ng gi chp cn li th in p tham kho c kt ni bn trong vi cc chn cung cp in p ADC . Mi ngun cung cp nng lng cn mt t chng nhiu i km.
Hnh 3.2. Cch b tr t chng nhiu cho STM32
3.3 Mch Reset

STM32 cha mt mch reset ni, mch ny gi cho chip trng thi reset cho ti khi no VDD vn cn di mc 2.0V.
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Hnh 3.3. c tnh ca mch reset bn trong STM32
B POR (Power On Reset) v PDR (Power Down Reset) m bo x l ch chy vi mt ngun cp in n nh, v khng cn bt k mt mch reset bn ngoi.
3.3.1 S mch phn cng c bn

Mt mch reset bn ngoi khng cn thit trong thit k ca STM32. Tuy nhin, trong qu trnh pht trin chn nRST c th c kt ni vi mt nt reset n gin, ng thi chn nRST cng c kt ni n cng JTAG, cng c pht trin c th to ra tn hiu reset vi iu khin. STM32 c mt s cc ngun reset ni c th pht hin cc iu kin vn hnh b li v chng ta s xem xt k hn trong mc tnh nng an ton ca STM32.
Hnh 3.4. Phn cng ti thiu cho mt thit k thc t da trn STM32
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Chng 4 KIN TRC H THNG CA ARM CORTEX

STM32 gm nhn Cortex kt ni vi b nh FLASH thng qua ng bus lnh chuyn bit. Cc bus d liu(Cortex Data busses) v h thng(Cortex System busses) c kt ni ti ma trn busses tc cao( ARM Advanced High Speed Busses- AHB). SRAM ni kt ni vi AHB v ng vai tr l b DMA. Cc thit b ngoi vi c kt ni bng 2 h thng bus ngoi vi tc cao( APB-ARM Advanced Peripheral Busses). Cc bus APBs thng qua cc bus cu ni AHB-APBs kt ni vo h thng AHB. Ma trn bus AHB s dng xung nhp ng h bng vi xung nhp ca nhn Cortex. Tuy nhin thng qua b chia tn s AHB c th hot ng tn s thp hn nhm tit kim nng lng. Mt iu quan trng cn nh l APB2 v APB1 hot ng tn s khc nhau, APB2 hot ng 72MHz trong khi APB1 gii hn hot ng 36MHz. C nhn Cortex v b DMA u ng vai tr l bus master. Khi c tc v x l song song th b phn x s quyt nh nhn Cortex hay b DMA s c quyn truy cp vo SRAM, APB1 v APB2. Tuy nhin nh trnh by mc DMA, b phn x lun m bo 2/3 thi gian truy cp s dnh cho b iu khin DMA and 1/3 dnh cho nhn Cortex.
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Cu trc bus ni cung cp ng truyn chuyn bit dnh cho tp lnh thc thi v ma trn bus ng d liu cho nhn Cortex and b iu khin DMA truy cp ti nguyn trn vi x l.
4.1 Cu trc b nh
Bn cnh h thng bus ni a dng STM32 cn cung cp 4Gbytes khng gian b nh lin tc dnh cho lp trnh.V STM32 l l nhn vi iu khin da trn nn tng Cortex nn phi tun theo chun phn vng b nh ca Cortex.B nh c bt u t a ch 0x00000000 .On-chip SRAM bt u t a ch 0x20000000 v tt c SRAM ni u c b tr im bt u vng bit band. Vng nh thit b ngoi vi c nh x t a ch 0x40000000 v vng bit band. Cc thanh ghi iu khin ca nhn Cortex c nh x t a ch 0xE0000000.
Vng nh dnh cho flash c chia nh thnh 3 vng. Vng th nht gi l User Flash bt u t a ch 0x00000000. K tip l System Memory hay cn gi l vng nh ln. Vng ny c ln 4Kbytes thng thng s c nh sn xut ci t bootloader. Cui cng l vng nh nh bt u t a ch 0x1FFFFF80 cha thng tin cu hnh dnh cho STM32. Bootloader thng c dng ti chng trnh thng qua USART1 v cha vng User Flash.
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kch hot bootloader ca STM32 ngi dng phi thit lp cc chn BOOT0 v BOOT1 mc in p thp v cao tng ng. Khi sau khi STM32 c khi ng, chng trnh s t bootloader vo a ch 0x00000000 v thc thi n thay thi thc thi chng trnh ca ngi dng User Flash. giao tip vi bootloader, ST cung cp mt chng trnh chy PC, chng trnh ny c kh nng ghi, xa vng nh User Flash. Ngoi ra chng ta c th cu hnh cc chn bootpins nh x SRAM ni vo a ch 0x00000000, cho php ti xung v thc thi chng trnh ngay ti SRAM. iu ny lm tng tc ti chng trnh v hn ch s ln ghi vo Flash.
4.2 Ti a hiu nng

Ngoi vic h tr 2 b to xung nhp ngoi STM32 cung cp thm 2 b to xung nhp ni. Sau khi reset ng h to xung ca nhn Cortex, b to xung nhp tc cao( High Speed Internal Oscillator) hot ng mc thp 8MHz. B to xung ni cn li l Low Speed Internal Oscillator hot ng mc 32768KHz. B xung nhp tc thp ny thng c dng cho ng h thi gian thc v watchdog.
Hnh 4.1 STM32 bao gm 2 b to xung nhp ni v 2 b to xung nhp ngoi thm vo l b vng kha pha( Phase Lock Loop-PLL).
Nhn Cortex c th c cp xung nhp t b to dao ng ni v ngoi, ng thi t PLL ni. Nh trn hnh 4.1, PLL c th ly dao ng t b to dao ng tc cao ni v ngoi. C mt vn l i vi b to dao ng ni tc
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cao xung nhp khng hot ng chnh xc 8MHz do khi s dng cc thit b ngoi vi nh: giao tip serial hay s dng nh thi thi gian thc th nn dng b to dao ng ngoi tc cao. Tuy vy, cho d s dng b dao ng no i na th nhn Cortex lun phi s dng xung nhp to ra t b PLL. Tt c thanh ghi iu khin PLL v cu hnh bus u c b tr nhm RCC ( Reset and Clock Control).
4.2.1 Vng Kha Pha(Phase Lock Loop)

Sau khi h thng reset STM32 nhn xung nhp t b to dao ng HIS. Ti thi im cc b to dao ng ngoi s b tt. Bc u tin STM32 hot ng mc xung nhp cao nht l bt b to dao ng HSE v ch cho n khi i vo hot ng n nh.
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on m sau m t cch cu hnh CPU ca STM32 hot ng mc xung nhp cao nht
RCC->CR |= 0x10000; //HSE on //wait until HSE stable While(!(RCC->CR & 0x0020000)) {};
B to dao ng ngoi c th c kch hot thng qua cc thanh ghi iu khin RCC_Control. S c 1 bit trng thi c bt khi chng i vo hot ng n nh. Mt khi b to dao ng ngoi hot ng n inh, n c th c chn l u vo cho b PLL. Xung nhp ra c to bi PLL c xc nh bng cch thit lp cc bi s nguyn trong thanh ghi cu hnh RCC_PLL. Trong trng hp xung nhp u vo ca PLL l 8MHz khi cn cu hnh bi s nhn cho PLL l 9 to xung nhp 72MHz u ra. Khi b to dao ng ngoi v PLL hot ng n nh, bit iu khin trng thi s bt ln, khi dao ng c to bi PLL s c cp cho nhn CPU Cortex ca STM32.
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on m cu hnh STM32 s dng dao ng t PLL

//HSE clock, PLLx9 RCC->CFGR = 0x001D0000; //Enable PLL RCC->CR |= 0x01000000; While( !(RCC->CR & 0x02000000)); //Set the remaining control fields RCC->CR |= 0x00000001; //Set the remaining configuration fields RCC->CFGR |= 0x005D0402;
4.2.1.1 Cu hnh cho bus

Khi PLL c chn l b to dao ng cho h thng, Cortex CPU s hot ng mc 72MHz. cho ton b cc phn cn li ca h thng hot ng mc ti u ngi dng cn phi cu hnh AHB v APB thng qua cc thanh ghi cu ni.
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//Enable clocks to the AHB,APB1 and APB2 busses AHBENR = 0x00000014; RCC->APB2ENR = 0x00005E7D; RCC->APB1ENR = 0x1AE64807; //Release peripheral reset line on APB1 and APB2 buses RCC->APB2RSTR = 0x00000000; RCC->APB1RSTR = 0x00000000;
4.2.2 Flash Buffer

Khi xem xt kin trc h thng ca STM32 chng ta c th thy nhn Cortex kt ni vi Flash thng qua ng d liu chuyn bit I-Bus. Bus d liu ny hot ng cng tn s vi CPU, do vy nu CPU ly dao ng t PLL th bus d liu s hot ng mc xung nhp cao nht 72Mhz. Cortex CPU s truy cp vo Flash c mi 1.3ns. Khi mi hot ng, nhn STM32 s dng b to dao ng ni, do thi gian truy cp Flash l khng ng k. Tuy nhin khi PLL c kch hot v s dng to dao ng cho CPU, thi gian truy cp vo Flash rt chm khong 35ns, iu ny lm gim hiu nng ca h thng. Cortex CPU hot ng xung nhp cao nht 72MHz vi thi gian trng thi ch l 0 b nh Flash c trang b b 2 nh m 64-bit. Hai b nh m ny c th thc thi cc lnh c ghi d liu 64-bit trn Flash v chuyn cc lnh 16 hay 32 bit cho nhn Cortex thc thi. K thut ny hot ng tt i vi cc lnh thuc tp lnh Thumb-2 v cc tp lnh c kh nng d bo ch dn(Branch Prediction) ca Cortex pipeline. Trong qu trnh hot ng bnh thng chng ta khng cn quan tm n b m ca Flash. Tuy nhin chng ta nn chc chn rng cc b m ny phi c kch hot trc khi s dng PLL nh l ngun xung nhp ca h thng. H thng b m Flash c qun l bi cc thanh ghi cu hnh Flash. Cng vi vic kch hot b m tin x l,chng ta phi iu chnh s trng thi ch khi Flash c 8 bytes lnh t b nh Flash. tr c thit lp nh sau: 0< SYSCLK <24MHz 0 waitstate 24< SYSCLK <48MHz 1 waitstate 48<SYSCLK <72MHz 2 waitstate
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Thi gian trng thi ch ny gia b m tin x l vi b nh Flash khng tc ng n nhn Cortex CPU. Khi CPU ang thc thi cc lnh na u ca b m th cc lnh na sau ca b m s c tin x l v ti ln nhn s l ngay tip theo, iu ny lm ti u ha hiu nng x l ca Cortex CPU.
4.2.3 Direct Memory Access

Mc d c th s dng chnh nhn Cortex trao i d liu gia cc thit b ngoi vi v SRAM ni, tuy nhin chng ta c th hon ton s dng c ch t ng cho vic ny vi b qun l DMA. STM32 c 7 knh DMA c lp dng chuyn d liu t: b nh sang b nh, ngoi vi ti b nh, b nh ti ngoi vi v ngoi vi ti ngoi vi. Trong trng hp trao i d liu gia b nh v b nh, tc d liu ph thuc tc ca knh DMA qun l n. Cn vi giao tip d liu vi ngoi vi, th tc ph thuc vo b iu khin ca ngoi vi v hng d liu di chuyn. Cng vi chuyn d liu theo lung, b DMA ca STM32 cn h tr b m vng. V hu ht cc ngoi vi hin nay khng c b nh FIFO, mi b DMA s lu d liu vo trong b nh SRAM. B DMA ca STM32 c thit k dnh cho trun cc loi d liu tc cao v nh.
Mi thao tc b nh DMA bao gm 4 giai on.
Qu trnh truyn d liu gm 4 giai on: ly mu v phn x, tnh ton a ch, truy cp ng truyn, v cui cng l hon tt. Mi giai on thc hin trong 1 chu k lnh, ring truy cp ng truyn mt 5 chu k lnh. giai
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on truy cp ng truyn thc cht l giai oan d liu c truyn, mi t(word) s mt 3 chu k lnh. B DMA v CPU c thit k cng lc c th hot ng m khng tranh chp ti nguyn ln nhau. Gia 2 knh DMA khc nhau, s c s u tin mc hot ng, da trn b phn x s quyt nh knh DMA c mc u tin cao hn s c ly ti nguyn trc. Nu 2 knh DMA c cng mc u tin, li ang trng thi ch truy cp ti nguyn, th knh DMA c s th t nh hn s c s dng ti nguyn trc.
B DMA c thit k cho truyn d liu tc v kch thc nh. B DMA ch s dng bus d liu khi giai on truy cp ng truyn.
B DMA c th thc hin vic phn x ti nguyn v tnh ton a ch trong khi b DMA khc ang giai on truy cp ng trun nh m t hnh trn. Ngay khi b DMA th nht kt thc vic truy cp ng truyn, b DMA 2 c th ngay lp tc s dng ng trun d liu. iu ny va lm tng tc truyn d liu, ti a ha vic s dng ti nguyn.
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giai on Bus Access CPU s c 3 chu k rnh. Khi chuyn d liu t vng nh sang vng nh iu ny s m bo nhn Cortex-M3 s dng 60% dung lng ca ng truyn d liu cho d b DMA vn hot ng lin tc.
Trong trng hp trao i d liu t vng nh sang vng nh mi knh DMA ch s dng ng truyn d liu giai on Bus Access v 5 chu k CPU chuyn 2 bytes d liu. Trong 1 chu k c v 1 chu k ghi, 3 chu k cn li c b tr xen k nhm gii phng ng d liu cho nhn Cortex. iu c ngha l b DMA ch s dng ti a 40% bng thng ca ng d liu. Tuy nhin giai on Bus Access hi phc tp trng hp d liu truyn gia thit b ngoi vi hoc gia ngoi vi v b nh do lin quan n AHB v APB. Trao i trn bus AHB s dng 2 chu k xung nhp ca AHB, trn bus APB s s dng 2 chu k xung nhp ca APB cng thm 2 chu k xung nhp ca AHB. Mi ln trao i d liu, b DMA s s dng bus AHB, bus APB v 1 chu k xung nhp AHB. V d chuyn d liu t bus SPI ti SRAM chng ta s s dng:
SPI n SRAM s dung DMA = SPI transfer(APB) + SRAM transfer(AHB) + free cycle(AHB) = (2 APB cycles + 2 AHB cycles) + (2 AHB cycles) + (1 AHB cycle) = (2 APB cycles) + (5 AHB cycles)
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* Lu : Qu trnh trn ch p dng cho cc nhn Cortex s dng ng I-bus np lnh cho nhn x l.
DMA Interrupt Control DMA Channel 1 7
STM32 c 7 b DMA c lp vi nhau
Vic s dng DMA rt n gin. u tin l kch hot ng h xung nhp

RCC->AHBENR |= 0x00000001; //enable DMA clock
Mt khi c cp ngun khi DMA s c iu khin bi 4 thanh ghi in khin. 2 thanh ghi iu khin a ch ch v ngun ca ngoi vi v vng nh. Kch thc d liu truyn v cu hnh tng quan DMA c lu trong 2 thanh ghi cn li.
DMA Channel Configuration Number of Data Peripheral Address Memory Address
Mi b DMA c 4 thanh ghi iu khin, 3 ngun tn hiu interrupt: hon tt, hon tt mt na, li.
Mi knh DMA c th c gn vi mt mc u tin: rt cao, cao, trung bnh v thp. Kch c ca d liu c truyn c th iu chnh ph hp cho ngoi vi v vng nh. V d vi b nh kch c n v d liu l 32-bit(mt 3 chu k truyn), chuyn n ngoi vi UART l 4 n v d liu 8-bit mt 35 chu k thay v 64 chu k nu chuyn tng n v d liu 8-bit ring r. Chng ta c th tng a ch ch hoc ngun trong qu trnh chuyn d liu. V d khi
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ly d liu t b ADC, chng ta c th tng a ch vng nh ln lu cc gi tr t ADC vo mng d liu. Trn thanh ghi iu khin c Transfer Direction Bit cho php ta cu hnh hng d liu t ngoi vi vo vng nh hay ngc li. cu hnh chuyn d liu t vng nh sang vng nh trn SRAM, ta kch hot bit 14 trn thanh ghi iu khin. Ngoi vic s dng DMA vi ch vng lp ch, chng ta c th dng ngt theo di qu trnh chuyn d liu. C ba loi ngt h tr cho DMA: hon thnh chuyn d liu, hon thnh mt na, v li. Sau khi cu hnh hon tt, chng ta kch hot Channel Enable Bit thc hin qu trnh chuyn d liu. V d sau m t qu trnh chuyn d liu gia 2 vng nh trn SRAM:
SRAM DMA SRAM
DMA_Channel1->CCR = 0x00007AC0; //cu hnh mem to mem DMA_Channel1->CPAR = (unsigned int)src_array;//a ch ngun DMA_Channel1->CMAR=(unsigned int)dst_array;//a ch ch DMA_Channel1->CNDTR=0x000A;//s lng d liu TIM2->CR1 = 1; //khi to thi gian DMA_Channel1->CCR |= 0x00000001;//kch hot qu trnh chuyn d liu While( !(DMA->ISR & 0x00000001); //ch cho n khi hon thnh TIM2->CR1 = 0; //ngng m TIM2->CNT = 0; // thit lp gi tr m bng 0 TIM2->CR1 = 1; //bt u m li for(index = 0;index < 0x000A;index++) dst_array[index]=src_array[index]; TIM2-CR1 = 0;
on m trn, ta s dng TIM2 o thi gian(tnh theo chu k) chuyn d liu t 2 vng nh kch thc 10 word. Vi DMA qu trnh chuyn tiu tn 220 chu k, vi cch s dng CPU tiu tn 536 chu k.
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Mi knh DMA c gn vi ngoi vi nht nh. Khi c kch hot, cc thit b ngoi vi s iu khin b DMA tng ng.
Kiu truyn d liu t b nh sang b nh thng hay c dng khi to vng nh, hay chp cc vng d liu ln. Phn ln tc v DMA hay c s dng chuyn d liu gia ngoi vi v vng nh. s dng DMA, u tin ta khi to thit b ngoi vi v kch hot ch DMA trn thit b ngoi vi , sau khi to knh DMA tng ng.
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Chng 5 NGOI VI
Chng ny s gii thiu cc thit b ngoi vi trn cc phin bn STM32. tin theo di, chng ti chia ra thnh 2 loi: ngoi vi a dng v ngoi vi giao tip. Tt c ngoi vi trn STM32 c thit k v da trn b DMA. Mi ngoi vi u c phn iu khin m rng nhm tit kim thi gian x l ca CPU.
5.1 Ngoi vi a dng

Ngoi vi a dng trn STM32 bao gm: cc cng I/O a dng, b iu khin ngt ngoi, b chuyn i ADC, b iu khin thi gian a dng v m rng, ng h thi gian thc, v chn tamper.
5.1.1 Cc cng I/O a dng

STM32 c 5 cng I/O a dng vi 80 chn iu khin.
PIN Configuration GPIO Alternate Function External Function
Mi chn iu khin c th cu hnh nh l GPIO hoc c chc nng thay th khc. Hoc mi chn c th cng lc l ngun ngt ngoi.
Cc cng I/O c nh s t A->E v mc p tiu th 5V. Nhiu chn ngoi c th c cu hnh nh l Input/Output tng tc vi cc thit b ngoi vi ring ca ngi dng nh USART hay I2C. Thm na c th cu hnh cc chn ny nh l ngun ngt ngoi kt hp vi cng GPIO khc.
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GPIO Configuration Low Configuration High Input Data Output Data Bit Set/Reset Reset Configuration Lock
Mi cng GPIO u c 2 thanh ghi 32-bit iu khin. Nh vy ta c 64-bit cu hnh 16 chn ca mt cng GPIO. Nh vy mi chn ca cng GPIO s c 4 bit iu khin: 2 bit s quy nh hng ra vo d liu: input hay output, 2 bit cn li s quy nh c tnh d liu.
Configuration Mode Analog Input Input Floating(Reset State) Input Pull-up Input Pull-down Output Push-Pull Output Open-drain AF Push-pull AF Open-Drain 1 1 0 0 1 1 0 0 0 1 0 10:2MHz 1 11:50MHz 00:Reserved 01:10MHz CNF1 0 0 CNF0 0 1 00 MOD1 MOD0
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Sau khi cng c cu hnh, ta c th bo v cc thng s cu hnh bng cch kch hot thanh ghi bo v. Trong thanh ghi ny, mi chn trong cng u c mt bit bo v tng ng trnh cc thay i v cc 4 bit cu hnh. kch hot ch bo v, ta ghi ln lt gi tr 1,0,1 vo bit 16:
uint32_t tmp = 0x00010000; //bit 16 tmp |= GPIO_Pin; //chn cn c bo v /* Set LCKK bit */ GPIOx->LCKR = tmp; //ghi gi tr 1 vo bit 16 v chn cn bo v /* Reset LCKK bit */ GPIOx->LCKR = GPIO_Pin; //ghi gi tr 0 vo bit 16 /* Set LCKK bit */ GPIOx->LCKR = tmp; //ghi gi tr 1 vo bit 16
Sau c li bit 16 lin tc 2 ln, nu gi tr tr v ln lt l 0 v 1 th thit lp kha hon thnh

tmp = GPIOx->LCKR; tmp = GPIOx->LCKR;
d dng c v ghi d liu trn cng GPIO, STM32 cung cp 2 thanh ghi Input v Output data. K thut bit banding c h tr nhm thc hin cc thao tc bit trn thanh ghi d liu. Thanh ghi 32-bit Set/Reset, vi 16 bit cao nh x ti mi chn ca cng iu khin reset khi c thit lp gi tr 1. Tng t vy 16 bit thp iu khin Set khi c gn gi tr 1. 5.1.1.1 Chc nng thay th(Alternate Function)
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Chc nng thay th cho php ngi dng s dng cc cng GPIO vi cc ngoi vi khc. thun tin cho thit k phn cng, mt thit b ngoi vi c th c nh x ti mt hay nhiu chn ca vi x l STM32.
EVENT CONTROL Remap&Debug I/O Config
S dng cc tnh nng thay th ca STM32 c iu khin bi cc thanh ghi Remap & Debug I/O. Mi thit b ngoi vi( USART, CAN, Timers, I2C v SPI) c 1 hoc 2 trng bit iu khin nh x ti cc chn ca vi iu khin. Mt khi cc chn c cu hnh s dng chc nng thay th, cc thanh ghi iu khin GPIO s c s dng iu khin cc chc nng thay th thay v tc v I/O. Cc thanh ghi Remap cn iu khin b JTAG. Khi h thng khi ng, cng JTAG c kch hot tuy nhin chc nng theo di d liu(data trace) vn cha khi ng. JTAG khi c th chuyn sang ch debug, xut d liu theo di ra ngoi, hoc n gin ch s dng nh cng GPIO. 5.1.1.2 Event Out Nhn Cortex c kh nng to xung nhp nh thc cc khi vi iu khin bn ngoi thot khi trng thi tit kim nng lng. Thng thng, xung nhp ny s c ni vi chn Wake up ca vi x l STM32 khc. Lnh SEV Thumb-2 khi c thc thi s to ra xung nhp Wake up ny. Thanh ghi iu khin s kin ca STM32 cu hnh chn GPI no s xut xung nhp Wake up. 5.1.2. Ngt ngoi(EXTI) B iu khin ngt ngoi c 19 ngt v kt ni vo bng vector ngt thng qua b NVIC. 16 ngt c kt ni thng qua cc chn ca cng GPIO v to ngt khi pht khi c xung ln(rasing) hoc xung (falling) hoc c hai. 3 ngt cn li c ni vi RTC alarm, USB wake up v Power voltage detect.
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NVIC cung cp bng vector ngt ring bit dnh cho cc ngt t 0-4, ngt RTC, ngt Power detect v ngt USB wake up. Cc ngt ngoi cn li chia lm 2 nhm 5-10, v 11-15 c cung cp thm 2 bng ngt b sung. Cc ngt ngoi rt quan trng trong qun l tiu th nng lng ca STM32. Chng c th c s dng nh thc nhn vi x l t ch STOP khi c 2 ngun to xung nhp chnh ngng hot ng. EXTI c th to ra cc ngt thot ra khi s kin Wait ca ch Interrupt v thot khi s kin Wait ca ch Event.
External Interrupt Configuration 1 Configuration 4
16 ngt ngoi c th c nh x ti bt k chn no ca vi x l thng qua 4 thanh ghi cu hnh iu khin. Mi ngt c iu khin bi trng 4 bit, on m sau m t cch cu hnh ngt cho chn GPIO
//Map the external interrupts to port pins AFIO->EXTICR[0] = 0x0000000; //Enable external interrupt sources EXTI->IMR = 0x00000001; //Enable wake up event EXTI->EMR = 0x00000000;
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//Select falling edge trigger souces EXTI->FTSR = 0x00000001; //Select resing edge trigger sources EXTI->RTSR = 000000000; //Enable interrupt souces in NVIC NVIC->Enable[0] = 0x00000040; NVIC->Enable[1] = 0x00000000;
5.1.3 ADC STM32 c th c 2 b chuyn i tn hiu tng t sang tn hiu s ty vo cc phin bn. B ADC c th c cung cp ngun ring t 2.4V n 3.6V. Ngun cung cp cho b ADC c th c kt ni trc tip hoc thng qua cc chn chuyn bit. B ADC c phn gii 12-bit v tn sut ly mu l 12Mhz. Vi 18 b ghp knh, trong 16 knh dnh cho cc tn hiu ngoi, 2 knh cn li dnh cho cm bin nhit v vn k ni.
5.1.3.1 Thi gian chuyn i v nhm chuyn i B ADC cho php ngi dng c th cu hnh thi gian chuyn i ring bit cho tng knh. C 8 mc thi gian chuyn i ring bit t 1.5 n 239.5 chu k.
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Mi b ADC c 2 ch chuyn i: thng thng(regular) v injected. ch regular cho php mt hay mt nhm cc knh kt hp vi nhau thc thi tc v chuyn i. Mt nhm knh ti a c th gm 16 knh. Th t chuyn i trong nhm c th c cu hnh bi phn mm, v trong mt chu k chuyn i ca nhm, mt knh c th c s dng nhiu ln. Chuyn i regular c th c kch hot bng s kin phn cng ca Timer hay ngt ngoi EXTI 1. Mt khi c kch hot, ch Regular c thc thi chuyn i lin tc( continuos convertion) hoc khng lin tc.
Mt nhm knh hot ng ch Regular c th lin tc thc hin qu trnh chuyn i, hoc ch chuyn i khi nhn tn hiu kch hot.
Khi mt nhm cc knh hon thnh vic chuyn i, kt qu c lu vo thanh ghi kt qu v tn hiu ngt c to. V b ADC c phn gii l 12 bit v c lu trong thanh ghi 16 bit do d liu c th c canh l tri hoc phi.
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D liu c th c canh l tri hoc phi trong thanh ghi kt qu
B ADC1 c ring knh DMA chuyn d liu t thanh ghi kt qu sang vng nh. Vi phng php ny, d liu t kt qu chuyn i ca mt nhm cc knh ADC s c chuyn ton b ln vng nh ngay trc khi ngt c pht sinh.
ADC1 s dng DMA chuyn d liu kt qu ca mt nhm cc knh vo vng nh c khi to trn SRAM
Loi ADC th 2 l Injected ADC. Injected ADC l dy cc knh ADC, ti a l 4 knh. Injected ADC c th c kch hot bng phn mm hoc tn hiu phn cng. Khi c kch hot, Injected ADC vi mc u tin cao hn s tm ngng cc knh Regular ADC ang hot ng. Cc knh Regular ADC ch tip tc hot ng sau khi Injected ADC thc thi xong. V cu hnh hot ng ca Injected tng t nh ca Regular, tuy nhin mi knh chuyn i ca Injected c thanh ghi d liu ADC_JDRx tng ng.
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Tng t nh Regular ADC, d liu thanh ghi ADC_JDRx c th c canh l tri hoc phi, km theo l du nu d liu m
5.1.3.2 Analogue WatchDog Ngoi 2 ch Regular v Injected, khi ADC cn c b sung thm Analogue WatchDog. Khi ny h tr pht hin d liu tng t nm ngoi vng hot ng bnh thng ca mt knh ADC cho trc. Khi c cu hnh ngng trn v ngng di, nu tn hiu tng t u vo nm ngoi vng trn, th ngt s c pht sinh. Ngoi vic gim st tn hiu in p thng thng, Analogue Watchdog c th c dng pht hin in p khc 0 V.
Analogue Watchdog c th dng gim st mt hay nhiu knh ADC vi vng ngng c cu hnh bi ngi dng
5.1.3.3 Cu hnh ADC

ADC Status and Control Sample time Injection Offset Watchdog Thresholds Sequence Registers Results Registers
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Cc thanh ghi ca khi ADC c tch ra thnh 6 nhm thanh ghi, trong cc thanh ghi Status v Control xc nh ch hot ng ca ADC.
C hai thanh ghi iu khin ADC_CR1 v ADC_CR2 cu hnh hot ng ca khi ADC.
Hai thanh ghi iu khin cu hnh hot ng ca khi ADC ADC1->CR2 = 0x005E7003; //Switch on ADC1 and enable continuous conversion ADC1->SQR1 = 0x0000; //set sequence length to one ADC1->SQR2 = 0x0000; //select conversion on channel zero ADC1->SQR3 = 0x0001; ADC1->CR2 = 0x005E7003; //rewrite on bit NVIC->Enable[0] = 0x00040000; //enable ADC interrupt NVIC->Enable[1] = 0x00000000;
hm x l ngt ADC
Void ADC_IRQHandler(void) { GPIOB->ODR =ADC1->DR << 5; //Copy ADC result to port B }
Hoc chng ta c th s dng DMA thay v ngt

DMA_Channel1->CCR = 0x00003A28; //Circular mode, peripheral and memory increased disable //Load destination address into peripheral register, GPIO port data register DMA_Channel1->CMAR = (unsigned int) 0x04001244C; DMA_Channel1->CNDTR = 0x0001; //number of words to transfer DMA_Channel1->CCR = 0x00000001;//Enable the DMA transfer
Chng ta kch hot ch DMA ca khi ADC

ADC1->CR2 |= 0x0100;
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5.1.3.4. Dual mode mt s phin bn, ST cung cp 2 khi ADC nhm p ng cc tc v phc tp hn
Khi hot ng ch Dual, khi ADC2 ng vai tr ph i vi ADC1. Khi kt hp ADC1 v ADC2, chng ta s c 8 ch hot ng
5.3.1.4.1. C hai khi ADC cng hot ng cng ch Regular hoc Injected
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Khi hot ng ch ny, cng lc khi ADC1 v ADC2 s chuyn i d liu t 2 knh khc nhau. V d trong cc ng dng cn theo di cng lc in p v cng dng.
5.3.1.4.2. C hai khi cng hot ng 2 ch Regular v Injected xen k
Nh hnh trn m t, c hai khi ADC hot ng cng mt ch ti cng thi im. Khi ch Injected c kch hot, c khi ADC1 v ADC2 tm thi ri trng thi Regular thc thi chuyn i cc knh trong ch Injected.
5.3.1.4.3. Hot ng xen k nhanh v chm Regular
ch xen k nhanh, mt knh c th lin tc chuyn i bi hai khi ADC, thi gian nh nht kch hot ln chuyn i k tip l 7 chu k xung nhp ca ADC. ch xen k chm khong cch thi gian ti thiu l 14 chu k
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xung nhp. Hai ch kt hp ny lm tng hiu sut chuyn i ca khi ADC.

5.3.1.4.4. Ch kch hot thay th
Ban u phn cng s kch hot knh u tin trong nhm chuyn i Injected ca khi ADC1, sau s kch hot tip nhm Injected ca ADC2. C nh vy lin tc v xen k.
5.3.1.4.5. Kt hp ng b ha Regular v kch hot thay th
Nh ta thy trn, vic chuyn i ch Regular c c hai khi ADC1 v ADC2 thc thi ng thi, ng b. Khi c kch hot bi hardware, nhm Injected ca khi ADC1 c thc thi, ch Regular tm thi ngng v hot ng tr li khi tc v thuc nhm Injected hon tt.
5.3.1.4.6. Kt hp ng b ha Injected v xen k Regular
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Hai khi ADC1 v ADC2 hot ng ch Regular xen k nhau th c kch hot chuyn sang hot ng ch ng b Injected. Lu l: khi ch xen k Regular, c hai knh ADC1 v ADC2 c th chuyn i chung trn cng mt knh, tuy nhin khi sang ch ng b Injected, th knh c s dng ca ADC1 v ADC2 phi khc nhau. 5.1.4. B nh thi a nhim v nng cao STM32 c bn khi nh thi. Timer1 l khi nng cao dnh cho iu khin ng c. 3 khi cn li m nhim chc nng a nhim. Tt c chng u c chung kin trc, khi nng cao s c thm cc c tnh phn cng ring bit. 5.1.4.1. B nh thi a nhim Tt c cc khi nh thi u gm b m 16-bit vi thanh ghi chia tn s dao ng 16-bit(prescaler) v thanh ghi t np(auto-reload). B m ca khi nh thi c th c cu hnh m ln, m xung hay trung tnh(ln xung xen k nhau). Xung nhp cho ng h c th c la chn da trn 8 ngun khc nhau: t ng h chuyn bit c ly t ng h h thng, t xung nhp chn ra ly t khi nh thi khc, hoc t ngun xung nhp ngoi. Khi nh thi s dng cng chn ly xung nhp u vo thch hp, ngi dng c th s dng chn ETR iu khin cng chn ny.
4 khi nh thi vi cc thanh ghi 16-bit Prescaler, 16-bit Counter v Auto-reload. Xung nhp hot ng c th ly t ng h h thng, tn hiu ngoi v cc khi nh thi khc
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Mi khi nh thi c cung cp thm 4 knh Capture/Compare. Mi khi nh thi cn c h tr ngt v DMA.
5.1.4.1.1 Khi Capture/Compare
Mi knh Capture/Compare c iu khin bi duy nht mt thanh ghi. Chc nng ca thanh ghi ny c th thay i ty thuc cu hnh. ch Capture, thanh ghi ny c nhm cc bit m nhn thit lp lc d liu u vo v ch nh gi cc ng PWM. ch Compare, STM32 cung cp hm chun so snh v b to xung PWM.
Mi mt knh Capture/Compare u c mt thanh ghi n cu hnh ch hot ng. Bit Capture Compare Selection dng chn ch .
5.1.4.1.2 Khi Capture
Mt khi Capture c bn gm c bn knh vo cu hnh b pht hin xung(Edge Detector). Khi mt xung ln(rising edge) hay xung cnh xung( falling edge) c pht hin, b m hin thi ca s c cp nht vo cc thanh ghi 16-bit Capture/Compare. Khi s kin capture xy ra b m c th c khi ng li hoc tm ngng. Mt ngt DMA c th c s dng trng hp ny.
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4 knh vo ca khi Capture c cc b lc d liu v pht hin xung cnh ring. Khi s kin capture c n c th c dng kch hot mt s kin DMA khc.
5.1.4.1.3 Ch PWM Input
Khi Capture c th c cu hnh dng 2 ng Capture u vo o tn hiu PWM ngoi.
ch o tn hiu PWM, 2 knh Capture c dng o chu k Period v Duty ca sng PWM.
M3->CR1 TIM3->PSC TIM3->ARR = = = 0x00000000;//default 0x000000FF;//set max prescale 0x00000FFF;//set max reload count
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TIM3->CCMR1 TIM3->CCER TIM3->CCMR1 TIM3->CCMR1 TIM3->SMCR TIM3->CCER TIM3->CR1
= 0x00000001;//Input IC1 mapped to TI1 |= 0x00000000;//IC1 triggers on rising edge |= 0x00000200;//Input IC2 mapped to TI1 |= 0x00000020;//IC2 triggers on falling edge = 0x00000054; //Select TI1FP1 as input, rising edge trigger //reset counter = 0x00000011;//enable capture channel = 0x00000001;//enable timer
ch PWM s dng 2 knh Capture. thi im bt u chu k PWM, b m c thit lp gi tr 0 v bt u m ln khi pht hin ra cc tn hiu cnh ln(rising edge). Khi tn hiu cnh xung c pht hin(falling edge) gi tr b m gi tr ca chu k Duty c tng thm.
5.1.4.1.4 Ch PWM
Mi khi Timer u c kh nng to cc xung nhp PWM. ch to xung PWM, gi tr Period c lu trong thanh ghi Auto Reload. Trong khi gi tr Duty c lu thanh ghi Capture/Compare. C hai kiu to xung PWM, mt l canh l(edge-aligned) v canh l gia(centre-aligned). Vi edge-aligned cnh xung ca tn hiu trng vi thi im thanh ghi reload cp nht li gi tr. Vi centre-aligned thi im thanh ghi reload cp nht li l khong gia ca chu k Duty.
Mi khi Timer u c kh nng to ra cc xung PWM vi lch chu k c th c cu hnh edge-aligned hoc centre-aligned tnh theo thi im cp nht gi tr ca thanh ghi Reload. TIM2->CR1 TIM2->PSC TIM2->ARR TIM2->CCMR1 TIM2->CCR1 TIM2->CCER TIM2->DIER TIM2->EGR TIM2->CR1 = 0x00000000;//default = 0x000000FF;//set max prescaler = 0x00000FFF;//set max reload count = 0x00000068;//set PWM mode = 0x000000FF;//Set PWM start value = 0x00000101;//Enable CH1 output = 0x00000000;//enable update interrupt = 0x00000001;//enable update = 0x00000001;//enable timer
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5.1.4.1.5 Ch One Pulse
cc ch trnh by trn, ta thy xung nhp PWM c to c dng dy cc tn hiu lin tip nhau. Khi Timer cn cung cp mt ch hot ng ring cho php to duy nht mt xung PWM vi tn s, b rng xung cng vi thi gian tr c kh nng c cu hnh mt cch linh ng.
5.1.4.3 ng b ho cc b nh thi Mc d cc b nh thi hot ng hon ton c lp vi nhau, tuy nhin chng c th c ng b ha tng i mt hay ton b.
Mi khi Timer c u vo l cc xung s kin t cc khi Timers khc.
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Mi khi Timer 3 ng vo h tr cc xung s kin t 3 khi Timers cn li. Ngoi ra chn Capture t Timer1 v Timer2(TIFP1 v TIFP2) cng c a khi iu khin s kin ca mi Timer.
Cu hnh cc khi Timer kt hp li to thnh mng cc Timer
m hnh to thnh mt mng Timer, mt Timer ng vai tr Master, cc Timer cn li ng vai tr l Slave.
5.1.5 RTC v cc thanh ghi Backup

STM32 bao gm 2 khi ngun chnh: ngun dnh cho nhn CPU, cc thit b ngoi vi v ngun dnh cho khi d phng. Cng c thit k chung vi khi d phng l 10 thanh ghi 16-bit, ng h thi gian thc RTC v mt khi Watchdog c lp. Cc thanh ghi d phng n gin ch l 10 vng nh lu cc gi tr d liu quan trng khi h thng i vo ch Standby v ngun chnh ca h thng b ngt. ch tit kim nng lng, ng h RTC v Watchdog c th c dng kch hot h thng hot ng tr li. STM32 c mt ng h thi gian thc vi thanh ghi m 32-bit v gi tr tng ln mt sau mi giy nu xung nhp u vo ca n l 32.768KHz. Khi cu hnh xung nhp hot ng h thng, xung nhp ngun cho ng h RTC ny c
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th c ly t 3 ngun: LSI, LSE, HSE vi gi tr chia l 128. B m RTC c th to c 3 s kin: tng gi tr m, b m trn v ngt bo ng. Ngt bo ng khi gi tr b m trng vi gi tr c cu hnh trong thanh ghi Alarm.
Khi RTC c th ly ngun xung nhp t LSI, LSE v HSE.
RTC c t trong khi d phng vi ngun cung Vbat v tn hiu ngt Alarm c kt ni vi chn nhn xung EXTI17. iu c ngha khi h thng vo trng thi hot ng ca mc nng lng thp, RTC vn hot ng. V thng qua s kin Alarm, ton b h thng c th c kch hot hot ng tr li ch bnh thng.
5.2 Kt ni vi cc giao tip khc

STM32 h tr 5 loi giao tip ngoi vi khc nhau. STM32 c giao din SPI v I2C giao tip vi cc mch tch hp khc. H tr giao tip CAN cho cc module, USB cho giao tip PC v giao tip USART.
5.2.1 SPI
H tr giao tip tc cao vi cc mch tch hp khc, STM cung cp 2 khi iu khin SPI c kh nng chy ch song cng(Full duplex) vi tc truyn d liu ln ti 18MHz. Khi SPI tc cao nm trn APB2, khi SPI
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tc thp nm trn APB1. Mi khi SPI c h thng thanh ghi cu hnh c lp, d liu truyn c th di dng 8-bit hoc 16-bit, th t h tr MSB hay LSB. Chng ta c th cu hnh mi khi SPI ng vai tr master hay slave.
h tr truyn d liu tc cao, mi khi SPI c 2 knh DMA dnh cho gi v nhn d liu. Thm vo l khi CRC dnh cho c truyn v nhn d liu. Khi CRC u c th h tr kim tra CRC8 v CRC16. Cc c tnh ny rt cn thit khi s dng SPI giao tip vi MMC/SD card.
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5.2.2 I2C
Tng t nh SPI, chun I2C cng c STM32 h tr nhm giao tip vi cc mch tch hp ngoi. Giao din I2C c th c cu hnh hot ng ch slave, master hay ng vai tr b phn x ng trong h thng multi-master. Giao din I2C h tr tc truyn chun 100kHz hay tc cao 400kHz. Ngoi ra cn h tr 7 hoc 10 bit a ch. c thit k nhm n gin ha qu trnh trao i vi 2 knh DMA cho truyn v nhn d liu. Hai ngt mt cho nhn Cortex, mt cho nh a ch v truyn nhn
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Thm na m bo tnh chnh xc d liu truyn, khi kim tra li d liu( PAC packet error checking) c tch hp thm vo giao din I2C cho php kim tra m CRC-8 bit. Thao tc ny c thc hin hon ton t ng bi phn cng.
5.2.3 USART
Mc d cc giao din trao i d liu dng ni tip dn dn khng cn c h tr trn my tnh, chng vn cn c s dng rt nhiu trong lnh vc nhng bi s tin ch v tnh n gin. STM32 c n 3 khi USART, mi khi c kh nng hot ng n tc 4.5Mbps. Mt khi USART nm trn APB1 vi xung nhp hot ng 72MHz, cc khi cn li nm trn APB2 hot ng xung nhp 36MHz.
Giao din USART c kh nng h tr giao tip khng ng b UARTS, modem cng nh giao tip hng ngoi v Smartcard.
Vi mch tch hp cho php chia nh tc BAUD chun thnh nhiu tc khc nhau thch hp vi nhiu kiu trao i d liu khc nhau. Mi khi USART c hai knh DMA dnh cho truyn v nhn d liu. Khi h tr giao
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tip dng UART, USART cung cp nhiu ch giao tip. C th trao i d liu theo kiu ch hafl-duplex trn ng truyn Tx. Khi h tr giao tip modem v giao tip c s dng iu khin lung (hardware flow control) USART cung cp thm cc tn hiu iu khin CTS v RTS.
H tr giao tip ch hafl-duplex da trn mt ng truyn
Ngoi ra USART cn c th dng to cc giao tip ni (local interconnect bus). y l m hnh cho php nhiu vi x l trao i d liu ln nhau. USART cn c khi encoder/decoder dng cho giao tip hng ngoi vi tc h tr c th t n 1115200bps, hot ng ch hafl-duplex NRZ khi xung nhp hot ng khong t 1.4MHz cho n 2.12Mhz. thc hin giao tip vi smartcard, USART cn h tr chun ISO 7618-3.
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Giao tip smartcard v hng ngoi
Ngi dng c th cu hnh khi USART cho cc giao tip ng b tc cao da trn 3 ng tn hiu ring bit nh SPI. Khi hot ng ch ny, khi USART s ng vai tr l SPI master v c kh nng cu hnh Clock Polarity/Phase nn hon ton c th giao tip vi cc SPI slave khc.
H tr giao tip ng b SPI
5.2.4 CAN
Khi iu khin CAN cung cp mt im giao tip CAN y h tr chun CAB 2.0A v 2.0B Active v Passive vi tc truyn d liu 1 Mbit/s. Ngoi ra khi CAN cn c khi m rng h tr giao tip truyn d liu dng deterministic da trn th thi gian Time-trigger CAN(TTCAN).
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Tn y ca CAN l bxCAN, trong bx l vit tt ca Base eXtended. Mt giao din c bn CAN ti thiu phi h tr b m n truyn v nhn d liu, trong khi cc giao din m rng cung cp nhiu b m. bxCan l s kt hp gia hai kin trc trn. bxCan c 3 b m d liu cho truyn v 2 b m nhn, cc b m ny thng c gi l mailbox(hp th). Mi mailbox c t chc nh mt FIFO hng i
Khi CAN c 3 mailbox cho truyn d liu vi nh nhn thi gian t ng cho chun TTCAN
Mt im quan trng na ca CAN l lc gi tin nhn(receive message filter). V giao thc CAN truyn d liu da trn a ch ch nhn, do gi tin s c pht trn ton b mng, ch c im no c a ch ging nh a ch nhn trn gi tin s dng gi tin . Lc gi tin gip cc im trn mng CAN trnh x l cc gi tin khng phi ca mnh. STM32 cung cp 14 b lc(14
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filters bank) c nh s t 0-13 cho php lc ton b cc gi tin khng cn thit. Mi b lc gm 2 thanh ghi 32-bit CAN_FxR0 v CAN_FxR1.
Mi b lc c th c cu hnh hot ng 4 ch lc c a vo 2 nhm chnh l lc theo ID hoc theo nhm ID. Ch th nht l lc da trn ID ca gi tin, nu cc gi tin no khng c ID ging hoc khng ging nh ID c cu hnh trong b lc, n s b b qua. Ch th hai cho php nhn gi tin trong cng mt nhm. Thanh ghi th nht cha ID ca gi tin, thanh ghi th hai cha mt n,quy nh cc thnh phn trn vng ID ca thanh ghi th nht m b lc da trn so snh lc hay khng lc gi tin. CAN hot ng hai ch : bnh thng truyn nhn d liu v ch khi to cu hnh thng s mng. Thm vo khi CAN c th s dng ch tit kim nng lng Sleep Mode. Khi ch Sleep Mode, ng h xung nhp cp cho CAN ngng hot ng, tuy nhin thanh ghi mailbox vn hot ng. iu ny cho php CAN c kch hot da trn cc hot ng mng. C hai ch ph khi CAN hot ng ch truyn nhn d liu thng thng. Ch Silent, khi CAN ch nhn d liu khng th truyn d liu, ngi ta hay s dng ch ny theo di mng v cc gi tin truyn trong mng. Ch Loopback cho php ton b cc gi tin chuyn c a vo ngay chnh b m nhn ca khi CAN . Ch ny dng t kim tra hot ng ca phn cng CAN v phn mm iu khin.
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5.2.5 USB
H tr giao tip Device USB vi tc Full Speed (12Mbps) c kh nng kt ni vi mt giao din host usb. Khi giao din ny bao gm Layer1 v Layer2 m nhn chc nng truyn vt l(phisical layer) v truyn d liu logic (data layer). Ngoi ra cn h tr y ch Suspend v Resume nhm tit kim nng lng.
Vi 8 endpoint, c th hot ng di cc ch : Control, Interrupt, Bulk hoc Isochronous. Vng m d liu 512 byte SRAM ca cc endpoint c chia s vi giao din CAN. Khi c cu hnh, ng dng s chia vng m ny thnh cc phn tng ng vi cc endpoint. Cc vng m ny m bo d liu c truyn nhn lin tc trn mi endpoint.
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Chng 6 CH TIU TH NNG LNG THP

STM32 c nhiu ch cng sut thp bn cnh ch bnh thng (normal RUN mode). Khi s dng mt cch ng n cc ch cng sut thp(SLEEP, STOP, STANDBY) s lm ti u ngun bin. Khi vo ch cng sut thp, CPU v cc ngoi vi Cortex c tm dng v tiu th cng sut ti thiu. Mt khi b x l Cortex vo ch cng sut thp, n xut mt tn hiu SLEEPDEEP n cc vi iu khin xung quanh, ra hiu rng n vo mt ch cng sut thp no . CPU Cortex vo cc ch cng sut thp bng cch thc hin lnh WFI hoc WFE. Ty vo cu hnh thanh ghi iu khin cng sut (power control registers) m STM32 s i vo cc trng thi tiu th thp tng ng. Trong phn k chng ta s tm hiu tng ch cng sut, cng nh so snh cng sut tiu th v thi gian phc hi (wake up time) ca chng.
6.1 Ch bnh thng - RUN mode

RUN mode l ch STM32 thc hin cc lnh chng trnh v n tiu th cng sut mc cao nht. Trong phn ny s ch ra nhiu cch gim cng sut tiu th tng th ca h thng trong chng trnh thc thi. im ct li l tt c cc chc nng ca h thng nn c dng mt cch linh hot khi thc thi m chng trnh. Ngha l khi c th, m nn c chy ch cng sut thp-hiu nng x l thp, v chuyn sang ch cng sut cao-cu hnh hiu nng cao p ng ngt v chng trnh s kin (program event). Trong hot ng bnh thng b x l Cortex v hu ht STM32 c th chy 72MHz. Khi chy tc ti a, STM32 tiu th hn 30mA. Trnh tiu tn nng lng cc ngoi vi khng s dng bng cch chn xung clock ca chng. Khi nng lng tiu th trn ton h thng s gim. Cc xung clock ngoi vi c th chuyn i on/off mt cch linh ng thng qua khi iu
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khin Clock Reset (Reset clock control module). Bn cnh , c th gim cng sut tiu th bng cch gim xung nhp hot ng ca h thng. Nu h thng khng cn hot ng tc cao, c th tt b nhn tn s PLL v STM32 c th dng xung nhp trc tip t b dao ng ngoi HSE. Hn na, c th tt lun HSE v dng xung nhp t b dao ng ni HSI. iu ny c mt bt li l ngun xung clock t HSI khng chnh xc bng HSE. Tng t, nu khng s dng khi Windowed Watchdog v ng h thi gian thc(realtime clock) khng dng ti, th tt b dao ng LSI nhm tit kim hn na cng sut tiu th.
6.1.1 Ch Half-cycle v Prefetch-buffer

Khi chy trc tip t b dao ng ngoi HSE vi tn s ti a 8MHz, ta c th tt b m ly trc lnh (FLASH Prefetch Buffer) v cho kch hot ch na chu k (Half Cycle). Lm nh vy tuy phi chu thm mt s trng thi ch, nhng gim c cng sut tiu th ch RUN mode.
Cng sut tiu th tc ti a khong 34mA, nhng 8MHz (9.6 DMIPS) cng sut tiu th di 1mA.
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6.2. Cc ch s dng cng sut tiu th thp

Cu hnh ch RUN mode ca STM32 mt cch cn thn c th gim cng sut tiu th khong 8,5mA. Nhm t c cc ng dng cng sut thp thc chng ta phi s dng cc ch cng sut thp ca STM32.
6.2.1. SLEEP
Mc u tin ca hot ng cng sut thp l ch SLEEP mode. Mc nh, khi mt lnh WFE hoc WFI c thc hin b x l Cortex s tm dng cc ng h xung nhp ni v dng thc thi m ng dng. Trong ch SLEEP cc phn cn li ca STM32 vn tip tc hot ng. STM32 s thot khi SLEEP mode khi mt ngoi vi no pht sinh ngt. Khi STM32 vo SLEEP mode cng tt c ngoi vi ang hot ng v n chy 72MHz t HSE thng qua b nhn PLL, cng sut tiu th ca n vo khong 14.4mA. Tuy nhin, c th c iu chnh li STM32 cho cc ng dng cng sut thp thng qua 2 bc: th nht tt tt c ng h to xung nhp cho cc ngoi vi (tr ngoi vi nh thc b x l Cortex); th hai chuyn qua dng b dao ng ni HSI (c th chia tn s hot ng n mc di 1MHz). Khi cng sut tiu th vo khong 0.5mA.
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Cng sut tiu th ch SLEEP mode c th thp n 0.14mA
Trong ng dng cng sut thp bn nn s dng ch SLEEP mode mi khi c th, nhm tiu th ti thiu cng sut. Vn tip theo l STM32 mt bao lu thot khi ch cng sut thp v tip tc x l. Cc hnh di y cho thy thi gian nh thc Cortex CPU khi phc x l ang chy bng b dao ng RC ni HSI.
6.2.2 STOP Mode
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STM32 c th c cu hnh vo ch cng sut thp STOP Mode bng cch thit lp bit SLEEPDEEP trong thanh ghi iu khin cng sut Cortex (the Cortex power control register) v xa bit Power Down Deep Sleep (PDDS) trong thanh ghi iu khin cng sut STM32.
Khi cu hnh cho ch STOP mode, vic thc hin lnh WFI hoc WFE s tm dng b vi x l Cortex v tt c b to dao ng ni HIS, ln ngoi HSE. Cc Flash, SRAM v thit b ngoi vi vn cn c cung cp ngun, do , trng thi ca STM32 vn c bo ton. Cng ging nh ch SLEEP, c th thot khi ch STOP bng ngt c pht ra t mt ngoi vi STM32. Tuy nhin, trong ch STOP tt c cc xung clock ngoi vi c tm dng, ngoi tr ngoi vi ngt ngoi(External Interrupt). Vic s dng cc thit b ngoi vi EXTI cho php STM32 thot khi ch STOP mode khi c s thay i trng thi trn bt k pin GPIO. Ngoi ra, EXTI c mt ng tn hiu iu khin m c th yu cu ngt v to ra ngt t s kin bo thc (Alarm) ca ng h thi gian thc. V ng h thi gian thc c b dao ng chuyn dng ca ring n (hoc l LSI hoc LSE) n c th cung cp ngt nh k nh thc STM32 t ch STOP. Mt khi STM32 vo ch STOP, tiu th in nng ca n gim mnh xung khong 24 uA thay v hng mA ch RUN. C th tit kim thm in nng bng cch t cc b iu p ni trong mt ch nng lng thp c bit, khi n vo ch STOP. Cc ch nng lng thp cho cc b iu p c chn bng cch thit lp bit LPDS (Low Power Sleep Deep) trong
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thanh ghi iu khin cng sut STM32. Vi thit lp ny khi STM32 vo ch STOP, tiu th in nng ca n s gim xung 14uA. Nu RTC ang c s dng, s tiu th thm 1,4 uA.
Thi gian nh thc trong ch Stop di nht l 5,5 us vi b iu p chy bnh thng v 7,3 us vi b iu p trong ch cng sut thp.
6.3 Standby
STM32 c th c cu hnh vo ch Standby bng cch thit lp bit SLEEPDEEP trong thanh ghi iu khin cng sut Cortex v thit lp bit
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Power Down Deep Sleep (PDDS) trong thanh ghi iu khin cng sut ca STM32. By gi, khi lnh WFI hoc WFE c thc hin, STM32 s vo ch nng lng thp nht ca n. Trong ch Standby, STM32 thc s tt. Cc iu in p ni b c tt cc b to dao ng HSE v HIS cng tt. Trong ch ny STM32 ch chim 2uA.
Trong ch Standby tiu th in nng l 2uA vi thi gian nh thc l 50uS.
Chng ta c th thot khi ch Standby bng cch s dng tn hiu ngt ca khi RTC tng t nh trong ch STOP. Ngoi ra ta c th s dng chn Reset ngoi hay chn Reset t Watchdog c lp. Ch Standby c th kt thc khi c xung nhp cnh ln(rising edge) chn 0 ca Port A nu chn ny c cu hnh nh l chn c tnh nng WKUP bng cch thit lp bi EWUP thanh ghi Power v Status. Standby l ch tiu th t nng lng nht cho nn s mt nhiu thi gian h thng phc hi tr li trng thi hot ng bnh thng. Mt khong 50usec
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trc khi nhn Cortex khi ng li tin trnh x l lnh. Mt khi vo ch Standby, ton b d liu trn SRAM, nhn Cortex v cc thanh ghi u b mt. Khi phc hi trng thi hot ng t ch Stanby tng t nh ta khi ng li h thng.
6.4. S tiu th cng sut ca ngun d phng (Backup Region Power Consumption)
Vng nng lng d phng (Backup Region) cha pin d phng duy tr RAM v RTC trong sut thi gian cc ch cng sut thp. Vng ny tiu th khong 1,4 uA in p 3,3V.
6.5 H tr Debug (Debug Support)

Trn h thng vi iu khin truyn thng, g li mt ng dng m s dng ch cng sut thp c th mt rt nhiu cng sc. Ngay sau khi vi iu khin vo cc ch cng sut thp n dng p ng cc trnh g li, iu ny s to mt li hoc ngng lm vic. Trong STM32 c th cu hnh cc ch cng sut thp gi b dao ng ni HSI chy trong cc ch nng lng thp tng ng, cung cp mt ng xung xung nhp dnh cho khi g li CoreSight. iu ny c ngha l bn c th g li y cc ng dng nng lng thp m khng cn phi g b ch nng lng thp. iu ny gip loi b cc vn g li timeout. Vic tng cng tnh nng g li STM32 c cu hnh vi thanh ghi DBG_MCU.
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Chng 7 TNH AN TON

STM32 cng c thit k vi mt s tnh nng vn c m s pht hin cc hot ng khng chnh xc ca cc m ng dng hoc ca chnh STM32. m bo rng c mt ngun cung cp nng lng ng tin cy, STM32 c mt b reset ni thc hin chc nng reset chip nu cc ngun cung cp in p di mc ti thiu VDD. Ngoi ra cn c mt mch kim tra in p ngun kh trnh c th c s dng pht hin vic mt ngun t ngt. Sau khi pht hin mch kim tra s to ra mt ngt t chip vo trng thi an ton. H thng gim st tnh an ton ca xung nhp h thng (clock security system) theo di theo di b dao ng ngoi HSE. Nu xung nhp ngoi b gp s c t ngt, CSS iu chnh h thng hot ng bng b dao ng ni. Mt chng trnh thc thi s c theo di bi hai b Watchdog ni. B th nht, l mt Windowed Watchdog vi thi gian theo di c cu hnh c th. B th hai l mt Watchdog c lp c cp xung nhp t mt b dao ng c lp vi h thng chnh. Ngoi ra, b nh Flash trn-chip c c kh nng lu d liu n 30 nm 85 C. y l s lu d liu tt nht cho mt vi iu khin a dng.
7.1 Reset Control

STM32 c nhiu ngun Reset khc ngoi ng Reset bn ngoi. STM32 c th b buc khi ng li t: cc Watchdogs ni, mt Reset mm thng qua NVIC, b Reset m/tt ngun ni v mch pht hin in p ngun thp. Nu mt hiu lnh Reset xut hin, mt b c trong thanh ghi kim sot v trng thi RCC c th c c xc nh nguyn nhn gy ra Reset. Trng thi ca nhng c ny s vn tn ti cho khi h thng c cp ngun tr li hoc cho n khi ngi dng thit lp bit Remove Reset.
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STM32 c th c nhiu tn hiu iu khin a h thng v trng thi Reset. Trng thi h thng s c lu li trong thanh ghi RCC
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7.2 Kim tra in p ngun

L mt phn ca b gim st ngun cung cp ni ca STM32 cha mt n v gim st ngun c gi l b Kim tra in p ngun - Power Voltage Detect (PVD). PVD c ngng kh trnh c th c thit lp vi sai s 0.1V t 2.2V n 2.9V. Ngng ny c cu hnh trong cc thanh ghi kim sot ngun.
u ra ca PVD c kt ni vi 16 ng ca b ngt ngoi. Do cc ng ngt ngoi EXTI c th c cu hnh to ra ngt t tn hiu cnh ln hoc cnh xung, hoc c hai, n v PVD c th c s dng to ra mt ngt cho c thp p v qu p.
7.3 H thng an ton xung nhp (Clock Security System - CSS)

Trong hu ht cc ng dng, xung nhp h thng c c dng bi b x l Cortex v cc thit b ngoi vi s ly t mt dao ng thch anh bn ngoi kt ni thng qua cc chn HSE. H thng to xung nhp dao ng ny cha mt khi CSS thc hin nhim v gim st dao ng thch anh ngoi. Nu ngun dao ng thch anh ngoi c vn , n s s dng h thng to dao ng ni HSI 8MHz.
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Khi CSS c kch hot bng cch thit lp bit Clock Security Enable trong thanh ghi iu khin RCC.
H thng CSS c mt ng ngt c kt ni vi ngt gy (break interrupt) ca khi nh thi nng cao Timer1, m ngt c nh x vo bng vector iu khin ngt Cortex NVIC non-maskable. iu ny m bo nu dao ng chnh khng hot ng na, cc ng ra PWM ca khi nh thi nng cao s ngay lp tc c t trong trng thi an ton tin lp trnh(pre-programmed safe state) bi phn cng. iu ny m bo rng bt k phn cng no c iu khin bi cc u ra PWM ca khi nh thi tin tin s khng c php hot ng khi khng c s kim sot ca b vi x l Cortex. N c bit quan trng cho cc ng dng iu khin ng c.
7.4 Watchdogs
STM32 cha hai Watchdogs ring bit. Watchdog c lp(independent watchdog) l hon ton tch bit vi h thng STM32 chnh. N c t trong min ngun in d phng v xung nhp ca n bt ngun t dao ng ni tc thp (LSI- Low Speed Oscillator). Windowed Watchdog l mt phn ca h thng STM32 chnh v c cp xung clock thng qua ng
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truyn xung nhp ngoi vi s 1(PCLK1). C hai Watchdogs phi c kch hot ring bit v c th c s dng ng thi. 7.4.1 Windowed Watchdog Windowed Watchdog l mt phin bn nng cao hn ca Watchdog truyn thng trn chip. Sau khi kch hot, Watchdog s m ngc v s to ra tn hiu Reset khi gi tr ca thanh ghi thay i t 0x40 sang 0x3F tc l khi bit T6 b xa. Gi tr m ngng trn c lu trong thanh ghi cu hnh
Windowed Watchdog. Nu phn mm ng dng lm ti b m Watchdog trong khi gi tr thc ca b m Watchdog ln hn gi tr ngng m trn mt tn hiu Reset cng s c pht ra. Windowed Watchdog cung cp mt khung lm ti kh trnh m khi Watchdog mi c th c ghi vo theo lch trnh thi gian nh. iu ny cho php ngi dng m bo ng dng vn ang trong ch hot ng bnh thng xc nh.
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Windowed Watchdog l b m xung 6 bit, c cung cp xung clock t PCLK1 thng qua b tin chia 12 bit chia PCKL1 xung bi 4096. B tin chia c thm 4 bit kh lp trnh cho php ngi dng chia thm 1,2,4 hoc 8. Cc bt ca b tin chia c cha trong bt 6,7 ca thanh ghi iu khin. Do thi gian lp ca windowed watchdog c cho bi: Twwdg = Tpclk1x4096x2POW (WDGTB) x (reload value+1) Vi Pclk1 chy tc ti a 36MHz, thi gian timeout nh nht ca windowed watchdog l 910uSec v ln nht l 58,25mSec. Sau khi windowed watchdog c cu hnh, n c th c kch hot bng cch thit lp bit Watchdog Activation trong trong thanh ghi iu khin. Sau khi Windowed Watchdog c kch hot bng phn mm n khng th b v hiu, ngoi tr h thng ti khi ng. 7.4.2 Independent Watchdog Mc d Independent Watchdog c thit k nm trn h thng chnh, nhng n c b dao ng ring tch bit vi ngun dao ng ca h thng chnh. Independent Watchdog cng c t trong min in ap VDD , l min m vn c duy tr khi h thng trong ch STOP v STANDBY.
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Independent Watchdog l mt nh thi m xung 12 bit, v s pht sinh hiu lnh Reset cho h thng khi gi tr t di ngng. N c cp xung nhp t dao ng ni tc thp thng qua mt b chia 8 bit. B to dao ng LSI c mt tn s danh ngha l 32kHz, nhng trong thc t n c th thay i gia 30 KHz n 60 KHz. Independent Watchdog c khi ng bng cch, u tin thit lp thanh ghi Prescaler, khi qua b chia Prescaler dao ng s c gi tr trong khong t 4 n 256. Khong thi gian ch ti thiu cho Independent Watchdog l 0mSec v ti a ch trn 26 giy. Thi gian ch c lp trnh trc tip vo thanh ghi np li (reload register).
Cc byte ty chn trong b nh Flash khi thng tin nh c th c dng cu hnh Independent Watchdog bt u sau khi reset, hoc bng lnh phn mm. Nu theo phn mm kim sot, Independent Watchdog c th c bt u bng cch ghi 0xCCCC vo thanh ghi kha. Independent Watchdog s m xung t mt gi tr ban u 0xFFF. Gi tri 0xAAAA phi c ghi vo thanh ghi kha lm ti watchdog. iu ny lm cho gi tr np li c np vo thanh ghi m xung, lm mi gi tr m.
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Rt kh g li chng trnh cc dng vi iu khin nh nu Watchdog c kch hot. Ngay sau khi CPU ngng hot ng, watchdog khng th c cp nht. N s ch thi gian ti hn(timeout) v sau s pht sinh ra ngt, khi ton b h thng khi ng li xa i trng thi li cn m ngi dng cn g. Bnh thng, mt Watchdog phi c v hiu ho n khng gy ri lon cc trnh g li. Nu vy th li kh khn trong vic nh gi cu hnh thi gian kim tra ca Watchdog l ti u hay cha. Trong thanh ghi MCUDBG STM32 c th cu hnh c hai Independent Watchdog v Window Watchdog dng hot ng khi Cortex-M3 CPU nm di s kim sot ca h thng g li CoreSight. iu ny cho php ngi dng g li ngay c khi hai khi Watchdogs c kch hot.
7.5 Tnh nng ngoi vi

Cc thit b ngoi vi cng c thit k vi mt s tnh nng h tr m bo s vn hnh an ton cc STM32. 7.5.1 GPIO Port Locking (kha port GPIO) Khi cc cng GPIO c khi to, mi dng IO s c cu hnh nh mt u vo hoc u ra. Mt khi cu hnh hon tt ta c th kha n li. iu ny ngn chn bt c thay i tnh c tip no ln cu hnh cng. Mi cng c th b kho trn mt da trn bit iu khin. 7.5.2 Analog Watchdog Mi b chuyn i ADC c 2 analog watchdogs. Nhng Watchdog ny c th c thit lp pht ngt khi trn hoc di ngng in p. 7.5.3 Break Input i vi cc ng dng da trn ng c, ng Break trong khi nh thi nng cao c th c dng t ba ng ra PWM b sung vo trng thi nh sn, p ng vi tn hiu u vo trn chn Break, hoc mt ngun to dao ng chnh.
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Chng 8: FLASH
B nh FLASH on-chip ca STM32 c b tr trong 3 vng chnh. u tin, vng nh FLASH chnh c thit k cha cc lnh chng trnh. y l vng nh 64 bit, cung cp s truy cp b nh hiu qu vi b m ly lnh. Vng nh ny c chia thnh tng trang 4K i vi hot ng xa v ghi chng trnh flash. B nh c bn 10.000 chu k, duy tr d liu 30 nm 85oC. Hu ht cc b nh FLASH vi iu khin ch duy tr d liu tt 25 0C, b nh FLASH ca STM32 l mt ngoi l. Bn canh vng nh chng trnh chnh, l 2 vng nh nh hn: khi thng tin ln v khi thng tin nh. Khi thng tin ln l 2k b nh FLASH cha chng trnh bootloader c cung cp bi nh sn xut, l chng trnh c thit k sn ti code v qua cng USART1. Khi thng tin nh cha 6 byte cu hnh, l cc byte c dng nh ngha cc thuc tnh Reset ca STM32 v bo v b nh.
8.1 Lp trnh v m bo an ton cho FLASH ni

B nh FLASH ni c th c cp nht bi bootloader, bng JTAG, hoc bng chng trnh ng dng bn trong thng qua mt b thanh ghi chuyn dng c gi l chng trnh FLASH v xa iu khin FPEC. FPEC cng c dng lp trnh cc byte ty chn trong khi thng tin nh.
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Khi FPEC c dng cho php trong ng dng lp trnh ca b nh FLASH. B nh FLASH cng c th c bo v c khi cc cng c debug v c bo v ghi.
8.2 Hot ng xa v ghi

Sau khi reset, cc thanh ghi FPEC c bo v v phi c m kha bng cch ghi mt chui c bit vo thanh ghi kha (key register). m kha FPEC bn phi ghi 0x45670123, theo sau bi 0xCDEF89AB. Nu c li xut hin trong chui ny, FPEC s trng thi b kha cho n ln reset k tip. Mt khi FPEC c m kha, n c th thc hin hot ng xa v ghi trn b nh FLASH chnh. Trong khi b nh FLASH chnh n c th thc hin xa theo khi hoc xa mt trang 4k c chn. Hot ng xa khi c thc hin bng cch thit lp n gin xa khi v khi ng cc bit trong thanh ghi iu khin. Khi bit Busy trong cng thanh ghi c reset, mi v tr trong b nh FLASH chnh s c reset v 0xFFFF. Xa mt trang th cng n gin nh vy. u tin, bn phi lp trnh a ch bt u ca mt trang FLASH trong thanh ghi a ch, sau thit lp xa trang v khi ng cc bit trong thanh ghi iu khin. Mt ln na, khi bit Busy b xa, trang c thit lp s b xa. D liu mi c th c ghi vo nh FLASH ch sau khi n c xa ri. Mt hot ng ghi (WRITE) c thc hin bng cch thit lp bit Program trong thanh ghi iu khin v sau thc hin ghi mt haft-word (2
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byte) vo v tr mong mun. Nu v tr FLASH c xa v khng c bo v ghi, FPEC s lp trnh gi tr mi vo trong nh FLASH.
8.3 Cc byte Option (Option Bytes)

Khi thng tin nh c 8 byte Option cu hnh dnh cho ngi dng. Trong 4 byte c dng thit lp hot ng bo v ghi trn b nh FLASH chnh. Byte th nm dng thit lp bo v c trnh s truy nhp vo cc vng nh khi chip trong ch debug. Byte th su c dng cu hnh cng sut thp v hot ng reset. Hai byte cui cng l nhng b nh FLASH n gin, sn c cho ngi dng ty chn. trc khi cc byte Option c th c ghi vo, FPEC phi c m kha nh m t trn. K tip cc byte ty chn phi c m kha bng cch ghi ging 2 kha vo thnh ghi kha option. Cc byte Option c mt chng trnh ring bit v th tc xa b nh FLASH chnh. Khi thng tin nh c xa bng cch thit lp bit OPTER trong thanh ghi iu khin k tip l bit STRT. Mt khi bit BSY c reset, khi thng tin nh c xa. lp trnh mt byte Option, set bit OPTPG trong thanh ghi iu khin FLASH v thc hin ghi half-word vo byte Option. Mi byte Option c lu nh mt half-word. Byte Option c lu trong byte thp ca halfword v gi tr b ca n c lu trong phn cao ca halfword. Bn phi ghi mt gi tr ph hp vo phn thp ca halfword v FPEC s tnh gi tr b mt cch t ng. 8.3.1 Bo v ghi Khi n c thit lp, mi bit trong cc byte Option bo v ghi cho php vic bo v trn mt trang FLASH. Vic bo v ghi c th khng c cho php bng cch xa khi thng tin nh. 8.3.2 Bo v c Khi bo v c c thit lp, tt c cc truy cp c vo b nh FLASH khng c php khi thit b vo ch debug. Truy cp vo SRAM th vn
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c v code c th c download v thc thi trong vng ny. Nn c th khng cho php vic bo v c khi chy mt chng trnh ngoi vng SRAM. Tuy nhin, khi bo v c b tt lc vic xa khi ca FLASH ni s c thc hin nhm trnh cc chng trnh n cp phn mm. Khi ch bo v c c cho php, b nh FLASH cng c bo v ghi trnh mt chng trnh him c (malicious) khi b chn vo vng nh cha bng vector. B nh STM FLASH c bo v nu byte bo v c v phn b ca n c set ln 0xFF. B nh c th c v hiu bo v bng cch ghi 0xFA v phn b ca n nh mt half-word vo byte Option bo v c. 8.3.3 Byte Cu hnh Byte Option cu hnh cha 3 bit active. Trong 2 bit qun l STM32 vo ch Standby v Stop nh th no. Mt trong hai ch c th c cu hnh pht mt tn hiu reset khi vo. iu ny s cu hnh cc chn IO s nh ng vo, gim cng sut tiu th ton b ca STM32. PLL v b dao ng ngoi cng s b v hiu ha v chip s chuyn qua dng b dao ng tc cao RC ni nh l ngun xung chnh. Bit cui cng trong byte Option cu hnh hot ng ca Independent Watchdog. Watchdog ny c mt ch watchdog cng n s bt u ngay lp tc sau khi b x l reset, hoc ch watchdog mm n phi c bt u di s iu khin ca phn mm.
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Chng 9: CNG C PHT TRIN

Vic chp nhn ARM7 v ARM9 l vi iu khin tiu chun dn ti mt s bng n trong cng c pht trin h tr cho cc CPU ny. Tt c cc nh pht trin trnh bin dch ln nh GCC, Greenhills, Keil, IAR v Tasking u cung cp cc cng c pht trin ARM . Vi vic gii thiu cc b vi x l Cortex, tt c cc cng c pht trin c m rng h tr cc tp lnh Thumb-2. Nu bn s dng mt vi iu khin ARM-based, th trnh bin dch cc bn ang dng s h tr bin dch m cho STM32. Nu phin bn phn mm ang dng qu c th chng ta phi nng cp chng. Nu y l d n u tin ca bn vi mt vi iu khin ARM-based, bn s c th chn mt b cng c (toolset) t nh sn xut quen thuc ca bn. Th nht l trnh bin dch "GCC" hoc "GNU" l mt cng c m ngun m c th c ti v v s dng min ph. Trnh bin dch GCC c tch hp vo mt s IDE thng mi v g ri lm cho thp chi ph cng c pht trin v kit nh gi. Trong khi cc trnh bin dch GCC l mt trnh bin dch ng tin cy v n nh. Cc bn c th s dng Sourcery phin bn min ph bin dch, tuy nhin m chng trnh s khng ti a bng cc phn mm thng mi khc. Ging nh cc phn mm ngun m khc, h tr s dng ca GCC rt hn ch, nu bn l ngi mi vo ngh th khng nn tip cn GCC khi lm d n. Trnh bin dch ARM RealView l trnh bin dch C bn gc v hu ht c chn lc v c pht trin bi ARM s dng vi CPU ca h. Trnh bin dch RealView c sn nh l mt phn ca toolset ARM RealView. Toolset ny l nhm vo cc nh pht trin system-on-chip v khng thc s ph hp cho cc d n vi iu khin. Tuy nhin k t thng 1 nm 2006 trnh bin dch RealView c tch hp vo Keil Microcontroller Development Kit (MDK-
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ARM). Nh tn gi ca n ng , MDK-ARM l mt chui cng c hon chnh thit k ring cho vi iu khin da trn ARM-based. nc ta, hu ht cc k s u quen thuc vi Keil khi lp trnh vi 8051, do s dng Keil lp trnh cho ARM cng l iu thun li. Nu bn ang lm cho mt quyt nh gia vic s dng cc trnh bin dch GCC v mt trnh bin dch thng mi, bn s b chi phi mt phn bi ngn sch d n. Mt d n 'n gin' dng nh khng c ngn sch chi cho mt toolset thng mi. Tuy nhin, nu bn c k hoch chun ha vi iu khin ARM- based, sau l mt toolset xn s sm chi cho bn thn d n c v rt ngn thi gian pht trin v mt m chng trnh nh gn v ti u hn.
9.1 Evaluation Tools

Hu ht cc nh cung cp trnh bin dch cng s cung cp mt kit nh gi hoc kit starter (evaluation kit or starter kit). y l mt board mch phn cng truyn thng v mt phin bn ct gim xung hoc gii hn thi gian ca toolset ca h. Chng ti gii thiu Kit GE-M3M-V2. Chi ph khong 899000VND, GE-M3M-V2 l cng c hon ho cc k s tip cn n vi x l STM32.
9.2 Cc th vin v giao thc

h tr pht trin m nhanh chng, ST cung cp mt th vin phn mm STM32 firmware nh l mt download min ph t trang web ca h. Th vin phn mm cung cp chc nng iu khin cp thp cho tt c cc thit b ngoi vi on-chip. iu ny cho php bn xy dng mt s khi c bn m trn bt u xy dng ng dng ca bn. Cc thit b ngoi vi phc tp nht trn cc bin th STM32 hin nay l b iu khin thit b USB. gip bn xy dng cc thit b lp USB ph bin, ST cng cung cp mt b kit pht trin USB min ph. Cng ging nh cc th vin phn mm, kit pht trin ca USB c
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th c ti v t trang web ca ST. Kit pht trin USB cung cp mt th vin USB v cc ng dng trnh din cho HID, Mass Storage, m thanh v thit Device Field Upgrade.
Vi s gia tng phc tp ca cc ngoi vi Vi iu khin, th iu quan trng l chn chui cng c ci m c h tr tt vi giao thc v cc phn mm ng dng ngn xp.
Nh cc bin th mi ca cc STM32 c pht hnh, chng s c nhiu thit b ngoi vi cng phc tp hn (Ethernet MAC, giao din mn hnh TFT, vv). Nh vy lm tng phc tp, n s tr thnh l ch khng th pht trin tt c cc m ng dng ca chnh bn. V vy, khi la chn cng c pht trin n cng rt quan trng xem xt tnh sn c ca giao thc ngn xp, chng hn nh ngn xp TCP / IP v phn mm ng dng khc, chng hn nh GUI, c th c yu cu trong cc d n tng lai. L tng nhng th ny nn t cng nh cung cp v tch hp tt vo toolset bn chn.
9.3 H iu hnh thi gian thc

Nu bn ang chuyn t mt vi iu khin tm hoc mi su bit, th c hi c rng hin ti bn khng s dng mt RTOS. Nh chng ta thy, cc Cortex-M3 cung cp cho bn sc mnh x l c bit nhiu hn so snh gi thnh cc vi iu khin v c thit k h tr RTOS footprint nh. V vy, nu bn khng s dng mt RTOS n l gi tr xem xt khi bn bt u lm vic vi cc STM32. Vic s dng mt RTOS cung cp cho bn nhng li th v pht trin thm m rt gn, nng cao ti s dng m, qun l d n d dng hn v tng cng g li. Vic s dng mt RTOS cng cung cp mt cu trc
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cho m ca bn, iu m buc bn phi ln k hoch cho ng dng trc khi bn nhy vo v bt u vit. C nhiu RTOS c sn hn cho ARM v Cortex hn cho hu ht cc CPU nhng. Nhiu nh cung cp trnh bin dch s cung cp h iu hnh ca chnh h v hoc mt RTOS ngoi, mt trong nhng h iu hnh m ngun m ph bin nht l "FreeRTOS", c sn t www.freertos.org. Mt phin bn thng mi ca FreeRTOS c gi l "SafeRTOS", m c th nghim p ng cc tiu chun an ton IEC 61508 v cng c sn t cng mt trang.
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Kien Truc Co Ban Cua STM32-ARM Cortex M3

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Kien Truc Co Ban Cua STM32-ARM Cortex M3

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Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca STM32_ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Chng 1 GII THIU

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 1.1. Kin trc vi x l ARM Cortex-M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 1.2. Kin trc ca STM32 nhnh Performance v Access

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

1.2.4 Pht trin phn mm

1.2.5 Dng Performance v Access ca STM32

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 1.3. c im ca bn nhnh trong h STM32

Kin trc c bn ca SMT32 - ARM Cortex M3

Chng 2 TNG QUAN V CORTEX

2.1 Cc phin bn kin trc ARM

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.1. Cc phin bn kin trc ca li ARM

2.2 B x l Cortex v n v x l trung tm Cortex

2.3 n v x l trung tm Cortex (Cortex CPU)

2.3.1 Kin trc ng ng (Pipline)

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.2. Kin trc ng ng ca ARM Cortex-M3

2.3.2 M hnh lp trnh (Programmers model)

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.3. Kin trc load v store ca ARM Cortex-M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.3. M hnh lp trnh ca ARM Cortex-M3

2.3.2.1 Thanh ghi XPSR

Kin trc c bn ca SMT32 - ARM Cortex M3

2.3.3 Cc ch hot ng ca CPU

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.5. M hnh hot ng ca ch Thread v Handler

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.6. th biu din hiu nng ca b x l Cortex

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.6. Bn b nh tuyn tnh 4Gbyte ca b x l Cortex-M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.9. Di Bit ca vng b nh SRAM v cc ngoi vi

Kin trc c bn ca SMT32 - ARM Cortex M3

By gi chng ta c th to ra mt con tr n a ch ny bng cch s dng

Con tr ny c th c s dng thit lp v xo cc bit ca cng I/O ny: PB8 = 1; // led on

To ra m assembly sau y: MOVS LDR STR r0,#0x00 r1,[pc,#88] r0,[r1,#0x00]

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.10. Cc thanh ghi trng thi v iu khin ca SysTick

Kin trc c bn ca SMT32 - ARM Cortex M3

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.11. Cu trc ca NVIC trong b x l Cortex

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.12. Stack frame trong ch ngt

Kin trc c bn ca SMT32 - ARM Cortex M3

Hnh 2.13. p ng thi gian khi mt ngt bt k xy ra ca Cortex-M3

Kin trc c bn ca SMT32 - ARM Cortex M3