Nguyn Th Hong

Khoa CN in T - HCN TPHCM

Th nghim thit k FPGA

Rev 1.0

[ Ti liu hng dn thc hnh thit k FPGA. y l Ti liu chuyn nghnh ginh cho sinh vin nm 3,4 chuyn ngnh in T - Vin thng T ng. Ti liu thuc chng trnh ging dy bc H ca khoa Cng Ngh in T, trng H Cng Nghip TP HCM ]

Contents
Phn 1 : I. II. III. Tng quan v thit k trn FPGA.......................................................................................... 2 Qui trnh thit k.......................................................................................................................... 2 Gii thiu FPGA............................................................................................................................ 4 Gii thiu Board DE2 ca Altera ............................................................................................... 9 1. Gii thiu .................................................................................................................................... 9 2. Thnh phn ............................................................................................................................... 10 3. Mt vi ng dng ca board DE2 .............................................................................................. 10 IV. Cch ci t Quartus II 10.0 v Nios II ..................................................................................... 13 1. Gii thiu .................................................................................................................................. 13 2. Ci t ...................................................................................................................................... 13 V. To mt project mi vi Quartus II 10.0: .................................................................................... 16 1. To 1 project: ............................................................................................................................ 16 2. Vit chng trnh v bin dch: ................................................................................................. 17 3. Gn chn v np xung phn cng FPGA: .................................................................................. 20 Phn 2 : 1. 2. H thng bi lab ca altera ................................................................................................. 26 Gii thiu v h thng bi lab ca altera .................................................................................... 26 Chi tit cc bi lab phi thc hin............................................................................................... 27

Reference Documents ....................................................................................................................... 28

Phn 1 : Tng quan v thit k trn FPGA

Mc tiu Nm c cng ngh FPGA Lm quen board thc hnh DE2 Ci t, v lm quen vi cc phn mm: Quartus II, Nios II

I. Qui trnh thit k

Hnh sau ch ra qui trnh thit k chip y . Qui trnh thit k ny ti u, hiu sut cao,mt tch hp cc ln, nhng gi thnh cao, phc tp ln , nhiu ri ro v thi gian ra sn phm rt lu. Ch nhng cng ty rt ln, v c nh my sn xut chip ring mi s dng phng php thit k ny.

Fail Fail Function Design Schematic Design Function And Timing verification
Pass

Layout Design

Post-Layout Pass Simulation

Fabrication

Hnh 1 : Full custom Design Methodology

Hin nay, theo qui trnh sn xut Chip fabless, cc nh sn xut chip khng trc tip ch to ra chip m h ch thit k cp cao ri outsource cho cc cng ty sn xut chuyn sn xut chip nh TSMC, Samsung gia cng. Phng php thit k ny da trn cc standard-cell do cc nh sn xut chip cung cp sn.
Logic Gate Library Cell Layout Library

VHDL or Verilog Coding

VHDL or Verilog Cimulation

RTL Design

High-Level Simulation Fail

Logic Synthesis

Gate-level Simulation Fail

Placement & Routing

Post-Layout Simulation Fail

Fabrication

Hnh 2 : Standard-Cell Based Design Methodology

Phng php thit k da trn FPGA , cng gn ging nh phng php thit k standardcell Based . Nhng n s dng cc FPGAs logic cell , phng php ny cho thi gian thit k v sn xut rt nhanh, v cc Chip FPGA c sn xut t trc , ri ro cng thp. Tuy nhin nhc im ca n l mt tch hp khng cao lm, tc cng khng bng hai phng php thit k trn. Tuy nhin phng php thit k da trn FPGA vn c s dng rt nhiu do thi gian thit k nhanh, c kh nng ti cu hnh ng.
FPGA Cell Library

VHDL or Verilog Coding

VHDL or Verilog Cimulation

RTL Design

High-Level Simulation Fail

Logic Synthesis

Placement & Routing

Post-Layout Verification Fail

Generate FPGA bitstream

Download

FPGA

Hnh 3 : FPGA-based Design Methodology

Hnh sau l mt v d v kin trc ca mt FPGA cng nghip v chip FPGA trong thc t.

Hnh 4 : V d v mt kin trc ca FPGA

ng dng ca FPGA : L tng cho vic ch to cc sn phm mu prototype. Cc thit b cn thi gian bn ra th trng ngn. Cc sn phm s lng nh, theo yu cu khch hng. Cc phn cng cn kh nng ti cu hnh linh hot. Cc h thng cn thay i cu hnh trong qu trnh hot ng (vd nh SDR)

II. Gii thiu FPGA

Qui c t tn cho FPGA ca altera.

Hnh 5 : Qui c t tn cho FPGA ca Altera

Logic Element y l phn t logic nh nht trong kin trc FPGA thng thng, gi tt l LE, n cho php thc hin cc chc nng logic hiu qu. c tnh ca mt LE : L mt bng tra 4 ng vo (hoc nhiu hn ty kin trc FPGA) gi l look-up table (LUT), m c th thc hin hm logic 4 bin bt k. Mt thanh ghi c th lp trnh c (programmable register) Mt chui cc kt ni mt xch. Mt chui kt ni cc thanh ghi. C kh nng li tt c cc loi lien kt ni bao gm : local, row, column, register chain, hoc ni trc tip Lin kt ni. H tr register packing H tr register feedback

Hnh 6 : Logic Element

LE Features Ta c th cu hnh mi thanh ghi ca LE thnh D, T, JK, hoc SR flip-flop. Mi thanh ghi c data, clock, clock enable, v chn clear. Tn hiu c th l global clock network, cc chn I/O pins, hoc bt k logic ni no. Cc chn I/O pins hoc logic ni c th li cc chn enable. Nu mun LE thc hin chc nng ca cc mch t hp, LUT s c bypass qua khi thanh ghi. Mng Logic (Logic Array Block) Mt mng logic bao gm nhiu khi LE v cc h thng lin kt ni hng ,ct , h thng bus ni b

Hnh 7 : LAB

Mng clock (Clock Network) Bi v clock c th cn phn phi ton b chip FPGA, v yu cu nghim ngt v timing, do clock c phn phi n ton b FPGA bi mt mng clock nh hnh 4.

Hnh 8 : Clock Network

I/O Pins H thng IO ca FPGA thng t chc thnh cc Bank, mi bank gm nhiu chn IO c cng tnh nng. h tr nhiu h thng phn cng khc nhau, cc chn IO ca FPGA gm hng chc kiu khc nhau vi cc tnh cht v in cng khc nhau (xem bng).

Hnh 9 : IO Pins

Hnh 10 : IO Banks

Kin trc ca mt FPGA

Hnh 11 : FPGA Architecture

Ngoi cc phn t c bn nh LE, LAB, Clock, IO pin. FPGA cn c cc phn t Embedded Memory block, Embedded Multiplier, DSP Block, Integrated Controller

III.

Gii thiu Board DE2 ca Altera

1. Gii thiu

Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc lnh vc lun l s hc (digital logic), t chc my tnh (computer organization) v FPGA.

Hnh 12 : Board DE2

Hnh 13 : DE2 Block diagram 2. Thnh phn

Board DE2 cung cp kh nhiu tnh nng h tr cho vic nghin cu v pht trin, di y l thng tin chi tit ca mt board DE2: FPGA: - Vi mch FPGA Altera Cyclone II 2C35. - Vi mch Altera Serial Configuration EPCS16. Cc thit b xut nhp: - USB Blaster cho lp trnh v iu khin API ca ngi dung; h tr c 2 ch lp trnh JTAG v AS. - B iu khin Cng 10/100 Ethernet. - Cng VGA-out. - B gii m TV v cng ni TV-in. - B iu khin USB Host/Slave vi cng USB kiu A v kiu B. - Cng ni PS/2 chut/bn phm. - B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in, lineout, v microphone. - 2 Header m rng 40-pin vi lp bo v diode. - Cng giao tip RS-232 v cng ni 9-pin. - Cng giao tip hng ngoi. B nh: - SRAM 512-Kbyte. - SDRAM 8-Mbyte. - B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte). - Khe SD card. Switch, cc n led, LCD, xung clock - 4 nt nhn, 18 nt gt. - 18 LED , 9 LED xanh, 8 Led 7 on - LCD 16x2 - B dao ng 50-MHz v 27-MHz cho ng h ngun.
3. Mt vi ng dng ca board DE2

ng dng lm TV box

Hnh 14 : ng dng TV Box

Chng trnh v bng chut USB (paintbrush)

Hnh 15 : Chng trnh v (paintbrush)

My ht Karaoke v my chi nhc SD

Hnh 16 : My ht Karaoke v my chi nhc t card SD

IV.

Cch ci t Quartus II 10.0 v Nios II

1. Gii thiu

B phn mm thit k i km vi board DE2 bao gm 2 a CDROM: Quartus 2 v Nios 2 Integrated Development Environment (IDE) Quartus II l phn mm h tr tt c mi qu trnh thit k mt mch logic, bao gm qu trnh thit k, tng hp, placement v routing (sp xp v chy dy), m phng (simulation), v lp trnh ln thit b (DE2). Nios II, mi trng pht trin tch hp ca h Nios II (IDE), n l cng c pht trin ch yu ca h vi x l Nios II. Phn mm s l mi trng cung cp kh nng chnh sa, xy dng, debug v m t s lc v chng trnh. IDE cn cho php to cc chng trnh t n nhim (single-threaded) n cc chng trnh phc tp da trn mt h iu hnh thi gian thc v cc th vin middleware. Ngoi ra, chng ta c th cn mt chng trnh m phng code Verilog cp RTL (mc truyn thanh ghi) hoc m phng mc cng (Gate level Simulation)
2. Ci t

Ci t Quartus II v Nios II Qu trnh ci t Quartus II v Nios n gin ch cn a a vo my v thc hin theo hng dn ca chng trnh ci t nh bt k phn mm no .

Hnh 17 : Phn mm Quartus v Nios II IDE

Ci t phn mm USB blaster driver V Board DE2 c lp trnh (programming) bng cch s dng cng c USB Blaster (USB Blaster mechanism). Do , c th kt ni kit DE2 v lp trnh thng qua my PC, chng ta cn phi ci t driver cho thit b USB Blaster . Sau khi gn board DE2 vo my tnh thng qua cng USB, nu USB Blaster driver cha c ci t th hp thoi sau s xut hin, Chn No, not this time sau nhn Next

Hnh 18 : Thng bo cha ci dirver

Chn Install from a specific location v chn Next

Hnh 19 : Chn cch thc ci t driver

Kt tip bn chn Search for the best driver in these location v sau nhn Browse.

Hnh 20 : Chn th mc tm kim driver

Hp thoi mi s xut hin bn tm n v tr C:\altera\10.0\quartus\drivers \usbblaster, sau nhn OK v tip tc nhn Next

Hnh 21 : Chn th mc cha dirver

Ca s thng bo vic kim tra logo window khng thnh cng, tuy nhin vic ny s khng b nh hng n vic kt ni ca chng trnh sau ny. Bn tip tc nhn Continue Anyway. Nhn Finish hon tt vic ci t. Ch driver USB blaster c th nm trong th mc khc so vi hng dn ty thuc vo phin bn quartus m bn ci t, thm ch bn c th copy driver ti mt th mc khc v tr ng dn ti th mc ny khi ci t.

V. To mt project mi vi Quartus II 10.0:

1. To 1 project:

Bc 1. Vo Menu > file chn New Project Wizard

Hnh 22 : To mi mt project

Bc 2. Ta chn th mc cha project v t tn cho project, xem hnh bn di

Hnh 23 : Chn tn v ng dn

 1:Chn dng dn th mc 2: Chn tn th mc Bc 3. Sau ta chn hng sn xut chip v tn loi chip trn mch (EP2C35F672C6)

Hnh 24 : Hp thoi la chn chip

Bc 4. Cui cng chn Finish hon tt

2. Vit chng trnh v bin dch:

Bc 1. Vo Menu > file chn New

Hnh 25 : To mi file

Bc 2. Sau chn loi file m chng ta mun vit chng trnh. y ta chn loai file Verilog HDL

Hnh 26 : La chn loi file cn to

Bc 3. Di y l mt on chng trnh demo: tnh hm f = x1 EX-OR x2

Hnh 27 : Ca s vit code

Bc 4. Sau khi vit xong th ta phi lu tn file trng vi tn module ca chng trnh

Hnh 28 : Hp thoi lu file

Ch : Chn Add file to current project Bc 5. Sau khi lu file xong phi thit lp cho file l top-level th mi bin dch c

Hnh 29 : La chn lop-level cho file

Bc 6. Bin dch chng trnh:

Hnh 30 : Bin dch chng trnh

Hnh 31 : Thng bo vic bin dch thnh cng

Ch : n y th c th np trc tip ln board DE2 kim th hoc s dng chng trnh m phng c trn Quartus II.
3. Gn chn v np xung phn cng FPGA:

Bc 7. Gn chn cho thit k: cc bc trn ta mi ch thc hin thit k v bin dch chng trnh. c th chy th trn phn cng FPGA, chng ta cn phi thc hin gn chn cho thit k. Qu trnh gn chn (Pin assignment) l qu trnh ch nh cc input/outout/inout trong thit k (logic) kt ni ti mt chn vt l thc s trn chip FPGA (physical). H thng chn ca FPGA c nh nhn bi ch ci v s theo qui nh ca nh sn xut FPGA, v d nh N25,M20 ta xem thng tin cc chn ny trong ti liu datasheet ca dng chip Cyclone II.

Hnh 32 : Pin planner (s layout chn ca mt chip FPGA)

Tuy nhin, khi thit k board DE2, nh thit k Terasic kt ni c nh cc chn ca FPGA vi phn cng tng ng trn kit, v d : nh SW[0] c kt ni vi PIN_N25, v LEDR[0] c kt ni vi chn PIN_AE23 ca Cyclone II. Nh vy, khi ta kt ni mt chn logic f (ca thit k) vi chn PIN_AE23 ca FPGA. C ngha l chn f trong thit k light.v s c kt ni trc tip vi LEDR[0] khi ta np thit k xung kit DE2. gn chn, ta vo menu Assignment>Pin planner, s hin ra hp thoi sau :

Hnh 33 : hp thoi Pin Planner

Trong thit k ny ta c 3 chn : f,x1,x2 .vi f l chn output, ta s gn cho LEDR[0]. x1,x2 l input, ta s gn cho SW[0] v SW[1]. Sau khi gn xong, ta s c nh sau:

Hnh 34 : gn chn cho thit k

Sau khi gn chn xong, ta thc hin bin dch li thit k cp nht thng tin v pin. Mt cu hi t ra l : ta ly thng tin v cc chn ny u ? Tr li : V cc chn ny c ghp ni vi phn cng trn board bi nh thit k board DE2, do c thng tin v chn IO, ta tm trong ti liu DE2 manual. Mt cch khc, cc nh thit k board FPGA thng cung cp mt file CSV (mt dng ging excel) c th import trc tip vo phn mm quartus vi tn chn c nh ngha sn, vd file DE2_pin_assignments.csv i vi board DE2. import file ny,vo assignments>import assignments. Chn ng dn n file DE2_pin_assignments.csvri nhn OK. kim tra kt qu, vo li Assignments>Pin Planner, s thy nh sau.

Bc 8. Np xung FPGA trn kit DE2: Chip FPGA phi c np v cu hnh thc hin thit k ca chng ta. File cu hnh c to ra bi qu trnh compile ca phn mm Quartus nu khng c li xy ra. V chng ta c th lp trnh v cu hnh FPGA theo hai cch, l ch JTAG v AS. File cu hnh c truyn t my ch PC (chy quartus) xung board FPGA bi mt cp USB kt ni gia board v my tnh PC. s dng cp ny, chng ta cn phi ci driver USB blaster nh ni trn. Trc khi np chng trnh, chng ta phi m bo cp USB c kt ni v board FPGA bt ngun. Trng ch np JTAG, FPGA s gi nguyn cu hnh c np min l cn cp ngun cho kit FPGA, c ngha l khi mt ngun, Chip FPGA s b mt cu hnh v tr thnh thit b

trng. Trong ch th hai, ch AS, file cu hnh c lu trong chip flash trn kit FPGA. V n s c load vo FPGA mi khi bt ngun, v vy, chng ta s khng cn phi np li file cu hnh mi khi bt ngun kit FPGA na (nh trng hp np JTAG) . chn la mode np, chn RUN/PROG switch trn DE2 board. V tr RUN l chn JTAG mode, cn v tr PROG l chn AS mode. Qu trnh np thng qua mode JTAG nh sau : o Gt switch RUN/PROG trn FPGA sang v tr RUN. o Chn Tools>Programmer. Mt ca s s hin ra nh hnh 35. o y chng ta cn phi ch nh cng c lp trnh v mode lp trnh o Chn JTAG trong hp thoi mode o Nu USB-Blaster cha c chn, nhn vo hardware Setup v chn USBBlaster trong hp thoi s xung nh hnh 36

Hnh 35 : Hp thoi programming

Hnh 36 : Chn cng c lp trnh USB blaster

o Nu khng thy hin ln thit b USB-Blaster no, hy kim tra cp USB, bt ngun board, driver o Sau chn file cn np dng sof (nu n cha c sn trong hp thoi) bng cch nhn Add file o Sau khi chn xong, nhn start bt u lp trnh. Mt led trn board s sang chi n khi qu trnh lp trnh thnh cng.

o Nu c bt c li g hin ln trn ca s quartus,th hy kim tra li board cp ngun cha. Nu vn khng pht hin ra li, hy hi thy hng dn ca bn c gip . Qu trnh np thng qua mode Active Serial nh sau : o chn thit b cn lp trnh, chn Assignments>Device nh hnh 37. o Click vo Device & Pin Options v chn nh hnh 38, ri nhn OK quay li hnh 38, tip tc nhn OK ri compile li ton b project.

Hnh 37 : Device Windows

Hnh 38 : Chn thit b lp trnh

o Sau khi compile xong th chn Tools>Programmer nh trn. o Chn Active Serial Programming trong hp thoi mode o Tin hnh cc bc tng t nh trn. Bc 9. Kim tra thit k. o Sau khi np xung Kit FPGA, gi y ta c th kim tra thit k ca mnh o Gt switch RUN/PROG sang v tr RUN. o Th tt c cc gi tr ca bin u vo x1 v x2 bng cch thay i trng thi SW0 v SW1 trn board. Kim tra kt qu vi bng s tht bng cch quan st trng thi led. o Nu mch hot ng khng ng nh thit k, hy sa li code, kim tra gn chn compile li, np li v kim tra li cho n khi mch hot ng ng nh mong mun.

Phn 2 : H thng bi lab ca altera

1. Gii thiu v h thng bi lab ca altera

Trong gio trnh ny, chng ta s s dng h thng bi lab tiu chun ca altera gm 9 bi t lab 0 ti lab 8. Hon thnh 9 bi lab ny, chng ta s c nhng k nng c bn trong lnh vc thit k chip s dng ngn ng Verilog HDL.

Lab 0a : Thit k bng s mch trn Altera Quartus Lab 0b : Thit k bng ngn ng m t phn cng Verilog HDL trn Altera Quartus Lab 1 : Cng tc, leds, v b ghp knh Lab 2 : H thng S v hin th Lab 3 : Latch & Flipflop (Option) Lab 4 : B m Counter Lab 5 : Clocks v Timers Lab 6 : B cng, tr, nhn Lab 7 : My trng thi Lab 8 : B vi x l n gin

Ty theo chng trnh hc s c yu cu khc nhau : i vi chng trnh i hc lin thng, yu cu thc hin t Lab 0 ti Lab 5 i vi chng trnh i hc chnh qui, yu cu thc hin t Lab 0 ti Lab 7 i vi h nng cao, yu cu thc hin thm Lab 8

Ty theo c s h tng thit b, cc bi lab c th thc hin theo cc cch khc nhau : Nu khng c phn cng, c th m phng bng phn mm model-sim hoc quartus simulation Nu c phn cng (DE1,DE2 hoc tng ng) c th tng hp trc tip v thc hin ngay trn phn cng ca kit FPGA (c th m phng hoc khng, ty yu cu ca gio vin hng dn).

2. Chi tit cc bi lab phi thc hin

Lab 0: FPGA Design using Quartus II o Quartus II Introduction Using Schematic Design o Quartus II Introduction Using Verilog Design Lab 1: Switches, Lights, and Multiplexers o Part 1.1 : Led Control o Part 1.2 : Design 2 to 1 Multiplexer o Part 1.3A : Design 5 to 1 Multiplexer from Mux2to1 o Part 1.3B : Extend to 8-bit Mux5to1 o Part 1.4 : Design Led 7 Segments Decoder o Part 1.5 : 7-Segments Led display. o Part 1.6: Led Rotation on 7-Segment Leds. (Optional) Lab 2: Numbers and Displays o Part2.1: Binary-to-Decimal conversion o Part2.2: BCD Display on 7-Segment Led o Part2.3: Implement 4-bit Adder (RCA) o Part2.4 : Design BCD Adder o Part 2.5 : Design 2-digit BCD Adder Lab 3: Latch & Flipflop (Optional) Lab 4: Counters o Part 4.1 : Design A 4-bit synchronous Counter o Part 4.2 : 7-segment Led Counter o Part 4.3 : Display scrolling text on 7-Segment Led Lab 5: Clocks and Timers o Part 5.1 : Implement a 3-digit BCD counter o Part 5.2 : Implement a time-of-day clock o Part 5.3 : Design and implement a reaction-timer circuit. Lab 6: Adders, Subtractors, and Multipliers o Part 6.1 : Design a 8-bit 2s-complement Adder o Part 6.2 : Expand to 8-bit Add/Sub Circuit o Part 6.3 : Implement a 4-bit Multiplier o Part 6.4 : Extend the multiplier to multiply 8-bit numbers o Part 6.5 : Design a MAC circuit (Multiply Accumulate Circuit) Lab 7: Finite State Machines o Part 7.1 : Finite State Machines o Part 7.2 : Design a modulo-10 counter-like circuit o Part 7.3 : Design a scrolling text display using shift-register Lab 8: A Simple Processor (Optional) o Part 8.1 : Design a simple Processor o Part 8.2 : Design a simple CPU with Memory and PC counter

Reference Documents
1) Haibo Wang , ECE428, ECE Department , Southern Illinois University , Carbondale, IL 62901. 2) Ti liu TN FPGA, Khoa KH-KTMT ,Trng i Hc BK TP HCM 3) Altera University Program Documents 4) Altera website 5) Internet