. .

.

1.
. .
(Integrated Circuit)
)
,
.

Jack Kilby Texas struments Robert Noyce Fairchild Semiconductor
( 1958). Kilby
2000 .

, , , ,
. [1],
[2], [3].
( ).

(. ).
,
, (
),
, , ,
.
. 1 -


[7].

 1
:
- nMOS n- MOS
;
-CMOS n-
p- MOS ;
-BiCMOS n p- MOS
;;
-ECL
;
-GaAs - GaAs.
1.1. ,
.

(
) .
(Scale Integration) [3], [7].


,
. -
( ) ,
- (
) .
(SSI small-scale integration): 100 .

I ( 1)
.

(MSI - medium-scale integration): 100 3,000
.
..
(Programmable logi devices -PLD) - PAL,PLA, PROM,
EPROM .

(Programmable array logic
-PAL),

.

(Erasable Programmable ReadOnly Memory - EPROM),

,
.

.
(LSI large-scale integration): 3,000 100,000
.
-
(Microprocessors),
(Complex Programmable Logic Devices - CPLD),
(Random Access Memory - RAM).

(Al

tera MAX 7000-series Complex
Programmable Logic Device CPLD) ,
(
)
.

(VLSI - very large-scale integration):
100,000 1,000,000 .

, .. (Field
programmable gate arrays - FPGA).

( Altera Stratix
II GX Field
Programmable Gate
Array - FPGA),

- (systemson-chip).

(ULSI - ultra large-scale integration):
1,000,000 .

, .
1.2.


,
(.2):
(Standard integrated circuits)
( Application Specific Integrated
Circuits - ASICs ) [2], [7].

(ASIC)

2


.
:

Intel Pentium Dual-Core E2140

SIM - RAM -
, .

(The Application-specific Integrated Circuits - ASICs)
,
( ).

,
.

 (layout)

o

ASIC :
(. 3):

(ASIC)

(
)

3

( )

,
[3], [7].

, , ,
.


(
) ()
( )

, , .

.
2. ( )
(PLD) [4]
.4
()
:


( )

(PLD)

PROM

PROM

EPROM

PAL

EEPROM

GAL

FLASH

CPLD

FPGA

 4

( ) .
.
(Programmable
Logic Devices - PLD)
()
,
( ), , ,
.
2.1.

(MSI chips) PROM, PLA, PAL, GAL.
[4], [8]
(PLD)
:

( ) , ,
, , ;

()
(
)
( ) ;

() (fusible
links) .
PLD:

(AND)

(OR)
;


- AND-;

AND ( product line)

OR - ;
PLD:
AND -
OR -

PROM

PAL

PLA

,
PLD

PLD :

 5
2.2. (
) PLD [4].

PLD - ,

,
.

.
.6
- PLD
, (
, :

 6
PAL
.. GAL (generic array logic) .

, PAL,


.
GAL 16V8 20V8 Lattice
corporation
GAL-

OR
AND
.
PAL, , AND
GAL

( floating
gate transistors).
7


.


( - OFF),

,
.
.

(

)

.

8
2.3. (
) PLD
. [4]
PLD
()
(programming unit), ( )

(text entry) (schematic capture)
:

 9
3.
e
(LSI VLSI) -
(CPLD) (FPGA). [1], [3], [7]
(Complex
Programmable Logic Devices CPLDs)
(Field Programmable Gate Arrays FPGAs) ,
-
(PLD) - (
), ( CPLD ),
( FPGA). ,

, .

(.10)

. , , ,
CPLD FPGA -.

 10
3.1. ,
CPLD . [4]
CPLD Xilinx

, CPLD
, .11 :

 11
, ,
CPLD ,
PLD - ( PLA , PAL),
( ).
,
CPLD -
CoolRunner II:

12
PLD ,

.
- ,
CoolRunner II (

, ,
, ):

()
CPLD- :

CPLD- - MOS -
, .
CPLD : ,
() :
, (LAN - ),
(UARTs ),
, (cache control ),
.

( )
,
CPLD .
3.2. ,
FPGA . [1],[3],[4], [12], [14]

FPGA Altera Xilinx

FPGA
( )
,
, ,
/ .

.
.13 FPGA :

13
- , FPGA
[1]
.14:

14
.15 .16
FPGA Spartan 3e,
[9]:

 15

16

:

17
, FPGA

Spartan 3e, :

FPGA- :
FPGA-

,

,
D
(
SRAM )

SRAM

,


FPGA .
3.3. FPGA
. [13],
[14], [15], [16]
FPGA
()
,
,
, ,
,

 (), -
, .

,
, FPGA ,


.
. 18
-- (System-on-Chip) ,
(soft-) MicroBlaze FPGA Virtex-6
Spartan-6 Xilinx.

18
. 19 - - FPGA
Spartan-6, (soft-)
MicroBlaze.

 19
. 20 FPGA
Virtex-6
:

20
. 21 FPGA
Virtex-6

 21
3.4. CPLD- FPGA- .
.[4]
CPLD, FPGA
- ,
/
. CPLD- , - -,
- , -
, , RAM.

() CPLD FPGA
.22.
- PLD
- ( ),

, ,
.
CPLD FPGA
, (- USB)
.

 22
.23
CPLD CoolRunner-II Xilinx ()
FPGA Spartan 3e Xilinx
().

.

23
3.5.
FPGA - .
.
.

FPGA ,
, .24:

 24

FPGA - , ,
(ISE, Xilinx) , :

- CPLD FPGA
, ,
.

, ( )
,
( ) .
.25:
:
,,

RTL -

RTL - ,

VHDL

FPGA -

FPGA

FPGA -

FPGA

25

3.6.

(CPLD, FPGA)
. [1], [5], [6]
Oa ,

.

(HDL), VHDL,
Verilog MATLAB,
( )
.
, ,
.
,
, ++:

-
,
VHDL.

Library...

Entity < > is

Port(...

()

()

( /

End < >

Architecture < >

of< >

Begin

End < >

26

. 27
, ,
.
. 28 , a VHDL
. 29

27
16

P
Q
R
S

16

16

16

CLK
mult

mult

A11
register

mult

A12
register

mult

A13
register

sub

A14
register

sub

register

register

16
M
N

32
sub

adder

sub

adder

Mp

Pp

Np

Qp

register

register

register

register

32

32

32

32

28

Qp
Np
Pp
Mp

VHDL -

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Fourier_butterfly is
port (CLK : std_logic;
P : in std_logic_vector (15 downto 0);
Q : in std_logic_vector (15 downto 0);
R : in std_logic_vector (15 downto 0);
S : in std_logic_vector (15 downto 0);
M : in std_logic_vector (31 downto 0);
N : in std_logic_vector (31 downto 0);
Mp : out std_logic_vector (31 downto 0);
Np : out std_logic_vector (31 downto 0);
Pp : out std_logic_vector (31 downto 0);
Qp : out std_logic_vector (31 downto 0) );
end Fourier_butterfly;

architecture Stage_1_2_3 of
Fourier_butterfly
signal Al1, Al2, Al3, Al4, A, B :
std_logic_vector (31 downto 0);
begin
process (CLK )
begin
if (CLK'event and CLK='1') then
Al1 <= P * R; Al2 <= S * Q;
Al3 <= P * S; Al4 <= R * Q;
A <= Al1 - Al2; B <= Al3 - Al4;
Mp <= M - A; Pp <= M + A;
Qp <= N + B; Np <= N - B;
end if;
end process;
end Stage_1_2_3;

29
:
1. .,
VHDL, -, 2006
2. . , , - , 2005
3. ., ., , -,
2006
4. . , 1998
5. Armstrong J. Structured Logic Design with VHDL, 1993
6. Lipsett R. VHDL: Hardware Description and Design, 1993
7. Weste N., K. Eshraghian, Principles of CMOS VLSI Design, AddisonWesley Publishing, Second edition, 2001
8. Wakerly J., Digital Design Principles and Practices, Prentice Hall Xilinx
Design Series, 2002.
9. Xilinx, Spartan-3E Starter Kit Board User Guide, UG230(v1.0) March 9,
2006
10. Altera, Video and Image Processing Design Using FPGAs, White
paper, March 2007, ver. 1.1
12. Altera, Cyclone II Device Family Data Sheet. http://www.altera.com.

16.

13. http://www.xilinx.com/products/spartan6/index.htm
14. http://www.xilinx.com/products/virtex6/
15. http://www.xilinx.com/products/devkits/EK-S6-SP605-G.htm
http://www.xilinx.com/products/devkits/EK-V6-ML605-

G.htm

.
.
.
1.

.
.
(Integrated Circuit)
)
,
.

Jack Kilby Texas struments Robert Noyce Fairchild Semiconductor
( 1958). Kilby
2000 .

, , , ,
. [1],
[2], [3].
( ).

(. ).
,
, (
),
, , ,
.
. 1 -


[7].

 1
:
- nMOS n- MOS
;
-CMOS n-
p- MOS ;
-BiCMOS n p- MOS
;;
-ECL
;
-GaAs - GaAs.
1.1. ,
.

(
) .
(Scale Integration) [3], [7].


,
. -
( ) ,
- (
) .
(SSI small-scale integration): 100 .

I ( 1)
.

(MSI - medium-scale integration): 100 3,000
.
..
(Programmable logi devices -PLD) - PAL,PLA, PROM,
EPROM .

(Programmable
array
logic
-PAL),

(Erasable Programmable ReadOnly Memory

- EPROM),

,
.

.
(LSI large-scale integration): 3,000 100,000
.

-
(Microprocessors),
(Complex Programmable Logic Devices - CPLD),
(Random Access Memory - RAM).

(Al

tera MAX 7000-series Complex

Programmable Logic Device CPLD)
,

(
)
.

(VLSI - very large-scale integration):

100,000 1,000,000 .

..

(Field
programmable gate arrays - FPGA).

( Altera Stratix
II
GX
Field
Programmable
Gate
Array
FPGA),

- (systemson-chip).

(ULSI - ultra large-scale integration):
1,000,000 .

, .
1.2.


,
(.2):
(Standard integrated circuits)
( Application Specific Integrated
Circuits - ASICs ) [2], [7].

(ASIC)

2


.
:

Intel Pentium Dual-Core E2140

SIM - RAM
, .

(The Application-specific Integrated Circuits - ASICs)
,
( ).

,
.

 (layout)

o

ASIC :
(. 3):

(ASIC)

(
)

3

( )

,
[3], [7].

, , ,
.



(
) ()
( )

, , .

.
2. ( )
(PLD) [4]
.4
()
:


( )

(PLD)

PROM

PROM

EPROM

PAL

EEPROM

GAL

FLASH

CPLD

FPGA

 4

( ) .
.

(Programmable
Logic Devices - PLD)
()

,

( ), , ,
.

2.1.

(MSI chips) PROM, PLA, PAL, GAL.
[4], [8]

(PLD)

( ) , ,
, , ;

()
(
)
( ) ;

() (fusible
links) .
PLD:

(AND)

(OR)
;

- AND-;
AND ( product line)
OR - ;

PLD:
AND -
OR -

PROM

PAL

PLA

,
PLD

PLD :

 5
2.2. (
) PLD [4].

PLD - ,

,
.

.
.6
- PLD
, (

 , :

6
PAL
.. GAL (generic array logic) .

, PAL,


.
GAL

16V8

corporation

20V8

Lattice

GAL- OR
AND . PAL, , AND
GAL
( floating gate transistors).
.

( - OFF),

,
.
.

(

)


.

8
2.3. (
) PLD

. [4]

PLD

()
(programming unit), ( )

(text entry) (schematic capture)
:

9
3.

e
(LSI VLSI) -
(CPLD) (FPGA). [1], [3], [7]

(Complex
Programmable Logic Devices CPLDs)
(Field Programmable Gate Arrays FPGAs) ,
-
(PLD) - (
), ( CPLD ),
( FPGA). ,

, .

(.10)

. , , ,
CPLD FPGA -.

 10
3.1. ,
CPLD . [4]
CPLD Xilinx

, CPLD
, .11 :

 11
, , CPLD
,
PLD - ( PLA , PAL),
( ).
,
CPLD - CoolRunner II:

12
PLD ,

.
- ,
CoolRunner II (

, ,
, ):

()
CPLD- :
CPLD-
- MOS ,

CPLD
: ,
() : ,
(LAN - ),
(UARTs ), ,
(cache control ),
.

( )
,
CPLD .
3.2. ,
FPGA . [1],[3],[4], [12], [14]

FPGA Altera Xilinx

FPGA
( )
,
, ,
/ .

 .
.13 FPGA :

13
- ,
FPGA [1]
.14:

14
.15 .16
FPGA Spartan 3e,
[9]:

 15

16

:

17
, FPGA

Spartan 3e, :

FPGA- :

FPGA

,

SRAM )

SRAM

FPGA .
3.3. FPGA
. [13],
[14], [15], [16]
FPGA

()
,
,
, ,
,

 (), -
, .

,
, FPGA ,


.
. 18
-- (System-on-Chip) ,
(soft-) MicroBlaze FPGA Virtex-6
Spartan-6 Xilinx.

18
. 19 - - FPGA
Spartan-6, (soft-)
MicroBlaze.

 19
. 20 FPGA
Virtex-6
:

20
. 21 FPGA
Virtex-6

 21
3.4. CPLD- FPGA- .
.[4]
CPLD, FPGA
- ,
/

. CPLD- , - -,
- , -
, , RAM.

() CPLD
FPGA
.22.
- PLD
- ( ),

, ,
.
CPLD FPGA
, (- USB)
.

 22
.23
CPLD CoolRunner-II Xilinx ()
FPGA Spartan 3e Xilinx
().

.

23
3.5.
FPGA - .

.
.

FPGA ,
, .24:

 24

FPGA - , ,
(ISE, Xilinx) , :

- CPLD
FPGA
, ,
.

, ( )
,
( ) .
.25:
:
,,

RTL -

RTL - ,

VHDL

FPGA -

FPGA

FPGA -

FPGA

25

3.6.

(CPLD, FPGA)
. [1], [5], [6]
Oa ,

.

(HDL), VHDL,
Verilog MATLAB,
( )
.
, ,
.
,
, ++:

-
,
VHDL.

Library...

Entity < > is

Port(...

()

()

( /

End < >

Architecture < >

of< >

Begin

End < >

26

. 27
, ,
.
. 28 , a VHDL
. 29

27
16

P
Q
R
S

16

16

16

CLK
mult

mult

A11
register

mult

A12
register

mult

A13
register

sub

A14
register

sub

register

register

16
M
N

32
sub

adder

sub

adder

Mp

Pp

Np

Qp

register

register

register

register

32

32

32

32

28

Qp
Np
Pp
Mp

VHDL -

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Fourier_butterfly is
port (CLK : std_logic;
P : in std_logic_vector (15 downto 0);
Q : in std_logic_vector (15 downto 0);
R : in std_logic_vector (15 downto 0);
S : in std_logic_vector (15 downto 0);
M : in std_logic_vector (31 downto 0);
N : in std_logic_vector (31 downto 0);
Mp : out std_logic_vector (31 downto 0);
Np : out std_logic_vector (31 downto 0);
Pp : out std_logic_vector (31 downto 0);
Qp : out std_logic_vector (31 downto 0) );
end Fourier_butterfly;

architecture Stage_1_2_3 of
Fourier_butterfly
signal Al1, Al2, Al3, Al4, A, B :
std_logic_vector (31 downto 0);
begin
process (CLK )
begin
if (CLK'event and CLK='1') then
Al1 <= P * R; Al2 <= S * Q;
Al3 <= P * S; Al4 <= R * Q;
A <= Al1 - Al2; B <= Al3 - Al4;
Mp <= M - A; Pp <= M + A;
Qp <= N + B; Np <= N - B;
end if;
end process;
end Stage_1_2_3;

29
:
1. .,
VHDL, -, 2006
2. . , , - , 2005
3. ., ., , -,
2006
4. . , 1998
5. Armstrong J. Structured Logic Design with VHDL, 1993
6. Lipsett R. VHDL: Hardware Description and Design, 1993
7. Weste N., K. Eshraghian, Principles of CMOS VLSI Design, AddisonWesley Publishing, Second edition, 2001
8. Wakerly J., Digital Design Principles and Practices, Prentice Hall Xilinx
Design Series, 2002.
9. Xilinx, Spartan-3E Starter Kit Board User Guide, UG230(v1.0) March 9,
2006
10. Altera, Video and Image Processing Design Using FPGAs, White
paper, March 2007, ver. 1.1
12. Altera, Cyclone II Device Family Data Sheet. http://www.altera.com.

13. http://www.xilinx.com/products/spartan6/index.htm
14. http://www.xilinx.com/products/virtex6/
15. http://www.xilinx.com/products/devkits/EK-S6-SP605-G.htm
16. http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm