DVD PLAYER

DVD-909
DVD-709

SERVICE MANUAL
SERVICE Manual

DVD-909/709
DVD PLAYER CONTENTS
1. Precautions
ELECTRONICS 2. Reference Information
3. Product Specification
4. Operating Instructions

STANDBY PHONE LEVEL DVD/VIDEO-CD/CD PLAYER DVD-909

SKIP 5. Disassembly and Reassembly
POWER OPEN/
OPEN/
OPEN/
CLOSE
CLOSE
CLOSE

6. Circuit Descriptions
MIN MAX

ADVANCED DOLBY DIGITAL DECORDER BUILT-IN SPATIALIZER

N-2-2
DIGITAL VIDEO

DVD-909 7. Troubleshooting
8. Exploded Views and Parts List
9. Electrical Parts List
10. Block Diagrams
SKIP

STANDBY

POWER
DVD/VIDEO-CD/CD PLAYER DVD-709

OPEN/
OPEN/
CLOSE
CLOSE
11. PCB Diagrams
24bit 96kHz AUDIO D/A CONVERTER SPATIALIZER
N-2-2
DIGITAL VIDEO

12. Wiring Diagram

DVD-709
13. Schematic Diagrams

© Samsung Electronics Co., Ltd. NOV. 1999

Printed in Korea
AH68-00137A
REV.-2
2. Reference Information
2-1 IC Dsecriptions
2-1-1 AIC1 (AK4324 ; Digital-to-Analog Converter)
DIF0 DIF1 DIF2 DEM0 DEM1 AVDD AVSS

LRCK De-emphasis
Serial Input Control
BICK Interface DZFL
SDATA

AOUTL+
PD 8X ∆∑
SCF
Interpolator Modulator AOUTL-

SMUTE

AOUTR+
DFS
8X ∆∑
Interpolator SCF
Modulator AOUTR-

Clock Divider
DZFR

MCLK CKS DVDD DVSS VREF

PIN I / O NAME FUNCTION PIN I / O NAME FUNCTION

1 - DVSS Digital ground pin 13 I DIF0 Digital input format pin

2 I DVDD Digital power supply 14 I DIF1 Digital input format pin

Master clock select pin (Internal pull-down pin)
3 I CKS Nomal speed "L":MCLK = 256fs, "H":MCLK = 384fs 15 I DIF2 Digital input format pin
Double speed "L":MCLK = 128fs, "H":MCLK = 192fs
4 I MCLK Master clock input pin 16 0 AOUTR- Rch negative analog output pin
Power-Down mode pin. When at "L", the AK4324 is in
5 I PD power-down and is held in rest. 17 O AOUTR+ Rch positive analog output pin
The AK4324 should always be reset upon power-pin
Audio serial data input pin
6 I BICK 18 O AOUTL- Lch negative analog output pin
64fs clock is recommended to be input on this pin
Audio serial data input pin
7 I SDATA 19 O AOUTL+ Lch positive analog output pin
2's complement MSB-first data is input on this pin.

8 I LRCK L/R clock pin. 20 - AVSS Analog ground pin

Soft mute pin

9 I SMUTE When this pin goes "H", soft mute cycle is initiated 21 O VREF Voltage reference input pin
When returning "L", the output mute releases.
Double speed sampling mode pin (Internal pull-down pin)
10 I DFS 22 O AVDD Analog power supply pin.
"L":normal speed, "H":double speed
11 I DEM0 De-emphasis frequency select pin 23 O DZFR Rch zero input detect pin
12 I DEM1 De-emphasis frequency select pin 24 O DZFL Lch zero input detect pin
Note : Allinput pins except internal pull-down pins should not be left floating.

Samsung Electronics 2-1

Reference Information

2-1-2 RIC1 (KS1461 ; RF)

AGCLEVEL

RFAGCO

MROFST
VZOCTL

EQGND

RFEQO

EQVCC

RFRPN
BCATH
PLLGF

AGCC
AGCP

AGCB

MIRRI
RDPF

RFRP

RFCT
AGCI

EQIN
EQG

CB 1

CB 2
CP 1

CP 2
EQF

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

to RF EQ
TUNING BLOCK
AGC-HOLD(OOH) AGC_DET

75 BCAO
ACD 1
MUX BCA
BCD 2 BLOCK
CCD 3 74 BCAI
A
DCD 4 B
RF RF SLM RF
C
MUX & AGC Equalizer
ADVD 5 D
RFRP BCA
BDVD 6
CDVD 7
GAIN_EQ(02H)
DDVD 8
73 RESET
AUTO
RFCT OFSTCTL
CD1 S12 DVD1.2
& 72 OSC
CDRSEL(00H) TE1RES MIRR
DELAY_SEL(OOH) HOLD_CTL(O8H) CD1
PLLCTL DPDMUTE S12
TBAL(O1H) DPD_MUTE(O2H) DVD1
SEOFHOLD DVD2
FLT_CTL(OOH) LDONB
DPDEQ1
RREFBF 9 CAL_ENDB(O2H) FLT_CTL 71 STB
VREF CDRSEL
RREFEQ 10 D DELAY PD,LPF TESEL S/IF
GENERATOR 70 CLOCK
GCA EQ COM AGC-HOLD BLOCK
RREF 11 TBAL
D TEOPST(04H) GAIN_TE3 69 DATA
MUX3 ENV_SEL
PDLIMITRES
D TE1_LIMIT DVCTL_SEL
GCA EQ COM DPD_MUTE
D GAIN_EQ
GAIN_FE 68 RREFDLY
GAIN_ABCD
DPDEQ2 TE_OFST
FE_OFST
FAULTOUT DPD
ABCD_OFST 67 VREFDPD
DELAY_CD
BLOCK
EQ
VREFEQ 12 DELAY_AB
VC AMP GAIN_TE3(02H) PDLIMIT
66 DPDGND
ga_RFSUM
E 13 DELAY_SEL(00H) HOLD_CTL
TE38 PLLCTL ga_PLLDP
ga_PLLDN 65 TE1RES
F 14 GCA
OFSTHOLD 64 PLLCTL

TEOFST(04H) 63 DPDMUTE
TBAL(01H) to DPD
BLOCK 62 FAUL TOUT
CDRSEL(OOH)
GAIN_ABCD(OOH) 61 DPDEQ2
ADVD1 15
60 DPDEQ1
BDVD1 16
D1
CDVD1 17 B1 ABCD
C1 SUM EQIN 59 TE30FST
DDVD1 18
SUB A1 ENV_SEL(02H)
58 BCA
ACD1 19 RF
BCD1 20 MUX GAIN_FE(03H) OFSTHOLD 57 MIRR
MUX
CCD1 21 FE ABCD_OFST(O6H)
FE_0FST(05H) 56 DPDVCC
DCD1 22
OFSTHOLD

55 DFCT2
AVCC 23 CDRSEL(00H) MUX
54 DFCT1
ANALOG LDONB(00H) TESEL(OOH)
VREFA 24 VC AMP 53 DFCTTH1
ENVELOPE FOK DEFECT
ALPC
52 DFCTTH2
FOFST 25

FOFST
51 DVCC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OFSTHOLD

VREFLP_BGI

LDODVD
PDVD
LDOCD
PDCD

AGND

FE

FEN

TEN

TE

PDLIMITRES

ABCDN

ABCD

ABCDI

ENVP
ENVB
ENV

DGND

FOKTH

FOKB

DFCT_CP1

DFCT_CP2

CC1

CC2

2-2 Samsung Electronics

 PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION

1 ACD I CD optical main beam A AC coupling input port for RF 34 FEN I FE Input port for AMP GAIN setting 65 TE1RES I DPD TE PLL variable bias resistance 96 RDPF - Bias resistance connection port for RF EQ frequency setting

2 BCD I CD optical main beam B AC coupling input port for RF 35 TEN I Input port for TE AMP GAIN setting 66 DPDGND P Power GND input port for DPD TE 97 EQG I RF EQ boost gain control voltage input port

Samsung Electronics
3 CCD I CD optical main beam C AC coupling input port for RF 36 TE O TE AMP output port 67 VREFDPD O CAP connection port for DPD TE center 98 EQF I RF EQ peak frequency control voltage input port

I RF EQ boost, peak frequency gain control port corre-

4 DCD CD optical main beam D AC coupling input port for RF 37 PDLIMTRES - Bias resistance port for PDLIMIT 68 RREFDLY - Bias resistance connection port for delta block
99 PLLGF I sponding to wideband PLL (PLLG. PLLF resistance
5 ADVD I DVD optical main beam A AC coupling input port for RF 38 ABCDN I Input port for ABCD AMP GAIN setting 69 DATA I Data input port internal design)
RF EQ control port (When No. PLLG isn’t adjusted,
6 BDVD I DVD optical main beam B AC coupling input port for RF 100 VZOCTL I
39 ABCD O ABCD AMP output port 70 CLOCK I Clock input port apply DC CTL voltage.)

7 CDVD I DVD optical main beam C AC coupling input port for RF 40 ABCDI I ABCD AC coupling input port for SERVO monitor 71 STB I Data enable input port

8 DDVD I DVD optical main beam D AC coupling input port for RF Peak hold time constant setting RC 72 OSC OSC time constant input port for auto offset block
41 ENVP -
connection port for RF envelope detect
9 RREFBF - RF AMP I/O buffer bias resistance connection port 73 RESET I Reset input port for auto offset block (L : RESET)
Bottom hold time constant setting RC
42 ENVB -
10 RREFEQ - RF EQ bias resistance connection port connection port for RF envelope detect 74 BCAI I BCA FILTER1
43 ENV O RF envelope detect output port O
11 RREF - Analog block bias resistance connection port 75 BCAO BCA FILTER2
44 DGND P Power GND input port for digital circuit
12 VREFEQ O CAP connection port for RF EQ center voltage 76 RFCT O RF ripple center voltage output port for mirror
45 FOKTH I Focus OK comparing level input port Bottom hold time constant RC connection port for
13 E I CD optical sub beam E input port for SERVO 77 CB2 -
Focus OK comparator output port RFCT generation
14 F I CD optical sub beam F input port for SERVO 46 FOKB O Peak hold time constant RC connection port for
(L: FOCUS OK) 78 CP2 -
Peak hold time constant connection port SERVO RFCT generation
15 ADVD1 I DVD optical main beam A input port for SERVO 47 DFCT_CP1 -
defect max. time setting 79 RFRP O RF ripple AMP output port for mirror
16 BDVD1 I DVD optical main beam B input port for SERVO Peak hold time constant connection port PLL defect
48 DFCT_CP2 - 80 RFRPN I RF ripple AMP GAIN input port for mirror
I min. time setting
17 CDVD1 DVD optical main beam C input port for SERVO
49 CC1 O Output port of peak detector for defect 81 MROFST I RF ripple offset control port for mirror
18 DDVD1 I DVD optical main beam D input port for SERVO
Bottom hold time constant RC connection port for
50 CC2 I AC coupling input port for defect 82 CB1 -
19 ACD1 I CD optical main beam F input port for SERVO RFCT generation
51 DVCC P Power voltage input port for digital circuit Peak hold time constant RC connection port for
20 BCD1 I CD optical main beam F input port for SERVO 83 CP1 -
RFCT generation
Resistance connection port for PLL defect comparat-
21 CCD1 I CD optical main beam F input port for SERVO 52 DVCTTH2 -
ing level setting 84 MIRRI I Input port for MIRR signal generation
Resistance connection port for SERVO defect com-
22 DCD1 I CD optical main beam F input port for SERVO 53 DFCTTH1 - 85 EQVCC P Power voltage input port for RF EQ
parating level setting
23 AVCC P Power voltage input port for analog part 86 RFEQO O RF EQ output port
54 DFCT1 O Defect output port for SERVO
CAP connection port for analog part
24 VREFA -/O 55 DFCT2 O Defect output port for PLL 87 BCATH I BCA comparating level control port
center voltage, Use at other block
25 FOFST O CAP connection port for focus auto offset (OPEN) 56 DPDVCC P Power voltage input port for DPD TE 88 EQIN I RFAGCO input port for RF EQ

ON/OFF connection port for auto offset block (L : 57 MIRR O Mirror output port 89 RFAGCO O RF AGC AMP output port
26 OFSTHOLD I
auto offset adjustment H : serial offset adjustment)
58 BCA O BCA output port 90 AGCC - AGC time constant CAP connection port
27 VREFLP_BGI I BANDGAP voltage input port for ALPC
59 TE3OFST - Resistance connection port for 3BTE offset 91 AGCI I When AGC is “HOLD”, AGC voltage input port
28 LDODVD O DVD optical laser diode driving voltage output port
60 DPDEQ1 O DPD EQ (A+C) output port 92 EQGND P Power GND input port for RF EQ
29 PDDVD I DVD optical laser monitor diode voltage input port
61 DPDEQ2 O DPD EQ (B+D) output port 93 AGCLEVEL I AGC level control voltage input port
30 LDOCD O CD optical laser diode driving voltage output port
62 FAULTOUT O DPD defect waveform output port (MONITOR) -
94 AGCB RF bottom hold time constant RC connection port for RF AGC
31 PDCD I CD optical laser monitor diode voltage input port
63 DPDMUTE I DPD TE MUTE control port (H : MUTE) 95 AGCP - RF peak hold time constant RC connection port for RF AGC
32 AGND P Power GND port for analog part

O 64 PLLCTL I DPD TE PLL variable input port

33 FE FE AMP output port

2-3
Reference Information
2-4
TILTI
TILTO
RSTB
TEST
XI
XO
XOUT
PHI1
TZCA
MIRR
FOKB
DFCT
LOCK
SMON
/PSO
SSTOP
PS1
DIRC
Reference Information

FLKB
VREF TIMING I/O INTERFACE TLKB
ENV GENERATOR BLOCK
LDONB
TZCO
A/D
2-1-3 SIC1 (KS1452 ; Digital Servo)

SME CONVERTER
SQCK
BLOCK SUB CODE
TE SQSI
READ BLOCK
FE SCOR
DAB
CSB

TRACK MWRB
COUT
COUNTER SYSCON MRDB
DSP CORE INTERFACE MDATA[7:0]
FOR BLOCK
FOD SENSE
DIGITAL SERVO
TRD PSB

SLD MDOUT[3:0]
D/A
SPD PLLLOCK
CONVERTER RFD
FBAL BLOCK RPD
TBAL
EFMRTD
DVCTL
PLCK

ROM WIDE RVCO

EFMI
CAPTURE VCTRL
RFI
EFM RANGE PLL EQCTL
ASYDVD ASYMETRY MAGICO

ASYCD FDCTL
EFM INTO_224
PLLHD
EFMOA

Samsung Electronics
 PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION PIN NAME I/O FUNCTION

1 MDOUT3 O Mode data3 out controlled by micom 34 FOKB I Focus OK signal input pin 65 FE I Focus error signal input pin 73 SLD O Sled motor drive signal output pin

2 SSTOP/PSO I Limit switch/sled position sensor input pin0 35 FDCTL I PLL frequency detect control input pin 66 ENV I RF envelope input pin 74 SPD O Spindle motor drive signal output pin

Samsung Electronics
3 PS1 I Sled motor position sensor input pin 1 36 LDONB O Laser diode ON signal output pin 67 TILTI I Tilt in (reserved) 75 FOD O Focus actuator drive signal output pin

4 TEST I Test pin (L : normal H : test) 37 DFCT I Defect Detection signal input pin 68 AVDD P Analog block VDD power supply pin 76 TRD O Tracking actuator drive signal output pin

5 COUT O Counter clock 38 MIRR I Mirror signal input pin 69 TILTO O Tilt out (reserved) 77 TZCA I TE signal for tracking zero cross input pin

6 FLKB O Focus servo lock signal output pin 39 PLLHD I PLL hold signal from micom 70 DVCTL O Depth variation control signal output pin 78 MDOUT0 O Mode data 0 out controlled by micom

7 TLKB O Tracking servo lock signal output pin 40 INTO_224 O Servo interrupt monitor pin 71 TBAL O Tracking balance signal output pin 79 MDOUT1 O Mode data 1 out controlled by micom

8 PSB I 0 : 1BIT 1 : 8BIT 41 PVDD P PLL logic block VDD power supply pin 72 FBAL O Focus balance signal output pin 80 MDOUT2 O Mode data 2 out controlled by micom

9 RSTB I System reset signal input pin 42 PLCK O PLCK

10 CSB I Micom chip select pin Frequency lock detect output

43 PLLLOCK O
11 DAB I Micom data/address select pin (H : Lock L : Unlock)

12 MWRB I Micom write clock signal input pin 44 EFMRTD O Latched EFM output signal

13 MRDB I Micom read clock signal input pin 45 PVSS P PLL logic block VSS power supply pin

14 MDATA0 I/O Micom data pin 0 46 RVCO I Resistor pin for VCO GAIN

15 MDATA1 I/O Micom data pin 1 47 RFD I Gain adjust resister for frequence detector

16 MDATA2 I/O Micom data pin 2 48 RPD I Gain adjust resister for phase detector

17 MDATA3 I/O Micom data pin 3 49 VCTL I Control voltage for VCO

18 MDATA4 I/O Micom data pin 4

50 MAGICO I Input for hysteresis control of FD output (for test)
19 MDATA5 I/O Micom data pin 5

20 MDATA6 I/O Micom data pin 6 51 EFMOA I EFM offset adjustment pin

21 MDATA7 I/O Micom data pin 7 52 TZCO O Tracking zero cross output pin

22 SENSE O Internal status monitor pin 53 SVDD P Servo CPU VDD power supply pin

23 DVDD P Servo logic & ROM VDD power supply pin 54 EQCTL O EQ control signal

24 XI I System clock signal input pin 55 EFMI I EFM signal for test

25 XO O System clock signal output pin 56 EFMO O EFM signal

26 XOUT O Clock out (33.9688MHz) to DSP 57 LPFDVD I Asymmetric input signal for DVD

27 DVSS P Servo logic & ROM VSS power supply pin 58 LPFCD I Asymmetric input signal for CD

28 SQCK O Clock output pin for subcode data read 59 RFI I RF input signal

29 SQSI I Subcode data input pin 60 SVSS P Servo CPU VSS power supply pin

30 SCOR I Timing detection input pin for subcode data read 61 AVSS P Analog block VSS power supply pin

31 SMON I Motor ON signal input pin 62 SME I Spindle error input pin

32 LOCK I Lock signal input pin 63 VREF I Reference voltage input pin

33 DIRC I Direct jump control (for 1 track jump) 64 TE I Tracking error signal input pin

2-5
Reference Information
2-6
TO MICOM (15)
TO D-EQ (8) MDAT(7:0), MRZA, ZCS, MWR,
Reference Information

PWMO(7:0) MRD, ZIRQZD, ZWAIT, ZRST

FROM R/F,
PLL(3) 32BIT SR 16-8 DEMOD DESCRAMBLER
MICOM I/F
EFMI
PLCK
BCARZ

ECSY (6, 4, 3)
FRAME SYNC EDC
efmwr ID ECC
DET/PROT/INS
(17.57KHz)
TO DRAM
2-1-4 DIC1 (KS1453 ; DVD Data Processor)

256K*16
TO (12) 26.16MHz
(6, 4, 3) (32)
XTI1 (208, 192, 17)
trans ID ECC DD(15:0)
XTO1 (182, 172, 11)
VCO TIMING DADR(8:0)
CK33MI X'TAL & ECC
GENERATOR ZRAS
CK33MO TIMING GEN
ZUCAS
17.58KHz = 26.16M/1488 676.08Hz
ZLCAS
FG M ZOE(1:0)
RFCK 17.58/7.35KHz 75Hz
MON 7.35KHz = 4.3218M/588 DEINTERLEAVE
ZWE(1:0)
MDP &
DVD CLV/CAV VCO TIMING (32, 28, 5) RAM CONTROL
MDS
GENERATOR (28, 24, 5)
FSW
PLL_LOCK CIRC
M WFCK 17.58/7.35KHz TO AV (13)
CLV_LOCK
SERVO_LOCK SDATA[0] / CDATA
CD CLV/CAV DVDP, SDATA[1] / LRCK
FRAME SYNC SQ-VCD SDATA[2] / BCLK
DET/PROT/INS SDATA[3] / C2PO
(7.35KHz) EFM DEMOD SDATA[4] / SQDT
V-CD, CD-DA
SDATA[5] / WFSY
M M SDATA[6] / SOS1
SDATA[7] / SQCK
DATREQ
CD-G CSTROBE
23BIT SR SUBCODE I/F
DTER
DATACK
TOS

Monitor(8) GFS, FRSYZ, TX, EFMO, WFCK, RFCK, CK 16M, DEMPHA Power(34)=VDD(11)+GND(23) Test Pin(3) TEST0, TEST1, TEST2

Samsung Electronics
 PIN NAME FUNCTION PIN NAME FUNCTION PIN NAME FUNCTION PIN NAME FUNCTION

1 DVSS Digital GND (0V) 33 DD6_BI DRAM data bus 66 SDATA6_OUT DVD data/Sub code block sink (S0S1) 98 TEST0_IN Test mode setting port

2 ZCS_IN Chip select (Active Low) 34 DD8_BI DRAM data bus 67 SDATA7_BI DVD data/Sub code serial clock (SQCK) 99 TEST1_IN Test mode setting port

Samsung Electronics
Micom register select 35 DD7_BI DRAM data bus 68 DVSS Digital GND (0V) 100 TEST2_IN Test mode setting port
3 MRZA_IN
(L -> Register H -> Data) 36 DVSS Digital GND (0V) 69 CSTROBE_OUT Data strobe (clock) output 101 EFMO_OUT EFM out

4 DVSS Digital GND (0V) 37 ZLCAS_OUT DRAM row column address strobe 102 WFCK_OUT Write frame pulse
70 DATREQ_IN Data request from A/V decoder or ROM decoder
5 MDAT7_BI Micom data bus 38 ZUCAS_OUT DRAM upper column address strobe 103 RFCK_OUT Reference frame pulse
71 DTER_OUT DVD data error output
6 MDAT6_BI Micom data bus 39 ZWE1_OUT DRAM write enable 1 (8M ONLY) 104 PLCK_IN Phase locked clock
72 DVSS Digital GND (0V)
7 MDAT5_BI Micom data bus 40 ZWE0_OUT DRAM write enable 0 (4M, 8M, 16M) 105 DVSS Digital GND (0V)
73 PWM07_OUT PWM output signal
8 MDAT4_BI Micom data bus 41 ZOE1_OUT DRAM output enable 1 (16M, --------, 16M) 106 PLLLOCK_OUT Lock signal for PLL
74 PWM06_OUT PWM output signal
9 MDAT3_BI Micom data bus 42 DVDD Digital power (+5V) 107 CLVLOCK_OUT Lock signal for CLV
75 PWM05_OUT PWM output signal
10 MDAT2_BI Micom data bus 43 ZOEO_OUT DRAM output enable 0 108 SERLOCK_OUT Lock signal for SERVO
76 PWM04_OUT PWM output signal
11 MDAT1_BI Micom data bus 44 ZRAS_OUT DRAM row address strobe Spindle motor phase control signal
109 MDP_OUT
77 DVDD Digital power (+5V) (3-state)
12 MDAT0_BI Micom data bus 45 DADR8_OUT DRAM address bus
78 PWM03_OUT PWM output signal Spindle motor speed control signal
13 DVDD Digital power (+5V) 110 MDS_OUT
46 DADR7_OUT DRAM address bus (3-state)
79 PWM02_OUT PWM output signal
14 XTI_IN System clock input for 26.16 MHz 47 DVSS Digital GND (0V) 111 DVSS Digital GND (0V)
80 PWM01_OUT PWM output signal
15 XTO_OUT System clock output for 26.16 MHz 48 DADR0_OUT DRAM address bus 112 DVSS Digital GND (0V)
81 PWM00_OUT PWM output signal
16 DVSS Digital GND (0V) 49 DADR6_OUT DRAM address bus 113 MON_OUT Spindle motor ON/OFF control output
82 DVSS Digital GND (0V)
17 DD15_BI DRAM data bus 50 DADR1_OUT DRAM address bus 114 FG_IN Reference signal for CAV
83 DVSS Digital GND (0V)
18 DD0_BI DRAM data bus 51 DADR5_OUT DRAM address bus Spindle motor output filter conversion output (3-
84 DVSS Digital GND (0V) 115 FSW_OUT
19 DD14_BI DRAM data bus 52 DADR2_OUT DRAM address bus state)
85 DVDD Digital power (+5V)
20 DD1_BI DRAM data bus 53 DADR4_OUT DRAM address bus 116 EFMI_IN EFM/EFM+ signal input
86 DVDD Digital power (+5V)
21 DVSS Digital GND (0V) 54 DADR3_OUT DRAM address bus 117 DVDD Digital power (+5V)
87 DVSS Digital GND (0V)
22 DD13_BI DRAM data bus 55 DVSS Digital GND (0V) 118 DVDD Digital power (+5V)
88 DVSS Digital GND (0V)
23 DD2_BI DRAM data bus 56 DVSS Digital GND (0V) 119 DVDD Digital power (+5V)
89 DVSS Digital GND (0V)
24 DD12_BI DRAM data bus 57 TOS_OUT Top of sector 120 CK16M_OUT 2∫–¡÷ clock of CK33M/16.934MHz
90 DVSS Digital GND (0V)
25 DD3_BI DRAM data bus 58 DATACK_OUT Data acknowledge signal output 121 DEMPHA_OUT When DEEMPHASIS is ON, “HIGH”.
91 FRSYZ_OUT Frame sync out
26 DVDD Digital power (+5V) 59 DVDD Digital power (+5V) 122 BCARZ_IN BCA input signal
92 TX_OUT Digital out
27 DD11_BI DRAM data bus 60 SDATA0_OUT DVD data/CD data bitstream output 123 DVSS Digital GND (0V)
Good frame sync detection result output (“H”
93 GFS_OUT
28 DD4_BI DRAM data bus 61 SDATA1_OUT DVD data/CD data L/R clock (LRCK) active) 124 ZRST_IN Hardware reset active low

29 DD10_BI DRAM data bus 62 SDATA2_OUT DVD data/CD data bit clock (BLCK) 94 DVSS Digital GND (0V) 125 ZWAIT_OUT Micom read/write access wait (“L” wait)

30 DD5_BI DRAM data bus 63 SDATA3_OUT DVD data/CD data error flag (C2P0) 95 CK33MI_IN System clock input for 33.8688MHz 126 ZIRQZD_OUT Interrupt request from micom

31 DVSS Digital GND (0V) 64 SDATA4_OUT DVD data/Sub code serial data (SQDT) 96 CK33MO_OUT System clock output for 33.8688MHz 127 MRD_IN Micom read strobe (schmidt trigger)

32 DD9_BI DRAM data bus 65 SDATA5_OUT DVD data/Sub code frame sink (WFSY) 97 DVSS Digital GND (+5V) 128 MWR_IN Micom write strobe (schmidt trigger)

2-7
Reference Information
Reference Information

2-1-5 DIC2 (KM416C254BJ-6 ; CMOS DRAM)

BLOCK DIAGRAM
RAS
UCAS Control Vcc
LCAS Clocks Vss
VBB Generator
W

Lower
Refresh Timer Row Decoder
Data in
DQ0
Buffer
to
Refresh Control Lower DQ7

Data out
Memory Array Buffer
Refresh Counter 262,144 x 16
Upper OE
Cells
Data in
DQ8
Buffer
Row Address Buffer to
AO
. Upper DQ15
.
Data out
A8 Col. Address Buffer Column Decoder
Buffer

NAME FUNCTION
A0-A8 Address Inputs

DQ0-15 Data in/Out

VSS Ground

RAS Row Address Strobe

UCAS Upper Column Address Strobe

LCAS Lower Column Address Strobe
W Read/Write Input

OE Data Output Enable

Power (+5V)
V CC
Power (+3.3V)

N.C No Connection

2-8 Samsung Electronics

 Reference Information

2-1-6 VIC1 (ZiVA-3 ; Audio/Video Decoder)

BLOCK DIAGRAM
ZiVA-3 Decoder
OSD
Decoder

SDRAM/
EDO/ROM Memory
Interface Controller
Subpicture Video Video
Decoder Mixer Interface

Host Host MPEG

Interface Interface Video
Control Logic Decoder

Secure View CD-DA and

CSS LPCM
Descrambling Program Decoder
DVD/CD
Stream
Interface
Bus Key Decoder
Dolby Digital Digital
Authentication Audio Audio
Audio Audio Interface
(Optional) DSP
Decoder Interface

Scrambled, Compressed Content

MPEG
Descrambled, Compressed Content Audio
Decoder
Decompressed Content

Display Content

LOGIC DIAGRAM

CS DA-DATA[0:3]

DTACKSEL DA-LRCK Audio

HADDR[2:0] DA-BCK Interface
Host RD DA-XCK Signals
Interface HDATA[7:0] DA-IEC

Signals WAIT/DTACK

INT EDO-CAS

HOST8SEL EDO-RAS
R/W LDQM

Video VDATA[7:0] MDATA[15:0]

Interface HSYNC MADDR[20:0] SDRAM/EDO

Signals VSYNC MWE Interface
VCLK ROM-CS Signals
SD-CAS
DVD-DATA0/CD-DATA
SD-RAS
DVD-DATA1/CD-LRCK
SD-CLK
DVD-DATA2/CD-BCK
SD-CAS[1:0]
DVD-DATA3/CD-C2PO
UDQM
DVD-DATA4/CDG-SDATA
DVD/CD
DVD-DATA5/CDG-VFSY
Interface
DVD-DATA6/CDG-SOS1 SYSCLK
Signals
DVD-DATA7/CDG-SCLK VDD

VSS
Global
VREQUEST

A_VSS
Interface
VSTROBE

A_VDD
Signals
ERROR

V-DACK/ASTROBE P10[10:0]

AREQUEST RESET
A-DACK
ZiVA Decoder

Samsung Electronics 2-9

Reference Information

2-1-7 VIC50 (SAA7128 ; Digital Video Encoder)

BLOCK DIAGRAM

TTXRQ
RESN

XTALI

VDDA
RCV1

RCV2

XCLK
XTAL

LLC1
SDA

SCL

4
35

34

43

37

25,28,31,36
42

41
40

8
20
VDD I2C I2 C- SYNC/
21 INTERFACE CLOCK
SA

I2 C-Control I2 C-Control Clock&Timing

I2 C-Control

9..16 Y Y 30 CVBS
MP D (CSYNC)
MP(7:0) OUTPUT-
FADER CbCr ENCODER C INTERFACE 27 VBS
MP
(CVBS)
A
24 C
(CVBS)

44 I2 C-Control
TTX 22,32,33 VSSA
I2 C-Control

Y 23
R(Cr)
D
RGB-
CbCr PROCESSOR 26 G(Y)
A
6,17,39
5,18,38

29 B(Cb)
19
2

RTC1
VDD
VSS

AP
SP

PIN I/O NAME FUNCTION

1 res. Reserved pin, do not connect

2 I SP Test Pin;connected to digital ground for normal operation

3 I AP Test Pin;connected to digital ground for normal operation

4 I LLC1 Line-Locked Clock input;this is the 27 MHz master clock

5 I V SS1 Digital supply ground 1

6 I V DD1 Digital supply 1

7 I/O RCV1 Raster Contral 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.

8 I/O RCV2 Raster Contral 2 for video port. This pin provides an HS pulse of programmable length or receives
an HS pulse.

2-10 Samsung Electronics

 Reference Information

PIN I/O NAME FUNCTION

9 I MP7

10 I MP6

11 I MP5
Double speed 54 MHzMPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data.
12 I MP4 Data are sampled on the rising and falling clock edge;data sampled on the risting edge then are sent to
13 I MP3 the encoding part of the device, data sampled on the falling edge are sent to the RGB part of the device.
(or vice verse, depending on programming)
14 I MP2

15 I MP1

16 I MP0

17 I V DD2 Digital supply voltage 2

18 I V SS2 Digital ground 2

Real Time Control input. If the LLC1 clock is provided by an SAA7111 or SAA7151B, RTCI should be
19 I RTCI
connected to the RTCO pin of the respective decoder to improve the signal quality.

20 I VDD 12C Sense input for 12C bus voltage;connect to 12C bus supply

21 I SA Select 12C address; low selects slave address 88h, high selects slave address 8Ch.

22 I V SSA1 Analog ground 1 for Red (Cr), C(CVBS), Green(Y) outputs

23 O R(Cr) Analog output of Red (Cr)signal

24 O C Analog output of Chrominance (CVBS) signal

25 I V DDA1 Analog supply voltage 1 for R(Cr), C(CVBS) outputs

26 O G(Y) Analog output of Green(Y) signal

27 O VBS Analog output of VBS (CVBS) signal

28 I V DDA2 Analog supply voltage 2 for VBS(CVBS), Green(Y) outputs

29 O B(Cb) Analog output of Blue(Cb) signal

30 O CVBS Analog output of CVBS(CSYNC) signal

31 I V DDA3 Analog supply voltage 3 for Blue(Cb)and CVBS(CSYNC), outputs

32 I V SSA2 Analog ground 2 for VBS (CVBS), Blue(Cb), CVBS(CSYNC)outputs

33 I V SSA3 Analog ground 3 for the DAC reference ladder and the oscillator

34 O XTAL Crystal oscillator output

35 I XTAL1 Crystal oscillator input; if the oscillator is not used, this pin should be connected to ground.

36 I V DDA4 Analog supply voltage 4 for the DAC reference ladder and the oscillator

37 O XCLK Clock output of the crystal oscillator

38 I V SS3 Digital supply ground 3

39 I V DD3 Digital supply 3

Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL-
40 I RESN Blackburst on CVBS, VBS and C;RGB outputs set to lowest voltage.
The 12C-bus receiver waits for the START condition.

41 I SCL 12C serial clock input

42 I/O SDA 12C serial data input/output
43 O TTXRQ Teletext Request output, indicating when text bits are requested

44 I TTX Teletext bit stream input

Samsung Electronics 2-11

Reference Information

2-1-8 MIC1 (TMP93CM41F ; Main Micom)

PAO~PA6
PORT A
PA7(SCOUT) VCC[3]
900L-CPU VSS[3]

P50 to P57 XWA W A

(ANO to AN7) XBC B C High
10-BIT 8CH Frequency
X1
AVCC ADE D E
X2
A/D XHL H L OSC
AVSS
CONVERTER XIX IX
VREFH IY
XIY
VREFL XIZ IZ CLK
XSP SP
32bit
(TXD0)P90 Low
SERIAL I/O Frequency
XT1
(RXD0)P91 SR F
XT2
(CH,0) OSC
(SCLK0/CTS0)P92 P C AM8/16
EA
(TXD1)P93 SERIAL I/O RESET
(RXD1)P94 (CH,1) ALE
(SCLK1)P95 TEST2,1
INTERRUPT
CONTROLLER
NMI
(PG 00)P60
PATTERN
(PG 01)P61
GENERATOR
(PG 02)P62
(CH,0)
(PG 03)P63 WATCH-DOG WDTOUT
(PG 10)P64 PATTERN TIMER
(PG 11)P65 GENERATOR
(PG 12)P66 (CH,1)
2KB RAM
(PG 13)P67 PORT 0 P00 to P07
(AD0 to AC7)
8BIT TIMER
(T10)P70 PORT 1 P10 to P17
(TIMER 0)
(AD8 to AD15/A8 toA15
8BIT TIMER
(T01)P71 (TIMER 1) PORT 2 P20 to P27
(A0 to A7/A16 to A23)
8BIT PWM
(T02)P72
(TIMER 2)
P30(RD)
8BIT PWM P31(WR)
(T03)P73 (TIMER 3) P32(HWR)
PORT 3
P33(WAIT)
P34(BUSRQ)
(INT4/T14)P80 P35(BUSAK)
(INT5/T15)P81 16BIT TIMER
P36(R/W)
(T04)P82 (TIMER 4)
P37(RAS)
(T05)P83

16BIT TIMER
(INT6/T16)P84 CS/WAIT P40(CS0/CAS0)
(TIMER 5)
(INT7/T17)P85 CONTROLLER P41(CS1/CAS1)
(T06)P86 (3-BLOCK) P42(CX2/CAS2)

(INTO)P87

2-12 Samsung Electronics

 PORT ASSIGNED PORT ASSIGNED PORT ASSIGNED PORT ASSIGNED
No I/O FUNCTION No I/O FUNCTION No I/O FUNCTION No I/O FUNCTION
NAME NAME NAME NAME NAME NAME NAME NAME
1 VREFL GND I A/D Ref input (L) 31 P96 XT1 O - 61 /WDTOUT WDTOUT O Watch dog timer output Chip slect 2
82 /CS2 /CS2 O
2 AVss AGND - A/D GND input 32 P97 XT2 O - 62 VSS GND - (EPROM, 4M Bit, 512KB)

Samsung Electronics
3 AVcc AVCC - A/D VCC input 33 TEST1 TEST1 - Test pin. connect to TEST2 63 Vcc VCC - 83 P60 - I/O

4 /NMI - I Non-maskable interrupt 34 TEST2 TEST2 - Test pin. connect to TEST1 64 A16 HA16 O Address 16 84 P61 TRAY-IN O Tray in control output

5 P70 ZRST O DSP H/W reset 35 PA0 ECK O EEPROM CLOCK 65 A17 HA17 O Address 17 (AV-DECODER) 85 P62 TRAY-OUT O Tray out control output

6 P71 MCK_SEL O Master clock select 36 PA1 EDT I/O EEPROM DATA I/O 66 A18 HA18 O Address 18 (Data processor) 86 P63 SCL O IIC clock (VIDEO ENCODER)

7 P72 ZIVA_RST O AV-DEC H/W reset 37 PA2 EWC O EEPROM WRITE PROTECT 67 A19 HA19 O Address 19 87 P64 SDA I/O IIC clock (VIDEO ENCODER)

8 P73 LED O Open/close blinking 38 PA3 - O 68 A20 HA20 O Address 20 (D. SERVO) 88 P65 DAB O D.Servo IC data/Address select

9 /INT4 DVDINT I Interrupt from AV-DEC 39 PA4 - O 69 A21 HA21 O Address 21 89 P66 CSB O D.Servo IC chip select

10 INT5 SRQ I Interrupt from front micom 40 PA5 - O 70 A22 HA22 O Address 22 90 P67 RSTB O D.Servo IC reset

11 P82 OPEN I Open switch 41 PA6 - O 71 A23 HA23 O Address 23 91 Vss GND -

12 P83 CLOSE I Close switch 42 PA7 - O 72 /RD /RD O /Read strobe 92 P50 SLOCK LOCK monitor from DSP

13 /INT6 FGINT I Interrupt from spindle motor FG 43 ALE ALE O Address latch enable 73 /WR /WR O /Write strobe 93 P51 TILTO I Monitor signal

14 INT7 - I 44 Vcc VCC - 74 P32 - I/O 94 P52 FR I Spindle direction from SP driver

15 P86 RRQ O Request to front micom 45 AD0 HAD0 I/O Address/Data 0 75 /WAIT /MWAIT I /Wait 95 P53 SENSE I SENSE monitor from SERVO

16 INTO ZINT I Interrupt from DSP 46 AD1 HAD1 I/O Address/Data 1 76 P34 RCODE I/O 96 P54 FOKB I Focus lock monitor from RF

17 TXDO RXD O Serial data output 47 AD2 HAD2 I/O Address/Data 2 77 P35 - I/O 97 P55 RFRP1 I Tracking lock monitor from SERVO

18 RXDO TXD I Serial data input 48 AD3 HAD3 I/O Address/Data 3 78 P36 - O 98 P56 RFO I RF sum signal

19 SCLKO SCLK I Serial data clock 49 AD4 HAD4 I/O Address/Data 4 79 P37 - I/O 99 P57 VREFO I

20 TXD1 MD O RF control data 50 AD5 HAD5 I/O Address/Data 5 80 P40/CS0 - O 100 VREFH AVCC I A/D Ref input (H)

21 094 STB I/O RF data latch 51 AD6 HAD6 I/O Address/Data 6 Chip select 1
81 /CS1 /CS1 -
22 SCLK1 MC O RF control clock 52 AD7 HAD7 I/O Address/Data 7 (SRAM, 1M Bit, 128KB)

23 AM8/16 AM8 I Address mode (H: 8 bit mode) 53 A8 HA8 O Address 8

24 CLK CLK O Clock output (System clock÷2) 54 A9 HA9 O Address 9

25 Vcc VCC - 55 A10 HA10 O Address 10

26 Vss GND - GND 56 A11 HA11 O Address 11

27 X1 X1 I High frequency OSC in 57 A12 HA12 O Address 12

28 X2 X2 O High frequency OSC out 58 A13 HA13 O Address 13

29 /EA /EA I External access CS41/CS40 59 A14 HA14 O Address 14

30 /RESET /MRST I Master reset from FRONT 60 A15 HA15 O Address 15

2-13
Reference Information
Reference Information

2-1-9 MIC8 (M27C801 ; 8MB (1M x 8-bit) CMOS EPROM)

BLOCK DIAGRAM
Data Outputs
DQ0-DQ7

Vcc
Vss

OE/VPP
Output Enable
CE Chip Enable and Output Buffers
Prog Logic

. Y
Y
. Gating
Decoder

A0-A19
Address .
Inputs X . 2,097,152-Bit
Decoder . Cell Matrix
.
.

TOP VIEW

A19 1 32 Vcc
A16 2 31 A18
NAME FUNCTION
A15 3 30 A17
A0-A19 Address Inputs
A12 4 29 A14
A7 5 28 A13 CE Chip Enable Input
A6 6 27 A8 DQ0-DQ7 Data Input/Outputs
A5 7 26 A9
OE Output Enable Input
A4 8 25 A11
A3 9 24 OE/VPP Vcc Vcc Syply Voltage

A2 10 23 A10 Vss Ground

A1 11 22 CE
A0 12 21 DQ7
DQ0 13 20 DQ6
DQ1 14 19 DQ4
DQ2 15 18 DQ4

Vss 16 17 DQ3

2-14 Samsung Electronics

 PORT ASSIGNED PORT ASSIGNED PORT ASSIGNED PORT ASSIGNED
No I/O FUNCTION No I/O FUNCTION No I/O FUNCTION No I/O FUNCTION
NAME NAME NAME NAME NAME NAME NAME NAME
1 P52 MRST O Front end reset 31 S0/T0 GRID8 O FLT GRID CONTROL 61 S28 SEG4 O FLT SEGMENT CONTROL 81 P30 S1 I SHUTTLE DATA

Samsung Electronics
2 PWM1 - - 32 S1/T1 GRID7 O FLT GRID CONTROL 62 S29 SEG3 O FLT SEGMENT CONTROL 82 P31 S2 I SHUTTLE DATA

3 P20 DFS O D/A Control 33 S2/T2 GRID6 O FLT GRID CONTROL 63 S30 SEG2 O FLT SEGMENT CONTROL 83 P32 S3 I SHUTTLE DATA

4 P21 DEMO0 O D/A Control 34 S3/T3 GRID5 O FLT GRID CONTROL 64 S31 SEG1 O FLT SEGMENT CONTROL 84 P33 S4 I SHUTTLE DATA

5 P22 DEMO1 O D/A Control 35 S4/T4 GRID4 O FLT GRID CONTROL 65 P00 KEY0 I KEY SCAN 85 P34 J1 I JOG DATA

6 P23 DARST O D/A Control 36 S5/T5 GRID3 O FLT GRID CONTROL 66 P01 KEY1 I KEY SCAN 86 P35 J2 I JOG DATA

7 P24 DIF0 O D/A Control 37 S6/T6 GRID2 O FLT GRID CONTROL 67 P02 KEY2 I KEY SCAN 87 P36 AT I TV TYPE

8 P25 DIF1 O D/A Control 38 S7/T7 GRID1 O FLT GRID CONTROL 68 P03 GND I 88 P37 AD I TV TYPE

9 P26 DIF2 O D/A Control 39 S8/T8 - O 69 P04 - O 89 VSS +5 V -

2-1-10 FIC2 (LC866232 ; Front Micom)

10 P27 DARST1 O D/A Control 40 S9/T9 - O 70 P05 - O 90 VDD GND -

11 TEST1 - - 41 S10/T10 - O 71 P06 - O 91 P40 RGBCTL O SCART CONTROL

12 *RES I Reset 42 S11/T11 SEG21 O FLT SEGMENT CONTROL 72 P07 SRQ O Request to MAIN Micom 92 P41 SCON_B O SCART CONTROL

13 XT1 GND Low frequency OSC in 43 S12/T12 SEG20 O FLT SEGMENT CONTROL 73 P10/S00 TXD O SERIAL DATA OUT 93 P42 - O

14 XT2 - Low frequency OSC out 44 S13/T13 SEG19 O FLT SEGMENT CONTROL 74 P11/S10 RXD I SERIAL DATA IN 94 P43 WIDE O SCART CONTROL

15 VSS GND 45 S14/T14 SEG18 O FLT SEGMENT CONTROL 75 P12/SCK0 SCLK O SERIAL CLOCK 95 P44 AMUTE3 O SUB WOOPER MUTE

16 CF1 - High frequency OSC in 46 S15/T15 SEG17 O FLT SEGMENT CONTROL 76 P13/S01 - 96 P45 AMUTE2 O CENTER MUTE

17 CF2 - High frequency OSC out 47 VDD +5V - 77 P14/S11 - 97 P46 AMUTE1 O REAR MUTE

18 VDD VDD 48 VP -28V - 78 P15/SCK1 - 98 P47 AMUTE0 O FRONT MUTE

19 AN0/P80 ECHO_VR I ECHO volume A/D input 49 S16 SEG16 O FLT SEGMENT CONTROL 79 P16/BUZ - 99 P50 LED O STANDBY LED

20 AN1/P81 MIC_DET I MIC detect 50 S17 SEG15 O FLT SEGMENT CONTROL 80 P17/PWMO 100 P51 ON/OFF O POWER ON/OFF CONTROL

21 AN2/P82 - I 51 S18 SEG14 O FLT SEGMENT CONTROL

22 AN3/P83 MODE0 I HARDWARE MODE SELECT 52 S19 SEG13 O FLT SEGMENT CONTROL

23 AN4/P84 MODE1 I HARDWARE MODE SELECT 53 S20 SEG12 O FLT SEGMENT CONTROL

24 AN5/P85 MODE2 I HARDWARE MODE SELECT 54 S21 SEG11 O FLT SEGMENT CONTROL

25 AN6/P86 MODE3 I HARDWARE MODE SELECT 55 S22 SEG10 O FLT SEGMENT CONTROL

26 AN7/P87 MODE4 I HARDWARE MODE SELECT 56 S23 SEG9 O FLT SEGMENT CONTROL

27 P70/INT0 RRQ I Request to front micom 57 S24 SEG8 O FLT SEGMENT CONTROL

28 P71/INT1 - I 58 S25 SEG7 O FLT SEGMENT CONTROL

29 P72/INT2 - I 59 S26 SEG6 O FLT SEGMENT CONTROL

30 P73/INT3 REMOCON I REMOCON data in 60 S27 SEG5 O FLT SEGMENT CONTROL

2-15
Reference Information
12. Wiring Diagram

MAIN PCB

JACK PCB

(DVD-909)
<PIN1 ~ 12>

<PIN1 ~ 6>
(DVD-709)

DVD-909
PHONE/POWER PCB

DVD-709
(DVD-909 ONLY) (DVD-909)
<PIN1 ~ 12>

PLAY PCB

<PIN1 ~ 6>
(DVD-709)
DECK PCB
POWER PCB
(DVD-709 ONLY)

Samsung Electronics 12-1

13. Schematic Diagrams

Block Identification of PCB

13-1 S.M.P.S. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-2

13-2 Main Power Supply - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-3

13-3 Main Micom - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-4

13-4 Servo - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-5

13-5 Video - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-6

13-6 Audio- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-7

13-7 5.1 Channel Audio (DVD-909 Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-8

Main PCB (Component Side)
13-8 RF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-9

13-9 ZiVA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-10

13-10 DSP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-11

13-11 Front Micom/VFD Display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-12

13-12 Component (DVD-909 Only ; Option) - - - - - - - - - - - - - - - - - - - - - - - - - - 13-13

13-13 Scart Jack (DVD-909 PAL Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-14

13-14 Mute - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-15

13-15 Play & Phone/Power (DVD-909 Only) - - - - - - - - - - - - - - - - - - - - - - - - - - 13-16

13-16 Play & Power (DVD-709 Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-16

13-17 Deck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-17

13-18 Remote Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-18

Jack PCB (Conductor Side)

Samsung Electronics 13-1

Schematic Diagrams

13-1 S.M.P.S.

13-2 Samsung Electronics

 Schematic Diagrams

13-2 Main Power Supply

Samsung Electronics 13-3

Schematic Diagrams

13-3 Main Micom

13-4 Samsung Electronics

 Schematic Diagrams

13-4 Servo

Samsung Electronics 13-5

Schematic Diagrams

13-5 Video

(DVD-909 OPTION)

(DVD-909 OPTION)

Y Output C Output CVBS Output

13-6 Samsung Electronics

 Schematic Diagrams

13-6 Audio

(DVD-909 OPTION)

Samsung Electronics 13-7

Schematic Diagrams

13-7 5.1 Channel Audio (DVD-909 Only)

13-8 Samsung Electronics

 Schematic Diagrams

13-8 RF

Samsung Electronics 13-9

Schematic Diagrams

13-9 ZiVA

13-10 Samsung Electronics

 Schematic Diagrams

13-10 DSP

Samsung Electronics 13-11

Schematic Diagrams

13-11 Front Micom/VFD Display

U.S.A.

FRANCE

CON23-A (DVD-909)
CON24 (DVD-709)

TO KEY CN18

CN15
(DVD-909 ; PIN12)

CN16 (DVD-709 ; PIN6)

TO KEY CON22 (PIN6)

TO KEY CON21
(PIN12)

13-12 Samsung Electronics

 Schematic Diagrams

13-12 Component (DVD-909 Only ; Option)

Samsung Electronics 13-13

Schematic Diagrams

13-13 Scart Jack (DVD-909 PAL Only)

R Output (Scart Jack) G Output (Scart Jack) B Output (Scart Jack)

13-14 Samsung Electronics

 Schematic Diagrams

13-14 Mute

Samsung Electronics 13-15

Schematic Diagrams

13-15 Play & Phone/Power (DVD-909 Only)

PLAY PHONE/POWER

13-16 Play & Power (DVD-709 Only)

PLAY POWER

13-16 Samsung Electronics

 Schematic Diagrams

13-17 Deck

Samsung Electronics 13-17

Schematic Diagrams

13-18 Remote Control

13-18 Samsung Electronics