Xy dng core gii nn m thanh s trong h thng a phng tin

Design of Digital Audio Decompressing Core Used in Multimedia Systems

L Tin Thng, Hong nh Chin, Cao Tun V
Abstract: This content is aimed to contribute the FPGAbased design methodology presented to a specific topic related to audio signal processing in mulimedia system for the representation of the used method. A multimedia system links images and audio to distribute and transmit information to users. These images and audio data have to be compressed for raising capacity of storing and processing in the real time, allowing the content of signals suitable for band-width of processing system. For each teminals, sofwares are the most common to read the compressed data, but in recent years potable devices such as mobile phones, MP3 players, etchave gained in popularity, therefore designing of decompressing cores used in the handheld devices are the necessary demand for professional ASIC designers. This paper introduces the architecture of an MP3 decoding core. The core can be partitioned into subbcores (Huffman, Requantizer, Reorder, Antialias, IMDCT, filterbank) small enough that each subcore can be designed, coded, and tested easily. This core is described as a functional specification in VHDL, and is synthetized, compiled and simulated on Xilinx ISE 7.1i sofware. Finally, this core is implemented on FPGA Virtex-II Pro board. Key words: MP3, Huffman decoding, Filterbank, VHDL, Multimedia, Xilinx ISE 7.1i.

cc mu audio m ho PCM tuyn tnh, c bin i t min thi gian thnh mt s nht nh cc bng tn khc nhau trong min tn s. Qu trnh gii m cho hnh 1.
ng b Coded bitstream (synchronizer)
Gii m Huffman
Lng t ho ngc (Requantizer

reorder

PCM Bng lc tng

h p

IMDCT

Chng chng ln
(Antialias)

Gii m Stereo

Hnh 1.

Qu trnh gii m mp3 [4]

1. ng b (Synchronizer) Trc lc vic gii m din ra, im bt u cc frame phi c tm thy. Nu frame b ngt ta khng tm c chnh xc v tr ca frame k tip. Cu trc mt frame c cho nh hnh 2.
Header
32 bit

CRC
16 bit

Thng tin ph D liu chnh

136 bit trong knh n 256 bit trong knh i

D liu ph

Hnh 2. Cu trc frame ca audio MP3 [4].

2. Gii m Huffman I. TNG QUAN V GII NN M THANH S THEO CHUN MP3 Chun MP3 (MPEG 1 layer 3) - c pht trin t nm 1988 n 1992 bi nhm Moving Picture Experts Group - s dng k thut nn d liu M ho bin i min tn s. K thut ny s dng cc khi ca 49 Qu trnh gii m c da trn cc bng Huffman (i vi MP3, c 32 bng Huffman khc nhau) m cc bng ny c s dng cho vic nh x t m Huffman n k t. S nh x ca cc k t n cc m Huffman da trn ni dung thng k ca chui ng vo. Cc k t

xut hin vi tn sut ln th c m ho vi mt t m ngn, trong khi cc k t xut hin vi tn sut nh hn th c m ho bng cc t m di hn. Ch c mt v mt k t cho mi chui ng vo hp l. Ng ra ca b gii m Huffman l 576 lines tn s, c gi tr integer. Cc lines tn s ny c chia thnh 3 phn: Big-values, count1 v rzero (hnh 3).
576 lines tn s Big-values
2*bigvalue 2*bigvalues + 4*count1

Khi lng t ho ngc s dng cc h s thang bin i cc gi tr c m ho Huffman isi tr v cc gi tr ph xri theo phng trnh (1) v (2). Phng trnh no c s dng ph thuc vo chc nng windowing c dng trong qu trnh m ho nh cng thc (1), (2). Vi scalefac_s v scalefac_l l cc h s thang c cung cp bi khi gii m Huffman. Global_gain, subblock_gain v preflag l cc tham s c th c tm thy trong thng tin ph ca frame. 4. Reorder Trong sut qu trnh m ho, MDCT c th sp xp ng ra thnh hai cch khc nhau. Ng ra t MDCT c sp xp bi cc bng con theo th t tng dn tn s. Khi mt short block c gii m, short window c s dng. Reorder ch thch hp vi cc short blocks, n sp xp cc lines tn s u tin l bng cc bng con v sau l bng tn s (hnh 4).
Window 0 Window 1 Window 2

Count1

rzero

Hnh 3. Cc lines tn s c chia thnh 3 phn [3]

Big-values cha cc lines tn s thp nht v c m ho vi chnh xc cao nht. Tm ca big-values l 15 . gii m cc gi tr ln hn, mt vi bng s dng gi tr 15 nh mt escape code, n c trong mt bng m c lp s lng cc bit v cng thm gi tr ny vo 15. S lng cc bit c m ch trn gi l linbits. Gi tr ca linbits bin thin t 1 n 13. Phn tip theo, count1, ch c th c m ho vi cc gi tr 0, 1, hoc -1. Phn cui cng, rzero, miu t cc tn s cao nht v khng phi l mt phn ca chui bit. Thay vo , rzeros cha cc tn s m b loi b bi encoder, v vng ny c n cc gi tr zero bi b decoder. Khi gii m big-values, bng m Huffman s to ra hai lines tn s cho mi chui ng vo v bn lines tn s khi gii m phn count1. 3. Lng t ho ngc (Requantizer) Cc k t t Huffman decoder c th ti cu trc cc lines tn s (normal frequency lines) bng cch s dng cc scalefactors trong thng tin ph (side information) ca frame.
- i vi short blocks:

..
Subband Subband

Subband 0

..
Subband 0 Subband Subband

(mu ti m ch tn s cao hn mu sng)

Hnh 4. Qu trnh reordering [10]

5. Gim chng ln (Antialias) y l c gng chng chng ln (antialias) ca cc blocks gim cc nh hng alias khng th trnh c do vic s dng cc b lc di nn (bandpass filter) khng l tng trong lc bng a pha encoder.

xri = sign(isi). is i 3 .2 4
- i vi long blocks:
4

( global _ gain[ gr ] 210 )

.2-scalefac_multiplier.scalefac_s[gr][ch][sfb][window]. 2-2.subblock_gain[window][gr]

(1)

xri = sign(isi) . is i 3 .2 4

( global _ gain[ gr ] 210 )

. 2-scalefac_multiplier.scalefac_l[gr][ch][sfb]. 2-preflag[gr].pretab[sfb]

(2)

50

S gim chng ln bao gm 8 tnh ton hnh bm cho mi subband nh hnh 5. Cc h s trong b lc hnh bm c nh ngha trong [3].
X0 . . . X 17 X18 . . . X 35 X 36 18 (0) (1) (2) .... 18 (0)
: :

18 gi tr vo

IMDCT
Block type 36 gi tr ng ra

short start stop normal

Windowing
18 gi tr thp hn 18 gi tr cao hn

(1)

(2)

....

Delay

+
: :

18 gi tr sau

o tn s

X 539 X 540 . . . X 557 X 558 . . . X57

(0)

(1)

(2)

....

Hnh 6. Chui hot ng ca IMDCT [10]

18 .... 18

7. Bng lc tng hp a pha (Synthesis filterbank) Tng hp bng con l bc cui cng trong qu trnh gii m. N bin i 32 khi subband (mi khi cha 18 mu min thi gian) to ra 32 mu PCM ng thi, mi mu t mt subband (hnh 7).
BT U 32 mu subband ng vo Si i=0..31 shifting for i=1023 down to 64 doV[i]=V[i-64] Matrixing for i=0 to 63 do Vi=

(0)

(1)

(2)

8
cs i

+ + +

(i)

ca i ca i cs i

Hnh 5. Gim chng ln vi tnh ton hnh bm [3]

6. Bin i ngc cosine ri rc ci bin (IMDCT) IMDCT bin i cc bng con t min tn s sang min thi gian. Biu thc IMDCT c cho nh (3). n n 1 2
xi = k = X k cos[

31 k =0

N ik * S k

[2i + 1 + ](2k + 1)] 2n 2 vi 0 i n 1 (3)

IMDCT c s dng trong MP3 l loi DCT 18 im cho ra 36 mu t 18 gi tr vo. Nhng mu ny c nhn vi mt ca s 36 im trc khi chng c a n bc tip theo ca qu trnh gii m. Vic to ra 36 mu t 18 lines tn s c ngha rng ch 18 trong s cc mu l duy nht. Do IMDCT s dng mt chng lp 50% (a 50% overlap). 36 gi tr t windowing c chia thnh hai nhm, mt nhm thp v mt nhm cao, cha 18 gi tr mi nhm. S chng chp c thc hin bng cch cng cc gi tr t nhm thp hn vi gi tr tng ng t nhm cao hn t frame trc.

Xy dng vector U for i=0 to 7 do for j=0 to 31 do U[i*64+j]=V[i*128+j]; U[i*64+32+j]=V[i*128+96+j] Che (window) bi 5 h s To vector W: for i=0 to 511 do Wi = Ui * Di Tnh ton 32 mu for j=0 to 31 do Sj=

15 i =0

W j +32i

Ng ra 32 mu PCM c ti cu trc KT THC

Hnh 7. S tng hp bng con

Trong qu trnh tng hp, 32 gi tr subband c truyn n vector V 64 gi tr bng cch s dng bin 51

Ma trn MDCT. Vector V c y vo b FIFO, ni y s lu tr 16 vector V nh th. Vector U c to t 32 khi thnh phn xen k trong b FIFO v mt hm ca s D c a n U to ra vector W. Cc mu PCM (c ti cu trc) c c bng cch phn ly W thnh 16 vectors (mi vector l 32 gi tr) cng c v cng nhng vectors ny li. II. TNG QUAN QU TRNH THIT K CORE Core l khi (block) mch silicon tin thit k, thng cha t nht 5000 cng m cc blocks ny c th c s dng trong vic xy dng mt ng dng ln hn v phc tp hn trn mt chip bn dn. Trong lnh vc thit k SoC (system on a chip), vn dng li thit k (reuse-design) l rt quan trng khi phc tp ca h thng ngy cng tng ln khng ngng. Vic dng li thit k i hi phi lp ti liu cc khi chc nng mt cch y , lp trnh vi k nng cao, v thit k phi c kim tra mt cch cn thn. Cc cores phi c kim tra bng cc testbench v phi c m phng mt cch c lp. Lu cho qu trnh thit k cores cho hnh 8 gm cc bc chnh: c t v phn hoch - Vic u tin l m bo phi hon ton hiu r c t core ban u. Tip theo, phi tinh ch c t v phn hoch thit k thnh cc khi con (subcores). Thit k v c t khi con (subcore) - Khi vic phn hoch hon thnh, ngi thit k pht trin mt c t chc nng cho khi con, nhn mnh vn nh thi v chc nng ca cc giao din n cc khi con khc. Pht trin testbench - tinh ch testbench hnh vi (behavioral testbench) thnh mt testbench m c th c s dng trong vic kim tra RTL ca ton b core. Cc kim tra nh thi (timing checks) - Phi kim tra d tr nh thi (timing budgets) ca cc subcores m bo rng chng l nht qun v c th thc hin c.

Tch hp (Intergration) - Tch hp cc subcores thnh core bao gm to ra danh sch cc kt ni mc cao (top-level netlist). To sn phm (productization) - Trong sut qu trnh to sn phm, phi chun b cc cores cho vic s dng tch hp SoC. III. KIN TRC CORE Ton b core c c t trn ngn ng VHDL, y l ngn ng m t phn cng c s dng nhiu nht hin nay. Sau core thc thi trn h FPGA Virtex-II Pro XC2VP30-FF896 ca Xilinx. c im ca h ny l c 30816 t bo logic, 136 block ram 18 kbit, 136 b nhn 18x18, c n 644 tn hiu vo ra. Ng vo ca core gii nn MP3 l mt chui bit v qu trnh gii m s bin i chui bit ny thnh cc mu trc lc c a n mch DAC (s thnh tng t).
C T CORE Pht trin c t chc nng
To m hnh hnh vi

Pht trin m hnh hnh vi

Pht trin Testbench

Kim tra m hnh hnh vi Phn hoch thnh cc khi con (subcores) Vit c t chc nng Vit c t cng ngh Pht trin
rng buc nh thi Thc hin cc bc ny cho mi subcore

Vit RTL

Pht trin testbench M phng Verilog/VHDL o ph ca testbench (VHDL Cover)

Tng hp Bin dch thit k Thc hin Phn tch nng lng

Khi con sn sng tch hp

Hnh 8.Qu trnh thit k core [2]

Lu thit k core cho hnh 8. Ton b c t 52

core ni r phn I, c th c tm gn li bng s hnh 9. Giai on tip theo, phn hoch core thnh cc subcore chnh sau y: 1. Synchronizer Subcore ng b (synchronizer.vhd) c thit k theo kiu my trng thi. Lu my trng thi ca subcore ng b c cho nh hnh 10 vi cc trng thi sau:
FIND_SYNC: trng thi tm t ng b gm 12 bit 1 lin tip nhau. HEADER: trng thi xc nh im bt u ca mt frame. VALIDATE: trng thi xc nhn tnh hp l ca mt frame mp3. Nu cc trng id, layer, bitrate, frequency = reserved th chui bit tm thy khng phi l mt frame mp3 v trng thi k tip ca trng thi ny l trng thi khi ng li RESTART SIDE_INFO: l trng thi xc nh thng tin ph ca mt frame. MAIN_DATA: l trng thi xc nh d liu chnh ca frame. DECODE: trng thi xc nhn hon tt vic xc nh mt frame. RESTART: trng thi khi ng vic bt u xc nh mt frame mi.
B nh Resevoir h s thang

gii m Huffman c t trong mt b nh ph bin c kch c l 576 t ( di mi t l 32 bit). B gii m Huffman so snh chui ng vo vi thng tin trong cc bng m Huffman (c tt c 17 bng m c lu trong BSRs ca Virtex-II Pro) v to ra mt k t khi tm thy thng tin ng. Ng ra ca b gii m Huffman l 576 lines tn s.
FIND_SYNC RESTART
Id, layer, birate, frequency

HEADER

=reserved

VALIDATE DECODE

CRC MAIN_DATA SIDE_INFO

Hnh 10. S my trng thi ca khi ng b

Hnh 11 l my trng thi cho gii m Huffman vi cc trng thi:

IDLE: trng thi khng lm g c, i tn hiu start. CONT1: l trng thi kim tra loi ca s v ch nh n trng thi tip theo CONT2: Trng thi ch nh n cc trng thi tip theo: trng thi s dng ca s hn hp (mixed window) v trng thi s dng ca s ngn (short window). CALC_SF1: trng thi tnh ton h s thang dng loi ca s hn hp (mixed window). CALC_SF2: trng thi tnh ton h s thang dng loi ca s ngn (short window).

si_data si_valid si_req

ng b Synchronize r

Gii m Huffman

Lng t ho ngc

Reorder

B nh chnh

Mainmem

Requantizer

iu khin Controller

Chng chng ln

Antialias

IMDCT

filterbank

Giao tip so_valid Giaotiep so_req

so_data

CALC_SF4, CALC_SF5, CALC_SF6, CALC_SF7, DONE_SF: Cc trng thi tnh ton h s thang s dng loi ca s di. INIT_DEC: trng thi khi to cho vic gii m, ch nh n trng thi gii m k tip. DEC_BV: Trng thi gii m cho min big-values, chng quyt nh bng m Huffman no c s dng. HUFFMAN_LOOP: Trng thi ny biu din qu trnh gii m min big-values v xc nh c s dng linbits hay khng? INIT_LOOP_LINBITS: trng thi khi to cho vic cng

Hnh 9. Core gii nn MP3

2. Huffman Mc ch chnh ca subcore gii m Huffman (huffman.vhd) trc tin l to ra cc h s thang . Cc h s thang ny c s dng trong khi lng t ho ngc (Requantizer). Cc gi tr t b 53

thm linbits cho cp gi tr (x, y) nu cp gi tr ny l escape codes.

IDLE CALC_SF4 CONT1 CALC_SF5 CALC_SF6

Huffman decoder
sci

Controller

Table_look_up
(to t CORE Generator)

Table_ requantize

Requantize
(state machine)

Gain_ Correction
(to t CORE Generator)

CONT2 CALC_SF1 DONE_SF CALC_SF2

CALC_SF7 index counter

Divider _win
INIT_LOOP_ LINBITS DO_LINBITS_X S chia (8)

INIT_DEC HUFFMAN_ LOOP DEC_BV DO_LINBITS_S IGN Y DEC_RC1 HUFFMAN_ LOOP2 SIGN_V FILL_ ZEROS SIGN_Y

shifter

DO_LINBITS_Y

DO_LINBITS_S IGN X

Hnh 12. Kin trc khi lng t ho ngc

DONE_ HLOOP2

SIGN_W

Khi requantize c vit theo kiu my trng thi (hnh 13). y l khi giao tip trc tip vi khi Controller, b nh chnh v khi gii m Huffman. Khi ny cn c nhim v truy lc d liu cn thit t frame header v thng tin ph.
start=1

SIGN_X READY

B_type

Adjust Block_info

Hnh 11. My trng thi khi gii m Huffman

DO_LINBITS_X, DO_LINBITS_SIGN_X: Hai trng thi trn
index=57

IDL
index<57 6 xr=0

CALC SHIF Gain_corr

thc hin vic cng linbits vo gi tr x (l escape code)

DO_LINBITS_Y, DO_LINBITS_SIGN_Y: Hai trng thi trn

RAM

thc hin vic cng linbits vo gi tr y (l escape code)

DEC_RC1, HUFFMAN_LOOP2, DONE_HLOOP2: Ba trng

Hnh 13. My trng thi khi requantize

thi trn biu din qu trnh gii m min coun1, kt qu cho ra cc gi tr bn lines tn s cho mi chui ng vo.
SIGN_V, SIGN_W, SIGN_X, SIGN_Y: Bn trng thi trn tng ng vi tnh ton bn lines tn s cho mi chui ng vo khi gii m min count1.

Bc u tin ca qu trnh lng t ho l tnh ton is 3 .Vic tnh ton trc tip vi s m 4/3 trong m VHDL l kh thc hin v tn rt nhiu ti nguyn. Bi bo ny ngh mt cch thc hin s tnh ton ny l s dng bng tra - bng tra c thit k cha tt c 8192 gi tr ng vo c th c, chim khong 256 kbit b nh. Tnh ton trn c th c chia thnh: Nu is(i) < 1024, kt qu c th tm thy trc tip trong bng tra Nu is(i) 1024, gi tr u tin c chia bi 8. Kt qu t bng tra s c nhn vi 16. Bng tra s c lu trong BSRs ca Virtex-II Pro. Mt b m cc lines tn s c to cung cp 54
4

FILL_ZEROS: trng thi biu din min cn li ca 576 gi tr ng ra, cc gi tr min ny c in tng ng bng 0. READY: trng thi sn sng c granule hin thi.

3. Requantizer Kin trc ca subcore lng t ho ngc (requantizer.vhd) c cho nh hnh 12. D liu lu tr trong Gain_correction l cc h s c nh ngha trong ISO/IEC 11172 standard [3].

cho khi lng t ho ngc thng tin v line tn s no ang c to lng t ho ngc ti thi im . Tng s lines tn s cho mi frame l 576. Khi divider_win c to cho vic tnh ton ca s nhanh chng v n gin. C th c tng cng 3 ca s trong mt short block. Khi shifter c s dng cho vic nhn sign(isi)
4 3

XK Aa_rom
(to t Core Generator)

Mult

(to t Core Generator) B

Counter

Antialias
(state machine)

Aa_rom XK+1
(to t Core Generator) A

is

vi 2

1/4C

. Khi gain_correction l loi bng tra

Mult
(to t Core Generator) B

khc s dng cho vic lu tr cc h s correction. 4. Reorder Khi reorder (reorder.vhd) c mt nhim v, l sp xp li cc lines tn s trong mt granule. Cc cch cc lines tn s c sp xp ph thuc vo cc c (flags) trong header ca thng tin ph. Khi reorder c xy dng xung quanh 2 b nh. Mt b nh (Reoder_mem) cha cc ct gi tm thi cho d liu mu v b nh th hai (Reorder_lookup) cha cc a ch cho b nh chnh v b nh ct gi tm thi (hnh 14).
c t b nh chnh Reoder_mem
(to t CORE Generator)

Hnh 15. Kin trc khi antialias

6. IMDCT Kin trc cho subcore IMDCT (imdct.vhd) cho hnh 16. Ton b s hng cosine cho mi ng ra c th c xem nh l mt h s hng s bit da trn kt hp ca i v k phng trnh (3). Mt vi kho st cho cc s hng ny chng t tnh i xng gia cc gi tr khc nhau xi. Ch ca cc gi tr l c xc nh. Phn cc gi tr cn li c th t c nh l mt hm ca cc s hng c tnh ton trc . Do vic tnh ton ca mt phn t u tin v th ba ca tt c cc gi tr s xc nh ton b tp gi tr.
Cho short windowing cng vo, chen vo

Ghi vo b nh chnh

Reoder
(state machine)

Reoder_lookup
(to t CORE Generator) Xk
A B

BS_RAM
A1 B0
(c to t CORE Generator)

Add/Sub
S A

Mult
P

Acc
(c to t CORE Generator)

B1

(c to t CORE Generator)

Ghi vo b nh chnh

A0 AddrB

A ADD

Hnh 14. Kin trc khi reorder

AddrA

5. Antialias Khi antialias (antialias.vhd) c nhim v gim cc chng ln khng th trnh c do s dng cc b lc di nn khng l tng b m ho. Cng vic ny c th c c thc hin bng cch kt hp cc tn s s dng cc tnh ton hnh bm. Khi antialias c thit k l mt my trng thi cha mt tnh ton hnh bm v mt vi b m. Bn php nhn s dng mt b nhn c tin hnh v cui cng mt php cng v mt php tr c thc hin.
IMDCT
(state machine) Zero

Add/Sub
(c to t CORE Generator)

ADD

Hnh 16. Kin trc khi IMDCT

i vi tt c cc php tnh nhn, b nhn thng thng c s dng. t c php tng nh phng trnh (3), mt thanh ghi tch lu (Acc) c s dng. Tt c cc gi tr cosine (c s dng cho cc tnh ton IMDCT) v cc gi tr sine (c s dng cho windowing) u c lu tr trong BSRs Virtex-II Pro (BS_RAM). 55

7. Filterbank Vic thc thi bng lc tng hp a pha (filterbank.vhd) c th c chia thnh 2 phn: Phn u tin l tnh ton DCT ci bin 32 im v phn th hai l windowing v tng ca 512 gi tr to ra 32 mu ng ra.
Filter_ shifter
(to t CORE Generator) Ctrl_neg Ctrl_neg_zer Ctrl_dru

IV. TI NGUYN PHN CNG

Device utilization summary: Selected Device : 2vp30ff896-7 Number of Slices: 3630 out of 13696 26% Number of Slice Flip Flops: 1583 out of 27392 5% Number of 4 input LUTs: 6213 out of 27392 22% Number of bonded IOBs: 27 out of 556 4% Number of BRAMs: 23 out of 136 16% Number of MULT18X18s: 4 out of 136 2% Number of GCLKs: 2 out of 16 12% Timing Summary: Minimum period: 22.351ns (Maximum Frequency: 44.741MHz) Minimum input arrival time before clock: 7.907ns Maximum output required time after clock: 13.127ns Maximum combinational path delay: 6.277ns

Filter_ window_ control

Filter_ negate

Dum_ mdct Xk
(to t CORE Generator)

Filter_ drum
(to t CORE Generator)

Filterbank
(State machine)
Ctrl_accum

Filter_ accum
(to t CORE Generator)

V. KT LUN kim chng hot ng ca core, ta tin hnh testbench core (hnh 18) v s dng core xy dng mt m hnh my nghe nhc MP3 (hnh 19).
Clock generator clk

memo

multo

Hnh 17. Kin trc filterbank

Mt MDCT 32 im yu cu 32 x 32 php nhn s dng mt phng thc tnh ton khng ti u. Cc thut ton thc hin cc tnh ton DCT nhanh u c th s dng c, v c da trn tnh i xng ca ma trn DCT. Trong bi bo ny, ngi thc hin ngh mt thut ton cho k thut ti u l thut ton Lee [11]. Trong thit k, hai block ROM c s dng cha cc h s DCT v windowing, cng nh hai block RAM c s dng nh l mt thanh ghi dch 2 cng cho vic dch chuyn d liu cc khi DCT . 8. Khi giao tip Khi giao tip c nhim v nh dng chun cho d liu giao tip vi th gii thc. Ng ra d liu nn c gi theo giao thc I2S, c pht trin bi Philips. Chun I2S ch nh rng d liu c gi trn mt bus ni tip ng b. Bi v b gii m MP3 lm vic vi cc frames v granules, do n khng c kh nng to ra mt chui lin tc d liu nhng c th to ra 576 lines ti mt thi im. khc phc nhc im ny ta s dng BSR ca Virtex-II Pro lu tr ng ra, hot ng nh b m 1024 mu.

Reset generator
MP3 file reader

rst Decoder (decoder.vhd) so_clk so_data si_data so_sel

Hnh 18. S testbench cho core

Flash memory (cha file mp3)
si_dat so_vali a si_re d q

To CLK
clk so_cl k so_dat so_se l

FPGA

Mem_reader

decoder

B ni tip sang song song

DAC
Hnh 19. M hnh my nghe nhc MP3

Qua hai m hnh kim nghim hot ng ca core ni trn, ta thy core t c cc yu cu ra ca mc tiu thit k. nng cao cht lng core v gim bt ti nguyn cho vic thc thi, tc gi thc c vic la chn cc thut ton cho qu trnh gii m. Mt s gii thut ti u c th c s dng, nht l cc gii thut cho 56

vic tnh ton IMDCT, filterbank, requantizer bi bo ny, trong cc phn tnh ton thc thi cho cc subcores, cc tc gi ngh mt s thut ton tnh ton nhanh nh IMDCT nhanh, thut ton Lee [11], v ngh cc h s c nh ngha bi [3] s c lu tr trong BSRs ca Virtex-II Pro thay v s dng cc khai bo hng trong m VHDL. TI LIU THAM KHO
[1] L Tin Thng, X l s tn hiu v Wavelets, NXB H Quc Gia, 2002. [2] Michael Keating and Pierre Bricaud, Reuse methodology manual for SoC designs, Kluwer Academic Publishers, 2001. [3] ISO/IEC 11 172-3, Information technology - Coding of moving pictures and associated audio for digital storage media at up to about 1,5 Mbit/s - Part 3: Audio, Aug. 1993. [4] Michael Robin and Michel Poulin, Digital Television Fundamentals, McGraw-Hill, 1997.

[5] K. Brandenburg and H. Popp, An Introduction to MPEG Layer-3, Fraunhofer Institute, EBU Technical Review, June 2000. [6] D. Pan et al., IIS MP3 Decoder Source Code, http://www.mp3-tech.org, April 1995. [7] W. Jung, SPLAYMP3 Decoder Source http://splay.sourceforge.net, April 2001. Code,

[8] M. Hipp et al., MPG123 MP3 Decoder Source Code, http://www.mpg123.de, April 2001. [9] K. Lagerstrum, MP3 Reference Decoder Source Code, http://www.dtek.chalmers.se, 2001. [10] Staffan Gadd, A hardware accelerated MP3 decoder with bluetooth streaming capabilities, Master of science Thesis, 2001. [11] B. G. Lee, A new algoritm to compute the discrete cosine transform, IEEE transactions on acoustics, speech and signal processing, vol ASSP-32, No 6, December 1984. Ngy nhn bi: 07/01/2006.

S LC TC GI L TIN THNG

HONG NH CHIN Sinh ngy: 17/4/1955 ti Qung Ngi. Tt nghip H MTYCI-Moscow 1979. Nhn bng Thc s H Bch khoa TP. HCM nm 1998, nhn bng Tin s nm 2003. Hin ang ging dy ti Khoa in- in t, H Bch khoa TP. HCM, Lnh vc nghin cu: Truyn thng v tinh, x l tn hiu s, h thng truyn thng, wavelets, neuron networks. Email: hdchien@hcmut.edu.vn

Sinh nm 1957 ti TP.HCM. Tt nghip i hc nm 1981, nhn bng Tin s nm 1998 ti i hc Tasmania, Australia ngnh in t - Vin thng, c phong chc danh Ph Gio s nm 2002. Hin cng tc ti Khoa in - in t, H Bch Khoa TP. HCM. Lnh vc nghin cu: X l tn hiu, Thng tin s, x l tn hiu radar, wavelets v ng dng, neuralfuzzy systems. Email: thuongle@hcmut.edu.vn

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