Verilog HDL

Gio trnh Verilog HDL
Verilog Hardware Description Language NI DUNG Chng1. Dn nhp thit k h thng s vi Verilog
Khi kch thc v phc tp ca h thng thit k ngy cng tng, nhiu cng c h tr thit k trn my tnh (CAD) c s dng vo qu trnh thit k phn cng. Thi k u, nhng cng c m phng v to ra phn cng a ra phng php thit k, kim tra, phn tch, tng hp v t ng to ra phn cng mt cch phc tp. S pht trin khng ngng ca nhng cng c thit k mt cch t ng l do s pht trin ca nhng ngn ng m t phn cng (HDLs) v nhng phng php thit k da trn nhng ngn ng ny. Da trn nhng ngn ng m t phn cng (HDLs), nhng cng c CAD trong thit k h thng s c pht trin v s dng rng ri bi nhng k s thit k phn cng. Hin ti, ngi ta vn ang tip tc nghin cu tm ra nhng ngn ng m t phn cng tt hn v tru tng hn. Mt trong nhng ngn ng m t phn cng c s dng rng ri nht l ngn ng Verilog HDL. Do c chp nhn rng ri trong ngnh cng nghip thit k s, Verilog tr thnh mt kin thc c i hi phi bit i vi nhng k s cng nh sinh vin lm vic v hc tp trong lnh vc phn cng my tnh. Trong chng ny, ta s trnh by nhng cng c v mi trng lm vic c sn tng thch vi ngn ng Verilog m mt k s thit k c th s dng trong qui trnh thit k t ng ca mnh gip y nhanh tin thit k. Chng ta s tho lun tng bc v thit k phn cp, thit k mc cao t vic m t thit k bng ngn ng Verilog n vic to ra phn cng ca thit k . Nhng qui trnh v nhng t kha chuyn mn cng s c minh ha phn ny. K tip, chng ta cng s tho lun nhng cng
Lm c Khi University of Information Technology Page 1
Verilog Hardware Description Language

c CAD hin c tng thch vi Verilog v chc nng ca n trong mi trng thit k t ng. Phn cui cng ca chng ny s ni v mt s c tnh ca Verilog khin n tr thnh mt ngn ng c nhiu k s thit k phn cng la chn. 1.1 Qui trnh thit k s Trong thit k mt h thng s s dng mi trng thit k t ng, qui trnh thit k bt u bng vic m t thit k ti nhiu mc tru tng khc nhau v kt thc bng vic to ra danh sch cc linh kin cng nh cc ng kt ni gia cc linh kin vi nhau ( netlist) cho mt mch tch hp vi ng dng c th (ASIC), mch in ( layout) cho mt mch tch hp theo yu cu khch hng ( custom IC), hoc mt chng trnh cho mt thit b logic c kh nng lp trnh c (PLD). Hnh 1.1 m t tng bc trong qui trnh thit k ny. Bc u ca thit k, mt thit k s c m t bi s hn hp gia m t mc hnh vi (behavioural) Verilog, s dng nhng gi (module) thit k Verilog c thit k sn, v vic gn h thng cc bus v wire lin kt cc gi thit k ny thnh mt h thng hon chnh. K s thit k cng phi c trch nhim to ra d liu kim tra (testbench) xem thit k ng chc nng hay cha cng nh dng kim tra thit k sau khi tng hp. Vic kim tra thit k c th thc hin c bng vic m phng, chn nhng k thut kim tra, kim tra thng thng hoc kt hp c ba phng php trn. Sau bc kim tra nh gi thit k ( bc ny c gi l kim tra tin tng hp (presynthesis verification)), thit k s c tip tc bng vic tng hp to ra phn cng thc s cho h thng thit k cui cng (ASIC, custom IC or FPLD,). Nu h thng thit k l ASIC, thit k s s c sn xut bi nh sn xut khc;

nu l custom IC, thit k s c sn xut trc tip; nu l FPLD, thit k s c np ln thit b lp trnh c. Sau bc tng hp v trc khi phn cng thc s c to ra, mt qu trnh m phng khc (hu tng hp (postsynthesis)) phi c thc hin. Vic m phng ny, ta c th s dng testbench tng t testbench s dng trong m phng tin tng hp (presynthesis). Bng phng php ny, m hnh thit k mc hnh vi v m hnh phn cng ca thit k c kim tra vi cng d liu ng vo. S khc nhau gia m phng tin tng hp v hu tng hp l mc chi tit c th t c t mi loi m phng.
Lm c Khi
University of Information Technology
Page 3

Nhng phn tip theo s m t t m v mi khi trong hnh 1.1.
1.1.1 Dn nhp thit k
Bc u tin trong thit k h thng s l bc dn nhp thit k. Trong bc ny, thit k c m t bng Verilog theo phong cch phn cp t cao xung thp (top-down). Mt thit k hon chnh c th bao gm nhng linh kin mc cng hoc mc transistor, nhng khi (module) phn cng c chc nng phc tp hn c m t mc hnh vi, hoc nhng linh kin c lit k bi cu trc bus. Do nhng thit k Verilog mc cao thng c m t mc m ti n m t h thng nhng thanh ghi v s truyn d liu gia nhng thanh ghi ny thng qua h thng bus, vic m t h thng thit k mc ny c xem nh l mc truyn d liu gia cc thanh ghi (RTL). Mt thit k hon chnh c m t nh vy s to ra c phn cng tng ng thc s r rng. Nhng cu trc thit k Verilog mc RTL s dng nhng pht biu qui trnh (producedural statements), php gn lin tc (continuous assignments), v nhng pht biu gi s dng khi (module) xy dng sn. Nhng pht biu qui trnh Verilog (procedural statements) c dng m t mc hnh vi mc cao. Mt h thng hoc mt linh kin c m t mc hnh vi th tng t vi vic m t trong ngn ng phn mm. V d, chng ta c th m t mt linh kin bng vic kim tra iu kin ng vo ca n, bt c hiu, ch cho n khi c s kin no xy ra, quan st nhng tn hiu bt tay v to ra ng ra. M t h thng mt cch qui trnh nh vy, cu trc if-else, case ca Verilog cng nh nhng ngn ng phn mm khc u s dng nh nhau.

Nhng php gn lin tc (continuous assignment) trong Verilog l nhng php gn cho vic th hin chc nng nhng khi logic, nhng php gn bus, v m t vic kt ni gia h thng bus v cc chn ng vo v ng ra. Kt hp vi nhng hm Boolean v nhng biu thc c iu kin, nhng cu trc ngn ng ny c th c m t nhng linh kin v h thng theo nhng php gn thanh ghi v bus ca chng. Nhng pht biu gi s dng khi Verilog c thit k sn (instantiantion statements) c dng cho nhng linh kin mc thp trong mt thit k mc cao hn. Thay vi m t mc hnh vi, chc nng, hoc bus ca mt h thng, chng ta c th m t mt h thng bng Verilog bng cch kt ni nhng linh kin mc thp hn. Nhng linh kin ny c th nh nh l mc cng hay transistor, hoc c th ln nh l mt b vi x l hon chnh.
1.1.2 Testbench trong Verilog
Mt h thng c thit k dng Verilog phi c m phng v kim tra xem thit k ng chc nng cha trc khi to ra phn cng. Trong qu trnh chy m phng ny, nhng li thit k v s khng tng thch gia nhng linh kin dng trong thit k c th c pht hin. Chy m phng mt thit k i hi vic to ra mt d liu ng vo kim tra v qu trnh quan st kt qu sau khi chy m phng, d liu dng kim tra ny c gi l testbench. Mt testbench s dng cu trc mc cao ca Verilog to ra d liu kim tra, quan st p ng ng ra, v c vic bt tay gia nhng tn hiu trong thit k. Bn trong testbench, h thng thit k cn chy m phng s c gi ra (instantiate) trong testbench. D liu testbench cng vi h thng thit k s to ra mt m hnh m phng m s c s dng bi mt cng c m phng Verilog.

1.1.3 nh gi thit k
Mt nhim v quan trng trong bt k thit k s no cng cn l nh gi thit k. nh gi thit k l qu trnh m ngi thit k s kim tra thit k ca h c sai st no c th xy ra trong sut qu trnh thit k hay khng. Mt sai st thit k c th xy ra do s m t thit k m h, do sai st ca ngi thit k, hoc s dng khng ng nhng khi trong thit k. nh gi thit k c th thc hin bng m phng, bng vic chn nhng k thut kim tra, hoc kim tra thng thng.
1.1.3.1 M phng
Chy m phng dng trong vic nh gi thit k c thc hin trc khi thit k c tng hp. Bc chy m phng ny c hiu nh m phng mc hnh vi, mc RTL hay tin tng hp. mc RTL, mt thit k bao gm xung thi gian clock nhng khng bao gm tr hon thi gian trn cng v dy kt ni (wire). Chy m phng mc ny s chnh xc theo xung clock. Thi gian ca vic chy m phng mc RTL l theo tn hiu xung clock, khng quan tm n nhng nguy him tim n c th khin thit k b li (hazards, glitch), hin tng chy ua khng kim sot gia nhng tn hiu (race conditions), nhng vi phm v thi gian setup v hold ca tn hiu ng vo, v nhng vn lin quan n nh thi khc. u im ca vic m phng ny l tc chy m phng nhanh so vi chy m phng mc cng hoc mc transistor. Chy m phng cho mt thit k i hi d liu kim tra, thng thng trong mi trng m phng Verilog s cung cp nhiu phng php khc nhau a d liu kim tra ny vo thit k kim tra. D liu kim tra c th c to ra bng ha s dng nhng cng c son tho dng sng, hoc bng testbench. Hnh 1.2 m t hai cch khc nhau

nh ngha d liu kim tra ng vo ca mt cng c m phng. Nhng ng ra ca cng c m phng l nhng dng sng ng ra ( c th quan st trc quan).
chy m phng vi Verilog testbench, trong testbench s gi h thng thit k ra kim tra, lc ny h thng thit k c xem nh l mt phn ca testbench, testbench s cung cp d liu kim tra n ng vo ca h thng thit k. Hnh 1.3 m t mt on code ca mt mch m, testbench ca n, cng nh kt qu chy m phng ca n di dng sng ng ra. Quan st hnh ta thy vic chy m phng s nh gi chc nng ca mch m. Vi mi xung clock th ng ra b m s tng ln 1. Ch rng, theo biu thi gian th ng ra b m thay i ti cnh ln xung clock v khng c thi gian tr hon do cng cng nh tr hon trn ng truyn. Kt qu chy m phng ch ra rng chc nng ca mch m l chnh xc m khng cn quan tm n tn s xung clock. Hin nhin, nhng linh kin phn cng thc s s c p ng khc nhau. Da trn nh thi v thi gian tr hon ca nhng khi c s

dng, thi gian t cnh ln xung clock n ng ra ca b m s c tr hon khc khng. Hn na, nu tn s xung clock c cp vo mch thc s qu nhanh so vi tc truyn tn hiu bn trong cc cng v transistor ca thit k th ng ra ca thit k s khng th bit c. Vic m phng ny khng cung cp chi tit v cc vn nh thi ca h thng thit k c m phng. Do , nhng vn tim n v nh thi ca phn cng do tr hon trn cng s khng th pht hin c. y l vn in hnh ca qu trnh m phng tin tng hp hoc m phng mc hnh vi. iu bit c trong hnh 1.3 l b m ca ta m s nhi phn. Thit k hot ng nhanh chm th no, hot ng c tn s no ch c th bit c bng vic kim tra thit k sau tng hp.
Lm c Khi
Page 8

1.1.3.2 K thut chn kim tra (assertion)
Thay v phi d theo kt qu m phng bng mt hay to nhng d liu kim tra testbench phc tp, k thut chn thit b gim st c th c s dng kim tra tun t nhng c tnh ca thit k trong sut qu trnh m phng. Thit b gim st c t bn trong h thng thit k c m phng bi ngi thit k. Ngi thit k s quyt nh xem chc nng ca thit k ng hay sai, nhng iu kin no thit k cn phi tha mn. Nhng iu kin ny phi tun theo nhng c tnh thit k, v thit b gim st c chn vo h thng thit k m bo nhng c tnh ny khng b vi phm. Chui thit b gim st ny s sai nu mt c tnh no c t vo bi ngi thit k b vi phm. N s cnh bo ngi thit k rng thit k khng ng chc nng nh mong i. Th vin OVL ( Open Verification Library) cung cp mt chui nhng thit b gim st chn vo h thng thit k gim st nhng c tnh thng thng ca thit k. Ngi thit k c th dng nhng k thut gim st ca ring mnh chn vo thit k v dng chng kt hp vi testbench trong vic kim tra nh gi thit k.
1.1.3.3 Kim tra thng thng
Kim tra thng thng l qu trnh kim tra nhng c tnh bt k ca thit k. Khi mt thit k hon thnh, ngi thit k s xy dng mt chui nhng c tnh tng ng vi hnh vi ca thit k. Cng c kim tra thng thng s kim tra thit k m bo rng nhng c tnh c m t p ng c tt c nhng iu kin. Nu c mt c tnh c pht hin l khng p ng ng, c tnh c xem nh vi phm. c tnh bao ph (coverage) ch ra bao nhiu phn trm c tnh ca thit k c kim tra.

1.1.4 Bin dch v tng hp thit k
Tng hp l qu trnh to ra phn cng t ng t mt m t thit k phn cng tng ng r rng. Mt m t phn cng Verilog dng tng hp khng th bao gm tn hiu v m t nh thi mc cng, v nhng cu trc ngn ng khc m khng dch sang nhng phng trnh logic tun t hoc t hp. Hn th na, nhng m t phn cng Verilog dng cho tng hp phi tun theo nhng phong cch vit code mt cch nht nh cho mch t hp cng nh mch tun t. Nhng phong cch ny v cu trc Verilog tng ng ca chng c nh ngha trong vic tng hp RTL. Trong qui trnh thit k, sau khi mt thit k c m t hon thnh v kt qu m phng tin tng hp ca n c kim tra bi ngi thit k, n phi c bin dch n tin gn hn n vic to thnh phn cng thc s trn silicon. Bc thit k ny i hi vic m t phn cng ca thit k phi c nhn ra. V d, chng ta phi ch n mt ASIC c th, hoc mt FPGA c th nh l thit b phn cng mc ch ca thit k. Khi thit b mc ch c ch ra, nhng tp tin m t v cng ngh (technology files) ca phn cng ( ASIC, FPGA, hoc custom IC) s cung cp chi tit nhng thng tin v nh thi v m t chc nng cho qu trnh bin dch. Qu trnh bin dch s chuyn i nhng phn khc nhau ca thit k ra mt nh dng trung gian ( bc phn tch), kt ni tt c cc phn li vi nhau, to ra mc logic tng ng ( bc tng hp), sp xp v kt ni ( place and route ) nhng linh kin trong thit b phn cng mc ch li vi nhau thc hin chc nng nh thit k mong mun v to ra thng tin chi tit v nh thi trong thit k.
Lm c Khi
Page 10

Hnh 1.4 m t qu trnh bin dch v m t hnh nh kt qu ng ra ca mi bc bin dch. Nh trn hnh, ng vo ca bc ny l mt m t phn cng bao gm nhng mc m t khc nhau ca Verilog, v kt qu ng ra ca n l mt phn cng chi tit cho thit b phn cng mc ch nh FPLD hay sn xut chip ASIC.
1.1.4.1 Phn tch
Mt thit k hon chnh c m t dng Verilog c th bao gm m t nhiu mc khc nhau nh mc hnh vi, h thng bus v dy kt ni vi nhng linh kin Verilog khc. Trc khi mt thit k hon chnh to ra phn cng, thit k phi c phn tch v to ra mt nh dng ng nht cho tt c cc phn trong thit k. Bc ny cng kim tra c php v ng ngha ca m ng vo Verilog.
1.1.4.2 To phn cng
Sau khi to c mt d liu thit k c nh dng ng nht cho tt c cc linh kin trong thit k, bc tng hp s bt u bng chuyn i d liu thit k trn sang nhng nh dng phn cng thng thng nh mt chui nhng biu thc Boolean hay mt netlist nhng cng c bn.
Lm c Khi
Page 11
1.1.4.3 Ti u logic
Bc k tip ca qu trnh tng hp, sau khi mt thit k c chuyn i sang mt chui nhng biu thc Boolean, bc ti u logic c thc hin. Bc ny nhm mc ch lm gim nhng biu thc vi ng vo khng i, loi b nhng biu thc lp li, ti thiu hai mc, ti thiu nhiu mc. y l qu trnh tnh ton rt hao tn thi gian v cng sc, mt s cng c cho php ngi thit k quyt nh mc ti u. Kt qu ng ra ca bc ny cng di dng nhng biu thc Boolean, m t logic di dng bng, hoc netlist gm nhng cng c bn.
Lm c Khi
Page 12

1.1.4.4 Binding
Sau bc ti u logic, qu trnh tng hp s dng thng tin t thit b phn cng mc ch quyt nh chnh xc linh kin logic no v thit b no cn hin thc mch thit k. Qu trnh ny c gi l binding v kt qu ng ra ca n c ch nh c th s dng cho FPLD, ASIC, hay custom IC.
1.1.4.5 Sp xp v i dy lin kt
Bc sp xp v i dy lien kt s quyt nh vic t v tr ca cc linh kin trn thit b phn cng mc ch. Vic kt ni cc ng vo v ng ra ca nhng linh kin ny dng h thng dy lin kt v vng chuyn mch trn thit b phn cng mc ch c quyt nh bi bc sp xp v i dy lin kt ny. Kt qu ng ra ca bc ny c a ti thit b phn cng mc ch, nh np ln FPLD, hay dng sn xut ASIC. Mt v d minh ha v qu trnh tng hp c ch ra trn hnh 1.5. Trong hnh ny, mch m m c dng chy m phng trong hnh 1.3 c tng hp. Ngoi vic m t phn cng thit k dng Verilog, cng c tng hp i hi nhng thng tin m t thit b phn cng ch tin hnh qu trnh tng hp ca mnh. Kt qu ng ra ca cng c tng hp l danh sch cc cng v flip-flop c sn trong thit b phn cng ch v h thng dy kt ni gia chng. Hnh 5 cng ch ra mt kt qu ng ra mang tnh trc quan m c to ra t ng bng cng c tng hp ca Altera Quartus II.
Lm c Khi
Page 13
1.1.5 M phng sau khi tng hp thit k
Sau khi qu trnh tng hp hon thnh, cng c tng hp s to ra mt netlist hon chnh cha nhng linh kin ca thit b phn cng ch v cc gi tr nh thi ca n. Nhng thng tin chi tit v cc cng c dng hin thc thit k cng c m t trong netlist ny. Netlist ny cng bao gm nhng thng tin v tr hon trn ng dy v nhng tc ng ca ti ln cc cng dng trong qu trnh hu tng hp. C nhiu nh dng netlist ng ra c th c to ra bao gm c nh dng Verilog. Mt netlist nh vy c th c dng m phng, v m phng ny c gi l m phng hu tng hp. Nhng vn v nh thi, v tn s xung clock, v hin tng chy ua khng kim sot, nhng nguy him tim n ca thit

k ch c th kim tra bng m phng hu tng hp thc hin sau khi thit k c tng hp. Nh trn hnh 1.1, ta c th s dng d liu kim tra m dng cho qu trnh m phng tin tng hp dng cho qu trnh m phng hu tng hp. Do tr hon trn ng dy v cc cng, p ng ca thit k sau khi chy m phng hu tng hp s khc vi p ng ca thit k m ngi thit k mong mun. Trong trng hp ny, ngi thit k phi sa li thit k v c gng trnh nhng sai st v nh thi v hin tng chy ua gia nhng tn hiu m khng th kim sot.
1.1.6 Phn tch thi gian
Quan st trn hnh 1.1, bc phn tch thi gian l mt phn trong qu trnh bin dch, hoc trong mt s cng c th bc phn tch thi gian ny c thc hin sau qu trnh bin dch. Bc ny s to ra kh nng xu nht v tr hon , tc xung clock, tr hon t cng ny n cng khc, cng nh thi gian cho vic thit lp v gi tn hiu. Kt qu ca bc phn tch thi gian c th hin di dng bng hoc biu . Ngi thit k s dng nhng thng tin ny xc nh tc xung clock, hay ni cch khc l xc nh tc hot ng ca mch thit k.
1.1.7 To linh kin phn cng
Bc cui cng trong qui trnh thit k t ng da trn Verilog l to ra phn cng thc s cho thit k. Bc ny c th to ra mt netlist dng sn xut ASIC, mt chng trnh np vo FPLD, hay mt mch in cho mch IC.
Lm c Khi
Page 15

1.2 Ngn ng phn cng Verilog ( Verilog HDL) Trong phn trc, ta trnh by tng bc thit k mc RTL t mt m t thit k Verilog cho n vic hin thc ra mt phn cng thc s. Qui trnh thit k ny ch c th thc hin c khi ngn ng Verilog c th hiu c bi ngi thit k h thng, ngi thit k mc RTL, ngi kim tra, cng c m phng, cng c tng hp, v cc my mc lin quan. Bi v tm quan trng ca n trong qui trnh thit k, Verilog tr thnh mt chun quc t IEEE. Chun ny c s dng bi ngi thit k cng nh ngi xy dng cng c thit k.
1.2.1 Qu trnh pht trin Verilog
Verilog c ra i vo u nm 1984 bi Gateway Design Automation. Khi u, ngn ng u tin c dng nh l mt cng c m phng v kim tra. Sau thi gian u ngn ng ny c chp nhn bi ngnh cng nghip in t, mt cng c m phng, mt cng c phn tch thi gian, v sau ny vo nm 1987, cng c tng hp c xy dng v pht trin da vo ngn ng ny. Gateway Design Automation v nhng cng c da trn Verilog ca hang sau ny c mua bi Cadence Design System. T sau , Cadence ng vai tr ht sc quan trng trong vic pht trin cng nh ph bin ngn ng m t phn cng Verilog. Vo nm 1987, VHDL tr thnh mt chun ngn ng m t phn cng ca IEEE. Bi do s h tr ca B quc phng (DoD), VHDL c s dng nhiu trong nhng d n ln ca chnh ph M. Trong n lc ph bin Verilog, vo nm 1990, OVI ( Open Verilog International) c thnh lp v Verilog chim u th trong lnh vc cng nghip. iu ny to ra mt s quan tm kh ln t ngi dng v cc nh cung cp EDA ti Verilog.

Vo nm 1993, nhng n lc nhm chun ha ngn ng Verilog c bt u. Verilog tr thnh chun IEEE, IEEE Std 1364-1995, vo nm 1995. Vi nhng cng c m phng, cng c tng hp, cng c phn tch thi gian, v nhng cng c thit k da trn Verilog c sn, chun Verilog IEEE ny nhanh chng c chp nhn su rng trong cng ng thit k in t. Mt phin bn mi ca Verilog c chp nhn bi IEEE vo nm 2001. Phin bn mi ny c xem nh chun Verilog-2001 v c dng bi hu ht ngi s dng v ngi pht trin cng c. Nhng c im mi trong phin bn mi l n cho php bn ngoi c kh nng c v ghi d liu, qun l th vin, xy dng cu hnh thit k, h tr nhng cu trc c mc tru tng cao hn, nhng cu trc m t s lp li, cng nh thm mt s c tnh vo phin bn ny. Qu trnh ci tin chun ny vn ang c tip tc vi s ti tr ca IEEE.
1.2.2 Nhng c tnh ca Verilog
Verilog l mt ngn ng m t phn cng dng c t phn cng t mc transistor n mc hnh vi. Ngn ng ny h tr nhng cu trc nh thi cho vic m phng nh thi mc chuyn mch v tc thi, n cng c kh nng m t phn cng ti mc thut ton tru tng. Mt m t thit k Verilog c th bao gm s trn ln gia nhng khi (module) c mc tru tng khc nhau vi s khc nhau v mc chi tit.
Lm c Khi
Page 17

1.2.2.1 Mc chuyn mch
Nhng c im ca ngn ng ny khin n tr nn l tng trong vic m hnh ha v m phng mc chuyn mch bao gm kh nng chuyn mch mt chiu cng nh hai chiu vi nhng thng s v tr hon v lu tr in tch. Nhng tr hon mch in c th c m hnh ha nh l tr hon ng truyn, tr hon t thp ln cao hay t cao xung thp. c im lu tr in tch mc tru tng trong Verilog khin n c kh nng m t nhng mch in vi linh kin ng nh l CMOS hay MOS.
1.2.2.2 Mc cng
Nhng cng c bn vi nhng thng s c nh ngha trc s cung cp mt kh nng thun tin trong vic th hin netlist v m phng mc cng. i vi vic m phng mc cng vi mc ch chi tit v c bit, nhng linh kin cng c th c nh ngha mc hnh vi. Verilog cng cung cp nhng cng c cho vic nh ngha nhng phn t c bn vi nhng chc nng c bit. Mt h thng s logic 4 gi tr n gin (0,1,x,z) c s dng trong Verilog th hin gi tr cho tn hiu. Tuy nhien, m hnh mc logic chnh xc hn, nhng tn hiu Verilog gm 16 mc gi tr v mnh c thm vo 4 gi tr n gin trn.
1.2.2.3 tr hon gia pin n pin
Mt tin ch trong vic m t nh thi cho cc linh kin ti ng vo v ng ra cng c cung cp trong Verilog. Tin ch ny c th c dng truy vn li thng tin v nh thi trong m t tin thit k ban u. Hn na, tin ch ny cng cho php ngi vit m hnh ha tinh chnh hnh vi nh thi ca m hnh da trn hin thc phn cng.
Lm c Khi
Page 18

1.2.2.4 M t Bus
Nhng tin ch v m hnh bus v thanh ghi cng c cung cp bi Verilog. i vi nhiu cu trc bus khc nhau, Verilog h tr chc nng phn gii bus v wire vi h thng logic 4 gi tr (0,1,x,z). Vi s kt hp gia chc nng bus logic v chc nng phn gii, n cho php m hnh ha c hu ht cc loi bus. i vi vic m hnh ha thanh ghi, vic m t xung clock mc cao v nhng cu trc iu khin nh thi c th c s dng m t thanh ghi vi nhng tn hiu xung clock v tn hiu reset khc nhau.
1.2.2.5 Mc hnh vi
Nhng khi qui trnh ( procedural blocks) ca Verilog cho php m t thut ton ca nhng cu trc phn cng. Nhng cu trc ny tng t vi ngn ng lp trnh phn mm nhng c kh nng m t phn cng.
1.2.2.6 Nhng tin ch h thng
Nhng tc v h thng trong Verilog cung cp cho ngi thit k nhng cng c trong vic to ra d liu kim tra testbench, tp tin truy xut c, ghi, x l d liu, to d liu, v m hnh ha nhng phn cng chuyn dng. Nhng tin ch h thng dng cho b nh c v thit b logic lp trnh c (PLA) cung cp nhng phng php thun tin cho vic m hnh ha nhng thit b ny. Nhng tc v hin th v I/O c th c s dng kim sot tt c nhng ng vo v ng ra d liu ca ng dng v m phng. Verilog cho php vic truy xut c v ghi ngu nhin n cc tp tin.
Lm c Khi
Page 19

1.2.2.7 PLI
Cng c tng tc ngn ng lp trnh (PLI ) ca Verilog cung cp mt mi trng cho vic truy xut cu trc d liu Verilog s dng mt th vin cha cc hm ca ngn ng C.
1.2.3 Ngn ng Verilog
Ngn ng Verilog HDL p ng tt c nhng yu cu cho vic thit k v tng hp nhng h thng s. Ngn ng ny h tr vic m t cu trc phn cp ca phn cng t mc h thng n mc cng hoc n c mc cng tc chuyn mch. Verilog cng h tr mnh tt c cc mc m t vic nh thi v pht hin li. Vic nh thi v ng b m c i hi bi phn cng s c ch trng mt cch c bit. Trong Verilog, mt linh kin phn cng c m t bi mt cu trc ngn ng khai bo module. S m t mt module s m t danh sch nhng ng vo v ng ra ca linh kin cng nh nhng thanh ghi v h thng bus bn trong linh kin. Bn trong mt module, nhng php gn ng thi, gi s dng linh kin v nhng khi qui trnh c th c dng m t mt linh kin phn cng. Nhiu module c th c gi mt cch phn cp hnh thnh nhng cu trc phn cng khc nhau. Nhng phn t con ca vic m t thit k phn cp c th l nhng module, nhng linh kin c bn hoc nhng linh kin do ngi dng t nh ngha. m phng cho thit k, nhng phn t con trong cu trc phn cp ny nn c tng hp mt cch ring l. Hin nay c rt nhiu cng c v mi trng da trn Verilog cung cp kh nng chy m phng, kim tra thit k v tng hp thit k. Mi

trng m phng cung cp nhng chng trnh giao din ha cho bc thit k trc layout (front-end) v nhng cng c to dng sng v cng c hin th. Nhng cng c tng hp th da trn nn tng ca Verilog. Khi tng hp mt thit k th thit b phn cng ch nh FPGA hoc ASIC cn phi c xc nh trc. 1.3 Tng kt Trong phn ny ta c cung cp mt ci nhn tng quan v nhng c ch, nhng cng c v nhng qui trnh dng trong vic m t mt thit k t bc thit k n qu trnh hin thc phn cng. Phn ny cng ni s lc v thng tin kin thc m ta s i su trong cc phn sau. Bn cnh , n cng cung cp n ngi c lch s pht trin ca Verilog. Cng vi vic pht trin chun Verilog HDL ny l s pht trin khng ngng ca cc cng ty nghin cu, xy dng v hon thin cc cng c h tr i km, kt qu l to ra nhng cng c tt hn v nhng mi trng thit k ng b hn. 1.4 Bi tp
1. Tm hiu mi trng thit k trn FPGA ca Altera v tm hiu mi trng m phng v mi trng tng hp ca n. Hy so snh mi trng thit k ny vi mi trng m phng v tng hp m c trnh by trong phn ny. 2. Tm kim mt vi cng c kim tra thit k m c thng mi ha v lm mt bo co v nhng nh dng ng vo ca n, nhng kh nng v nhng tin ch dng cho vic kim tra thit k. 3. Tm hiu v h thng ngn ng C v tho lun v nhng cng c c sn cho ngn ng ny.
Lm c Khi
Page 21

4. Tm hiu v ngn ng m t phn cng VHDL v tho lun v nhng cng c c sn h tr cho ngn ng ny.
Chng2. Qui c v t kha

2.1 Biu tng 2.2 Khong trng Khong trng c th cha nhng k t c bit nh k t space, k t tab, k t xung dng. Nhng k t ny c th c b qua tr khi n c s dng tch bit vi nhng k t c bit mang ngha khc. Tuy nhin, nhng k t khong trng v k t tab c th c xem nh nhng k t c bit trong chui (xem trong mc 2.6). 2.3 Ch thch Ngn ng Verilog HDL c hai cch to ch thch. Ch thch mt dng c th bt u bng hai k t // v kt thc vi mt dng mi. Ch thch mt khi s bt u vi mt /* v kt thc vi */. Ch thch khi khng nn qu ri rm. Trong ch thch khi th hai k t // khng mang ngha g c bit c. 2.4 Ton t Nhng ton t nh chui k t n, kp hay gm ba k t c dng trong nhng biu thc. Trong phn tho lun v biu thc ta s trnh by v cch s dng cc ton t trong biu thc nh th no. Nhng ton t n thng xut hin bn tri ca ton hng ca chng. Nhng ton nh phn thng xut hin gia nhng ton hng ca
Lm c Khi
Page 22

chng. Ton t c iu kin thng c hai ton t k t c phn bit bi ba ton hng 2.5 S hc Hng s c m t nh l hng s nguyn hoc hng s thc. Number= decimal_number|octal_number|binary_number|hex_number|real_number Decimal_number = usigned_number | [size] decimal_base unsigned_number | [size] decimal_base x_digit{_} | [size] decimal_base z_digit{_} Octal_number = [size] octal_base octal_value Binary_number = [size] binary_base binary_value Hex_number = [size] hex_base hex_value Real_number = unsigned_number.unsigned_number | unsigned_number Exp = e | E Sign = + | Size = non_zero_unsigned_number
unsigned_number[.unsigned_number]
exp
[sign]

Non_zero_unsigned_number decimal_digit} Non_zero_decimal_digit = 1|2|3|4|5|6|7|8|9 Unsigned_number = decimal_degit{_| decimal_digit} Decimal_digit = 0|1|2|3|4|5|6|7|8|9 Binary_value = binary_digit {_| binary_digit } Binary_digit = x|X|z|Z|0|1 Octal_value = octal_digit {_| octal_digit } Octal_digit = x|X|z|Z|0|1|2|3|4|5|6|7 Hex_value = hex_digit {_|hex_digit } Hex_digit = x|X|z|Z|0|1|2|3|4|5|6|7|8|9|a|A|b|B|c|C|d|D|e|E|f|F = non_zero_decimal_digit { _|
Decimal_base = [s|S]d | [s|S]D Binary_base = [s|S]b | [s|S]B Octal_base = [s|S]o | [s|S]O Hex_base = [s|S]h | [s|S]H
Lm c Khi
Page 24
2.5.1 Hng s nguyn
Hng s nguyn c th c m t theo nh dng s decimal, hexadecimal, octal v binary. C hai dng biu din hng s nguyn. Dng th nht l mt s thp phn n gin, n c th l mt chui k t t 0 n 9 v c th bt u vi ton t n cng hoc tr. Dng th hai c m t di dng hng c s, n gm ba thnh phn mt l thnh phn m t rng hng s, mt thnh phn l k t mc n c theo sau bi mt k t ca c s tng ng (D), v thnh phn cui cng m t gi tr ca s . Thnh phn u tin, rng hng s, m t rng s bit cha hng s. N c m t nh l mt s thp phn khng du khc khng. V d, rng ca hai s hexadecimal l 8 bit bi v mi mt s hexadecimal cn 4 bit cha. Thnh phn th hai, nh dng c s, bao gm mt k t c th k t thng hoc k t hoa m t c s ca s , ta c th thm vo hoc khng thm vo pha trc n k t s (hoc S) ch rng n l mt s c du, tip tc pha trc n l mt k t mc n. Nhng c s c dng c th l d, D, h, H, o, O, b, B m t cho c s thp phn, c s thp lc phn, c s bt phn v c s nh phn mt cch tng ng. K t mc n v k t nh dng c s khng c cch nhau bi bt k khong trng no.

Thnh phn th ba, mt s khng du, bao gm nhng k t ph hp vi c s c m t trong thnh phn th hai. Thnh phn s khng du ny c th theo sau ngay thnh phn c s hoc c th theo sau thnh phn c s bi mt khong trng. Nhng k t t a n f ca s thp lc phn c th l k t thng hoc k t hoa. Nhng s thp phn n gin khng km theo rng bit v nh dng c s c th c xem nh l nhng s nguyn c du, trong khi nhng s c m t bi nh dng c s c th c xem nh nhng s nguyn c du khi thnh phn ch nh s c km thm vo hoc n s c xem nh nhng s nguyn khng du khi ch c thnh phn nh dng c s c s dng. Thnh phn ch nh s c du s khng nh hng n mu bit c m t m n ch nh hng trong qu trnh bin dch. Ton t cng hay tr ng trc hng s rng l mt ton t n cng hay tr. Hai ton t ny nu c t nm gia thnh phn nh dng c s v s l khng ng c php. Nhng s m c biu din di dng b hai. Mt s x dng biu din mt gi tr khng xc nh trong nhng hng s thp lc phn, hng s bt phn v hng s nh phn. Mt s z dng biu din mt s c gi tr tng tr cao. Mt s x c th c thit lp trn 4 bit biu din mt s thp lc phn, trn 3 bit biu din mt s bt phn, trn 1 bit biu din mt s nh phn c gi tr khng xc nh. Tng t, mt s z c th c thit lp trn 4 bit biu din mt s thp lc phn, trn 3 bit biu din mt s bt phn, trn 1 bit biu din mt s nh phn c gi tr tng tr cao.

Nu rng bit ca s khng du nh hn rng c m t trong phn m t hng s th s khng du s c thm vo bn tri n l cc s 0. Nu bt ngoi cng bn tri trong s khng du l x hoc z th mt x hoc mt z s c dng thm vo bn tri mt cch tng ng. Nu rng ca s khng du ln hn rng c m t trong phn m t hng s th s khng du s b ct xn i t bn tri. S bit dng to nn mt s khng c rng ( c th l mt s thp phn n gin hoc mt s khng m t rng bit) nn t nht l 32 bit. Nhng hng s khng du, khng rng m bit c trng s cao l khng xc nh (x) hoc tng tr cao (z) th n s c m rng ra n rng ca biu thc cha hng s. Gi tr x v z m t gi tr ca mt s c th l ch hoa hoc ch thng. Khi c s dng m t mt s trong Verilog, th k t du chm hi (?) c ngha thay th cho k t z. N cng thit lp 4 bit ln gi tr tng tr cao cho s thp lc phn, 3 bit cho s bt phn v 1 bit cho s nh phn. Du chm hi c th c dng gip vic c code d hiu hn trong trng hp gi tr tng tr cao l mt iu kin khng quan tm (dont care). Ta se tho lun r hn v vn ny khi trnh by v casez v casex. K t du chm hi cng c dng trong nhng bng trng thi do ngi dng t nh ngha. Trong mt hng s thp phn, s khng du khng bao gm nhng k t x, z hoc ? tr trng hp ch c ng mt k t ch ra rng mi bit trong hng s thp phn l x hoc z.
Lm c Khi
Page 27

K t gch di (_) c th dng bt k ni u trong mt s, ngoi tr k t u tin. K t gch di s c b qua. c tnh ny c th c dng tch mt s qu di gip vic c code d dng hn. V d1 : Hng s khng du 659 h 837FF o7460 4af h) V d 2: Hng s c rng bit 4b1011 5 D 3 3b01x nht c gi tr khng xc nh 12hx xc nh 16hz cao. V d 3: S dng du vi hng s // s thp lc phn 16 bit c gi tr tng tr // s thp lc phn 12 bit c gi tr khng // s nh phn 4 bit // s thp phn 5 bit // s nh phn 3 bit vi bit c trng s thp // s thp phn // s thp lc phn // s bt phn // khng hp l ( s thp lc phn i hi
Lm c Khi
Page 28

8 d -6 -8 d 6 4 shf tng ng vi 4h1 -4 sd15 = 0001 16sd? //tng ng 16sbz // tng ng vi (4sd15), hay (-1) = 1 // c php khng ng // s b 2 ca 6, tng ng vi (8d 6) // s c du (s b 2) 4 bit 1111, bng -1,
V d 4 T ng thm vo bn tri reg [11:0] a, b, c, d; initial begin a = h x; b= h 3x; c = h z3; d = h 0z3; end reg [84:0] e = h5; f = hx
Lm c Khi
// to ra xxx // to ra 03x // to ra zz3 // to ra 0z3
e, f, g; // to ra {82{1b0}, 3b101} // to ra {85{1hx}}

Page 29

g = hz; // to ra {85{1hz}}
V d 5: S dng du gch di trong m t s 27_195_000 16b0011_0101_0001_1111 32 h 12ab_f001 Nhng hng s m c rng bit v nhng hng s c du c rng bit l nhng s c du m rng khi n c gn n mt loi d liu l reg bt chp bn thn reg ny c du hay khng. di mc nh ca x v z ging nh di mc nh ca mt s nguyn.
2.5.2 Hng s thc
Nhng s hng s thc c th c biu din nh c m t bi chun IEEE 754-1985, mt chun IEEE cho nhng s double-precision floating point. Nhng s thc c th c m t bng mt trong hai cch, mt l theo dng thp phn ( v d, 14.72 ), hai l theo cch vit hn lm ( v d, 39e8, c ngha l 39 nhn vi 10 ). Nhng s thc c biu din vi du chm thp phn s c t nht mt k s mi bn ca du chm thp phn. V d: 1.2
8
Lm c Khi
Page 30

0.1 2394.26331 1.3E12 or 1.3e12 1.3e-2 0.1e-0 23E10 29E-2 236.123_763_e-12 ( du gch di c b qua ) Nhng dng s sau khng ng l s thc v chng khng c t nht mt k s mi bn ca du chm thp phn. .12 9. 4.E3 .2e-7
2.5.3 S o
S thc c th bin i sang s nguyn bng cch lm trn s thc n s nguyn gn nht thay v ct xn s bit ca n. Bin i khng tng minh c th thc hin khi mt s thc c gn n mt s nguyn. Nhng ci ui nn c lm trn khc 0. V d:

Hai s thc 35.7 v 35.5 u tr thnh 36 khi c bin i sang s nguyn, v s 35.2 s tr thnh 35. Bin i s thc -1.5 sang s nguyn s c -2, bin i s 1.5 sang s nguyn s c 2. 2.6 Chui Mt chui l mt dy cc k t c ro bi hai du nhy kp() v c ghi trn mt dng n. Nhng chui m c dng nh l nhng ton hng trong biu thc v trong nhng php gn c xem nh l nhng hng s nguyn khng du c biu din bi mt dy k t 8 bit ASCII, vi mt mu gi tr 8 bit ASCII biu din mt k t.
2.6.1 Khai bo bin chui
Bin chui l bin c loi d liu l reg vi rng bng vi s k t trong chui nhn vi 8. V d: lu tr mt chui 12 k t Hello world! i hi mt reg c rng 8*12, hoc 96 bit reg [8*12:1] stringvar; initial begin stringvar = hello world!; end
Lm c Khi
Page 32

2.6.2 X l chui
Chui c th c x l bng vic s dng cc ton t Verilog HDL. Gi tr m c x l bi ton t l mt dy gi tr 8 bit ASCII. V d: module string_test; reg [8*14:1] stringvar; initial begin stringvar = Hello world; $display (%s is stored as %h, stringvar, stringvar); stringvar = {stringvar, !!!}; $display (%s is stored as %h, stringvar, stringvar); end endmodule Kt qu thu c nh sau: Hello world is stored as 00000048656c6c6f20776f726c64 Hello world !!! is stored as 48656c6c6f20776f726c64212121 Khi rng mt bin ln hn rng cn thit lu mt chui gi tr c gn vo, gi tr s c dch phi, v nhng bit ngoi cng bn tri s c gn vo gi tr 0, ging nh thc hin vi gi tr khng phi l

chui. Nu mt chui ln hn bin chui m n gn vo th chui ny s dch phi v nhng k t ngoi cng bn tri s b xn b.
2.6.3 Nhng k t c bit trong chui
Mt s k t ch c s dng trong chui khi ng trc n l mt k t m u, gi l k t escape. Bng bn di lit k nhng k t ny ct bn tay phi, vi dy escape m t k t ct bn tay tri. Chui escape \n \t \\ \ \ddd K t to bi chui escape K t xung dng K t tab K t \ K t Mt k t c m t trong 1-3 k s bt phn (0 d 7) Nu t hn ba k t c s dng, k t theo sau khng th l mt k s bt phn. Vic thc thi c th dn n li nu k t c biu din ln hn 377
2.7 Tn nhn dng, t kha v tn h thng Tn nhn dng ( indentifier) c dng gn cho mt thc th (object) mt tn duy nht n c th c gi ti khi cn. Tn nhn dng c th l mt tn nhn dng n gin hoc mt tn nhn dng escaped. Mt
Lm c Khi
Page 34

tn nhn dng n gin c th l mt dy bt k gm cc k t, k s, du dollar ($), v k t gch di (_). K t u tin ca mt tn nhn dng khng th l mt k s hay $; n c th l mt k t hoc mt du gch di. Tn nhn dng s l khc nhau gia ch thng v ch hoa. V d: shiftreg_a busa_index error_condition merge_ab _bus3 n$657 y c s gii hn v di ca tn nhn dng, nhng gii hn ny t nht l 1024 k t. Nu mt tn nhn dng vt ra khi gii hn v chiu di c xc nh th li c th c thng bo ra.
2.7.1 Tn nhn dng escaped
Tn nhn dng escaped c bt u vi k t gch cho li (\) v kt thc bi khong trng ( k t khong trng, k t tab, k t xung dng). Chng cung cp cch thc chn thm nhng k t ASCII c th in c vo trong tn nhn dng ( gi tr thp phn t 33 n 126, hoc gi tr thp lc phn t 21 n 7E).

C hai k t gch cho li (\) v k t khong trng kt thc u khng c xem nh l thnh phn ca tn nhn dng. Do , mt tn nhn dng escaped \cpu3 s c x l ging nh tn nhn dng nonescaped cpu3. V d: \busa+index \-clock \***error-condition*** \net1/\net2 \{a,b} \a*(b+c)
2.7.2 T kha
T kha l nhng t nhn din c nh ngha trc v c dng nh ngha nhng cu trc ngn ng. Mt t kha trong Verilog HDL m ng trc n l mt k t escape s khng c bin dch nh l mt t kha. Tt c nhng t kha c ch c nh ngha di nh dng ch thng. Ph B s cung cp danh sch tt c nhng t kha c nh ngha.
Lm c Khi
Page 36

2.7.3 Tc v h thng v hm h thng
Du dollar ($) m u mt cu trc ngn ng s cho php pht trin nhng tc v h thng v hm h thng do ngi dng nh ngha. Nhng cu trc h thng khng phi l ngn ng thit k, m n mun ni n chc nng m phng. Mt tn theo sau du $ c bin dch nh l mt tc v h thng hoc hm h thng. C php ca mt tc v h thng/hm h thng c cho nh sau system_task_enable ::= system_task_indentifier [([expression]{, [expression]})]; system_function_call ::= system_function_indentifier [(expression{, expression})] system_function_identifier ::= $[a-zA-Z0-9_$]{[a-zA-Z0-9_$]} system_task_identifier ::= $[a-zA-Z0-9_$]{[a-zA-Z0-9_$]} Du dollar ($) trong system_function_identifier hay
system_task_identifier s khng c theo sau bi khong trng. Mt system_function_identifier hay system_task_identifier khng c thot ra. Tc v h thng/hm h thng c th c nh ngha trong ba vi tr: 1. Mt tp hp chun nhng tc v h thng v hm h thng. 2. Nhng tc v h thng v hm h thng thm vo c nh ngha dng cho PLI.
Lm c Khi
Page 37

3. Nhng tc v h thng v hm h thng thm vo c nh ngha bi thc thi phn mm.
Chng3. Loi d liu trong Verilog

3.1 Khi qut Verilog ch h tr nhng loi d liu c nh ngha trc. Nhng loi d liu ny bao gm d liu bit, mng bit, vng nh, s nguyn, s thc, s kin, v mnh ca d liu. Nhng loi ny nh ngha trong phn ln m t ca Verilog. Verilog ch yu x l trn bit v byte khi m t mch in t. Loi s thc th hu dng trong vic m t tr hon v nh thi v n cng rt hu dng trong vic m hnh ha mc cao nh l phn tch xc sut kt ni mch trong h thng v nhng gii thut x l tn hiu s. Loi d liu phn cng bao gm net v reg. Thng thng nhng loi ny c th c xem nh l dy kt ni v thanh ghi. D liu net c th c khai bo chi tit hn to ra nhng loi d liu khc nh tri-stated hay non-tri-stated v ph thuc vo cc x l nhiu kt ni s to ra nhng php and, or hoc dng gi tr trc . Phn tip theo s trnh by chi tit v nhng vn ny. 3.2 Nhng h thng gi tr Mi loi d liu c nhng mc ch c th ca n trong vic m t. Nhng h thng gi tr nh ngha nhng loi gi tr khc nhau c nh ngha trong ngn ng v bao gm c nhng thao tc gip h tr nhng h thng gi tr ny. Chng cng c nhng nh ngha hng s tng ng. Trong Verilog c nhiu gi tr khc nhau nh:
Lm c Khi
Page 38

bits and integers(32 bits), time (64 bits) bit-vectors v integers c th phi hp mt cch t do. Integers c nh ngha c 32 bit. Gi tr time c 64 bit. Thc s bit c hai loi sau: 4 gi tr trng thi (0,1,x,z); c bit nh l gi tr logic. 128 loi trng thi ( 4 trng thi v 64 mnh ( 8 cho mnh 0 v 8 cho mnh 1) Loi floating point ( s thc) Chui k t Gi tr tr hon Nhng gi tr ny c th l single, double, triplet hay n-tuple ch tr hon cnh ln, cnh xung hoc s chuyn i khc ca tn hiu. Gi tr chuyn trng thi (01) chuyn trng thi t 0 sang 1. Gi tr ny c th c trong nhng linh kin c bn do ngi dng nh ngha hoc trong nhng khi m t ( specify blocks) Nhng gi tr c iu kin/Boole true/false hoc 0/1 units ( ch dng cho timescale) femtoseconds (Fs) n seconds (s) 3.3 Khai bo loi d liu
3.3.1 Gii thiu
Nhng loi d liu khc nhau trong Verilog c khai bo bng pht biu khai bo d liu. Nhng pht biu ny xut hin trong nhng nh ngha module trc khi s dng v mt s trong chng c th c khai

bo bn trong nhng khi tun t c t tn. Thm vo , nhng loi gi tr c th phn bit vi nhng loi ca d liu khc, nhng c tnh phn cng ca wires so vi registers cng c phn bit nh l nhng khai bo net so vi khai bo reg trong Verilog. T driving ngha l iu khin c dng trong nhng m t phn cng m t cch thc mt gi tr c gn n mt phn t. Nets v regs l hai phn t d liu chnh trong Verilog. Nets c iu khin mt cch ni tip t nhng php gn ni tip ( continuous assignments) hoc t nhng phn t cu trc nh module ports, gates, transistors hoc nhng phn t c bn do ngi dng t nh ngha. Regs c iu khin mt cch cht ch t nhng khi hnh vi ( behavioural blocks). Nets thng thng c thc thi nh l wires trong phn cng v regs th c th l wires hoc phn t tm hoc flip-flops (registers). Nhng loi d liu khc nhau trong Verilog c khai bo nh l mt trong nhng loi sau: Parameter Loi ny l nhng biu thc gi tr hng s c
phn tch sau qu trnh bin dch v cho php modules c gn tham s. input , output, inout chiu v rng ca mt port. Net y l loi d liu dng cho vic kt ni hoc Nhng loi d liu ny nh ngha
wire trong phn cng vi s phn tch khc nhau. Reg y l loi d liu tru tng ging nh l mt
thanh ghi (register) v c iu khin theo hnh vi.
Lm c Khi
Page 40

Time y l loi d liu lu tr khong thi gian nh
tr hon v thi gian m phng. Integer Real Event bt tch cc. Nhng loi d liu ny tt c c th c khai bo mc module. Nhng m t khc trong Verilog vi nhng kh nng to lp mc ch bao gm nhng tc v, nhng hm v nhng khi begin-end c t tn. Nets c iu khin khng theo hnh vi (non-behaviorally) nn do n khng th c khai bo cho nhng mc ch khc. Tt c nhng loi d liu khc c th c th hin trong nhng tc v v trong nhng khi beginend.
3.3.2 V d
y l loi d liu s nguyn. y l loi d liu floating point hay s thc y l d liu ch ra rng mt c hiu c
input i1, i2; reg [63:0] data; time simtime; Dng u tin trong v d trn l mt dng khai bo input, dng th hai l mt khai bo d liu data reg 64 bit. Dng cui cng l khai bo cho mt bin c t tn l simtime.
3.3.3 C php
Data_declarations ::= parameter_declaration


|| = input_declaration || = output_declaration || = inout_declaration || = net_declaration || = reg_declaration || = time_declaration || = integer_declaration || = real_declaration || = event_declaration
3.4 Khai bo net

3.4.1 Gii thiu
Net l mt trong nhiu loi d liu trong ngn ng m t Verilog dng m t dy kt ni vt l trong mch in. Net s kt ni nhng linh kin mc cng c gi ra, nhng module c gi ra v nhng php gn ni tip. Ngn ng Verilog cho php c gi tr t mt net t bn trong nhng m t hnh vi, nhng ta khng th gn mt gi tr t mt net bn trong nhng m t hnh vi. ( Mt khi always l mt loi c bit ca khi beginend). Mt net s khng lu gi gi tr ca n. N phi c iu khin bi mt trong hai cch sau.
Lm c Khi
Page 42

Bng vic kt ni net n ng ra ca mt cng hay mt module. Bng vic gn mt gi tr n net trong mt php gn ni tip.
Nhng loi net khc nhau c nh ngha trong Verilog c m t bn di v trong nhng bng hnh 2.1 s tm tt chc nng ca chng. S phn gii l mt qui nh phn gii nhng gi tr vi nhng b iu khin sau cng c gii thch trong bng trang k.
Wire mt net vi gi tr 0,1,x v s phn gii c da trn s tng ng. Wand mt net vi gi tr 0,1,x v s phn gii ca wired and Wor Tri Tri0 mt net vi gi tr 0,1,x v s phn gii ca wired or mt net vi gi tr 0,1,x,z v s phn gii ca bus tri-state mt net vi gi tr 0,1,x,z v s phn gii ca bus tri-state v mt gi tr
mc nh l 0 khi khng c iu khin Tri1 mt net vi gi tr 0,1,x,z v s phn gii ca bus tri-state v mt gi tr
mc nh l 1 khi khng c iu khin Trior mt net vi gi tr 0,1,x,z v s phn gii ca tri-state cho gi tr z-non-z s dng hm or ca gi tr non-z Triand mt net vi gi tr 0,1,x,z v s phn gii ca tri-state cho gi tr z-non-z s dng hm and ca gi tr non-z Trireg mt net vi gi tr 0,1,x,z v s phn gii ca tri-state cng vi gi tr lu tr in tch (gi tr trc c dng phn gii gi tr mi) Supply0, supply1 (gnd v vdd)
tri/wire 0 1 X Z
0 0 X X 0
1 X 1 X 1
X X X X X
Z 0 1 X X
triand/wand 0 0 Lm c Khi 0
1 0
X 0
Z 0 Page 43

1 X Z 0 0 0 1 X 1 X X X 1 X Z
trior/wor 0 1 X Z
0 0 1 X 0
1 1 1 1 1
X X 1 X X
Z 0 1 X Z
tri1 0 1 X Z
0 0 X X 0
1 X 1 X 1
X X X X X
Z 0 1 X 1
tri0 0 1 X Z
0 0 X X 0
1 0 1 X 1
X 0 X X X
Z 0 1 X 0
trireg 0 1 X Z
0 0 1 X 0
1 1 1 1 1
X X 1 X X
Z 0 1 X P
Lm c Khi
Page 44

3.4.2 Wire
Loi d liu wire nh ngha mt loi n gin l kt ni gia hai linh kin. D liu wire dng cho nhng net m c iu khin bi mt cng linh kin n hay trong php gn ni tip (continuous assignments). Trong v d 2.3, nhng khai bo 2-wire c to ra. Khai bo u tin m t wire n ( scalar wire ) w. Khai bo th hai m t mt mng (vector) w2 vi 3 bits. Bit trng s cao nht (MSB) ca n c trng s l 2 v bit trng s thp nht (ISB) c trng s l 0. V d 2.3 wire w1; wire [2:0] w2;
3.4.3 Tri net
D liu tri th hon ton ging vi d liu wire v c php s dng v chc nng tuy nhin n khc vi d liu wire ch, d liu tri c dng cho nhng net c iu khin bi nhiu cng linh kin ng ra. Loi d liu tri (tri-state) l loi d liu c bit ca wire trong s phn gii gi tr ca net c iu khin bi nhiu linh kin iu khin c thc hin bng vic s dng nhng qui lut ca bus tri-state. Tt c cc bin m iu khin net tri phi c gi tr Z (tng tr cao), ngoi tr mt bin. Bin n ny xc nh gi tr ca net tri. Trong v d 2.6, ba bin iu khin bin out. Chng c thit lp trong module khc ch mt linh kin iu khin tch cc trong mt thi im.
Lm c Khi
Page 45

Module tri_test (out, a, b,c); Input [1:0] select, a, b, c; Output out; Tri out; Assign out = a Assign out = b; Assign out = c; Endmodule Module abc (a, b, c, select) Output a, b, c; Input [1:0] select; Always @(select) begin A = 1bz; B = 1bz; C = 1bz; Case (select) 2b00: a = 1b1;
; to kt ni cho net tri
// thit lp tt c cc bin c gi tr Z
// ch thit lp mt bin non-Z

2b01: b = 1b0; 2b10: c = 1b1; Endcase End Endmodule Module top_tri_test ( out, a, b, c, select); Input [1:0] select; Input a, b, c; Output out; Tri out; Abc (a, b, c, select); Tri_test (out, a, b, c); endmodule
3.4.4 Wired net
Wired nets bao gm nhng loi d liu wor, wand, trior v triand. Chng c dng m hnh gi tr logic ca net. Nhng wired net trn c

bng s tht khc nhau phn gii nhng xung t nu xy ra khi c nhiu cng linh kin cng iu khin mt net.
3.4.4.1 Wand/triand nets
Wand/triand l loi d liu c bit ca wire dng hm and tm gi tr kt qu khi nhiu linh kin iu khin mt net, hay ni cch khc nu c bt k ng ra linh kin iu khin no c gi tr 0 th gi tr ca net c iu khin s l 0. Trong v d 2.4, hai bin iu khin bin c. Gi tr ca out c xc nh bng hm logic and gia i1 v i2. V d 2.4 Module wand_test (out, i1, i2); Input i1, i2; Ouput out; Wand out; Assign out = i1; Assign out = i2; Endmodule Ta c th gn mt gi tr tr hon trong khai bo wand, v ta c th s dng nhng t kha n (scalar) v mng (vector) cho vic m phng.
Lm c Khi
Page 48

3.4.4.2 Wor/Trior
Loi d liu wor /trior l loi d liu c bit ca wire dng hm or tm gi tr kt qu khi nhiu linh kin iu khin mt net, hay ni cch khc nu c bt k ng ra linh kin iu khin no c gi tr 1 th gi tr ca net c iu khin s l 1. Trong v d 2.5, hai bin iu khin bin c. Gi tr ca out c xc nh bng hm logic OR gia i1 v i2. V d 2.5 module wor_test(i1, i2); input i1, i2; ouput out; wor out; assign out = i1; assign out = i2; endmodule
3.4.5 Unresolved nets 3.4.6 Trireg net
Net trireg c dng m hnh gi tr in dung lu gi trn net ca mch in, n c kh nng lu gi gi tr in tch. Mt trireg c th l mt trong hai trng thi sau:
Lm c Khi
Page 49

Trng thi c iu khin (driven state): Khi c t nht mt ng ra ca linh kin iu khin net trireg c gi tr 1, 0 hoc x th gi tr ny s c truyn n net trireg v gi tr ny iu khin gi tr ca net trireg. Trng thi lu gi in dung: Khi tt c cc ng ra ca linh kin iu khin net trireg u c gi tr tng tr cao (z) th net trireg s lu gi gi tr cui cng m n trng thi c iu khin. Gi tr tng tr cao ca cc ng ra linh kin iu khin s khng c truyn n net trireg. Do , net trireg s lun c gi tr 0 hay 1 hoc x v khng c gi tr z. mnh gi tr trn net trireg trong trng thi lu gi in dung c m t bi rng, c th l ln (large), va (medium) hay nh (small) vi gi tr mc nh l medium nu n khng c m t. Trong trng thi c iu khin, mnh ca net trireg s ph thuc vo mnh ca linh kin iu khin nh supply, strong, pull, weak m ta s tho lun sau. Nh mt m hnh Verilog nh pha di, ta s ly c gi tr kt qu ca wire trireg khi transistor iu khin n b tt. V d 2.9 module m; reg c0, c1, i1, i2; tri d0, d1, d2; trireg d; and(d0, il, i2); nmos nl (d1, d0, c0);

nmos n2(d, d1, c1); initial begin $monitor(time = %d d = %d c0=%d c1=%d d0=%d d1=%d i1=%d i2=%d, $time, d, c0, c1, d0, d1, i1, i2); #1 i1 = 1; i2 = l; c0 = l; c1 = 1; #5 c0 = 0; end endmodule
Simulation result: time = 0 time = 1

Lm c Khi
d= x c0=x c1=x d0=x d1=x i1=x i2=x d= 1 c1=1 c1=1 d0=1 d1=1 i1=1 i2=1
University of Information Technology Page 51

time = 6 d= 1 c0=0 c1=1 d0=1 d1=0 i1=1 i2=1
3.4.7 Tri0 v tri1 nets
Net tri0 v tri1 dng m hnh nhng net vi linh kin in tr ko ln hoc ko xung. Mt net tri0 s tng ng vi mt net vi c iu khin lin tc bi gi tr 0 vi mnh pull. Mt net tri1 s tng ng vi mt net vi c iu khin lin tc bi gi tr 1 vi mnh pull. Khi khng c linh kin iu khin net tri0, gi tr ca n vn l 0 vi mnh pull. Khi khng c linh kin iu khin net tri1, gi tr ca n vn l 1 vi mnh pull. Khi c nhiu linh kin iu khin net tri0 hoc tri1 th s phn gii mnh ca cc linh kin iu khin vi mnh pull ca net tri0 hoc tri1 s xc nh gi tr ca net.
3.4.8 Supply0/supply1 nets
Loi d liu supply0 v supply1 nh ngha nhng net wire c mc c nh n mc logic 0 (ni t, vss) v logic 1 ( ngun cung cp, vdd). Vic s dng supply0 v supply1 tng t nh khai bo mt wire v sau gn gi tr 0 hoc 1 ln n. Trong v d 2.7, power c ni ln ngun cung cp (lun l logic 1 c mnh ln nht) v gnd c ni n t (ground) ( lun l logic 0 c mnh nht). V d 2.8 Supply0 gnd; Supply1 power;
Lm c Khi
Page 52

3.4.9 Thi gian tr hon trn net 3.4.9.1 Gii thiu
Trong thc t bt k net no trong mch in t cng to ra tr hon trn net. Trong Verilog, tr hon c th c khai bo kt hp trong pht biu khai bo net. Nhng gi tr tr hon ny l thi gian tr hon c tnh t khi tn hiu ti ng ra ca linh kin iu khin thay i cho n khi tn hiu trn net thc s thay i. tr hon c m t bi s hoc biu thc theo sau biu tng #. Nhng gi tr ny l hng s, tham s, biu thc ca chng hay c th l nhng biu thc ng dng nhng bin s khc. tr hon c th l rise, fall, hay hold (thi gian thay i n z) v mi loi tr hon ny c th c ba gi tr - minimum, typical v maximum. S m t tr hon rise, fall, v hold c phn bit bi du phy (,) v s m t min-typ-max c phn bit bi du hai chm (:). tr hon rise bao gm thi gian tr hon khi gi tr tn hiu thay i t 0 ln 1, 0 n x v t x n 1. tr hon fall bao gm thi gian tr hon khi gi tr tn hiu thay i t 1 xung 0, 1 n x v t x n 0. tr hon hold bao gm thi gian tr hon khi gi tr tn hiu thay i t 0 ln z, 1 n z v t x n z. Khi nim tr hon ny cng c dng cho vic nh ngha tr hon ca cng, transistor, linh kin c bn do ngi dng t nh ngha v nhng m t hnh vi.
3.4.9.2 V d
Tri #5 t1, t2; Wire #(10,9,8) w1, w2; Wand #(10:8:6, 9:8:6) w3;
Lm c Khi
Page 53

Trong v d trn, dng u tin m t t1, t2 c thi gian tr hon rise, fall, hold u l 5 n v thi gian. Dng th hai, wire w1 v w2 nh ngha ba gi tr khc nhau cho ba s thay i 10 cho rise, 9 cho fall v 8 cho hold. Dng cui cng, wand w3 nh ngha gi tr min, type cho c ba s thay i rise, fall, hold.
3.4.9.3 C php khai bo tr hon cho net
delay ::= delay2 | delay 3 delay3 [,delay_value]]) delay2 ::= #delay_value | #( delay_value [,delay_value]) delay_value ::= unsigned_number | parameter_identifier | (mintypmax_expression [,mintypmax_expression] ::= #delay_value | #( delay_value [,delay_value
[,mintypmax_expression])
3.4.10 C php khai bo net
net_declaration ::= NETTYPE [expandrange] [delay] list_of_net_ identifiers; | trireg [charge_strength] [expandrange] [delay] list_of_ net_ identifiers; | NETTYPE [drive_strength] [expandrange] [delay] list_of_net_decl_assignments ;

list_of_net_ identifiers ::= net_ identifier, { net_ identifier } NETTYPE ::= : wire | tri | tri1 | supply0 | wand | triand | tri0 |
supply1 | wor | trior | trireg expandrange ::= range | scalared range | vectored range charge_strength ::= ( small ) | (medium) | (large) Trong nh ngha c php trn, mc t la chn expandrange dng nh ngha vector v n c gii thch trong mc 2.7.2. Biu thc tr hon c nh ngha trong mc 2.12. S m t mnh ca linh kin iu khin s c tho lun trong mc cp v m hnh mc cng transistor trong chng 17.
3.4.11 V d
Wire w1, w2; Tri[7:0] t1, t2;
Lm c Khi
Page 55

Trireg large trg1, trg2; Triand [63:0] #(10:5) trnd1; Trong v d trn, dng u tin vi t kha wire khai bo w1 v w2 l wire n ( scalar wire hay single bit). Dng th hai khai bo hai vector wire 8 bit t1 v t2 c loi d liu l tri. Dng k tip khai bo net c kh nng lu gi in dung trg1 v trg2 vi ln in dung l large. Dng cui cng khai bo mt net c rng 64 bit c loi d liu l triand vi tr hon l ti thiu (minimum) v trung bnh (typical). 3.5 Khai bo reg
3.5.1 Gii thiu
Khai bo reg c thc hin cho tt c nhng tn hiu m c iu khin t nhng m t hnh vi. Loi d liu reg lu gi mt gi tr c cho n khi n c gn mt gi tr mi trong mt m t tun t (khi intitial hoc always). Loi d liu reg th c mc tru tng hn so vi loi d liu net nhng n c quan h mt thit vi khi nim thanh ghi (register) vi kh nng lu gi gi tr v c th c xem nh l mt register trong phn cng. Tuy nhin, chng cng c th c xem nh l wire hoc phn t nh tm thi m khng phi l phn t thc trong phn cng, iu ny ph thuc vo vic s dng chng bn trong khi m t hnh vi.
3.5.2 V d
V d 2.2: reg r1, r2; reg [63:0] data_a, data_b, data_c;


3.5.3 C php
reg_declaration ::= reg [range] list_of_register_ identifiers; list_of_ register_ identifiers ::= register _ identifier , { register _ identifier } 3.6 Khai bo port
3.6.1 Gii thiu
Ta phi khai bo tht tng minh v chiu (input, output hay bidirectional) ca mi port xut hin trong danh sch khai bo port. Trong Verilog nh ngha ba loi port khc nhau, l input, output v inout. Loi d liu ca port c th l net hoc reg. Loai d liu reg ch c th xut hin port output. Hng s v biu thc lun nm pha di khai bo port. input: tt c port input ca mt module c khai bo vi mt pht biu input. Loi d liu mc nh ca input port l wire v c iu khin bi c php ca wire. Ta c th khai bo rng ca mt input nh mt mng (vector) ca nhng tn hiu, ging nh input b trong v d di. Nhng pht biu input c th xut hin bt c v tr no trong m t thit k nhng chng phi c khai bo trc khi chng c s dng. V d: input a; input [2:0] b; output: tt c port output ca mt module c khai bo vi mt pht biu output. Nu khng c mt loi d liu khc nh l reg, wand,

wor, hoc tri c khai bo, th output port s c loi d liu mc nh l wire v n cng c iu khin bi c php ca wire. Mt pht biu output c th xut hin bt c v tr no trong m t thit k, nhng n phi c khai bo trc khi c s dng. Ta c th khai bo rng ca mt output nh mt mng (vector) ca nhng tn hiu. Nu ta s dng loi d liu reg khai bo cho output th reg phi c cng rng vi rng ca mng (vector) ca tn hiu. V d: output a; output [2:0] b; reg [2:0] b; inout: ta c th khai bo port hai chiu (bidirectional) vi pht biu inout. Mt port inout c loi d liu l wire v c iu khin bi c php ca wire. Ta phi khai bo port inout trc khi n c s dng. V d: inout a: inout [2:0] b;
3.6.2 V d
V d 2.11: module fulladder(cOut, sum, aIn, bIn, cIn); input aIn, bIn, cIn; output cOut, sum;
Lm c Khi
Page 58

wire aIn, bIn, cIn; reg cOut, sum; Endmodule
3.6.3 C php
list_of_ports ::= ( port {,port }) port ::= [port_expression] | . port_identifier ( [port_expression] ) port_expression ::= port_reference | { port_reference ,port_reference } port_reference ::= port_identifier | port_identifier[ constant_expression ] | port_identifier [ msb_constant_expression :lsb_constant_expression ]

3.7 Khai bo mng v phn t nh mt v hai chiu.
3.7.1 Gii thiu
Verilog ch h tr khai bo mng mt v hai chiu. Nhng mng mt chiu c gi l bit-vectors v n c th l loi d liu net hoc reg. Nhng mng hai chiu c gi l nhng phn t nh v l loi d liu reg. Ta c th nh ngha rng cho tt c cc loi d liu c trnh by trong chng ny. Vic nh ngha rng cung cp mt cch to ra mt bit-vector. C php ca mt m t rng l [msb:lsb]. Nhng biu thc ca msb ( bit c trng s ln nht) v lsb (bit c trng s nh nht) phi l nhng biu thc c gi tr hng khc 0. Nhng biu thc c gi tr hng ch c th to nn bi nhng hng s, nhng tham s ca Verilog v cc ton t. Khng c gii hn trong vic nh ngha rng ti a ca mt bit-vector trong Verilog, tuy nhin vic gii hn ny c th s ph thuc vo cng c m phng, tng hp, hoc nhng cng c khc.
3.7.2 Mng net
V d 2.12: wire [63:0] system_bus v d 2.12 m t vic khai bo mt wire c rng 64 bits. V d 2.13: wire vectored [31:0] bus1; wire scalared [31:0] bus2;
Lm c Khi
Page 60

v d 2.13, ta s dng hai t kha ch dn vectored v scalared, chng u c dng khai bo multi-bit nets, tuy nhin chng khc nhau ch c cho php m t tng bit hay tng phn ca net hay khng. assign bus1 [1] = 1b1; // sai c php v s dng vic chn bit ca mt vectored net. Assign bus2 [1] = 1b1; // ng v vic chn bit ca mt scalared net l c php. Trnh bin dch chp nhn c php ca nhng cu trc m t Verilog ny, tuy nhin chng s b b qua khi mch c tng hp ra phn cng.
3.7.3 Mng thanh ghi
V d 2.13: Khai bo mng thanh ghi Reg [7:0] Areg
3.7.4 Mng phn t nh
V d 2.14: Khai bo mng phn t nh Reg Amem [7:0] ;
Lm c Khi
Page 61
reg Bmem [7:0][0:3];
Lm c Khi
Page 62
reg [7:0] Cmem [0:3];
Lm c Khi
Page 63

Reg [2:0] Dmem [0:3][0:4];
3.7.5 C php 3.7.5.1 Khai bo Vectored Net v Reg
C php ca hai loi ny c trnh by trong mc 3.4.10 (net) v 3.5.3 (reg).

3.7.5.2 Khai bo phn t nh
memory_variable ::= memory_identifier [ constant_expression : constant_expression ]

3.7.5.3 Nhng trng hp c bit ca Vectored Net
expandrange ::= range | scalared range | vectored range
Lm c Khi
Page 64

3.8 Khai bo s nguyn, thi gian, s thc, v thi gian thc
3.8.1 Gii thiu
Thm vo kh nng m hnh ha cho phn cng trong Verilog, ta c th s dng thm mt s bin d liu khc ngoi bin d liu reg. Mc d bin d liu reg c th c dng cho nhng chc nng tng qut nh m thi gian, lu gi s thay i gi tr ca net, bin d liu integer v time th cung cp s thun li v d c hiu hn trong vic m t thit k.
3.8.2 Integer 3.8.2.1 Gii thiu
Loi d liu integer l bin c chc nng tng qut c dng tnh ton s lng. N khng c xem nh l thanh ghi trong phn cng thit k. Loi d liu integer gm 32 bit v n c th c gn v s dng hon ton ging nh loi bin d liu reg. Php gn qui trnh (procedural assignment) c dng kch s thay i gi tr ca loi d liu integer. Nhng php tnh trn bin d liu integer s to ra nhng kt qu di dng b 2. V d 2.16: Integer i1, i2;
3.8.2.2 C php
Integer_declaration ::= integer list_of_register_identifiers;
Lm c Khi
Page 65

3.8.3 Time 3.8.3.1 Gii thiu
Bin d liu time c rng 64 bit v ny thng c dng lu gi gi tr output ca hm h thng $time hoc tnh ton thi gian chy m phng trong nhng trng hp m vic kim tra nh thi l bt buc hoc cho nhng mc ch d tm v pht hin li ca thit k trong qu trnh m phng. Loi d liu time c th c gn v s dng hon ton ging nh loi bin d liu reg. Php gn qui trnh (procedural assignment) c dng kch s thay i gi tr ca loi d liu time V d 2.17: time t1, t2;
3.8.3.2 C php
time_declaration ::= time list_of_register_identifiers;

3.8.4 S thc (real) v thi gian thc (realtime) 3.8.4.1 Gii thiu
Bn cnh bin d liu integer v time, Verilog cn c h tr vic s dng hng s thc v bin d liu thc (real). Ngoi tr nhng ngoi l nh trnh by pha di th bin d liu real c th c s dng tng t nh integer v time.
Lm c Khi
Page 66

Khng phi tt c cc php ton trong Verilog c th c s dng vi
nhng s thc.
Bin d liu khng co khai bo rng ca bin. Vic tnh ton c
thc hin dng chun nh dng IEEE floating point. Bin d liu c gi tr mc nh l 0.
Thi gian thc (realtime) c khai bo v s dng tng t nh s thc (real). Chng c th hon i cho nhau. V d 2.18: real float; realtime rtime;
3.8.4.2 C php
real_declaration
Lm c Khi
Page 67

::= real list_of_real_indentifiers; realtime_declaration ::= realtime list_of_realtime_identifiers; 3.9 Khai bo tham s
3.9.1 Gii thiu
Trong Verilog HDL, loi d liu tham s (parameter) khng thuc loi d liu bin (variables: reg, integer, time, real, realtime) cng nh loi d liu net. D liu tham s khng phi l bin m chng l hng s. C hai loi tham s: tham s module (module parameter), v tham s c t (specify parameter). Vic khai bo trng tn gia net, bin hay tham s l khng c php. C hai loi tham s trn u c php khai bo rng. Mc nh, parameters v specparams s c rng cha gi tr ca hng s, ngoi tr khi tham s c khai bo rng.
3.9.2 Tham s module (module parameter)
Tham s module c hai loi khai bo: parameter v localparameter.

3.9.2.1 Parameter 3.9.2.1.1 Gii thiu
Gi tr ca khai bo parameter trong mt module c th c thay i t bn ngoi module bng pht biu defparam hoc pht biu gi instance ca module . Thng thng khai bo parameter c dng m t nh thi hoc rng ca bin.

3.9.2.1.2 C php
parameter_declaration ::= parameter [ signed ] [ range ] list_of_param_assignments | parameter parameter_type list_of_param_assignments parameter_type ::= integer | real | realtime | time list_of_param_assignments ::= param_assignment { , param_assignment } param_assignment ::= parameter_identifier = constant_mintypmax_expression range ::= [ msb_constant_expression : lsb_constant_expression ]
3.9.2.1.3 V d
parameter msb = 7; // nh ngha tham s msb c gi tr hng s l 7 parameter e = 25, f = 9; // nh ngha hai hng s parameter r = 5.7; // khai bo r l mt hng s thc parameter byte_size = 8,
Lm c Khi
Page 69

byte_mask = byte_size - 1; parameter average_delay = (r + f) / 2; parameter signed [3:0] mux_selector = 0; parameter real r1 = 3.5e17; parameter p1 = 13'h7e; parameter [31:0] dec_const = 1'b1; // gi tr c i sang 32 bit parameter newconst = 3'h4; // ng l tham s ny c rng [2:0] parameter newconst = 4; // ng l tham s ny c rng ti thiu l 32 bit.
3.9.2.1.4 Thay i gi tr ca tham s khai bo parameter
Mt tham s module c th c m t loi d liu v m t rng. S tc ng ca gi tr tham s mi khi n ln gi tr ca tham s c khai bo ban u trong module vi m t loi d liu v m t rng s tun theo nhng qui lut sau:
Mt khai bo tham s m khng m t loi d liu v rng s c loi
d liu v rng mc nh ca gi tr cui cng c gn vo tham s . Mt khai bo tham s m khng m t loi d liu m ch m t rng
th rng ca tham s s khng i, cn loi d liu s l unsigned khi gi tr mi c ln. Mt khai bo tham s m ch m t loi d liu m khng m t rng
th loi d liu ca tham s s khng i, cn rng s c gi tr cha gi tr mi c ln. Lm c Khi
Page 70

Mt khai bo tham s m m t c loi d liu l c du v m t c
rng th loi d liu v rng ca tham s cng s khng i khi gi tr mi c ln.
Trong Verilog c hai cch thay i gi tr ca tham s c khai bo bi parameter : mt l pht biu defparam, vi pht biu ny n s cho php gn gi tr mi vo tham s trong module bng cch dng tn gi mt cch phn cp, hai l php gn gi tr tham s khi gi instance ca module , bng cch ny s cho php thay i gi tr tham s trong cng mt dng vi vic gi instance ca module .
3.9.2.1.4.1 Pht biu defparam
S dng pht biu defparam, gi tr tham s c th c thay i bn trong instance ca module thng qua vic s dng tn phn cp ca tham s. Tuy nhin, pht biu defparam c m t trong mt instance hoc mt dy cc instance th s khng lm thay i gi tr tham s trong nhng instance khc ca cng mt module. Biu thc bn phi ca php gn defparam l biu thc hng s ch bao gm s v nhng tham s tham chiu c khai bo trc trong cng module vi pht biu defparam. Pht biu defparam c bit hu dng v ta c th nhm tt c cc php gn thay i gi tr cc tham s ca cc module khc nhau ch trong mt module. Trong trng hp c nhiu pht biu defparam cho mt tham s duy nht th gi tr tham s s ly gi tr ca pht biu defparam sau cng.

Nu pht biu defparam ca mt tham s c khai bo trong nhiu file khc nhau th gi tr ca tham s s khng c xc nh. V d: module top; reg clk; reg [0:4] in1; reg [0:9] in2; wire [0:4] o1; wire [0:9] o2; vdff m1 (o1, in1, clk); vdff m2 (o2, in2, clk); endmodule module vdff (out, in, clk); parameter size = 1, delay = 1; input [0:size-1] in; input clk; output [0:size-1] out; reg [0:size-1] out;

always @(posedge clk) # delay out = in; endmodule module annotate; defparam top.m1.size = 5, top.m1.delay = 10, top.m2.size = 10, top.m2.delay = 20; endmodule Trong v d trn, module annotate c pht biu defparam, gi tr t pht biu ny s ln nhng gi tr tham s size v delay trong instance m1 v m2 trong module top. Hai module top v annotate u c xem nh module top-level.
3.9.2.1.4.2 Php gn gi tr tham s khi gi instance ca module
Trong Verilog c mt phng php khc dng gn gi tr n mt tham s bn trong instance ca mt module l s dng mt trong hai dng ca php gn gi tr tham s trong instance ca module. Mt l php gn theo th t danh sch tham s, hai l php gn bi tn. Hai dng php
Lm c Khi
Page 73

gn ny khng th t ln ln vi nhau m chng ch c th l mt trong hai dng cho ton b instance ca module. Vic gn gi tr tham s instance ca module theo th t danh sch tham s tng t nh vic gn gi tr tr hon cho nhng cng ca instance, cn vic gn gi tr tham s instance ca module theo tn tham s th tng t nh vic kt ni port ca module bi tn. N gn nhng gi tr tham s cho nhng instance c th m trong module ca nhng instance ny nh ngha nhng tham s trn. Mt tham s m c khai bo trong mt block, mt tc v hay mt hm ch c th khai bo li mt cch trc tip dng pht biu defparam. Tuy nhin, nu gi tr tham s ph thuc vo mt tham s th hai, th vic nh ngha li gi tr tham s th hai cng s cp nht gi tr ca tham s th nht.
3.9.2.1.4.2.1 Php gn gi tr tham s theo th t danh sch tham s
Th t ca nhng php gn trong php gn gi tr tham s theo th t danh sch tham s instance ca module s theo th t tham s lc khai bo bn trong module. N khng cn thit phai gn gi tr cho tt c cc tham s c bn trong module khi dng phng php ny. Tuy nhin, ta khng th nhy qua mt tham s. Do , gn nhng gi tr cho mt phn nhng tham s trong tt c cc tham s khai bo trong module th nhng php gn thay th gi tr ca mt phn nhng tham s s ng trc nhng khai bo ca nhng tham s cn li. Mt phng php khc l phi gn gi tr cho tt c cc tham s nhng dng gi tr mc nh (cng c gi tr nh c gn trong khai bo tham s trong nh ngha module) cho cc tham s m khng cn c gi tr mi.

V d: Xt v d sau, trong v d ny nhng tham s bn trong instance ca nhng module mod_a, mod_c, v mod_d c thay i trong khi gi instance. module tb1; wire [9:0] out_a, out_d; wire [4:0] out_b, out_c; reg [9:0] in_a, in_d; reg [4:0] in_b, in_c; reg clk; // To testbench clock v stimulus. // Bn instance ca module vdff vi php gn gi tr tham s theo th t danh sch tham s // mod_a c hai gi tr tham s mi size=10 v delay=15 // mod_b c gi tr tham s mc nh l (size=5, delay=1) // mod_c c mt gi tr tham s mc nh l size=5 v mt gi tr mi l delay=12 // thay i gi tr ca tham s delay, ta cng cn phi m t gi tr mc nh ca tham s size

// mod_d c mt gi tr tham s mi l size=10, v gi tr tham s delay vn gi gi tr mc nh ca n. vdff #(10,15) mod_a (.out(out_a), .in(in_a), .clk(clk)); vdff mod_b (.out(out_b), .in(in_b), .clk(clk)); vdff #( 5,12) mod_c (.out(out_c), .in(in_c), .clk(clk)); vdff #(10) mod_d (.out(out_d), .in(in_d), .clk(clk)); endmodule module vdff (out, in, clk); parameter size=5, delay=1; output [size-1:0] out; input [size-1:0] in; input clk; reg [size-1:0] out; always @(posedge clk) #delay out = in; endmodule Nhng gi tr ca tham s cc b khng th b ln, do chng khng c xem nh l mt phn th t ca danh sch cho php gn gi tr

tham s. Trong v d ny, addr_width s c gn gi tr 12, v data_width s c gn gi tr 16. Mem_size s khng c gn gi tr mt cch tng minh do th t danh sch, nhng n s c gi tr 4096 do biu thc khai bo ca n. module my_mem (addr, data); parameter addr_width = 16; localparam mem_size = 1 << addr_width; parameter data_width = 8; ... endmodule module top; ... my_mem #(12, 16) m(addr,data); endmodule
3.9.2.1.4.2.2 Php gn gi tr tham s bi tn
Php gn gi tr tham s bi tn bao gm tn tng minh ca tham s v gi tr mi ca n. Tn ca tham s s l tn c m t trong instance ca module.
Lm c Khi
Page 77

Ta khng cn thit gn nhng gi tr n tt c cc tham s bn trong module khi s dng phng php ny. Ch nhng tham s no m c gn gi tr mi th mi cn c ch ra. Biu thc tham s c th l mt la chn vic gi instance ca module c th ghi li vic hin din ca mt tham s m khng cn bt k mt php gn n n. Nhng du ng m ngoc c i hi, v trong trng hp ny tham s s gi gi tr mc nh ca n. Khi mt tham s c gn mt gi tr, th mt php gn khc n tn tham s ny l khng c php. Xt v d sau, trong v d ny c nhng tham s ca mod_a v ch mt tham s ca mod_c v mod_d b thay i trong khi gi instance ca module. module tb2; wire [9:0] out_a, out_d; wire [4:0] out_b, out_c; reg [9:0] in_a, in_d; reg [4:0] in_b, in_c; reg clk; // Code to testbench clock & stimulus ... // Bn instance ca moduel vdff vi gi tr tham s c gn bi tn // mod_a c gi tr tham s mi l size=10 v delay=15

// mod_b c gi tr tham s mc nh l (size=5, delay=1) // mod_c c mt gi tr tham s mc nh l size=5 v c mt gi tr tham s mi l delay=12 // mod_d c mt gi tr tham s mi l size=10. // cn tham s delay vn gi gi tr mc nh vdff #(.size(10),.delay(15)) mod_a (.out(out_a),.in(in_a),.clk(clk)); vdff mod_b (.out(out_b),.in(in_b),.clk(clk)); vdff #(.delay(12)) mod_c (.out(out_c),.in(in_c),.clk(clk)); vdff #(.delay( ),.size(10) ) mod_d (.out(out_d),.in(in_d),.clk(clk)); endmodule module vdff (out, in, clk); parameter size=5, delay=1; output [size-1:0] out; input [size-1:0] in; input clk; reg [size-1:0] out; always @(posedge clk) #delay out = in;

endmodule N th hp l khi gi nhng instance ca module dng nhng loi nh ngha li tham s trong cng module top-level. Xt v d sau, trong v d ny nhng tham s ca mod_a b thay i bng cch dng vic nh ngha li tham s theo th t danh sch v tham s th hai ca mod_c c thay i bng cch dng vic nh ngha li tham s bng tn trong khi gi instance ca module. module tb3; // s pha trn gia instance c khai bo tham s theo th t v instance c khai bo tham s theo tn th hp l vdff #(10, 15) mod_a (.out(out_a), .in(in_a), .clk(clk)); vdff mod_b (.out(out_b), .in(in_b), .clk(clk)); vdff #(.delay(12)) mod_c (.out(out_c), .in(in_c), .clk(clk)); endmodule N s khng hp l khi gi instace ca bt k module no dng ln ln nhng php gn li gi tr tham s bng th t danh sch tham s v tn ging nh trong php gi instance ca module mod_a di. // instance mod_a khng hp l do c s pha trn gia cc php gn tham s vdff #(10, .delay(15)) mod_a (.out(out_a), .in(in_a), .clk(clk));
3.9.2.1.5 S ph thuc tham s Lm c Khi University of Information Technology Page 80

Mt tham s (v d, memory_size) c th c nh ngha vi mt biu thc cha nhng tham s khc (v d, word_size). Tuy nhin, vic gn gi tr tham s, c th l bng pht biu defparam hoc trong pht biu gi instance ca module, s thay th mt cch hiu qu vic nh ngha tham s vi mt biu thc mi. Bi v memory_size ph thuc vo gi tr ca word_size, bt k c s thay i no ca word_size s lm thay i gi tr ca memory_size. V d, trong khai bo tham s sau, mt gi tr mi cp nht ca word_size, c th l bi pht biu defparam hoc pht biu gi instance ca module m trong module ny nh ngha nhng tham s trn, th gi tr ca memory_size s c t ng c nht. Nu memory_size c cp nht bi pht biu defparam hay mt pht biu gi instance th n s ly gi tr m khng cn quan tm n gi tr ca word_size. parameter word_size = 32, memory_size = word_size * 4096;
3.9.3 Tham s cc b (localparam) 3.9.3.1 Gii thiu
Trong Verilog, tham s cc b (localparam) ging tng t vi tham s (parameter) ngoi tr l n khng th c gn li gi tr bi pht biu defparam hoc php gn gi tr tham s khi gi instance ca module. Nhng tham s cc b (localparam) c th c gn bi nhng biu thc hng s cha nhng tham s (parameter) m nhng tham s (parameter) ny c th c gn li gi tr bi pht biu defparam hoc php gn gi tr tham s khi gi instance ca module.

Vic chn bit hay mt phn ca tham s cc b m loi d liu ca n khng phi l real th c php.
3.9.3.2 C php
local_parameter_declaration ::= localparam [ signed ] [ range ] list_of_param_assignments | localparam parameter_type list_of_param_assignments parameter_type ::= integer | real | realtime | time list_of_param_assignments ::= param_assignment { , param_assignment } param_assignment ::= parameter_identifier = constant_mintypmax_expression range ::= [ msb_constant_expression : lsb_constant_expression ]
3.9.4 c t tham s (specify parameter) 3.9.4.1 Gii thiu
T kha specparam khai bo n l mt loi c bit ca tham s (parameter) ch dng cho mc ch cung cp gi tr nh thi (timing) v gi tr tr hon (delay), nhng n c th xut hin trong bt k biu thc no

m biu thc khng c gn n mt tham s (parameter) v biu thc cng khng phi l phn m t rng trong mt khai bo. Nhng tham s c t ( specparams) c php khai bo bn trong khi c t (specify block) hoc bn trong mt module chnh. Mt tham s c t (specify parameter) khai bo bn ngoi mt khi c t (specify block) th cn c khai bo trc khi n c s dng. Gi tr m c gn n mt tham s c t c th l mt biu thc hng s bt k. Mt tham s c t c th c dng nh l phn ca mt biu thc hng s cho mt khai bo tham s c t k tip. Khng ging nh mt tham s module (module parameter), mt tham s c t khng th c gn li gi tr t bn trong ngn ng Verilog, nhng n c th c gn li gi tr thng qua tp tin d liu SDF ( Standard Delay Format). Nhng tham s c t (specify parameter) v tham s module (module parameter) th khng th thay th cho nhau. Ngoi ra, tham s module (module parameter) khng th c gn bi mt biu thc hng s m c cha tham s c t ( specify parameter). Bng 4.7 tm tt s khc nhau gia hai loi khai bo tham s. Specparams (tham s c t) S dng t kha specparam Parameters ( tham s module) S dng t kha parameter
Cn c khai bo bn trong mt Cn c khai bo bn ngoi nhng module hoc mt khi c t ( khi c t ( specify block) specify block) C th c dng bn trong mt Khng th c dng bn trong
Lm c Khi
Page 83

module hoc mt khi c t ( nhng khi c t (specify block). specify block) C th c gn bi tham s c t Khng th c gn bi
(specparam) v tham s module specparams. (parameter). S dng tp tin d liu SDF gn Dng pht biu defparam hoc php gi tr cho tham s c t. gn gi tr tham s cho instance ca module gn gi tr cho tham s.
Mt tham s c t (specify parameter) c th c m t rng. rng ca nhng tham s c t cn tun theo nhng qui lut sau:
Mt khai bo tham s c t m khng c m t rng th mc nh s l rng ca gi tr cui cng c gn n n, sau khi c bt k gi tr no gn ln n. Mt khai bo tham s c t m c m t rng th rng ca n s theo rng khai bo. rng s khng b nh hng bi bt k gi tr no c gn ln n.
Vic chn bit hay mt phn ca tham s cc b m loi d liu ca n khng phi l real th c php. V d: specify specparam tRise_clk_q = 150, tFall_clk_q = 200;

specparam tRise_control = 40, tFall_control = 50; endspecify Nhng dng gia nhng t kha specify v endspecify l khai bo bn tham s c t. Dng u tin khai bo hai tham s c t tRise_clk_q v tFall_clk_q vi gi tr tng ng l 150 v 200. Dng th hai khai bo hai tham s c t tRise_control v tFall_control vi gi tr tng ng l 40 v 50. V d: module RAM16GEN (output [7:0] DOUT, input [7:0] DIN, input [5:0] ADR, input WE, CE); specparam dhold = 1.0; specparam ddly = 1.0; parameter width = 1; parameter regsize = dhold + 1.0; // Khng hp l - khng th gn tham s c t (specparam) n mt tham s (parameter) endmodule
END
Lm c Khi
Page 86

Verilog HDL

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Verilog HDL

Uploaded by

Copyright:

Available Formats

Gio trnh Verilog HDL

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

Verilog Hardware Description Language

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

1.1.5 M phng sau khi tng hp thit k

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

1.2.2 Nhng c tnh ca Verilog

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Chng2. Qui c v t kha

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

2.5.1 Hng s nguyn

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

// to ra xxx // to ra 03x // to ra zz3 // to ra 0z3

e, f, g; // to ra {82{1b0}, 3b101} // to ra {85{1hx}}

University of Information Technology

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

Verilog Hardware Description Language

University of Information Technology

Verilog Hardware Description Language

University of Information Technology