n tt nghip

Trang 42

Chng 3: KIT TMS320C6713

Hnh 3.1: Kt TMS320C6713 DSK

3.1

Gii thiu TMS320C6713

3.1.1 Tng quan v TMS320C6713 Kit DSK l mt h thng DSP hon chnh. Board DSK bao gm b x l s du chm ng C6713 v b Codec 32-bit stereo TLV320AIC23 (gi tt l AIC23) cho vic xut nhp tn hiu. B codec on board AIC23 s dng k thut sigma-delta bin i A/D v D/A. N c kt ni vi mt ng h h thng 12 MHz. Tn s ly mu c th thay i t 8 n 96 Khz. B x l Kt TMS320C6713 ca hng Texas Instrument da trn kin trc VLIW (very-long-instruction-word), ph hp cho cc gii thut nng v tnh ton s. B nh chng trnh ni c t chc mi chu k c th np 8 lnh, mi lnh di 32 bt. Cc b x l C67xx (nh C6701,C6711 v C6713) thuc v h cc b x l C6x du chm ng, trong khi C62xx v C64xx thuc v h cc b x l C6x du chm tnh. C6713 c th x l c du chm tnh v du chm ng. Cc yu cu phn cng cao hn cng c th c p ng vi cc khe cm m rng. S khi ca kt TMS320C6713 hnh 3.2 bn di.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 43

Hnh 3.2: S khi C6713 DSK

Thnh phn chnh trn Kit Trung tm l chp x l tn hiu TMS320C6713, chy xung nhp 225Khz, TMS320C6713 nm trong dng chp TMS320C6x ca TI, y l dng vi x l tc cao, s dng kin trc c bit p ng cc tc v x l tn hiu. Da trn kin trc VLIW, TMS320C6713 c kh nng x l cc s thc du chm ng v c coi l dng chp x l tn hiu mnh nht ca TI hin nay. B bin i tn hiu AIC23. Bn cng kt ni tn hiu vo ra: MIC IN (Microphone input), LINE IN (line input), LINE OUT (line output) v HEADPHONE (headphone output). Trng thi ca 4 led v Dip Switch trn DSK c th cu hnh iu khin theo nhu cu ca ngi s dng. Cng USB giao tip vi PC. Trn cng cng c thit k b JTAG nhng gip ta c th sa li chng trnh chy trn chip m khng cn ni JTAG ngoi. Cng PRW (+5V) cung cp ngun cho board. Cng ny cung cp in p +1.26V cho li chp C6713 v +3.3V nui b nh v cc thit b ngoi vi khc. B nh: +16MB +512 KB b nh Flash. B nh trong: trn mch c 264kB b nh trong (4 KB b m d liu L1D; 4KB b m chng trnh L1P; 256 Kb b nh L2). Di y l s phn vng v a ch b nh ca kt (hnh 3.3) B nh ngoi: kt DSP c sn 16Mb b nh ngoi (SDRAM (Synchronous Dynamic RAM)) + 512 KB b nh Flash. Ngoi ra kt c th b sung b nh ngoi qua khe cm m rng. Vi chiu di thanh ghi 32 bt, kt c th qun l 4GB b nh ngoi.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 44

C th nhn thy rng, tuy hot ng vi xung nhp khng cao nhng kt TMS320C6713 c dung lng b nh lu tr ln, kh nng x l du chm ng, c sn JTAG nhng thun tin cho debug v tnh nng x l thi gian thc RTDX, hon ton thch hp cho nhiu ng dng thc t.

Hnh 3.3: S phn vng v a ch b nh

3.1.2 Khi qut chc nng

Cc thit b ngoi vi trn board TMS320C6713 DSK giao tip vi nhau thng qua b nh ngoi EMIF (External Memory InterFace). SDRAM, Flash v CPLD c kt ni vi nhau thng qua bus trn board. Tn hiu t b nh ngoi EMIF c kt ni thng qua cc card m rng, s dng trn nhng khe cm m rng trn bo. Giao tip x l tn hiu m thanh tng t thng qua chp AIC23 Codec v jack audio 3.5mm (microphone input, line input, line output, v headphone output). C th s dng microphone hoc line input ly tn hiu u vo. Ng ra tng t c ly ra qua ng ra lineout, v headphone. McBSP0 c s dng gi dng lnh ti giao din iu khin Codec, v McBSP1 c s dng cho vic m cc d liu m thanh. McBSP0 v McBSP1 c th ti kt ni ti cc kt ni m rng trong phn mm. Mt thit b logic lp trnh CPLD s dng thc hin x l logic v gn kt cc thnh phn khc trn board. CPLD c thanh ghi c s dng cho x l logic.
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 45

Trn DSK gm 4 n LED v 4 cng tt DIP cung cp ngi dng thao tc tc ng qua li. C hai u c thc hin bi c v ghi vo thanh ghi CPLD. S dng ngun cung cp +5V, trn bo c mch iu chnh in p cung cp in cp 1,26 V cho li DSP v 3.3 V cho cng I/O. Code Composer giao tip vi DSK thng qua mt JTAG gi lp vi giao din cng USB. Cc DSK cng c th s dng vi m phng bn ngoi thng qua kt ni JTAG bn ngoi.

3.1.3 B nh S khi b nh C6713

Hnh 3.4: S khi C6713

DSK s dng bn vng b nh ngoi: CE0: SDRAM CE1: B nh Flash v cng I/O (switch, leds) CE2 v CE3: chn kt ni ti daughter card H C67xx c khng gian a ch byte nh ln. M ngun chng trnh v d liu c th c cha bt c ni no trn khng gian a ch vng nh. rng a ch 32 bt. Bn sau m t vng a ch b x l 6713. Theo mc nh, b nh trong nm u vng a ch. EMIF c 4 vng a ch ring bit gi l chip cho php c khng gian (CE0 CE3). SDRAM chim gi CE0 trong khi Flash v CPLD l CE1, CE2 v CE3 dnh cho cc card con (Daughter Card).

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 46

Hnh 3.5: Bn vng nh

External SDRAM
SDRAM (Synchronous DRAM) DSK s dng mt 64 megabit ng b DRAM (SDRAM) trn EMIF 32-bit. SDRAM l nh x bt u t CE0 (a ch 0x80000000), tng b nh c sn l 16MB. B iu khin SDRAM tch hp l mt phn ca EMIF v phi c cu hnh trong phn mm cho hot ng tt. Mt s cc thng s quan trng nht c lit k di y: Bng 3.1 cc thng s ca SDRAM Thng s Gi tr CE0 Memory Type 32-bit wide SDRAM Num. Banks 4 Num. Row Address Lines 12 Num. Column Address Lines 8 Chu k lm mi trng thi 1400 Mt trong nhng thng s SDRAM chnh l chu k refresh. SDRAMs phi c refresh lin tc hoc n s tr nn bt n v mt ni dung. Cc DRAM c s dng trn DSK C6713 phi refresh mt dng mi 15,6 micro giy. Cc cu hnh c hin th trn s dng mt gi tr ca 1400 (0x578 (hex)). Ch nh chu k refresh (1400 x 11.11ns, chu k clock 90MHz). Tc Refresh = 64 ms / 4096 (64ms t ng refresh 4K)

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 47

External Flash
DSK c 128K Flash B nh khng linh ng, c lp trnh li S dng lu tr d liu ban u Lu tr cc hng s c s dng trong qu trnh thc thi

Hnh 3.6: Kt ni gia EMIF vi Flash Flash l mt loi b nh m khng b mt ni dung khi ngun in c tt. Khi truy xut ging nh truy xut b nh ch c ROM. Flash c th b xa trong tng khi ln l sectors hay pages. Mi khi c xa thng qua chui lnh c bit trong lp trnh. Cc khi xa c th ghi ni dung tr li. DSK mc nh l thm hai chu k vit cho tt c nhng b nh khng ng b. B nh Flash DSK l b nh khng bay hi, mc d cho php ghi li ni dung, nhng khng th c ghi mt cch d dng, m phi m kha (unlock) bi mt s lnh c bit. Write 0xAA to 0x5555 Write 0x55 to 0x2AAA Write 0xA0 to 0x5555 Ghi d liu mi ti 128 byte sector. My tnh da vo cng c c sn ghi d liu ti flash. Chc nng BSL cho php vit ti Flash.

3.1.4 Switch cu hnh khi ng

DSK c 4 Switch cu hnh cho php ngi s dng iu khin trng thi hot ng. Khi Switch cu hnh c nhn SW3 gn Switch Reset. SW1 dng iu khin endianness ca DSP, SW2, SW3 cu hnh ch boot khi bt u thc thi DSP. SW4 iu khin ghp knh trn chip ca HPI v tn hiu McASP a ra kt ni m rng ti HPI m rng.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 48

Bng 3.2: Bng cu hnh cc Switch

3.1.5 Ngun cung cp

DSK s dng tn hiu in p +5V c cp bi ngun cung cp thng qua u cm J5. Tn hiu ny c i qua b iu chnh in p bn trong board a ra tn hiu in p +1.26V v +3.3V. in p +1.26V s dng cho cc li DSP v in p +3.3V s dng cho cc cng I/O v cc chp khc trn board. u cm ngun l loi jack cm 2.5mm. kim tra mc in p, ta c th kim tra ti cc im JP1, JP2 v JP4. Tt c dng I/O u i qua JP2, v dng in li i qua JP1. Tt c dng in ca h thng i qua JP4. u J6 c dng in p +12V v -12V, cung cp ngun cho cc Daughter Card.

3.2 Chc nng tng thnh phn trn bo TMS320C6713 DSK

3.2.1 TMS320C6713 TMS320C6713 DSP hot ng tn s 225MHz. Li ca DSP c thit k thc thi cc php ton du chm ng. Bn ngoi li, C6713 tch hp mt s ti nguyn trn chip ci tin chc nng v ti thiu ha phn cng pht trin phc tp. VLIW Core l kin trc ca b x l cho php thc hin nhiu lnh trn 1 xung clock (8 lnh trn 6713 DSP ). Kin trc VLIW c th t c mc x l cao nhng n t gnh nng nhiu hn vo trnh bin dch sp xp thc thi cng lc lnh. 192Kbytes b nh ni B nh trong tc cao cho s thc thi ti a. 64Kbytes L2 cache/RAM 4 khi 16Kbytes ca RAM ni c th c cu hnh nh RAM hoc cache. 4Kb Program/Data caches cache ring r cho m lnh chng trnh v d liu. On-chip PLL pht ra xung clock b x l t ngun xung clock tham chiu bn ngoi. 2 timers . EDMA controller b iu khin DMA nng cao cho php truyn ti d liu tc cao m khng cn s can thip t DSP. 2 McBSPs cng ni tip m nhiu knh. Mi McBSP c th c dng cho vic truyn ti d liu ni tip tc cao vi thit b bn ngoi hoc lp trnh li nh l mc ch I/O chung. McBSP1 c s dng truyn v nhn
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 49

d liu m thanh t AIC23. McBSP0 c dng iu khin codec thng qua ng vo ni tip. Thanh ghi MISC trong CPLD c s dng chn khi no McBSP0 v McBSP1 c ni vi AIC23 hoc nhng kt ni m rng. 2 McASPs Cng m thanh ni tip a knh. S dng cho nhiu knh v nhng ng dng m thanh chuyn nghip. Khng s dng trn DSK, nhng mang li nhng kt ni m rng. 2 giao din I2C Bus I2C l bus ni tip c th h tr mt vi thit b chun trn bus. EMIF giao din b nh m rng. Mt bus 32 bit trn b nh m rng v thit b khc c th c kt ni. N bao gm tnh nng nh trng thi ch bn trong v iu khin SDRAM. Giao din EMIF bao gm c ng b vo d b b nh. DSP c thit k thc thi ti xung nhp 225MHz vi 50MHz t b dao ng bn ngoi. thc thi bnh thng trn 6713 DSK, vng kha pha bn trong c cu hnh vi b nhn ca 9 v b chia ca 2 t c 225Mhz t ngun tham chiu 50MHz. Kt ni gia AIC23 vi McBSP0, McBSP1

Hnh 3.7: Kt ni AIC23 vi McBSP

Cc thit b TMS320C67x cha ng cc thit b ngoi vi giao tip vi b nh off-chip, ng b x l, b x l gia my ch v thit b ni tip. B x l C6713 gm c:
Enhanced DMA (EDMA) Truy cp b nh tng cng trc tip (EDMA_enhaced direct memory access) iu khin truyn ti d liu gia cc vng trong bng b nh khng qua s can thip ca CPU. EDMA cung cp truyn ti d liu ti/t b nh ni, thit b ngoi vi ni, thit b bn ngoi trong bi cnh hot ng ca CPU. EDMA c 16 knh c lp trnh c lp cho php thao tc 16 hot ng khc nhau.
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 50

EDMA c th c v vit d liu c bn t vng ngun hoc vng ch tng ng trong b nh. EDMA cng cung cp vic truyn ti khi hoc truyn ti khung. Mi knh EDMA s lng lp trnh c lp ca cc yu t d liu trn 1 khung v s lng khung cho mi khi. EDMA c cc tnh nng sau: DMA hot ng c lp vi CPU. Thng lng cao: Cc yu t c th c truyn ti cng vi tc xung clock ca CPU. 16 knh: EDMA c th gi vic theo di, kim tra cc ng cnh ca vic truyn ti 16 knh. Tch hot ng: Mt knh n c th s dng truyn v nhn, truyn t/ti thit b ngoi vi v b nh. Lp trnh u tin: Mi knh c cc u tin lp trnh c lp so vi CPU. Mi knh a ch thanh ghi ngun v ch c th c cc ch s cu hnh cho truyn ti c v ghi. a ch c th khng i, tng, gim hoc c iu chnh bi gi tr lp trnh. Lp trnh thay i rng truyn ti: Mi knh c th c cu hnh c lp truyn ti byte, 16 bt word, 32 bt word. Xc thc: Mi ln truyn ti hon tt, EDMA s t ng qu trnh khi to chnh n cho ln truyn ti k tip. Lin kt: Mi knh EDMA c th c lin kt ti truyn ti tip theo sau khi truyn ti kt ti hon tt. S kin ng b: Mi knh c bt u bi mt s kin. Chuyn giao c th l ng b phn t hoc khung. EDMA gi tt c d liu truyn gia b nh m L2/ b nh iu khin, v thit b ngoi ngoi vi. EDMA c th di chuyn d liu t v ti bt k a ch vng nh no bao gm c b nh ni (L2 SDRAM), thit b ngoi vi, v b nh ngoi. B iu khin RAM bao gm s kin v x l ngt, s kin gii m, tham s RAM, v a ch phn cng. EDMA c 16 knh c lp v chng c th c ginh u tin. Sau khi s kin xut hin, n truyn ti bng c c t bng RAM (PaRAM). EDMA c th truyn ti 8 bit bytes, 16 bt 1/2words, hoc 32 bt words. Sau khi truyn ti, ngun v/hoc ch v yu t a ch c th ging nhau, cng tng, gim mt yu t, hoc tng gim bi gi tr trong thanh ghi ELECXD cho knh. Sau khi chng trnh truyn ti kt thc, EDMA c th tip tc cho truyn d liu bi link bi lin kt chng trnh ti knh khc. EDMA C6713 h tr 16 knh EDMA. o Thanh ghi x l s kin +ER (Event Register): khi s kin n c pht hin, bt n c ci t vo trong EER. +EER (Event Enable Register): bt n c thit lp 1 cho php x l s kin. Gi tr 0 th khng cho php.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 51

+ECR (Event Clear Register): nu mt s kin c cho php trong EER v c a ln ER, bt ER t ng xa v 0 khi EDMA x l truyn ti s kin. Nu s kin b v hiu ha, CPU c th xa bt c s kin trong ER. +ESR (Event Det Register): Gi tr 1 chp nhn thit lp s kin, cho php CPU yu cu s dng cng c g li.

Host Port Interface (HPI)

Giao din Host-Port (HPI_Host-Port Interface) l port song song 16 bt thng qua b x l ch c th truy xut trc tip khng gian b nh CPU. Chc nng thit b my ch nh qun l giao din, tng ln d dng ca vic truy cp. My ch v CPU c th trao i thng tin thng qua b nh trong v ngoi. My ch c th truy cp vo b nh nh x thit b ngoi vi. HPI c kt ni ti b nh ni thng qua b thanh ghi. Hoc my ch hoc CPU c th s dng thanh ghi iu khin HPI (HPIC) cu hnh giao din. My ch c th truy cp thanh ghi a ch my ch (HPIA) v thanh ghi d liu ch (HPID) dng truy cp ti khng gian b nh ni ca thit b.

Two Multichannel Audio Serial Ports (McASPs)

B x l TMS320C6713 bao gm 2 cng m thanh ni tip a knh (McASP). M un giao din McASP h tr mt truyn mt nhn. Mi McASP c 8 chn d liu ni tip, chng c th c nh r v tr ring l ti bt k ca 2 vng. Cng ni tip h tr ghp knh phn chia thi gian trn mi chn t 232 khe thi gian. D liu ni tip trn mi vng c th c truyn ti v nhn trn nhiu chn d liu ni tip ng thi trn nh dng I2S (Inter-IC Sound). Truyn ti McASP c th c lp trnh ti nhiu ng ra S/PDIF IEC60958, AES-3, CP-430 c m ha d liu nhiu knh ng thi, vi b nh RAM thc hin y cc d liu ngi dng v cc trng trng thi knh. McASP cng cung cp tnh nng kim tra li v khi phc. McASP gm McASP0 v McASP1 2 m un c lp truyn v nhn. o Tnh nng McASP: Cho php truyn v nhn 2 tc khc nhau Lp trnh to ra ng h v khung ng b Dng TDM t 2 n 32 v 383 slots time H tr kch c slot time ca 8,12,16,20,24,28 v 32 bt nh dng d liu cho cc thao tc bt Chn d liu ni tip ti 16 chn H tr giao din truyn ti m thanh s Khe 384 TDM vi giao din m thanh s bn ngoi (DIR) M rng kim tra li v phc hi
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 52

Two Multichannel Buered Serial Ports (McBSPs)

C th to s dch chuyn xung clock v ng b khung tn hiu bn trong hoc s dng tn hiu bn ngoi. C th truyn hoc nhn 8, 12, 16, 20, 24, hoc 32 bt word. Thanh ghi d liu m i cho php lin tc dng d liu. C truyn truyn v nhn ngt ti CPU hoc s kin ti EDMA. Chn a knh ti 32 phn t t 128 phn t khung TDMA Giao din trc tip ti cc codec chun cng nghip. S khi McBSP.

Hnh 3.8: S khi McBSP DX/DR : Truyn/nhn d liu ni tip FSX/FSR: Truyn /Nhn ng b khung CLKX/CLKR: Truyn/Nhn xung dch chuyn ni tip XINT/RINT: Truyn/nhn ngt ti CPU XEVT/REVTL: Truyn/nhn ngt ti DMA CLKS: Xung ngoi. Truyn d liu: p ng truyn ti d liu ni tip ti ghi vo DXR. Ni dung ca DXR c sao chp ti thanh ghi XRS. Bt u truyn ti ngay khi ng b khung (FSX) c tm thy. Mt bt ca d liu c truyn ti c dch chuyn ra khi SXR trong 1 xung truyn CLKX. D liu mi c th c ghi ti DXR s dng CPU hoc DMA.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 53

Hnh 3.9: Qu trnh truyn d liu Thanh ghi iu khin port ni tip (018C0008H)
XINTM XEMPTY XRDY XRST RJUST RINTM RFULL RRDY RRST

Thao tc truyn ni tip: CPU hoc EDMA ghi mt t vo trong thanh ghi truyn d liu (DXR_Data Transmit Register). C XRDY c xa bt k khi no d liu c vit ti DXR. Sau khi mt t (32 bt) c dch ra ngoi thanh ghi XSR, s c truyn ti song song vo trong XSR. C XRDY s c thit lp khi xut hin truyn ti. Truyn ti cng ni tip gi mt yu cu ngt (XINT) ti CPU khi XRDY chuyn t 0 ln 1 nu XINTM=00b vo trong SPCR. N gi tn hiu XEVT (Transmit Event Notice) ti EDMA. Nhn d liu: D liu nhn trn chn DR c dch vo trong thanh ghi RSR (Receive Shift Register) trong mi xung clock nhn (CLKR). D liu trong RSR c sao chp ti Recevice Buffer Register (RBR) v sau ti DRR (Data Receive Register). DRR c th c c bi mt CPU hoc DMA. S khi qu trnh nhn d liu:

Hnh 3.10: Qu trnh nhn d liu

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 54

Thao tc nhn ni tip: Bt RX c dch vo trong RSR (Receive Shift Register). Khi tt c c bt c nhn, 32 bt RSR c truyn song song ti thanh ghi m nhn (RBR-Receive Buffer Register) nu n rng. RBR sao chp ti DRR (Data Receive Register) nu n rng. Bt RRDY trong SPCR c thit lp ln mc 1 khi RSR c di chuyn ti DRR, v n c xa v 0 khi DRR c c. Khi RRDY chuyn t 0 ti 1, McBSP pht ti CPU 1 yu cu ngt (RINT) nu RINTM=00b trong SPCR. Mt s kin nhn (REVT) c gi ti iu khin EDMA. To ra tc mu: Nh tn gi ca n, m un ny pht ra tn hiu iu khin ging nh xung clock truyn/nhn v tn hiu ng b khung khi cn thit cho vic truyn ti d liu ti v t McBSP. Mch to xung clock cho php ngi s dng chn la clock CPU hoc ngun ngoi thng qua CLK ti pht ra CLKR/X. Thuc tnh tn hiu ng b khung ging nh chu k khung v rng khung c lp trnh. FSR/X, CLKR/X l chn 2 chiu, v v th c th l u vo v u ra. To ra s kin/ngt: McBSP to ra s kin ng b ti DMA, cho bit d liu d liu c sn sng trong DRR hoc DXR l sn sng cho d liu mi. Chng c c s kin ng b REVT, v ghi s kin ng b XEVT. Tng t CPU c th c/vit ti McBSP cn c vo ngt (RINT v XINT).

Two 32-Bit General Purpose Timers C62x/C67x c hai b nh thi 32 bt general-purpose c th c s dng : Time event Count event To xung Ngt CPU Gi s kin ng b ti b iu khin DMA.
B nh thi c u vo l chn TINP, u ra l chn TOUT. Chn TINP c th c s dng thu u vo general-purpose, v u ra nh u ra general-purpose. Khi xung ni c cung cp, b nh thi khi to m, kch hot cc thit b ngoi vi nh iu khin DMA hoc chuyn i A/D tng ng. Khi xung ngoi c cp, b nh thi khi to m cc s kin bn ngoi v ngt CPU sau mt s s kin c qui nh. 3.2.2 CPLD C6713 DSK dng Altera EMP3128TC100-10 CPLD thc thi: 4 thanh ghi iu khin/ trng thi vng nh cho php phn mm iu khin nhiu im trn board. iu khin giao tip daughter card v tn hiu. Kt ni cc thnh phn ca board li vi nhau.
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 55

c im ca thit b: EPM3128TC100-10 c in p hot ng l 3.3V (c th chu c 5V), 100 chn cho php cung cp 128 macrcells v ln n 80 chn I/O vi thi gian tr l 10ns t chn chn. Thit b da trn EEPROM v l c th lp trnh trn h thng thng qua giao din JTAG (10 chn u trn DSK). Tp tin ngun CPLD c vit theo chun cng nghip VHDL. Thanh ghi CPLD Thanh ghi CPLD cho php ngi dng iu khin chc nng CPLD trong phn mm. Trn KIT 6713 DSK thanh ghi c s dng chnh cho vic truy cp cc LED v DIP switch v iu khin card daughter. Thanh ghi l nh x trong CE1 ca EMIF ti khng gian a ch 0x90080000, l thanh ghi 8 bit bt ng b. Bng 3.3: nh ngha thanh ghi CPLD

Thanh ghi USER_REG USER_REG c dng c trng thi 4 DIP Switch v tr v 4 LED On hoc Off. Cc DIP switch c c bi 4 bit cao v vit bi 4 bt thp ca thanh ghi. Bng 3.4: Thanh ghi USER_REG

Thanh ghi DC_REG DC_REG c s dng iu khin, gim st daughter card. N d tm s c mt ca daughter card. DC_STAT v DC_CNTL cung cp giao tip n gin vi daughter card qua ng trng thi c v ng iu khin vit. DC_RST c th s dng t li (reset) card.
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 56

Bng 3.5 Thanh ghi DC_RST

Phin bn thanh ghi Phin bn ca thanh ghi c xc nh theo bng sau: Bng 3.6: Phin bng thanh ghi

3.2.3 AIC23 Codec

c im AIC23 Codec: Line input: ADC c full-scale vng 1.0V RMS Microphone input: Tr khng cao, in dung thp, tng thch u vo vi vng rng ca microphone. Line output: DAC full-scale ouput 1.0V RMS Headphone Output: u ra headphone m thanh ni c thit k 16 hoc 32 Ohm ng ra. Anlog Bypass mode: Ng vo tng t c th kt ni trc tip ti ng ra tng t. Sidetone Interface: AIC23 c ch lng ghp, ni m u vo microphone c i ti ng ra headphone. DSK dng TI AIC23, b gii m - m ha 2 knh cho tn hiu m thanh ng vo v ng ra. Codec ly mu tn hiu tng t trn micro hoc ng tn hiu ng vo v chuyn i chng sang tn hiu s, cho php chuyn x l bi DSP. Khi DSP c hon thnh vi d liu n s dng codec chuyn i mu tr li tn
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 57

hiu tng t trn ng tn hiu ra v headphone, v vy ngi dng c th nghe thy m thanh. B codec giao tip s dng 2 knh ni tip, 1 n iu khin thanh ghi cu hnh bn trong ca codec v 1 n gi v nhn mu m thanh s. AIC23 h tr trng thi cu hnh khc nhau m nh hng n nh dng ca d liu ca knh d liu v knh iu khin, nhng tm tt di y l bn ci t c a thch hn cho 6713 DSK, nhiu m t chi tit hn c cho pha di. Control channel : McBSP0, SPI vi xung ni v frame ng b. Data channel : MCBSP1, AIC23 trong ch chnh vi 12MHz xung clock.

Hnh 3.11: AIC23 Codec Knh iu khin m ha gii m 6713 DSK s dng McBSP0 nh l knh iu khin b m ha v gii m. Ch SPI l mt dng truyn d liu n gin v c s dng bi nhiu thit b cho giao tip c bn. Lc thi gian ch SPI nh sau:

Hnh 3.12 Lc thi gian ch SPI McBSP c kt ni n b m ha v gii m nh sau: Bng 3.7: Kt ni McBSP vi b m ha, gii m McBSP0 AIC23 FSX Transmit Frame Sync LRCIN Left-Right Clock input CLKX Data Clock BCLK Data Clock DX Transmit Data DIN Receive Data
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 58

Knh d liu m ha gii m Knh d liu c dng truyn v nhn d liu m thanh n AIC23. 6713 DSK dng McBSP1 nh l knh d liu. Ch DSP l ch n gin ni m s chuyn i trng thi t cao xung thp ca LTCIN bt u hot ng. D liu 32 bit, gm 16 bit cho knh phi v 16 bit cho knh tri. Thi gian ch DSP nh sau:

Hnh 3.13 Thi gian ch DSP McBSP c kt ni n AIC23 nh sau: Bng 3.8: McBSP kt ni n AIC23 McBSP1 AIC23 FSX Transmit Frame Sync LRCIN Left-Right Clock input FSR Receive Frame Sync LRCOUT Left-Right Clock output CLKX Data Clock BCLK Data Clock DX Transmit Data DIN Receive Data DR Receive Data DOUT Transmit data Thanh ghi Codec AIC23 c 10 thanh ghi iu khin chc nng nh m lng, nh dng d liu, tc ly mu v ch nng lng thp. Thanh ghi c vit thng qua knh iu khin McBSP0. Bng 3.9 thanh ghi Codec

Ly mu t ti codec Gi tr 32 bit c gi ti codec bi hm DSK6713_AIC23_write (). Hm ny:

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 59

Xt c MsBSP1 XRDY v tr v gi tr tc thi ca n, nu l False (0) v c tr v gi tr 0 v khng gi mu. Nu l True (1) th gi mu xung SXR ca McBSP1 v tr v gi tr 1. Ly mu t codec c t codec bi hm DSK6713_AIC23_read(). Hm ny: Xt c RRDY ca McBSP1 v tr v gi tr tc thi, nu l False th khng c gi tr v tr v gi tr false. Nu l true th c gi tr 32 bt t DRR ca McBSP1 v tr v gi tr True (1).

3.2.4 LED v Switch

Hnh 3.14 V tr LED v SWITCH DSK c tm n LED to thnh t bn ch s trng thi v bn n dng xc nh User LED. Cc ch s c biu hin bi cc n bn cnh DIP Switches. User LEDs : S dng 4 LED iu khin cho php cc thng tin phn hi ca ngi dng v hin th cc thng tin trng thi n gin. H c iu khin bng bng cch vit vo thanh ghi CPLD USER_REG. H cng c th thit lp xa thng qua LED Module ca Bo Support Library. Ch s trng thi: Cc ch s theo di trng thi cc chc nng. n LED PWR l mch in c ngun cung cp 5V, s c sng khi c kt ni. n RESET LED sng khi c s kin RESET. n LED USB_IN_USE sng khi chy m phng USB v tt khi a chy thc ngoi. n USB BUSY LED s sng khi vic truyn ti qua USB ang tin hnh. Cc Dip Switch s dng Bn thit b chuyn mch DIP cho php phn hi t ngi s dng. DIP Switches c th c thng qua thanh ghi CPLD USER_REG. DIP Switch c th c bng cch s dng module DIP Switch ca Bo Support Library. Switch cu hnh 6713 DSK c 4 Switch cu hnh cho php ngi s dng kim sot tnh trng DSP khi n Reset. Cc khi cu hnh switch c nhn SW3 trn bng DSK, bn cnh cc nt reset. Cu hnh Switch 1 iu khin DSP, trong khi Switch 2 v 3 cu hnh ch khi ng, s c s dng khi bt u thc hin DSP. Switch 4 xc nh tn

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 60

hiu HPI hoc McASP a ra trn chn share. Ci t cu hnh mc nh cc Switch u off. Bng 3.10: Cu hnh Switch

HPI Expansion Interface DSK cung cp ba kt ni m rng c th c s dng chp nhn mt u cm kiu daughtercard. Daughtercard cho php ngi s dng xy dng trn nn tng DSK ca h m rng kh nng v cung cp cc ty chnh v ng dng I/O. Cc kt ni m rng l b nh, thit b ngoi vi v Host Port Interface (HPI). bit thm thng tin c th tm thm vi t kha 6713 DSK Technical Reference. B nh, thit b ngoi vi v Host Port Interfaces. Cc kt ni b nh cho php truy cp khng ng b ti EMIF ca DSP giao tip ti b nh v thit b nh x b nh. Cc kt ni ngoi vi s a ra tn hiu ngoi vi ca DSP nh McBSPs, timers v clocks. C hai kt ni cung cp ngun v mass ti daughtercard.

3.2.5 JTAG Emulator Cung cp JTAG debug tc cao thng qua giao tip cng USB. JTAG cp ti mt b quy tc c thit k bao gm kim tra, lp trnh v g li ca chip. Giao din JTAG cho php ngi dng kim tra tn hiu v ng k vo mt con chip thng qua mt giao din bn ngoi m ch s dng nm chn thm trn chip. Trong mt mi trng pht trin DSP TI Code Composer s dng giao din JTAG g ri chng trnh khng xm nhp thng qua mt thit b phn cng gi l JTAG gi lp. B gi lp nhng USB (Embedded USB Emulator): Giao tip vi PC thng qua giao din tng thch USB 1.1. USB port PinOut: Bng 3.11: USB port PinOut Tn Chn 1 S dng USB VDD M t p ng ra USB

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 61

2 3 4 5 6

D+ DUSB VSS V bc (shield) V bc (shiled)

Data + Data Ni t Cp v bc Cp v bc

H thng n led TMS320C6713 DSK c 4 n led h thng. Bng 3.12: H thng n led
Tham chiu D4 Mu Xanh l cy Chc nng Gi lp USB c s dng. Khi gi lp JTAG ngoi c dng th n tt +5V Ch RESET Ch USB, truyn ti d liu thng qua cng USB Trng thi ON 1

D3 D6 DS201

Xanh l cy Cam Xanh l cy

1 1 1

3.3

Hng dn s dng phn mm Code Composser Studio

ng dng Code Composser Studio (CCS) cung cp nhng tnh nng: Mi trng bin tp, g li, qun l cc project, H tr bin dch, ng gi cc chng trnh vit vi ngn ng C/C++ M phng H thng hot ng thi gian thc (DSP/BIOS) Trao i d liu thi gian thc gia host vi target. Phn tch thi gian thc

3.3.1.1 Ci t phn cng v phn mm Phn mm: Ci t chng trnh CCS vo my, qu trnh ci t tng t nh ci t cc phn mm khc. Qu trnh ci t thnh cng s c 2 Shortcut trn Desktop

6713 DSK CCStudio v.3.1: Vit Code np cho Kit DSP. 6713 DSK Diagnostics Utility v3.1 Chng trnh chun on kim tra li Kit Phn cng: + Cp ngun 5V cho Kit DSP, s thy n LED bo hiu in p.
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 62

+ Gn cp USB kt ni t Kit DSP ln my tnh qua cng USB. Test KIT Click Icon 6713DSK Diagnostc Unity v3.1

Hnh 3.15 Giao din kim tra DSK 3.3.2 Kt ni

Khi ng CCS Click Nu s dng phin bn 3.1 th khng hin th icon kt ni, ta phi thc hin kt ni. Menu Debugg/Connect Nu thnh cng s xut hin Icon kt ni pha cui bn tri mn hnh CCS.

Hnh 3.16: Giao din chnh CCS 3.3.3 M Project tn ti Project/ Open

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 63

3.3.4

Hnh 3.17 : m Project Load v Run Project

Hnh 3.18: load v run project Chn File .out trong th mc Debug, chn Open, chng trnh s load ti DSK

Hnh 3.19: run chng trnh Dng chng trnh ang chy trn DSK C6713, Debug/ Halt (Shift + F5 hoc icon )

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 64

Hnh 3.20: dng (haft) mt chng trnh Thit lp ng dn th mc Include Project -> Build Options ->[Compiler tab] ->[Preprocessor category]

Hnh 3.21 Thit lp ng dn th mc Include Thit lp Mem modem i memory modem: data=far

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 65

Hnh 3.22: Thit lp Mem modem To Project mi To Project v vit code To Project mi : Project/ new, chn Target ng vi dng KIT ang dng TMS32C67xx 3.3.5

Hnh 3.23 : chn target Vit code C (.c): File->New->Source File, vit code chng trnh y. Lu vo vo th mc File->Save Lu vo cng th mc trn, file .c (file bt.c) Thm file .c vo Project:
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 66

Project->Add Files to Project Thm file .c mi to vo (bt.c)

Hnh 3.24 Ca s vit Code Thm mt s file cn thit Project->Add Files to Project Nhp phi vo Include, chn Add files to Project

Hnh 3.25 Thm file vo project Thm tt c file dng trong on chng trnh vo: "tonecfg.h", "dsk6713.h", "dsk6713_aic23.h" Tng t, nhp phi vo Libraries, chn Add files to Project, Add file dsk6713bsl.lib.

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 67

Hnh 3.26: thm file vo project 3.3.6 Built v Run Qu trnh built mt ng dng tri qua trnh t nh hnh ..

Hnh 3.27 Trnh t xy dng (built) mt ng dng Built project: Project Rebuild All,

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 68

Hnh 3.28: Ca s built project Nu thnh cng, tp tin .out s c to ra. V th trong CCS Chng ta c th v th ca tn hiu trong min tn s v min thi gian s dng CCS. Gi s c on code sau, v cn hin th dng sng khi thc thi chng trnh vi on code . 3.3.7 #include "DSK6713_AIC23.h" Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //Tn s ly mu shor output_buffer[256]; const short BUFLEN = 256; int index = 0; void main() { short sample_data; comm_poll(); //init DSK, codec, McBSP while(1) //infinite loop { sample_data = input_sample(); //sample input output_buffer[index] = sample_data; //copy of the data index++; index = index%BUFLEN; //if index is greater than BUFLEN // reinitialize it to zero output_sample(sample_data); //output sample } }
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 69

Nhn xt, th s c v ra theo bin output_buffer. V th. Trong ca s CCS, chn View Graph Time/Frequency.

Hnh 3.29: Thit lp th hin th trong min thi gian

Hnh 3.30: Thit lp th hin th trong min tn s 3.3.8 Mo sa mt s li thng thng Thit lp thuc tnh Built Project Build Options Chn Target Version: C671x

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 70

Hnh 3.31: chn phin bn target Sa li thuc tnh Suppress linker warnings Project->Build Options (linker tab) B check Warm About Output Sections (-w)

Hnh 3.32: Suppress linker warnings

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 71

Mo sa li file: during linking

Hnh 3.33: sa li during linking Vn ny do sai ng dn trong include th vin trong thuc tnh linker. Sa li ny: Ta remove 3 file: rts6700.lib, DSK6713bsl.lib, and csl6713.lib t linker options v thm th cng bng cch add file theo ng dn (Project -> Add files to Project)

Hnh 3.34: thit lp thuc tnh linker

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 72

3.4

Kho st mt s ng dng ca Kt TMS320C6713

Stater Kit TMS320C6713 c cc ng dng trong nhng lnh vc sau: Truyn thng: Modem in thoi, FAX, cc t bo in thoi, mng khng dy, loa in thoi, my tr li,. m thanh/ting ni: Voice mail, s ha v nn m thanh ting ni, kim tra speaker, tng hp m thanh. T ng: iu khin ng c, dng hot ng, chun on h thng H thng iu khin: H thng iu khin servo trong a, iu khin my in laser, iu khin robot, iu khin m t v ng c, cng c iu khin my t ng. Trong qun i: X l tn hiu raa v tn hiu tu ngm, h thng nh v tn la, modem pht tn s radia HF, m bo khong rng ca ph v m bo ting ni. Y hc: Thit b tr thch, nh MRI (nh chp s dng cng hng), nh siu m, gim st bnh nhn.. Thit b o c: Phn tch ph, to tn hiu. X l nh: HDTV, nng cao cht lng nh, xoay 3 chiu v hot hnh. Di y l mt s ng dng: 3.4.1 To tn hiu sng Sin 3.4.1.1 Lu gii thut
Main() Gui bang tin hieu ra output

Khoi tao thu vien ho tro DSK6713_init() Sample < Sin_table_size Kich hoat Codec AIC23

no
yes
Xuat mau hien tai ra ngo ra

Gui bang tin hieu ra output Sample ++

End

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 73

3.4.1.2

Code chng trnh pht ra dng sng Sine f=1KHz

#include "dsk6713.h" #include "dsk6713_aic23.h" #define SINE_TABLE_SIZE 48 /* Ci t cu hnh Codec */ DSK6713_AIC23_Config config = { 0x0017, // 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume 0x0017, // 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume 0x00d8, // 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume 0x00d8, // 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume 0x0011, // 4 DSK6713_AIC23_ANAPATH Analog audio path control 0x0000, // 5 DSK6713_AIC23_DIGPATH Digital audio path control 0x0000, // 6 DSK6713_AIC23_POWERDOWN Power down control 0x0043, // 7 DSK6713_AIC23_DIGIF Digital audio interface format 0x0001, // 8 DSK6713_AIC23_SAMPLERATE Sample rate control 0x0001 // 9 DSK6713_AIC23_DIGACT Digital interface activation }; /* Bng gi tr 48 mu sng sin */ Int16 sinetable[SINE_TABLE_SIZE] = { 0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b, 0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef, 0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4, 0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75, 0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1, 0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c }; /* Hm main */ void main() { DSK6713_AIC23_CodecHandle hCodec; Int16 sample; /* Hm h tr cho th vin hm */ DSK6713_init(); /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config); for (sample = 0; sample < SINE_TABLE_SIZE; sample++) { /* Gi mt mu ti knh tri */ while (!DSK6713_AIC23_write(hCodec, sinetable[sample])); /* Gi mt mu ti knh phi */ while (!DSK6713_AIC23_write(hCodec, sinetable[sample])); } /* Close the codec */ DSK6713_AIC23_closeCodec(hCodec); }

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 74

3.4.1.3

Hnh nh dng sng

Hnh 3.35: Hnh nh dng sng Sine

3.4.2

To tn hiu sng tam gic 3.4.2.1 C s tnh ton T chng trnh sng sin trn ta ch thay i 48 mu gi tr gn cho bin sinetable [SINE_TABLE_SIZE], thnh 48 mu mi ng vi dng sng tam gic vi cch tnh ton nh sau:

Ta c 48 mu cho ton chu k T vy T l 24 mu nhng do dng sng c tnh cht i xng nn ta c th tnh trong T, th c 12 mu
Chng 3: Kt TMS320C6713

 n tt nghip

Trang 75

u tin. tnh khong mu cho xung tam gic ta tnh nh sau:( d tnh ton ta i v s thp phn). Ta tnh cho na chu k u (dng). 7ffd h = 7x163 + 15x162 + 15x161 + 13x160 = 32765. 0000 h = 0. T gi tr cc i trn tnh n gi tr cc tiu ny l 12 khong nn chia cho 12. Khong gi tr gia cch mu: V sng dng tam gic l hm tuyn tnh nn ta tnh c 12 gi tr trong T l nh sau:
STT S t/phn S Hex 1 2730 2 5460 3 8190 4 10920 2aa8h 5 13650 3552h 6 16380 3ffch 7 19110 4aa6h 8 21840 5550h 9 24570 5ffah 10 27300 6aa4h 11 30030 754eh 12 32760 7ffdh

32765 0 2730 12

0aaah 1554h 1ffeh

Gi tr mu 12 l 32760 32765 =7ffd h. T tip theo ta ly i xng qua t gi th cc i. Ta tnh cho na chu k sau (m). 8002 h = 8x163 + 0x162 + 0x161 + 2x160 = 32770. L gi tr cc tiu nh nht. ef4c h = 14x163 + 15x162 + 4x161 +12x160 = 61260. T gi tr cc tiu tnh n gi tr ny l 12 khong nn chia cho 12. Khong gi tr gia cch mu: V sng dng tam gic l hm tuyn tnh nn ta tnh c 12 gi tr trong T l ly gi tr cc tiu cp s cng vi s gia l 2730 c nh sau:
STT S t/phn S Hex 1 32770 8002h 2 35500 8aach 3 38230 9556h 4 40960 a000h 5 43690 aaaah 6 46420 b554h 7 49150 bffeh 8 51880 caa8h 9 54610 d552h 10 57340 dffch 11 60070 eaa6h 12 62800 f550h

32770 0 2730 12

Gi tr mu 12 l 62800 ta ly gi tr ny l 0 = 0000 h. T tip theo ta ly i xng qua t gi th cc i. 3.4.2.2 Code chng trnh Tng t on chng trnh sng sin ta ch thay gi tr bng Int16 sinetable[SINE_TABLE_SIZE] thnh Int16 tamgiactable[SINE_TABLE_SIZE], vi gi tr nh sau: Int16 tamgiactable[SINE_TABLE_SIZE] =
{ 0x0000 0x3ffc 0x7ffd 0x3ffc 0x0000 0xbffe 0x8002 0xbffe , , , , , , , , 0x0aaa 0x4aa6 0x754e 0x3552 0xf550 0xb554 0x8aac 0xcaa8 , , , , , , , , 0x1554 0x5550 0x6aa4 0x2aa8 0xeaa6 0xaaaa 0x9556 0xd552 , , , , , , , , 0x1ffe 0x5ffa 0x5ffa 0x1ffe 0xdffc 0xa000 0xa000 0xdffc , , , , , , , , 0x2aa8 0x6aa4 0x5550 0x1554 0xd552 0x9556 0xaaaa 0xeaa6 , , , , , , , , 0x3552 0x754e 0x4aa6 0x0aaa 0xcaa8 0x8aac 0xb554 0xf550 , , , , , , ,

Chng 3: Kt TMS320C6713

 n tt nghip };

Trang 76

3.4.2.3

Hnh nh dng sng

Hnh 3.36: Hnh nh dng sng tam gic 3.4.3 ng dng dng sw la chn dng sng ng ra (sin, vung, tam gic) 3.4.3.1 Code chng trnh
#include "tonecfg.h" #include "dsk6713.h" #include "dsk6713_aic23.h" #include "dsk6713_led.h" #include "dsk6713_dip.h" #define TABLE_SIZE 48 //chieu dai bang song sin DSK6713_AIC23_Config config = { /* cau hinh codec */ 0x0017, 0x0017, 0x00d8, 0x00d8, 0x0011, 0x0000, 0x0000, 0x0043, 0x0001, 0x0001 }; Int16 sinetable[TABLE_SIZE] = { // Bng gi tr sng sin 0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b, 0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef, 0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4, 0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75, 0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1, 0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c }; Int16 squaretable[TABLE_SIZE] = { //Bng gi tr sng vung 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd, 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd, 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x8001, 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001, 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001, 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 }; Int16 triangletable[TABLE_SIZE] = { // Bng gi tr sng tam gic 0x0000, 0x0aaa, 0x1554, 0x1ffe, 0x2aa8, 0x3552, 0x3ffc, 0x4aa6, 0x5550, 0x5ffa, 0x6aa4, 0x754e, 0x7ffd, 0x754e, 0x6aa4, 0x5ffa, 0x5550, 0x4aa6, 0x3ffc, 0x3552, 0x2aa8, 0x1ffe, 0x1554, 0x0aaa, Chng 3: Kt TMS320C6713

 n tt nghip 0x0000, 0xf550, 0xeaa6, 0xdffc, 0xd552, 0xcaa8, 0xbffe, 0xb554, 0xaaaa, 0xa000, 0x9556, 0x8aac, 0x8002, 0x8aac, 0x9556, 0xa000, 0xaaaa, 0xb554, 0xbffe, 0xcaa8, 0xd552, 0xdffc, 0xeaa6, 0xf550 }; Int16 out_sample[TABLE_SIZE]; void main() { DSK6713_AIC23_CodecHandle hCodec; Int16 i, sample; DSK6713_init(); DSK6713_LED_init(); DSK6713_DIP_init(); hCodec = DSK6713_AIC23_openCodec(0, &config); while (1) { if (DSK6713_DIP_get(0) == 0) { for (i=0;i<TABLE_SIZE;i++) { out_sample[i]=sinetable[i]; } DSK6713_LED_on(0); DSK6713_LED_off(3); for (sample = 0; sample < TABLE_SIZE; sample++) { while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); } } else if (DSK6713_DIP_get(1)==0) { for (i=0;i<TABLE_SIZE;i++) { out_sample[i]=squaretable[i]; } DSK6713_LED_on(1); DSK6713_LED_off(3); for (sample = 0; sample < TABLE_SIZE; sample++) { while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); } } else if (DSK6713_DIP_get(2)==0) { for (i=0;i<TABLE_SIZE;i++) { out_sample[i]=triangletable[i]; } DSK6713_LED_on(2); Chng 3: Kt TMS320C6713

Trang 77

 n tt nghip DSK6713_LED_off(3); for (sample = 0; sample < TABLE_SIZE; sample++) { while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); while (!DSK6713_AIC23_write(hCodec, out_sample[sample])); } } else if (DSK6713_DIP_get(3)==0) { DSK6713_LED_on(0); DSK6713_waitusec(200000); DSK6713_LED_off(0); DSK6713_waitusec(200000); DSK6713_LED_on(1); DSK6713_waitusec(200000); DSK6713_LED_off(1); DSK6713_waitusec(200000); DSK6713_LED_on(2); DSK6713_waitusec(200000); DSK6713_LED_off(2); DSK6713_waitusec(200000); DSK6713_LED_on(3); DSK6713_waitusec(200000); DSK6713_LED_off(3); DSK6713_waitusec(200000); DSK6713_LED_off(3); DSK6713_LED_off(0); DSK6713_LED_off(1); DSK6713_LED_off(2); DSK6713_LED_on(0); DSK6713_waitusec(200000); DSK6713_LED_on(1); DSK6713_waitusec(200000); DSK6713_LED_on(2); DSK6713_waitusec(200000); DSK6713_LED_on(3); DSK6713_waitusec(200000); } else { DSK6713_LED_on(3); DSK6713_LED_off(0); DSK6713_LED_off(1); DSK6713_LED_off(2); } } }

Trang 78

Chng 3: Kt TMS320C6713

 n tt nghip

Trang 79

3.4.3.2 Hnh nh thc nghim

Hnh 3.37: Dng sng ra khi la chn SW

Chng 3: Kt TMS320C6713