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Finite State Machines (FSMs)

Finite State Machine Design Using VHDL

Any Circuit with Memory Is a Finite State Machine

Even computers can be viewed as huge FSMs

Design of FSMs Involves

Defining states Defining transitions between states Optimization / minimization

Above Approach Is Practical for Small FSMs Only

FSM Design Using VHDL 1 FSM Design Using VHDL 2

Moore FSM
Output Is a Function of Present State Only
Inputs Next State function Next State clock reset Present State Register Present State Inputs

Mealy FSM
Output Is a Function of a Present State and Inputs
Next State function Next State clock reset Present State Register Present State

Output function
FSM Design Using VHDL

Outputs
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Output function
FSM Design Using VHDL

Outputs
4

Moore Machine
transition condition 1 state 1 / output 1 state 2 / output 2

Mealy Machine
transition condition 1 / output 1 state 2 transition condition 2 / output 2

state 1

transition condition 2

FSM Design Using VHDL

FSM Design Using VHDL

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Moore vs. Mealy FSM (1)

Moore and Mealy FSMs Can Be Functionally Equivalent
Equivalent Mealy FSM can be derived from Moore FSM and vice versa

Moore vs. Mealy FSM (2)

Mealy FSM Computes Outputs as soon as Inputs Change
Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

Mealy FSM Has Richer Description and Usually Requires Smaller Number of States
Smaller circuit area
FSM Design Using VHDL 7

Moore FSM Has No Combinational Path Between Inputs and Outputs

Moore FSM is more likely to have a shorter critical path
FSM Design Using VHDL 8

Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10
0 S0 / 0 reset Meaning of states: S0: No elements of the sequence observed 1 1 S1 / 0 0 1 S2 / 1

Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence 10
0/0 S0 reset 0/1 S0: No elements of the sequence observed
FSM Design Using VHDL

1/0 S1

1/0

0 S1: 1 observed

S2: 10 observed

Meaning of states:

S1: 1 observed

FSM Design Using VHDL

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Moore & Mealy FSMs Example 1

clock 0 input S0 Moore S0 Mealy S1 S0 S0 S0 S1 S2 S0 S0 1 0 0 0

Synchronous Design Summary using VHDL

Draw a state graph and state table Write VHDL code and implement in EDA software package Check and simulate your design Download or fabricate

FSM Design Using VHDL

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FSM Design Using VHDL

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State assignment in VHDL

State encoding:
Binary state encoding One-hot state encoding

State assignment in VHDL

Binary state encoding
type STATE_TYPE is (S1 (S1, S2 S2, S3 S3, S4 S4); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "00 "00 01 10 11"; 11"; signal CURRENTSTATE, NEXTSTATE: STATE_TYPE;

Example: four states S0,S1,S2,S3 Binary state encoding: 00,01,10,11 One-hot state encoding: 1000,0100,0010,0001 Binary state encoding: CPLD One-hot state encoding: FPGA, rich resources in registers.
FSM Design Using VHDL 13

One-hot state encoding

type STATE_TYPE is (S1 (S1, S2 S2, S3 S3, S4 S4); Attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "0001 "0001 0010 0100 1000"; 1000"; signal CS, NS: STATE_TYPE;

FSM Design Using VHDL

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State machine VHDL code

TWO processes for Mealy Machine:
One process is used to model the state registers to decide the next state Second process models to update the next state and output logic

State machine VHDL code

Two or Three processes for Moore machine:
One process is used to model the state registers to decide the next state Second process models to update the next state Three process models the output logic OR 2nd and 3rd combined into one process
15 FSM Design Using VHDL 16

FSM Design Using VHDL

FSM VHDL Design Example

0110 sequence detector, Mealy machine no pattern overlapping

0110 Detector Mealy FSM No overlapping

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MEALY0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MEALY0110NV;
architecture NOOV of MEALY0110NV is type STATE_TYPE is (IDLE,S0,S01,S011); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK,RST) is begin if (rising_edge(CLK)) then if (RST=1 ) then CS<=IDLE; else CS <= NS; end if; end if; FSM Design Usingend VHDL 18 process SEQ;

FSM Design Using VHDL

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0110 Detector Mealy FSM-No overlapping

COM: process (CS,X) is begin Z<=0; case CS is when IDLE => if (X = 0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = 0') then NS<=S0; else NS<=S01; end if; when S01=> if (X = 0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = 0') then NS<=IDLE; Z<=1; else NS<=IDLE; end if; end case; end process COM; end architecture NOOV;
FSM Design Using VHDL 19

0110 Detector Mealy FSM No overlapping Simulation

FSM Design Using VHDL

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0110 detector Moore Machine

0110 sequence detector, Moore machine no pattern overlapping

0110 Detector Moore FSM No overlapping

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV;
architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=1 ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;
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FSM Design Using VHDL

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FSM Design Using VHDL

0110 Detector Moore FSM No overlapping with two processes

COM: process (CS,X) is begin Z<=0; case CS is when IDLE => if (X = 0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = 0') then NS<=S0; else NS<=S01; end if;
when S01=> if (X = 0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = 0') then NS<=S0110; else NS<=IDLE; end if; when S0110=> Z<=1; NS<=IDLE; end case; end process COM; end VHDL architecture NOOV; FSM Design Using

0110 Detector Moore FSM No overlapping Simulation

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FSM Design Using VHDL

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0110 Detector Moore FSM No overlapping Another VHDL code style

library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV;

(three processes)

0110 Detector Moore FSM No overlapping when S01=> COM: process (CS,X) is
begin case CS is when IDLE => if (X = 0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = 0') then NS<=S0; else NS<=S01; end if;
if (X = 0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = 0') then NS<=S0110; else NS<=IDLE; end if; when S0110=> NS<=IDLE; end case; end process COM;
FSM Design Using VHDL

architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=1 ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;
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No output Z in the COM process

FSM Design Using VHDL

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0110 Detector Moore FSM No overlapping

OUTPUTZ: process (CS) is begin case CS is when IDLE|S0|S01|S011=> Z<=0; when S0110=> Z<=1; end case; end process OUTPUTZ; end architecture NOOV;

FSMs in VHDL
Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed
State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process
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OR
Z<=1 when CS=S0110 else 0; end architecture NOOV;

3rd process defines the output function

FSM Design Using VHDL

Moore FSM
process(clock, reset)
Inputs Next State function Next State clock reset Present State Register Present State clock reset Inputs

Mealy FSM
process(clock, reset)
Next State function Next State Present State Register Present State

concurrent statements

Output function
FSM Design Using VHDL

Outputs
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concurrent statements

Output function
FSM Design Using VHDL

Outputs

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FSM States (1)

architecture behavior of FSM is type state is (list of states); signal FSM_state: state; begin process(clk, reset) begin if reset = 1 then FSM_state <= initial state; elsif (clock = 1 and clockevent) then case FSM_state is
FSM Design Using VHDL 31

FSM States (2)

case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if; end case; end if; end process;
FSM Design Using VHDL 32

Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10
0 S0 / 0 reset 1 1 S1 / 0

Moore FSM in VHDL (1)

TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = 1) THEN Moore_state <= S0; ELSIF (clock = 1 AND clockevent) THEN CASE Moore_state IS WHEN S0 => IF input = 1 THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;
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0 1 S2 / 1

FSM Design Using VHDL

Moore FSM in VHDL (2)

WHEN S1 => IF input = 0 THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = 0 THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= 1 WHEN Moore_state = S2 ELSE 0;
FSM Design Using VHDL 35

Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence 10
0/0 S0 reset 0/1 1/0 S1 1/0

FSM Design Using VHDL

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Mealy FSM in VHDL (1)

TYPE state IS (S0, S1); SIGNAL Mealy_state: state; U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = 1) THEN Mealy_state <= S0; ELSIF (clock = 1 AND clockevent) THEN CASE Mealy_state IS WHEN S0 => IF input = 1 THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
FSM Design Using VHDL 37

Mealy FSM in VHDL (2)

WHEN S1 => IF input = 0 THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= 1 WHEN (Mealy_state = S1 AND input = 0) ELSE 0;

FSM Design Using VHDL

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Moore FSM Example 2: State diagram

Moore FSM Example 2: State table

Present state A B C

Next state w = 0 A A A w = 1 B C C

Output z 0 0 1

FSM Design Using VHDL

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FSM Design Using VHDL

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Moore FSM
process(clock, reset)
Input: w Next State function Next State clock resetn Present State Register Present State: y

Moore FSM Example 2: VHDL code (1)

USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( clock resetn w z END simple ;

: IN STD_LOGIC ; : IN STD_LOGIC ; : IN STD_LOGIC ; : OUT STD_LOGIC ) ;

concurrent statements

Output function
FSM Design Using VHDL

Output: z
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ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN
FSM Design Using VHDL 42

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Moore FSM Example 2: VHDL code (2)

CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; FSM Design Using VHDL

Moore FSM Example 2: VHDL code (3)

END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ;

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FSM Design Using VHDL

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Moore FSM
process Input: w (w, y_present) process (clock, resetn) concurrent statements
Next State function

Alternative VHDL code (1)

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ;
FSM Design Using VHDL

Next State: y_next clock resetn Present State Register Present State: y_present

Output function
FSM Design Using VHDL

Output: z
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Alternative VHDL code (2)

WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; FSM Design Using VHDL END Behavior ;

Mealy FSM Example 2: State diagram

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FSM Design Using VHDL

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Mealy FSM Example 2: State table

Mealy FSM
process(clock, reset)
Input: w Next State function Next State clock resetn Present State Register Present State: y

Present state A B

Next state w = 0 A A w = 1 B B

Output w = 0 0 0

z w = 1 0 1

FSM Design Using VHDL

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concurrent statements

Output function
FSM Design Using VHDL

Output: z

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Mealy FSM Example 2: VHDL code (1)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN resetn : IN w : IN z : OUT END Mealy ;

Mealy FSM Example 2: VHDL code (2)

CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ;

STD_LOGIC ; STD_LOGIC ; STD_LOGIC ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN
FSM Design Using VHDL

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FSM Design Using VHDL

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Mealy FSM Example 2: VHDL code (3)

END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= 0 WHEN others; END Behavior ;

Example of a Moore state machine

FSM Design Using VHDL

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FSM Design Using VHDL

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FSM Design Using VHDL

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FSM Design Using VHDL

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