Do An UPS Chung

Thit k b nghch lu cho h thng UPS c kh nng kt ni li
MC LC
LI NI U ....................................................................................................... 2 Chng 1: TM HIU V UPS V NG DNG ............................................... 3 1.1 Gii thiu chung v UPS ................................................................................ 3 1.2 Phn loi UPS : ............................................................................................. 4 1.3 ng dng ca UPS trong thc t : .................................................................. 9 Chng 2: TNH TON THIT K ................................................................. 11 2.1 Thut ton to sng sin ................................................................................. 11 2.2 Cc khi mch s dng ................................................................................ 17 2.3 Tnh ton mch lc thng thp ..................................................................... 24 Chng 3: XY DNG KHU IU CHNH IN P ................................ 30 3.1 Nguyn l chung ca khu t ng iu chnh in p : ............................... 30 3.2 Xy dng m hnh ton cho cc khu ca mch nghch lu : ....................... 30 Chng 4. NGHIN CU CC MODULE C BN CA DSPIC33FJ12MC202 .......................................................................................... 37 4.1 Tng quan v vi iu khin dsPIC33FJ12MC202: ....................................... 37 4.2 Cu trc vi iu khin : ................................................................................ 38 4.3 T chc b nh: ........................................................................................... 40 4.4 Khi qut v cc thanh ghi: .......................................................................... 41 4.5 Gii thiu cc module c bn ....................................................................... 43 Chng 5: TM HIU PHNG PHP HA NG B.............................. 63 5.1. Nhu cu ha ng b vo li ..................................................................... 63 5.2 Cc iu kin ha ng b ........................................................................... 63 5.3 Vng kha pha (Phase Locked Loop - PLL) ................................................. 63 Chng 6: M HNH V KT QU O C ............................................ 73 KT LUN .......................................................................................................... 75
SVTH: Nguyn Vn Chung Lp TB-T1-K51
LI NI U
S ra i, pht trin nhanh v ngy cng hon thin ca cc linh kin in t, c bit l vi x l to ra s thay i su sc v pht trin mnh m trong cc thit b, h thng thit b in - in t. Nhm m bo tnh lin tc v cht lng cung cp in cho nhng ti nhy cm m khng ph thuc trng thi h thng cung cp, phng php duy nht l s dng b ngun d tr lm vic tin cy. Hn na, hin nay nng lng ngy cng cn kit, nn nhiu ngun nng lng mi v ang c ch , s dng nhiu hn nh: nng lng mt tri, nng lng gi,... Cc ngun nng lng c th ni l v tn ny s gip to ra ngun in nng ln nu c s dng tt, gim ng k gnh nng cho thy in v nhit in hin nay ang phi gnh vc. Xut pht t nhu cu thc t trn em quyt nh chn ti nghin cu l: Thit k b nghch lu cho h thng UPS c kh nng kt ni li. Em c gng nghin cu v thit k di s hng dn tn tnh ca thy Hong Anh v thy Nguyn Thnh Khang. Tuy nhin, do s hn ch v nhiu mt nn chc chc n ny cn nhiu thiu xt. Em rt mong nhn c s gp ca cc thy c ti ny hon thin hn! Em xin chn thnh cm n!
Sinh vin thc hin Nguyn Vn Chung
Chng 1: TM HIU V UPS V NG DNG

1.1 Gii thiu chung v UPS
UPS c vit tt ca cm t ting Anh: Uninterruptible Power Supplier c hiu nh l h thng ngun cung cp lin tc hay n gin hn l b lu tr in d phng nhm lm tng tin cy cung cp in cho h thng. 1.1.1 Cu trc chung : Ngun d phng (Acquy hoc my pht) Mt b chnh lu Mch lc cho khu chnh lu Mch nghch lu Mch iu khin hot ng cho cc van. 1.1.2 Gii php dng UPS : iu cn ch trc ht ca nhng s c v hu qu ca n v phng din: An ton cho ngi An ton cho thit b nh xng Mc tiu vn hnh kinh t. Ta cn phi tm cch loi b tt c cc s c. C nhiu gii php k thut khc nhau cho vn ny, nhng gii php ny c so snh trn c s ca hai tiu chun sau nh gi: Cung cp in lin tc Cht lng in cung cp
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Hot ng nh mt giao din gia h thng cung cp in v nhng ti nhy cm, UPS cung cp cho ti mt nng lng in lin tc, cht lng cao, khng ph thuc mi tnh trng ca h thng cung cp. UPS to ra mt in p cung cp tin cy: Khng b nh hng ca nhng s c ca h thng cung cp, c bit khi h thng cung cp ngng hot ng. Phm vi sai s cho php tu theo yu cu ca nhng thit b in nhy cm. UPS c th cung cp in p tin cy, c lp v lin tc thng qua cc khu trung gian: Acquy v chuyn mch tnh.
1.2 Phn loi UPS :

1.2.1 Phn bit theo ch lm vic a. UPS offline :
Hnh 1.1 Cu trc b UPS offline SVTH: Nguyn Vn Chung Lp TB-T1-K51 4
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Nghch lu ni song song vi h thng cung cp l ngun d tr phng tnh trng khn cp. Trong qu trnh vn hnh, ngun li c cung cp trc tip n ti m khng qua nghch lu. Nu s c h thng cung cp in hoc in p h thng cung cp in khng n m trong sai s cho php th ti chuyn t h thng cung cp in qua nghch lu trong thi gian ngn <10 ms. Khi in p h thng cung cp c phc hi,ti s t ng chuyn v h thng cung cp. Dng vi ti P <2 KVA. Thi gian chuyn mch ph hp vi ti nhy cm. Nhc im: Thi gian chuyn mch t khi s c in li cho n khi ngun pin cung cp cho thit b tiu th. Cng tc ngt in khi ngun li chuyn sang dng in t pin phi m bo khi ngt hon ton ra khi li in mi c php cung cp in t b inverter bi nu khng dng in cung cp t pin s phi cp cho c li in a phng - v cng nh my pht in, h thng s h hng v qu ti. UPS offline khng c cng d ng n p khi chng s dng in li bnh thng - bi n gin khi khng c s c v li in th cc thit b pha sau UPS n thun c ni trc tip vi li in thng qua r le. b. UPS online
Hnh 1.2 Cu trc UPS online c chn vo gia h thng cung cp v ti. Ton b in nng cung cp cho ti u phi qua nghch lu do vy vic cung cp in c lin tc trong phm vi sai s cho php ca f, U. Khng ph thuc vo trng thi ca h thng cung cp in. p dng cho ti c cng sut trung bnh P 40 KVA. 1.2.2 Phn loi UPS da theo b chuyn i
Hnh 1.3 Cu trc UPS tnh a. UPS tnh: S dng b chuyn i tnh thc hin cung cp nng lng. SVTH: Nguyn Vn Chung Lp TB-T1-K51 6
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Gii hn dng trong vn hnh cho php Icp=2.33Im. Cch li v in. Bo dng v vn hnh n gin, lm vic tin cy cy chc chn. Kh nng phn ng tc thi trc nhng dao ng bin ca h thng cung cp, s dng thit b iu khin vi x l da trn k tht s. Bin in p iu chnh trong phm vi sai s 0.5% 1%, thi gian iu chnh nhanh, kch thc v trng lng ca h nh. b. UPS quay
Power
FL M DK M G G
Output
Hnh 1.4 Cu trc UPS quay Trong : M: ng c G: My pht FL: Flywheel (Bnh ) S dng my in quay thc hin bin i nng lng. Mt b UPS quay hot ng nh vo qun tnh cao ca bnh khi lng ln (Flywheel energy storage) cung cp nng lng trong trng hp c s c in ngn hn. Bnh hot ng nh 1 b m chng li s tng hay gim t ngt SVTH: Nguyn Vn Chung Lp TB-T1-K51 7
Thit k b nghch lu cho h thng UPS c kh nng kt ni li ca ngun cung cp v nhng s c ngn hn khng th nh hng ng k n tc quay ca bnh khi lng ln. y l 1 trong nhng dng thit k c in nht trong lch s ngnh in. C th coi UPS quay l mt b UPS online v n hot ng c trong iu kin bnh thng. Tuy nhin, n ch bo v h thng ti trong khong thi gian t 10 n 20 giy trc khi bnh quay ch m xung di mc cho php v u ra b ngt. Mt h thng UPS quay tiu biu bao gm cc thnh phn sau: 1 ng c ko 1 my pht in ng b (My pht v ng c c lin kt v mt c kh nh h thng li hp, ai truyn .v.v.) Trc quay my pht c gn vi 1 bnh khi lng ln. Khi h thng xy ra s c ngn hn, ng c b ngt in. Bnh tip tc quay (do qun tnh ln), do tip tc ko my pht v cung cp in cho u ra. 1.2.3 S nguyn l chung ca UPS :
+
CL
-
NL
AQ
Hnh 1.5 S nguyn l chung ca UPS SVTH: Nguyn Vn Chung Lp TB-T1-K51 8
Thit k b nghch lu cho h thng UPS c kh nng kt ni li CL: Cung cp ngun mt chiu cho nghch lu v np thng trc cho acquy AQ: To nng lng d tr cung cp cho nghch lu khi xy ra: - Ngng hot ng h thng cung cp. - H thng cung cp c s c hoc cht lng h thng cung cp khng nm trong gii hn cho php. NL: Chuyn i DC thng chnh K: Bao gm c h thng phn hi ,iu khin hot ng ca CL, NL v qu trnh phng np AQ, n nh cung cp in theo yu cu. AC vi sai s cho php cht ch, chc chn hn h
1.3 ng dng ca UPS trong thc t :

Hin nay nhu cu ng dng UPS trong cc lnh vc tin hc, vin thng, ngn hng, y t, hng khng l rt ln. S lng UPS c s dng gn bng 1/3 s lng my tnh ang c s dng. C th ly mt vi v d v cc thit b s dng UPS, l nhng my tnh, vic truyn d liu v ton b thit b mt trng thi no u l rt quan trng v khng cho php c mt in. UPS c s dng trong ngnh hng khng m bo s thp sng lin tc ca ng bng sn bay.
ng dng chnh
Thit b c bo v - My in, h thng v th v cc thit b u cui. khin gim st, my t ng. Tng i in thoi, h thng truyn d liu, h thng raa. 9
1. H thng my tnh - My tnh, mng my tnh ni chung cng nghip 3. Vin thng 2. H thng my tnh B iu khin lp trnh, h thng iu khin s, iu
Thit k b nghch lu cho h thng UPS c kh nng kt ni li 4. Y t, cng nghip 5. Chiu sng 6. Cc ng dng khc Dng c y t, thang my, thit b o nhit , thit b iu khin chnh xc ng hm, ng bng sn bay, nh cng cng... My qut hnh, cung cp nng lng cho my bay...
Ni tm li UPS l mt ngun in d phng, n c mt mi ch mi ni, nhng ni i hi cao v yu cu cp in lin tc. Bi tm quan trng ca UPS, n ca em c mc tiu thit k b UPS va c kh nng chy c lp (nghch lu), ng thi c kh nng kt ni vi li in (ha ng b).
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Chng 2: TNH TON THIT K

2.1 Thut ton to sng sin
2.1.1 Phng php to sng iu bin : C hai phng php to ra sng iu bin : 1. Phng php s dng sng sin cao tn : c m t bng hnh v sau :
Hnh 2.1 Phng php sng sin cao tn Nguyn l : s dng sng sin c tn s cao cho giao vi sng sin tn s mong mun to ra sng iu bin nh hnh v. 2. Phng php s dng sng tam gic :
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Hnh 2.2 Phng php sng mang tam gic Nguyn l: s dng sng tam gic tn s cao cho giao vi sng sin tn s mong mun to ra sng iu bin. 2.1.2 Nguyn l to sng sin a) Cu trc mch Half-bridge (Na cu) :
VI 2
Ls C R
K1
VI 2
K2
Hnh 2.3 Mch na cu Ni ti vo im gia hai ngun, khi i m gia C ng vai tr l trung tnh .
12
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Theo hnh v trn : khi ta cp tn hiu iu bin sng Sin kch m kha K1 v K2 th in p t trn in tr s c dng hnh Sin.V bin in p sng Sin ny l
V
VI 2
uR
Voc(t)
Hnh 2.4 in p to bi mch na cu b) Cu trc mch Full-Bridge (C cu) :
K1 Ls A R B
VI
K2
Hnh 2.5 Mch c cu Da vo mch Half-Bridge ta thy rng mch Full-Bridge l s kt hp ca hai na cu. in p ra trn ti l hiu ca hai in p ti i m A v B (uAB = uA uB). Bin in p ti ph thuc vo gc lch pha gia in p ti im A v i m B, gi s gi gc lch pha l . Suy ra :
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uA uB
VI .sin( t ) 2 VI .sin( t 2
u AB
u AB
uA
uB
) VI [sin( t ) sin( t 2 )]
VI VI .sin( t ) .sin( t 2 2
Ta thy rng : [sin( t)-sin( t)]
2
sin( t ) 180 O
Du bng xy ra khi v ch khi : sin( t )
Vy nn tn hiu sng Sin iu bin phi lch pha nhau 180o bin in p ra l ln nht .
VA
VB
uAB
Hnh 2.6 ip p to ra bi mch c cu SVTH: Nguyn Vn Chung Lp TB-T1-K51 14
Thit k b nghch lu cho h thng UPS c kh nng kt ni li c) T s iu bin : Xt t s iu bin bin : l mi quan h gia bin sng sin chun v sng tam gic, k hiu l ma :
ma
A c pk
Vi A l bin sng sin chun cpk l bin sng mang tam gic
VAB VI
min tuyn tnh
min tuyn qu iu bin
sng vung
1,0
2,0
3,0
ma
Hnh 2.7 Mi quan h gia t s iu bin bin T s iu bin tn s: l t s gia tn s sng mang (fpwm) v sng sin chun (fsin), k hiu t s ny l mf :
mf
f pwm fc
Thng th mf > 9 m bo t l hi trong in p u ra b . 2.1.3 M phng trn Psim : Cch to ra tn hiu iu bin :
15
Thit k b nghch lu cho h thng UPS c kh nng kt ni li S dng mt tn hiu sin chun giao vi sng tam gic qua b so snh ta s c c sng iu bin. Hai tn hiu sng sin chun t lch pha nhau gc 1800
Hnh 2.8 S m phng trn PSim
Hnh 2.9 Dng sng tn hiu iu bin u ra (trc lc) SVTH: Nguyn Vn Chung Lp TB-T1-K51 16
Hnh 2.10 Dng v p trn in tr R (sau lc) Nguyn l to sng sin c trnh by trn l c s ta thit k mch ng lc cho phn nghch lu.
2.2 Cc khi mch s dng

2.2.1 Mch ng lc C hai la chn chnh cho vic s dng kho ng ct cng sut trong iu khin ng c l MOSFET v IGBT. C hai loi MOSFET v IGBT u l linh kin c iu khin bng in p, ngha l vic dn v ngng dn ca linh ki n c iu khin bng mt ngun in p ni vi cc gate ca linh kin thay v l dng in trong cc b nghch lu s dng transitor nh trc y. V vy cch s dng loi linh kin ny lm cho vic iu khin tr nn d dng hn. SVTH: Nguyn Vn Chung Lp TB-T1-K51 17
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Ngy nay c nhiu ci tin trong vic sn xut, MOSFET c th hot ng tn s ng ct cao hn vi RDS(on) nh (khong vi miliohm) lm cho tn tht cng sut c gim i rt nhiu. V vy ngy nay, a s cc b nghch lu thng s dng MOSFET hn l IGBT nh trc kia. Tnh chn van Cng sut u ra ca mch nghch lu l P = 1kW. in p Ura = 220V. dng in u ra : I dm
P U 10000 220 4,5( A)
in p mt chiu a vo l Vdc = 350V Chn van cho mch lc ta phi da vo mt s iu kin sau : i vi van hot ng ch lm mt t nhin (khng c cnh tn nhit). Dng lm vic ca van bng khong 10% dng in nh mc cho php c a van. Im = 10%Ivan => Ivan = 10.Im = 10.4,5 = 45(A) i vi van lm vic ch c cnh tn nhit lm mt, dng in lm vic ca van cho php khong 30%Im Ivan =
10 10 .Im = .4,5 = 15 (A) 3 3
Nu c cnh tn nhit v lm mt cng bc bng qut gi lm mt dng lm vic cho php c th ti 70%.Im Ivan =
10 10 .Im = .4,5 = 6,43 (A) 7 7
Nu van lm vic c lm mt cng bc bng nc dng lm vic cho php c th ti 90%.Im Ivan =
10 10 .Im = .4,5 = 5 (A) 9 9
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li V van hot ng ch c cnh tn nhit lm mt nn ta chn MOSFET IRFP460 (vi cc thng s VDSS = 500V, ID = 20A, RDS(on) = 0.27 ).
Hnh 2.11 S Mch lc S dng 4 Mosfet IRF460, cho php dng in ti nh mc chy qua l 20A, in p ngc chu ng l 500V, mc s nh hnh v. Gic cm J2 ni vi in p mt chiu u vo, gic cm J1 l in p iu bin u ra, J3 v J4 ni vi mch li nhm iu khin 4 van lc m v kha, ng thi n cng gip np in p cho hai t booststrap. 2.2.2 Mch li C hai s la chn cho cc kha ng ngt cng sut to ra sng sin l MOSFET v IGBT v kh nng chu dng v p cao. Ni chung, khi s dng cc kha ng ngt (MOSFET, IGBT ) iu khin th u cn dng n mch li (gate drive scheme). C 2 phn c bn trong vic iu khin cc ng ngt linh kin cng sut l: iu khin pha cao (high side Q1) v pha thp (low side Q2).
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Hnh 2.12 V d s iu khin MOSFET Trong v d trn Q1 v Q2 lun trng thi lm vic i nghch nhau. Khi Q1 trng thi ON th Q2 trng thi OFF v ngc li. Khi Q1 ang trng thi OFF chuyn sang trng thi ON => chn S ca Q1 chuyn t ground sang in p cao (high voltage rail). Do mun kch Q1 tip tc ON th phi to in p kch VGS1 c gi tr VGS1= VSQ1 + V. Trong khi tn hiu ra ca vi x l iu khin ng ngt cc kha ch c gi tr in p +3.3V (so vi ground). Nn cn phi c mch li to tri p v cch ly trong vic ng ngt pha cao Q1. Tuy nhin i vi Q2 th chn S c ni ground, do in p kch VGS2 ch cn c gi tr V. Do vic ng ngt kha low side (Q2) c iu khin d dng hn. y ta thit k mch li dng IC li IR2110.
Hnh 2.13 Mch li SVTH: Nguyn Vn Chung Lp TB-T1-K51 20
Thit k b nghch lu cho h thng UPS c kh nng kt ni li S dng 2 IC li IR2110, th t cc chn c ni nh hnh v trn, ngun cp cho n l 5V v 15V, c to bi IC n p 7805 v 7815 ni n trn. Cc u vo 10 v 12 c ni vi u ra ca mch cch ly. T C2 v C4 l cc t bootstrap. u ra ca gim J1 v J4 c ni ti iu khin mch lc. Gii thiu IC IR2110 IR2110 l loi IC chuyn dng li MOSFET v IGBT ca hng IR (International Rectifier). IC ny c 1 knh output (mi knh gm high side v low side) c th li cho mt nhnh ca cu bn dn.
2.2.3 Mch iu khin Dng vi iu khin dsPIC33FJ12MC202 (y l 1 loi vi iu khin kh mnh v s c trnh by r hn phn sau). Mch iu khin c nhi m v pht ra xung iu khin iu khin cc kha bn dn ca b nghch lu ba pha qua mch cch ly v mch li.
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Hnh 2.14 Mch iu khin Mch gm ngun 3,3V cp vo chn VDD v chn AVDD ca vi iu khin, b to xung dao ng thch anh 7,37MHz c ni vo chn 9 v chn 10. Chn c tn hiu phn hi ADC c ni vo chn 2. Cc chn 4 (PGD1), chn 5 (PGC1), chn MCLR dng np chng trnh cho vi iu khin. Cc u ra ca tn hiu PWM nm cc chn 23, 24, 25, 26. 2.2.4 Mch cch ly Cc mch pht ra tn hiu iu khin mch cng sut bn dn phi c cch ly v in. iu ny c th thc hin c bng mch cch ly quang hoc bng bin p xung. Mch cch ly l phn ni gia mch iu khin v mch li. Bin p xung :
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li Gm mt cun dy s cp v c th nhiu cun th cp. Vi nhiu cun dy pha th cp, ta c th kch ng nhiu transistor mc ni tip hoc song song. Bi n p xung cn c cm khng tn nh v p ng nhanh. Trong trng hp xung iu khin c cnh tc ng ko di hoc tn s thp, bin p xung sm t trng thi bo ha v ng ra ca n khng ph hp yu cu iu khin. Cch ly quang (Opto): Gm ngun pht tia hng ngoi dng diode (IR-LED) v mch thu dng phototransistor. Do tha mn yu cu cch ly v in, ng thi p ng ca opto tt hn my bin p xung. n gin v tin dng, ta chn phng n dng opto. Vi tn s ng ct cao (10kHz), ta s dng cch ly quang 6n137.
Hnh 2.15 Mch cch ly
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li Mch dng 4 cch ly quang 6n137 c nui bng ngun 5V, u vo cc cch ly quang l cc xung PWM a vo t mch iu khin nh J2, 4 chn ra 7 s a vo mch li li MOSFET.
2.3 Tnh ton mch lc thng thp

2.3.1 S cn thit ca mch lc thng thp Khi thit k mch nghch lu ta mong mun in p u ra c tn s l 50Hz. Do in p iu bin u ra ca cu nghch lu l tp hp ca cc thnh phn tn s bc nht v bc cao. Nn c c in p u ra 50Hz ta phi loi b i thnh phn tn s bc cao. thc hin iu ny ta s dng mch lc thng thp c dng nh di hnh v, gm hai thnh phn L v C. 2.3.2 Tc dng ca C v L trong mch lc Ta bit ZL = 2.f.L , nn khi tn s f tng, dn n ZL tng, hay ni cch khc n ngn khng cho nhng tn s bc cao i qua. Tng t Z C
1 , khi tn s tng , dn n ZC gi m, do ZC mc song song 2. . f .C
vi ti nn n c xu hng cho thnh phn bc cao chy qua v trit tiu n. 2.3.3 M hnh ton tnh ton gi tr L v C Khi tnh ton gi tr cun lc v t lc, do in tr cun lc rt nh nn ta c th b qua. Khi ta c m hnh mch lc:
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L
Laplace
Ls
uvao
ura
uvao
1/Cs
ura
Hnh 2.16 Bin i Laplace Theo s mch ta c :
uvao ( s)
I ( L.s
1 ) C.s
ura ( s )
ura uvao
I.
1 C.s
1 LC.s 2 1
K (s)
Nn hm truyn ca mch lc c dng nh sau: K ( s)
1 LC.s 2 1
K( j )
1 LC ( j ) 2
1 1 1 LC
Bin hm truyn : | K ( j ) | Xt : L()=20. log |K(j)| L() = - 20. log |1- LC2|
1 |1 LC
Xt biu thc :
L() = - 20. log |1- LC2| 25
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Khi : 0 L1 () = 0 Khi : + LC2 >>1 L() - 20.logLC 40.log
Hai ng ny ct nhau ti im : Biu din trn th :

L() C
1 L.C
(rad/s) -40dB L()
Hnh 2.17 th bode 2.3.4 Tnh ton gi tr L v C Chn tn s ct : fc = 1000 Hz c= 2..fc = 2..1000 = 6283,2 (rad/s) Do ti u song song vi C nn phi chn L v C sao cho : Zc>> ZL m bo cho khi y ti in p ri trn L l b v in p p trn C l ln nht. Nu UL = 5V v dng khi y ti I = 5,05A suy ra : ZL = 5/5,05= 0,99 (). ng vi = 2..f = 2..50 = 314,16 (rad/s) SVTH: Nguyn Vn Chung Lp TB-T1-K51 26
Lmax Cmin
ZL
1 Lmax .
0,99 2. .50
2 c
3,15(mH )
8, 06.10 6 ( F )
1 3,15.10 3.6283, 22
Chn C = 10 F = 10.10-6 F
L
ZL
1 C. c2
2. . f .L
1 10.10 .6283, 22
6
2,54.10 3 ( H )
3
2. .50.2,54.10
0, 798( )
ZC
1 2. . f .C
1 2. .50.10.10
318,3( )
R rng iu kin: ZC >> ZL c tha mn. 2.3.5 Thit k cun khng lc Vi cc thng s thng s nh mc: Dng nh mc chy qua cun khng : I = 5,05 A St p trn cun khng :U = 5 V Tn s hot ng: f = 50 Hz Mt t cm : T cm B = 0,3 0,5 T, ta chn B = 0,4 T
: L = 2,54 mH
Vt liu li : Ferrite H s dng sng : Kf = 4,44 ( Dng sng hnh sin) H s lp y: Ku = 0,4 Mt dng in: J = 700 A/cm2
27
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Theo nhng thng s nh mc trn, ta tin hnh lp t ni tip 2 cun khng c thng s ging nhau. Khi st p trn mi cun l 2,5V, v t cm mi cun l 1,27 mH. Cng sut cun khng: VA = U.I = 2,5.5,05 = 12,625 (W)
Ap VA.104 K f .Ku . f .B.J 12, 625.104 4, 44.0, 4.50.0, 4.700 5, 08
Tra bng mch t dng ETD ng vi Ap va tm c ta chn li ETD49 vi cc thng s: - Chiu di ng sc t : - Trng lng li : - Chiu di trung bnh vng dy : - Din tch ca s mch t : - Mch t : - Chiu cao cun dy : - Chiu rng cc t chnh : Tnh s vng dy:
N U .104 K f .B. f . Ac 2,5.104 133, 4(vng) 4, 44.0, 4.50.2,11
MPL = 11,4 cm WtFe = 124 grams MLT = 10,3 cm Wa = 3,434 cm2 Ap = 7,2453 G = 3,54 cm E = 1,67 cm
- Tng din tch mt ct cc cc t : Ac = 2,11 cm2
Chn N = 133 vng Khong cch khe h khng kh:
28
lg
Tnh t tn:
0, 4. .N 2 . Ac .10 L
0, 4. .1332.2,11.10 1, 27.10 3
0,37(cm)
F 1
lg Ac
.ln
2G 1 lg
0,37 2.3,54 .ln 1, 752 0,37 2,11
S dng kt qu va tnh c tnh li s vng dy:
N'
lg .L 0, 4. . Ac .F .10
8
0,37.1, 27.10 3 0, 4. .2,11.1, 752.10
101(vng)
S dng s vng dy mi tnh li mt t cm:
U .104 K f .N '. f . Ac
2,5.104 0,52(T ) 4, 44.101.50.2,11
Tnh tit din dy qun:
I J
5, 05 700
7, 21.10 3 (cm2 )
Chn dy c ng knh d = 1 mm => Tit din dy Aw = 7,854.10-3 (cm2) Tnh li h s lp y:
Ku
in tr cun khng lc:
N '. Aw Wa
101.7,854.10 3, 434
0,3
MLT .N '.
cm
.10
10,3.101.219.10
0, 228( )
29
Chng 3: XY DNG KHU IU CHNH IN P

3.1 Nguyn l chung ca khu t ng iu chnh in p :
Hnh 3.1 S khi h thng
3.2 Xy dng m hnh ton cho cc khu ca mch nghch lu :

3.2.1 Xy dng mi quan h gia rng xung d (Duty Cycle) v in p u ra :
Hnh 3.2 M hnh cu H Suy ra s mch c dng n gin nh sau :
30
Hnh 3.3 Bin i Laplace Tng tr ca mch c tnh nh sau :
Ls
1 Cs
LCs 2
Rs Cs
uO ( s )
I O ( s ).
1 Cs
V i : I O ( s )
u AB ( s ) ( Vi uAB l dng in p iu bin ) Z
G '( s)
uO ( s) u AB ( s)
Cs 1 . ( LC ) s RCs 1 Cs
2
G '( s)
1 ( LC ) s
2
RCs 1
(R l in tr cun cm) Quan h gia in p u ra vi rng xung d :
31

VA
VB
uAB
Hnh 3.4 in p ra UAB Ta c :
VA (t )
1 . VA ( )d T t
t T
VA (t )
1 .(T .VDC .d1 (t )) T
VA (t ) VDC .d1 (t )
(d1 l rng xung trong mt chu k pwm ca VA)
1 VB (t ) . VB ( )d T t
t T
VB (t )
1 .(T .VDC .d 2 (t )) T
VB (t ) VDC .d 2 (t )
(d2 l rng xung trong mt chu k pwm ca VB) Suy ra :
u AB VA VB VDC .d1 VDC d 2
u AB VDC .(d1 d 2 )
u AB VDC .d ( trong d = d1-d2 )

VDC
u AB (t ) d
32
Do :
G( s)
uO (t ) d
VDC .
1 LCs 2 Rs 1
3.2.2 Xc nh hm truyn ca khi PWM :

m(t) ZOH T
C(t),m(t) cpk
ms (t) c(t)
V MO(t)
m(t) ms(t)
VMO(t)
Hnh 3.5 M hnh PWM Khu PWM c xp x nh mt khu t l nn ta c hm truyn ca n nh sau:
PWM ( s )
VMO ( s ) M (s)
1 c pk , cpk l bin sng mang
3.2.3 S khi m t vng kn ca b nghich lu :
Hnh 3.6 S vng kn SVTH: Nguyn Vn Chung Lp TB-T1-K51 33
Thit k b nghch lu cho h thng UPS c kh nng kt ni li xc nh cc h s ca khu iu chnh Kp, Kd ta s dng tiu chun Nyquist p dng cho hm truyn h h. 3.2.4 Tiu chun Nyquist : Hm truyn h h:
Gh ( s )
(K p
K d .s ).
VDC 1 . .Gu c pk LC.s 2 RC.s 1

VDC 1 . .Gu c pk 1 LC 2 j RC
Gh ( j )
(K p
j K d ).
Tiu chun Nyquits h kn n nh: Bin ca hm truyn h h tn s ct phi bng 1 |Gh(j c)| = 1 Gc pha ca h h tn s ct phi ln hn -180o
c
= arctg Gh(j c) > -180o
Ta c: Vdc=350V; Gu=1/311; L=2,54mH; C=10 F; R=0,228 chn fc = 2kHz ( c=2 fc), cpk = 1 Kp = 1,7 v Kd = 1,343.10-4 Hm truyn h h:
Gh ( s )
1, 694.10 4.s 2,129 2,54.10 8.s 2 2, 2.106 1
34
Hnh 3.7 Biu bode
35
Hnh 3.8 S khi m phng matlab
Hnh 3.9 Kt qu m phng SVTH: Nguyn Vn Chung Lp TB-T1-K51 36
Chng 4. NGHIN CU CC MODULE C BN CA DSPIC33FJ12MC202

4.1 Tng quan v vi iu khin dsPIC33FJ12MC202:
Microchip l nh nh sn xut vi iu khin v cc thit b bn dn hng u th gii. Microchip ch trng vo cc sn phm p ng nhu cu ca th trng i u khin nhng. Hin nay Microchip l nh cung cp dn u v cc sn phm sau:
Vi iu khin 8 bit thng dng (PICMCUs) Cc vi iu khin 16 bit v 32 bit Cc b iu khin tn hiu s dng dsPIC 16 bit. Cc b nh bn, chun v chuyn dng. Cc thit b bo v. Cc thit b cho nhng ng dng c bit. Cc dng dsPIC rt a dng, trong n ny, vi iu khin c s dng l dsPIC33FJ12MC202 vi cc thng s sau:
37
Thit k b nghch lu cho h thng UPS c kh nng kt ni li MCU dsPIC33FJ12MC202 c thit k da trn kin trc RISC, c th hot ng vi 40 MIPS (triu lnh/giy) di in p (3.0V- 3.6V), cng sut thp c th hot ng tc cao p ng c cc ng dng c yu cu tc tnh ton nhanh v yu cu chnh xc cao. Tp lnh gm c 83 ch lnh C b nh RAM l 1024 bytes, b nh FLASH l 12K. Hot ng ch ngun dao ng ngoi (External Clock) ti a l 40Mhz Hot ng ch dao ng thch anh tn s t 4Hhz-8Mhz vi cc cp nhn PLL(Phase Locked Loop) c th cu hnh vi cc b nhn khc nhau ty theo cch thit lp chng trnh m dao ng thc s a vo trong MCU c th ln n 80Mhz. MCU dsPIC33F c 118 ngun ngt, mi ngun ngt c 7 cp ngt u tin Gm c 2 port I/O (A,B) (cng vo/ ra) 3 b Timer/Counter 16 bits, trong c th ghp li vi nhau thnh cc b Timer/Counter 32 bits c tch hp cc moudle Compare/ Capture, c 8 knh PWM Moudle I2C h tr ch Multi-Master/Slave, 7 bits/10 bits xc nh a ch Ngoi ra cn tch hp cc chun giao tip CAN, UART v 3-wire SPI 6 knh 10 bits - Analog to Digital Converter tc cao (1.1 Msps) hoc 12 bits tc 500 Ksps, c kh nng chuyn i trong lc MCU trng thi Sleep, Idle.
4.2 Cu trc vi iu khin :

Parameter Name Thng s Value (Gi tr) 38
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Architecture CPU Speed (Microchips) Memory Type Program Memory (KB) RAM Bytes Temperature Range C Operating Voltage Range (V) I/O Pins Pin Count System Management Features Internal Oscillator Digital Communication Peripherals Analog Peripherals Cc ngoi vi tng t Cu trc Tc CPU Dng b nh Dung lng b nh S byte RAM Di nhit hot ng Di in p hot ng S chn vo/ra Tng s chn Tnh nng qun l h thng B dao ng ni Cc ngoi vi giao tip s 7.37 MHz, 512 kHz 1-UART, 1-SPI, 1I2C 1-A/D 6x10-bit @ 1100(ksps) 16-bit PWM resolutions Tc x l PWM 16 16-bit 40 Flash 12 1,024 -40 to 125 3 to 3.6 21 28 PBOR
39
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Motor Control PWM Channels Timers Cc knh PWM iu khin ng c B nh thi 3 x 16-bit 1 x 32-bit 8
Hnh 4.1 S chn ca dsPIC33FJ12MC202
4.3 T chc b nh:

Vng nh chng trnh c t chc thnh cc khi truy cp c theo t. Mc d c coi l c rng 24 bits nhng chng ta nn coi mi a ch ca b nh chng trnh g m c t thp v t cao, trong nhng byte cao ca t cao khng c s dng. T thp lun lun c a ch chn trong khi t cao lun c a ch l. Vng nh d liu: CPU ca dsPIC33FJ12MC202 c vng nh d liu 16 bits ring bit. Vng nh d liu c truy cp bng cch s dng khi pht a ch (Address Generation SVTH: Nguyn Vn Chung Lp TB-T1-K51 40
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Units) c v ghi cc php tnh ton. Bn b nh d liu c cho hnh d i y:
16 bits MSB address 0x0001 2 Kbyte SFR Space SFR Space 0x07FF 0x0801 X Data RAM(X) 1 Kbyte SFR Space 0x09FF 0x0A01 Y Data RAM(Y) 0x0BFF 0x0C01 0x01FFF 0x2001 0x0BFE 0x0C00 0x1FFE 0x2000 0x07FF 0x0801 0x07FE 0x0800 8 Kbyte Near Data Space LSB address 0x0000
MSb
LSb
0x800 1 X Data unimplemented (X)
0x8000
0xFFFF
0xFFFE
Hnh 4.2 T chc b nh ca dsPICFJ12MC202
4.4 Khi qut v cc thanh ghi:

Tt c cc chn I/O trn MCU ( ngoi tr cc chn VDD, VSS, AVDD, AVSS, MCLR, OSC1/CLK1) c th va ng vai tr l chc nng tng qut (General Purpose) va c ng vai tr s dng t bit. Cc chc nng tng qut cho php dsPIC33F gim st v iu khin cc thit b khc. Hu ht cc I/O u c kt hp nhiu chc nng ring bit khc nhau. S kt hp cc chc nng ny ty thuc vo SVTH: Nguyn Vn Chung Lp TB-T1-K51 41
Thit k b nghch lu cho h thng UPS c kh nng kt ni li c im trn loi MCU xc nh. V khi mt I/O c s dng vi chc nng chuyn bit th I/O c th s khng th c s dng vi chc nng tng qut. 4.4.1 Cc thanh ghi iu khin : Tt c cc I/O Port trong MCU thuc h 12F, 16F,18F,30F ... u c 3 thanh ghi trc tip lin quan n phng thc hot ng ca cc Port , cc thanh ghi l TRISx, PORTx, LATx, trong x l tn tng ng ca cc Port trong MCU. Mi chn I/O u c mt bit tham chiu tng ng trong ba thanh ghi trn. 4.4.2 Thanh ghi TRIS: Cc bits iu khin trong thanh ghi TRIS xc nh trng thi hot ng ca cc I/O l input hay output. Nu bit TRIS ca mt I/O l 1 th I/O s ng vai tr nh l mt ng input, ngc li nu bit TRIS ca mt I/O l 0 th I/O s ng vai tr nh l mt ng output. iu cn lu l tt c cc I/O s ng vai tr l input ngay sau khi MCU b Reset. 4.4.3 Thanh ghi PORT: D liu trn mt I/O c truy xut thng qua thanh ghi PORT, s kin c thanh ghi PORTx s c gi tr ca ca I/O tng ng v s kin ghi vo thanh ghi PORTx s ghi gi tr vo Port cht d liu. Mt s lnh nh BSET v BCLR l cc lnh cho php Read-Modify-Write d liu trn cc Port. Vic ghi vo mt Port ngha l cc I/O ca Port s c c vo, gi tr s c hiu chnh li, sau c ghi vo Port cht d liu.Mt iu cn ch l khi cc lnh Read- Modify-Write s dng trn mt thanh ghi PORTx th cc I/O c lin quan c a Port phi c cu hnh nh l ng input. Nu mt I/O c cu hnh nh l ng input b chuyn sang cu hnh l output
42
Thit k b nghch lu cho h thng UPS c kh nng kt ni li trong khi thc hin cc lnh Read-Modify-Write th s dn n nhng kt qu khng mong mun trn I/O . 4.4.4 Thanh ghi LAT: Thanh ghi LATx lin quan n mt chn I/O hn ch cc s c c th xy ra i vi cc lnh Read-Modify-Write. Vic c thanh ghi LAT s tr v gi tr c ct gi trong Port cht ng ra ( Port output latches), thay v gi tr trn chn I/O port. Lnh Read-Modify-Write trn thanh ghi LAT, lin quan n mt I/O, trnh kh nng ghi gi tr ca chn input vo Port cht. V trnh t ghi vo thanh ghi LATx cng tng t nh trn. S khc nhau gia thanh ghi PORT v LAT c th c tm tt nh sau: Vic ghi vo thanh ghi PORTx s ghi gi tr d liu vo Port cht (Port latch) Vic ghi vo thanh ghi LATx s ghi gi tr d liu vo Port cht Vic c t thanh ghi PORTx s c gi tr d liu trc tip trn chn I/O Vic c t thanh ghi LATx s c gi tr d liu c ct gi trong Port cht.
4.5 Gii thiu cc module c bn

4.5.1 Module to dao ng ca dsPIC33FJMC202 (oscillator) : Cu trc b dao ng: H thng b dao ng ca h dsPIC33F c cc c im sau: - Ty chn gia 4 b dao ng ngoi v 1 b dao ng ni. - B nhn tn s y tn s lm vic trong vi iu khin ln ti tn s ngu n dao ng ngoi (ni) chn. - Cng tc chuyn i gia cc ngun dao ng. SVTH: Nguyn Vn Chung Lp TB-T1-K51 43
Thit k b nghch lu cho h thng UPS c kh nng kt ni li - Ch tit kim in (doze mode) Ngun dao ng ca h thng c th c cung cp bi 1 trong cc ngun sau: - Ngun dao ng s cp (POSC) cc chn OSC1 v OSC2. - Ngun dao ng th cp (SOSC) cc chn SOSC1 v SOSC2. - B dao ng FRC (Internal Fast RC) - B dao ng LPRC (Internal Low Power RC) Cu hnh cho b nhn tn s: Cc ngun dao ng POSC v FRC c th s dng 1 b nhn tn s tch hp trn chip (Phase Locked Loop) t c tc lm vic cao hn. S khi b nhn tn s cho hnh sau:
0.8<Fref<8.0 MHz
100<Fvco<200 MHz
Fosc<80 MHz
FIN N1
FREF PFD VCO
FVCO N2
Fosc
M
PLLPOST<1:0>
PLLDIVE<8:0>
Hnh 4.3 Cu trc b nhn tn s b PLL hot ng chnh xc, tn s u vo trc khi PFD (Phase Frequency Detector) v tn s u ra sau khi VCO phi p ng cc yu cu sau : - Tn s u vo trc khi PFD (FREF) phi nm trong di 0.8-8.0 MHz - Tn s u ra sau khi VCO (FVCO) phi nm trong di 100-200 MHz SVTH: Nguyn Vn Chung Lp TB-T1-K51 44
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Bit PLLPRE<4:0> trong thanh ghi chia tn s (CLKDIV<4:0>) xc nh t s chia u vo (N1), c dng gim tn s u vo (FIN)sao cho tha mn c yu cu: tn s u vo khi FPD n m trong di 0,8-8MHz. Bit PLLDIV<8:0> trong thanh ghi chia phn hi (Clock Divisor register PLLFBD<8:0>) xc nh t s M, dng xc nh t l gim FVCO cho tn hiu ph n hi ca khi PFD: FVOC = M.FREF. Bit PLLPOST<1:0> trong thanh ghi chia tn s (CLKDIV<7:6>) xc nh t s chia N2, dng gii hn FOSC ngng di 80 MHz. Phng trnh sau th hin mi quan h gia FIN v FOSC:
FOSC FIN ( M ) N1.N 2 FIN ( PLLDIV 2 ) ( PLLPRE 2).2.( PLLPOST 1)
Trong :
N1 = PLLPRE+2 N2 =2.(PLLPOST +1) M = PLLDIV+2
Phng trnh th hin mi quan h gia FIN v FVCO:
FVCO
FIN (
M ) N1
FIN (
PLLDIV 2 ) PLLPRE 2
Thit lp b nhn tn s hot ng vi b dao ng s cp POSC: Di y l quy trnh thit lp b nhn tn s c th s dng vi iu khin tc 40Mbps vi thch anh gn ngoi (tn s dao ng 10MHz): 1. thc hin lnh 40MHz, cn m bo rng tn s dao ng ca h thng l: FOSC = 2.FCY = 80MHZ. SVTH: Nguyn Vn Chung Lp TB-T1-K51 45
Thit k b nghch lu cho h thng UPS c kh nng kt ni li 2. m bo rng gi tr reset mc nh ca PLLPRE, PLLPOST v PLLDIV phi ph hp vi b PLL v yu cu ca ngi dng. 3. Nu b PLL ph hp vi yu cu ca ngi dng, ta cu hnh trc tip bit FNOSC<2:0 v FOSCSEL<2:0> s dng POSC vi b PLL ti ngay trng thi POR. Nu b PLL cha ph hp vi yu cu ca ngi s dng, ta thao tc theo cc bc sau: - La ch t l chia u ra PLL p ng yu cu ca tn s u ra FVCO (100<FVCO<200 MHz). - La chn t l chia u vo PLL p ng yu cu ca tn s u vo kh i PFD (0,8<FREF<8MHz). - La chn t l chia phn hi PLL to ra tn s FVCO da trn tn s PFD u vo. - Cu hnh bit FNOSC<2:0> v FOSCSEL<2:0> la chn ngun pht xung khng km b PLL (v d: b dao ng ni FRC) ti trng thi POR. 4.5.2 Module ADC : a) Tm lc chung v module ADC B chuyn i ADC tc cao cho php chuyn i tn hiu vo tun t sang 10 bits hoc 12 bits tn hiu s (high-speed analog to digital converter). Module ADC ny da trn kin trc Succesive Approximation Register (SAR) v cung cp kh nng ly mu ti a 1.1 Msps (vi ch 10bits) hay 500 Ksps vi ch 12 bits. Module ADC c 6 ng vo analog . in p tham chiu cho module ADC c la chn bng phn mm, c th l chnh ngun cung cp cho MCU
46
Thit k b nghch lu cho h thng UPS c kh nng kt ni li (AVDD/AVSS) hoc mc in p trn cc chn ( VREF+/VREF-) . B ADC c kh nng hot ng khi CPU ang trong trng thi ng (Sleep Mode) Module ADC c iu khin bi vic thit lp cho cc thanh ghi sau : AD1CON1: ADC1 CONTROL REGISTER 1 AD1CON2: ADC1 CONTROL REGISTER 2 AD1CON3: ADC1 CONTROL REGISTER 3 AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW Module bao gm b nh m kp 16-word (16-word dual port read-only buffer), y l b nh ch c dng cha gi tr ca vic chuyn i tng t - s. Ni dung ca 16 thanh ghi trong b nh m ( t ADCBUF0 n ADCBUFF) khng th dc ghi vo bi ngi s dng. Sau khi Module ADC c thit lp xong, vic thu thp mu c bt u bng vic set bit SAMP. Mt s tc ng nh l cc bit lp trnh (Programable bit), s kin ngoi (external events), trn timer (timer time-out), s kt thc vic thu thp mu v bt u qu trnh chuyn i. Khi s chuyn i hon tt, kt qu s c a vo cc thanh ghi trong b nh m t ADCBUF0ADCBUFF. C bo ADIF v bit DONE s c set sau mt s ln ly mu c xc nh bi bit SMPI b) Khi to hot ng cho module ADC :
47
Thit k b nghch lu cho h thng UPS c kh nng kt ni li 1. La chn chn dng c tn hiu ADC . iu ny c thc hin thng qua vic cu hnh cc thanh ghi ADxPCFGH<15:0> hoc thanh ghi ADxPCFGL<15:0>. 2. La chn in p tham chiu ph hp vi gii gi tr ADC u vo. Vic ny c thc hin da vo cu hnh cho thanh ghi ADxCON2<15:13>. 3. La chn xung clock cho hot ng ca b ADC da vo thanh ghi ADxCON3<7:0>. 4. Thanh ghi ADxCON2<9:8> v thanh ghi ADxPCFGH<15:0> ho c thanh ghi ADxPCFGL<15:0> quyt nh xem bao nhiu qu trnh ly mu v gi mu xy ra trn mt ln ngt. 5. Vic la chn tun t ly mu trong trng hp ta cn s dng nhiu tn hiu ADC u vo s c cu hnh trong thanh ghi ADxCON1<7:5> v ADxCON3<9:8>. 6. La chn cch lu gi tr chuyn i ADC vo thanh ghi m (buffer) c thc hin bng cch cu hnh trong thanh ghi ADxCON1<9:8>. 7. Bit n m trong thanh ghi ADxCON1<15> s khi ng module ADC hot ng. 8. Cu hnh cho ngt ADC gm hai th tc nh sau : - Xa bit ADxIF - La chn u tin ngt ADC. c) Tun t chuyn i mu nh sau :
48
+ -
+ -
SAR ADC
Sample Time SOC Trigger
Conversion Time
Hnh 4.4 Trnh t trch mu v chuyn i Theo hnh v trn ta c trnh t nh sau : 1. Tn hiu in p u vo c kt ni vi t ly mu. 2. T ly mu b ngt kt ni vi u vo 3. in p lu gi trong t ly mu s c chuyn i tng ng thnh gi tr s. d) Thi gian ly mu : iu ny ph thuc vo cch la chn gi tr np vo bit ADxCON1<2> : ASAM 0 1 e) Thi gian chuyn i : Thi gian chuyn i ph thuc vo vic ta la chn phn gii cho gi tr ADC ( 12bit hoc 10bit ) v xung clock dng cung cp cho b ADC . i vi b ADC 10bit : TCONV =12.TAD SVTH: Nguyn Vn Chung Lp TB-T1-K51 49 Start of Sampling Selection Trch mu bng tay Trch mu t ng
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Trong : TCONV = Conversion Time (Thi gian chuyn i) TAD = Chu k b ADC i vi b ADC 12bit : TAD c xc nh nh sau : TCONV = 14.TAD
TCY
0 ADC Clock (TAD)
ADCS<7:0>
ADC Internal RC
ADRC
Hnh 4.5 Cng thc xc nh chu k hot ng ca b ADC Khi ADCS=1 th TAD =TCY.(ADCS+1) Trong : TCY l tn s m lnh. Gi tr ca ADRC c np vo bit 15 ca thanh ghi AD1CON3 f) Hm chuyn i ADC v gi tr thc : Da vo gi tr in p max v min c a in p tham chiu ng thi phn gi i ta suy ra c gi tr thc.
50

Output code
11 1111 1111 (=1023) 11 1111 1111 (=1023)
(E)
10 0000 0011 (=515) 10 0000 0010 (=514)
(C) (B) (A)

00 0000 0001 (=1) 00 0000 0000 (=0)
(D) VREFL
VREFL
512
VREFH VREFL 1024

VREFL 1023
VREFH
VREFH VREFL 1024
VREFL
VREFH VREFL 1024
Hnh 4.6 Ch 10 bits

Output code
1111 1111 1111 (=4095) 1111 1111 1110 (=4094)
(E)
1000 0000 0011 (=2051) 1000 0000 0010 (=2050) 1000 0111 0111 0111 0000 1111 1111 1111 0001 1111 1110 1101 (=2049) (=2047) (=2046) (=2045)
0111 1111 1100 (=2044)
(C) (B) (A)
0000 0000 0001 (=1) 0000 0000 0000 (=0)
(D) VREFL
VREFL 2048 VREFH 4096
VREFL
VREFL
1023
VREFH
VREFH 4096 VREFL
VREFL
VREFH VREFL 4096
Hnh 4.7 Ch 12 bits SVTH: Nguyn Vn Chung Lp TB-T1-K51 51
Thit k b nghch lu cho h thng UPS c kh nng kt ni li 4.5.3 Module Timer: MCU dsPIC33FJ12MC202 cung cp 3 module timer 16 bits, mi module Timer/Counter 16 bit u c cc thanh ghi ch c( Reable/Writeable Register): - TMRx: l thanh ghi 16 bit, dng lu gi tr hin ti ca Timer tng ng. - PRx: l thanh ghi 16 bit, dng np gi tr m cho Timer. - TxCON: l thanh ghi iu khin 16 bit, dng thit lp cc thng s iu khin, ch hot ng ca Timer. Mi Module Timer u c cc bits lin quan dng cho phc v ngt: - Interrupt Enable Control bit(TxIE): kch hot hoc ngng kch hot Timer. - Interrupt Flag Status bit(TxIF): bo khi trn b m. - Interrup Priority Control bit( TxIP): t cc mc u tin cho ngt Timer. Cc timer c phn thnh cc loi sau: Module Timer 1: Timer 1 module l mt timer 16 bits , c th c s dng lm b m thi gian cho thi gian thc (Real Time Clock), hoc c th c vn hnh nh l b nh thi ni b (interval timer), b m (counter), b 16-bits Timer1 c cc ch : - Ch nh thi 16 bits (16-bits Timer) - Ch b m ng b 16 bits (16-bits Synchronous Counter) - Ch b m bt ng b 16 bits (16-bits Asynchronous Counter) S kin ngt Timer: 16-bit TIMER c kh nng to ra ngt . Khi gi tr ca Timer bng vi gi tr trong thanh khi PR1 th bit T1IF s c tc ng v to ra ngt. V nu c kch hot, bit T1IF phi c xo bng phn m m. C ngt Timer T1IF c t trong thanh ghi iu khin IFS0 . SVTH: Nguyn Vn Chung Lp TB-T1-K51 52
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Module Timer 2/3: Module Timer 2/3 l mt 32-bit Timer v c th c thit lp thnh 2 Timer 16 bits ring bit l Timer 2 v Timer 3, trong Timer 2 thuc loi Timer B (typeB) v Timer 3 thuc loi Timer C (type C) S kin ngt Timer: 32-bit TIMER c kh nng to ra ngt khi gi tr ca Timer bng vi mt gi tr nh trc c np vo thanh ghi 32 bit PR2/PR3 hoc khi pht hin c c sn xung t cng tn hiu bn ngoi.Bit T3IF (IFS0<7>) s c tc ng v to ra ngt.Trong ch ny, T3IF c s dng nh l ngun to ngt v bit T3IF phi c xo bng phn mm. Vic kch hot hot ng ca ngt c thc hin thng qua bit T3IE<ICE0<7>)( Timer Interrup Enable) 4.5.4 Module PWM : DsPIC33FJ12MC202 c 2 Module PWM l MCPWM1 v MCPWM2 a) Tng quan chung v Module MCPWM1: Module MCPWM1 thng dng pht ra chui xung ng b vi u ra. Di y l cc ng c v b ngun thc t c h tr bi MCPWM1 : ng c phn khng ng c BLDC B ngun lin tc (UPS) Cc tnh nng c bit ca khi MCPWM c tm lc nh sau : C n 8 u ra PWM vi bn u ra lm nhi m v iu bin rng xung . C phn cng ring to ra ngun pht Dead time. Th t u tin cc chn u ra c cu hnh bi cc bit trong Vi iu khin. SVTH: Nguyn Vn Chung Lp TB-T1-K51 53
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Cc ch cho u ra v ch hot ng : Single event mode Edge-aligned mode Center-aligned mode Center-aligned mode with double updates Complementary output mode Independent output mode b) Tng quan chung v module MCPWM2: MCPWM2 cung cp cc ch Comlementary u ra ca PWM, iu ny th hu dng trong cc trng hp sau : Ngun PFC ( power factor correction) iu khin ng c mt chiu. c) M t cc thanh ghi ca Module PWM: Di y l cc thanh ghi thng c dng iu khin qu trnh hot ng ca b MCPWM1 v MCPWM2 : Thanh ghi PxTCON : Thanh ghi ny dng cu hnh tn s xung Clock u vo v tn s xung Clock u ra . Thanh ghi PxTMR : Thanh ghi ny dng m, cho bit gi tr m tc thi thng qua gi tr hin ti ca n. Thanh ghi PxTPER : Vic np gi tr vo thanh ghi ny s quyt nh tn s ca b PWM (fPWM) .
54
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Thanh ghi PxSECMP: Thanh ghi ny cung cp gi tr so snh v i PxTMR, m ti s xy ra qu trnh chuyn i ADC ng b vi b PWM. Thanh ghi PWMxCON1: y l thanh ghi nhm cu hnh ch Independent hoc Comlementary u ra. Thanh ghi PWMxCON2 : Thanh ghi ny cung cp cc chc nng di y : - La chn gi tr np vo thanh ghi s kin c bit. - La chn chc nng update tc thi. - La chn ch update ng b. Thanh ghi PxDTCON1: Thanh ghi ny gip cu hnh khong deadtime ph hp vi yu cu mong mun Cc thanh ghi cu hnh rng xung : PxDC1: gi tr rng xung 16 bit ca cp 1 c vit vo thanh ghi ny. PxDC2: gi tr rng xung 16 bit ca cp 2 c vit vo thanh ghi ny. PxDC3: gi tr rng xung 16 bit ca cp 3 c vit vo thanh ghi ny. PxDC4: gi tr rng xung 16 bit ca cp 4 c vit vo thanh ghi ny. d) Tng quan chung v kin trc module MCPWM:
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Gated Period Load
PWM Period Buffer
PWM Period Register (PxTPER) Period Compare
Zero Match Time Base 1:1 1:4 Input 1:16 Prescaler 1:64 Period Match
PTMOD<1:0>
Tcy
Clock Control Logic
PTMR Clock
PWM Timer Register (PxTPER)
Zero Detect
0
Timer Direction Control
PTMOD1 UDIS (Update Disable) UDIS (Immediate Update Enable) Period Match PWM Interrupt Flag (PWMxIF) Gated Duty Cycle
Time Base 1:1 Out put 1:4 Postscaler 1:16
Interrupt Control
PTMOD<1:0>
Hnh 4.8 Kin trc Module PWM Nguyn l hot ng nh sau : Thng qua b chia tn s u vo ta c th xc nh c tn s nui cho b PWM l bao nhiu (c cc t l so vi tn s m lnh 1:1, 1:4, 1:16, 1:64). Np gi tr vo thanh ghi PxTPER (nh ca xung tam gic) . Xem thanh ghi PxTMR nh mt bin m (tng dn gi tr t 0 cho ti gi tr np trong PxTPER). Thng qua b so snh 2 gi tr PxTPER v PxTMR ta s bit lc no 2 gi tr bng nhau. Khi 2 gi tr ny bng nhau th thanh ghi PxTMR s b Reset.
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li ng thi ti thi im ny n s qua b AND (kt hp vi UDIS ) hi xem c cho php update gi tr PxTPER mi hay khng. C hai thi im cho php update gi tr PxTPER mi l ti lc nh v ti lc bng khng (thng qua b so snh vi 0). Khi thanh ghi PxTMR bng 0 n s i qua b Postscaler hi xem c cho php ngt PWM hay khng. e) Duty Cycle: nh ngha : Duty Cycle (k hiu l d) l t s gia khong thi gian tch cc so vi mt chu k ca PWM. Module MCPWM c ti 4 ngun pht PWM. C 4 thanh ghi tng ng lin quan ti vic pht PWM l cc thanh ghi PxDCy. f) Ngun to Dead Time (Dead Time Generation): Ngun to Dead Time c t ng khi to khi cc cng u ra PWM hot ng ch b sung (Comlementary). C hai khong cn to Dead Time (ti sn ln v sn xung ca mi xung).
PWM generator
Dead time =0
None zero Dead time
Time selected by DTSxA bit (A or B)
Time selected by DTSxI bit (A or B)
Hnh 4.9 Hnh v m t chn Dead Time SVTH: Nguyn Vn Chung Lp TB-T1-K51 57
Zero Compare
TCY
Prescaler
Clock Control
6-bit Down Counter
High-side PWM signal to output pin Low-side PWM signal to output pin
Dead Time Select Logic Dead Time A PWM Generator Input Dead Time B
Hnh 4.10 S khi m t cu trc ca Dead Time Nguyn l hot ng chung : t ngun pht xung PWM (PWM Generator Input) ta s xc nh c sn ln v sn xung ca mi xung. Qua xc nh c v tr Dead Time cn chn. Cch cu hnh gi tr Dead Time vo chng trnh cho ph hp vi gi tr mong mun trong thc t : Qua b chia tn s u vo ta xc nh c tn s s dng cho b Dead Time (cu hnh vo thanh ghi PxDTCON1) . Xc nh gi tr cn np vo thanh ghi PxDTCON1bits.DTA hoc PxDTCON1bits.DTB, da vo cng thc sau :
DT
Trong :
DeadTime Pr escaleValue.TCY
TCY l tn s m lnh; PrescaleValue l t s chia tn s. DeadTime l thi gian cn to
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li V d : Ta mun to DeadTime c thi gian l 1 s Vi PrescaleValue = 1 v TCY = 10-6/40 Theo cng thc trn ta c :
DT
deadtime Pr escaleValueT . CY
10 6.40 1.10 6
40
g) Special Event Trigger : Module PWM c b Special Event Trigger cho php chuyn i ADC ng b vi PWM. V thun li ca n l c th cho php chuyn i ADC ti bt k khong no ca PWM. Nguyn tc hot ng c th m t bng s sau :
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REGISTER
PxTCON
PWM Time Base Control PWM Enable and Mode Selection
PxTCON PWMxCON1
PWMxCON2
PxDTCON1
16-Bit DATA BUS
PWM Deadtime Control

PxDTCON2
PxFLTACON
Fault Pin Control

PxFLTBCON
PxPOVDCON
Manual Override Control

Dead time Generator and Override Control
External Fault Signals FLTxA FLTxB PWMxHy PWMxLy
PxDCy Buffer
PxDCy Register
Driver
PWM Duty Cycle
PxTMR
PWM Output
PxTPER Buffer
PxTPER Register
PWM Timer Reset/Count Output
PxSECMP
SEVTDIR PTDIR
Special Event Trigger Postscaler
1:1 . . . 1:16
Special Event Trigger for A/D Conversions
Hnh 4.11 S nguyn l ca b Special Event Trigger Gii thch nguyn l: Np gi tr m ti cho php xy ra Special Event Trigger vo thanh ghi PxSECMP. Thng qua bin m PxTMR ta s bit c gi tr hin ti ca b PWM. SVTH: Nguyn Vn Chung Lp TB-T1-K51 60
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Khi gi tr PxTMR bng vi gi tr trong thanh ghi PxSECMP (bit c thng qua b so snh ) s pht ra tn hiu nhng tn hiu ny cho php xy ra Special Event Trigger th yu cu n phi tha mn 2 yu cu sau : Ta mong mun xy ra Special Event Trigger l sn ln hay sn xung bng cch cu hnh cho n thng qua bit SEVTDIR . Xem xt trn iu kin va nu vi gi tr thc t thng qua bin ng PTDIR h) Cch xc nh gi tr np vo thanh ghi PxTPER: Tng ng vi cc dng sng tam gic mong mun ta c cc cng thc tnh ton nh sau :
Gi tr chu k iu bin c np t thanh ghi m PxTPER
PxTMR PxTPER
Hnh 4.12 Cp nht chu k PWM trong ch m t do(Free running mode) Cch xc nh PxTPER:
PxTPER
FCY 1 FPWM .( PxTMR Pr escaler)
V d : Fcy = 40 MHz, Fpwm = 10 kHz PxTMR Prescaler = 1:4 SVTH: Nguyn Vn Chung Lp TB-T1-K51
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PxTPER FCY 1 FPWM .( PxTMR Pr escaler) 40000 1 999 10.4
Gi tr chu k iu bin c np t thanh ghi m PxTPER
PxTMR PxTPER
Hnh 4.13 Cp nht chu k PWM trong ch m ln/xung (up/down count mode) Cch xc nh PxTPER: V d :
PxTPER
FCY 1 FPWM .( PxTMR Pr escaler).2
Fcy = 40 MHz; Fpwm = 10 kHz PxTMR Prescaler = 1:4
PxTPER
FCY 40000 1 1 499 FPWM .( PxTMR Pr escaler).2 10.4.2
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Chng 5: TM HIU PHNG PHP HA NG B

5.1. Nhu cu ha ng b vo li
ng trc tnh trng thiu in nh hin nay, vic pht trin thm h thng nhng ngun in mi l mt nhu cu ht sc cp bch. Vn c cp y l: Lm th no c th ho chung in ca my pht in vo li in, sao cho an ton, nhanh chng, tit kim. lm c iu ny i hi phi o, kim tra s ng b in ca my pht v in ca li, sao cho ti thi im ng my ct: lch in p, lch tn s, lch pha ca hai h thng in ny phi nm trong gii hn cho php. Trong vic kim tra lch pha c coi trng nht v nu in p v tn s bng nhau nhng li ngc pha nhau th khng khc g hai vt th ang bay cng vn tc cng phng nhng li ngc chiu lao vo nhau, trong h thng in s c ny cn nghim trng hn c s c ngn mch. Ha ng b vo li c ng dng nhiu trong cc h thng nng lng mi nh pin mt tri, nng lng gi,...
5.2 Cc iu kin ha ng b
1. Tn s nghch lu to ra phi bng tn s li 2. in p to ra bng in p li 3. Trng pha vi li
5.3 Vng kha pha (Phase Locked Loop - PLL)

to ra sng sin ng pha vi li ta s dng mt vng kha pha (PLL) 5.3.1 Tng quan v vng kha pha SVTH: Nguyn Vn Chung Lp TB-T1-K51 63
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Vng kho pha PLL l h thng vng kn hi tip, trong tn hiu hi tip dng kho tn s v pha ca tn hiu ra theo tn s v pha tn hiu vo. Tn hiu vo c th c dng tng t hnh sine hoc dng s. ng dng u tin ca PLL vo nm 1932 trong vic tch sng ng b. Ngy nay, nh cng ngh tch hp cao lm cho PLL c kch thc nh, tin cy cao, gi thnh r, d s dng. k thut PLL c ng dng rng ri trong cc mch lc, tng hp tn s, iu ch v gii iu ch, iu khin t ng v.v... 5.3.2 S khi
Hnh 5.1 S khi ca Vng kha pha 5.3.2.1 B tch sng pha (phase detector): so snh pha gia tn hiu vo v tn hiu ra ca VCO to ra tn hiu sai lch
Hnh 5.2 Nguyn l hot ng b tch sng pha B i tn (mch nhn) thc hin nhn hai tn hiu. Ng ra ca n c in p:
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Thit k b nghch lu cho h thng UPS c kh nng kt ni li Qua b lc thng thp LPF, ch cn thnh phn tn s thp. Khi kha pha ( i= pha
0)
c Vd = Asin( i 0.
0).
in p ny t l vi bin in p vo A v sai
e= i
Nu
nh, hm truyn t ca b tch sng pha coi nh tuyn tnh.
5.3.2.2 Lc thng thp (Low pass filter): lc gn ca in p sai lch tr thnh in p bin i chm LPF thng l mch lc bc 1, tuy nhin cng dng bc cao hn trit thnh phn AC theo yu cu. LPF c th dng mch th ng hay tch cc.
Hnh 5.3 Mch lc thng thp Ng ra b tch sng pha gm nhiu thnh phn f0, fi, fi-f0, fi+f0, v.v... Sau LPF ch cn thnh phn tn s rt thp (fi-f0) n b khuch i iu khin tn s VCO bm theo fi. Sau vi vng iu khin hi tip PLL c ng b (kha pha) fi=f0 (tc l fi-f0=0). Vng kha pha hot ng chnh xc khi tn s vo fi, f0 thp khong vi trm KHz tr li. 5.3.2.3 VCO (Voltage Controlled Oscillator): L mch dao ng c tn s c kim sot bng in p. Yu cu chung ca mch VCO l quan h gia in p iu khin Vdk (t) v tn s ra f0(t) phi tuyn tnh. Ngoi ra mch cn c n nh tn s cao, di bin i ca tn s theo in p vo rng, n gin, d iu chnh v thun li cho vic t hp thnh vi mch (khng c in cm). SVTH: Nguyn Vn Chung Lp TB-T1-K51 65
Thit k b nghch lu cho h thng UPS c kh nng kt ni li V nguyn tc c th dng mi mch dao ng l tn s dao ng c th bin thin c trong phm vi t 10% n 50% xung quanh tn s dao ng t do. Tuy nhin cc b dao ng to xung ch nht c s dng rng ri v loi ny c th lm vic trong phm vi tn s kh rng (t 1MHz n khong 100MHz). Trong phm vi t 1MHz n 50MHz thng dng cc mch dao ng a hi.
Hnh 5.4 Mch VCO tiu biu 5.3.2.4 N : b chia
Dng chia nh tn s fN to ra bi VCO sao cho bng vi tn s vo fi. Khi PLL thc hin kho pha, th ta c fi = 5.3.3 Nguyn l hot ng Vng kho pha hot ng theo nguyn tc vng iu khin m i lng vo v ra l tn s v chng c so snh vi nhau v pha. Vng iu khin pha c nhim . Suy ra fN = fi.N = f0.N
66
Thit k b nghch lu cho h thng UPS c kh nng kt ni li v pht hin v iu chnh nhng sai s nh v tn s gia tn hiu vo v ra. Ngha l PLL lm cho tn s f0 ca tn hiu VCO bm theo tn s fi ca tn hiu vo. Khi khng c tn hiu Vi ng vo, in p sau lc thng thp Vdc(t) =0, b dao ng VCO hot ng tn s t nhin fN c ci t bi in tr, t in ngoi. Khi c tn hiu vo Vi, b tch sng pha so snh pha v tn s ca tn hiu vo vi tn hiu ra ca VCO. Ng ra b tch sng pha l in p sai lch V d(t), ch s sai bit v pha v tn s ca hai tn hiu. in p sai lch Vd(t) c lc ly thnh phn bin i chm Vdc(t) nh b lc thng thp LPF, tn hiu ny cng chnh l tn hiu iu khin Vdk(t) a n ng vo VCO, iu khin tn s VCO bm theo tn s tn hiu vo. n khi tn s f0 ca VCO bng tn s fi ca tn hiu vo, ta ni b VCO bt kp tn hiu vo. Lc by gi s sai lch gia 2 tn hiu ny ch cn l s sai lch v pha m thi. B tch sng pha s tip tc so snh pha gia 2 tn hiu iu khin cho VCO hot ng sao cho s sai lch pha gia chng gim n gi tr b nht. 5.3.4 Di bt v di kha Di bt BC (Capture range): k hiu BC=f2- f1, l di tn s m tn hiu vo thay i nhng PLL vn t c s kho pha, ngha l b VCO vn bt kp tn s tn hiu vo. Ni cch khc, l di tn s m tn hiu vo ban u phi lt vo PLL c th thit lp ch ng b (ch kha).
Hnh 5.5 Di bt v di kha ca PLL SVTH: Nguyn Vn Chung Lp TB-T1-K51 67
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Gi s mch PLL t c ch kho, VCO ng b vi tn hiu vo. By gi ta thay i tn s tn hiu vo theo hng ln hn tn s VCO th VCO s bm theo. Tuy nhin khi tng n mt gi tr no th VCO s khng b m theo c na v quay v tn s t nhin ban u ca n. Ta lm tng t nh trn nhng thay i tn s tn hiu vo theo hng nh hn tn s VCO. n mt gi tr no ca tn s tn hiu vo th VCO s khng bm theo c na v cng tr v tn s t nhin ca n. Di gi tr tn s t thp nht n cao nht ca tn hiu vo c gi l di kho. T ta nh ngha: Di kha BL (Lock range): BL=fmax- fmin, l di tn s m PLL ng nht c tn s f0 vi fi. Di ny cn gi l ng chnh (Tracking range). Cc tn s fmax, fmin l tn s cc i v cc tiu m PLL thc hin c kha pha (ng b). Di kha ph thuc hm truyn t ( li) ca b tch sng pha, khuch i, VCO. N khng ph thuc vo p tuyn b lc LPF v khi PLL kha pha th fi- f0= 0. Khi PLL cha kha pha th fi f0, khi PLL kha phath fi= f0. ch kha pha, dao ng f0 ca VCO bm ng b theo fi trong di tn kha BL rng hn di tn bt BC. p ng ca vng PLL c tnh i xng, ngha l tn s t nhin ti trung tm ca di kho v di bt. 5.3.5 Vng kha pha s dng IC4046 to mt mch kha pha, ta dng 1 IC cng l IC4046 (y l loi IC kh ph bin, gi thnh r v c th mua d dng). Mch kha pha dng IC4046 l mch gm 1 b VCO tuyn tnh v 2 b so snh pha
68
Hnh 5.6 S chc nng 4046 Cc in tr R1, R2 v t C1 to ra tn s f0 ca b VCO. Ta c th tnh gi tr cc t in v in tr ny hoc c th tra ra t th. y, to ra tn s fN = 50kHz ta tra th sau tm ra gi tr in tr v t in ph hp:
69
Hnh 5.7 th tn s trung tm fN vi R2 = T th ta tra ra c R1 = 100k , R2 = , C1= 200pF
f0 = fi = 50Hz th ta cn c b chia vi N = 1000, ta c th dng 3 IC4017(chia 10) mc ni tip. Tnh ton b lc thng thp: B lc thng thp dng ct b cc tn s cao fi, f0,... SVTH: Nguyn Vn Chung Lp TB-T1-K51 70
Thit k b nghch lu cho h thng UPS c kh nng kt ni li Tn s ct c tnh nh sau: fc = Chn fc = 5Hz, C2 = 1 F => R3 = 31,8k Vy s mch PLL vi IC4046 nh sau: => Ly R3 = 33k
Hnh 5.8 Mch PLL vi IC4046 Sng sin 50Hz t li c a vo chn 14 ca IC4046 qua 1 op -apm. T C1 v R1 to ra tn s 50kHz chn 4, qua 3 IC chia 4017 s c tn s 50Hz a v chn 3 so snh vi sng sin chun ca li. Xung 50Hz v 50kHz c ly ra a vo dsPIC (nh s ).
71
Hnh 5.9 ng pha gia 2 xung 50Hz ti chn 3 v chn 14 SVTH: Nguyn Vn Chung Lp TB-T1-K51 72
Chng 6: M HNH V KT QU O C
Hnh 6.1 Phn mch iu khin
Hnh 6.2 Phn mch lc SVTH: Nguyn Vn Chung Lp TB-T1-K51 73
Hnh 6.3 Dng in p u ra
74
KT LUN
Qua mt thi gian nghin cu v thit k b nghch lu c th nhn thy tnh kh thi trong vic ng dng vo thc t. Vic ch to th nghim b nghch lu t c mt s kt qu nht nh. Nhng kt qu c th t c trong n ca em nh sau: - Xy dng m hnh tnh ton i tng - Xy dng b iu khin PD - M phng trn Matlab/Simulink - iu ch ra sng sin chun - Xy dng vng kho pha Hng pht trin ca ti: - Hon chnh vng phn hi ho ng b - Nng cao hiu sut b nghch lu - Nghin cu th nghim b nghch lu 3 pha.
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PH LC 1: CHNG TRNH VIT CHO VI IU KHIN

/*----------------------------------------------------------------------------------------------------------------------------------------*/ // DO AN TOT NGHIEP //
//-----------------------------------------------------------------------------------------------------------------------------------------// // De tai: Thiet ke bo nghich luu cho he thong UPS c kha nang ket noi luoi //
//-----------------------------------------------------------------------------------------------------------------------------------------// // Giang vien huong dan : // Dong huong dan // Sinh vien thuc hien // Lop : : Ths Hoang Anh Ths Nguyen Thanh Khang Nguyen Van Chung // // // //
: Thiet bi dien Dien tu 1 - K51 DHBKHN
/*----------------------------------------------------------------------------------------------------------------------------------------*/
#include<P33FJ12MC202.h> _FOSCSEL(FNOSC_PRIPLL&IESO_OFF); //dung dao dong ngoai co bo PLL _FOSC(FCKSM_CSDCMD&OSCIOFNC_OFF&POSCMD_XT); //chon che do XT _FWDT(FWDTEN_OFF); //tat watchdog _FPOR(PWMPIN_ON & HPOL_OFF & LPOL_OFF); // cac chan ra dieu khien boi PORT luc reset deu co the cao //-----------------------------------------------------------------------------//Cac hang so cua chuong trinh (gia tri tuc thoi dung trong chuong trinh) #define Fcy 40000000 //Tan so thuc thi lenh Fcy = 40 MHz #define Fpwm 10000 //Tan so PWM = 10 kHz #define TS 499 //Cac prototype cho cac chuong trinh con void Init_PORTS(void); void Init_MCPWM(void); void Init_ADC10(void); void Read_ADC (void);
76

//bien toan cuc float V, vmax, hs, e1, voffset, kp, kd, vref, vadc, v1, vph, vthuc, e, p, d, u, edel;
unsigned int i=0; float const sin_table[200] = {0, 0.0314, 0.0628, 0.0941, 0.1253, 0.1564, 0.1874, 0.2181, 0.2487, 0.279, 0.309, 0.3387, 0.3681, 0.3971, 0.4258, 0.454, 0.4818, 0.509, 0.5358, 0.5621, 0.5878, 0.6129, 0.6374, 0.6613, 0.6845, 0.7071, 0.729, 0.7501, 0.7705, 0.7902, 0.809, 0.8271, 0.8443, 0.8607, 0.8763, 0.891, 0.9048, 0.9178, 0.9298, 0.9409, 0.9511, 0.9603, 0.9686, 0.9759, 0.9823, 0.9877, 0.9921, 0.9956, 0.998, 0.9995, 1, 0.9995, 0.998,0.9956, 0.9921, 0.9877, 0.9823, 0.9759, 0.9686, 0.9603, 0.9511, 0.9409, 0.9298, 0.9178, 0.9048, 0.891, 0.8763, 0.8607, 0.8443, 0.8271, 0.809, 0.7902, 0.7705, 0.7501, 0.729, 0.7071, 0.6845, 0.6613, 0.6374, 0.6129, 0.5878, 0.5621, 0.5358, 0.509, 0.4818, 0.454, 0.4258, 0.3971, 0.3681, 0.3387, 0.309, 0.279, 0.2487, 0.2181, 0.1874, 0.1564, 0.1253, 0.0941, 0.0628, 0.0314, 0, -0.0314, -0.0628, -0.0941, -0.1253, -0.1564, -0.1874, -0.2181, -0.2487, -0.279, -0.309, -0.3387, 0.3681, -0.3971, -0.4258, -0.454, -0.4818, -0.509, -0.5358, -0.5621, -0.5878, -0.6129, -0.6374, -0.6613, -0.6845, 0.7071, -0.729, -0.7501, -0.7705, -0.7902, -0.809, -0.8271, -0.8443, -0.8607, -0.8763, -0.891, -0.9048, -0.9178, 0.9298, -0.9409, -0.9511, -0.9603, -0.9686, -0.9759, -0.9823, -0.9877, -0.9921, -0.9956, -0.998, -0.9995, -1, -0.9995, -0.998, -0.9956, -0.9921, -0.9877, -0.9823, -0.9759, -0.9686, -0.9603, -0.9511, -0.9409, -0.9298, -0.9178, -0.9048, 0.891, -0.8763, -0.8607, -0.8443, -0.8271, -0.809, -0.7902, -0.7705, -0.7501, -0.729, -0.7071, -0.6845, -0.6613, 0.6374, -0.6129, -0.5878, -0.5621, -0.5358, -0.509, -0.4818, -0.454, -0.4258, -0.3971, -0.3681, -0.3387, -0.309,0.279, -0.2487, -0.2181, -0.1874, -0.1564, -0.1253, -0.0941, -0.0628, -0.0314}; //-----------------------------------------------------------------------------//Chuong trinh chinh int main(void) { V=220; vmax=V*1.41; hs=3.6; e1=0; voffset =1.65; kp= 1.85217285; kd= 1473.91; PLLFBD=41; // M=43 CLKDIVbits.PLLPOST=0; // N1=2 CLKDIVbits.PLLPRE=0; // N2=2 while (_COSC !=0b011); //dung bo PLL tao Fosc=80MHz,cho` cho dao dong on dinh while (_LOCK !=1); //Cho PLL bat dau khoa pha Init_PORTS(); //Khoi tao cac cong I/O Init_MCPWM(); //Khoi tao module PWM Init_ADC10(); //Khoi tao module ADC
77

Read_ADC(); while (1); } //Chuong trinh con khoi tao cac cong I/O, de xuat cac tin hieu PWM, va doc tin hieu dieu chinh cua bien tro tai AN0 void Init_PORTS(void) { TRISB = 0xFFC0; //Cac tin hieu PWM nam tai RB10..RB15 TRISA = 0x0001; //Chan RA0 la ngo vao analog AN0, cac chan khac la ngo ra } //Chuong trinh con khoi tao module PWM void Init_MCPWM(void) { P1TCONbits.PTMOD=0b10; //Che do Continous up/down count P1TCONbits.PTOPS=0; //Postscale 1:1 P1TCONbits.PTCKPS=0b01; //Prescale 4TCY P1TPER = TS; //Tan so PWM = 10 kHz //P1TPER=Fcy/(Fpwm*(2*PxTMR Prescaler))-1 //P1TPER=40*10^6/((10*10^3)*2*4)-1=499 PWM1CON1bits.PEN1L = 1; //khoi tao cac chan PWM PWM1CON1bits.PEN2L = 1; PWM1CON1bits.PEN1H = 1; PWM1CON1bits.PEN2H = 1; P1OVDCON = 0xFF00; //Khong dung overdrive P1DTCON1bits.DTAPS=0; //Dead time prescale 1:1 P1DTCON1bits.DTA=40; // DT = (Dead time)/(Prescale Value*Tcy) // Dead time = 1us, Prescale Value = 1, Tcy = 1/(40*10^6) // DT = (1*10^-6)/(1*1/(40*10^6)) = 40 P1DC1 = 0; //Khoi tao PWM1 P1DC2 = 0; P1TCONbits.PTEN = 1; //Kich hoat module PWM
78

} //Chuong trinh con khoi tao module chuyen doi A/D, doc ngo vao AN0 void Init_ADC10(void) { AD1PCFGL = 0xFFFE; //Cac chan khac la digital, chan AN0/RA0 la analog AD1CON1bits.SAMP = 1; AD1CON1bits.ASAM = 1; // lay mau ngay lap tuc sau chuyen doi cuoi AD1CON1bits.SSRC = 0b011; //Module PWM cham dut lay mau va kich hoat viec chuyen // i A/D AD1CHS0 = 0; //Kenh 0 doc tin hieu giua AN0 va AVss AD1CSSL = 0; //Khong quet cac ngo vao AD1CON3bits.SAMC = 0b00001; //Dung 1 TAD cho lay mau AD1CON3bits.ADCS = 0x03; // TAD = 4*Tcy = 100 ns _AD1IF = 0; _AD1IE = 1; AD1CON1bits.ADON = 1; } void Read_ADC (void) { while(_DONE == 0); } void __attribute__((interrupt,auto_psv)) _ADC1Interrupt(void) { vref = sin_table[i]; vadc= ADC1BUF0; v1=vadc*0.003258; vph=v1-voffset; vthuc=vph*hs; e=vref-vthuc; edel=e-e1; //cho chuyen doi xong
79

p=kp*e; d=kd*edel; u=p+d; e1=e; i++; if (i == 200) i=0; if (u>=1){u=1;} if(u<=-1){u=-1;} P1DC1 =TS*(1-u); //Cap nhat cac thanh ghi dem chu ky nhiem vu P1DC2 =TS*(1+u); _AD1IF = 0; }
80
PH LC 2: TI LIU THAM KHO

1. in t cng sut L thuyt- Thit k- ng dng Tc gi: L Vn Doanh, Nguyn Th Cng, Trn Vn ThnhNXB Khoa hc k thut H Ni. 2. L thuyt iu khin tuyn tnh Tc Gi: Nguyn Don Phc. 3. Refference Manual of dsPIC33FJ12MC202 4. Datasheet of dsPIC33FJ12MC202 5. Digital Control Power Electronics Tc Gi: Simone Buso v Paolo Mattavelli 6. Transformer and inductor design handbook Tc gi: Colonel Wm. T. McLyman
Mt s trang web: http://thietbidien.vn http://www.microchip.com http://www.dientuvietnam.net http://www.picvietnam.net
81

Do An UPS Chung

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Do An UPS Chung

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Thit k b nghch lu cho h thng UPS c kh nng kt ni li

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Sinh vin thc hin Nguyn Vn Chung

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Chng 1: TM HIU V UPS V NG DNG

SVTH: Nguyn Vn Chung Lp TB-T1-K51

1.2 Phn loi UPS :

Hnh 1.1 Cu trc b UPS offline SVTH: Nguyn Vn Chung Lp TB-T1-K51 4

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Hnh 1.5 S nguyn l chung ca UPS SVTH: Nguyn Vn Chung Lp TB-T1-K51 8

1.3 ng dng ca UPS trong thc t :

SVTH: Nguyn Vn Chung Lp TB-T1-K51

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Chng 2: TNH TON THIT K

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Hnh 2.4 in p to bi mch na cu b) Cu trc mch Full-Bridge (C cu) :

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Ta thy rng : [sin( t)-sin( t)]

Du bng xy ra khi v ch khi : sin( t )

Hnh 2.6 ip p to ra bi mch c cu SVTH: Nguyn Vn Chung Lp TB-T1-K51 14

min tuyn tnh

min tuyn qu iu bin

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Hnh 2.8 S m phng trn PSim

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

2.2 Cc khi mch s dng

SVTH: Nguyn Vn Chung Lp TB-T1-K51

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Hnh 2.13 Mch li SVTH: Nguyn Vn Chung Lp TB-T1-K51 20

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Hnh 2.15 Mch cch ly

SVTH: Nguyn Vn Chung Lp TB-T1-K51

2.3 Tnh ton mch lc thng thp

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

Hnh 2.16 Bin i Laplace Theo s mch ta c :

Nn hm truyn ca mch lc c dng nh sau: K ( s)

L() = - 20. log |1- LC2| 25

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Hai ng ny ct nhau ti im : Biu din trn th :

(rad/s) -40dB L()

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

SVTH: Nguyn Vn Chung Lp TB-T1-K51

- Tng din tch mt ct cc cc t : Ac = 2,11 cm2

Chn N = 133 vng Khong cch khe h khng kh:

SVTH: Nguyn Vn Chung Lp TB-T1-K51

Thit k b nghch lu cho h thng UPS c kh nng kt ni li

0,37 2.3,54 .ln 1, 752 0,37 2,11

S dng kt qu va tnh c tnh li s vng dy:

0,37.1, 27.10 3 0, 4. .2,11.1, 752.10

S dng s vng dy mi tnh li mt t cm:

2,5.104 0,52(T ) 4, 44.101.50.2,11

Tnh tit din dy qun: