Scribd Logo
Upload

Welcome to Scribd!

  • VHDL 4-bit Adder with Full Adder Components

    Uploaded by

    Kato Pinder
    70 views1 page
    This document describes a VHDL code for an 4-bit adder circuit. It defines an adder entity with input1, input2, carry_in ports for 4-bit inputs and sum, carry_out ports for 4-bit sum and carry outputs. The architecture uses four full adder components connected in series, with the carry output of each stage connected to the carry input of the next stage, to perform the addition.

    Original Description:

    VHDL Adder code

    Original Title

    VHDL Adder code

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document describes a VHDL code for an 4-bit adder circuit. It defines an adder entity with input1, input2, carry_in ports for 4-bit inputs and sum, carry_out ports for 4-bit sum and carry outputs. The architecture uses four full adder components connected in series, with the carry output of each stage connected to the carry input of the next stage, to perform the addition.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    70 views1 page

    VHDL 4-bit Adder with Full Adder Components

    Uploaded by

    Kato Pinder
    This document describes a VHDL code for an 4-bit adder circuit. It defines an adder entity with input1, input2, carry_in ports for 4-bit inputs and sum, carry_out ports for 4-bit sum and carry outputs. The architecture uses four full adder components connected in series, with the carry output of each stage connected to the carry input of the next stage, to perform the addition.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    Date: September 13, 2013 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 library ieee; use ieee.std_logic_1164 .

    all; entity adder is port ( input1 : input2 : carry_in : sum : carry_out : end adder;

    adder.vhd

    Project: adder8

    in in in out out

    std_logic_vector (3 downto 0); std_logic_vector (3 downto 0); std_logic ; std_logic_vector (3 downto 0); std_logic );

    architecture STR of adder is signal c1,c2,c3 : std_logic ; Component fa port( carry_in , input1, input2 : in std_logic ; sum, carry_out : out std_logic ); end component ; begin -- STR stage0: fa port map (carry_in ,input1(0),input2(0),sum(0),c1); stage1: fa port map (c1,input1(1),input2(1),sum(1),c2); stage2: fa port map (c2,input1(2),input2(2),sum(2),c3); stage3: fa port map (carry_in =>c3, carry_out =>carry_out , input1=>input1(3), input2=> input2(3),sum=>sum(3)); end STR;

    Page 1 of 1

    Revision: adder8

    You might also like