Bai Giang S7-200 PTuan Powerpoint

MN HC IU KHIN LP TRNH
(Programmable Logic Controller)
Ging Vin: Phm Vn Tun
10/1/2013
Ging vin: PHM VN TUN B MN L THUYT KHOA IN TRNG H SPKT VINH
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nh gi kt qu hc tp
* Thang im: 10; bao gm:
+ 30% im thnh phn

+ 70% im thi hc k
- im thnh phn c tnh nh th no? . Lm ti: 40% ca im thnh phn.
. im chuyn cn 60% ca im thnh phn.
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PHN 1
SIMATIC S7- 200
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NI DUNG CA PHN 1
I. Gii thiu chung v PLC. II. Lp trnh trong S7- 200. III. ng dng iu khin khi ng ng c. IV. Cc ng dng trong cng nghip.
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CHNG I
GII THIU CHUNG V PLC

1.1. PLC * Th no l PLC? PLC v vit tt ca Programmable Logic Controller, l b iu khin logic c kh nng lp trnh c, cho php thc hin linh hat cc thut ton iu khin logic thng qua ngn ng lp trnh. (y l nh ngha v PLC ca Nguyn Don Phc Phan Xun Minh trong sch T ng ho vi simatic S7 200). * Phm vi ng dng: + Lc u ch yu trong cc ngnh cng nghip ch to, iu khin cc qu trnh ri rc. + Ngy nay c trong iu khin trnh t v iu khin qu trnh lin tc, cnh tranh vi Compact Digital Controllers v cc h DCS trong cc ng dng lai.
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+ Thit b thu thp d liu trong cc h SCADA * Lch s ra i ca PLC Hnh thnh t nhm cc k s ca hng General Motor nm 1968 vi tng ban u l thit k mt b iu khin tha mn cc yu cu sau: + D dng sa cha v thay th. + n nh trong mi trng cng nghip.
+ Lp trnh d dng, ngn ng lp trnh ph hp vi ngnh ngh.

+ Gi c cnh tranh Nm 1969 PLC u tin (do hng Allen Bradlley v Bedford), c General Motor s dng trong cng nghip t (128 I/O, b nh 1 kilo bytes).
Nm 1973 PLC thng minh vi kh nng tnh ton, iu khin my in, x l d liu, c giao din HMI.
Nm 1975 PLC vi b iu khin PID ra i. Nm 1976: Ln u tin PLC s dng trong h thng phn cp iu khin dy chuyn sn xut. Nm 1977 : mP-based PLC. Nm 1980: Cc module vo/ra thng minh.
Nm 1981: PLC ni mng, 16-bit PLC, cc mn hnh CRT mu. Nm 1982: PLC vi 8192 I/O (ln nht).
Nm 1992: Chun IEC 61131 ra i. Nm 1996: Slot-PLC, Soft-PLC,...
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V d 1.1 Phn bit gia PLC v mn mch my
MCCB K 1 K RN KTG D M 3 5 2 K 2 RN Rth KS 1
Rth 9
KTG11
Rth 13 KS KTG 15 KS a)
b)
Hnh 1.1. Khi ng sao tam gic.

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Hnh 1.2. Khi ng sao tam gic dng PLC

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* Vai tr ca PLC trong qu trnh t ng ha sn xut: Nh bit, nc ta hin nay ang trong qu trnh cng nghip ha, hin i ha. V th, t ng ha sn xut ng vai tr quan trng, t ng ha gip tng nng sut, tng chnh xc v do tng hiu qu qu trnh sn xut. c th thc hin t ng ha sn xut, bn cnh cc my mc c kh hay in, cc dy chuyn sn xutv.v, cng cn thit phi c cc b iu khin iu khin chng. PLC l mt trong cc b iu khin p ng c yu cu . 1.2. Cu trc v nguyn l hot ng ca PLC
1.2.1. Cu to ca PLC
Hin nay trn th gii c rt nhiu hng sn xut PLC nh:
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Toshiba, Hitachi, Omron, Misubishi ca Nht Bn; LS ca Hn Quc GM4; Siemens, ABB ca c; Rockwell, General electric ca M; Schneider ca Php ; Danfort ca an Mch; Allen Bradley ca Anh; B&G system 2000 ca o; Honeywell;
Tt c chng u gm 4 thnh phn chnh (nh hnh v 1.1)

Inputs CPU - Memory Outputs
Source
Hnh 1.3. Cu to ca PLC.

Thit b lp trnh
B nh
Giao din nhp
B x l
Giao din xut
Ngun cng sut
Hnh 1.4. S cu trc ca PLC. * CPU (Central Processing Units- Khi x l trung tm n v x l trung tm): L b x l trung tm, n nh b no ca PLC c nhim v iu khin v qun l mi hot ng bn trong PLC. Vic trao i thng tin gia CPU, b nh v cc u vo/ ra c thc hin
thng qua h thng cc bus ni di s iu khin ca CPU. PLC ca hng Siemens dng S7- 200 CPU 21x bao gm: CPU 210, CPU 212, CPU 214, CPU 215- 2DP, CPU 216. Dng S7- 200 CPU 22x bao gm: CPU 221, CPU 222, CPU 224, CPU 224XP, CPU 226, CPU 226XM; Trong CPU 224XP c h tr analog 2I/1O onboard v 2 port truyn thng. * B nh chng trnh (Memory):
Dng lu gi v sao chp chng trnh. Tt c cc loi PLC u s dng cc loi b nh sau c bn sau: ROM, EPROM, EEPROM, RAM, a cng, a mm.
+ ROM (Read Only Memory): L b nh ch c, trong PLC b nh ny dng lu gi h iu hnh do nh sn xut np v ch np c mt ln.
+ EPROM (Electrically Programmable ROM) l b nh m ngi s dng bnh thng ch c th c ch khng ghi ni dung vo c. Ni dung ca EPROM khng b mt khi mt ngun, n c gn sn trong my, c nh sn xut np v cha h iu hnh sn. EPROM c th xa c bng tia cc tm. + B nh EEPROM (Electrical Erasable Programable ROM): L b nh ROM c th xa v np li bng tn hiu in, ty thuc loi EEPROM cho php xa v np li vi vi nghn n vi chc nghn ln. B nh EEPROM c dng lu gi chng trnh ng dng trong PLC. + RAM (Random Acess Memory): L b nh truy cp ngu nhin, trong PLC b nh ny dng lu gi d liu hoc kt qu tm thi ca cc php ton. RAM c th np chng trnh, thay i hay xa b
ni dung bt k lc no. Ni dung ca RAM s b mt nu ngun in nui b mt. trnh tnh trng ny cc PLC u c trang b mt t hoc mt pin kh nui RAM, do khi mt in d liu trong RAM c th lu trong vi chc gi, vi thng n vi nm. Trong thc t RAM c dng khi to v kim tra chng trnh. Khuynh hng hin nay dng CMOS RAM nh kh nng tiu th thp v tui th ln. + Mi trng ghi d liu na l a cng hoc a mm: c s dng trong my lp trnh. a cng hoc a mm c dung lng ln nn thng c dng lu nhng chng trnh ln trong mt thi gian di.
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Hnh 1.5. Cu trc b nh RAM, EEPROM.
+ Kch thc b nh: - Cc PLC loi nh c th cha t 300 -1000 dng lnh ty vo cng ngh ch to. - Cc PLC loi ln c kch thc t 1K - 16K, c kh nng cha t 2000 -16000 dng lnh.
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* Cc cng vo/ ra- Inputs/ Outputs: Mi hot ng bn trong PLC u c mc in p hoc (mc in p cp cho cc IC TTL hoc CMOS) trong khi tn hiu iu khin theo tiu chun cng nghip l 24 VDC hoc 230 VAC. Do cc cng vo/ ra ng vai tr l mch giao tip gia cc vi mch in t bn trong PLC vi cc mch cng sut bn ngoi, n thc hin chuyn i mc tn hiu v cch ly. 1.2.2. Nguyn l hot ng ca PLC
* Vng qut ca PLC: PLC thc hin chng trnh theo chu trnh lp. Mi vng lp c gi l vng qut (scan). Mi vng qut c bt u bng giai on c dliu t cc cng vo vng b m o, tip theo l giai on thc hin chng trnh.
Trong tng vng qut, chng trnh c thc hin bng lnh u tin v kt thc ti lnh kt thc. Sau giai on thc hin chng trnh l giai on truyn thng ni b v kim tra li. Vng qut c kt thc bng giai on chuyn cc ni dung ca b m o ti cc cng ra.
4. Chuyn d liu ra u outputs
1. Nhap d lieu t ngoai vi vao
3. Truyen thong va t kiem tra loi
2.Thc hien
chng trnh
Hnh 1.6. Vng qut ca PLC.
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Nh vy, ti thi im thc hin lnh vo/ ra, thng thng lnh khng lm vic trc tip vi cng vo/ ra m ch thng qua b m o ca cng trong vng nh tham s. Vic truyn thng gia b m o vi ngoi vi trong cc giai on 1 v 4 do CPU qun l. Khi gp lnh vo/ ra ngay lp tc th h thng s cho dng mi cng vic khc, ngay c chng trnh x l ngt, thc hin lnh ny mt cch trc tip vi cng vo/ ra.
Nu s dng cc ch ngt, chng trnh con tng ng vi tng tn hiu ngt c son tho v ci t nh mt b phn ca chng trnh. Chng trnh x l ngt ch c thc hin trong vng qut khi xut hin tn hiu bo ngt v c th xy ra bt c thi im no trong vng qut.
1.2.3. Truyn thng cho CPU S7 - 200
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SIMATIC NET l mng truyn thng cho php kt ni vi cc b iu khin ca SIEMENS, cc my tnh ch, cc trm lm vic. SIMATIC NET bao gm cc mng truyn thng, cc thit b truyn d liu, cc phng php truyn thng d liu, cc giao thc v dch v truyn d liu gia cc thit b, cc module cho php kt ni mng LAN (CP-Communication Processor hoc IM Interface Module).
Vi h thng SIMATIC NET, SIEMENS cung cp h thng truyn thng m cho nhiu cp khc nhau ca cc qu trnh t ng ho trong mi trng cng nghip. H truyn thng SIMATIC NET da trn nhiu tiu chun quc t ISO/OSI (International Standardization Organisation / Open System Interconnection). C s ca cc h thng truyn thng ny l cc mng cc b (LANs), c th thc hin theo nhiu cch khc nhau: in hc, quang hc, khng dy hoc kt hp c ba cch trn.
Theo cc yu cu v chc nng cc lp trong t chc iu hnh, qun l sn xut th mng cng nghip c chia thnh nhiu cp bao gm: cp iu hnh qun l, cp phn xng, cp trng v cp c cu chp hnh cm bin - i tng.
Theo phng php t chc h thng nh trn SIMATIC cung cp cc loi sub-net nh sau:
- Mng PPI. - Mng MPI - Mng AS- interface. - Mng Profibus. - Mng Ethernet cng nghip.
1.3. Gii thiu chung v S7- 200

1.3.1. Dng S7- 200
L PLC c nh ca hng siemes (c) hay cn gi l Micro PLCs, c cu trc theo kiu modul v c cc modul m rng. Cc modul ny c s dng cho cho nhiu ng dng lp trnh khc nhau. Dng sn phm S7- 200 v ang c ci tin nh gn hn, nhanh hn v c thm nhiu chc nng hn na.
Thnh phn c bn ca S7- 200 l khi vi x l CPU 2xx. Hin nay khi vi x l ny chia lm hai loi c bn: * CPU 21x: bao gm CPU 210, 212, 214, 216 (Loi ny khng cn sn xut na). + Cu hnh ca CPU 212 nh sau: - 8DI: I0.x (x= 0 n 7). - 6 REL.OUTP: Q0.x (x= 0 n 5). - in p vo 24VDC hoc 120 VDC.
- in p ra 24VDC hoc 230 VAC; - C th ghp ni thm ti a 2 modul (k c modul tng tAnalog) m rng s cng vo / ra, khi s cng logic vo / ra cc i l 64 cng vo v 64 cng ra. - 64 timer, trong c 2 timer c phn gii 1ms, 8 timer c phn gii 10ms v 54 timer c phn gii 100ms. - 64 counter, chia lm 2 loi: loi b m ch m tin v loi b m va m tin va m li. - 368 bits nh c bit, s dng lm cc bit trng thi hoc cc bit t ch lm vic. - Cc ch ngt v x l tn hiu ngt khc nhau bao gm: ngt truyn thng, ngt theo sn ln hoc sn xung, ngt theo thi gian v ngt bo hiu ca b m tc cao (2KHz).
- Thi gian mt d liu khi mt ngun nui l 50 gi.
Hnh 1.7. CPU 212. + Cu hnh ca CPU 214 nh sau:

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- 14DI: I0.x; I1.x (x= 0 n 7) - 10 REL.OUTP: Q0.x (x= 0 n 7); Q1.0, Q1.1 - in p vo 24VDC hoc 120VDC - in p ra 24VDC hoc 230VAC - C th ghp ni thm ti a 7 modul (k c modul tng tAnalog) m rng s cng vo / ra, khi s cng logic vo / ra cc i l 64 cng vo v 64 cng ra. - 128 timer, chia lm 3 loi theo phn gii khc nhau: 4 timer 1ms, 16 timer 10ms v 108 timer 100ms.
- 128 counter chia lm 2 loi: ch m tin v va m tin va m li. - 688 bit nh c bit dng thng bo trng thi v t ch lm vic.
- Cc ch ngt v x l ngt gm: ngt truyn thng, ngt theo sn ln hoc xung, ngt thi gian, ngt ca m tc cao v ngt truyn xung. - 3 b m tc cao HC0, HC1 v HC2 vi nhp xung 2KHz v 7 KHz.
- 2 b iu chnh tng t. - Ton b vng nh khng b mt d liu trong khong thi gian 190 gi khi PLC b mt ngun nui.
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Hnh 1.8. CPU 214. Tng hp: Cu hnh phn cng ca CPU 21x nh sau:
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+ CPU 22x: bao gm CPU 221, CPU 222, , CPU 224, CPU224XP, CPU 226, CPU 226XM; Trong CPU 224XP c h tr analog 2I/1O onboard v 2 port truyn thng. Tng hp: Cu hnh phn cng ca CPU 22x nh sau:
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* Cu hnh vo ra ca S7- 200 CPU 22x
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1.3.2. Cu trc b nh ca S7- 200

1.3.2.1. B nh ca S7- 200 c chia thnh 4 vng, vi mt t in c nhim v duy tr d liu trong mt khong thi gian nht nh khi mt ngun in. 4 vng nh gm: chng trnh, tham s, d liu v i tng. * Vng chng trnh: Lu gi cc lnh chng trnh, vng ny thuc kiu Non- volatile, c/ ghi.
* Vng nh tham s: Lu gi cc tham s nh: t kha, a ch trm..., vng ny thuc kiu Non- volatile, c/ ghi. * Vng d liu: Ct cc d liu ca chng trnh, bao gm cc kt qu php tnh, hng s c nh ngha trong chng trnh,..., vng ny thuc kiu Non- volatile, c/ ghi.
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* Vng i tng: Timer, counter, b m tc cao v cc cng vo ra tng t, c t trong vng nh ny. Vng ny khng thuc kiu Non- valatile nhng c/ ghi c./.
Hnh 1.9. Vng nh S7- 200 Hai vng nh cui c ngha quan trng trong vic thc hin mt chng trnh, do vy s c trnh by k hn.
Vng d liu: L min nh ng, c th truy cp theo tng bit, byte,... v c s dng lm min lu tr d liu cho cc thut ton, cc hm truyn thng, cc hm dch chuyn, xoay vng thanh ghi, con tr a ch...
Vng d liu li c chia thnh nhng min nh nh vi cng dng khc nhau.
V - Variable memory (vng nh bin vng nh thay i).
I - Input image register (vng nh b m o u vo). Q - Output image register (vng nh b m o u ra). M - Internal memory bits (vng nh ni). SM - Special memory bits (vng nh c bit).
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a ch cc vng nh d liu ca CPU 212

- u vo (Input) c 8 u vo s: I0.0 n I0.7 - u ra (output) c 6 u ra s: Q0.0 n Q0.5
- B m o u vo: I0.0 n I7.7 (64 DI) - B m o u ra: Q0.0 n Q7.7 (64DQ) - Vng nh V- variable memory (c/ ghi): VB0 n VB1023 - Vng nh ni M- Internal memory bits(c/ ghi), thng dng lm bin nh trung gian, 16 bytes, c truy cp theo bit: M0.0 n M15.7.(MB 0 n MB 15)
- Vng nh c bit SM- Special memory bits, truy cp theo bit:
Ch c: SM0.0 n SM29.7. c / ghi: SM30.0 n SM45.7.

a ch cc vng nh d liu ca CPU 214

- u vo (Input) - c 14 u vo s: I0.0 n I1.7 - u ra (output) c 10 u ra s: Q0.0 n Q1.1
- B m o u vo: I0.0 n I7.7 (64 DI) - B m o u ra: Q0.0 n Q7.7 (64DQ) - Vng nh V- variable memory (c/ ghi): VB0 n VB4095 - Vng nh ni M- Internal memory bits(c/ ghi), thng dng lm bin nh trung gian, 32 bytes, c truy cp theo bit: M0.0 n M31.7.
- Vng nh c bit SM- Special memory bits, truy cp theo bit; byte. * Vng i tng:
c s dng lu gi d liu cho cc i tng lp trnh nh cc gi tr tc thi, gi tr t trc ca Timer, counter. D liu ca vng nh i tng bao gm cc thanh ghi ca timer, counter, cc b m tc cao, b m vo/ ra tng t v cc thanh ghi Accumulator (AC- thanh ghi tng 32 bits). a ch cc vng nh i tng ca CPU 212
- Min nh phc v Timer T:
T0 n T63 (i vi CPU 212) T0 n T127 (i vi CPU 214) - Min nh phc v Counter C: C0 n C63 (i vi CPU 212) C0 n C127 (i vi CPU 214)
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- B m cng vo tng t, ch c: AIWx (x= 0 n 30) - B m cng ra tng t, ch c: AQWx (x= 0 n 30)
Trong x l s chn, x = 0, 2, 4,..., 30
- Thanh ghi tng Accumulator (c/ ghi) AC; AC0 n AC3, trong AC0 khng c kh nng lm con tr. - B m tc cao (c/ ghi): HC0. a ch cc vng nh i tng ca CPU 214 - Min nh phc v Timer T: T0 n T127 (i vi CPU 214) - Min nh phc v Counter C: C0 n C127 (i vi CPU 214) - B m cng vo tng t, ch c: AIWx (x= 0 n 30)
- B m cng vo tng t, ch c: AQWx (x= 0 n 30)

Trong x l s chn, x= 0, 2, 4,..., 30 - Thanh ghi tng Accumulator (c/ ghi) AC; AC0 n AC3, trong AC0 khng c kh nng lm con tr. - B m tc cao (c/ ghi): HC0 (HC1 v HC2 ch c trong CPU 214). Tng kt:
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1.3.2.2. Cch truy cp d liu trong S7- 200

* Cch truy cp d liu trc tip 1 W= 2 byte= 16 bt. 1 D= 4 byte = 32 bt. + Truy cp theo bit: I0.2; Q0.5;... + Truy cp theo Byte: VB100; MB15;
0 VB100 7
MSB
LSB
+ Truy cp theo word (t n): VW100; MW10;
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+ Truy cp theo Double word: VD100
* Cch truy cp d liu gin tip thng qua con tr + Con tr (Pointer): L mt nh c kch thc 1 t kp (32 bt) cha a ch ca mt nh khc. Khi ta truy cp con tr c ngha l ta ang c ni dung ca nh mong mun. - C 3 vng nh trong S7- 200 cho php dng con tr: VD; LD; AC1; AC2; AC3 (AC0 khng dng lm con tr). - S7- 200 cho php dng con tr truy cp cc a ch nh sau: I; Q; V; M; S; T (T_Word); C (C_Word). - S7- 200 khng cho php dng con tr truy cp a ch nh sau: AI; AQ; SM; HSC; L v a ch di dng bit.
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1.3.3. M rng cng vo/ ra trong S7- 200 * CPU 212 c th m rng ti a 2 module EM 221, EM 222.
* CPU 214 c th m rng ti a 7 module. Cc module m rng tng t v s u c trong S7- 200. * CPU 216 c th m rng ti a 7 module. * CPU 221 khng ghp ni c module m rng. * CPU 222 ghp ni c ti a 2 module m rng. * CPU 224 ghp ni c ti a 7 module m rng. * CPU 226 ghp ni c ti a 7 module m rng. * C cc loi module m rng sau:
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Hnh 1.10. Cc module m rng ca S7- 200.

Hnh 1.11. Cch kt ni module m rng vi CPU.
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1.3.4. Bng lnh ca CPU S7- 200

1.3.4.1. CPU 21x c nhng c im sau:
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1.3.4.2. CPU 22x c nhng c im sau:
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CHNG II
LP TRNH TRONG S7- 200

2.1. Phng php lp trnh Trong S7- 200 cho php la chn 3 ngn ng lp trnh: + Ngn ng STL (Statement List)- lit k lnh.
+ Ngn ng LAD (Ladder Logic)- Ngn ng bc thang. + Ngn ng FBD (Function Block Data) Lp trnh theo khi chc nng. Ba ngn ng ny v hnh thc c th chuyn i ln nhau. Mnh nht l ngn ng STL. Chuyn vin ngnh in hay lp trnh theo kiu Ladder hn. * Nu mt v d nh cho sinh vin (3 ngn ng lp trnh c th chuyn i cho nhau).
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V d 2.1: Chuyn i on chng trnh sau t ngn ng Ladder sang ngn ng STL v FBD: Ladder
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Mun chuyn i t Ladder sang STL?

Cch chuyn i ngn ng
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Mun chuyn i t Ladder sang FBD?

Cch chuyn i
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* Vng qut ca PLC S7- 200 (Scan PLC)- Nguyn l lm vic ca PLC: ging nguyn l lm vic chung ca PLC
4. Chuyn d liu ra u outputs
1. Nhap d lieu t ngoai vi vao
3. Truyen thong va t kiem tra loi
2.Thc hien chng trnh
Hnh 2.1. Vng qut ca PLC
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* Cu truc ca mt chng trnh PLC S7- 200 Cc chng trnh cho S7- 200 phi c cu trc bao gm chng trnh chnh (main program) v sau n cc chng trnh con v cc chng trnh x l ngt c ch ra sau y: + Chng trnh con v chng trnh x l ngt l b phn ca chng trnh. Nu cn s dng chng trnh con hoc chng trnh x l ngt phi vit sau chng trnh chnh. + Nu cn s dng chng trnh con hoc chng trnh x l ngt, chng phi c gi ra bng lnh gi c vit chng trnh chnh. V d 2.2: Cch vit mt chng trnh con hoc chng trnh x l ngt:
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Chng trnh chnh (Main)
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2.2. Cc lnh n bit trong S7- 200

Mc d S7- 200 c mt khi lng lnh tng i ln th hin cc thut ton ca i s Boolean song ch c mt vi cc kiu lnh khc nhau. Sau y tng lnh ca S7- 200 c m t chi tit v cch s dng, chc nng v tc ng ca chng vo ni dung ngn xp, trong gi tr ca ngn xp trc khi thc hin lnh c k hiu t Iv0 n Iv8. 2.2.1. Ngn xp (Stack) * La chn ngn ng lp trnh: Trong S7- 200 c th chn mt trong ba ngn ng lp trnh sau: + STL + LADDER + FBD
V mt hnh thc, 3 ngn ng lp trnh ny c th chuyn i ln nhau, nhng mnh nht vn l ngn ng lp trnh STL. Cn b v chuyn vin nghnh in hay s dng ngn ng LADDER (gn ging vi s trang b in- gn gi hn).
* Khi nim ngn xp:

Ngn xp trong S7- 200 l mt thanh ghi c bit gm 9 bits, nguyn tc hot ng ca ngn xp l FILO (First Input, Last Out).
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nh ngn xp
Iv0 Iv1 Iv2
Iv3 Iv4 Iv5 Iv6 Iv7
Cc lnh logic v kt qu php ton thng lin quan mt thit n bit u tin ca ngn xp, ngoi tr mt s lnh c lin quan n bit th 2 hoc bit th 3.
Iv8
Ngn xp
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2.2.2. Lnh vo/ ra * Lnh np d liu STL LD bit LDN bit
LAD
iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7 iv8
bit iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7
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+ Cc dng khc nhau ca lnh LD, LDN

LADDER
bit
STL LD bit
M T Tip im thng m s c ng nu bit= 1 Tip im thng ng s m khi bit= 1 Tip im thng m s ng tc thi khi bit= 1 Tip im thng ng s m tc thi khi bit= 1
TON HNG bit : I, Q, M, T, C, V, SM.
bit
LDN
bit
bit
LDI
bit
bit: I
bit
LDNI
bit
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* Lnh xut d liu
Trc =
Sau =
Bit Iv0 c lu vo nh c a ch ghi trong lnh = V d 2.3: = Q0.1 Lu bit u tin ca ngn xp vo nh c a ch Q0.1
+ Cc dng khc nhau ca lnh xut d liu

LADDER =I STL nv M T Lnh =I (Immediate) sao chp tc thi gi tr ca nh ngn xp ti tip im bit c ch nh trong lnh. TON HNG nv(bit): I, Q, M, T, C, V, SM.
bit
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2.2.3. Cc lnh logic i s Boolean

a ch ca ton hng nv (bit): I, Q, M, SM, T, C, V, S, L.
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V d 2.4: Chuyn on chng trnh sau t STL sang Ladder

STL Network 1 LD I0.0 A I0.1 = Q0.0 NOT = Q0.1 Ladder
Network 2 LD I0.2 ON I0.3 = Q0.2
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2.2.4. Cc lnh ghi/ xa gi tr cho tip im Lnh Set (S) v Reset (R) thc hin set v reset N bit, c bt u t a ch bit c trong lnh. Bn c th set hoc reset t 1 to 255 bit. N l s bit cn Set hoc Reset Bit l a ch bit u tin trong s N bit Nu lnh Reset c dng cho Timer hoc Counter th lnh ny c tc dng reset T_bit, C_bit v xa ni dung ca T_word, C_word.
Nu c li th Set ENO = 0: 0006 (sai a ch) 0091 ( ton hng ra ngoi khong).
V d 2.5: Chuyn on chng trnh t Ladder sang STL
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2.2.5. Cc lnh logic lm vic vi ngn xp khng c ton hng

Cc lnh khng c ton hng, ch c bn ngn ng STL, khng c bn ngn ng LAD v FBD
ALD (And Load)

OLD (Or Load)
LPS (Logic Push)

LPP (Logic Pop)
LRD (Logic Read)
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Lnh ALD thc hin AND 2 bit u ca ngn xp, cc bit cn li c ko ln 1 bit. Bit cui cng trng d liu.
Lnh OLD thc hin OR 2 bit u ca ngn xp, cc bit cn li c ko ln 1 bit. Bit cui cng trng d liu.
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LPS
iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7 iv8 iv0
iv0
iv1 iv2 iv3 iv4 iv5 iv6 iv7
Lnh LPS copy bit u ca ngn xp xung bit th 2, cc bit cn li ca ngn xp c y xung 1 bit. Bit cui cng ca ngn xp b ri d liu.
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Lnh LPP: y ton b ngn xp ln 1 bit, bit u tin ca ngn xp b mt d liu. Bit cui cng b trng d liu.
Lnh LRD
Lnh LRD: sao chp bit th 2, ri dn ln bit u tin, cc bit cn li c gi nguyn.
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V d 2.6: on chng trnh Ladder sang STL
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V d 2.7: on chng trnh STL sang Ladder

Network 1 Network 2
LD
LD LD A
I0.0
I0.1 I2.0 I2.1
LD
LPS LD O
I0.0
I0.5 I0.6
OLD
ALD = Q5.0
ALD
= LRD LD I2.1 Q7.0
O
ALD = LPP A =
98 Ging Vin: Phm Vn Tun
I1.3
Q6.0
I1.0 Q3.0
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Ladder
2.2.6. Cc lnh logic c bit
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Network 1
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Network 1
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Lnh copy v paste bit th (n+1) ln nh ngn xp, cc bit cn li c y xung 1 bit.
2.3. Timer trong S7- 200 CPU 21x
Timer l b to thi gian tr mong mun gia tn hiu logic u vo v tn hiu logic u ra.
Timer( Txx )
t
t+
Trong S7- 200 CPU21x bao gm: 64 Timer (vi CPU 212); 128 Timer (CPU 214); 256 Timer (CPU 215/ 216)
Timer trong S7- 200 CPU 21x c chia lm hai loi khc nhau, l: * Timer to thi gian tr, tc ng theo sn dng khng c nh (On- Delay Timer), k hiu l TON. * Timer to thi gian tr, tc ng theo sn dng c nh (Retentive On- Delay Timer), k hiu l TONR.
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Mi b timer trong S7- 200 (k c CPU 21x v CPU 22x) u c k hiu l Txx , Mi b Txx gm 3 dng d liu: T_bit v T_word (current value gi tr m tc thi); PT (Preset value) + T_bit: l kt qu u ra ca timer. + T_word: lu gi tr m tc thi ca timer. + PT : Gi tr t trc (dng d liu s nguyn)
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phn gii (Resolution): L khong thi gian ngh gia hai ln m ca current value (T_word). Cc b Timer ca S7- 200 c 3 phn gii: 1 ms, 10ms, 100ms. Cch tnh thi gian tr cho Timer Thi gian tr ca Timer = phn gii ca Timer x Gi tr t trc Trong : Gi tr t trc (PT): chnh l gi tr m ca Timer. Mi b Timer, ngoi thanh ghi 2 byte T_word lu gi tr m tc thi, cn c mt bit, k hiu l T_bit ch trng thi logic u ra. Gi tr logic ca T_bit ph thuc vo kt qu so snh gia gi tr m tc thi v gi tr t trc. Timer m tin bng T_word v gi tr m tc thi c lu T_word - Gi tr m cc i ca timer l 32767 (Ti sao ?)
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2.3.1. Timer kiu TON
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V d 2.8: Gii thch tc ng ca u ra
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2.3.2. Timer kiu TONR
Network 1 LD I0.0 TONR T30, +100

Network 2 LDW= T30, +150 R T30, 1
Cch khai bo Timer TONR
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STL
Network 1 LD I0.0 TONR T1, +100
Network 2 LD T1 = Q0.0 Network 3

LD R I0.1 T1, 1
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Nguyn l lm vic ca TONR
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2.4. Timer trong S7- 200 CPU 22x Timer trong S7- 200 CPU 22x c chia lm ba loi khc nhau, l: * Timer to thi gian tr khng c nh tc ng theo sn dng (On- Delay Timer), k hiu l TON. * Timer to thi gian tr c nh (Retentive On- Delay Timer), k hiu l TONR. * Timer to thi gian tr, tc ng theo sn m TOF (OffDelay Timer).
Trong S7- 200 CPU22x bao gm: 256 Timer

* Vi TON v TONR hon ton tng t nh trong CPU S7200 CPU 21x. * Vi TOF, timer tc ng theo sn xung sn m.
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2.4.1. Timer kiu TOF Nguyn l lm vic ca b to tr TOF: Khi Timer c kch ln 1 (u IN t 0 ln 1) th T_bit thay i trng thi ngay lp tc. T_word cha m. Khi u vo IN chuyn t 1 -> 0, Timer (T_word) bt u m, nu T_word< PT th T_bit vn cha tr v trng thi c. Nu T_word = PT th T_word s dng m tin, ng thi T_bit tr li trng thi c. Trong khi T_word ang m m u vo IN c kch ln 1(t 0 ln 1) th T_word b reset v 0, T_bit vn s khng tr v trng thi c. Khi T_word = PT, T_bit tr v trng thi c ri, m u vo IN c kch ln 1 th T_bit ngay lp tc thay i trng thi, T_word b reset v 0.
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2.5. Counter trong S7- 200 CPU 21x
Counter trong S7- 200 CPU 21x c 2 loi counter: * Counter m tin CTU (Counter Up). * Counter m tin/ li CTUD (Counter Up/ Down). Trong S7- 200 CPU21x bao gm: 64 counter (vi CPU 212); 128 counter (CPU 214); 256 counter (CPU 215/ 216) c chia
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* Counter up (CTU) vi CPU 21x c chia thnh cc vng nh sau: CPU 212: C0 n C47;
CPU 214: C0 n C47 v t C80 n C127 * Counter up/ down (CTUD) vi CPU 21x c chia thnh cc vng nh sau: CPU 212: C48 n C63; CPU 214: C48 n C79
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Counter( Cxx ) Input Kt qu u ra (Tn hiu m) Mi b counter trong S7- 200 (k c CPU 21x v CPU 22x) u c k hiu l Cxx , Mi b Cxx gm 3 dng d liu: C_bit, C_word (current value) v PV (preset value). + C_bit: l kt qu u ra ca counter. + C_word: lu gi tr m tc thi ca counter. + PV: Gi tr t trc. Counter m bng C_word v gi tr m tc thi c lu c_word - Gi tr m cc i ca counter l 32767, cc tiu l -32767 (Ti sao ?)
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V d 2.9: Gii thch tc dng ca cc lnh
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V d 2.10: Gii thch tc dng ca cc lnh
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2.6. Counter trong S7- 200 CPU 22x
Counter trong S7- 200 CPU 22x c 3 loi counter: * Counter m tin CTU (Counter Up). * Counter m tin/ li CTUD (Counter Up/ Down). * Counter m li CTD (Counter Down). Trong S7- 200 CPU22x c 256 b counter: C0 n C255
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Nguyn l lm vic ca hai b m CTU v CTUD ca S7200 CPU 22x ging vi S7-200 CPU 21x ( c trnh by mc 2.5).
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* Nguyn l lm vic ca b m CTD B CTD thc hin chc nng m xung t gi tr t trc PV v 0 khi c sn ln ca CD (chuyn t 0 ln 1). Khi gi tr m tc thi (C_word) bng 0 th b CTD dng m xung, ng thi C_bit chuyn trng thi: + Tip im C_bit thng ng th m ra. + Tip im C_bit thng m th m li. Counter s reset C_bit (tr v trng thi c) v np gi tr m tc thi = gi tr t trc PV (C_word = PV), khi tn hiu LD c bt (chuyn t 0 ln 1).
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V d 2.11: CTD
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Bi tp ng dng phn lnh n bit, Timer v Counter

Bi 1: iu khin 5 n theo yu cu cng ngh sau: - Ti mi thi im ch c 1 n sng. - n 1 sng trong 5s th tt, n 2 sng trong 5s th tt, , n 4 sng trong 5s th tt, n 5 sng trong 5s th tt(1 chu k). - Trong 200.000 chu k th tt tt c cc n Bi 2: iu khin theo yu cu sau: n nt A vi s ln l th ng c chy. n nt A vi s ln chn th ng c dng.
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Bi 3: iu khin 3 ng c 3 pha theo yu cu sau: n nt khi ng th ng c 1 chy, sau 10 pht th ng c 2 chy, sau 3 gi th ng c 3 chy, ng thi ng c 1 v 2 ngt. ng c 3 chy c 4 gi th ngt (Ht 1 chu k). Chu k ny lp i lp li 5 ln th dng. Bi 4: Khi ng ng c kb rotor lng sc bng khi ng sao tam gic. Bi 5: Khi ng ng c kb rotor lng sc bng khi ng theo 3 cp in tr ph. Bi 6: iu khin khi ng ng c kb rotor dy qun bng 3 cp in tr ph.
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Bi 7: m s s sinh vin, vi yu cu:

- t c s s sinh vin trong lp. - Nu sinh vin th n xanh sng.
- Nu cha th n vng sng.

- Nu qu s sinh vin th n sng v ci ku trong 3 giy./.
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2.7. Cc lnh lm vic vi Byte, word v Double word
Cc lnh lm vic vi byte, word v double word l cc lnh c iu kin - c ngha l cc lnh ton hc ny ch c thc hin khi nh ca ngn xp c gi tr logic =1. 2.7.1. Cc lnh x l ton hc lin quan n s nguyn
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Nhm lnh ton hc lin quan n s nguyn 16 bit:
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Nhm lnh ton hc lin quan n s nguyn 32 bit:
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LU : * Php ton chia 2 s nguyn 16 bit (/I in1, out), kt qu cho s nguyn 16 bit. Phn d khng c lu li. * Php ton chia 2 s nguyn 32 bit (/D in1, out), kt qu cho s nguyn 32 bit. Phn d khng c lu li.
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LU : Php ton chia 2 s nguyn 16 bit (DIV in1, out), kt qu cho s nguyn 32 bit. Phn d c lu li 16 bit ca 2 byte cao; thng c lu 16 bit ca 2 byte thp.
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V d 2.12:
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2.7.2. Nhm lnh tng, gim ni dung thanh ghi, nh
Lnh tng ni dung ca byte, gim ni dung ca byte
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Lnh tng ni dung ca t n, gim ni dung ca t n
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Lnh tng ni dung ca t kp, gim ni dung ca t kp
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V d 2.13:
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2.7.3. Cc lnh x l ton hc lin quan n s thc Lnh cng, tr s thc
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Lnh nhn, chia s thc
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V d 2.14:
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Cc hm lng gic: sin, cos, tan
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Cc hm cn, hm logarit t nhin ln, hm m ex
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2.7.4. Cc lnh x di chuyn d liu MOVE
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V d 2.15:
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Lnh Swap Bytes trao i ni dung byte cao vi ni dung byte thp ca t n trong IN.
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V d 2.16:
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2.8. Chng trnh con v x l ngt

2.9. Thi gian thc RTC Real Timer Clock 2.10. B m tc cao HSC (Hight Speed Counter)
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MN HC IU KHIN LP TRNH

(Programmable Logic Controller)

Ging Vin: Phm Vn Tun

Ging vin: PHM VN TUN B MN L THUYT KHOA IN TRNG H SPKT VINH

Ging Vin: Phm Vn Tun

+ 30% im thnh phn

- im thnh phn c tnh nh th no? . Lm ti: 40% ca im thnh phn.

. im chuyn cn 60% ca im thnh phn.

Ging Vin: Phm Vn Tun

SIMATIC S7- 200

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

GII THIU CHUNG V PLC

+ Lp trnh d dng, ngn ng lp trnh ph hp vi ngnh ngh.

Ging Vin: Phm Vn Tun

V d 1.1 Phn bit gia PLC v mn mch my

MCCB K 1 K RN KTG D M 3 5 2 K 2 RN Rth KS 1

Hnh 1.1. Khi ng sao tam gic.

Hnh 1.2. Khi ng sao tam gic dng PLC

Hin nay trn th gii c rt nhiu hng sn xut PLC nh:

Ging Vin: Phm Vn Tun

Tt c chng u gm 4 thnh phn chnh (nh hnh v 1.1)

Hnh 1.3. Cu to ca PLC.

Giao din nhp

Giao din xut

Ngun cng sut

Ging Vin: Phm Vn Tun

Hnh 1.5. Cu trc b nh RAM, EEPROM.

Ging Vin: Phm Vn Tun

3. Truyen thong va t kiem tra loi

Hnh 1.6. Vng qut ca PLC.

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

1.3. Gii thiu chung v S7- 200

- Thi gian mt d liu khi mt ngun nui l 50 gi.

Hnh 1.7. CPU 212. + Cu hnh ca CPU 214 nh sau:

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

* Cu hnh vo ra ca S7- 200 CPU 22x

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

1.3.2. Cu trc b nh ca S7- 200

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

a ch cc vng nh d liu ca CPU 212

Ch c: SM0.0 n SM29.7. c / ghi: SM30.0 n SM45.7.

a ch cc vng nh d liu ca CPU 214

Ging Vin: Phm Vn Tun

- B m cng vo tng t, ch c: AQWx (x= 0 n 30)

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun

Ging Vin: Phm Vn Tun