TM TT BI GING VERILOG I.

Gii thiu CHNG I - TNG QUAN

1. Khong trng Khong trng ngn nhng t v c th cha khong cch, khong di, dng mi v dng ng dn. Do , mt lnh c th a ra nhiu dng phc tp hn m khng c nhng c tnh c bit. 2. Ch gii Nhng ch gii c th ch nh bng hai cch: (ging trong C/C++). Ch gii c vit sau hai du gch xin (//). c vit trn cng mt dng. c vit gia /* */, khi vit nhiu dng ch gii. 3. Ch s Lu tr s c nh ngha nh l mt con s ca cc bit, gi tr c th l: s nh phn, bt phn, thp phn, hoc thp lc phn. V d: 3b001, 5d30 = 5b11110, 16h5ED4 = 16d24276 = 16b0101111011010100 4. T nh danh T nh danh do ngi dng quy nh cho bin s, tn hm, tn mun, tn khi v tn trng hp. T nh danh bt u bng mt mu t hoc ng gch di _ ( khng bt u bng mt con s hoc $ ) v k c mi ch s ca mu t, nhng con s v ng gch di, t nh danh trong Verilog phn bit dng ch. 5. C php K hiu cho php: ABDCEabcdef1234567890_$ Khng cho php: cc k hiu khc -, &, #, @ 6. Ton t Ton t l mt, hai, hoc ba k t dng thc hin cc ton hng trn bin. Cc ton t bao gm >, +, &, !=. 7. T khaVerilog C nhiu t m c ngha c bit trong Verilog. V d: assign, case, while, wire, reg, and, or, nand, v module. Chng khng c dng nh t nh danh. T kha Verilog cng bao gm c ch dn chng trnh bin dch v System Task (h thng son tho) v cc hm.

Verilog HDL l mt trong hai ngn ng m phng phn cng thng dng nht, c dng trong thit k IC, ngn ng kia l VHDL. HDL cho php m phng cc thit k d dng, sa cha li, hoc thc nghim bng nhng cu trc khc nhau. Cc thit k c m t trong HDL l nhng k thut c lp, d thit k, d tho g, v thng d c hn dng biu , c bit l cc mch in ln. Verilog thng c dng m t thit k bn dng: Thut ton (mt s lnh ging ngn ng C nh: if, case, for,while). Chuyn i thanh ghi (kt ni bng cc biu thc Boolean). Cc cng kt ni( cng: OR, AND, NOT). Chuyn mch (BJT, MOSFET) Ngn ng ny cng ch r cch thc kt ni, iu khin vo/ra trong m phng. Cu trc chng trnh dng ngn ng Verilog // Khai bo module Module tn chng trnh (tn bin I/O); trng tn file.v. Input [msb:lsb] bin; Output [msb:lsb] bin; Reg [msb:lsb] bin reg; Wire [msb: lsb] bin wire; // Khai bo khi always, hoc khi initial. cc lnh Endmodule
.II.

// tn chng trnh

Cc tp tin vn bn ngun Verilog bao gm nhng biu hin thuc tnh t vng sau y:

ngha cc thut ng trong VERILOG

I. t gi tr Verilog bao gm 4 gi tr c bn. Hu ht cc dng d liu Verilog cha cc gi tr sau: 0: mc logic 0, hoc iu kin sai. 1: mc logic 1, hoc iu kin ng. X: mc logic tu nh Z: trng thi tng tr cao. X v Z dng c gii hn trong tng hp (synthesis) II. Wire M t vt liu ng dy dn trong mt mch in v c dng kt ni cc cng hay cc module. Gi tr ca Wire c th c, nhng khng c gn trong hm (function) hoc khi (block). Wire khng lu tr gi tr ca n nhng va?n phi c thc thi bi 1 lnh gn k tip hay bi s kt ni Wire vi u ra ca 1 cng hoc 1 module. Nhng dng c bit khc ca Wire: Wand(wired_and): gi tr ph thuc vo mc logic And ton b b iu khin kt ni n Wire. Wor (wired_or): gi tr ph thuc vo mc logic Or ton b b iu khin kt ni n Wire. Tri(three_state): tt c b iu khin kt ni n 1 tri phi trng thi tng tr cao. 1. C php Wire [msb:lsb] tn bin wire. Wand [msb:lsb] tn bin wand. Wor [msb:lsb] tn bin wor. Tri [msb:lsb] tn bin tri. 2. V d Wire c; Wand d; Assign d= a; Assign d= b;// gi tr d l mc logic ca php And a v b. Wire [9:0] A; // vect A c 10 wire. III. Reg Reg (register) l i tng d liu m n cha c gi tr t mt th tc gn k tip. Reg ch c dng trong hm v khi th tc. Reg l mt loi bin Verilog v khng nht thit l thanh ghi t nhin. Trong thanh ghi

Chng II - CC DNG D LIU

nhiu bit, data c lu tr bng cc ch s khng du v khng c k hiu ui m rng, c thc hin m ngi s dng c ch yu l s b hai. 1. C php: Reg [msb:lsb] tn bin reg. 2. V d: Reg a; // bin thanh ghi n gin 1 bit. Reg [7:0] A; // mt vect 8 bit; mt bank ca 8 thanh ghi. Reg [5:0]b, c; // hai bin thanh ghi 6 bit. IV. Input, Output, Inout Nhng t kho ny biu th u vo, u ra, v port hai chiu ca mt module hoc task. Mt port u ra c th c cu h?nh t cc dng: wire, reg, wand, wor, hoc tri. Mc nh l wire. 1. C php: Input [msb:lsb] port u vo. Output [msb:lsb] port u ra. Inout [msb:lsb] port u vo,ra hai chiu. 2. V d: Module sample (b, e, c, a); Input a; // mt u vo mc nh l kiu wire. Output b, e; // hai u ra mc nh l kiu wire. Output [1:0] c; /* u ra hai bit, phi c khai botrong mt lnh ring*/ Reg [1:0] c; // u c c khai bo nh mt reg. V. Integer (S nguyn) Integer l mt bin a nng. Trong tng hp chng c dng ch yu cho vng lp, tham s, v hng s. Chng hon ton l reg. Tuy nhiu chng cha d liu bng nhng s c du, trong khi khai bo dng reg cha chung bng s khng du. Nu chng cha nhng s m khng nh ngha thi gian bin dch th kch thc mc nh l 32 bit. Nu chng cha hng, s tng hp iu chnh cc s c kch thc nh nht cn thit cho s bin dch. 1. C php: Integer tn bin nguyn; tn hng nguyn; 2. V d: Integer a; // s nguyn n gin 32bit. Assign b= 63; // mc nh l mt bin 7 bit.

VI. Supply 0, Supply1 Xc nh ch ng dn ln mc logic 0 ( t), logic 1( ngun) theo th t nh sn. VII. Time Time l mt lng 64 bit m c s dng cng vi $time, h thng thao tc cha lng thi gian m phng. Time khng c h tr tng hp v v th ch c dng trong mc ch m phng. 1. C php: Time bin time; 2. V d: Time c; c = $time; // c = thi gian m phng dng in. VIII. Parameter (Tham s) Mt Parameter xc nh 1 hng s m c t khi bn cho v d c th l mt module. Cc ny cho php ta c th sa cha. 1. C php: Parameter par_1= gi tr, par_2= gi tr, ; Parameter [gii hn] par_3 = gi tr?; 2. V d: Parameter add = 2b00, sub = 3b111; Parameter n = 4; Parameter [3:0] par_2 = 4b1010; reg [n-1:0] harry; /* mt thanh ghi 4 bt m rng c t bi tham s n trn */. always @(x) y = {{(add - sub) {x}}} if (x) begin state = par_2[1]; else state =par_2[2]; end.

Cc cng logic c s l mt b phn ca ngn ng Verilog. C hai c tnh c ch r l: drive_strenght v delay. Drive_strenght ch sc bn ca cng. bn u ra l s kt ni mt chiu n ngun, k to nn s kt ni trong sut trans dn, kt thc l tng tr ko ln hoc xung. Drive_strenght thng khng c ch r, trong trng hp ny bn mc nh l strong1 v strong0 . Delay: nu delay khng c ch r, th khi cng khng c tr hon truyn ti; nu c hai delay c ch nh, th trc tin l miu t tr hon ln, th hai l tr hon xung. Nu ch c mt delay c ch nh, th khi tr hon ln xung l nh nhau. Delay c b qua trong tng hp. Phng php ca s tr hon ch nh ny l mt trng hp c bit ca Parameterized Modules. Cc tham s cho cc cng c s phi c nh ngha trc nh delay. I. Cc cng c bn Cc cng c bn c mt u ra, v c mt hoc nhiu u vo. Trong cc cng, c php c th biu din bn di, cc t kho ca cc cng: and, or, nand, nor. 1. C php GATE (drive_strength)#(delays) Tn t kha cng _tn (output, input_1, input_2, , input_N); Delay: #( ln, xung) hoc #ln_v_xung hoc #( ln_v_xung) 2. V d And c1 (o, a, b, c. d); // c 4 u vo cng And gi l c1 c2 (p, f, g); // v 2 u vo cng and gi l c2 Or #(4,3) ig ( o, b, c); // cng Or c gi l ig, rise time = 4, fall time = 3 Xor #(5) xor1 (a, b, c); // sau 5 n v thi gian th a = b xor c II. Cng buf, not Cc cng ny thc thi m v o theo theo th t nh sn. Chng c mt u vo, hai hay nhiu u ra. C php c th biu din xem bn di; t kho buf, not. 1. C php Tn t kha cng _tn (output_1, output_2, , output_N, input); 2. V d Not #(5) not_1( a,c); // sau 5 n v thi gian th a = o c Buf c1 (o, p, q, r, in); // b m 5 u ra v 2 u ra c2 (p, f, g);

Chng III - CC CNG C BN TRONG VERILOG

ChngV- TON T
I. Ton t s hc Nhng ton t ny thc hin cc php tnh s hc. Du + v - c th c s dng mt trong hai ton t n (-z) hoc kp (x - y). 1. Ton t: +, -, *, /, %. 2. V d: parameter n = 4; Reg[3:0] a, c, f, g, count; f= a +c; g= c n; count = (count +1) % 16; // c th m t 0 n 15. II. Ton t quan h Ton t quan h so snh hai ton hng v tr v mt n bit l 0 hoc 1. Nhng ton t ny tng hp vo dng c so snh. Bin Wire v Reg l nhng bin dng. V th, (-3b001) = (3b111) v (-3b001) > ( 3b110) nhng nu l s nguyn th -1< 6. 1. Cc ton t quan h: <, <=, >, >=, = =, !=. 2. V d: If (x= =y) e =1; Else e= 0; // so snh hai vector a, b reg [3:0] a, b; if (a[3] = =b [3]) a[2:0] >b[2:0]; else b[3]; III. Ton t bit_wire So snh tng bit hai ton ton hng. 1. Cc ton t: ~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwire XOR), ~^ hoc, ^~ (bitwire XNOR). 2. V d: Module and2(a, b, c); Input [1:0] a, b; Output [1:0] c;

Assign c = a & b; Endmodule IV. Ton t logic Ton t logic tr v 1 bit n 0 hoc 1. chng ging nh ton t bitwire ch l nhng ton hng n bit. Chng c th lm vic trn biu thc, s nguyn hoc nhm bit, v coi nhu tt c cc gi tr khng bng 0 l 1. Ton t logic c dng nhiu trong lnh iu kin (if else), khi chng lm vic trn biu thc. 1. Ton t: !(NOT), && (AND), || (OR) 2. V d: Wire [7:0] x, y, z; Reg a; if ((x= = y)&&(z)) a=1; else a=! x; V. Ton t bin i C tc dng trn tt c cc bit ca mt vect ton hng v tr v gi tr n bit. Nhng ton t ny l h?nh thc t i s ca cc ton t bitwire trn. 1. Cc ton t: ~ (bin i NOT), & (bin i AND), ~&( bin i NAND), | (bin i OR), ~| (bin i NOR), ^ (bin i XOR), ~^ hoc ^~ (bin i XNOR). 2. V d: Module chk_zero (a,z); Input [2:0] a; Output z; Assign z = ~| a; Endmodule VI. Ton t ghp Dch ton t u bng ch s ca cc bit c nh ngha bi ton t th hai. V tr cn trng s c in vo vi nhng s 0 cho c hai trng hp dch tri hoc phi.

1. Ton t << ( dch tri), >> (dch phi). 2. V d: assign c = a<<2; c = a dch tri 2 bit cc ch trng c in vi nhng s 0. VII. Ton t dch Ghp hai hoc nhiu ton hng thnh mt vect ln. 1. Ton t: {} (concatenation) 2. V d: Wire [1:0] a, b; Wire [2:0] x; Wire [3:0] y, Z; Assign x = {1b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0]. Assign y = {a, b}; // y[3]= a[1], y[2] = a[0], y[1] = b[1], y[0] = b[0]. VIII. Ton t th bn To ra nhiu bn sao ca mt mc chn. 1. Ton t: {n{ mc chn }} n nhm th bn trong mt mc chn. 2. V d: Wire [1:0] a, b; Wire [3:0] x; Assign x = {2{1b0},a}; // x= {0, 0, a}. IX. Ton t iu kin Ging nh C/C++. Chng nh gi mt trong hai biu thc c bn trong mt iu kin. N s tng hp thnh b a cng (MUX). 1. Ton t : (iu kin)? kt qu khi iu kin ng : kt qu khi iu kin sai. 2. V d: assign a = (g) ? x : y; Assign a = ( inc = =2) ? a+1: a-1; X. Th t ton t Nhng ton t trong mc ging nhau nh gi t tri sang phi

Ton t [] () !, ~ &, |, ~&, ~|, ^, ~^ +, {} {{ }} *, /, % +, <<, >> <, <=, >, >= = =, != & ^, ~^ | &&, || ?:

Tn Chn bit, chn phn Phn trong ngoc n Mc logic v bit_wire NOT Bin i: AND, OR, NAND, NOT, XOR, XNOR. Du ch s m s dng. Ghp ni { 3b101,3b110} = 6b101110 Th bn {3{3b101 }}=9b101101101 Nhn, chia, phn trm. Cng tr nh phn. Dch tri, phi. Du so snh. Bin Reg v wire c ly bng nhng s dng. Bng v khng bng trong ton t logic. Bit_wire AND, and tt c cc bit vi nhau. Bit_wire XOR, Bit_wire XNOR. Bit_wire OR. Ton t logic AND, OR. x = ( iu kin ) T:F

Chng VI- TON HNG

I. Literals (dng k t) L ton hng c gi tr khng i m c dng trong biu thc Verilog. C hai dng k t l: Chui: l mt mng c nhiu k t c t trong du . Ch s: l nhng s khng i, nh phn, bt phn, thp phn, hoc s hex. 1. C php cc ch s: nF dddd Trong : n : s nguyn miu t s bit. F: mt trong bn nh dng sau: b( s nh phn), o( s bt phn), d( s thp phn), h( s hex). 2. V d: time is // chui k t. 267 // mc nh 32 bit s thp phn. 2b01 // 2 bit nh phn. 20h B36E // 20 bit s hex. o62 // 32 bit bt phn. II. Chn 1 phn t bit v chn 1 phn cc bit y l s la chn mt bt n hoc mt nhm bit theo th t, t mt wire, reg hoc t tham s t trong ngoc [ ]. Chn 1 phn t bit v chn 1 phn cc bit c th c dng nh l cc ton hng trong biu thc bng nhiu cch thc ging nhau m cc i tng d liu gc c dng. 1. C php: Tn bin [ th t bit]. Tn bin [ msb: lsb]. 2. V d: Reg [7:0] a, b; Reg [3:0] ls; c = a[7] & b[7]; ls = a[7:4] + b[3:0]; III. Gi hm chc nng Gi tr tr v ca mt hm c th c dng trc tip trong biu thc m khng cn gn trc cho bin reg hoc wire. Gi hm chc nng

nh l mt trong nhng ton hng. Chiu rng bt ca gi tr tr v chc chn c bit trc. 1. C php: Tn hm(danh sch bin). 2. V d: Assign a = b & c & chk_bc(b, c); Function chk_bc; Input c, b; Chk_bc = b^ c; Endfunction IV. Wire, reg, v tham s Wire, reg, v tham s c th c dng nh l cc ton hng trong biu thc Verilog.

I. Khai bo modules: Mt module l bn thit k ch yu tn ti trong Verilog. Dng u tin ca khai bo module ch r danh sch tn v port (cc i s). Cc dng k tip ch r dng I/O (input/output, hoc inout) v chiu rng ca mi port. Mc nh rng port l 1 bit. Sau , cc bin port phi c khai bo wire, wand, , reg (mc nh l wire). Cc u vo l dng wire khi d liu c cht bn ngoi module. Cc u ra l dng reg nu cc t/hiu ca chng c cha trong khi always hoc initial. 1. C php: Module tn module (danh sch port); Input [msb:lsb] danh sch port u vo; Output [msb:lsb] danh sch port u ra; Inout [ msb:lsb ] danh sch port vo_ ra; cc lnh endmodule 2. V d: Module add_sub(add, in1, in2, out); Wire, reg, v tham s: Input[7:0 ] in1, in2; Wire in1, in2; Output [7:0] out; Reg out; cc lnh khc Endmodule II. Ch nh lin tip: Cc ch nh lin tip c dng gn mt gi tr ln trn mt wire trong mt module; bn ngoi khi always hoc khi initial. Cc ch nh lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s ch nh mt gi tr n mt wire trong lc khai bo. Lu , cc lnh ch nh lin tip th tn ti v c chy lin tc trong sut qu trnh m phng. Th t cc lnh gn khng quan trng. Mi thayi bn phi ca bt c u vo s lp tc thayi bn tri ca ccu ra. 1. C php: Wire bin wire = gi tr?; Assign bin wire = biu thc;

Chng VII - MODULES

2. V d: Wire [ 1:0 ] a = 2b 01; Assign b = c &d; Assign d = x | y; III. Module instantiations: Cc khai bo module phi theo mu t cc i tng thc t (instantiation). Cc module n bn trong cc module khc, v mi dn chng to mt i tng c nht t khun mu. Ngoi tr l module mc trn l nhng dn chng t chnh chng. Cc port ca module v d phi tha nhng nh ngha trong khun mu. y l mt l thuyt: bng tn, s dng du chm(.) .tn port khun mu (tn ca wire kt ni n port). Bng v tr, t nhng port nhng v tr ging nhau trong danh sch port ca c khun mu ln instance. 1. C php: Tn instance1 (danh sch kt ni port ); Tn instance2(danh sch kt ni port); 2. V d: // nh ngha module module and4(a,b,c); input [3:0]a,b; output [3:0]c; assign c = a&b; endmodule // module instantiations wire [3:0] in1, in2; wire [3:0] o1, o2; // t v tr and4 C1(in1, in2,o1); // tn and4 C2(.c(o2), .a(in1), .b(in2));

Chng VIII - KHUN MU HNH VI (BEHAVIORAL)

Verilog c 4 mc khun mu: Chuyn mch. (Khng xt gio trnh ny). Cng. Mc trn d liu. Hnh vi hoc th tc c cp bn di. Cc lnh th tc Verilog c dng to mt mu thit k mc cao hn. Chng ch ra nhng cch thc mnh ca vc lm ra nhng thit k phc tp. Tuy nhin, nhng thay i nh n phng php m ha c th gy ra bin i ln trong phn cng. Cc lnh th tc ch c th c dng trong nhng th tc. I. Nhng ch nh theo th tc L nhng ch nh dng trong phm vi th tc Verilog (khi always v initial). Ch bin reg v integers (v chn n bit/ nhm bit ca chng, v kt ni thng tin) c th c t bn tri du = trong th tc. Bn phi ca ch nh l mt biu thc m c th dng bt c dng ton t no. II. Delay trong ch nh Trong ch nh tr t l khong thi gian tri qua trc khi mt lnh c thc thi v bn tri lnh gn c to ra. Vi nhiu ch nh tr (intraassignment delay), bn phi c nh gi tr trc tip nhng c mt delay ca t trc khi kt qu c t bn tri lnh gn. Nu thm mt qu trnh thay i na cnh bn phi tn hiu trong khong thi gian t, th khng cho kt qu u ra. Delay khng c h tr bi cc cng c. 1. C php ch nh th tc: Bin = biu thc; Ch nh tr: #t bin = biu thc; intra_assignment delay: bin = #t biu thc. 2. V d: Reg [6:0] sum; reg h, zilch; Sum[7] = b[7]^c[7]; // thc thi tc thi; Ziltch = #15 ckz & h; // ckz & h nh gi tr tc thi; //ziltch thay i sau 15 n v thi gian. #10 hat = b & c; /* 10 n v thi gian sau khi ziltch thay i, b & c c nh gi v hat thay i*/ III. Ch nh khi

Ch nh khi (=) thc hin lin tc trong th t lnh c vit. Ch nh th hai khng c thc thi nu nh ch nh u cho hon thnh. 1. C php: Bin = biu thc; Bin = #t biu thc; #t bin = biu thc; 2. V d: Initial Begin a = 1; b = 2; c = 3; #5 a = b + c; // sau 5 n v thi gian thc hin a = b + c = 5. d = a; // d = a = 5. Always @(posedge clk) Begin Z = Y; Y = X; // thanh ghi dch. y = x; z = y; // flip flop song song. IV. Begin end Lnh khi begin end c dng nhm mt vi lnh m mt lnh c php c cho php. Bao gm function, khi always v khi initial. Nhng khi ny c th c ty gi tn. V bao gm khai bo reg, integer, tham s. 1. C php: Begin: tn khi Reg[msb:lsb] danh sch bin reg; Integer [msb:lsb] danh sch integer; Parameter [msb:lsb] danh sch tham s; cc lnh End 2. V d: function trivial_one;// tn khi l: trivial_one input a; begin: adder_blk integer i; lnh end V. Vng lp for Ging nh c/c++ c dng thc hin nhiu ln mt lnh hoc khi lnh. Nu trong vng lp ch cha mt lnh th khi begin end c th b qua.

1. C php: For (bin m = gi tr 1; bin m </ <=/ >/ >= gi tr 2; bin m = bin m +/- gi tr?) begin lnh end 2. V d: For (j = 0; j<=7; j = j+1) Begin c[j] = a[j] & b[j]; d[j] = a[j] | b[j]; end VI. Vng lp while Vng lp while thc hin nhiu ln mt lnh hoc khi lnh cho n khi biu thc trong lnh while nh gi l sai. 1. C php: While (biu thc) Begin cc lnh end 2. V d: While (!overflow) @(posedge clk); a = a +1; end VII. Khi lnh if else if else Thc hin mt lnh hoc mt khi lnh ph thuc vo kt qu ca biu thc theo sau mnh if. C php If (biu thc) Begin cc lnh end else if (biu thc) Begin cc lnh end else

Begin cc lnh end VIII. Case Lnh case cho php la chn trng hp. Cc lng trong khi default thc thi khi khng c trng hp la chn so snh ging nhau. Nu khng c s so snh, bao gm c default, l ng, s tng hp s to ra cht khng mong mun. 1. C php: Case (biu thc) Case 1: Begin cc lnh end Case 2: Begin cc lnh end Case 3: Begin cc lnh end default: begin cc lnh end endcase 2. V d: Case (alu_clk) 2b00: aluout = a + b; 2b01: aluout = a - b; 2b10: aluout = a & b; default: aluout = 1bx; endcase

I. Khi always: L cu trc chnh trong khun mu RTL (Register Transfer Level). Khi always c th c dng trong cht, flip flop hay cc kt ni logic. Tt c cc khi always trong mt module thc thi mt cch lin tc. Nu cc lnh ca khi always nm trong phm vi khi begin end th c thc thi lin tc, nu nm trong khi fork join, chng c thc thi ng thi (ch trong m phng). Khi always thc hin bng mc, cnh ln/xung ca mt or nhiu tn hiu (cc tn hiu cch nhau bi t kha OR). C php: Always @(s kin 1 or s kin 2 or) Begin cc lnh end Always @(s kin 1 or s kin 2 or) Begin: tn khi cc lnh end II. Khi initial Tng t khi always nhng khi initial ch thc thi mt ln t lc bt u ca qu trnh m phng. Khi ny l tiu biu bin khi chy v ch nh dng sng tn hiu trong lc m phng. 1. C php: Initial Begin cc lnh end 2. V d: Initial Begin Clr = 0; Clk = 1; End Initial Begin a = 2b00; #50 a = 2b01; #50 a = 2b10; end

Chng IX KHI ALWAYS V KHI INITIAL

Hm c khai bo trong phm vi mt module, v c th c gi t cc lnh lin tc, khi always, hoc cc hm khc. Trong lnh ch nh lin tc, cng c ch nh lin tc khi bt k cc hm khai bo u vo thay i. Trong chng trinh chng c ch nh ti khi cn gi. Cc hm m t s kt ni logic, v khng to ra cht. Do mt lnh if m khng else s m phng , mc d n c cht d liu nhng m phng th khng c. y l trng hp d ca tng hp khng c m phng theo sau. y l khi nim tt m ha hm, v vy chng s khng to ra cht nu m hm c dng trong mt chng trnh. I. Khai bo hm: Khai bo hm l ch ra tn hm, chiu rng ca hm gi tr tr v, i s hm d liu vo, cc bin (reg) dng trong hm, v tham s cc b ca hm, s nguyn ca hm. 1. C php: Function [msb:lsb] tn hm; Input [msb:lsb]bin vo; Reg [msb:lsb]bin reg; Parameter [msb:lsb] tham s; Integer [msb:lsb] s nguyn; cc lnh endfunction 2. V d Function [7:0] my_func; // hm tr v gi tr 8 bit Input [7:0] i; Reg [4:0] temp; Integer n; temp = i[7:4]| (i[3:0]); my_func = temp,i[1:0] ; endfunction II. V d: Mt hm ch c cha mt d liu ra. Nu c nhiu hn mt gi tr tr v c yu cu, u ra s phi kt ni to thnh mt vector trc khi t gi tr cho hm gi tn hm. Gi tn chng trnh module c th trch ra sau , ring i vi u ra t cc biu mu ni vo nhau. V d di y minh ha tng qut cch dng v c php hm trong verilog. 1. C php: Tn hm = biu thc.

Chng X- HM

2. V d: Module simple_processor (instruction, outp); Input [31:0] instruction; Output [7:0] outp; Reg [7:0] outp;// c th c gn trong khi always. Reg func; Reg [7:0] opr1, opr2; Function[16:0] decode add(instr) Input [31:0] instr; Reg add_func; Reg [7:0] opcode, opr1, opr2; Begin Opcode = instr[31:24]; Opr1 = instr[7:0]; Case (opcode) 8b 10001000: begin add_func = 1; opr2 = instr[15:8]; end 8b 10001001: begin add_func = 0; opr2 = instr[15:8]; end 8b 10001010: begin add_func = 1; opr2 = 8b 00000001; end default: begin add_func = 0; opr2 = 8b00000001; end endcase decode_add = add_func, opr2, opr1 ; end endfunction always @(intruction) begin

{func, opr2, opr1}= decode_add (intruction); if (func= =1) outp = opr1+ opr2; else outp = opr1 opr2; end endmodule

Cht d liu (latches): c suy nu mt bin, mt trong cc bit khng c gn trong cc nhnh ca mt lnh if. Cht d liu cng c suy ra t lnh case nu mt bin c gn ch trong mt vi nhnh. C php: If else if else v case. I. Thanh ghi Edge_triggered, flip_flop, b m: Mt thanh ghi (flip_flop) c suy lun bng vic dng xung kch cnh ln hoc xung trong danh sch s kin ca lnh khi always. C php: Always @(posedge clk or posedge reset1 or nesedge reset2) Begin If (reset1) begin Cc ch nh reset end else if (reset2) begin Cc ch nh reset End Else begin Cc ch nh reset End II. B a cng: c suy ra bi vic gn mt bin m gi tr mi bin khc nhau trong mi nhnh ca lnh if hoc case. C th trnh cc ch nh v mi nhnh c th tn ti bng vic s dng ngoi nhng nhnh mc nh. Ch rng cht s c to ra nu mt bin khng c gn cho cc iu kin nhnh c th tn ti.

Chng XI CHC NNG LINH KIN

 hon thin m c th c c, dng lnh case to mu a cng ln. III. B cng, tr: Ton t cng tr trong b cng tr m c chiu rng ph thuc vo chiu rng ca ton t ln hn. IV. B m 3 trng thi: B m ba trng thi c suy ra nu bin c gn theo iu kin gi tr tng tr cao Z dng mt trong cc ton t: if, case, V. Cc linh kin khc: Hu ht cc cng logic c suy ra t vic dng nhng ton hng tng ng ca chng. Nh mt s la chn mt cng hoc mt thnh phn c th c gii thch r rng bng v d c th v s dng cc cng c s (and, or, nor, inv) min l bng ngn ng Verilog.

I. Cu trc mt chng trnh dng ngn ng Verilog: // Khai bo module Module tn chng trnh (tn bin I/O); // tn chng trnh trng tn file.v. Input [msb:lsb] bin; Output [msb:lsb] bin; Reg [msb:lsb] bin reg; Wire [msb: lsb] bin wire; // Khai bo khi always, hoc khi initial. cc lnh Endmodule II. Mt s v d: Phn mn h tr: MAX+plusII 10.0 BASELINE 1. V d 1: a. Chng trnh tnh NOR cc bit ca bin vo module vdcong(in,out); input[3:0] in; output out; assign out= ~|in; endmodule b. M phng

Chng XII - MT S V D

2. V d 2: a. Chng trnh cng hai bin bn bit module adder (sum_out, carry_out, carry_in, ina, inb);

output [3:0]sum_out; input [3:0]ina, inb; output carry_out; input carry_in; wire carry_out, carry_in; wire[3:0] sum_out, ina, inb; assign { carry_out, sum_out } = ina + inb + carry_in;

wire en; always @(w or en) begin if(en==1'b1) begin case(w) 2'b00: y<=4'b1000; 2'b01: y<=4'b0100; 2'b10: y<=4'b0010; default:y<=4'b0001; endcase end else end y<= 4'b0000;

Endmodule b. M phng

endmodule b. M phng

3. V d 3: a. Chng trnh gii m 2 sang 4 module dec2to4 (w, en, y); input [1:0] w; input en; output[3:0] y; wire[1:0]w; reg[3:0]y;

4. V d 4: a. B dn knh 2 sang 1 module mux12(w0, w1, s, y); input w0, w1; input s; output y; wire w0, w1, s; reg y; always @(w0 or w1 or s) begin if(s==1) y = w0; else y = w1; end endmodule b. M phng

input w0, w1, w2, w3; input[1:0] s; output y; wire w0, w1,w2,w3; reg y; always @(w0 or w1 or s) begin case (s) 2'b00: y=w0; 2'b01: y=w1; 2'b10: y=w2; default: y = w3; endcase end endmodule b. M phng

5. V d 5: a. Chng trnh dn knh 4 sang 1 module mux14(w0, w1, w2, w3, s, y);

6. V d 6: a. Chng trnh i BCD sang by on Module mp_led(bcd,led); input [3:0] bcd; output [7:0] led;

wire [3:0] bcd; reg [7:0] led; always @(bcd) begin case(bcd) 4'b0000: led = 8'b00000011; 4'b0001: led = 8'b10011111; 4'b0010: led = 8'b00100101; 4'b0011: led = 8'b00001101; 4'b0100: led = 8'b10011001; 4'b0101: led = 8'b01001001; 4'b0110: led = 8'b01000001; 4'b0111: led = 8'b00011111; 4'b1000: led = 8'b00000001; 4'b1001: led = 8'b00001001; default: led = 8'b00000000; endcase end endmodule b. M phng

7. V d 7: a. Chng trnh gim t 9 xung 0, hin th ra led 7 on module bcd (clock, rst, s1, led, digit1); input clock, s1, rst; output [7:0] led; output digit1; reg [7:0] led; reg [3:0] bcd; wire digit1; assign digit1 = 1'b1; always @(posedge clock ) begin if (rst == 1'b1) bcd <= 4'b1001; else if (s1 == 1'b1) bcd <= bcd - 1'b1; if (bcd == 4'b0) bcd <= 4'b1001; end always @(posedge clock) begin case(bcd) 4'b0000: led = 8'b11111100; 4'b0001: led = 8'b01100000; 4'b0010: led = 8'b11011010; 4'b0011: led = 8'b11110010; 4'b0100: led = 8'b01100110; 4'b0101: led = 8'b10110110; 4'b0110: led = 8'b10111110; 4'b0111: led = 8'b11100000; 4'b1000: led = 8'b11111110; 4'b1001: led = 8'b11100110; default: led = 8'b11111111; endcase end endmodule

b. M phng

4'b0010: led = 8'b11011010; 4'b0011: led = 8'b11110010; 4'b0100: led = 8'b01100110; 4'b0101: led = 8'b10110110; 4'b0110: led = 8'b10111110; 4'b0111: led = 8'b11100000; 4'b1000: led = 8'b11111110; 4'b1001: led = 8'b11100110; default: led = 8'b11111111; endcase end

8. V d 8: a. Chng trnh tng t 0 n 9, hin th ra led 7 on module bcdtang (clock, rst, s1, led, digit1); input clock, s1, rst; output [7:0] led; output digit1; reg [7:0] led; reg [3:0] bcd; wire digit1; assign digit1 = 1'b1; always @(posedge clock ) begin if (rst == 1'b1) bcd <= 4'b0; else if (s1 == 1'b1) bcd <= bcd + 1'b1; if (bcd == 4'b1001) bcd <= 4'b0000; end always @(posedge clock) begin case(bcd) 4'b0000: led = 8'b11111100; 4'b0001: led = 8'b01100000;

endmodule b. M phng

TI LIU THAM KHO

1. Verilog Digital System Design 2. Introduction of Verilog Peter M. Nyasulu 3. Cadence Verilog XL Reference Manual 4. Synopsys HDL Compiler for Verilog Reference Manual