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LP TRNH VK PIC VI MPLAB C18

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Bi 1 : Ci t MPLAB IDE 8.36 1.1 Gii thiu MPLAB IDE l phn mm c h tr bi Microchip, dng son tho code cho cc ng dng ca PIC. Hin ti, thng 8/2010 MPLAB IDE c phin bn 8.51. Trong ti liu ny ti chn phin bn 8.36 v n c kh nhiu li v cu hnh . Cc phin bn khc nh 8.43, bn c th khng chn cu hnh ban u nhng bn thn n c th t ng tm kim cc th vin cn thit trong qu trnh bin dch. Vi phin bn 8.36 chng ta phi cu hnh ton b cho IDE. 1.2 Ci t MPLAB IDE 8.36 Bc 1 : Double Click vo file setup trong th mc MPLAB IDE 8.36. Mn hnh Welcome s hin ra nh sau. Bn chn Next tip tc.

Hnh 1.1 : Welcome to MPLAB IDE 8.36 Bc 2 : Chn I accept the term of the license agreement v chn Next.

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 1.2 : License Agreement Bc 3 : ch mc nh l ci t Complete v chn Next tip tc.

Hnh 1.3 : Chn ci t complete Bc 4 : Chn ng dn ci t, ta nn mc nh l C:\Program Files\Microchip\

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 1.4 : Chn ng dn ci t Bc 5 : Tip tc chn I accept cho Maestro License v C32 License.

Hnh 1.5 : Maestro License

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 1.6 : C32 License Bc 6 : Giao din sau tng kt li cc la chn ca bn, nhn Next tin hnh ci t. Nu mun hiu chnh bn nhn Back.

Hnh 1.7 : Bt u ci t

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 1.8 : Ch ci t xong Bc 7 : Khi ci t xong MPLAB IDE s hi bn c cn ci Hi Tech khng. y l compiler C h tr cho MPLAB IDE, tuy nhin ta s khng dng compiler ny m s dng MPLAB C18. Bn chn No nhn Finish hon tt vic ci t MPLAB IDE.

Hnh 1.9 : Ci t hon tt Thng bo di u xut hin, thng k cc ti liu hng dn i km. Cc ti liu ny u nm trong th mc ci t C:\Program Files\Microchip\

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 1.10 : Cc ti liu hng dn

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Bi 2 : Ci t compiler MPLAB C18 2.1 Gii thiu Khi ci t xong MPLAB IDE, compiler mc nh cho n l MPASM, dng dch project vit bng ASM sang file HEX. Mun vit chng trnh bng C, ta cn phi ci t thm 1 compiler khc c h tr cho chip PIC ang dng. Trong phn ny, ti th nghim trn vi iu khin PIC18F4520 v chn compiler C18 h tr cho lp trnh C chun. 2.2 Cc bc ci t Bc 1 : Double Click vo file MPLAB C18 V1.0.exe tin hnh ci t, mn hnh welcome ca MPLAB C18 s hin ra nh sau :

Hnh 2.1 : Welcome MPLAB C18 Bc 2 : Chn ni lu tr cho cc file bin dch ca MPLAB C18, ta c th mc nh l C:\mcc18 .

Hnh 2.2 : Chn ng dn lu tr Bc 3 : Chn la cc thnh phn ca gi MCC18, thng thng ta s chn ht tt c cc gi trong compier C18.

Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 2.3 : Chn cc gi ci t Bc 4 : Nhn Next tin hnh ci t

Hnh 2.4 : Ci t C18 Ch cho n khi ci t xong.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 2.5 : Ch ci t C18 Bc 5 : Nhn Finish kt thc ci t MPLAB C18.

Hnh 2.6 : Kt thc ci t C18 2.3 Cp nht ln C18 version 3.01 Phin bn m ta va ci t l C18 v1.0. cp nht ln v3.01, ta s double click v file MPLAB-C18-pgrade-doc-v3_01.exe. Mn hnh welcome s hin ra nh sau:

Hnh 2.7 : Welcome C18 update Chn I Accept v nhn Next tip tc ci t.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 2.8 : License Agreement Cc ti liu h tr lp trnh cho compiler C18 i km.

Hnh 2.9 : Cc ti liu hng dn Chn th mc mc nh cho vic update (ging vi th mc ci t C18)

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

mc nh cc thnh phn s c ci t, khng cn phi check thm.

Hnh 2.10 : Cc gi ci t C18 v3.01 Check chn thm cc option di y MPLAB IDE t ng cu hnh cc thng s tng thch vi phin bn C18 v3.01

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 2.11 : Chn cu hnh update cho MPLAB IDE Chn Next tin hnh Update

Hnh 2.12 : Tin hnh ci t Ch cho n khi hon tt.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 2.13 : Ch cho n khi hon tt Nhn Finish kt thc.

Hnh 2.14 : Ci t hon tt

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Bi 3 : To project trn MPLAB 8.36 v C18 3.01 To 1 project ln u trn MPLAB kh phc tp. Ngi s dng cn phi cu hnh cho MPLAB kh nhiu. Tuy nhin hu ht cc thng s cu hnh ny s c lu li cho ln sau, chng ta ch cn phi thit lp 1 ln. Phn ny hng dn cch to 1 project n gin trn MPLAB cho chip 18F4520 v mch np PICKit2 trn board BKIT PIC. 3.1 To mi project Kch hot chng trnh MPLAB IDE 8.36 t biu tng Microchip trn mn hnh Desktop, ca s sau y s hin ra.

Hnh 3.1 : Mn hnh khi ng ca MPLAB IDE 8.36 Chn menu Project v chn New

Hnh 3.2 : To mi project Ca s sau y hin ra, bn t tn cho project khung Project Name v chn ng dn cho n khung Project Directory.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.3 : t tn v chn th mc lu tr Ca s lm vic ca project s hin ra bn tri nh hnh di y. Nu ca s project khng hin ra bn s chn menu View v chn Project.

Hnh 3.4 : Ca s project Chn compile C18 cho project ny bng cch chn vo menu Project v chn Select Language Toolsuite.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.5 : Chn Language ToolSuite (Compiler) Chn Active Toolsuite l Microchip C18 Toolsuite. Cc ng dn ca cc chng trnh trong gi compiler cho C18 c cu hnh trong lc ci t C18 upgrade, bn khng cn phi chnh li. Cc gi ny u nm trong th mc C:\mcc18.

Hnh 3.6 : Chn compiler C18 3.2 Cu hnh cho chip Phn ny c nh hng i vi qu trnh dch v np cho chip. Chn menu Configure v chn Select Device chn chip.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.7 : Select Device Giao din di y hin ra v bn chn cho ng chip m mnh ang dng. y ti chn chip PIC18F4520.

Nhn OK ng ca s ny li. Tip theo l vic la chn cu hnh thch anh v 1 s cu hnh khc. Bn vo li menu Configure v chn Configuration Bits

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.8 : Configuration Bits Mn hnh bn cu hnh cho ch hot ng ca chip di y hin ra. Check b du chn Configuration Bits set in code bn c th thay i cc thng s. Thng s u tin l ch thch anh, ty vo mi loi chip v thch anh m chn la khc nhau. y ti s dng thch anh ngoi 12MHz nn s chn ch thch anh l HS (High Speed). Cc ch thch anh ca PIC18F4520 s c cp cc bi sau. PORTB bit 4-0 ch mt nh l cc chn analog. Khi khng s dng analog bn cn phi chnh sang ch Digital khi reset. Disable chc nng Low Voltage Programming (LVP - Np in p thp), mch PICKit2 khng h tr chc nng ny. Sau khi hon thnh bn check li Configuration Bits set in code v ng ca s ny li.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.9 : Thit lp thch anh, PortB, LVP 3.3 To mi file v add th vin cho project Bc tip theo l to file source vit code. T toolbar bn c th chn New File hoc v menu File v chn New.

Hnh 3.10 : To mi source file

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Mt file mi c to ra vi tn mc nh l Untitled nh hnh di y.

Hnh 3.11 : File mi c to ra Bn nhn v menu File v chn Save As lu li file ny. Ca s di y hin ra v bn chn ng dn lu cho chnh xc. Thng thng ta s lu trong th mc cha project hin ti cho d qun l.

Hnh 3.12 : Lu file trong th mc cha project Nhn Save lu file vi tn mi l main.c v ng ca s trn li. Bc tip theo l add file va mi lu (main.c) v th mc Source File ca project. Click chut phi vo Source File v chn Add Files

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.13 : Add file vo Source Files Chn ng dn n file main.c v nhn Open.

Hnh 3.14 : Browse ng dn n main.c File main.c s c add vo mc Source File ca project nh hnh bn di.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.15 : Add xong main.c cho Source Files Tip theo ta s add cc th vin cho project. u tin l Header Files. Cng tng t nh khi add file vo Source File, click chut phi v chn Add Files. Browse ng dn n C:\mcc18\h v chn file p18f4520.h hoc g tn file ny vo mc File name ri nhn Open.

Hnh 3.16 : Add Header File Add file vo mc Linker Script, browse ng dn n C:\mcc18\lkr v chn file 18f4520.lkr.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.17 : Add file Linker Script Add file lib vo mc Library Files, 18f4520.lib ti th mc C:\mcc18\lib

Hnh 3.18 : Add Library File 3.4 Cu hnh cho qu trnh dch project Khi dch project, compiler cn 1 s file object ca n (chng hn nh c018i.o), ta cn phi ch ng dn tm kim cc file object ny cho compiler. i vi 1 s phin bn MPLAB, n t ng tm ng cc file ny. Tuy nhin i vi phin bn 8.36 ta cn phi ch nh ng dn tm kim. T menu Project, chn Build Option v chn Project.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Giao din Build Option hin ra, ti mc Show Directories for bn chn Include Search Path, chn New v Browse ng dn n C:\mcc18\h. Sau chnh sang Library Search Path v to mi 1 ng dn C:\mcc18\lib

Hnh 3.19 : To ng dn cho include file

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.20 : To ng dn cho Library File Nhn OK hon tt vic cu hnh ca qu trnh dch. 3.5 Vit code cho project Double Click vo file main.c v bt u vit code cho project. Ta vit 1 on code nh lm cho cc led ni vi PORTB ca vi iu khin sng xen k (PORTB = 0xAA) Code: #include <p18f4520.h> void main() { TRISB = 0x00; PORTB = 0xAA; while(1); }

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.21 : Double Click v main.c v vit code kim tra code vit c li hay khng bn vo menu Project v chn Build All hoc nhn t hp phm nng Ctrl F10. Nu khng c li thng bo BUILD SUCCEEDED s xut hin.

Hnh 3.22 : Bin dch thnh cng 3.6 Kt ni vi board Sau khi bin dch thnh cng, bn kt ni my tnh vi board np v chy th chng trnh. Vi mch BKIT PIC bn cm dy USB vo chn mch np, bt cng tt ngun v gt tt c cc switch ca SW2 ln ON kt ni mch np PICKit2.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.23 : Kt ni vi PICKit2 trn BKIT PIC Gt tt c cc switch ca SW1 ln ON enable nt Reset, Led PortB v chn thch anh ngoi.

Hnh 3.24 : Enable Reset, Led v XTAL ngoi 3.7 Cu hnh mch np T menu Programmer chn Select Programmer v chn mch np tng ng l PICKit2. Mun chn mch np khc hoc kt ni vi mch np li bn phi chn li None ri sau mi chn li mch np.

Hnh 3.25 : Chn mch np thun tin cho qu trnh lp trnh, ta nn thit lp thm 1 s thng s cho mch np c th t ng np v chy chng trnh khi bin dch khng c li. lm c iu ny ta s chn Programmer v chn Settings.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hnh 3.26 : Setting cho mch np Giao din sau hin ra v bn check chn Program after successful build (Np chng trnh khi bin dch thnh cng) v Run after a successful program (Chy chng trnh khi np thnh cng). Nhn OK kt thc.

Hnh 3.27 : Cu hnh np v chy chng trnh By gi bn nhn li t hp phm Ctrl F10 (Build All), MPLAB s lm 1 lot cc thao tc nu khng c li : Dch chng trnh Np chng trnh Ko chn VDD ln mc cao th chn Reset v chng trnh bt u chy trn board.

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Hnh 3.28 : Dch - Np - Chy chng trnh Hnh nh chng trnh chy trn board BKIT PIC nh sau :

Hnh 3.29 : Chng trnh chy trn BKIT PIC

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Bi 4 : Kho st cc ch dao ng 1.1 Gii thiu Dng PIC18F c 10 ch dao ng khc nhau, k hiu v tn gi ca chng nh sau: 1. 2. 3. 4. LP : Low Power Crystal , thch anh c tn s dao ng thp (khong vi chc kHz). XT : Crystal/ Resonator, thch anh/resonator c tn s trung bnh (di 4MHz). HS : High Speed Crystal/Resonator, thch anh/resonator c tn s cao (trn 4Mhz). HSPLL : High Speed Crystal/Resonator with Phase Locked Loop enabled, thch anh tn s cao vi b khuyt i PLL. 5. RC : External Resistor/Capacitor with Fosc/4 output on RA6, dao ng RC ngoi,output vi tn s chia 4 chn RA6. 6. RCIO : External Resistor/Capacitor with I/O on RA6, chn RA6 l I/O. 7. INTIO1 : Internal Oscillator with Fosc/4 output on RA6 and I/O on RA7, dao ng ni, output chn RA6, input/output chn RA7 vi tn s Fosc/4 . 8. INTIO2 : Internal Oscillator with I/O on RA6 and RA7, dao ng ni vi RA6, RA7 l I/O. 9. EC : External Clock with Fosc/4 output, clock ngoi, RA6 l output tn s Fosc/4. 10. ECIO : External Clock with I/O on RA6, clock ngoi, RA6 l chn I/O. 1.2 Crystal v Resonator y l loi dao ng n gin nht. Resonator cn c tn gi khc l Ceramic Resonator. Hnh nh ca Crystal v Resonator nh hnh bn di. Cc loi dao ng LP, XT, HS, HSPLL s dng Crystal hoc Resonator.

ch hot ng ny, Crystal/Resonator s c kt ni vi 2 chn OSC1 v OSC2 ca vi iu khin nh hnh di y. Khi dng Crystal, gi tr ca t in ph thuc vo tn s ca Crystal nh bng di y

Bng 2 1 : Gi tr Capacitor cho Crystal Gi tr ca t in cng cao th dao ng cng n nh, nhng b li thi giai khi ng s lu hn. Khi dng Resonator, gi tr ca t in nh sau:

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Bng 2 2 : Gi tr Capacitor cho Resonator Khi tn s resonator ln hn 3.5 MHz ta nn cu hnh l HS thay v XT. 1.3 External Clock Ngun dao ng clock ngoi c ni vo chn OSC1. c im ca loi dao ng ny l vi iu khin hot ng ngay khi c ngun cp (hoc thc dy t ch sleep) m khng cn tn thi gian khi ng (start-up time). i vi chip PIC18F th dao ng ny c 2 loi : EC : chn RA6 output vi tn s Fosc/4 (Fosc l tn s clock a vo chn OSC1). Chn output ny c th dng kim tra hoc lm chn clock cho 1 s ng dng (nh 1 tn hiu ng b). Trong ca s Configuration Bits, tn gi ca ch ny l EC-CLKOUT on RA6.

ECIO : chn RA6 truy xut nh 1 I/O bnh thng. Trong ca s Configuration Bits, tn gi ca ch ny l EC-Port on RA6.

1.4 Dao ng RC i vi 1 vi ng dng khng i hi chnh xc v nh thi cao th dao ng RC l 1 la chn tit kim. Do tn s dao ng ti chn OSC1 ph thuc vo in p cp, in tr, t in, nhit v thm ch l hng sn xut chip, nn tn s dao ng RC khng c chnh xc. Ch ny cng c 2 loi l RC (RC-CLKOUT on RA6, Port on RA7) : Clock out vi tn s chia 4 chn RA6 v RCIO (RC-Port on RA6, Port on RA7) : RA6, RA7 s dng nh I/O. 1.5 B khuch i tn s PLL PLL l 1 mch tch hp bn trong chip, c tc dng nng tn s input ln nhiu ln, nng cao tc thc thi chng trnh ca vi iu khin. B PLL c th c dng kt hp vi nhiu ch hot ng thch anh ca vi iu khin PIC. HSPLL : PLL khi dng vi ch HS c th nhn gp 4 ln tn s input. Khi tn s input ti a l 10Mhz, tn s khuch i t 40MHz. Trong ca s Configuration Bits tn

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

gi ca ch ny l HS-PLL enabled freq = 4xFosc1. Trong ch ny bit PLLEN khng c tc dng. PLL v INTOSC : PLL cng c th c dng kt hp vi b dao ng ni, khi tn s khuch i c th t 32Mhz. Ch ny phi c thit lp bng phn mm, khng c option chn la trong ca s Configuration Bits. PLLEN bit dng kch hot ch ny.

1.6 B dao ng ni Gn tng t vi b dao ng External Clock, b dao ng ni (Internal Oscillator Block) cng c 2 ch , output tn s Fosc/4 chn RA6 v ch I/O chn ny. Tn s ca b dao ng ni c lp trnh software. Cc thanh ghi nh hng n tn s ny l OSCCON v OSCTUNE. b dao ng ni c 2 ngun clock, ngun clock 8MHz v ngun clock RC 31kHz. B ngun clock 8MHz s i qua 1 b chia (Prescaller) v cp clock cho thit b hot ng. Gi tr ca b chia ny c xc nh bi 3 bit IRCF2:IRCF0 trong thanh ghi OSCCON. Khi gi tr cc bit u l 0 th vic chn clock source da vo bit INTRC trong thanh ghi OSCTUN. Nu INTRC = 0 th tn s ly t clock source th 2, 31kHz. Ngc li tn s s l 8MHz/256 = 31.5kHz (b chia l 256 cho clock 8MHz). Khi tn s ca b dao ng ni l 4MHz hoc 8MHz (OSCCON<6:4> = 110 hoc 111) th n c th c s dng kt hp vi b PLL. kch hot b PLL ta phi set bit PLLEN thanh ghi OSCTUNE ln 1. 1.7 Demo Kit BKIT PIC c thit k dng switch gt kt ni vi thch anh (crystal) 20MHz, nn ta c th s dng ch thch anh ngoi khng PLL (PLL ch dng c vi thch anh nh hn 10MHz) hoc dng thch anh ni kt hp vi PLL. demo tn s cung cp cho chip, ta s vit chng trnh c 1s tng gi tr ca PORTB ln 1 n v. Mt cu lnh trong PIC chim 4 chu k dao ng. 1.7.1 Thch anh ngoi 20MHz Ta s dng 2 vng lp for to hiu ng delay. Vi chu k 20MHz ta phi m 5 000 000 chu k lnh (do 1 chu k lnh chim 4 chu k dao ng). Khi mun tnh ton chnh xc thi gian, ta phi dng cc cu lnh ASM. Khi vit bng ngn ng C, ta ch c th c lng gn ng. Cu lnh (for i=0 ; I < MAX_I ; i++) tn khong 4 chu k lnh : i++ tn 2 chu k lnh, i< MAX_I tn 2 chu k lnh, lnh gn i =0 ch thc hin 1 ln nn ta c th b qua. Vy hm to hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau: Code: void delay1s_20MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } } }

Nh cp trn, 1 vng for thc hin khong 4 chu k lnh nn tng s chu k lnh ca 2 vng for trn l (250 * 4) * (1250 *4) = 5 000 000.

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Hm main ta c th vit nh sau: Code: void main() { TRISB = 0x00; //setup PORTB is output PORTB = 0x00; //init value while(1) { PORTB++; //increase PORTB Delay1s_20MHz(); //call delay 1s } } Chnh ch thch anh trong ca s Configuration Bits l HS, PORTB l Digital (mc nh l analog), Disable chc nng np in p thp (LVP), dch v np chng trnh ta s thy gi tr PORTB tng dn sau 1s. Chnh ch thch anh sang ch LP hoc XT, dch v np li chng trnh bn s thy chng trnh khng chy hoc chy sai. Do vi thch anh 20MHz ta phi chn l HS nh datasheet ca PIC18F4520. 1.7.2 Thch anh ni 8MHz Cng tng t nh trn, ch thch anh ni 8MHz ta phi thc hin 2 000 000 chu k lnh. Hm to hiu ng tr hon 1s vi tn s 20MHz ta s vit nh sau: Code: void delay1s_8MHz() { int i,j; for(i=0;i<250;i++) { for(j=0;j<1250;j++) { } } } s dng c thch anh ni 8MHz, trc tin ta phi cu hnh l dng thch anh ni trong ca s Configuration Bits (chn INT RC Port on RA6, Port on RA7), sau vit code trong hm main la chn b Prescaller cho ngun clock 8MHz. Ta s set 3 bit <6:4> ca thanh ghi OSCCON ln 1. Hm main s vit nh sau: Code: void main() { TRISB = 0x00; //setup PORTB is output PORTB = 0x00; //init value OSCCON |= 0x70 //set bit <6:4> -> freq = 8MHz while(1) { PORTB++; //increase PORTB Delay1s_8MHz(); //call delay 1s } }

1.7.3 Thch anh ni 8MHz v PLL Khi s dng thch anh ni 8MHz v b PLL nhn 4, tn s dao ng cp cho chip s l 32MHz, vy ta phi m 8 000 000 chu k lnh. Hm to hiu ng delay s nh sau: Code:

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

void delay1s_8MHzPLL() { int i,j; for(i=0;i<500;i++) { for(j=0;j<1000;j++) { } } } Hm main ngoi vic chn Prescaller cho clock ni ta phi set thm bit PLLEN (bit 6) trong thanh ghi OSCTUNE: Code: void main() { TRISB = 0x00; //setup PORTB is output PORTB = 0x00; //init value OSCCON |= 0x70 //set bit <6:4> -> freq = 8MHz OSCTUNE |= 0x40 //enable PLL while(1) { PORTB++; //increase PORTB Delay1s_8MHzPLL(); //call delay 1s } }

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Lp trnh VK PIC vi MPLAB C18 HBK TP HCM - BKIT4U 4RUM EDITTER : TRI - IUH

Bi 5 : Interrupt v ngt Timer 2.1 Interrupt trong PIC Dng PIC18F4520 (2420, 2520, 4420) c nhiu ngun ngt (interrupt source) v 2 mc u tin ngt (high priority interrupt v low priority interrupt). Vector ngt c mc u tin cao c a ch 0x08 cn ngt c mc u tin thp c a ch 0x18. Khi hm phc v ngt qung cho ngt u tin thp ang xy ra, ngt u tin cao xy ra s tm dng ngt u tin thp v phc v cho ngt u tin cao. i vi 1 ngt, thng thng c 3 bit iu khin n: Flag bit : C bo hiu interrupt, khi flag bit c set, ngt s xy ra. Enable bit : Cho php ngt i vi cc ngt c mt n (maskabled interrupt) Priority bit : Thit lp u tin ngt, khi c set ngt s c mc u tin cao.

c th thit lp mc u tin cho cc ngun ngt, ta phi enable chc nng u tin ngt bng cch set IPEN bit (Interrupt Priority Enable bit : RCON<7>). Khi IPEN = 1 : GIEH bit (INTCON<7>) s enable cc ngt c mc u tin cao, GIEL bit (INTCON<6>) s enable cc ngt c mc u tin thp. Khi ngt ton cc, Flag bit, Enable bit c set, ngt s c kch hot, con tr chng trnh s nhy ti a ch 0x08 hoc 0x18 ty theo ngt c thip lp l u tin cao (Priority bit l 1) hay u tin thp (Priority bit l 0). Khi IPEN = 0 : y l trng hp mc nh, disable chc nng u tin ngt (gi l ch compatibility mode). INTCON<6> lc ny l PEIE bit, enable hay disable cc ngt ngoi vi (peripheral interrupt). INTCON<7> lc ny l GIE bit, enable hay disable tt c cc ngun ngt. ch compatibility ny, tt c cc ngt s nhy n a ch 0x08. Khi cc ngun ngt c cng u tin, chng s cng nhy n 1 a ch ngt. Hm phc v ngt qung cn phi kim tra tt c cc c xc nh ngun ngt no ang gy ra ngt. C ngt cn c xa trnh hin tng ngt quy (recursive interrupt), vi iu khin s lp v tn trong hm ngt cho n khi trn stack. im ch quan trng trong thanh ghi INTCON l khi IPEN = 1 : INTCON<7> = 1 s enable tt c cc ngt c u tin cao nhng khi INTCON<7> = 0 n li disable tt c cc ngt, bao gm c ngt u tin thp. Mt ngt u tin thp ngoi vic thit lp GIEL (INTCON<6>) cn phi set lun c bit GIEH (INTCON<7>). 2.2 Gii thiu Timer0 Timer0 c 2 ch 16 bit hoc 8 bit. Clock cp cho timer 0 c th l clock ni hoc clock ngoi (ly t chn T0CKI). Ngoi ra Timer0 cn c b Prescaller chia tn s clock.

Hnh 2.1 : Thanh ghi iu khin T0CON Timer0 c iu khin bi thanh ghi T0CON. ngha cc bit trong thanh ghi ny nh sau: Bit 7 TMR0ON : Bt tt Timer 0. 1 : Bt Timer 0 . 0 : Tt Timer 0. Bit 6 T08BIT : Chn cu hnh cho Timer 0. 1 : Timer 16 bit. 0 : Timer 8 bit. Khi hot ng ch 16 bit, gi tr ca b nh thi (counter)/ b m Timer 0 c ghi vo 2 thanh ghi TMR0H v TMR0L. Ngc li, ch 8 bit, gi tr m c lu trong thanh ghi TMR0L. Bit 5 T0CS : Chn ngun clock cho Timer 0. 1 : Clock ngoi t chn T0CKI.

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0 : Clock ni (Fosc/4). Bit 4 T0SE : Chn ch kch Timer 0 khi dng ngun ngoi. 1 : Timer 0 m ln khi c tn hiu t High sang Low chn T0CKI. 0 : Timer 0 m ln khi c tn hiu t Low sang High chn T0CKI. Bit 3 PSA : Bt/ Tt ch Prescaller cho Timer 0. 1 : Tt Prescaller. 0 : Cho php Prescaller. Bit 2 : 0 T0PS2 :T0PS0 : Chn gi tr Prescaller. 111 : 1:256 011 : 1:16 110 : 1:128 010 : 1:8 101 : 1:64 001 : 1:4 100 : 1:32 000 : 1:2 Khi chn b Prescaller, tn s ca Timer 0 s b chia xung. V d thch anh dng cho mch l 20MHz, th tn s ca clock ni l Fosc/4 = 5MHz. Nu ta chn Prescaller l 1:2 th tn s m ca timer 0 l 2.5MHz. Khi Timer 0 m trn t FF :FF (ch 16 bit) hoc FF (ch 8 bit) ln 0, c TMR0IF s c bt ln 1 v gy ra ngt nu cc bit cho php ngt (ngt ton cc, ngt timer0) c set ln 1. 2.3 Lp trnh module Timer0 2.3.1 Hm init_timer0 Trong phn ny, chng ta s khi to timer0 ch 16 bit, s dng clock ni v prescaller 1:2, ngt timer0 s c cu hnh l ngt u tin thp v sau mi 1ms s xy ra ngt 1 ln. Timer0 s m ln sau mi ln tch cc ca clock. Trong ch 16 bit, khi gi tr trong 2 thanh ghi TMR0H:TMR0L chuyn t FFFF sang 0000 s xy ra ngt, c TMR0IF s c bt ln 1. Mch BKIT PIC s dng thch anh 20MHz, nn clock ni cho timer0 s l 5MHz (timer0 s m 5 000 000 n v trong 1 giy). c c ngt 1ms ta s np cho thanh ghi TMR0H:TMR0L gi tr thp hn FFFF 5000 n v. V Timer0 c cu hnh s dng prescaller 1:2, nn con s ny s thp hn FFFF 2500 n v : 65535 2500 = 63035 = F63B. Vic np gi tr ny cho thanh ghi TMR0 s c thc hin trong hm phc v ngt qung timer0_isr. enable ngt timer 0, ta cn set bit ngt ton cc GIE, set bit ngt thp GIEL, set bit enable timer 0 TMR0IE v c ngt timer 0 TMR0IF trong thanh ghi INTCON. Cu hnh u tin ngt timer 0 l ngt thp bng cch clear bit TMR0IP trong thanh ghi INTCON2. Hm ngt timer0 s c khi to nh sau: Code: void init_timer0() { counter0 = 0;//counter for virtual timer timer0_flag = 0;//flag for virtual timer T0CON = 0x00;//timer0 16bit clock, Prescaller 1:2 RCONbits.IPEN = 1;//enable interrupt priority INTCON2bits.TMR0IP = 0;//low interrupt priority INTCONbits.GIE = 1;//enable global interrupt INTCONbits.GIEL =1;//enable low priority interrupt INTCONbits.TMR0IE = 1;//enable timer0 interrupt INTCONbits.TMR0IF = 1;//force timer0 interrupt } 2.3.2 Hm timer0_isr Hm ny c gi khi ngt Timer0 xy ra. i vi tt c cc ngt ca PIC, ta cn phi xa c ngt trc tin v n khng c t ng xa bng phn cng. Trong hm phc v ngt qung Timer0 ny ta nn tt n i bng cch xa bit TMR0ON, np li gi tr cho 2 thanh ghi m

mode,

internal

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Timer0. cui hm phc v ngt qung ta s bt cho Timer0 m ln (set bit TMR0ON). Gi tr trong 2 thanh ghi m Timer0 s tng dn theo mi xung nhp ca clock, v khi t gi tr FFFF n s xy ra ngt ln tip theo. Code: void timer0_isr() { INTCONbits.TMR0IF = 0; //clear interrupt flag T0CONbits.TMR0ON = 0; //stop timer 0 TMR0H = 0xF6; TMR0L = 0x3B; //CODE HERE virtual_timer(); //END CODE T0CONbits.TMR0ON = 1; //reconfig timer 0 //1ms interrupt

//start timer 0 } gi c hm ny, ta phi dng thm ch th pragma dch 1 hm ti a ch nht nh v ch th pragma interrupt dch hm ny l dng hm interrupt. Timer0 c cu hnh l ngt u tin mc thp (low priority interrupt), nn khi ngt xy ra, con tr chng trnh s nhy ti a ch 0x18. Chng trnh hin thc lnh gi hm timer0_isr c hin thc cui file main.c Code: #pragma code #pragma interrupt low_interrupt_isr void low_interrupt_isr() { if(INTCONbits.TMR0IF == 1) timer0_isr(); } #pragma code _vector_low = 0x18 void _vector_low(void) { low_interrupt_isr(); } #pragma code void main() { while(1) { } } Vi ch th u tin, hm vecter_low s c dch ti a ch 0x18, l a ch vector ngt thp. Do 2 a ch ngt ca PIC l 0x08 cho ngt cao v 0x18 cho ngt thp cch gn nhau, nn ta s ch t tht t lnh ti 2 a ch ny. Trn y ch t 1 lnh gi hm low_interrupt_isr ti a ch 0x18. Trong hm ny ta s kim tra ngt ang xy ra c phi l Timer0 hay khng bng cch xt bit th 2 ca thanh ghi INTCON (bit TMR0IF) trc khi gi hm timer0_isr. Hm main() by gi phi thm ch th #pragma code compiler dch hm ny 1 vng nh khc trong vng code memory. Ngoi Timer0, PIC cn c thm 3 Timer na. V cc chc nng c bn nh Timer0, chng cn c thm 1 vi chc nng c bit khc. 2.4 Gii thiu Timer 1 Khc vi Timer0 l 1 interrupt, Timer1 l 1 Peripheral Interrupt. V vy c th enable cho ngt Timer1, ta phi set bit PEIE.

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Tng t vi Timer0, Timer1 cng c chc nng counter t clock ngoi ( chn T13CKI) v tng gi tr ln 1 mi khi c clock cnh ln chn T13CKI. Khi chn clock ngoi, T1SYNC bit dng chn ch cho counter, l Ansynchronous Counter hoc Synchronous Counter. Hai loi counter ny u tng gi tr m ln 1 sau mi ln tch cc ca clock, im khc bit ca chng nm kt ni phn cng. Synchronous Counter cp clock cho tt c cc flip flop trong khi Ansynchronous Counter ch cp clock cho flip flop u tin.

Hnh 2.2: Synchronous Counter

Hnh 2.3 : Ansynchronous Counter Bn cnh , Timer1 cn c th m ln nh dao ng ngoi 2 chn T1OSI v T1OSO. Ngi ta thng dng thch anh 32,768kHz v bin Timer1 thnh 1 b Real Time Clock (ng h thi gian thc) . S kt ni nh sau:

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Hnh 2.4 : Timer1 Osillator s dng c chc nng ny ta cn phi set bit T1OSCEN. Chc nng c bit cui, Timer1 l ngn clock cho module CCP. Chi tit v module ny s c trnh by Bi 16. Hai timer cn li thng c dng tch hp vi cc module khc, Timer2 (c thm b Post Scaller) s c dng cho module PWM Bi 14 v Timer3 s c dng cho module Capture Bi 16. 2.5. Ngt Timer1 v Timer2 Timer 1: Khi khng c interrupt priority : GIE enable all interrupts, PEIE/GIEL enable all peripheral interrupt. Khi c interrupt priority : GIE enable all high interrupt, nhng nu bng 0 s disable all interrupts. Nn nu set timer 1 l interrupt mc thp th phi set GIEH ln enable, sau set tip GIEL enable interrupt u tin thp. Nu timer1 mc cao th phi set GIEH enable high interrupt v set PEIE v timer1 l peripheral interrupt. Timer 2: Timer 8 bit, gi tr trong thanh ghi TMR2 khi bng vi PR2 s set c TMR2IF v gy ra ngt. Prescaller l b chia tn s input. (1,4,16) PostScaller l b chia tn s output. (1-16) Timer 2 l peripheral interrupt. Code:

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void init_timer2() { T2CON = 0x00; //postscaller 1 T2CONbits.T2OUTPS0 = 1; T2CONbits.T2OUTPS1 = 0; T2CONbits.T2OUTPS2 = 0; T2CONbits.T2OUTPS3 = 0; //prescaller 4 T2CONbits.T2CKPS0 = 1; T2CONbits.T2CKPS1 = 0; } void init_timer2_interrupt() { //enable timer 2 interrupt PIE1bits.TMR2IE = 1; //enable interrupt priority RCONbits.IPEN = 1; //enable timer1 low priority interrupt IPR1bits.TMR2IP = 0; INTCONbits.GIEH = 1; INTCONbits.GIEL = 1; //force into interrupt TMR2 = 0x00; PR2 = 200; PIR1bits.TMR2IF = 1; } #pragma code vector_high = 0x08 void _vector_high(void) { _asm goto timer1_isr_high _endasm } #pragma code vector_low = 0x18 void _vector_low(void) { _asm btfsc PIR1, 0, 0 goto timer1_isr_low btfsc PIR1, 1, 0 goto timer2_isr_low _endasm } #pragma interrupt timer2_isr_low void timer2_isr_low() { static int counter = 0; counter++; PIR1bits.TMR2IF = 0; if(counter == 6250) { PORTB++; counter = 0; } }

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Bi 6 : Ma trn phm 3.1 Khi nim Ma trn phm l cch kt ni cc phm theo hng v ct. Cch kt ni nh vy s tit kim c ti nguyn ca vi iu khin. V d di y l cch mc ma trn phm 4x4 :

Hnh 3.1 : Ma trn phm 4x4 Ta c 16 phm v 8 tn hiu iu khin. Nu mc 16 phm ny nh cc phm n, ta phi cn n 16 tn hiu iu khin. 3.2 Gii m ma trn phm Ta xt 1 ma trn phm 2x2 nh hnh di y:

Hnh 3.2 : Ma trn 2x2 Khi phm A c nhn th in p ti C1 s bng R1. Nh vy nu ban u ti C1 v C2 l mc cao, R1 l mc thp v R2 l mc cao, th khi phm A c nhn, in p ti C1 (ban u l mc cao) s b ko xung mc thp.

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Hnh 3.3 : Phm A c nhn Tng t nu phm B c nhn th C2 s b ko xung mc thp. xc nh 2 phm C v D c c nhn hay khng, ta s nng in p ti R1 ln mc cao, ko in p ti R2 ln mc cao (chuyn hng tch cc).

Hnh 3.4 : Phm D c nhn Nh vy, xc nh v tr ca phm no c nhn, ta s duyt qua tt c cc hng v xt cc phm hng . Quy c tn hin DEACTIVE l mc 1 v tn hin ACTIVE l mc 0, tng bc gii m ma trn phm nh sau: Cho tn hiu cc ct l DEACTIVE Ci t tn hin ti cc ct l INPUT Cho tn hin cc hng l DEACTIVE Ci t tn hiu cc hng l OUTPUT Lp qua cc hng o Cho tn hiu hng ang xt l ACTIVE. o Xt cc ct trong hng ang cho ACTIVE, ct no c tn hiu ACTIVE l phm tng ng c nhn. Kt thc vng lp

3.3 Vit chng trnh

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Chng trnh dnh cho gii m ma trn gm 2 phn : phn u dng khi to cc chn vi iu khin, phn 2 l duyt qua cc hng v ct xc nh phm no c nhn. File key_matrix.h nh ngha cc hng s v 2 hm dng trong ma trn phm: Code: #define TRIS_BUTTON TRISC #define PORT_BUTTON PORTC #define MAX_COL 4 #define MAX_ROW 4 extern char key_data[]; extern char key_code[]; void init_key_matrix(); void scan_key_matrix(); key_code l 1 mng 16 phn t tng ng vi 16 phm, nu phm c nhn th phn t tng ng c gi tr l 1. key_data cng l 1 mng 16 phn t, ta c th dng lu thng tin cho phm v tr th nht, chng hn nh data hin th s 0 (0x3F) trn led 7 on. 3.3.1 Khi to ma trn phm Theo nh s kt ni ma trn phm hnh 4.1, ta s khi to cc hng l output v cc ct l input. Quy nh DEACTIVE l mc 1 nn ta s gn gi tr ban u ca PORTC l 0xFF. Code: void init_key_matrix() { TRIS_BUTTON = 0x0F; //C3-C0:input C7-C4:output PORT_BUTTON = 0xFF; } 3.3.2 Qut ma trn phm Nh cp gii thut trn, ta s ln lt duyt qua tt c cc hng bng cch xut tn hiu ca hng l ACTIVE (mc 0) ri xt tng ct. Code: void scan_key_matrix() { int i,j; //loop all rows for(i=0;i<MAX_ROW;i++) { //pull down row i PORT_BUTTON &= ~(1<<(7-i)); //loop all cols for(j=0;j<MAX_COL;j++){ //reset key code key_code[i*MAX_ROW+j] = 0; //when col j is activated if((PORT_BUTTON & (1<<j)) == 0){ //set key code key_code[i*MAX_ROW+j] = 1; } } //pull up row i PORT_BUTTON |= (1<<(7-i)); } } 3.3.3 Hm main file main.c, ta s include file key_matrix.h c th gi c cc hm ca n. Bin key_code c extern file key_matrix.h nn ta cng c th truy xut file main.c. Code:

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#include "KEY_MATRIX\\key_matrix.h" void main() { int i; TRISB = 0x00; //init PORTB for output PORTB = 0x00; //initial value init_key_matrix(); while(1) { scan_key_matrix(); for(i=0;i<16;i++) { if(key_code[i] != 0) { PORTB = i; break; } } } } Code chi tit ca ma trn phm cc bn c th tham kho Bai7.

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Bi 7 : Chng rung cho ma trn phm 4.1 Nguyn l chng rung

Hnh 4.1 : Hin tng rung phm Hnh trn minh ho mc in p ca 1 phm nhn tch cc mc 0, trng thi bnh thng, in p vi iu khin nhn vo l 5V cn khi nhn l 0V. Tuy nhin, do rung c hc ca phm, ti thi im va nhn xung, in p s khng n nh trong 1 khong thi gian, trc khi n nh mc 0V. Hiu tng ny gi l rung phm. Mc d khong thi gian in p mc 0 trong giai on rung phm l nh nhng cng vi iu khin nhn c. V vy khi ta xt nu in p l 0 th gi hm func() th hm ny s c gi rt nhiu ln, l iu m ta khng mong mun. khc phc hin tng rung phm, c 2 hng gii quyt : dng phn cng v phn mm. V gii php phn cng : thay v mc n gin nh kit th nghim ny (xem li s ), ta c th dng thm t in hn ch vic thay i in p t ngt, s nguyn l nh sau:

Hnh 4.2 : Chng rung bng phn cng

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s trn, khi khng nhn l mc 1, khi nhn l mc 0. Phm nhn trn tch cc mc 0. Mch trn cn gi l mch RC. Nu nt nhn c 2 cc (3 chn), ta c th chn gii php dng mch RS flip flop, y l mch phn cng chng rung tt nht, s nguyn l nh sau:

Hnh 4.3 : Chng rung bng phn cng (tt) V gii php phn mm : Ta s nh k c tn hiu t nt nhn, cho n khi no chng trng nhau n ln th mi x l. Hnh di y minh ho trong trng hp 2 ln l 0 th mi xc nhn l phm c nhn v mi x l tc v m ta mong mun.

Hnh 4.4 : Chng rung bng phn mm Khong thi gian gia 2 ln c l khong 10ms, ta s hin thc hm c ny v gi n trong timer. Gii thut n gin x l chng rung c th hin thc nh sau: Code: previous_key = current_key; current_key = Port_key; If(previous_key == current_key) effective_key = current_key; Trong : previous_key : bin lu gi tr phm trc . current_key : bin lu gi tr phm hin ti. Port_key : Port ca vi iu khin kt ni vi phm. y chng ta gi hm c ma trn phm tr v gi tr ca phm c nhn. effective_key : gi tr phm hp l (gi tr trong giai on n nh) tng tnh chnh xc, ta c th dng nhiu bin previous_key lu li cc gi tr v so snh nhiu ln. on code trn ch so snh trng nhau 2 ln. 4.2 Kt ni phn cng

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S nguyn l ca phm trong kit ny nh sau :

Hnh 4.5 : S kt ni nt nhn Phm nhn ny tnh cc mc 0, c kt ni kh n gin, nn ta s dng phn mm chng rung. Ta s dng 3 bin so snh 2 ln trng nhau, 2 ln lin tip cch nhau 10ms. Trong trng hp nhn 1 phm, ta s dng bin TimeOutForKeyPress xc nh thi gian tch cc tip theo. Bin ny s quan trng trong trng hp ta vit 1 ng dng chng hn nh son tho vn bn. Nu khng c bin ny qun l, nu ta th trong 1s c ti 100 ln tch cc. 4.3 Vit chng trnh Module ny c 2 hm nh sau : void initKey() : Khi ng cc thng s ban u void getKey() : Hm ny c gi trong timer0, dng qut phm. void SubKeyProcess() : Hm ny hin thc tc v bn cn thc hin khi nhn phm. kit th nghim ny, cc nt nhn c ni thnh dng ma trn v c ni vi PORTC nn ta nh ngha thm u file Key.c : Code: #define KEY_PORT PORTC 4.3.1 Hm initkey() Code: void initKey() { KeyReg0 = 0x00; KeyReg1 = 0x00; KeyReg2 = 0x00; KeyReg3 = 0x00; } Trong KeyReg0, KeyReg1, KeyReg2 dng lu 3 ln lin tip. Khi 3 bin ny bng nhau, bin KeyReg3 mi c cp nht. Bin KeyReg3 l gi tr hp l ca phm nhn. 4.3.2 Hm getKey() Hm ny c chia lm 2 phn, phn u l chng rung phm dng 2 ln so snh trng nhau. Phn th 2 x l khi 1 phm c , phi sau 1 khong thi gian TimeOutForKeyPress mi c tch cc. Code:

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void getKey(){ KeyReg2 = KeyReg1; KeyReg1 = KeyReg0; KeyReg0 = read_matrix_key();// Cho phep nut nhan nao duoc tich cuc. if ((KeyReg1 == KeyReg0) && (KeyReg1 == KeyReg2)) { TimeOutForKeyPress --; if (TimeOutForKeyPress == 0) { KeyReg3 = 0x00; } if (KeyReg2 != KeyReg3) { KeyReg3 = KeyReg2; If (FlagFirstTimeKeyPress == 1)//Day la lan dau phim duoc nhan. { TimeOutForKeyPress = 100; SubKeyProcess(); FlagFirstTimeKeyPress = 0; } else { if (KeyReg2 == 0x00) FlagFirstTimeKeyPress = 1; else { TimeOutForKeyPress = 100; SubKeyProcess(); } } } } } 4.4. Code mu Download code mu ti y

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Bi 8 : LCD 16x2 v bn phm in thoi 5.1 Chc nng cc chn ca LCD

Hnh 5.1 : LCD 16x2 LCD thng s dng 14 chn, ch 16 chn khi cn iu khin n nn. Chc nng ca cc chn nh sau:

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5.2 Kt ni mn hnh LCD

Hnh 5.2 : Kt ni mn hnh LCD Hnh trn m t kt ni LCD vi ch 16 chn, 2 chn K v A dng kt ni vi n nn. 5.3 Cc vng nh ca LCD 5.3.1 Display Data Ram (DDRAM) Lu tr m k t hin th ra mn hnh. M ny ging vi m ASCII. C tt c 80 nh DDRAM. Vng hin th tng ng vi ca s gm 16 nh hng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch ch bng cch s dng lnh dch , khi ca s hin th s dch em li hiu ng dch ch.

Hnh 5.3 : Vng nh DDRAM 5.3.2 Character Generator Ram (CGRAM) Lu tr tm mu k t do ngi dng nh ngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* mang gi tr ty nh 0 hay 1).

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Hnh 5.4 : Vng nh CGRAM 5.3.3 B nh CGROM B nh dng lu tr cc k t hin th trn LCD. Cc gi tr lu trong b nh ny nh sau:

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Hnh 5.5 : Vng nh CGROM Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin th ang bt u t v tr u tin (hng th nht hin th d liu ca nh t 0x00 n 0x0f, hng th hai hin th d liu ca nh t 0x40 n 0x4f, y l v tr home). Gi tr ca nh 0x07 l 0x43 (k t C), ca nh 0x08 l 0x45 (k t E). Chng ta mun hin th ch gi hng th hai, gi s c s hin th ang v tr home. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta phi nh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k t CGRAM th nht. Lc ny gi tr ca nh 0x47 l 0x00 hoc 0x08 (v tr ca mu k t CGRAM th nht ). 5.4 Cc lnh c bn ca LCD truyn lnh cho LCD th chn RS = 0, khi cc tn hin trn D0-D7 c xem l lnh. ngha ca cc lnh iu khin LCD nh sau:

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I/D 1 = 0 = RL 1 = 0 = S 1 = 0 = DL 1 = 0 = D 1 = 0 = N 1 = 0 = U 1 = 0 =

Increment (by 1) Decrement (by 1) Shift right Shift left Display shift on Display shift off 8-bit interface 4-bit interface Display on Display off Display in two lines Display in one line Cursor on Cursor off

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F 1 = 0 = B 1 = 0 = D/C

Character format 5x10 dots Character format 5x7 dots Cursor blink on Cursor blink off

1 = Display shift 0 = Cursor shift 5.5 Kt ni LCD vi vi iu khin LCD c 2 ch 8 bit v 4 bit. ch 8 bit, ta dng ton b 8 chn D0-D7 giao tip. ch 4 bit, ta ch dng 4 bit cao D4-D7 giao tip vi LCD. D liu gi cho LCD ch ny bao gm 4bit cao gi trc, sau s n 4bit thp. S kt ni 2 ch nh sau:

Hnh 5.6 : Kt ni LCD vi vi iu khin Nu mun tit kim chn, R/W c th ni xung GND. ch 4bit th 4 bit thp ca LCD c th ni xung GND. 5.6 Khi to LCD Qu trnh khi to LCD ch 8 bit nh sau:

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Hnh 5.7 : Khi to LCD 8 bit Qu trnh khi to ch 4 bit nh sau:

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Hnh 5.8 : Khi to LCD 4 bit 5.7 Kt ni phn cng LCD c kt ni vi Port B ca vi iu khin PIC nh sau: Trch: LED_BACKLIGHT PIN_RS PIN_RW PIN_EN D4 = : : : : PortB.0 PortB.1 PortB.2 PortB.3 PortB.4

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D5 D6 D7 : PortB.7

: :

PortB.5 PortB.6

5.8 Vit chng trnh & 5.9 Cc hm c bn qu trnh iu khin LCD hiu qu, ta nh ngha 1 s hm c bn nh sau: Hm delay: trung bnh PIC thc hin 5 lnh mt 1us vi thch anh 20Mhz. Code: void lcd_delay(int time) { while(--time); } Hm ghi d liu ra LCD: Code: //Ghi 4 bit void lcd_write_4bits(unsigned char dat) { RW(WRITE); //ko chn RW xung 0 EN(SET); //set chn Enable ln 1 LCD_DATA_OUT(dat & 0xF0); //Gi data ra lcd_delay(10); EN(CLR); //ko chn Enable xung 0 lcd_delay(10); } //Ghi 1 byte : ghi 4 bit 2 ln void lcd_write_cmd(unsigned char cmd){ lcd_wait_busy(); RS(CMD); lcd_write_4bits(cmd); lcd_write_4bits(cmd << 4); } Mt s macro trong file lcd.h, v d nh: Code: #define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) ) //Nu x = 1 th thc hin lnh LCD_PORT |=0x02, x=0 th thc hin LCD_PORT &=0xFD . 5.10 Khi to LCD ch 4 bit Code:

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void init_lcd() { lcd_delay(15000); RS(CMD); lcd_write_4bits(0x03 lcd_delay(4100); lcd_write_4bits(0x03 lcd_delay(100); lcd_write_4bits(0x03 lcd_write_4bits(0x02 lcd_write_cmd(0x28) lcd_write_cmd(0x0C); lcd_write_cmd(0x06); } ngha cc lnh trn nh sau:

<< 4); << 4); << 4); << 4); ;

//1 //2 //3 //4 //5 //6 //7 //8 //9 //10 //11

Lnh 1 : gi hm lcd_delay(15000) delay 15ms. Lnh 2 : ko chn RS (ni vi LCD_PORT ti bit 1) xung 0. Lnh ny c nh ngha l 1 macro trong file lcd.h: #define RS(x) ( (x) ? ( LCD_PORT |= 0x02 ) : ( LCD_PORT &= 0xFD ) )

CMD c define l 0 nn lnh RS(CMD) s c iu kin (x) l false v s thc hin phn th 2 ca lnh trn : LCD_PORT & 0xFD (ko bit 1 xung 0 : 1111 1101). Lnh 3 : thc hin trng thi u tin sau khi ch 15ms, ghi D7 D6 D5 D4 = 0011. Cc chn ny c ni vi 4 bit cao ca vi iu khin nn ta phi dch tri gi tr 0x03 4 bit. Lnh 4 : delay khong 41ms. Lnh 5,6,7,8 : Thc hin cc trng thi 2,3 v 4. Sau lnh 7 th LCD chuyn sang ch 4 bit, v gi 1 byte, ta s gi 2 ln 4 bit cao trc ri ti 4 bit thp. Lnh 9 : gi hm lcd_write_cmd ghi 4 bit 2 ln, gi tr 0x28 tng ng vi N = 1 (hin th trn 2 hng ca LCD) v B = 0 (font nh dng 5x7 im). Lnh 10 : thc hin lnh display on (xem thm trong bng lnh), D = 1. Lnh 11 : thc hin lnh entry set mode, 0x06 tng ng vi ch dch phi tng dn.

5.11 Xo mn hnh Hm ny ch n gin l gi lnh clear mn hnh lcd (xem thm trong bng lnh ca LCD). Code: void lcd_clear() { lcd_write_cmd(0x01); lcd_goto_xy(0, 0); } 5.12 Thit lp v tr con tr Hm ny thit lp v tr bt u xut d liu trn mn hnh LCD 2 hng 16 ct. hin thc hm ny ta phi tnh c a ch tng ng vi to (row,col) v dng lnh SET DDRAM ADDRESS (bit 7 ca lnh ny bng 1). Code:

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char lcd_goto_xy(unsigned char row, unsigned char col) { unsigned char addr = 0x00; if(col >= 20 || row >= 4) return FALSE; if(row < 2) { addr = (row * 0x40) + col; addr = 0x80 | (addr & 0x7F); } else { addr = (row * 0x40) + col; addr = 0x94 | (addr & 0x7F); } lcd_write_cmd(addr); current_row = row; current_col = col; return TRUE; } 5.13 In k t ra mn hnh Hm ny nhn thng s l 1 k t v hin th k t ra mn hnh LCD. Vic hin thc hm ny kh n gin, ta ch cn ko chn RS xung 0 l LCD s hiu cc bit D7-D4 l d liu. Code: void lcd_print_char(unsigned char dat) { lcd_wait_busy(); //find next position if(current_row == 0 && current_col == 16) lcd_goto_xy(1,0); if(current_row == 1 && current_col ==16) lcd_goto_xy(0,0); RS(DAT); //RS = 0 lcd_write_4bits(dat); lcd_write_4bits(dat << 4); current_col ++; //update new position } T nhng hm c bn ny, bn c th hin thc thm cc hm xut 1 string hay 1 gi tr s ra mn hnh LCD. Code chi tit c th xem thm file nh km. 5.14 Thit lp bn phm in thoi Tm tt : bn phm 4x4 c nh cc k t s (0-9) v ch (A,B,C,D,*,#) s l cc phm chc nng m phng theo bn phm in thoi. Cc trng thi cng nh thng tin s c hin th trn mn hnh LCD. lm c bi ny cc bn cn c nhng hm v qut ma trn phm (trong th mc button_matrix) cng nh xut ra LCD (trong th mc lcd). Trc ht bn cn phi bit qua bi qut ma trn phm. Trong Button.c chng ta c hm button_process(void); Hm ny c gi nh k trong timer kim tra xem c nt no c nhn khng.Hm read_matrix_key(void) khi khng c nt no c nhn, n s tr v gi tr 0. Khi c nt nhn n s tr v gi tr t 1-16 ty theo v tr ca nt nhn. Vic kim tra ny c thc hin nhiu ln v chng ta s ch x l n khi c t nht 3 ln c gi tr ging nhau (theo nguyn l chng rung, c thm bi chng rung cho phm). Bi th 2 cn bit l bi v xut lcd. Trong lcd.c h tr cho bn sn cc hm ghi ln lcd (Tham kho thm trong lcd.h). Chng ta bt u bng vic to mt project mi vi nhng thit lp ph hp. copy th mc button_matrix, lcd, timer, interrupt vo ni cha chng trnh hon chnh project mi. Thm nhng file .h trong cc th mc ny vo main.c. To th mc Phone v cha cc file phone.c, phone.h . add vo project. Cc s kin v trng thi ca chic in thoi ca chng ta s c x l chnh trong file phone.c ny. Include file .h ca button_matrix v lcd.

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nh hnh: trc ht chng ta nh hnh li v tr v chc nng ca tng nt. V thc hin c chc nng nhn tin cng nh gi in nn mi nt t 0-9 c thm cc chc nng ring. Ta khai bo mt mng lu gi nhng gi tr m ta mun nt nhn c th thc hin. Code: unsigned char key[16][5] = { '0',' ',0,0,0, '1','.',',',0,0, '2','a','b','c',0, '3','d','e','f',0, '4','g','h','i',0, '5','j','k','l',0, '6','m','n','o',0, '7','p','q','r','s', '8','t','u','v',0, '9','w','x','y','z', '*',0,0,0,0, '#',0,0,0,0, 'A',0,0,0,0, 'B',0,0,0,0, 'C',0,0,0,0, 'D',0,0,0,0}; y c cc nt c nhiu k t (7-p-q-r-s) cng c nt c t k t (1-.) nn thun tin ta to thm mt mng cha gi tr l s k t c s dng ca nt : Code: unsigned char limit_key[16]={2,3,4,4,4,4,4,5,4,5,1,1,1,1,1,1}; By gi coi li trong button.c c hm qut ma trn phm. Tuy nhin, gi tr tr v ca hm ny l v tr ca cc nt trn bn phm (vd:1=1,2=2,3=3,A=4). Ta s cn phi chuyn i sang mt h khc thun tin trong vic lp trnh thng qua mt mng sau: Code: unsigned char convert_key[16]={1,2,3,12,4,5,6,13,7,8,9,14,10,0,11,15}; Chng trnh chnh ca chng ta l hm Phone() c gi lin tc trong hm main(). Hm ny u tin s xt bin ActiveKey xem c nt nhn no c nhn khng . Khi c nt nhn th s c mt chuyn i nh Code: KeyPress = convert_key[ActiveKey-1]; V bin KeyPress ny chnh l gi tr chng ta x l chnh. Bin PhoneStatus cha gi tr ca ca cc trng thi ca in thoi. Cc trng thi chnh l i (WAIT_STATUS), gi in (ENTERING_NUMBER_STATUS, CALLING_STATUS,ENDCALL_STATUS), nhn tin (MESS_STATUS, TYPING_MESS_STATUS, SENDING_STATUS, ENDSEND_STATUS). Vi mi trng thi ta x l nt C l quay li, D l xa k t, A l enter ty theo quy nh mi ngi. Tip theo chng ta x l nt nhn ti mi trng thi. Ti trng thi i, nu nhp vo l s th s ch hin s key[KeyPress][0]. Cn nu trong ch nhn tin th nu nh phm c nhn lp li trong khong thi gian timeout th coi nh s chuyn k t ngay ti nt : Code: KeyMessIndex = (KeyMessIndex +1)%(limit_key[KeyPress]); lcd_putChar(key[KeyPress][KeyMessIndex]); , nu khng th in k t mi.: Code: KeyMessIndex = 1; lcd_putChar(key[KeyPress][KeyMessIndex]); Download code mu Ti y

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Bi 9 : Qut led 7 on v led ma trn 6.1 iu khin led 7 on v led ma trn. 6.1.1 Cu to Led 7 on LED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp. Mi on l mt led, kt hp tt/sng ca cc led ny hin th s m chng ta hiu c.

Hnh 6 1 Led 7 on LED 7 on c hai loi l Common Anode v Common Cathode, tng ng cc LED ni chung Anode hay ni chung Cathode. Mch th nghim BKIT PIC s dng loi Common Anode.

Hnh 6.1 : S nguyn l led 7 on 6.1.2 Cu to led ma trn LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct.

Hnh 6 3. Led ma trn Mi im c hai LED tng ng vi hai mu. Cc LED trn cng mt hng ni chung Anode, cc LED cng mu trn cng mt ct ni chung Cathode.

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Hnh 6 4 S nguyn l led ma trn 6.1.3 Nguyn l qut LED hin th 1 led 7 on, ta cn 8 ng tn hiu gi d liu cho n. Nh vy, vi 8 led 7 on, theo kt ni bnh thng, ta cn tng cng 64 ng tn hiu thp sng 8 led cng lc. Vic ny rt tn ti nguyn v phn cng. khc phc, ngi ta dng k thut qut led. Cc ng d liu ca cc led s c ni vi nhau.

Hnh 6 5 Kt ni khi qut led 7 on Vi k thut qut led ny, ti 1 thi im, ch c 1 led sng. Ti thi im t1 ch c led 1 sng, ti thi im t2 = t1 + t0 ch c led 2 sng, khi t0 rt nh, mt ngi khng th nhn bit c nhp nhy gia 2 ln lun chuyn, v s c cm gic l 2 n sng cng lc. Thng th t0 ny phi nh hn 1/24 giy, tc l trong mt giy s c nhiu hn 24 ln lun chuyn gia cc led. Bng m t qu trnh qut Led 7 on:

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Tng t i vi led ma trn, ta dng 16 ng tn hiu iu khin hai mu led v 8 ng tn hiu tch cc dng (ROW). Ti mi thi im ch c mt dng led ma trn c hin th d liu.

Hnh 6 6 Nguyn l qut led ma trn 6.2 S kt ni mch

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Hnh 6-7 S kt ni led 7 on v led ma trn Mc ch ca bi ny l mi ngi lm quen vi led 7 on v led ma trn cho nn cc led 7 on v led ma trn c kt ni theo kiu song song, cc chn d liu v iu khin led c gn trc tip vi chn vi iu khin PIC, v vy chng trnh s n gin v d thc hin hn. 6.3 Xy dng chng trnh 6.3.1 tng hin thc c th hin thc gii thut qut led chng ta cn s dng ti b inh thi(timer) v ngt qung thit lp thi gian qut. V d chng ta qut 1 led vi tn s 50Hz(ngha l led sng 50 ln/giy) nh vy ta cn cu hnh cho timer l c sau 1000ms/50 = 20ms th ngt 1 ln v trong hm x l ngt ta s a d liu ra cho led. Nu s led nhiu hn th ta ch cn ly tn s chun cho mi led nhn vi s lng led. V d nu qut cng luc 8 led 7 on vi tn s mi led l 50Hz th tn s ngt ca timer l 8*50 = 400Hz. 6.3.2 Cc hm phc v qut led 2.6.3.1 Hm qut led 7 on Code: void display_led7(void) { PORTE = 0; PORTD = led7_buffer[index_led7]; PORTE = 1 << index_led7; index_led7 = (index_led7 + 1) % 3; } Theo s nguyn l PORTD l port a d liu ra led 7 on v PORTE l port chn led( y chng ta c 3 led 7 on).Trc mi ln xut led, ta cn phi tt tt c cc led trnh trng hp d liu c c a vo led c chn tip theo,hay ngc li d liu mi c a vo led trc . 2.6.3.2 Hm qut led ma trn Code:

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void display_ledmatrix(void) { PORTA = 0; PORTB = green_buffer[index_matrix]; PORTC = red_buffer[index_matrix]; PORTA = 1 << index_matrix; index_matrix = (index_matrix + 1) % 8; } Theo s nguyn l, PORTA l port la chn led, PORTB v PORTC tng ng l cc d liu xanh v ca led ma trn, cch qut vn ging vi vic qut led 7 on. i vi vic qut led ta nn to ra nhng mng buffer tin cho vic xut d liu v cp nhp chng, cng vi vic hin thc 1 s hm cp nhp buffer nh update_led7_buffer(), update_green_bugffer(), update_red_buffer() chng trnh ca chng ta tr nn thn thin, trong sng, n gin hn rt nhiu v ph hp vi vic pht trin ln thnh nhng bi kh hn nh chy ch hay cc hiu ng led river.

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Bi 10 : Giao tip ni tip SPI 7.1 Gii thiu v SPI SPI (Serial Peripheral Interface) l mt dng giao thc truyn ni tip c dng giao tip vi cc thit b ngoi vi(EEPROM,SDcard) v cc vi iu khin khc. 7.2 Ch SPI trong vi iu khin PIC Giao tip SPI c hin thc qua 4 chn ca vi iu khin: SDI( Serial Data In ): Tn hiu ni tip c a vo vi iu khin SDO( Serial Data Out): Tn hiu ni tip t vi iu khin i ra CLK(Clock): xung clock to ra bi master SS(Slave Select): tch cc mc thp, dng chn slave truyn d liu

Hnh 7-1 S khi ca SPI 7.2.1 Cc thanh ghi iu khin SPI Ch SPI c iu khin bng 4 thanh ghi sau MSSP Control Register 1 (SSPCON1) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register(SSPBUF) MSSP Shift Register(SSPSR) thanh ghi ny khng c truy xut bi ngi dng

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Hai thanh ghi SSPCON1 v SSPSTAT l hai thanh ghi iu khin, cn than ghi SSPSR l thanh ghi dng dch d liu ra/vo vi iu khin, SSPBUF l thanh ghi dng c d liu t ngoi vo hoc ghi d liu truyn ra ngoi. ch nhn, 2 thanh SSPBUF v SSPSR l 1 b buffer i, khi d liu t ngoi truyn vo c lu y trong SSPSR(8 bits) th d liu ny c truyn ti thanh ghi SSPBUF ngi dng ly ra. Cn ch truyn th khi d liu c ghi vo thanh ghi SSPBUF th cng lc d liu cng c ghi vo thanh ghi SSPSR dch ra ngoi. 2.7.2.1 Thanh ghi SSPSTAT

Bit 7: SMP Sample bit SPI Master mode 1 = d liu vo s c ly cui chu k xung clock 0 = d liu vo s c ly gia chu k cung clock SPI Slave mode SMP phi c gn bng 0 Bit 6: CKE SPI Clock Select bit Bit 0: BF BuFffer Full Status bit(dnh cho qu trnh nhn) 1 = qu trnh nhn hon thnh, SSPBUF y 0 = qu trnh nhn ang thc hin, SSPBUF trng 2.7.2.1 Thanh ghi SSPCON1

Bit 7: WCOL Write Collision Detect bit(ch dng ch truyn tn hiu) 1 = thanh ghi SSPBUF c ghi d liu trong khi d liu c truyn cha ht 0 = khng c ng Bit 6: SSPOV Receive Overflow Indicator bit(dng ch nhn tn hiu) 1 = c d liu mi nhn v ghi ln thanh ghi SSPBUF trong khi d liu trc cha c c. 0 = d liu khng b ghi Bit 5: SSPEN Synchronous Serial Port Enable bit 1 = bt ch SPI v cc chn SDI, SDO, SCK, SS c cu hnh tng ng. 0 = tt ch SPI Bit 4: CKP Clock Polarity Select bit 1 = thit lp trng thi rnh khi xung clock mc cao 0 = thit lp trng thi rnh khi xung clock mc thp Bit 3-0: SSPM3:SSPM0 Synchronous Serial Port Mode Select bit 0101 = ch slave, clock = chn SCK, tt chc nng ca chn SS 0100 = ch slave, clock = chn SCK, bt chc nng ca chn SS

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0011 0010 0001 0000

= = = =

ch ch ch ch

master, master, master, master,

clock clock clock clock

= = = =

tn s ca timer 2 /2 Fosc / 64 Fosc / 16 Fosc / 4

7.2.2 Cu hnh SPI cu hnh ch SPI cho vi iu khin PIC ta s dng cc bit SSPCON1<5:0> v SSPSTAT<7:6>, khi cu hnh cc bit ny SPI ca PIC s c cu hnh ch master hoc slave, cung clock cho SPI, v thit lp vic nhn d liu xy ra cnh ln hoc xung ca xung clock. Thanh ghi SSPSR c chc nng dch d liu ra v vo vi iu khin v lun l bit trng s cao trc. trong ch truyn, thanh ghi SSPBUF s ch cho n khi thanh ghi SSPSR sn sng nhn d liu ri mi ghi d liu ln thanh ghi SSPSR, nu c hnh ng ghi d liu vo thanh ghi SSPBUF trong lc d liu truyn cha xong th hnh ng c b qua v bitWCOL c bt ln bo hiu c xy ra ng . trong ch nhn, sau khi SSPSR nhn 8 bit d liu s c chuyn n thanh ghi SSPBUF v bit BF c bt ln bo hiu, nu d liu trc c lu trong thanh ghi SSPBUF cha c c m li c thm d liu mi th d liu mi s ghi ln d liu c v bitSSPOV c bt ln.

Hnh 7-2 Kt ni SPI master/slave Hm cu hnh ch SPI master cho vi iu khin PIC Code: void init_spi_master(void) { SSPSTATbits.CKE = 1; // when CKP = 0,CKE = 0 transmit data on falling clock,CKE = 1 transmit data on rising clock // when CKP = 1,CKE = 1 transmit data on rising clock,CKE = 1 transmit data on falling clock SSPCON1bits.CKP = 1; // CKP=0 data first,second is clock; CKP=1 clock SSPCON1bits.SSPEN = 1; // enable SPI master SSPCON1bits.SSPM0 = 0; // SSPCON1bits.SSPM1 = 0; // SSPCON1bits.SSPM2 = 0; // SSPCON1bits.SSPM3 = 0; // preacaler 1:4 }

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Bi 11 : iu khin led 7 on v m trn bng SPI 8.1 Kt ni phn cng

Hnh 8-1 S kt ni led 7 v led ma trn bi ny chng ta s s dng mch ri s1, mch bao gm 8 led 7 on v 1 led ma trn c s dng giao tip vi vi iu khin thng qua giao thc SPI. Trong mch ny vi iu khin PIC ng vai tr l master v cc IC TPIC595, 74HC595 ng vai tr l slave vi chc nng dch bit, ngoi chc nng dch bit IC TPIC595 cn c tc dng m v o tn hiu u vo, IC ny c s dng ph hp vi nguyn l hot ng ca led 7 on v led ma trn. Cch thc hot ng ca mch l vi iu khin s dch d liu cn xut ra ngoi n cc con IC dch, v khi no dch d liu cn xut ra ngoi vi iu khin s kha d liu li bng cch to mt xung t thp ln cao trn chn LATCH ca cc IC dch ny, lc ny cc IC dch s ly d liu c ct trong b m trong qu trnh dch d liu ca vi iu khin v xut ra ngoi. 8.2 Xy dng chng trnh Ngoi hm cu hnh ch SPI cho PIC nhu bi trn, chng ta cn hin thc thm hm to tn hiu LATCH, hm qut led 7 on v led ma trn, hm xa led 7 on v led ma trn.

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Ngoi ra chng ta cng cn b sung thm cc hm tin ch trong vic xut led 7 on v led ma trn, chi tit cc bn c th tham kho trong th vin source code. 8.2.1 Hm to tn hiu LATCH Code: void latch_spi(void) { unsigned char j; LATCH = 0;// create a rising clock to push data into output register for (j = 0; j <10;j++); LATCH = 1; for (j = 0; j< 10; j++); } 8.2.2 Hm xut led 7 on v led ma trn Vi cng gii thut qut led nh bi trn ch khc l trong chng trnh ngt ca timer ta gi hm xut trc tip d liu ra cc port ca vi iu khin th ra gi hm dch d liu t vi iu khin ra cc IC ngoi vi.Chi tit hm dch nh sau: Code: void scan_led7_matrix(void) { SSPBUF = 0x00; // select column for led matrix while (!SSPSTATbits.BF); SSPBUF = 0x00; // green matrix's data while (!SSPSTATbits.BF); SSPBUF = 0x00; // red matrix's data while (!SSPSTATbits.BF); SSPBUF = column[index]; // select column for led 7 segment while (!SSPSTATbits.BF); SSPBUF = code[buffer[index]]; // led7's data while (!SSPSTATbits.BF); latch_spi(); index = (index+1) % 8; } 8.2.3 Hm xa d liu trn led 7 on v led ma trn Code: void clear_spi(void) { unsigned char i; for (i =0; i< 5; i++) { SSPBUF = 0xff; while (!SSPSTATbits.BF); } latch_spi(); }

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Bi 12 : Qut 2 led ma trn bng SPI 9.1 Kt ni phn cng

Hnh 9 1 S kt ni 2 led ma trn trong bi ny chng ta s dng mch ri c 2 led ma trn. Trong s ny ng d liu(16 bits) c truyn theo giao thc SPI, dch tng bit d liu ra cho con IC TPIC595; cn ng chn hng ca led ma trn(8 bits) c kt ni trc tip vi PORTD ca vi iu khin PIC,nn c ch truyn y l truyn theo kiu song song. 9.2 Xy dng chng trnh Tng t i vi nhng bi qut led trn, ch khc y chng ta kt hp c phng php truyn song song v phng php truyn ni tip SPI.Vi mch ri c thit k 2 led ma trn s to thm iu kin thc hin nhng hiu ng chy ch a dng p mt, nh nhng bng quang bo hay thy thc t. Code: void scan_2_led_matrix(void) { PORTD = 0; SSPBUF = green_buffer[index]; // high byte green color while (!SSPSTATbits.BF); SSPBUF = green_buffer[MAX + index]; // low byte green color while (!SSPSTATbits.BF); SSPBUF = red_buffer[index]; // low byte red color while (!SSPSTATbits.BF); SSPBUF = red_buffer[MAX + index]; // high byte red color while (!SSPSTATbits.BF); latch_spi(); PORTD = 1 << index; index = (index+1) % 8; } Trong th vin source code, chng ti co demo mu hiu ng ch chy vi hai mu xanh v , cc bn c th tham kho trong ti liu nh km. 9.3 Code mu Download ti y

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Bi 13 : Giao tip ni tip I2C v DS1307 Mc ch: Tm hiu chun giao tip I2C v module I2C ca PIC18F. Tm hiu IC thi gian thc DS1307. Yu cu: Vit chng trnh hin th thng tin ngy gi ln LCD. 10.1 Gii thiu I2C I2C l 1 chun truyn ni tip theo m hnh Master Slave. Mt Master c th giao tip vi nhiu Slave. Mun giao tip vi slave no, master phi gi ng a ch tch cc slave ri mi c php ghi hoc c d liu t slave.

Hnh 10.1 : I2C interface Bus I2C gm 2 dy tn hiu SCL (Serial Clock Line) v SDA (Serial Data Line) u c ko ln ngun. D liu c truyn tng bit SDA theo tng clock ca SCL.

Hnh 10.2 : I2C Protocol Hnh 11.2 l giao thc I2C. Trc khi truyn d liu, ta cn khi ng I2C bng cch ko ln lt SDA v SCL xung mc thp. Sau 8 bit d liu s c ra tun t theo tng cnh xung chn SCL. Clock th 9 s dnh cho bit ACK. Bit ACK ny c th l do master gi xung hoc do slave gi v. Khi kt thc giao tip I2C, ta phi stop n bng cch ko 2 chn SCL v SDA ln mc cao. 10.2 I2C trong PIC18F4520 Module I2C trong PIC18F4520 h tr mode master v c slave (7bit a ch v 10bit a ch). Trong ti liu ny chng ti ch gii thiu chnh mode master ca PIC18F4520 giao tip vi

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IC real time clock DS1307. File i2c.h nh ngha 1 s hng s v 4 hm c bn ca giao tip I2C. Code: #ifndef __I2C_H #define __I2C_H /* PIC18 I2C peripheral library header */ /* SSPCON1 REGISTER */ #define SSPENB 0x20 // Enable serial I2C port #define SLAVE_7 6 // I2C Slave 7bit mode #define SLAVE_10 7 // I2C Slave 10bit mode #define MASTER 8 // I2C Master mode /*I2C interface*/ void i2c_init(unsigned char sync_mode,unsigned char slew, unsigned char baudrate ); //open I2C port void i2c_start(); //start condition void i2c_stop(); //stop condition void i2c_write_byte(unsigned char abyte); unsigned char i2c_read_byte(unsigned char ACK); #endif 10.2.1 Hm i2c_init u tin ta phi thit lp chiu input cho 2 chn SCL v SDA bng cch thit lp 2 bit tng ng trong thanh ghi TRISC l 1. PIC18F4520 s ng vai tr l master gi clock, ni dung trong thanh ghi SSPADD s c dng cho b sinh clock. Tn s cho giao tip I2C s c tnh theo cng thc sau y Code: f = Fosc/4*(SSPADD + 1) Ta s chn tn s cho SCL l 100kHz v phi np vo thanh ghi ny gi tr 49 (0x31) cho thnh anh 20MHz. Tip theo l chn mode master cho PIC18F4520, thit lp SSPM3:SSPM0 = 1000 v enable bit SSPEN trong thanh ghi SSPCON1. Code: void i2c_init(unsigned char sync_mode,unsigned char baudrate ) { SSPSTAT &= 0x3F; // power on state SSPCON1 = 0x00; // power on state SSPCON2 = 0x00; // power on state SSPCON1 |= sync_mode; // select serial mode DDRCbits.RC3 = 1; //Set SCL to input DDRCbits.RC4 = 1; //Set SDA to input SSPADD = baudrate; SSPCON1 |= SSPENB;//enable I2C } 10.2.2 Hm i2c_start khi ng I2C (Start condition) ta ch cn set bit Start Enable, SEN (SSPCON2<0>) v ch cho n khi qu trnh ny kt thc. Qu trnh khi ng I2C gm nhiu gian on, kt thc mi giai on s c cc c bo hiu.

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Hnh 10.3 : Khi ng I2C Ban u 2 chn SDA v SCL mc cao. Khi SEN = 1, b sinh baudrate bt u m v khi ht time out, chn SDA ko xung mc thp, bit S (SSPSTAT<3>) bt ln 1 bo hiu giai on 1 ca qu trnh khi ng I2C kt thc. Sau b sinh baudrate c load li v bt u m. Khi ht time out, chn SCL s c ko xung thp, kt thc qu trnh khi ng I2C. Lc ny bit SEN c xa bng phn cng v bit SSPIF c bt ln 1. Khi hin thc code nu vit k ta c th ch tng giai on, tuy nhin module I2C c tch hp sn trong PIC nn xc sut li cng rt thp. Ta c th lm n gin hn bng cch set bit SEN ln v ch cho n khi SSPIF bt ln 1. Ta cn phi xa SSPIF cho ln kim tra tip theo v bit ny khng c t ng xa bng phn cng. Code: void i2c_wait() { while(PIR1bits.SSPIF != 1){}; //wait SSPIF set PIR1bits.SSPIF = 0; //clear SSPIF } void i2c_start() { SSPCON2bits.SEN = 1; //set start enable bit i2c_wait(); //wait SSPIF set } 10.2.3 Hm i2c_stop

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Hnh 10.4 : Stop I2C Qu trnh kt thc I2C c bt u bng cch set bit PEN (SSPCON2<2>). Cng ging nh qu trnh khi ng, qu trnh kt thc gm 2 giai on chnh v mi giai on u c bit bo hiu nhng ta c th lp trnh n gin bng cch set bit PEN v ch cho n khi SSPIF c set ln 1. Code: void i2c_stop() { SSPCON2bits.PEN = 1; //set stop enable bit i2c_wait(); //wait SSPIF is set } 10.2.4 Hm i2c_write_byte Vic gi 1 byte d liu t master xung slave c bt u khi c lnh gn vo thanh ghi SSPBUF. Ngay lc ny c BF (Buffer Full) s bt ln 1. Qu trnh gi d liu bt u theo tng xung clock chn SCL. Sau 8 clock, 8 bit d liu trong thanh ghi SSPBUF c shift ht v c BF bt xung 0. Master s th chn SDA slave c th gi tn hiu ACK v master. Nu nhn c ACK, bit ACKSTAT s c xa, ngc li bit ny s c bt ln 1. Gi tr ACK c lu trong bit ACKDT. Qu trnh gi ACK t slave ln master c thc hin trong clock th 9 ca SCL v sau bit SSPIF c set ln 1. Ngi lp trnh c th check qua cc c BF, ACKSTAT v sau cng l SSPIF kim tra li. on code di y ch kim tra c nhn c ACK hay khng ch cha kim tra ACK ng hay sai. Code: void i2c_write_byte(unsigned char abyte) { SSPBUF = abyte; //wait BF is set while(SSPSTATbits.BF != 0){} //wait ACK received, ACKSTAT is set while(SSPCON2bits.ACKSTAT != 0){} i2c_wait(); } Tuy nhin trong 1 vi ng dng n gin ta c th vit nh sau: Code:

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void i2c_write_byte(unsigned char abyte) { SSPBUF = abyte; //byte to send i2c_wait(); //wait SSPIF is set } 10.2.5 Hm i2c_read_byte Hm ny dng c 1 byte d liu t slave v. Khi bit RCEN (SSPCON2<3>) c set ln 1, d liu t slave bt u gi vo thanh ghi SSPBUF. Sau 8 clock d liu s c shift vo thanh ghi SSPBUF v c BF s c bt ln 1. ng thi c SSPIF cng c set v RCEN c clear bng phn cng. Khi c xong, c SSPIF s c xa, ta cn set ACKEN ln 1 (SSPCON2<4>) gi ACK v cho slave. Bit ACK l 0 hay 1 c quy nh trong bit ACKDT (SSPCON2<5>). Khi gi xong ACK clock th 9, c SSPIF s c bt ln li. Code: unsigned char i2c_read_byte(unsigned char ack) { SSPCON2bits.RCEN = 1; //enable receive i2c_wait(); //wait SSPIF is set SSPCON2bits.ACKDT = ack; i2c_wait(); SSPCON2bits.ACKEN = 1; return SSPBUF; //set ACK value //wait SSPIF is set //enable ACK feedback

} 10.3 Real Time Clock DS1307 DS1307 l IC thi gian thc (Real time clock) m gi, pht, giy, thng, ngy ca thng, ngy ca tun, nm k c nm nhun (n nm 2100). 56 byte Ram lu tr d liu, nhng d liu khng S dng 2 dy tn hiu truyn d liu theo giao thc I2C. b mt khi tt ngun.

C th lp trnh c xut tn hiu xung vung. T ng pht hin ra ngun cung cp b li (ngt ngun) v chuyn qua mch bo v s dng ngun pin d tr.

10.3.1 Nguyn l hot ng DS1307 hot ng nh mt slaver trn bus d liu ni tip. truy xut ni dung ta phi thit lp mt iu kin Start v cung cp m nhn dng ca IC (Device Identification Code) theo sau bi thanh ghi a ch. Cc thanh ghi theo sau c truy xut tun t cho n khi gp tn hiu Stop. Khi VCC = 1.25Vbat th DS1307 s kt thc vic truy xut v reset li b m a ch. Cc Input s khng c nhn ra ti thi im ny ngn nga mt s lng ln d liu c ghi ti DS1307 t h thng bn ngoi. Khi VCC < Vbat th ic ny s chuyn sang mode s dng pin d tr. Khi ngun chnh c bt ln th IC ny s chuyn t dng ngun pin sang dng ngun chnh. Hnh sau m t nhng phn chnh ca DS1307.

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Hnh 10.5 : S khi DS1307 10.3.2 Cc tn hiu Input v Output VCC, GND : Ngun DC c cung cp cho IC qua nhng chn ny. Khi gn vo ngun 5V th IC ny c th c ghi bnh thng. Nhng khi ngun gim xung cn 3V th vic c ghi s khng c php. Tuy nhin, cc chc nng ca timer vn tip tc vi ngun cung cp thp. Khi Vcc gim xung di VBAT th RAM v timekeeper c chuyn qua s dng ngun cung cp ti VBAT. VBAT : Cung cp ngun d tr 3V. hot ng ch s dng ngun Vbat th 2.0V < Vbat < 3.5V. Khi VCC gn bng 1.25VBAT th chng ta s khng c php truy xut vo RTC (Real time clock) v Ram bn trong ca IC. SCL (Serial Clock Input) : SCL c dng ng b d liu trn ng truyn ni tip. SDA (Serial Data Input/Output) : SDA l chn I/O. SDA l chn Open drain nn cn c in tr ko ln bn ngoi. SQW/OUT (Square Wave/Output Driver) : Khi c bt ln, th bit SQWE set ln 1, v chn ny s output ra 1 trong 4 tn s sng vung l 1hz, 4khz, 8khz, 32khz. Chn ny cng l chn Open drain nn cng yu cu c in tr ko ln ngun bn ngoi. SQW/OUT s hot ng khi c ngun cung cp vo cho d l ngun VCC hay l VBAT. X1, X2 : Kt ni vi thch anh 32.768Khz. Mch to xung bn trong c thit k hot ng vi thch anh v t CL = 12.5 pF.

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10.3.3 RTC v s a ch Ram S a ch ca RTC v cc thanh ghi Ram ca DS1307 nh hnh di. Cc thanh ghi RTC c nh a ch t 00h n 07h. Cc thanh ghi Ram c nh a ch tip theo sau v t 08h n 3fh. Trong khi truy sut nhiu byte v khi con tr a ch ch ti 3fh, v tr cui ca vng nh Ram, th n s quay li a ch 00h truy xut tip.

Hnh 10.6 : RTC v s RAM 10.3.4 Thng tin thi gian v lch Thng tin thi gian v lch c cha trong trong cc thanh ghi tng ng. Cc thanh ghi RTC nh hnh trn. Thi gian v lch c set hoc khi to bng cch ghi ra cc byte thanh khi tng ng. Ni dung ca cc thanh ghi thi gian v lch c nh dng theo kiu BCD. Bit 7 ca thanh ghi 0 l clock halt bit (CH). Khi bt ny c set ln 1 th mch dao ng s b n khng c s dng na, khi clear xung 0 th mch dao ng s c kch hot tr li. DS1307 c th chy ch 12h hay 24h. Bt th 6 ca thanh ghi hours c nh ngha set xem s dng IC ny ch no. Khi bit ny bng 1 th ch 12h c chn. Trong ch 12h th bit 5 ch AM/PM (PM khi bit ny l 1). Trong ch 24h, th bt 5 l bt th 2 ca 10hour (20:23).

Hnh 10.7 : nh dng d liu 10.3.5 Ghi d liu vo DS1307

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Hnh 10.8 : Ghi d liu vo DS1307 y l qu trnh truyn d liu t master xung slave. Khi master gi xong 1 byte, slave s gi li bit ACK. Qu trnh giao tip nh sau: Master gi tn hiu Start. Master gi a ch ca DS1307 (1101 000) v bit R/W, trong trng hp ny l 0. Byte u tin m master gi xung sau khi start l D0. Master gi a ch pointer d liu cn ghi, chng hn l 0x00 (register pointer, word address) Master gi cc byte data cn ghi. Master gi tn hin stop.

Code hin thc cho qu trnh ny nh sau Code: void rtc_write(unsigned char *buff) { i2c_start(); i2c_write_byte(0xD0); //Address + Write bit i2c_write_byte(0x00); //Pointer i2c_write_byte (*(buff+0)); //Second i2c_write_byte (*(buff+1)); //Minute i2c_write_byte (*(buff+2)); //Hour i2c_write_byte (*(buff+3)); //Day i2c_write_byte (*(buff+4)); //Date i2c_write_byte (*(buff+5)); //Month i2c_write_byte (*(buff+6)); //Year i2c_stop(); } buff l 1 mng c 7 phn t, tng ng vi cc gi tr giy, pht, gi, th, ngy, thng v nm. 10.3.6 c d liu t DS1307

Hnh 10.9 : c d liu t DS1307 y l qu trnh truyn d liu t slave ln master. Nh trnh by phn trc, khi gi nhn tng byte, s c bit ACK i km ngoi tr byte cui cng trc khi stop. c th c chnh xc gi tr mong mun, thng thng ta phi ghi vo thanh ghi a con tr d liu (register pointer). Qu trnh ny chnh l trnh truyn d liu t master xung slave nn R/W bit s l 0. Sau khi ghi d liu v register pointer xong, qu trnh c d liu mi bt u, v bit R/W s l 1. Tng bc c d liu t DS1307 nh sau:

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Master Master Master Master Master Master NACK. Master

gi tn hiu start. gi a ch DS1307 + R/W = 0 : 0xD0. gi byte ghi vo register pointer : 0x00. gi tn hiu start gi a ch DS1307 + R/W = 1 : 0xD1. c cc byte d liu v gi bit ACK. Byte cui cng trc khi stop, master gi bit gi tn hin stop.

Code hin thc cho qu trnh ny nh sau Code: void rtc_read(unsigned char * buff) { //send address to slave and reset pointer i2c_start(); i2c_write_byte(0xD0); //Address + Write bit i2c_write_byte(0x00); //Pointer i2c_start(); //Restart i2c_write_byte(0xD0); //Address + Read bit *(buff+0)=i2c_read_byte(ACK); // Second *(buff+1)= i2c_read_byte(ACK); // Minute *(buff+2)= i2c_read_byte(ACK); // Hour *(buff+3)= i2c_read_byte(ACK); // Day *(buff+4)= i2c_read_byte(ACK); // Date *(buff+5)= i2c_read_byte(ACK); // Month *(buff+6)= i2c_read_byte(ACK); // Year i2c_stop(); } 10.4 Xy dng chng trnh y s gii thiu cu trc chng trnh hin th thng tin ngy thng nm, gi pht giy ca DS1307 ln LCD. Chng trnh gm 3 module 9 l I2C, RTC v LCD.

Hnh 10.10 : Cu trc chng trnh Chi tit chng trnh c hin thc trong th mc Bai11_I2C. chy c chng trnh bn cn bt 2 switch ca RTC (SW4) ln ON, bt ngun ca LCD (SW3) v tt led PortB (SW1).

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Hnh 10.11 : Chng trnh DS1307 trn BKIT PIC 10.5 Code mu Download ti y

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Bi 14 : Analog to Digital Converter ADC Mc ch: Tm hiu module ADC ca PIC18F. Yu cu: Vit chng trnh hin th gi tr ADC chn AN0 ln LCD. 11.1 Gii thiu Vi iu khin ch c th x l c tn hiu s ri rc (digital signal), chng khng th x l c cc tn hiu tng t (analog signal). B chuyn i tn hiu tng t sang s (analog to digital converter) hay cn gi l ADC, s chuyn in p tng t (analog voltage hay analog signal) sang dng s ri rc (digital number). Vi x l s biu din tn hiu in p tng t thnh 1 s nguyn (non-fractional number) v s x l trn s nguyn ny.

Hnh 11.1: Analog to Digital Converter Theo v d trn, in p 2.343volt s c chuyn i thnh s nguyn 87. Ngi lp trnh c th dng s 87 ny biu din cho gi tr in p ng vo 2.343 volt. Vic vi iu khin x l trn s 87 s t hiu qu cao hn, v n l 1 s nguyn. 11.2 Nguyn l chuyn i ADC

Hnh 11.2 : Chuyn i ADC Qu trnh chuyn i ADC gm 3 giai on: Giai on 1 : Np in cho t chn ADC (Holding Capacitor). Giai on ny tn 1 khong thi gian c gi l Acquisition time (TACQ). Trong vi iu khin PIC, thi gian ny c th c cu hnh bng tay hoc t ng. Khi chn cu hnh bng tay, ngi lp trnh phi t tnh ton thi gian delay c th np y t trc khi ban hnh lnh chuyn i. Khi chn cu hnh t ng, vi iu khin s m bo l sau khi ban hnh lnh chuyn i 1 khong TACQ, qu trnh chuyn i mi bt u. Thi gian ny l 1 hng s v ty thuc vo vi iu khin. Chng ta cn c k datasheet ca n xc nh cho ng. Giai on 2 : Ngt kt ni vi t Holding Capacitor bng 1 lnh SLEEP. Qu trnh ny c thc hin t ng bi vi iu khin, ngi lp trnh khng cn phi quan tm. Thi gian chuyn i ph thuc vo phn gii ca gi tr ADC (8bit, 10bit hay 13 bit) v clock cp cho module ADC. Khi lp trnh, chng ta thng khng quan tm n thi gian ny v khi chuyn i xong, vi iu khin s set c bo hiu. Ngi lp trnh ch cn polling xt c ny hoc s dng ngt ly gi tr chuyn i. Giai on 3 : X t Holding Capacitor. Giai on ny ch chim 1 khong thi gian nh v n c thc hin t ng bi vi iu khin. Giai on ny xy ra sau khi c bo hiu chuyn i hon tt. c th bt u tip vic chuyn i ln th 2, vi iu khin s cn phi ch thm 1 khong thi gian x t v acquisition time. Nu khng ch ng thi gian ny, qu trnh chuyn i bt u sm hn, kt qu thu c c th khng cn chnh xc na. 11.3 ADC trong PIC18F i vi dng chip PIC 40/44 chn c 13 knh ADC, dng 28 chn th c 10 knh ADC. Module ADC s chuyn i tn hiu tng t thnh tn hiu s 10 bit. Module ADC trong PIC c 5 thanh ghi:

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ADRESH : Thanh ghi kt qu, cha phn bit cao. ADRESL: Thanh ghi kt qu, cha phn bit thp. ADCON0, ADCON1, ADCON2 : Cc thanh ghi iu khin.

Thanh ghi ADCON0

Hnh 11.3 : Thanh ghi ADCON0 Bit 7-6 : Khng s dng. Bit 5-2 CHS3-CHS0 : La chn knh Analog. 0000 : Knh 0 (AN0) 0001 : Knh 1 (AN1) 0010 : Knh 2 (AN2) 1101 : Knh 11 (AN11) 1100 : Knh 12 (AN12) 1101,1110,1111 : Khng s dng. Bit 1 GO/DONE : Bit trng thi ca qu trnh chuyn i khi ADON = 1. 1 : ang chuyn i A/D. 0 : Chuyn i hon tt. Bit 0 ADON : A/D On bit 1 : Cho php chuyn i. 0 : Tt chc nng chuyn i. Thanh ghi ADCON1

Hnh 11.4 : Thanh ghi ADCON1 Bit 7 6 : Khng s dng. Bit 5 : VCFG1 Voltage Reference Configuration bit (bit cu hnh in p tham kho VREF-) 1 : in p tham kho VREF- l in p chn AN2 0 : in p thao kho VREF- = VSS Bit 4 : VCFG0 Voltage Reference Configuration bit (bit cn hnh in p tham kho VREF+) 1 : in p tham kho VREF+ l in p chn AN3 0 : in p tham kho VREF+ l VDD Bit 3-0 A/D Port Configuration Control bits : Cu hnh chn l Analog hay Digital Thanh ghi ADCON2

Hnh 11.5 : Thanh ghi ADCON2 Bit 7 ADFM : nh dng kt qu trong 2 thanh ghi ADRESH v ADRESL 1 : Canh phi

0 : Canh tri

Bit 6 : Khng s dng Bit 5-3 : A/D Acquisition Time Select bit : Bit chn thi gian np cho t Holding Capacitor.

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111 : 20 TAD 110 : 16 TAD 101 : 12 TAD 100 : 8 TAD 011 : 6 TAD 010 : 4 TAD 001 : 2 TAD 000 : 0 TAD TAD l thi gian chuyn i 1 bit ADC, ph thuc vo clock c la chn bn di. Thi gian np cho t Holding Capacitor c nh l 2.4us, sau khi chn clock cho module ADC, ta s phi tnh ton chn h s nhn vi TAD Lu trong trng hp 000, y l ch lp trnh bng tay cho thi gian Acquisition Time, ngi lp trnh phi t to 1 khong thi gian delay cho qu trnh np t Holding Capacitor. Bit 2-0 : A/D Conversion Clock Selection bit : Bit chn clock cho b chuyn i A/D 111 : FRC 110 : FOSC/64 101 : FOSC/16 100 : FOSC/4 011 : FRC 010 : FOSC/32 001 : FOSC/8 000 : FOSC/2 Nu ta chn l 000 th TAD = 2 TOSC = 2/FOSC, FOSC l chu k lnh, bng tn s dao ng. 11.4 Cu hnh ADC trong PIC18F Vic cu hnh module ADC trong PIC18F i theo trnh t sau: Cu hnh chn A/D (s knh AD, chiu ca chn AD l input), in p tham kho (ADCON1) Chn knh A/D (ADCON0) Chn thi gian acquisition time (ADCON2) Chn clock. Bt ch AD (bit ADON trong ADCON0).

Nu chn la ch acquisition time l t ng, bn ch cn set bit GO_DONE bt u qu trnh chuyn i v polling bit ny ch cho n khi qu trnh chuyn i hon tt. Nu acquisition time c chn l ch chnh bng tay (manual mode), bn phi t vit delay ch, sau mi c php set bit GO_DONE. 11.5 Hin thc chng trnh

Hnh 11.6 : Kin trc chng trnh ADC 11.5.1 Hm init_adc() Hm ny dng khi to ban u cho module ADC, c hin thc ng theo trnh t cu hnh ADC trong PIC 18F. mch BKIT PIC, ch c 1 knh ADC ni vi chn AN0, bit 0 ca PortA. thanh ghi ADCON1, ta s ln lt chn in p tham kho l VSS v VDD, cc bit 5,4 set l 0. Cu hnh ch dng 1 knh AD chn AN0, bit 3:0 PCFG3:PCFG0 = 1110, ADCON1 = 0x0E. Cu hnh chiu input cho chn ADC ny. Chn knh AD0 chuyn i bng cch thit lp CHS3:CHS0 = 0000, ADCON0 = 0x00. Chn clock l FOSC /2 (ADCS2:ADCS0 = 000), lc TAD = 2TOSC = 2/(5MHz) = 2/(510^6) (s).

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Thi gian acquisition time l hng s 2.4us = 2.4 10^-6 (s). Ta phi tha mn c 2.4 10^-6 <= 2k/(510^6) => k >= 1.2 Ta s chn k = 2 AQCT2:AQCT0 = 001. Nh vy ADCON2 = 0x04. Bt bit ADON thanh ghi ADCON0. Code: void init_adc() { TRISA = 0x01; //input for analog pin ADCON1 = 0x0E; //config ADC pins ADCON0 = 0x00; //select AN0 ADCON2 = 0x04; //select acquisition time ADCON0bits.ADON = 1; //enable ADC } 11.5.2 Hm get_adc_value Sau khi khi to xong module ADC, ta c th ly kt qu bt c lc no. Trc tin ta s set bit GO_DONE ln 1 bt u qu trnh chuyn i v ch cho n xung 0, vic chuyn i hon tt, kt qu s c lu trong 2 thanh ghi ADRESH:ADRESL (ch canh tri). Code: int get_adc_value() { int result = 0; ADCON0bits.GO_DONE = 1; //start conversion while(ADCON0bits.GO_DONE == 1){} //polling result = ADRESH; result = (result<<2) + (ADRESL>>6); return result; } Nu ngi dng ch cn 8 bit th c th s dng gi tr trong thanh ghi ADRESH l .

Hnh 11.7 : Chng trnh ADC trn BKIT PIC 11.6 Code mu Download ti y

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Bi 15 : iu ch xung PWM Mc ch: Tm hiu module CCP1 ca PIC18F, thit lp ch hot ng PWM. Yu cu: Vit chng trnh iu khin tc ng c, hin th tc ra mn hnh LCD. 12.1 Khi nim PWM PWM vit tt ca t Pulse Width Modulation. PWM c s dng nhiu trong h thng iu khin t ng ngy nay. N c ng dng trong iu khin tc ng c, sng ti ca led, mn hnh LCD, pha mu cho bang quang bo, s dng trong cc thut ton iu khin vn tc cho Robot nh PI, PD, PID Hiu n gin PWM hot ng nh mt cng tc ng m rt nhiu ln trong 1 giy. Nu tn s ng m cng nhanh th in p cp trung bnh cng ln.

Mt s khi nim c bn ca PWM : Tn s (Hz, Khz). Chu k T, thi gian xung mc cao TH + thi gian xung mc thp TL. Duty Cycle: t l thi gian xung mc v thi gian xung mc thp.

Nh hnh trn ta c Duty Cycle ln lt l 0%, 25%, 50%, 75%, 100%. Mt s cng thc :

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Khi nu TOn = 0 th VoltOutput = 0 (V) cn TOn = TTotal th VoltOutput = VoltInput . 12.2 PWM trong PIC18F4520 PIC18F4520 c 2 module CCP. y chng ti gii thiu module CCP1. Module ny ngoi chc nng PWM thng thng, n cn c chc nng Enhanced PWM dng iu khin mt s loi mch cu H thng dng. Nguyn l hot ng chung ca cc module PWM tch hp sn trong vi iu khin l n s s dng 1 b timer m. Khi gi tr m ca timer bng vi Chu k hoc Duty Cycle th ng ra s thay i. Hnh di y minh ha cch hot ng ca module PWM trong PIC18F4520, n s dng timer2 cho b m.

Hnh 12.1 : Nguyn l hot ng ca PWM Trnh t thit lp PWM trong PIC18F4520 nh sau: 12.2.1 Thit lp chu k PWM Chu k ca module CCP1 c tnh nh sau : PWM Period = (PR2 + 1)*4*TOSC*(TMR2 Prescaller) Trong TOSC = 1/FOSC, FOSC = 20MHz nu s dng thch anh ngoi. TMR2 Prescaller c xc nh trong thanh ghi T2CON. ch mc nh ban u, TMR2 Prescaller=1. Trn thc t, ngi ta dng thut ng tn s PWM, l nghch o ca chu k :

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PWM Frequence = FOSC/ [ (PR2+1) * 4 * (TMR2 Prescaller) ] Tn s iu khin PWM ty thuc vo tng loi thit b. i vi ng c, tn s PWM phi ph hp vi p ng ca driver iu khin ng c. Trong mch BKIT PIC, chng ti chn tn s l 2 kHz. Gi s ta chn TMR2 Prescaller l 16 (T2CKPS1 = 1), th gi tr ca PR2 l PR2 = 20MHz/ (4 * 16 * 2KHz) - 1 ~ 155 12.2.2 Thit lp PWM Duty Cycle Duty Cycle ca CCP1 c thit lp trong 2 thanh ghi CCPR1L (8bit) v 2 bit DC1B1:0 trong thanh ghi CCP1CON. Tuy nhin i vi ng c nh th vi 8 bit l , ta c th mc nh DC1B1:0 = 00 ngay khi khi to. Gi tr ca CCPR1L cng cao th duty cycle cng ln, v nh vy in p ng ra ca CCP1 (RC2) cng cao. Sau khi thit lp xong 2 thng s trn, cc bc cn li l thit lp chiu output cho chn RC2, cho php timer2 m bng cch set bit TMR2ON ln 1, v cu hnh CCP1CON l ch Single PWM. 12.3 Xy dng chng trnh Kin trc chng trnh gm c 2 module chnh PWM v LCD.

Hnh 12.2 : Kin trc chng trnh PWM Module PWM gm c 2 file pwm.h khai bo cc interface v pwm.c hin thc cc interface . Interface trong pwm.h nh sau: Code: #ifndef _PWM_H_ #define _PWM_H_ #include <P18F4520.h> void init_pwm(); void set_DC(unsigned char duty_cycle); #endif 12.3.1 Hm init_pwm Hm ny hin thc qu trnh khi ng cho module PWM. Trc tin l cu hnh prescaller cho timer2, np gi tr PWM Period v chn ch PWM trong thanh ghi CCP1CON. Code:

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void init_pwm() { T2CONbits.TMR2ON = 0;

//turn off timer2

T2CONbits.T2CKPS0 = 0; T2CONbits.T2CKPS1 = 1; //prescaler 1:16 PR2 = 155; //PWM period CCP1CONbits.DC1B0 = 0; //PWM duty cycle CCP1CONbits.DC1B1 = 0; //2 bits LSB CCPR1L = 0x00; //8bits MSB CCP1CONbits.P1M0 = 0; //PWM single mode CCP1CONbits.P1M1 = 0; CCP1CONbits.CCP1M0 = 0;//select PWM function CCP1CONbits.CCP1M1 = 0; CCP1CONbits.CCP1M2 = 1; CCP1CONbits.CCP1M3 = 1; TRISCbits.TRISC2 = 0; //config RC2 output T2CONbits.TMR2ON = 1; //start timer2 } 12.3.2 Hm set_DC Hm ny ch n gin l thit lp duty cycle trong thanh ghi CCPR1L. Gi tr trong thanh ghi ny cng cao th p ra chn RC2 cng cao, gi tr ti a l 255 tng ng vi khong 5V. Code: void set_DC(unsigned char duty_cycle) { CCPR1L = duty_cycle; } Chng trnh demo cho phn ny c hin thc trong th mc Bai13_PWM. Hm main s tng dn duty cycle ln v ng c s quay nhanh dn. Gi tr ca duty cycle (hay tc ca ng c) s c hin th ra LCD.

12.4 Code mu Download ti y

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Bi 16 : Giao tip UART RS232 13.1 Nguyn l giao tip UART Uart RS232 l chun giao tip kh ph bin v c h tr hu ht cc dng vi iu khin v khong cch xa v chi ph thp. Dng 8051 h tr 1 knh giao tip uart. D liu c truyn i trn chn TX gm 1 start bit (mc 0), data v 1 stop bit (mc 1). Tc truyn : n v bit per second (bps) cn gi l Baud (s ln thay i tn hiu trong 1 giy thng s dng cho modem). i vi ng truyn th Baud v bps l nh nhau. UART l phng thc truyn nhn bt ng b. ngha l bn nhn v bn pht khng cn phi c chung tc xung clock (v d : xung clock ca vi iu khin khc xung clock ca my tnh) . Khi bn truyn mun truyn d liu s gi start bit (bit 0) bo cho bn thu bit bt u nhn d liu v khi truyn xong d liu th stop bit (bit 1) s c gi bo cho bn thu bit kt thc qu trnh truyn. Khi c start bit th c hai bn s dng chung 1 xung clock (c th sai khc mt t) vi rng 1 tn hiu (0 hoc 1) c quy nh bi baud rate, v d baud rate = 9600bps ngha l rng ca tn hiu 0(hoc 1) l 1/9600 = 104 ms v khi pht th bn pht s dng baud rate chnh xc (v d 9600bps) cn bn thu c th dng baud rate sai lch 1 t(9800bps chng hn). Truyn bt ng b s truyn theo tng frame v mi frame c cu trc nh sau:

Ngoi ra trong frame truyn c th c thm bit odd parity (bit l) hoc even parity (bit chn) kim tra li trong qu trnh truyn. Bit parity ny c c im nu s dng odd parity th s cc bit 1 + odd parity bit s ra 1 s l cn nu s dng even parity th s cc bit 1 + even parity bit s ra 1 s chn. 13.2 Giao tip UART vi my tnh giao tip COM gia vi iu khin v my tnh, ta kt ni mch theo s nh sau:

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Hnh 13.1 : Kt ni my tnh v vi iu khin Do mc in p ca tn hiu logic 1/0 cng COM ca my tnh khc vi vi iu khin, nn MAX 232 c tc dng chun ho mc in p gia my tnh v iu khin trong qu trnh truyn nhn d liu. Nu giao tip trc tip gia 2 vi iu khin, ta khng cn phi s dng MAX 232.

13.3 UART trong PIC18F Trong phn ny xin gii thiu cc bc thit lp vic truyn 1 byte UART, vic cu hnh nhn UART cng tng t nh truyn. Trnh t cc bc nh sau : Np gi tr vo 2 thanh ghi BRGH: BRG thit lp tc truyn theo cng thc Baudrate = Fosc/ (64 * ([BRGH : BRG] + 1)). Enable serial port bng cch clear bit SYNC v set bit SPEN Nu mun thit lp interrupt, th set thm TXIE, GIE v PEIE. Set bit TXEN cho php truyn. Np d liu vo thanh ghi TXREG. Khi truyn xong c TXIF s bt ln 1, ta s kim tra c ny trc khi truyn d liu mi.

Hin thc bng code nh sau :

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Code: void init_uart_transmit() { //step 1 : Select baurate TXSTAbits.BRGH = 0; BAUDCONbits.BRG16 = 1; SPBRGH = 0; SPBRG = 25; //9600 //step 2 : enable ASYN TXSTAbits.SYNC = 0; RCSTAbits.SPEN = 1; //step 3 : enable uart transmission interrupt PIE1bits.TXIE = 1; PIR1bits.TXIF = 0; INTCONbits.GIE = 1; INTCONbits.PEIE = 1; //step 4 : disable bit 9 TXSTAbits.TX9 = 0; //step 5 : enable transmission TXSTAbits.TXEN = 1; } Sau khi enable vic truyn, ta ch cn ghi d liu v thanh ghi TXREG v kim tra c TXIF bt ln: Code: void uart_transmit(unsigned char data) { TXREG = data; while(PIR1bits.TXIF == 1){} } 13.4 Kim tra truyn nhn UART kim tra vic truyn nhn uart c ng hay khng ta thng dng 1 s ng dng hyper terminal kim tra. Lc ny my tnh ca chng ta s l i tng dng giao tip vi BKIT PIC. Trong a CD ny c phn mm hyper terminal kh thng dng cha trong th mc Terminal, bn ch cn double click vo file Terminal.exe l khi ng c chng trnh.

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Hnh 13.2 : Hyper Terminal Cng vic cn li l cu hnh cho cng COM truyn nhn uart cho tng thch vi giao thc truyn nhn ca board 89. Cc thng s thng thng l Baud rate 9600, Data bit 8bit, khng c Parity (chn none) v 1 Stop bit. Nhn nt Connect kt ni. K t y nu board 89 c gi d liu ln, d liu ny s nm trong phn Receive. Ngc li, mun gi d liu xung board 89 ta g vo textbox v n Send. 13.5 Download Code mu Phn mm Terminal

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Bi 17 : Giao tip vi bn phm PS2 13.6 Ngt ngoi 13.6.1 Gii thiu ngt ngoi Ngt ngoi trn vi iu khin thng l mt chn vo c kh nng pht hin s thay i tn hiu bn ngoi. C th chia ngt thnh hai loi : Ngt cnh v ngt mc. Ngt cnh c hai loi: ngt cnh ln xy ra khi c s chuyn tn hiu t mc thp ln mc cao chn ngt ngoi. Tng t ngt cnh xung xy ra khi c s chuyn tn hiu t mc cao xung mc thp. Ngt mc cng c hai loi: ngt mc cao v mc thp. Ngt mc cao (thp) xy ra khi tn hiu ti chn ngt ngoi mc cao (thp) trong ti thiu 1 chu k. Trong vi iu khin PIC ch c ch ngt cnh(ln/xung) khng tn ti ch ngt mc. 13.6.2 Ngt ngoi trong vi iu khin PIC Trong vi iu khin PIC, c 3 ngt ngoi INT0, INT1, INT2 nm tng ng vi cc chn RB0, RB1, RB2. V trong vi iu khin PIC ch c hai loi ngt l ngt cnh ln v ngt cnh xung. i vi ngt ngoi INT1 v INT2 c hai mc u tin ngt l ngt c u tin cao v u tin thp, cn i vi ngt ngoi INT0 th lun c nh l ngt c u tin cao. Cc chn ngt ngoi khi s dng phi c cu hnh ch input. 13.6.3 Cc thanh ghi cu hnh ngt ngoi cho PIC Ngt trong ci iu khin PIC c cu hnh qua cc thanh ghi INTCON, INTCON2, INTCON3. Thanh ghi INTCON

Code: Bit 7 GIE Global Interrupt Enable Nu IPEN = 0 1 = cho php ngt 0 = cm tt c cc ngt Nu IPEN = 1 1 = cho php ngt mc cao 0 = cm tt c cc ngt PEIE Peripheral Interrupr Enable Nu IPEN = 0 1 = cho php ngt ngoi vi 0 = cm cc ngt ngoi vi Nu IPEN = 0 1 = cho php ngt mc thp 0 = cm ngt mc thp INT0IE External Interrupt 0 Enable 1 = cho php ngt ngoi 0 0 = tt ngt ngoi 0 INT0IF External Interrupt Flag

Bit 6

Bit 4

Bit 0

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1 = c bo ngt ca ngt ngoi 0 0 = khng c tn hiu ngt ngoi 0 Thanh ghi INTCON2

Code: Bit 6 INTEDG0 External Interrupr 0 Edge Select 1 = ngt ngoi 0 khi c cnh ln 0 = ngt ngoi 0 khi c cnh xung INTEDG1 External Interrupr 1 Edge Select 1 = ngt ngoi 1 khi c cnh ln 0 = ngt ngoi 1 khi c cnh xung INTEDEG2 External Interrupt 2 Edge Select 1 = ngt ngoi 2 khi c cnh ln 0 = ngt ngoi 2 khi c cnh xung Thanh ghi INTCON3

Bit 5

Bit 4

Code: INT2IP External Interrupt 2 Priority 1 = u tin cao 0 = u tin thp Bit 6 INT1IP External Interrupt 1 Priority 1 = u tin cao 0 = u tin thp Bit 4 INT2IE External Interrupt 2 Enable 1 = cho php ngt ngoi 2 0 = tt ngt ngoi 2 Bit 3 INT1IE External Interrupt 1 Enable 1 = cho php ngt ngoi 1 0 = tt ngt ngoi 1 Bit 1 INT2IF External Interrupt 1 Flag 1 = c bo ngt ca ngt ngoi 0 0 = khng c tn hiu ngt ngoi 0 Bit 0 INT1IF External Interrupt 1 Flag 1 = c bo ngt ca ngt ngoi 0 0 = khng c tn hiu ngt ngoi 0 Cc c ngt ngoi INT0IF, INT1IF, INT2IF phi c xa bng chng trnh trong hm x l ngt ca chng. 13.7 Giao tip PS/2 D liu trong giao tip PS/2 c truyn ni tip tng bit. Khi mt phm c nhn, 11 bit bao gm Start bit, 8 bit d liu (bit trng s thp truyn trc), 1 bit parity v 1 stop bit s c gi i: Bit 7

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Hnh 14.1 Dng sng ca giao tip PS/2 Ta s ly d liu ti cnh xung ca clock, chn ca clock c ni vo chn ngt ngoi INT0 ca vi iu khin Atmega32 (PD2) nh sau:

Hnh 14 14.2 S kt ni PS/2 Khi 1 phm c nhn xung, m make_code s c gi ln. Trong khong thi gian phm c xung th m make_code vn c nh k gi ln. Khi th phm ra th bn phm gi ln m break_code v make_code. Bng m make_code v break_code ca cc phm nh sau:

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D dng nhn ra m break_code ca 1 phm gm 0xF0 v m make_code ca phm . 13.8 Xy dng chng trnh Gt bit 2 ca Switch3 ln ON gn in tr ko ln cho chn CLOCK v DATA ca bn phm PS/2 13.8.1 Khi to ngt ngoi Code: void init_ext_int0(void) { INTCONbits.INT0IE = 1; INTCONbits.INT0IF = 0; INTCON2bits.INTEDG0 = RB0/INT0 TRISBbits.TRISB0 = 1; TRISBbits.TRISB1 = 1; }

// set external interrupt0 // clear external interrupt0 flag 0;// interrupt when appear an falling edge on // set input for CLOCK pin // set input for DATA pin

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13.8.2 X l ngt Phn chnh ca bi thc hnh ny l ly cho c d liu truyn ln t bn phm. Qu trnh dch tng bit ly d liu 8 bit trong chui 10 bit c hin thc trong hm phc v ngt ngoi INT0. Code: #pragma code #pragma interrupt high_isr void high_isr(void) { if (INTCONbits.INT0IF) { INTCONbits.INT0IF = 0; count_bits ++; if (count_bits == 1) ps2_scan_code = 0; if (count_bits >1 && count_bits < 10) { ps2_scan_code = ps2_scan_code >> 1; if (PS2_DATA == 1) ps2_scan_code |= 0x80; parity ^= PS2_DATA; } if (count_bits == 12) { scan_code = ps2_scan_code; ps2_scan_code = 0; parity = 0; } } } Bin count_bits dng m s bit gi v, khi count_bit_input = 11 ta s c c d liu scan_code t bn phm truyn ln. Bn s phi x l phn loi y l m make_code hay break_code, c c nhn km vi phm Shift hay Caps Lock hay khng chuyn sang m ASCII cho k t c nhn. 13.9 Download Code mu

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Bi 18 : Graphics LCD 128x64 14.1 Gii thiu GLCD 128x64 Graphic LCD c s dng trn mch BKIT PIC l loi LCD chm, khng mu, c phn gii 128x64 tc 8192 chm. GLCD c thit k iu khin c tng chm, nn c th dng hin th bt k k t hay hnh nh no. Vi mi chm tng ng mt bit d liu, GLCD 128x64 cn 8192 bits RAM hay 1024 bytes RAM hin th ton mn hnh. Loi GLCD YM12864J s dng 2 chip iu khin KS0108 rt ph bin ca Samsung, mi chip c 512 bytes RAM. Do , n tng t nh 2 LCD 64x64 ghp li vi nhau.

Hnh 15 1 GLCD 128x64

14.1.1 Chc nng cc chn ca GLCD 128x64 Chc nng cc chn:

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Cc chn t 4 n 17 c kt ni trc tip n vi iu khin. Cc chn cn li c kt ni ty theo chc nng tng ng ca n. Chn EN Khi thc hin mt qu trnh giao tip vi GLCD, ban u, chn EN c ko xung thp. Trong khi , cc chn iu khin khc c thit lp. Sau khi thit lp xong, chn EN c kch ln mc cao cho php tn hiu. Sau khong thi gian cn thit cho qu trnh hon tt, chn EN li c ko xung thp sn sng cho mt qu trnh khc. Chn RS v RW Hai chn ny c kt hp thit lp cho cc thanh ghi ca GLCD theo bng sau:

Chn CS1 v CS2 Chn chip iu khin GLCD KS0108 giao tip, tch cc mc cao. 14.1.2 T chc b nh RAM Chip iu khin GLCD KS0108 ch c mt loi b nh l RAM, khng c b nh cha b font CGROM hay cha m font t to CGRAM nh ca Text LCD. D liu ghi vo RAM s c hin th trc tip trn GLCD. Mi chip KS0108 c 512 bytes RAM tng ng vi 4096 chm trn mt na (64x64) LCD. RAM ca KS0108 c truy cp theo tng byte, ngha l mi ln vit mt gi tr vo mt byte no trn RAM ca GLCD, s c 8 chm b tc ng, 8 chm ny nm trn cng 1 ct. Do , 64 dng GLCD c chia thnh 8 pages, mi page c cao 8 bit v rng 128 ct (tnh c 2 chip). S b tr RAM:

Hnh 15 2 S b tr RAM ca GLCD 128x64

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Vi mi chip KS0108, RAM chia thnh 8 page, mi page bao gm 64 ct, mi ct bao gm 8 chm. Cc page c gi l a ch X, mang gi tr t 0 n 7, X = 0 tng ng vi page 0 v tng t. Cc ct c gi l a ch Y, ct u tin c gi tr Y = 0 v ct cui cng c gi tr Y = 63. Mi ct l mt byte RAM, D0 n D7, vi D0 tng ng im trn cao v D7 tng ng im bn di. Cc lnh di chuyn c h tr theo cp a ch X, Y. Minh ha hin th k t a trn GLCD:

Hnh 15 3 K t "a" trn GLCD Nh hnh trn, k t a c xc nh bng cch ghi d liu vo X = 0 v Y = 0...7 theo bng sau:

Hnh 15 4 D liu RAM cho k t "a" Gi tr Data l cc gi tr cn np cho vng RAM tng ng. 14.1.3 Cc lnh ca GLCD 128x64 Bng lnh

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1. Lnh hin th ON/OFF D liu c hin th ln mn hnh khi bit D (DB0) bng 1 v ngc li khi D bng 0. Khi D bng 0, d liu vn tn ti trong DDRAM. Lp trnh: RW = 0 RS = 0 Opcode = 0x3E + D (D = 0:1) 2. Hin th Start Line Chn mt dng no ca RAM lm dng u tin c hin th ln, ngha l cun hnh nh trong RAM ln mt khong LOffset, vi LOffset c gi tr t 0 n 63. Phn b che khut khi cun s c hin th tip ngay bn di. V d vi LOffset = 20:

Hnh 15 5 Cun ln 20 dng Lp trnh: RS = 0 RW = 0 Opcode = 0xC0 + LOffset 3. Thit lp trang (a ch X)

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Thit lp a ch X truy xut RAM. Lp trnh: RS = 0 RW = 0 Opcode = 0xB8 + X 4. Thit lp a ch Y Thit lp a ch Y truy xut RAM. Lp trnh: RS = 0 RW = 0 Opcode = 0x40 + Y 5. c trng thi c trng thi ca GLCD, ch yu kim tra bit BUSY (bit 7). Lp trnh: RS = 0 RW = 1 6. Ghi d liu hin th Ghi d liu vo RAM ti a ch X, Y. Sau khi ghi xong, gi tr Y s t ng c tng ln 1 n v, chuyn sang ct tip theo hoc tr v ct u tin, tc Y = 0. Lp trnh: RS = 1 RW = 0 7. c d liu hin th c d liu t RAM ti a ch X, Y. Sau khi c xong, gi tr Y s t ng c tng ln 1 n v, chuyn sang ct tip theo hoc tr v ct u tin, tc Y = 0. Lp trnh: RS = 1 RW = 1

14.2 Xy dng chng trnh 14.2.1 Khi to graphic LCD Qu trnh khi to c thc hin nh sau: Khi to cc chn lin kt vi glcd(thit lp input/output). Chn chip iu khin th nht. Thit lp chn RS ch ghi lnh. Gi lnh bt mn hnh (0x3F). Gi lnh thit lp a ch Y (0x40 + Y). Gi lnh thit lp a ch X (a ch trang) (0xB8 + X). Gi lnh chn dng no trong RAM hin th ln. Lm tng t bc th 2 cho chip th 2.

Tng ng vi tng lnh trn trong chng trnh nh sau: Code:

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glcd_write_byte(GLCD_ON_DISPLAY); glcd_write_byte(GLCD_SET_Y_ADDR); glcd_write_byte(GLCD_SET_PAGE); glcd_write_byte(GLCD_START_LINE); Vi cc tham s truyn vo c gi tr nh sau: Code: #define #define #define #define GLCD_ON_DISPLAY 0x3F GLCD_START_LINE 0xC0 GLCD_SET_PAGE 0xB8 GLCD_SET_Y_ADDR 0x40 // // // // DB0: turn 11XXXXXX: 10111XXX: 01YYYYYY: display set lcd set lcd set lcd on start line page (X) address Y address

14.2.2 Ghi d liu ln GLCD Hm ghi d liu(mt byte) c th vit nh sau: Code: GLCD_CTRL_PORTbits.GLCD_CTRL_RW = 0;// ch ghi GLCD_DATA_PORT = abyte; // ghi d liu GLCD_CTRL_PORTbits.GLCD_CTRL_E = 1; // sau khi ghi bt chn EN ln 1 cho php tn hiu _nop();_nop();_nop(); GLCD_CTRL_PORTbits.GLCD_CTRL_E = 0;// cho chn EN xung 0 li chun b cho ln thit lp tip theo _nop();_nop();_nop(); Chi tit c th v qu trnh xut d liu ln GLCD cc bn c th tham kho chng trnh mu km theo. 14.3 Download Code mu

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Bi 19 : Giao tip SD Card bng SPI 15.1 Gii thiu tng quan v Sdcard 15.1.1 S lc v SD card

Hnh 18 18.1 Cc loi SD Card Secure Digital (SD) Card l b nh flash tch hp cao vi kh nng truy xut tun t v ngu nhin. Vi tc truyn nhn d liu nhanh v n nh, kch thc nh gn, kh nng lu tr cao t 4MB n 2GB, SD thch hp cho cc thit b k thut s cm tay nh my nghe nhc, in thoi di ng, PDA, my quay phim, chp nh 15.1.2 S khi ca SD card

Hnh 18 18.2 S khi ca SD Card

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15.1.3 S chn

15.1.4 Cc thanh ghi bn trong

15.1.5 Chun giao tip vi SD card SD Card h tr 2 ch giao tip l ch SD Card v SPI. Host (h thng ch - vi iu khin) c th chn mt trong hai ch ny thc hin giao tip vi SD Card. Ch SD Card h tr 2 ch con l 1-bit v 4-bit, tc truyn d liu nhanh. Ch SPI tuy c tc thp hn nhng d s dng v c h tr trong hu ht cc h thng vi iu khin. Trong ti liu ny, chng ta s s dng SPI giao tip vi SD Card.

15.2 Gii thiu v FAT 15.2.1 Tng quan FAT FAT (File Allocation Table Bng cp pht tp tin) l kin trc h thng tp tin c s dng cho my tnh v hu ht cc loi th nh. c pht trin bi Microsoft t nm 1976. FAT qun l b nh bng cch chia nh b nh (sector, cluster) v nh du cc khi nh bng cc bit a ch. Mt sector cha 512 byte b nh. Mt cluster cha nhiu sector. S sector

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trong

mt

cluster

nh

do

ngi

dng

chn

lc

nh

dng

nh.

ch mc nh mt cluster cha 8 sector. Khi lu tr mt file, FAT cp pht mt hoc nhiu cluster c tng kch thc khng nh hn kch thc file . V d file c kch thc 5kB s c cp pht 2 cluster (8 sector/cluster) lu tr. Nu s sector trong mi cluster cng ln s gy nhiu lng ph b nh, ngc li nu s ny cng nh th h thng hot ng cng chm. Cc phin bn FAT l FAT12, FAT16, FAT32. im khc nhau c bn gia cc phin bn l v gii hn qun l b nh. FAT12 dng 12 bit nh du a ch cc cluster, nn c th qun l gn 212 cluster (tr mt s a ch nh du cc vng c bit). Tng t FAT16 dng 16 bit, FAT32 dng 28 bit nh du a ch. 15.2.2 Cu trc phn vng FAT Mt h thng file FAT gm 4 phn: 1. Reserved sectors: Nm v tr u tin (sector 0) l Boot sector (tn y l Partition Boot Record). Sector ny cha mt vng gi l BIOS Parameter Block (vi mt s thng tin ca h thng file, chi tit v kiu file, v con tr ti cc phn khc) v thng cha boot loader code ca h iu hnh. Tng s Reverved sector cng c lu trong mt trng ca Boot sector. Nhng thng tin quan trng ca Boot sector mt cu trc gi l Drive Parameter Block trong DOC v OS/2. Ring FAT32 c thm mt File System Information Sector (sector 1) v mt Backup Boot Sector (sector 6). 2. FAT Region: Gm hai bng, l bn ca vng Data Region, cho bit nhng cluster no c dng. 3. Root Directory Region: y l Directory Table, cha thng tin v file v th mc trong th mc gc (root directory), ch c trn FAT12 v FAT16. 4. Data Region: y l ni thc s file v th mc c lu tr v chim hu ht dung lng ca phn vng a. FAT32 ly cluster u tin ca Data Region lm Root Directory Table. 15.2.3 Bng cp pht tp tin Phn vng b nh c chia nh thnh nhng phn nh k nhau, c kch thc bng nhau gi l cluster. Kch thc ca cluster thng t 2kB n 32kB, ph thuc vo kiu FAT, kch thc phn vng b nh v la chn ca ngi dng. Mi file chim mt hoc nhiu cluster ty thuc vo kch thc ca file ; nh vy, mt file c cha bi mt dy cc cluster to thnh mt danh sch lin kt. Cc cluster ca mt file khng nht thit phi lin k nhau, iu ny thng gy ra tnh trng phn mnh (fragmented). Bng cp pht tp tin FAT l mt danh sch cc mc (entry) v nn bn ca tng cluster trn phn vng a. Mi entry cha cc thng tin: s ca cluster tip theo trong dy cc cluster entry nh kt thc ca dy cluster (end of clusterchain EOC) entry c bit nh du mt cluster li (bad cluster) entry c bit nh du cluster khng dng c zero nh du cluster cha dng

Kch thc FAT entry khc nhau mi phin bn. FAT12 v FAT16 dng 12 v 16 bit cho mi entry. Trong FAT32, mi entry l 32 bit, nhng thc s ch dng 28 bit, 4 bit cao d tr (khng dng, thng l 0). 15.2.4 Directory table

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Mi file/directory (cng hiu l mt folder) khi lu tr c biu th l mt entry 32-byte trong bng Directory Table. Mi entry ghi: tn, thuc tnh (attributes: archive, directory, hidden, read-only, system and volume), ngy to lp, a ch ca cluster d liu u tin, v kch thc ca file/directory. Tt c cc Directory Table u c cha trong vng Data Region (tr FAT12 v FAT16, Root Directory Table chim mt vng ring gi l vng Root Directory Region). M t mt Directory entry (c Root Directory v subdirectory):

15.3 Gii thiu b th vin MDD SD card giao tip thng qua SPI, chng ta c th lm tt c cc bc t cu hnh SPI cho PIC, sau gi lnh t vi iu khin xung SD card ri ch tn hiu tr v, c master boot record, boot sector, c ghi FAT Vi cch lm ny i hi bn tn nhiu thi gian hn xy dng cc hm API giao tip vi SDcard nhng bn s nm c nhiu kin thc hn v SDcard. Ngoi ra cn mt cch khc na lm l s dng th vin cc hm c sn trn mng s dng nh vy chng ta s tn t thi gian hn cho vic vit cc hm giao tip th nh v tp trung hn vo xy dng ng dng s dng SD card. MDD l th vin cha cc hm v thit lp giao tip vi SD card,nm trong b th vin y h tr cc chc nng gm SD card, mTouch, GraphicLCD, USB, audio do Microchip cung cp v c t tn l Microchip solutions. y chng ti tp trung vo cch s dng th vin MDD vo giao tip vi SD card bng SPI. 15.3.1 Hng dn s dng MDD y l mt b th vin ca Microchip cung cp c th chy trn cc dng PIC 8 bit (PIC18F), PIC 16bit (PIC24F, PIC24H, dsPIC30) v PIC 32bit (dsPIC33) nn th vin cng kh ln, i hi b chng trnh ca vi iu khin s dng cng phi nhiu, c th nu s dng th vin v ch c th c file t SDcard th cn gn 22000 bytes b nh chng trnh lu tr(ch tnh khng gian lu tr cho code chng trnh ng dng t vit) v s dng ton b chc nng ca th vin (c th c ghi file, format th nh, tm kim file, to xa qun l th mc, s dng cc hm m rng pgm, s dng c hm Fsfprintf, h tr th nh nh dng FAT32) th cn gn 35000 bytes b nh chng trnh. l thng tin do Microchip cung cp nhng thc th s dng th vi vi iu khin ch c 32KB b nh chng trnh th hon ton khng th s dng c b th vin(tr ch ch c file) m vi iu khin PIC18F4520 ch c 32KB b nh chng trnh nn chng ti chn mt chip khc cng dng vi vi iu khin l vi iu khin PIC18F4620 vi b nh chng trnh l 64KB, nhng vn cn mt vi chc nng ph m chng ti b khng s dng thu gn chng trnh sau khi bin dch, nn nu bn mun s dng ton b chc nng ca th vin th nn chn vi iu khin c b nh chng trnh 96KB tr ln.

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Hnh 18-3 Chi tit s dng b nh chng trnh cho th vin MDD

Hnh 18-4 Cc tnh nng c la chn ca th vin Mun b bt chc nng no ca th vin chng ta cn phi tm v kha tt c cc dng code define cho tnh nng (vd #ifdef ALLOWS_DIRS #endif). Bc 1: To 1 project mi, sau vo trang ca Microchip download xung th vin Microchip Solutions(hoc c sn trong a CD km theo) , trong bao gm lun c th vin MDD. Vo th mc Microchip Solutions chp th mc MDD File System v th mc Microchip vo th mc cha project. Sau vo th mc MDD File System xa ht nhng file khng cn thit tr th mc PIC18F, tng t trong th mc Microchip chng ta ch li th mc PIC18 salloc v th mc Include, trong th mc Include chng ta cng xa ht v ch li nhng file .h trong th mc ny v th mc PIC18 salloc,MDD File System. Tip theo chng ta include nhng file sau vo project vi ng dn ./ l th mc m cha project. .\Microchip\MDD File System\FSIO.c .\Microchip\MDD File System\SD-SPI.c .\Microchip\PIC18 salloc\salloc.c .\MDD File System-SD Card\PIC18F\Fsconfig.h .\MDD File System-SD Card\PIC18F\HardwareProfile.h .\Microchip\Include\MDD File System\FSIO.h .\Microchip\Include\MDD File System\SD-SPI.h .\Microchip\Include\MDD File System\FSDefs.h

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.\Microchip\Include\PIC18 salloc\salloc.h .\Microchip\Include\Compiler.h .\Microchip\Include\GenericTypeDefs.h

Hnh 18-5 Project sau khi thm cc file header File tmp.c l file cha hm main do chng ta t vit. Sau vo tab Project Build Options Project, chn Include Search Path, chn New sau thm vo cc ng dn nh trn.

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Hnh 18-6 Thm ng dn cho project Bc 2: Thit lp buffer c v ghi, buffer cho FAT M file linker tng ng vi vi iu khin PIC ang s dng( y l file 18f4620.lkr ), ri chnh sa li vi ni dung nh sau

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Hnh 18-7 Chnh sa file linker cho project Bc 3: Thit lp b nh cache v xung clock Thit lp b nh cache Trong file Fsconfig.h cu hnh sn b nh cache s dng l 512bytes thng qua cu lnh nh ngha Code: #define MEDIA_SECTOR_SIZE 512 Nu bn mun thay i b nh ca cache th ch cn chnh sa trong cu lnh ny nhng nh l b nh cache l bi s ca 512.Ngoi ra cn mt s thit lp chc nng khc nh bt/tt chc nng ghi, tm file u c trong file FSconfig.h cc bn c th t c tm hiu thm. Thit lp xung clock cu hnh xung clock bn m file HardwareProfile.h tm n dng lnh define sau Code: #define GetSystemClock() 20000000 // System clock frequency (Hz)

y vi iu khin ang c cu hnh s dng xung tn s 20MHz, v ty vo nhu cu s dng cc bn c th thay i con s ny.

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Bc 4: Thit lp cc chn giao tip v cc thanh ghi ca ch SPI Trong th vin ny ca Microchip ch h tr cho mt s con PIC18F (PIC18F87J50, PIC18F8722, PIC18F46J50), ton b PIC24F,PIC32F v dsPIC.Cho nn s dng cho nhng con PIC khc(v d l PIC18F4620) th cn phi chnh sa thm mt s file sau. Trong file HardwareProfile.h bn thm vo trong mc define dnh cho PIC18F nhng dng nh ngha sau Code:

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#elif defined PIC18F4520_PIM #define USE_PIC18 #define USE_SD_INTERFACE_WITH_SPI #define INPUT_PIN 1 #define OUTPUT_PIN 0 #define USE_SD_INTERFACE_WITH_SPI #define TRIS_CARD_DETECT #define CARD_DETECT #define TRIS_WRITE_DETECT #define WRITE_DETECT // Chip Select Signal #define SD_CS #define SD_CS_TRIS // Card detect signal #define SD_CD #define SD_CD_TRIS // Write protect signal #define SD_WE #define SD_WE_TRIS // TRIS #define #define #define TRISBbits.TRISB4 PORTBbits.RB4 TRISDbits.TRISD7 PORTDbits.RD7 // Input

// Input

PORTAbits.RA5 TRISAbits.TRISA5

PORTBbits.RB4 TRISBbits.TRISB4

PORTDbits.RD7 TRISDbits.TRISD7

pins for the SCK/SDI/SDO lines SPICLOCK TRISCbits.TRISC3 SPIIN TRISCbits.TRISC4 SPIOUT TRISCbits.TRISC5

// Latch pins for SCK/SDI/SDO lines #define SPICLOCKLAT LATCbits.LATC3 #define SPIINLAT LATCbits.LATC4 #define SPIOUTLAT LATCbits.LATC5 // Port #define #define #define pins for SCK/SDI/SDO lines SPICLOCKPORT PORTCbits.RC3 SPIINPORT PORTCbits.RC4 SPIOUTPORT PORTCbits.RC5

// Registers for the SPI module you want to use #define SPICON1 SSPCON1 #define SPISTAT SSPSTAT #define SPIBUF SSPBUF #define SPISTAT_RBF SSPSTATbits.BF #define SPICON1bits SSPCON1bits #define SPISTATbits SSPSTATbits #define SPI_INTERRUPT_FLAG #define SPIENABLE PIR1bits.SSPIF SSPCON1bits.SSPEN

// Will generate an error if the clock speed is too low to interface to the card #if (GetSystemClock() < 400000) #error System clock speed must exceed 400 kHz #endif V trc bn cn phi nh ngha cc nhn PIC18F4520_PIM bng cch phn nh ngha nhn cho cc con PIC khc bn thm vo on code sau Code:

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#elif defined(__18F4620) #define DEMO_BOARD PIC18F4620_PIM #define PIC18F4620_PIM

Bc 5: Cu hnh b nh Trong MPLAB IDE, chn Project Build Options Project, chn th MPLAB C18 ri chn Memory Model trong Categories v thit lp nh sau: Code model : Small code model Data model : Large code model Stack model : Multibank model

Hnh 18-8 Cu hnh Memory Model Cc bc thit lp s dng hon tt, by gi cc bn c th to 1 file source ca mnh v s dng cc hm c sn trong th vin giao tip vi SDcard.

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Hnh 18-9 Chng trnh mu 15.3.2 Cc hm trong th vin FSInit Initializes the card,loads the master boot record(partition information),loads the boot sector and updates the parameters passed into it with its information FSfclose Updates the file information, writes the remaining entry in and frees the RAM from the heap that was used to hold the information about the file.This also updates the time-stamp information for thr file. FSfeof Verifies if the end of the file has been reached FSfopen Allocates space in the heap for file information.If the file being opened already exist, Fsfopen can open it so that the data would be appended at the end of the line, erase it and create a new file qith the same name to be written to,or simply open it for reading.If the file does nont exist, Fsfopen can creat it. This function then returns a pointer to the tructure in the heap that contains information for this file FSfread Reads information from an open file to a buffer. The number of bytes written can be specified by its parameters. If Fsfread is called consecutively on the same open file, the read will continue from the place it stopped after the previous read. This function returns the number of data objects read Fsfseek Changes the position in a file. When a user calls FSfseek, they specify the base address to set, which can either be at the beginning or end of the file, or at the current position in the file. The user also specifies an offset to add to the base (note that if the base address is at the end of the file, the offset will be subtracted). Hence, if FSfseek is called with the base set to the beginning of the file and a specified offset of 0, the position would be changed to the first byte of the file. Fsftell Returns the current position in the file. The first position in the file is the first byte in the first sector of the first cluster, which has the value 0. Hence, if a file was

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created and 2000 bytes were written to it, FSftell would return the number 1999 if it was called. Fsfwrite Writes information from a buffer to an open file. The algorithm it uses reads a sector from the data region of the disk to SRAM, modifies the relevant bytes and then writes the sector back to the disk. Because each FSfwrite call reads the data first, the ability to open multiple files at a time is supported. This also means that writing data in larger blocks takes less time than writing the same data in smaller blocks as fewer sector reads and writes will be needed. Fsremove Searches for a file based on a filename parameter passed into it. If the file is found, its directory entry is marked as deleted and its FAT entry is erased. Fsremovepgm Deletes the file identified by a given filename. If the file is opened with FSfopen, it must be closed before calling FSremovepgm. The filename must be specified in ROM. This function is necessary only on the PIC18 architecture. Fsfopenpgm Opens a file on the SD card and associates an FSFILE structure (stream) with it using arguments specified in ROM. This function is necessary only on the PIC18 architecture. FSrename Changes the name of a file or directory. If the pointer passed into this function is NULL, the name of the current working directory will be changed. Fsrewind Resets the position of the file to the beginning of the file. Fsmkdir Creates a new subdirectory in the current working directory. Fschdir Changes the current working directory to the one specified by the user. FSrmdir Deletes the specified directory. The user may also choose to specify whether subdirectories and files contained within the deleted directory are removed. If the user does not permit the function to delete subdirectories, it fails if the user attempts to delete a non-empty directory. Fsgetcwd Returns the name of the current working directory to the user. FindFirst Locates files in the current working directory that meet the name and attribute criteria. A SearchRec Structure Pointer will be passed into the function. Once a file is located, the file-name, file size, create time and date stamp, and attributes fields in the SearchRec structure will be updated with the correct file information. FindFirstpgm Operates in the same manner as the FindFirst function, except the name criteria for the file to be found will be passed into the function in ROM. This function is necessary only on the PIC18 architecture. FindNext Locates the next file in the current working directory that matches the criteria specified in the last call of FindFirst or FindFirstpgm. It will then update the SearchRec structure provided by the user with the file information. Fsformat Erases the root directory and file allocation table of a card. The user may also call the function in a mode that causes it to create a new boot sector based on the information in the master boot record. Fsfprintf Writes a formatted string to a file. It automatically replaces any format specifiers in the string with dynamic values from variables passed into the function. Integer promotion must be enabled in the build options menu when using this function with the PIC18 architecture. SetClockVars Used in user-defined Clock mode to manually set the current date and time. This date and time would be applied to files as they are created or modified.

15.4 Xy dng chng trnh 15.4.1 Kt ni phn cng

Hnh 18-10 S kt ni Sdcard V SDcard hot ng in p 3V3 m tn hiu ra ca vi iu khin l 5V nn cc chn SDI,SDO,SS,SCK c gn thng qua cc in tr chia p xung 3V3 cho ph hp vi giao tip SDcard.

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15.4.2 Chng trnh mu Code: 1 #include <p18f4520.h> 2 #include <FSIO.H> 3 void blocking(void) 4 { 5 while (1); 6 } 7 void main(void) 8 { 9 FSFILE *file1; 10 unsigned char txt[] = "Giao tiep SDcard!!"; 11 while (!MDD_MediaDetect()); 12 while(!FSInit()); 13 file1 = FSfopenpgm("file_test_1.txt","w+"); 14 if (file1 == NULL) 15 blocking(); 16 if (FSfwrite((void*)txt,1,18,file1) != 18) 17 blocking(); 18 if (FSfclose(file1) != 0) 19 blocking(); 20 while (1); 21 } Gii thch cc lnh: Dng Dng Dng Dng Dng Dng Dng Dng Dng Dng 2: include file header chnh ca th vin. 36: to hm blocking h thng nu c li. 9: khai bo con tr s tr n file cn x l. 10: khai bo chui s c ghi vo file. 11: i tn hiu bo c th nh thng qua chn card dectec. 12: khi to th nh bt u giao tip vi th nh. 13: khi to cho file, t tn file , truyn vo i s cho php ghi ln file. 1415: kim tra c khi to c file hay khng. 1617: ghi chui vo file. 1819: ng file

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Hnh 18-11 Kt qu ca chng trnh 15.5 Download Code mu

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