Design with PLD (Thit k phn cng vi vi mch logic kh trnh)

Bi Thc hnh 1: Lm quen vi Xilinx ISE v ngn ng m t phn cng VHDL Ni dung: 1.1. Dng VHDL thit k v vit Testbench m phng kim tra mch so snh Test sau y:

Hnh 1.1. S khi mch Test 1.2. Thit k v vit Testbench m phng kim tra mch MUX 2-to-1 vi s khi v bng chn tr Hnh 1.2. Lu cc knh d liu u vo w0, w1 v u ra f c rng 8 bits.

Hnh 1.2. Mch MUX 2-1 1.3. Thc hin mch MUX 4-to-1 bng cch s dng 2 khi mch MUX 2-to-1 c thit k Bi 1.3 (cc knh d liu u vo c rng 8 bits), s khi mch MUX 4-to-1 c cho Hnh 1.3.

Hnh 1.3. Mch MUX 4-to-1 c xy dng t mch MUX 2-to-1

1

1.4. Thc hin DFF vi xung clock tch cc theo sn ln bng VHDL, theo s khi cho Hnh 1.4.

Clk Hnh 1.4. S khi DFF 1.5. S dng DFF thc hin Bi 1.4 v cc cng logic AND v XOR ph tr thit k mt b m 4-bit (4-bit counter) theo s mch Hnh 1.5. Trong : U1, U3, U5, U7 l cc cng AND 2 ng vo U2, U4, U6, U8 l cc cng XOR D0, D1, D2, D3 l cc u vo ca DFF0, DFF1, DFF2, DFF3 tng ng a, b, c l cc tn hiu ni b bn trong Q3, Q2, Q1, Q0 l tn hiu ra biu din ni dung m Carry l c bo trn b m Xung clock Clk tch cc sn ln Yu cu: Thc hin mch bng VHDL v vit testbench tng ng kim tra thit k.

D0

U2 U1 DFF0
a

D1

U4 U3 DFF1
b D2

U6 U5 DFF2

D3

U8 U7 DFF3 Clk Carry

Vit v np bo co Lab (np bn mm v bn in): 1, mi nhm vit chung 1 bn bo co (nhm ti a 3 SV, t chn thnh vin, thnh vin c th thay i cc bui lab khc nhau); 2, nh dng bo co: MS Word (97-2003, .DOC) hoc nh dng PDF, paper size A4, nh s trang, trang u tin ghi tn cc thnh vin trong nhm v lp, tn bi Lab; 3, qui nh v tn file bo co: fpga-report-labX-studentnames.doc hoc fpga-reportlabX-studentnames.pdf, trong X l s th t bi lab v studentnames l tn (first name) cc thnh vin ca nhm; v d: fpga-report-lab1-Tung-Huy-Thien.doc 4, ni dung bo co bao gm: + m t s lc yu cu thit k (c th trnh by s khi, bng chn tr, cc s my trng thi FSM nu c) + code VHDL ca khi mch s c thit k / thc hin + bng kt qu tng hp sau khi chy Synthesize (Project Status, Device Utilization Summary) + code VHDL ca Testbench c dng kim tra v m phng mch + dng sng m phng chp t chng trnh m phng ca Xilinx ISE + cc nhn xt, kt lun (nu c) 5, {bn mm file bo co + ton b file/folder cha code VHDL} c nn li thnh 1 file .ZIP duy nht v email n a ch: <thang143@gmail.com> trc 12h tra ca ngy thc hin bi Lab (th Nm hng tun), cch t tn file .ZIP tng t cch t tn file bo co .DOC/.PDF 6, ng thi bn in (bn cng) ca file bo co cng phi c in ra v np (cho GV) ti Vn phng khoa TVT (Khu C, tng 1) trc 12h tra cng ngy (lu : bn in c th in trn 1 hay c 2 mt giy A4 u c, ch cn bm ghim khng nht thit phi ng gy hay ba gng) 7, bo co ca nhm l hp l khi np c bn cng (bn in) v bn mm! 8, mi s chm tr khi np bn cng hoc bn mm ca bo co s b tr im: tr 1 ting tng ng 1 im tr, sau 15h cng ngy s khng chp nhn bo co, 9, mi s sao chp bo co, code VHDL, dng sng gia cc nhm s b tr im hoc b im khng (0) ty theo tng trng hp c th; lu hnh thc tr im ny p dng cho tt c cc nhm c ni dung bo co l sao chp ca nhau.