Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP.

HCM BI TP C LI GII PHN 2 MN K THUT S

B mn in t i Hc Bch Khoa TP.HCM Bi 1 Cho mach logic nh hnh ve. Khao sat dang tn hieu Y, Z, T theo tn hieu A, B, C. Biet rang gia tr ban au ngo ra Q cua chot D va Flip Flop D eu bang 1.

EN

CK C

T=ZC=ZC

A B C Y Z T

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

Bi 2 S dung JK.FF co xung clock kch theo canh len, ngo vao Preset va Clear tch cc logic 0 (tch cc thap), thiet ke b m noi tiep (bo em bat ong bo) 3 bit QAQBQC (QC la LSB) co gian o trang thai nh hnh ve. QAQBQC

111 110 001 000

101

QA QB 1 0 1 1 1 1 0 0 0 0 0 1

QC 1 0 1 0 1 0

Z = QA QB = QA + QB (Tch cc thap)

T gian o trang thai ta co ay la bo em len co day em tuan hoan: 101, 110, 111, 000, 001 QC QB QA (msb)

1 1 J CK 1 K Cl 1 Q 1 Pr Q 1 J CK K Cl Q 1 Pr Q 1 J CK K Cl 1 Q Pr Q

Bi 3 Xac nh gian o trang thai cua he tuan t gom 1 ngo vao X va 2 T-FF Q1, Q0 nh hnh ve Q0 Q1

CK CK

CK

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

T s o ta co: T0 = X + Q1 va T1 = (X + Q1) Q0 Lap bang chuyen trang thai: X Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 T1 1 0 0 1 0 1 0 1 T0 0 0 1 1 1 1 1 1 Q+1 Q+0 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0

Ta co gian o trang thai: Q1 Q0 00

1 1 0, 1 X=0

Q0Q1 10
0, 1

Hoc

00
1 1

X=0

01
0, 1

0, 1

01
0

11
0

10

11

Bi 4 Thanh lap bang chuyen trang thai hoac gian o trang thai cua he tuan t kieu MOORE co 1 ngo vao X va 1 ngo ra Z. Ngo ra Z ch bang 1 khi ngo vao X nhan c chuoi lien tuc 1, 1, 0, 1. Hay rut gon bang trang thai.

Bang trang thai rut gon: TTHT (reset) (1) ( 1, 1 ) (1, 1, 0) (1, 1, 0, 1) A B C D E TTKT X=0 X=1 A B A C D C A E A C Ngo ra 0 0 0 0 1 Hoc TTHT (reset) S0 (1) S1 ( 1, 1 ) S2 (1, 1, 0) S3 (1, 1, 0, 1) S4 TTKT X=0 X=1 S0 S1 S0 S2 S3 S2 S0 S4 S0 S2 Ngo ra 0 0 0 0 1

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

Bi 5 Cho he tuan t co 1 ngo vao X va 2 ngo ra Z1, Z2. He co 4 trang thai A, B, C va D co gian o trang thai nh hnh ve. Vi phep gan trang thai (ma hoa trang thai) A: Q1Q2 = 10, B: Q1Q2 = 00, C: Q1Q2 = 01 va D: Q1Q2 = 11. Hay thiet ke he bang JK_FF va cong logic hoac D_FF va PLA (ch chon 1 trong 2). Biet rang khi xung clock vao co canh xuong he se chuyen trang thai.
0 1

A 01

X=1

B 11
0

1 0

D 10

C 00

X Q1 Q2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Z1 1 0 0 1 1 0 0 1

Z2 1 0 1 0 1 0 1 0

Q+1 Q+2 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0

J1 K 1 J2 K 2 0 X 1 X 1 X X 0 X 0 0 X X 0 X 1 0 X 0 X 1 X X 1 X 1 0 X X 1 X 1

Dung ba K, ta co:

Z1 = Q 1 Q 2 + Q1 Q2 = Q 2 Q 2 D 1 = Q +1 = X Q 1 + Q 1 Q 2 J1 = Q 2 K1 = X J2 = X Q 1

Z2 = Q 2 D2 = Q+2 = X Q1 K2 = X + Q1

* Thit k bng JK-FF v cng: Z1 J1 CK X K1 Q1 Q1 J2 CK K2 Q2 Z2 Q2

CK * Thit k bng D-FF v PLA: PLA X Q1 Q2 Z1 Z2 D1 D2 CK 4 D Q D Q Bng np PLA X 0 0 Q 1 Q2 0 0 1 1 - 0 1 0 1 0 Z1 Z2 D1 D2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

Bi 6 Cho he tuan t co lu o may trang thai (lu o SM, gian o trang thai nh hnh ve). Xac nh phng trnh (ham) trang thai ke cua cac bien trang thai Q+1, Q+2 va phng trnh (ham) ngo ra Z1, Z2.

S0 Z1 X

01 = Q1Q2

Z2 S1 11 S2 10 Z1, Z2
1

X
0

Z1 11

P/trnh ngo ra:

Z1 = Q1 Q 2 + Q 1 Q2 + X Q1 Q2 Z2 = X Q1 Q2 + Q 1 Q 2

P/trnh TTKT:

Q +1 = X Q 1 Q 2 + X Q 1 Q 2 + X Q 1 Q 2 Q +2 = X Q 1 Q 2 + X Q 1 Q 2 + X Q 1 Q 2 + X Q 1 Q 2 + X Q 1 Q 2

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

Bi 7 Mot he to hp co ngo ra Z la so nh phan 4 bit (z3 z2 z1 z0); co chc nang chon 1 trong 4 ma nh phan 4 bit ngo vao: M, N, P hoac Q phu thuoc 2 ngo vao ieu khien x1 va x0. x1 x0 0 0 0 1 1 0 1 1 Z= M= N= P= Q= z3 m3 n3 p3 q3 z2 m2 n2 p2 q2 z1 m1 n1 p1 q1 z0 m0 n0 p0 q0 1 co khai bao s1 s0 0 0 0 1 1 0 1 1 y d0 d1 d2 d3

Viet ma VHDL thc hien mach nay s dung component MUX 4 ENTITY:
ENTITY MUX4 IS PORT (d0, d1, d2, d3: IN STD_LOGIC; s1, s0: IN STD_LOGIC; y: OUT STD_LOGIC); END MUX4;

Gi y: - Moi ngo ra zi chon 1 trong 4 ngo vao mi, ni, pi, qi. - Cac ngo vao va M, N, P, Q va ngo ra Z khai bao kieu STD_LOGIC_VECTOR.

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY cau7 IS PORT (m, n, p, q: IN std_logic_vector(3 downto 0); x1, x0: IN std_logic; z: OUT std_logic_vector(3 downto 0)); END cau7;

ARCHITECTURE structure OF cau7 IS

COMPONENT MUX4 IS PORT (d0, d1, d2, d3: IN STD_LOGIC; s1, s0: IN STD_LOGIC; y: OUT STD_LOGIC); END COMPONENT; BEGIN U0: MUX4 PORT MAP(m(0),n(0),p(0),q(0),x1,x0,z(0)); U1: MUX4 PORT MAP(m(1),n(1),p(1),q(1),x1,x0,z(1)); U2: MUX4 PORT MAP(m(2),n(2),p(2),q(2),x1,x0,z(2)); U3: MUX4 PORT MAP(m(3),n(3),p(3),q(3),x1,x0,z(3)); END structure;

Nguyn Trng Lut BM in T - Khoa in-in T - H Bch Khoa TP. HCM

Bi 8 Mot mach hoan oi mang 2 day (2-input permutation network): co 2 ngo vao a, b; ngo vao ieu khien c va 2 ngo ra x, y. Mach co hoat ong nh sau: - Khi c = 0 th x = a va y = b. - Khi c = 1 th x = b va y = a. Hay viet ma VHDL (s dung phat bieu Process) mo ta hoat ong cua mach.

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY cau8 IS PORT (a, b, c: IN std_logic; x, y : OUT std_logic); END cau8;

ARCHITECTURE behavior OF cau8 IS BEGIN PROCESS (a, b, c) BEGIN IF c = 0 THEN x <= a; y <= b; ELSE x <= b; y <= a; END IF; END PROCESS; END behavior;