Question #1

PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2

! 1 2

Week 11 Tutorial

$nstruction %"1&2'(

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

$nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

Zero ALU result ALU -ut

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

Given the datapath above, what signals would the control unit turn on and off in order to add $r1 to $r2 and store the result in $r7?

Basic approach
12 3igure out the data source4s5 and destination2 22 6eter+ine the path of the data2 "2 6educe the signal values that cause this path7

Question #1 (contd)
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2
$nstruction %"1&2'(

! 1 2

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

a5 .tart with Read 8 Write signals 4at +ost one

$nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

Zero ALU result ALU -ut

can be high at a ti+e52 b5 9hen, +u1 signals along the data path2 c5 :on&essential signals get an X value2

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

.tep ;17 6ata source and destination

6ata starts in register bloc<2 6ata goes to register bloc<2

Question #1 (contd)
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Question #1 (contd)
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Control Unit

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2
$nstruction %"1&2'(

! 1 2 /0 ! 1
Write data

.hift left 2
$nstruction %"1&2'( $nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

! 1 2

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

$nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

Address *e+or, data

Zero ALU result ALU -ut

Zero ALU result ALU -ut

Memory

! 1 2 "

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

*e+or, data register

1 .ign e1tend .hift left 2

.tep ;27 6eter+ine the path of the data

6ata needs to go through the ALU before heading bac< into the register file2

.tep ;"a7 Read 8 Write signals

-nl, RegWrite needs to be high2 PCWrite, PCWriteCond, MemRead, MemWrite, IRWrite would be low2

Question #1 (contd)
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Question #1 (contd)
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2
$nstruction %"1&2'( $nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

! 1 2
$nstruction %"1&2'( $nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

.hift left 2 Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

! 1 2

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! /0 ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

Zero ALU result ALU -ut

! 1

Address *e+or, data Write data

Zero ALU result ALU -ut

Memory

! 1 2 "

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

*e+or, data register

1 .ign e1tend .hift left 2

.tep ;"b7 6ata path signals

*u1es before ALU7 ALUSrcA 1, ALUSrcB ALUOp 001 4Add5 *u1 before registers7 MemToReg 0 002

.tep ;"c7 :on&essential signals

:o writing to /07 PCSource X2 :o reading fro+ +e+or,7 IorD X2

Question #1 (contd)
PCWrite = 0 PCWriteCond = X IorD = X MemRead = 0 MemWrite = 0 MemToReg = 0 IRWrite = 0 PCSource = X ALUOp = 001 ALUSrcA = 1 ALUSrcB = 00 RegWrite = 1 RegDst = 1 :ote7 RegDst rule
high for "&register operations low for 2&register operations

Question #2
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Control Unit

PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2
$nstruction %"1&2'(

! 1 2

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

$nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

Zero ALU result ALU -ut

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

Given the datapath above, what signals would the control unit turn on and off in order to add 100 to the progra+ counter?

Question #2 (contd)
Read > Write signals7
PCWrite high, all others low2
PCWriteCond is X, when PCWrite is high2

Question #2 (contd)
PCWrite = 1 PCWriteCond = X IorD = X MemRead = 0 MemWrite = 0 MemToReg = X IRWrite = 0 PCSource = 0 ALUOp = 001 ALUSrcA = 0 ALUSrcB = 10 RegWrite = 0 RegDst = X

6atapath signals7
ALUSrcA 0 ALUSrcB 2 4100 is an i++ediate value? needs to co+e fro+ the instruction5 PCSource 0

:on&essential signals7
IorD, MemToReg, RegDst

Question #3
PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite Opcode

Question #3 (contd)
Control Unit
PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst

.hift left 2
$nstruction %"1&2'(

! 1 2

Registers Read reg 1 Read reg 2 ! 1 Write reg Write data ! ! Read data 1 Read data 2 A 1

/0

! 1

Address *e+or, data Write data

$nstruction %2)&21( $nstruction %2!&1'( $nstruction %1)&!( Instruction Register

Zero ALU result ALU -ut

Memory

! 1 2 "

*e+or, data register

1 .ign e1tend .hift left 2

Given the datapath above, what signals would the control unit turn on and off in order to load a new instruction?

PCWrite = 0 PCWriteCond = 0 IorD = 0 MemRead = 1 MemWrite = 0 MemToReg = X IRWrite = 1

PCSource = X ALUOp = XXX ALUSrcA = X ALUSrcB = XX RegWrite = 0 RegDst = X

Question #4
What are the following asse+bl, language instructions doing?
sub $t7, $t0, $t1 .ubtract register $t1 fro+ $t0 and placing the result into $t7 itwise A:6 between register $t0 and 1) 411115, with the result placed into register $t7 Arith+etic shift of register $t1 two bits to the right, with the result stored in $t2

Question #5
@ow do ,ou translate the following asse+bl, language instruction into +achine code?
add $t7, $t0, $t1

andi $t7, $t0, 15

R&t,pe instructionA
opcode rs ) rt ) rd ) shamt ) funct ' '

sra $t2, $t1, 2

As a reminder
*$/. register values7
Register 0 4BCero57 value 0 && alwa,s2 Register 1 4Bat57 reserved for the asse+bler2 Registers 2-3 4Bv!, Bv157 return values Registers 4-7 4Ba!&Ba"57 function argu+ents Registers 8-15, 24-25 4Bt!&BtD57 te+poraries Registers 16-23 4Bs!&BsE57 saved te+poraries Registers 28-31 4Bgp, Bsp, Bfp, Bra57 +e+or, and function support Registers 27-287 reserved for -. <ernel

Question #5
add $t7, $t0, $t1

.tep ;17 9he opcode

Arith+etic operations start with si1 0Fs, and have the function identifier at the end2
000000 sssss ttttt ddddd XXXXX 100000

.tep ;27 9he register values

Re+e+ber that $t0 does not translate to register 0 9he te+porar, registers start at register G, so $t0 8, $t1 9 and $t7 15
000000 01000 01001 01111 XXXXX 100000

Question #6
3inal H1a+, Winter 2!127

Question #6

@ow would ,ou convert this to asse+bl, language?

3or the final e1a+, ,ouFll have the list of asse+bl, language co++ands available7

Week 11

a!

"he #ina
0larit,2

destination

9hings to note for the proIect report7

@oora,, no labsA Last proIect de+o7

9hursda,, :ove+ber 2Gth2

9ell us what ,ou learned2

Get up&close and personal

/roIect report7
6ue date7 9uesda,, .ub+ission7 lac<board 6ece+ber "rd

.ections are vital2

$ntroduction
Wh, this proIect?

*ethods
What did ,ou do 4include figures5

Lin< is in 0ourse *aterial folder2

Results
@ow did it go?

6onFt include full Jerilog code2 -nl, include snippets in ,our report that ,ou thin< the 9As should <now about2 Length7 enough to conve, the following topics clearl,K

6iscussion
6id it wor<? What did ,ou learn specificall,? What would ,ou do different?

0onclusion Appendi1
code, sche+atics, etc2