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Vit chng trnh iu khin v m phng h thng dng PLC S7-300 4.1 Nhm lnh logic tip im 4.1.

1 Lnh gn i vi ngn ng STL: C php = <ton hng>

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Ton hng l a ch bit I, Q, M, L, D. Lnh gn gi tr logic ca RLO ti nh c a ch c ch th trong ton hng. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x 1 K hiu: (-) Ch ni dung bit khng b thay i theo lnh. (x) Ch ni dung bit b thay i theo lnh. V d: Thc hin Q4.5 = I2.6 A I2.6 //c ni dung ca I2.6 vo RLO. = Q4.5 // a kt qu ra cng Q4.5. i vi ngn ng dng LAD v FBD: LAD <address> <address> V i Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,D,T,C M t Kim tra bit FBD &

Khi gi tr logic ca bit ti <address> bng 1 th RLO c gi tr 1. Khi gi tr logic ca bit ti <address> bng 0 th RLO c gi tr bng 0. 4.1.2 Lnh thc hin php tnh AND i vi ngn ng dng STL: C php A <ton hng> Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC = 0 lnh s gn gi tr logic ca ton hng vo RLO. Ngc li khi FC = 1. lnh s thc hin php tnh AND RLO vi ton hng v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC x x x 1

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 V du: Thc hin Q8.0 = I0.2 ^ I0.3 A A = I0.2 I0.3 Q8.0 // c ni dung ca I0.2 vo RLO. // And vi ni dung cng I0.3. // a kt qu ra cng Q8.0.

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i vi ngn ng dng LAD v FBD: LAD <address> <address> <address> <.address> Vi: Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,T,C FBD &

Khi gi tr logic hai a ch <address> bng 1 th RLO c gi tr 1. Nu c t nht 1 trong 2 ng vo xung mc 0 th RLO c gi tr bng 0. 4.1.3 Lnh thc hin php tnh AND vi gi tr nghch o i vi ngn ng STL: C php AN <ton hng> Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC = 0 lnh s gn gi tr logic nghch o ca ton hng vo RLO. Ngc li khi FC =1 n s thc hin php tnh AND RLO vi gi tr nghch o ca ton hng v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC x x x 1 V d: Thc hin Q8.0 = I0.2 ^ I0.3 A AN = I0.2 I0.3 Q8.0 //c ni dung ca I0.2 vo RLO. // And vi gi tr nghch o ca I0.3. // a kt qu ra cng Q8.0. FBD <address> <address> &

i vi ngn ng dng LAD v FBD: LAD <address> <address>

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Trong : Thng s <address> V d: - Dng LAD Kiu d liu BOOL Ton hng I, Q, M, L, D, T, C

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Ng ra Q0.0 S mc 1 nu ng vo I0.0 mc 1 v I0.1 mc 0. 4.1.4 Lnh thc hin php tnh OR i vi ngn ng dng STL: C php O <ton hng> Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC = 0 lnh s gn gi tr logic ca ton hng vo RLO. Nu FC = 1 n thc hin php tnh OR RLO vi ton hng v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 V d: Thc hin Q8.0 = I0.2 v I0.3 A O = I0.2 I0.3 Q8.0 LAD <address> <address> <address> <address>. V i : Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,D,T,C FBD

i vi ngn ng dng LAD v FBD:

RLO c gi tr 1 khi c t nht mt trong hai tn hiu ti hai a ch <address> mc 1. RLO c gi tr 0 khi c hai tn hiu ng vo u xung mc 0. 4.1.5 Lnh thc hin php tnh OR vi gi tr nghch o i vi ngn ng dng STL: C php ON <ton hng>

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC=0 lnh s gn gi tr logic nghch o ca ton hng vo RLO. Nu FC=1 n thc hin php tnh OR RLO vi gi tr nghch o ca ton hng v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 V d: Thc hin Q8.1 = I0.2 V I0.3 A I0.2 ON I0.3 = Q8.1 i vi ngn ng dng LAD va FBD: LAD <address> <address> V d: FBD <address> <address>

Ng ra Q8.1 s xung 0 khi ng vo I0.2 mc 0 v I0.3 mc 1. Cc trng thi khc ca hai ng vo I0.2 v I0.3 u lm cho ng ra Q mc 1. 4.1.6 Lnh thc hin php tnh AND vi 1 biu thc i vi ngn ng dng STL: C php A( Lnh khng c ton hng. Nu FC = 0 lnh s gn gi tr logic ca biu thc trong du ngoc sau n vo RLO. Nu FC = 1 n s thc hin php tnh AND gia RLO vi gi tr logic ca biu thc trong du ngoc sau n v ghi li kt qu vo RLO . Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 V d: Thc hin Q4.0 = (I0.2 v I0.3) ^ (I0.4 v I0.5). A( O I0.2 O I0.3 ) A( O I0.4 O I0.5 ) = Q4.0 i vi ngn ng dng LAD v FBD: Lnh c biu din bng cc s tng ng trong LAD v FBD nh sau: Dng LAD

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Dng FBD

4.1.7 Lnh thc hin php tnh AND vi gi tr nghch o ca 1 biu thc i vi ngn ng dng STL: C php AN( Lnh khng c ton hng. Nu FC = 0 lnh s gn gi tr logic ca biu thc trong du ngoc sau n vo RLO. Nu FC = 1 n s thc hin php tnh AND gia RLO vi gi tr nghch ologic ca biu thc trong du ngoc sau n v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 V d: Thc hin Q4.0 = I0.2 ^ (I0.4 V I0.5) A I0.2 AN( ON I0.4 O I0.5 ) = Q4.0 4.1.8 Lnh thc hin php tnh OR vi gi tr nghch o 1 biu thc i vi ngn ng dng STL: C php ON(

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Lnh khng c ton hng. Nu FC = 0 lnh s gn gi tr logic ca biu thc trong du ngoc sau n vo RLO. Nu FC = 1 n s thc hin php tnh AND gia RLO vi gi tr nghch o logic ca biu thc trong du ngoc sau n v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0 V d: Thc hin Q4.0 = I0.2 V (I0.4 V I0.5) A ON ON O ) = I0.2 ( I0.4 I0.5 Q4.0

i vi ngn ng dng LAD v FBD: Tng t nh dng LAD v FBD ca lnh thc hin php tnh OR vi 1 gi tr biu thc. 4.1.9 Lnh thc hin php tnh OR vi gi tr 1 biu thc i vi ngn ng dng STL: C php O( Lnh khng c ton hng. Nu FC = 0 lnh s gn gi tr logic ca biu thc trong du ngoc sau n vo RLO. Nu FC = 1 n s thc hin php tnh OR gia RLO vi gi tr ca biu thc trong du ngoc sau n v ghi li kt qu vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0 Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 V d: Thc hin Q4.0 = I0.2 v (I0.4 v I0.5) A O( AN A ) = I0.2 I0.4 I0.5 Q4.0 Dng LAD:

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i vi ngn ng dng LAD v FBD:

Dng FBD:

4.1.10 Lnh thc hin php tnh EXOR i vi ngn ng dng STL: C php X <ton hng> Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC = 0 lnh ghi gi tr logic ca ton hng vo RLO. Nu FC = 1 lnh s kim tra xem ni dung ca RLO v gi tr logic ca ton hng c khc nhau khng. Trong trng hp khc nhau th ghi 1 vo RLO, ngc li th ghi 0. Ni cch khc lnh s o ni dung RLO nu ton hng c gi tr 1. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 V d: Nu I0.4 ^ I0.5 I0.2 th Q4.0 = 1 AN A X = I0.4 I0.5 I0.2 Q4.0

i vi ngn ng dng LAD: Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Lnh c biu din bng s mch tng ng. V d:

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i vi ngn ng dng FBD: Dang FBD <address> <address> XOR Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,D,T,C

Lnh EXOR kim tra trng thi ca hai tn hiu u vo theo bng s tht. Ng ra trng thi 1 khi 1 v ch 1 trong hai ng vo ln mc 1. V d:

4.1.11 Lnh thc hin php tnh EXNOR i vi ngn ng dng STL: C php XN <ton hng> Ton hng l d liu kiu BOOL hoc a ch bit I, Q, M, L, D, T, C. Nu FC = 0 lnh ghi gi tr logic nghch o ca ton hng vo RLO. Nu FC = 1 lnh s kim tra xem ni dung ca RLO v gi tr logic ca ton hng c ging nhau khng. Trong trng hp ging nhau th ghi 1 vo RLO, ngc li th ghi 0. Ni cch khc lnh s o ni dung RLO nu ton hng c gi tr 0. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 V d: AN A XN = I0.4 I0.5 I0.2 Q4.0

4.1.12 Lnh thc hin php tnh EXOR vi gi tr 1 biu thc i vi ngn ng dng STL: Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 C php X(

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Lnh khng c ton hng. Khi FC = 0, lnh s ghi gi tr logic ca biu thc trong ngoc sau n vo RLO. Nu FC = 1, lnh s o ni dung ca RLO khi biu thc trong du ngoc sau n c gi tr 1. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0 4.1.13 Lnh thc hin php tnh EXNOR vi gi tr 1 biu thc i vi ngn ng dng STL: C php XN( Lnh khng c ton hng. Khi FC = 0, lnh s ghi gi tr logic nghch o ca biu thc trong ngoc sau n vo RLO. Nu FC = 1, lnh s o ni dung ca RLO khi biu thc trong du ngoc sau n c gi tr 0. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 4.2 Nhm lnh tip im c bit 4.2.1 Lnh ghi gi tr logic 1 vo RLO i vi ngn ng dang STL: C php SET Lnh khng c ton hng v c tc dng ghi 1 vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 1 1 0 i vi ngn ng dng LAD v FBD: Lnh khng c th hin. 4.2.2 Lnh ghi gi tr logic 0 vo RLO i vi ngn ng dng STL: C php CLR Lnh khng c ton hng v c tc dng ghi 0 vo RLO. Lnh tc ng vo thanh ghi trng thi nh sau: Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 BR CC1 CC0 OV OS OR STA RLO FC 0 0 0 0 i vi ngn ng dng LAD v FBD : Lnh khng c th hin. 4.2.3 Lnh o gi tr ca RLO i vi ngn ng dng STL: C php NOT Lnh khng c ton hng v c tc dng o ni dung ca RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 1 x i vi ngn ng dng LAD v FBD: LAD FBD

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Lnh NOT c tc dng o gi tr ca RLO. V d: Dng LAD:

Dng FBD:

4.2.4 Lnh pht hin sn ln i vi ngn ng dng STL: C php FP <Ton hng> Ton hng l a ch I, Q, M, L, D v c s dng nh mt bin c ghi li gi tr ca RLO ti v tr ny trong chng trnh. RLO s c gi tr trong vng qut khi c sn ln trong RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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i vi ngn ng dng LAD v FBD: LAD FBD

Vi: Thng s <address> Kiu d liu BOOL Ton hng M t I, Q, M, L, D a ch bit lu tr trng thi tn hiu ca RLO trc

Khi RLO thay i t 0 ln 1 kt qu ca lnh kim tra FB trng thi 1 trong mt vng qut. h thng pht hin c s thay i cnh ln th RLO phi c lu tr trong 1 bit nh FB hoc bit d liu <address>. Nu gi tr RLO trc lu tr trong <address > c gi tr 0 v RLO vng qut hin ti c gi tr 1 th kt qu RLO ca lnh c gi tr 1 trong vng qut. 4.2.5 Lnh pht hin sn xung i vi ngn ng dng STL: C php FN <Ton hng> Ton hng l a ch I, Q, M, L, D v c s dng nh 1 bin c ghi li gi tr ca RLO ti v tr ny trong chng trnh. RLO s c gi tr trong vng qut khi c sn xung trong RLO. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x x 1 i vi ngn ng dng LAD v FBD: LAD FBD

Vi: Thng s <address> Kiu d liu Ton hng BOOL I,Q,M,L,D M t a ch bit lu tr trng thi tn hiu ca RLO trc

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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Khi RLO thay i t 1 xung 0 kt qu ca lnh kim tra FB trng thi trong 1 vng qut. h thng pht hin c s thay i cnh ln th RlO phi c lu tr trong mt bit nh FB hoc bit d liu <address>. Nu gi tr RLO trc lu tr trong <address > c gi tr 0 v RLO vng qut hin ti c gi tr 1 th kt qu RLO ca lnh c gi tr 1 trong vng qut. 4.3 Nhm lnh ghi/xa gi tr cho tip im 4.3.1 Lnh gn c iu kin gi tr logic 1 vo nh i vi ngn ng dng STL: C php S <ton hng> Ton hng l a ch bit I, Q, L, M, D. Nu RLO=1 lnh s ghi gi tr 1 vo nh c a ch trong ton hng. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x 0 i vi ngn ng dng LAD v FBD: LAD FBD

Vi: Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,D M t a ch bit c set

Nu RLO = 1 th a ch c th c t mc 1 v duy tr trng thi ny cho n khi n b reset bng 1 lnh reset. 4.3.2 Lnh gn c iu kin gi tr logic 0 vo nh i vi ngn ng dng STL: C php R <ton hng> Ton hng l a ch bit I, Q, M, L, D. Nu RLO=0, lnh s ghi gi tr 0 vo nh c a ch trong ton hng. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 x 0

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 i vi ngn ng dng LAD v FBD: LAD FBD

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Vi: Thng s <address> Kiu d liu BOOL Ton hng I,Q,M,L,D M t a ch bit c reset

Nu RLO = 1 th a ch c th c t mc 0 v duy tr trng thi ny cho n khi n b reset bng 1 lnh set. 4.4 Nhm lnh so snh s nguyn 16 bit LAD Lnh so snh bng STL TON HNG = =I IN1 I,Q,L,M,D (INT) const IN2 I,Q,M,L,D (INT) const <>I IN1 (INT) IN2 (INT) IN1 (INT) IN2 (INT) IN1 (INT) IN2 (INT) IN1 (INT) IN2 (INT) IN1 (INT) IN2 (INT) I,Q,L,M,D const I,Q,M,L,D const I,Q,L,M,D const I,Q,M,L,D const I,Q,L,M,D const I,Q,M,L,D const I,Q,L,M,D const I,Q,M,L,D const I,Q,L,M,D const I,Q,M,L,D const M T Ng ra s ln mc 1 nu tha: -IN1=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<>IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<=IN2 -Ng vo ln mc 1.

Lnh so snh khng bng Lnh so snh ln hn Lnh so snh nh hn Lnh so snh ln hn hoc bng Lnh so snh nh hn hoc bng

>I

<I

>=I

<=I

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 4.5 Nhm lnh so snh s nguyn 32 bit LAD Lnh so snh bng Lnh so snh khng bng Lnh so snh ln hn Lnh so snh nh hn Lnh so snh ln hn hoc bng Lnh so snh nh hn hoc bng STL TON HNG ==D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const <>D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const >D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const <D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const >=D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const <=D IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const

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M T Ng ra s ln mc 1 nu tha: -IN1=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<>IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<=IN2 -Ng vo ln mc 1.

4.6 Nhm lnh so snh s thc 32 bit LAD Lnh so snh bng Lnh so snh khng bng Lnh so snh ln hn STL TON HNG ==R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const <>R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const >R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const M T Ng ra s ln mc 1 nu tha: -IN1=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<>IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>IN2 -Ng vo ln mc 1.

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Lnh so snh nh hn Lnh so snh ln hn hoc bng Lnh so snh nh hn hoc bng 4.7 Cc lnh ton hc 4.7.1 Nhm lnh lm vic vi s nguyn 16 bit LAD Lnh cng STL +I TON HNG IN1 I,Q,L,M,D (INT) const IN2 I,Q,M,L,D (INT) const OUT I.Q.M.L.D, (INT) const IN1 I,Q,L,M,D (INT) const IN2 I,Q,M,L,D (INT) const OUT I.Q.M.L.D, (INT) const IN1 I,Q,L,M,D (INT) const IN2 I,Q,M,L,D (INT) const OUT I.Q.M.L.D, (INT) const IN1 I,Q,L,M,D (INT) const IN2 I,Q,M,L,D (INT) const OUT I.Q.M.L.D, (INT) const <R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const >=R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const <=R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const

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Ng ra s ln mc 1 nu tha: -IN1<IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1>=IN2 -Ng vo ln mc 1. Ng ra s ln mc 1 nu tha: -IN1<=IN2 -Ng vo ln mc 1.

M T Lnh cng 2 s nguyn 16 bit trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh tr 2 s nguyn 16 bit trong IN 1 v IN 2.Kt qu ct vo OUT. Lnh nhn 2 s nguyn 16 bit trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh chia 2 s nguyn 16 bit trong IN 1 v IN 2. Kt qu ct vo OUT.

Lnh tr

-I

Lnh nhn

*I

Lnh chia

/I

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 4.7.2 Nhm lnh lm vic vi s nguyn 32 bit LAD Lnh cng STL +D TON HNG IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const OUT I.Q.M.L.D, (DINT) const IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const OUT I.Q.M.L.D, (DINT) const IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const OUT I.Q.M.L.D, (DINT) const IN1 I,Q,L,M,D (DINT) const IN2 I,Q,M,L,D (DINT) const OUT I.Q.M.L.D, (DINT) const

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M T Lnh cng 2 s nguyn 32 bit trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh tr 2 s nguyn 32 bit trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh nhn 2 s nguyn 32 bit trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh chia 2 s nguyn 32 bit trong IN 1 v IN 2. Kt qu ct vo OUT.

Lnh tr

-D

Lnh nhn

*D

Lnh chia

/D

4.7.3 Nhm lnh lm vic vi s thc LAD Lnh cng STL +R TON HNG IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const OUT I.Q.M.L.D, (REAL) const IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const OUT I.Q.M.L.D, (REAL) const M T Lnh cng 2 s thc trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh tr 2 s thc trong IN 1 v IN 2. Kt qu ct vo OUT.

Lnh tr

-R

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Lnh nhn *R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const OUT I.Q.M.L.D, (REAL) const /R IN1 I,Q,L,M,D (REAL) const IN2 I,Q,M,L,D (REAL) const OUT I.Q.M.L.D, (REAL) const ABS IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) SIN IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) Cos IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) TAN IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) ASIN IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) ACOS IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) ATAN IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL) SQR IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL)

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Lnh nhn 2 s thc trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh chia 2 s thc trong IN 1 v IN 2. Kt qu ct vo OUT. Lnh ly gi tr tuyt i trong IN. Kt qu ct vo OUT. Lnh tnh sin trong IN. Kt qu ct vo OUT. Lnh tnh cos trong IN. Kt qu ct vo OUT. Lnh tnh tg trong IN. Kt qu ct vo OUT. Lnh tnh arsin trong IN. Kt qu ct vo OUT. Lnh tnh arcos trong IN. Kt qu ct vo OUT. Lnh tnh artg trong IN. Kt qu ct vo OUT. Lnh tnh bnh phng trong IN. Kt qu ct vo OUT.

Lnh chia

Lnh ly gi tr tuyt i Lnh tnh sin Lnh tnh cos Lnh tnh tg Lnh tnh arsin Lnh tnh arcos Lnh tnh artg Lnh tnh bnh phng

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Lnh tnh cn bc 2 SQRT IN I,Q,L,M,D (REAL) OUT I.Q.M.L.D, (REAL)

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Lnh tnh cn trong IN. Kt qu ct vo OUT.

4.8 Nhm lnh chuyn i s BCD thnh s nguyn v ngc li LAD Lnh chuyn s BCD thnh s nguyn 16 bit Lnh chuyn i BCD thnh s nguyn 32 bit Lnh chuyn i s nguyn 16 bit thnh s BCD Lnh chuyn i s nguyn 32 bit thnh s BCD Lnh chuyn i s nguyn 16 bit thnh s nguyn 32 bit Lnh chuyn s nguyn 32 bit thnh s thc STL BTI TON HNG IN I,Q,M,L,D (WORD) OUT I,Q,M,L,D (INT) IN I,Q,M,L,D (DWORD) OUT I,Q,M,L,D (INT) IN I,Q,M,L,D (INT) OUT I,Q,M,L,D (WORD) IN I,Q,M,L,D (DINT) OUT I,Q,M,L,D (DWORD) IN I.Q,L.M.D (INT) OUT I,Q,M,L,D (DINT) IN I,QM,L,D (DINT) OUT I,Q,M,L,D (REAL) M T Lnh chuyn s BCD trong IN thnh s nguyn 16 bit ct trong OUT. Lnh chuyn s BCD trong IN thnh s nguyn 32 bit ct trong OUT. Lnh chuyn s nguyn 16 bit trong IN thnh s BCD ct trong OUT. Lnh chuyn s nguyn 32 bit trong IN thnh s BCD ct trong OUT. Lnh chuyn s nguyn 16 bit trong IN thnh s nguyn 32 bit trong OUT. Lnh chuyn s nguyn 32 bit trongIN thnh s thc ct trong OUT.

BTD

ITB

DTB

ITD

DTR

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 4.9 Nhm lnh kt thc chng trnh 4.9.1 Lnh kt thc khng iu kin C php BEU

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Lnh khng c ton hng v thc hin vic kt thc chng trnh trong khi mt cch v iu kin. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 0 1 0 4.9.2 Lnh kt thc c iu kin C php BEC Lnh khng c ton hng v thc hin vic kt thc chng trnh trong khi nu nh RLO c gi tr 1. Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC x 0 1 1 0 4.10 Nhm lnh r nhnh theo bit trng thi Lnh r nhnh theo bit trng thi l loi lnh thc hin bc nhy nhm b qua 1 on chng trnh ti on chng trnh khc c nh du bng nhn nu iu kin kim tra trong thanh ghi trng thi c tho mn. Ni lnh nhy ti phi cng 1 khi. Khng th nhy t khi ny sang khi khc. 4.10.1 Lnh r nhnh khi BR = 1 C php JBI <nhn> Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0 4.10.2 Lnh r nhnh khi BR = 0 C php JNBI <nhn> Lnh tc ng vo thanh ghi trng thi nh sau: BR CC1 CC0 OV OS OR STA RLO FC 0 1 0 4.10.3 Lnh r nhnh khi RLO = 1 C php JC <nhn> Lnh tc ng vo thanh ghi trng thi nh sau: Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 BR CC1 CC0 OV OS OR STA RLO FC 0 1 1 0 4.10.4 Lnh r nhnh khi RLO = 0 C php JCN<nhn> BR CC1 CC0 OV OS OR STA RLO FC 0 1 1 0 4.11 B nh thi (Timer) 4.11.1 Nguyn tc lm vic Lnh tc ng vo thanh ghi trng thi nh sau:

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B thi gian Timer l b to thi gian tr T mong mun gia tn hiu logic ng vo v tn hiu logic ng ra. S7 300 c 5 loi timer khc nhau. Tt c 5 loi Timer ny cng bt u to thi gian tr tn hiu k t thi im kch ca tn hiu u vo, tc l khi tn hiu u vo chuyn trng thi, c gi l thi im timer c kch. Thi gian tr T mong mun c khai bo vi timer bng mt gi tr 16 bit bao gm 2 thnh phn: - phn gii: timer ca S7 300 c 4 ch phn gii: 10ms, 100ms, 1s v 10s. - Mt s nguyn BCD trong khong 0 999 c gi l PV (reset value _ gi tr t trc). Thi gian tr T mong mun s c tnh: T = phn gii *PV. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Khng s dng phn gii 0 0 1 1 0 1 0 1 10ms 100ms 1s 10s

Gi tr PV di dng s BCD 0 PV 99

Bit 14, 15 khng s dng. Bit 13, 12 dng t phn gii: Bit 0 n bit 11 l gi tr PV di dng BCD (0< PV < 999). Ngay ti thi im kch timer, gi tr PV c chuyn vo thanh ghi 16 bit ca T-word (gi l thanh ghi CV, vit tt current value, gi tr tc thi). Timer s ghi nh khong thi gian tri qua k t khi c kch bng cch gim dn mt cch tng ng ni Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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dung thanh ghi CV. Nu ni dung thanh ghi tr v bng 0 th timer t c thi gian tr mong mun T v iu ny s c bo ra ngoi bng cch i trng thi tn hiu ng ra. CPU 314 c 128 timer c nh s t 0 n 127. Mt timer c t tn l Tx, trong x l s hiu ca timer (0 x 127). K hiu Tx cng ng thi l a ch hnh thc ca thanh ghi CV (T- word) v ca u ra T-bit ca timer . Tuy chng c cng a ch hnh thc, song T-word v T-bit vn c phn bit vi nhau nh kiu lnh s dng vi ton hng Tx .Khi dng lnh lm vic vi t, Tx c hiu l a ch ca Tword, ngc li khi s dng lnh lm vic vi tip im Tx s c hiu l a ch ca T-bit. Mt timer ang trong ch lm vic (sau khi c kch) c th c a v ch ch khi ng ban u, tc l ch sn ln ca tn hiu u vo. Cng vic ny gi l reset timer. Tn hiu reset timer c gi l tn hiu xo v khi tn hiu xo c gi tr bng 1 timer s khng lm vic. Ti thi im xut hin sn ln ca tn hiu xo, Tword v T-bit c xo v 0, tc l thanh ghi CV c t v 0 v tn hiu u ra c trng thi 0. 4.11.2 Khai bo s dng Vic khai bo s dng timer gm c 5 bc: Khai bo tn hiu enable nu mun s dng tn hiu ch ng kch. Khai bo tn hiu u vo. Khai bo tn hiu tr mong mun. Khai bo loi timer c s dng. Khai bo tn hiu xo timer nu mun. Khai bo tn hiu enable C php A FR <a ch bit> <Tn timer>

Ton hng th nht a ch bit xc nh tn hiu s c s dng lm tn hiu ch ng kch cho timer c tn trong ton hng th hai. Khai bo tn hiu u vo: C php A <a ch bit> a ch bit trong ton hng xc nh tn hiu u vo cho timer. V d: A I2.0 FR T1 A I2.1 Khai bo thi gian tr mong nun: C php L <hng s> Hng s trong ton hng xc nh thi gian tr T t trc cho timer. Hng s ny c hai dng: Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 S5T#h_m_s_ms: y l dng d liu thi gian trc tip. V d: thi gian tr l 5 pht 20 giy. L S5T#00H05M20S00MS. Dng khai bo theo phn gii: L W#16#2127 // Thi gian tr l 127 giy. Khai bo loi timer: S7-300 c 5 loi timer c khai bo theo cc lnh: SD: Timer ng mch chm C php SD <Tn timer>

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Thi gian gi tr c bt u tnh t khi c sn ln ca tn hiu u vo (hoc khi c sn ln ca tn hiu enable ng thi tn hiu vo bng 1), tc l ngay thi im gi tr PV (gi tr t trc) c chuyn vo thanh ghi T-word (CVgi tr tc thi). Trong khong thi gian tr T-bit c gi tr 0. Khi ht thi gian tr, T-bit c gi tr bng 1. Nh vy T-bit c gi tr 1 khi T-word = 0 hay CV = 0. Khong thi gian tr chnh l khong thi gian gia thi im xut hin sn ln ca tn hiu u vo v sn ln ca T-bit. Khi tn hiu vo bng 0, T-bit v T-word cng nhn gi tr 0. SS: Timer ng mch chm c nh SS <tn timer> C php :

Thi gian gi tr c bt u tnh t khi c sn ln ca tn hiu u vo (hoc khi c sn ln ca tn hiu enable ng thi tn hiu vo bng 1), tc l ngay thi im gi tr PV (gi tr t trc) c chuyn vo thanh ghi T-word (CVgi tr tc thi). Trong khong thi gian tr T-bit c gi tr 0. Khi ht thi gian tr, tc l khi T-word = 0, T-bit c gi tr bng 1. Khong thi gian tr chnh l khong thi gian gia thi im xut hin sn ln ca tn hiu u vo v sn ln ca T-bit. Vi b timer tr theo sn ln c nh, thi gian tr vn c tnh cho d lc tn hiu u vo v 0. SP: Timer Xung SP <tn timer> C php

Thi gian gi tr c bt u tnh t khi c sn ln ca tn hiu u vo (hoc khi c sn ln ca tn hiu enable ng thi tn hiu vo bng 1), tc l ngay thi im gi tr PV (gi tr t trc) c chuyn vo thanh ghi T-word (CVgi tr tc thi). Trong khong thi gian tr ,tc l khi T-word c gi tr 0, T-bit c gi tr bng 1. Ngoi thi gian tr T-bit c gi tr bng 0. Nu cha ht thi gian tr m tn hiu u vo v 0 th gi tr T-bit v t-word cng v 0. SE: Timer gi rng xung

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 C php SE <Tn timer>

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Thi gian gi tr c bt u tnh t khi c sn ln ca tn hiu u vo (hoc khi c sn ln ca tn hiu enable ng thi tn hiu vo bng 1), tc l ngay thi im gi tr PV (gi tr t trc) c chuyn vo thanh ghi T-word (CVgi tr tc thi). Trong khong thi gian tr, tc l khi T-word c gi tr 0, T-bit c gi tr bng 1. Ngoi thi gian tr T-bit c gi tr bng 0. Nu cha ht thi gian tr m tn hiu u vo v 0 th thi gian tr vn c tnh tip tc, tc l T-bit v T-word khng v 0 theo tn hiu u vo. SF: Timer m mch chm SF <Tn timer> C php

Thi gian gi tr c bt u tnh t khi c sn ln ca tn hiu u vo (hoc khi c sn ln ca tn hiu enable ng thi tn hiu vo bng 1), tc l ngay thi im gi tr PV (gi tr t trc) c chuyn vo thanh ghi T-word (CVgi tr tc thi). Trong khong thi gian tr, tc l khi T-word c gi tr 0, T-bit c gi tr bng 1. Ngoi thi gian tr T-bit c gi tr bng 0. Khai bo tn hiu xa (reset) C php A <a ch bit> R <Tn timer> Ton hng th nht a ch bit xc nh tn hiu s c s dng lm tn hiu ch ng xa cho timer c tn trong ton hng th hai. Khi tn hiu xa bng 1, T-word (thanh ghi CV) v T-bit cng ng thi c a v 0. Nu tn hiu xa bng 0, timer s ch c kch li. Timer ng mch chm (SD) biu din trong LAD v FBD LAD FBD

Bng 4.1: Bng khai bo thng s timer. Thng s X ( S hiu ca timer,tu loi CPU) S (ng vo khi ng) TV (Gi tr t trc:t 0 n 999) R (Ng vo reset) Q (Ng ra) BI (Gi tr hin hnh timer dng integer) BCD (Gi tr hin hnh timer dng BCD) Chng 4: Tp lnh ca PLC S7-300 Kiu d liu TIMER BOOL S5TIME BOOL BOOL WORD WORD Ton hng I,Q,L,M,D I,Q,M,L,D I,Q,M,L,D I,Q,M,L,D I,Q,M,L,D I,Q,M,L,D I,Q,M,L,D

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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RLO at S RLO at R Thi gian chy Ng ra Q Hnh 4.1: Biu chc nng timer SD. Khi ng: Timer khi ng khi RLO ti ng vo S thay i t 0 ln 1. Timer bt u chy vi gi tr thi gian r rng t ti ng vo TV min l trng thi ng vo S =1. Xo: Khi RLO reset ng vo R l 1, th gi tr thi gian hin hnh v phn gii b xo v ng ra Q trng thi Reset. Ng ra digital: Gi tr thi gian hin hnh c th c nh mt s nh phn ti ng ra BI v BCD. Gi tr thi gian hin hnh l gi tr ban u ca TV tr i gi tr thi gian hot ng ca timer, tnh t khi timer c khi ng. Ng ra Binary: Tn hiu ti ng ra Q l 1, sau khi timer chy ht, khng c li v ng vo S c tn hiu trng thi 1. Khi timer ang hot ng, nu tn hiu ng vo S thay i t 1 xung 0, th timer ngng hot ng. Trong trng hp ny ng ra Q c trng thi tn hiu 0. Timer ng mch chm c nh (SS) biu din trong LAD v FBD LAD FBD

Vi cc thng s, kiu d liu v ton hng khai bo ging nh dang LAD v FBD ca timer ng mch chm (SD).

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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RLO at S RLO at R Thi gian chy Ng ra Q Hnh 4.2: Biu chc nng Timer SS. Khi ng: Timer khi ng khi RLO ng vo S thay t 0 n 1. Timer bt u hot ng vi gi tr thi gian xc nh r rng ti ng vo TV v tip tc hot ng thm ch nu tn hiu ng vo S thay i thnh 0 trong sut thi gian . Nu tn hiu ti ng vo S thay i t 0 n 1 trong khi timer ang hot ng, th timer s khi ng mi li. Reset: Khi RLO ti ng vo R l 1 th gi tr thi gian hin hnh v phn gii b xo v ng ra Q trng thi Reset. Ng ra nh phn: Trng thi tn hiu ng ra Q l 1 sau khi timer hot ng khng b li, th khng cn ch n trng thi tn hiu ng vo S l 1 hay 0. Timer m mch chm (OFF Delay, SF) biu din trong Lad v FBD LAD FBD

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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RlO at S RLO at R Thi gian chy Ng ra Q

Hnh 4.3: Biu chc nng timer SF. Khi ng: Timer khi ng khi RLO ng vo S thay i t 1 n 0. Sau khi timer hot ng xong, th ng ra Q s chuyn i v 0. Nu trng thi tn hiu ng vo S thay i t 0 n 1 trong khi timer ang hot ng, th timer s dng v thi gian k tip trng thi tn hiu ca S thay i t 1 thnh 0 n s bt u li t u. Reset : Khi RLO ng vo R l 1 th gi tr thi gian hin hnh v phn gii b xo v ng ra Q b reset. Nu c hai ng vo (S v R ) c cng trng thi tn hiu 1, th ng ra Q khng c set cho n khi ng reset tr v 0. Ng ra nh phn: Ng ra Q c kch hot khi RLO ti ng vo S thay i t 0 dn 1. Nu ng vo S khng c kch hot th ng ra Q vn c trng thi tn hiu 1 cho n khi thi gian lp trnh c hon thnh. Timer Xung (Pulse, SP) biu din trong LAD v FBD LAD FBD

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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RLO at S RlO at R Thi gian chy Ng ra Q Hnh 4.4: Biu chc nng Timer SP. Khi ng: Timer khi ng khi RLO ti ng vo S thay i t 0 n 1. Ng ra Q cng t thnh 1. Reset: Ng ra Q b reset khi: Timer hot ng xong, hoc Tn hiu start chuyn i t 1 n 0, hoc Ng vo reset R c trng thi tn hiu 1. Timer gi rng xung (SE) biu din trong Lad v FBD LAD FBD

RLO at S RLO at R Thi gian chy Ng ra Q Hnh 4.5: Biu chc nng timer SE. Khi ng : Timer hot ng khi RLO ti ng vo S thay i t 0 n 1. Ng ra Q cng c set thnh 1. Trng thi tn hiu ng ra Q cng vn l 1, mc d tn hiu ng Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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vo S thay i thnh 0. Nu tn hiu ng vo start li thay i t 0 n 1 trong khi timer ang hot ng, th timer s khi ng li. Reset: Ng ra Q b reset khi: Timer hot ng xong, hoc Ng vo reset R c trng thi tn hiu 1. 4.11.3 Timer hot ng theo lnh bit V d: -Dng LAD: Network 1: -Dng FBD: Network 1:

Network 2: Network 2:

Network 3:

Network 3:

-Dng STL: Network 1: A I0.0 L S5T#5S SD T4 Netwok 2: A T4 = Q8.0 Network 3: A I0.1 R T4 Timer T4 s c kch nu I0.0 ln mc 1. Sau 5s, T4 ng lm Q8.0 ln mc 1. Timer c reset nu I0.1 ln mc 1. Cu lnh bit: tt c nhng chc nng timer cng c th c khi ng vi nhng lnh bit n gin. S ging nhau v khc nhau gia phng php v nhng chc nng timer c a ra nh sau: S ging nhau: iu kin khi ng ng vo S. Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 t trc gi tr thi gian. iu kin reset ng vo R . p ng tn hiu ti ng ra Q. S khc nhau (trong LAD v FBD) Khng c kh nng kim tra gi tr hin hnh, khng c ng ra BI v BCD. 4.12 B m(counter) 4.12.1 Nguyn tc lm vic:

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Counter l b m thc hin chc nng m sn xung ca cc tn hiu u vo. S7300 c ti a 256 counter (tu loi CPU), k hiu bi Cx, trong x l s nguyn trong khong t 0 n 255. Nhng b m ca S7-300 u c th ng thi m tin theo sn ln ca mt tn hiu vo th nht, c k hiu l CU (count up) v m tin theo sn ln ca tn hiu vo th hai, k hiu CD (count down). Thng thng b m ch cc sn ln ca tn hiu CU v CD, song cng c th c m rng m c mc tn hiu ca chng bng cch s dng thm tn hiu enable. Nu c tn hiu enable, b m s m tin khi xut hin sn ln ca tn hiu enable ng thi ti thi im CU c mc tn hiu 1. Tng t b m s m li khi c sn ln ca tn hiu enable v ti thi im CD c mc tn hiu 1. S sn xung m c, c ghi vo thanh ghi 2 byte ca b m, gi l thanh ghi C word. Ni dung ca C-Word c gi l gi tr m tc thi ca b m v k hiu bng CV (current value). B m bo trng thi ca C-Word ra ngoi thng qua chn C-bit ca n. Nu CV 0, C-Bit c gi tr 1. Ngc li khi CV = 0 C-bit nhn gi tr 0. CV lun l 1 gi tr khng m. B m s khng m li khi CV = 0. Khc vi timer, gi tr t trc PV ca b m ch c chuyn vo C-Word ti thi im xut hin sn ln ca tn hiu t (set S). B m c th c xo ch ng bng tn hiu xa (reset). Khi b m c xa, c C-Word v C-bit u nhn gi tr 0. 4.12.2 Cc thng s cn khai bo s dng trong STL Khai bo tn hiu enable nu mun s dng tn hiu ch ng kch m. Khai bo tn hiu u vo CU c m ln. Khai bo tn hiu u vo CD c m xung. Khai bo tn hiu t set v gi tr t trc PV. Khai bo tn hiu xa reset. <a ch bit>

Khai bo tn hiu enable: C php A FR <Tn timer> Ton hng th nht a ch bit" xc nh tn hiu s c s dng lm tn hiu kch m cho b m c tn trong ton hng th hai. Tn ca b m c dng Cx vi 0 x 255.

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Khai bo tn hiu u vo CU: C php A <a ch bit> CU <tn counter>

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Ton hng th nht a ch bit xc nh tn hiu m sn ln ca n c b m vi tn cho trong ton hng th hai m tin. Mi khi xut hin mt sn ln ca tn hiu, b m s tng ni dung thanh ghi Cword (CV) ln 1 n v. Khai bo tn hiu u vo CD: C php A <a ch bit> CD <tn counter> Ton hng th nht a ch bit xc nh tn hiu m sn ln ca n c b m vi tn cho trong ton hng th hai m li. Mi khi xut hin mt sn ln ca tn hiu, b m s gim ni dung thanh ghi Cword(CV) xung 1 n v. Khai bo tn hiu t SET: C php A L S <a ch bit> C#<hng s> <hng s>

Ton hng th nht a ch bit xc nh tn hiu m mi khi xut hin sn ln ca n, hng s cho trong lnh th hai di dng BCD s c chuyn vo thanh ghi Cword ca b m c tn trong ton hng th 3. Khai bo tn hiu t RESET: C php A <a ch bit> R <Tn counter> Ton hng th nht a ch bit xc nh tn hiu m mi khi xut hin sn ln ca n. Thanh ghi C-word ca b m c tn trong ton hng th hai s c xa v 0. 4.12.3 B m ln: LAD FBD

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 Bng 4.2: Bng khai bo thng s counter. Thng s x (S hiu ca counter, ty vo loi CPU) CU (Ng vo b m ln) S (Ng vo t gi tr m) PV (Gi tr t trc: t 0 n 999) R (Ng vo Reset) Q (Ng ra, trng thi ca counter) CV (Gi tr hin hnh counter dng integer) CV_BCD (Gi tr hin hnh counter dng BCD) Kiu d liu TIMER BOOL BOOL WORD BOOL BOOL WORD WORD

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Ton hng T I,Q,M,L,D I,Q,M,L,D,T,C I,Q,M,L,D,CONST I,Q,M,L,D,T,C I,Q,M,L,D I,Q,M,L,D I,Q,M,L,D

m ln: Khi RLO ti ng vo CU thay i t 0 n 1 gi tr m hin hnh tng ln 1. ( ti a = 999). Set b m: Khi RLO ti ng vo S thay i t 0 ln 1 b m c t vi gi tr ti ng vo PV. Reset b m: Khi RLO =1 counter c t v 0. Khi iu kin reset c tho mn th counter khng th t v khng th m. PV: Gi tr t trc t (0 ..999) c xc nh ti ng vo PV dng BCD. PV l hng s m (C#...). Qua giao tip d liu trong dng BCD. CV/CV-BCD: Gi tr counter c th l mt s nh phn hoc s BCD c np vo tch lu v t chuyn ti cc a ch khc. Q: Tnh trng tn hiu ca counter c th kim tra ti ng ra Q. Gi tr m bng 0 suy ra Q = 0. Gi tr m khc 0 suy ra Q = 1. 4.12.4 B m xung: LAD FBD

m xung: Khi RlO ti ng vo CD thay i t 0 ln 1 gi tr m hin hnh gim xung 1( ti thiu bng 0). Set b m: Khi RLO ti ng vo S thay i t 0 ln 1 b m c t vi gi tr ti ng vo CV. Reset b m: Khi RLO =1 counter c t v 0. Khi iu kin reset c tho mn th counter khng th t v khng th m. PV: Gi tr t trc t (0 ..999) c xc nh ti ng vo PV dng BCD. Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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CV/CV-BCD: Gi tr counter c th l mt s nh phn hoc s BCD c np vo tch lu v t chuyn ti cc a ch khc. Q Tnh trng tn hiu ca counter c th kim tra ti ng ra Q Gi tr m bng 0 suy ra Q = 0. Gi tr m khc 0 suy ra Q = 1. 4.12.5 B m ln-xung LAD FBD

Gi tr m: Mi mt b m chim mt word 16 bit trong vng nh d liu h thng, dng lu tr gi tr m cho counter t (0..999) trong m nh phn. m ln: Khi RLO ti ng vo CU thay i t 0 n 1 gi tr m hin hnh tng ln 1. ( ti a = 999). m xung: Khi RLO ti ng vo CD thay i t 0 ln 1 gi tr m hin hnh gim xung 1( ti thiu bng 0). Set b m: Khi RLO ti ng vo S thay i t 0 ln 1 b m c t vi gi tr ti ng vo CV. Reset b m: Khi RLO =1 counter c t v 0. Khi iu kin reset c tho mn th counter khng th t v khng th m. PV: Gi tr t trc t (0 ..999) c xc nh ti ng vo PV dng BCD. Gi tr t vo PV l hng s m (C#...). Qua giao tip d liu trong dng BCD. CV/CV-BCD: Gi tr counter c th l mt s nh phn hoc s BCD c np vo tch lu v t chuyn ti cc a ch khc. Ng a Q : Tnh trng tn hiu ca counter c th kim tra ti ng ra Q. Gi tr m bng 0 suy ra Q = 0. Gi tr m khc 0 suy ra Q = 1. Cc loi b m: S_CU B m ln ( ch m ln). S_CD B m xung (ch m xung). S_CUD B m ln /m xung.

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300

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CU CD S R Counter

Hnh 4.6: Biu chc nng Counter. 4.12.6 B m cu lnh bit - Dng LAD

Chng 4: Tp lnh ca PLC S7-300

Vit chng trnh iu khin v m phng h thng dng PLC S7-300 - Dng FBD:

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- Dng STL:

Cu lnh bit: Tt c nhng chc nng ca counter cng c th hot ng vi nhng cu lnh bit n gin. S ging nhau v khc nhau gia phng php ny v nhng chc nng c counter a ra nh sau: Ging nhau: - iu kin set ng vo SC. - Gi tr t trc ca b m. - RlO thay i ng vo CU. - RLO thay i ng vo CD. Khc nhau: - Khng c kh nng kim tra gi tr m hin hnh. - Ng ra nh phn Q khng th hin c bng biu .

Chng 4: Tp lnh ca PLC S7-300

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