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  • Chapter 8 Counters

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    Sao Sovannarith
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    Registers are used to store binary data, while counters store the number of clock pulses. There are two main types of counters: asynchronous counters where flip-flops change state independently in response to previous operations rather than a clock, and synchronous counters where all flip-flops change simultaneously in sync with a master clock, allowing for higher speeds. Common registers include buffer, shift, serial-in serial-out, serial-in parallel-out, and parallel-in serial-out.

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    Registers are used to store binary data, while counters store the number of clock pulses. There are two main types of counters: asynchronous counters where flip-flops change state independently in response to previous operations rather than a clock, and synchronous counters where all flip-flops change simultaneously in sync with a master clock, allowing for higher speeds. Common registers include buffer, shift, serial-in serial-out, serial-in parallel-out, and parallel-in serial-out.

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    Attribution Non-Commercial (BY-NC)
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    28 views21 pages

    Chapter 8 Counters

    Uploaded by

    Sao Sovannarith
    Registers are used to store binary data, while counters store the number of clock pulses. There are two main types of counters: asynchronous counters where flip-flops change state independently in response to previous operations rather than a clock, and synchronous counters where all flip-flops change simultaneously in sync with a master clock, allowing for higher speeds. Common registers include buffer, shift, serial-in serial-out, serial-in parallel-out, and parallel-in serial-out.

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    of 21

    REGISTER COUNTERS

    Overview
    IntroductiontoRegister
    BufferRegister ShiftRegister

    IntroductiontoCounter
    AsynchronousCounter SynchronousCounter

    IntroductiontoRegister
    Aregisterisagroupofflipflopsormemory elementsthatworktogethertostoreandshift agroupofbitsorabinaryword. Themostbasictypeofregisteriscalledthe bufferregister,anditsfunctionissimplyto storeabinaryword. Theotherregisters,suchastheshiftregister, modifythestoredwordbyshiftingthestored bitstotheleftortotheright
    3

    BufferRegister
    Thebufferregistersimplystoresadigitalword
    CLK 1D Input 2D 3D 4D Q1 Q2 output Q3 Q4
    4

    ShiftRegister
    Shiftregisterisastorageregisterthatwill moveorshiftthebitsofthestoredword eithertotheleftortotheright Thethreebasictypesofshiftregistersare:
    Serialin,serialout(SISO)shiftregisters Serialin,parallelout(SIPO)shiftregisters Parallelin,serialout(PISO)shiftregisters

    ShiftRegister
    RotateRight ShiftRight Paralleldata bitsin ShiftLeft Paralleldata bitsout Paralleldata bitsin Paralleldata bitsout RotateLeft

    Paralleldata bitsin Paralleldata bitsout Paralleldatabitsout


    6

    Paralleldatabitsin

    SerialIn,SerialOut(SISO)Shift Registers

    SISOShiftRight

    SISOShiftLeft RotateRight RotateLeft

    SerialIn,Parallelout(SIPO)Shift Registers
    SerialData input

    Clock input

    Q0

    Q1

    Q2

    Q3

    ParallelDataOutput

    ParallelIn,SerialOut(PISO)Shift Registers
    Shift/Loadcontrol 1=shift,0=load D0 D1 D2 D3

    Clockinput

    ThreeStateOutputRegisters

    10

    IntroductiontoCounter
    Acounterislikearegisterinthatitisasequential logiccircuitmadeupofseveralflipflop. Aregister,however,isdesignedtostoreabinary word,whereasthebinarywordstoredina counterrepresentsthenumberofclockpulse thathaveoccurredattheclockinput. Theinputclockpulse,therefore,causetheflip flopsofthecountertochangestate,andby monitoringtheoutputsoftheflipflops.
    11

    AsynchronousCounters
    Asmentionedintheintroduction,mostofthe flipflopsinanasynchronouscounterarenot connectedtotheclocksignal,andthereforethe flipflopsdonotchangestateinsyncwiththe masterclocksignal Asynchronouscounterisacounterinwhichan actionstartsinresponsetoasignalgeneratedto asignalgeneratedbyapreviousoperation,rather thaninresponsetoamasterclocksignal.
    12

    AsynchronousBinaryUpCounters
    +5V Q0 Q1 Q2 Q3 CLK
    Q3 0 0 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

    CLK Q0 Q1 Q2 Q3

    0 0 0 0 0 0 1 1 1 1 1 1 1 1

    13

    AsynchronousBinaryUpCounters
    Themaximumcount(N)ofacounter N=2n 1 N=maximumcountbeforecyclerepeats N=numberofflipflopinthecountercircuit TheModulus(MOD)ofacounter MOD=2n MOD=Modulusofthecounter n=numberofflipflopinthecounter Thepropagationdelaytime(tp)ofacounter f=(1x109)/(nxtp) f=upperclockpulefrequencylimit n=numberofflipflopsinthecountercircuit tp=propagationdelaytimeofeachflipflopin nanoseconds

    Thefrequencydivisionofacounter DivisionFactor=2n n=numberofflipflopinthecountercircuit

    14

    AsynchronousBinaryDownCounters
    +5V CLK

    Q0

    Q1
    Q3 1 1 1 1 1

    Q2
    Q2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Q1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

    Q3
    Decimal 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

    CLK Q0 Q1 Q2 Q3

    1 1 1 0 0 0 0 0 0 0 0

    15

    AsynchronousBinaryUp/Down Counters
    Q0 +5V CLK UP/ Down Q1 Q2 Q3

    16

    AsynchronousDecade(MOD10) Counter
    +5V

    CLK

    Q0

    Q1

    Q2

    Q3

    17

    AsynchronousPresettable Counter
    D0 D1 D2 D3

    +5V

    CLK

    Q0

    Q1

    Q2

    Q3

    Mp=MODD Mp=naturalmodulusofthecounter D=presetdatavalue

    18

    SynchronousCounters
    Asmentionedpreviously,asynchronouscountersareoften referredtoasripplecounters.Thetermrippleisused becausetheflipflopmakinguptheasynchronouscounter arestrungtogetherwiththeoutputofoneflipflopdriving theinputofthenext.Asaresult,theflipflopdonot changestatesimultaneouslyorinsyncwiththeinputclock pulses,sincethenewcounthastoripplethroughand updatealloftheflipflops.Thisripplethroughactionleads topropagationdelaytimesthatlimitthecounterscounting speed.Thislimitationcanbeovercomewithasynchronous counterinwhichalloftheflipflopswithinthecounterare triggeredsimultaneouslyandthereforesynchronizedtothe mastertimingclocksignal.

    19

    SynchronousBinaryUpCounters
    Q0 Q1 Q2 Q3

    +5V

    CLK

    20

    SynchronousCounterAdvantages
    Asynchronouscountercircuitissimple Asynchronouscounterisitsfrequencyof operationspeedlimitation Synchronouscounterissmallpropagation delaytime Synchronouscountercircuitiscomplex
    tp=singleflipfloptp +singleANDgatetp

    21

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